RC64474™ RC64475™ RISControllerTM Embedded 64-bit
Contents
1. JEDEC VARIATION B MN NOM A 10 5 5 520 340 560 iii Cocoon D 30 60 856 4 ne 01 28 00 BSC 5 2 30 60 BSC n E El 28 00 856 52 H 21 00 REF e 50 BSC a 2 7 s 20 23 P Pl E 2 ddd 08 E E OTES 1 DIMENSIONING AND TOLERANCING CONFORM TO ASME Y14 5M 1994 ES ES LN PACKAGE MAY BE SMALLER THAN BOTTOM PACKAGE BY 15 mm E E 2 Ti ZX DIMENSIONS D AND E ARE TO BE DETERMINED AT SEATING PLANE C DIMENSIONS D1 AND 1 DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE 4 7 MOLD PROTRUSION IS 25 mm PER SIDE 01 AND E1 ARE BODY SIZE a DIMENSIONS INCLUDING MOLD MISMATCH MN MAX OF PIN 1 IDENTIFIER IS OPTIONAL BUT MUST BE LOCATED WITHIN P 3120 3140 THE ZONE INDICATED ZX DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR SW Hoi PROTRUSION IS 08 mm IN EXCESS OF THE b DIMENSION AT MAXIMUM x 40 MATERIAL CONDITION DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS e 50 BSC OR THE FOOT N 208 EXACT SHAPE OF EACH CORNER IS OPTIONAL rac M Integrated Devise Technology Ine THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN eo e 2975 Stender Way Santa Ch 86564 AND 25 mm FROM THE LEAD En2. ROB MIN AX 251 20 CTAB 8 N 4 40 SEE DETAIL X sap H re K 11 40 IIl Jil 20 MIN iii SEATING PLANE R 08 25 GAGE PLANE J 27 SBTC aa A 1 30 REF b ddd G1 CJA BODS DET AIL B FO RE with PLATING TOLERANCES tax DECIMAL ANGULAR 2875 Stender Way Santa Clara CA 95054 09 20 09 16 xxi PHONE 408 727 6116 A FAX 408 492 8674 810 338 2070 1 APPROVALS DATE TILE DP PACKAGE OUTLINE b DRAIN TUR 2 28 0 X 28 0 X 54 mm 1 30 25 MIN FORM SECTION SIZE DRAWING No REV C PSC 4069 00 DD NOT SCALE DRAWING SHEET 1 0F 2 20 of 25 April 10 2001 RC64474 RC64475 RC64475 208 pin Package page 2 REVISIONS DCN REV DESCRIPTION DATE APPROVED 61478 00 INITIAL RELEASE 08 20 98 LAND PATTERN DIMENSIONS
3. RC64474 RC6447 RC64474 128 Pin Package Page 1 of 3 RC64474 RC6447 RC64474 128 pin Package page 2 of 3 40 c 133HS 31 25 LON OG 00 AJA 0 07 925 ONIMVAD 375 303 560 091 9309 WU pg X 085 X 082 JNIuno 79 suu 2 1 02 80 aya SWAOQUddY 02 8 lt lt 016 XML 298 26 80 318 222 20 9056 VO 0490 pjung ADM JapueiS 5 60 ou So ouqoo pojergojup TXXXX FXXX F FXX YVINONY TIYADI 031512345 6631 532 43101 96 02 60 35 3134 00 11919 4 alya 01 9149534 SNOISLAdA V V NOILOAS 1558 411 19 ONUVId HIM b REF 4 11 23 E 3979 08 8 19130 Ge NIN 3 l 19130 0 Y0 8 400 5305 4 5305 0V31 April 10 2001 23 of 25 10 2001 lt lt
4. E 24 0125 30 13365 31 25 LON OG 00 0 07 205 ON SNIMY HU 325 1 90 i404 607 097 c0 SW 5034 S6 23037 OL SNYOANOO JNITLNO SIH 9304 x 092 X 092 8 02 60 40 39vMOvd ZO SALIANTA JAY SNOISN3HIO TIY 0 02 865 016 XML 298 26 xw4 3119 227 gor NOHA FP FXX dil JHL Sc 0 73096 YO unio BJuBG APM 291946 GLEE SN es IME G31 40 NOUO3S 13 OL Alddv SNOISN3MIQ 3S3H So ouqae dadas ser Nr SI M3NH02 40 34945 10X3 Bel N 004 3HL X0 258 08 Snldva JHL NO 31201 38 LONNYO 02 09 Or X WOWIXVA 1Y NOISNSNIG 9 3HL 40 55303 NI go 51 NOISNYLOYd ASE 877 74 NOISNYLOMd JONIONI LON 300 4 NOISNSNIG INOZ 3H bores Og Ig d 0319907 38 ISNAN 108 WNOILdO SI 3511301 d 30 3 NI HOIVASIA TION INIJAT NI SNOISN3 a 325 008 387 13 ONY LO GIS 34 WW S NOISNYLONd 010 4 um NOIShMlONd OTON LON OQ 13 Ld SNOISNINIG nmnmnomm
5. Pin Function Pin Function Pin Function Pin Function 34 SysCmd3 86 Voc 138 SysAD25 190 SysADC5 35 Vss 87 SysAD17 139 SysAD57 191 SysADC1 36 Voc 88 SysAD49 140 N C 192 Voc 37 SysAD38 89 IntO 141 Vss 193 Vss 38 SysAD6 90 SysAD18 142 N C 194 SysAD47 39 ModeClock 91 Vas 143 SysAD26 195 SysAD15 40 WrRdy 92 Voc 144 SysAD58 196 SysAD46 41 SysAD37 93 SysAD50 145 N C 197 Voc 42 SysAD5 94 Validin 146 Voc 198 43 Vss 95 SysAD19 147 Vss 199 SysAD14 44 Voc 96 SysAD51 148 SysAD27 200 SysAD45 45 N C 97 Vas 149 N C 201 SysAD13 46 N C 98 Voc 150 202 SysAD44 47 N C 99 ValidOut 151 N C 203 Vss 48 N C 100 SysAD20 152 N C 204 Voc 49 N C 101 N C 153 N C 205 SysAD12 50 N C 102 N C 154 N C 206 SysCmdP 51 N C 103 N C 155 N C 207 SysAD43 52 N C 104 N C 156 N C 208 N C Table 6 RC64475 208 pin QFP Package Pin Out Page 2 of 2 RC64474 128 Package Pin out Pin Function Pin Function Pin Function Pin Function 1 JTAG32 33 Voc 65 Voc 97 Vcc 2 SysCmd2 34 Vss 66 SysAD28 98 Vss 3 Vcc 35 SysAD13 67 ColdReset 99 SysAD19 4 Vss 36 SysAD14 68 SysAD27 100 Validin 5 SysAD5 37 Vss 69 Vss 101 Vcc 6 WrRdy 38 Vcc 70 Vcc 102 Vss 7 ModeClock 39 SysAD15 71 JR Vcc 103 SysAD18 8 SysAD6 40 Vss 72 SysAD26 104 IntO 9 Vcc 41 Vcc T3 N C 105 SysAD17 10 Vss 42 SysADC1 74 Vss 106 Vcc 11 SysCmd3 43 Vss 75 N C 107 Vss 12 SysAd7 44 Vcc 76 SysAD25 108 I
6. RISController Embedded RC64474 D 64 bit Microprocessor based RC64475 RISCore4000 RiSController Features Software compatible with entire RISController Series of High performance 64 bit microprocessor based on the Embedded Microprocessors RISCore4000 Industrial temperature range support Minimized branch and load delays through streamlined Active power management 5 stage scalar pipeline Powers down inactive units through sleep mode feature Single and double precision floating point unit 100 pin compatibility between RC64574 RC64474 and 22 100 compatibility between RC64575 RC64475 and Joint TLB on chip for virtual to physical address mapping RC4650 On chip two way set associative caches RC64474 available in 128 pin QFP package for 32 bit only 16KB instruction cache systems 16KB data cache D cache RC64475 available in 208 pin QFP package for full 64 32 bit Optional and D cache locking per set provides systems improved real time support Simplified board level testing through full Joint Test Action Enhanced flexible bus interface allows simple low cost Group JTAG boundary scan design Windows CE compliant 64 bit Bus Interface option 1000MB s bandwidth support 32 bit Bus Interface option 500MB s bandwidth support SDRAM timing protocol through delayed data in write cycles RC4000 RC5000 family bus protocol compatibility
7. Bus runs at fraction of pipeline clock 1 2 to 1 8 Implements MIPS III Instruction Set Architecture ISA 3 3V core with 3 3V I O Block diagram System Control 330 MIPS 64 bit Coprocessor 125 MFLOPS Single Double RISCore4000 Sea CPU Core FPA Control Bus A Data Bus Instruction Bus 16 Y 16KB Instruction Cache 32 64 bit Data Cache Lockable Synchronized Lockable System Interface The IDT logo is a trademark and RC32134 RC32364 RC64145 RC64474 RC64475 4650 RC4640 RC4600 RC4700 RC3081 RC3052 RC3051 RC3041 RISController and RISCore are trademarks of Inte grated Device Technology Inc 1 of 25 April 10 2001 2001 Integrated Device Technology Inc DSC 4952 RC64474 RC64475 Device Overview Extending Integrated Device Technology s IDT RISCore4000 based choices see Table 1 the RC64474 and RC64475 are high perfor mance 64 bit microprocessors targeted towards applications that require high bandwidth real time response and rapid data processing and are ideal for products ranging from internetworking equipment switches routers to multimedia systems such as web browsers set top boxes video games and Windows CE based products These processors are rated at 330 Dhrystone MIPS and 125 Million floating point operations per second at 250 MHz The inter
8. JTAG Interface TDI JTAG Data In On the rising edge of TCK serial input data are shifted into either the Instruction register or Data register depending on the TAP controller state TDO JTAG Data Out On the falling edge of TCK the TDO is serial data shifted out from either the instruction or data register When no data is shifted out the TDO is tri stated high impedance TCK JTAG Clock Input An input test clock used to shift into or out of the boundary scan register cells TCK is independent of the system and pro cessor clock with nominal 40 60 duty cycle TMS JTAG Command Select The logic signal received at the TMS input is decoded by the TAP controller to control test operation TMS is sampled on the rising edge of TCK TRST JTAG Reset The TRST pin is an active low signal used for asynchronous reset of the debug unit independent of the processor logic During normal CPU operation the JTAG controller will be held in the reset mode asserting this active low pin When asserted low this pin will also tristate the TDO pin JTAG32 JTAG 32 bit scan This pin is used to control length of the scan chain for SYsAD 32 bit or 64 bit for the JTAG mode When set to Vss 32 bit bus mode is selected In this mode only SysAD 31 0 are part of the scan chain When set to Vcc 64 bit bus mode is selected In this mode SysAD 63 0 are part of the scan chain This pin has a built in pull down device to guarantee 32 bit
9. 2 5 2 2 ns MasterClock Fall Time tucEa 2 5 2 2 ns ModeClock Period IModeCKP 256 256 256 ns JTAG Clock Input trck 100 100 100 ns JTAG Clock HIGH 40 40 40 ns JTAG Clock Low trckLoW 40 40 40 ns Clock Rise Time tTCKRise 5 5 5 ns Clock Fall Time trckeai 5 5 5 ns Timings are measured from 1 5V of the cl ock to 1 5V of the signal 16 25 10 2001 RC64474 RC64475 Capacitive Load Deration RC64474 RC64475 Test 180MHz 200MHzt 250MHzt Parameter Symbol Conditi Units 5 Min Max Min Min Load Derate 2 2 2 ns 25pF System Interface Parameters Note Operation of the RC64474 RC64475 is only guaranteed with the Phase Lock Loop enabled 64474 RC64474 RC64474 64475 RC64475 RC64475 Parameter Symbol Test Conditions 480MHz 200MHz 250MHz Units Min Min Min DataOupu mode 4 10 05 6 0 5 0 47 noder 15 7 11 03 6 o 5 o m mode44 43 00 9 9 7 5 mode 13 01 9 9 7 ns Data Output Hold mode44 13510 03 03 03 ns mode44 13 11 03 03 0 ns modey4 43 00 03 03
10. Dri Ein d md Driven if D y y SysAD SysCmd Received SysADC te Ig Control Signal CPU driven ValidOut Release Control Signal CPU received RdRdy WrRdy ExtRqst Validln NMI Int 5 0 vs nz wa 5 188 active low signal Figure 3 System Clocks Data Setup Output and Hold Timing 15 of 25 April 10 2001 RC64474 RC64475 TDI TMS TDO Notes to diagram trekqoy t2 t3 troKFALL reset pulse width 5 trckRise TDO X tbo 25ns Figure 4 Standard JTAG timing AC Electrical Characteristics Commercial Temperature Range RC64474 RC64475 3 3 5 0xC to 85 C Clock Parameters RC64474 RC64475 RC64474 RC64475 RC64474 RC64475 Parameter Symbol Test 180MHz 200MHz 250MHz Units Conditions Min Max Min Max Min Max Pipeline clock 80 180 80 200 80 250 2 Frequency MasterClock HIGH Transition lt 3ns 3 3 2 5 ns MasterClock LOW tucLow Transition lt 3ns 3 3 2 5 ns MasterClock 10 90 10 100 10 125 2 Frequency MasterClock Period 11 1 100 10 100 8 100 ns Clock Jitter for 250 250 250 ps MasterClock MasterClock Rise Time tycrise
11. be left a N C Table 9 RC64575 Socket Compatibility to RC64475 amp RC4650 Absolute Maximum Ratings Note Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability RC64474 475 RC64474 475 50 50 Symbol Rating P IO dio ds Unit Commercial Industrial VrERM Terminal Voltage with respect to GND 0 51 to 44 6 0 51 to 44 6 V Tc Operating Temperature case 0 to 85 40 to 85 C Case Temperature Under Bias 55 to 125 55 to 125 C Storage Temperature 55 to 125 55 0 125 C lin DC Input Current 20 20 DC Output Current 503 503 K Vin minimum 2 0V for pulse width less than 15ns Viy should not exceed 0 5 Volts 2 When Viy lt OV or Viy gt Voc 3 Not more than one output should be shorted at a time Duration of the short should not exceed 30 seconds Recommended Operation Temperature and Supply Voltage RC64474 475 Grade Temperature Gnd Vcc Commercial 0 to 85 C Case 3 3 5 Industrial 40 85 Case 3 3 5 13 of 25 April 10 2001
12. in addition to arithmetic operations and the logic unit performs all of the processor s logical and shift operations Each unit is highly optimized and perform an operation in a single pipeline cycle Both 32 and 64 bit data operations are performed by the RISCore4000 utilizing 32 general purpose 64 bit registers GPR that are used for integer operations and address calculation A complete on chip floating point co processor CP1 which includes a floating point register file and execution units forms a seamless interface decoding and executing instructions in parallel with the integer unit CP1 s floating point execution units support both single and double precision arithmetic as specified in the IEEE Standard 754 and are separated into a multiply unit and a combined add convert divide square root unit Overlap of multiplies and add subtract is supported and the multiplier is partially pipelined allowing the initiation of a new multiply instruction every fourth pipeline cycle The floating point register file is made up of thirty two 64 bit regis ters The floating point unit can take advantage of the 64 bit wide data cache and issue a co processor load or store doubleword instruction in every cycle The 5 40005 system control coprocessor registers are also incorporated on chip and provide the path through which the virtual memory system s page mapping is examined and changed exceptions are handled
13. scan if it is left uncovered JR Vcc JTAG VCC This pin has an internal pull down to continuously reset the JTAG controller if left unconnected bypassing the TRst pin When supplied with Vcc the TRst pin will be the primary control for the JTAG reset Table 5 Pin Descriptions Page 2 of 2 8 of 25 April 10 2001 Logic Diagram RC64474 RC64475 Figure 2 illustrates the direction and functional groupings for the processor signals z g E MasterClock gt woe SysAD 63 0 8 Bip 43 SysCmd 8 0 55 _ 8 gt TDI GET RC64474 TDO VCCOK RC64475 En TMS Logic CodReset amp 8 2 TRST Symbol Reset 2 lt ModeClock 2 JTag32 Em Modeln JR S ES RdRdy gt WrRdy NMI 58 6 E ExtRast gt lt Int 5 0 22 at E E Release o So ValidIn ValidOut Figure 2 Logic Diagram for RC64474 RC64475 9 of 25 April 10 2001 RC64475 208 QFP Package Pin out Pin names followed an asterisk are active when low For maximum flexibility and compatibility with future designs pins should be left floating Pin Function Pin Function Pin Function Pin Function 1 N C
14. with Veg if JTAG is not needed Is tristated when TRst is low 49 5 Yes Can be driven with V if JTAG is not needed 50 Vas TCK Yes Can be driven with if JTAG is not needed 51 Vas TRst Yes Can be driven with if JTAG is not needed 52 Vas TDI Yes Can be driven with if JTAG is not needed 71 N C JR Vec Yes Can be left N C in RC64474 if JTAG is not need If JTAG is needed it must be driven to V Table 8 RC64574 Socket Compatibility to RC64474 and R4640 12 of 25 April 10 2001 RC64474 RC64475 Socket Compatibility RC64475 amp RC4650 RC64575 RC64575 Pin RV4650 32 bit RV4650 64 bit Compatible 32 bit RC64475 64 bit RC64475 to RV4650 32 bit 64 bit 53 N C JTAG32 No Connect JTAG32 Yes In 32 bit this pin can be left unconnected because of internal pull down In 64 bit this assumes that JTAG will not be used If using JTAG this pin must be at V 150 N C JR Vec No Connect JR Vec Yes In RC64475 can be left a N C if JTAG is not need If JTAG is needed it must be driven to Voc 180 N C TDI No Connect TDO Yes If JTAG is not needed can be left a N C 181 N C TRsT No Connect TRsT Yes If JTAG is not needed can be left a N C 182 N C TCK No Connect TCK Yes If JTAG is not needed can be left a N C 183 N C TMS No Connect TMS Yes If JTAG is not needed can be left a N C 184 N C TDO No Connect TDIO Yes If JTAG is not needed can
15. 03 mode44 43 01 03 03 03 ns Input Data Setup tos trise ONS 2 2 2 ns Input Data Hold ix tan 508 10 ho l 09 m T Timings are measured from 1 5V of the clock to 1 5V of the signal Capacitive load for all output timings is 50pF 3 Guaranteed by design S 50pf loading on external output signals fastest settings Also applies to JTAG signals TRST TDO TDI TMS Boot Time Interface Parameters 64474 64474 64474 64475 64475 64475 Parameter Symbol 180 MHz 200 MHz 250MHz Units Min Max Min Max Min Max Mode Data Setup DS 3 3 3 Master Clock Cycle Mode Data Hold 0 0 0 Master Clock Cycle 17 of 25 April 10 2001 RC64474 RC64475 Mode Configuration Interface Reset Sequence 2 3V 2 3V as RN sue ess MCIk VCCOK L2 ModeClock __ Bit DE gt 64K cycles ColdReset IDS tT DS Reset Figure 5 Power on Reset Master x cor 2 a ee MeO ee eee Dee 4 N xx leeds PES gt TDS IDS 2 gt 100 5 256 VCCOK _ 56 cycles ModeClock _ dM TMDS gt lt TMDH Bit Bit rx m Modeln _ 0 1 255 TD
16. 11 7 cycles 14 13 Drv Out Output driver strength output driver slew rate control Bit 14 is MSB 10 100 strength fastest Affects only non clock outputs 11 83 strength 00 67 strength 01 50 strength slowest 12 System interface bus width 0 64 bit system interface 1 32 bit system interface 11 TmrintEn 0 Enabled Timer Interrupt Disables the timer interrupt on Int 5 1 Disabled Timer Interrupt 10 9 Non block write 00 RC4x00 compatible Selects non block write type Bit 10 is MSB 01 Reserved 10 Pipelined writes 11 Write re issue 7 5 Clock Clock multiplier Multiplier 0 Multiply by 2 MasterClock is multiplied internally to gener 1 Multiply by 3 ate PClock 2 Multiply by 4 3 Multiply by 5 4 Multiply by 6 5 Multiply by 7 6 Multiply by 8 7 Reserved 8 EndBit 0 Little endian Specifies byte ordering 1 Big endian 4 1 Writeback data rate 64 bit 32 bit System interface data rate for block writes 9 15 Reserved 9 15 Reserved only bit 415 MSB 8 dxxxdxxxdxxxdxxx 8 gt WXXXWXXXWXXXWXXXWXXXWHXXWXXXWAXX gt WWXXXXXXWWXXXXXXWWXXXXXXWWXXXXXX 6 dxxdxxdxxdxx 6 WXXWXXWXXWXXWXXWXXWXXWXX 5 ddxxxxddxxxx 5 gt WWXXXXWWXXXXWWXXXXWWXXXX 4 gt ddxxxddxxx gt WWXXXWWXXXWWXXXWWXXX 3 dxdxdxdx 3 WXWXWXWXWXWXWXWX 2 ddxxddxx 2 WWXXWWXXWWXXWWXX 1 ddxddx 1 gt WWXWWXWWXWWX 0 dddd 0 gt A WWWWWWWW 0 Reser
17. 2 ge 727 Mo FAX 408 482 8674 TWX 810 338 2070 10 ALL DIMENSIONS ARE IN MILLIMETERS APPROVALS nme VILE DP PACKAGE OUTLINE DRAWN e 20 00 28 0 X 280 X 34 mm POFP 11 THIS OUTLINE CONFORMS TO JEDEC PUBLICATION 95 REGISTRATION MO 143 CERES 1 30 25 MIN FORM VARIATION FA 1 SIZE DRAWING No REV C PSC 4089 00 DO NOT SCALE DRAWING SHEET 2 2 21 of 25 April 10 2001 30 L33HS ONIMYHG 31 05 LON 00 00 040v 9Sd 38 ON 3255 303 57 091 9309 X OBZ X 082 88 02 00 39vMNOvd 20 suu 020 855 018 XML 9 26 BOP xvi 319 282 9 FXX 9098 04010 04105 4 oup KSopouqoa ooria 31512395 5631 532 43101 MINIS 1V3H 03504 3 86 02 60 25 1 8 00 sig ava 1 9109530 A34 SNOISIAGA edesim pee WI 335 719130 335 v Bip April 10 2001 22 of 25 m p
18. 53 JTAG32 105 N C 157 N C 2 N C 54 N C 106 N C 158 N C 3 N C 55 N C 107 N C 159 SysAD59 4 N C 56 N C 108 N C 160 ColdReset 5 N C 57 SysCmd2 109 N C 161 SysAD28 6 N C 58 SysAD36 110 N C 162 VCC 7 N C 59 SysAD4 111 N C 163 Vas 8 N C 60 SysCmd1 112 N C 164 SysAD60 9 N C 61 Vss 113 N C 165 Reset 10 SysAD11 62 Voc 114 SysAD52 166 SysAD29 11 Vss 63 SysAD35 115 ExtRqst 167 SysAD61 12 Voc 64 SysAD3 116 Voc 168 SysAD30 13 SysCmd8 65 SysCmd0 117 Vas 169 Voc 14 SysAD42 66 SysAD34 118 SysAD 1 170 Vas 15 SysAD10 67 Vss 119 SysAD53 171 SysAD62 16 SysCmd7 68 Voc 120 RdRdy 172 SysAD31 17 Vsg 69 SysAD2 121 Modein 173 SysAD63 18 Voc 70 Int5 122 SysAD22 174 Voc 19 SysAD41 71 SysAD33 123 SysAD54 175 Vas 20 SysAD9 72 SysAD1 124 V 176 21 SysCmd6 T3 Vas 125 Vas 177 SysADC3 22 SysAD40 74 Voc 126 Release 178 SysADC7 23 Vsg 75 Int4 127 SysAD23 179 N C 24 Voc 76 SysAD32 128 SysAD55 180 TDI 25 SysAD8 77 SysADO 129 NMI 181 TRst 26 SysCmd5 78 Int3 130 Voc 182 TCK 27 SysADC4 79 Vas 131 Vas 183 TMS 28 SysADCO 80 Voc 132 SysADC2 184 TDO 29 Vsg 81 Int2 133 SysADC6 185 30 82 SysAD16 134 SysAD24 186 31 SysCmd4 83 SysAD48 135 Vos 187 MasterClock 32 SysAD39 84 Int1 136 Vas 188 33 SysAD7 85 Vsg 137 SysAD56 189 Vsg Table 6 RC64475 208 pin QFP Package Pin Out Page 1 of 2 10 of 25 April 10 2001 RC64474 RC64475
19. 6 page TLB 96 page TLB Key Features Cache locking on chip MAC 32 bit external bus Cache locking JTAG SyncDRAM mode 32 bit external bus Cache locking JTAG SyncDRAM mode 32 bit external bus Cache locking on chip MAC 32 bit amp 64 bit bus option Cache locking JTAG SyncDRAM mode 32 64 bit bus option Cache locking JTAG SyncDRAM mode 32 64 bit bus option Table 1 RISCore4000 RISCore5000 Processor Family 2 of 25 April 10 2001 RC64474 RC64475 A secure user processing environment is provided through the user supervisor and kernel operating modes of virtual addressing to system software Bits in a status register determine which of these modes is used If configured for 64 bit virtual addressing the virtual address space layout becomes an upwardly compatible extension of the 32 bit virtual address space layout Figure 1 is an illustration of the address space layout for the 32 bit virtual address operation OxFFFFFFFF Kernel virtual address space kseg3 0 0000000 Mapped 0 568 OxDFFFFFFF Supervisor virtual address space sseg Mapped 0 5GB 0xC0000000 OxBFFFFFFF Uncached kernel physical address space kseg1 0xA0000000 Unmapped 0 5GB Ox9FFFFFFF Cached kernel physical address space kseg0 Unmapped 0 5GB 0x80000000 Ox7FFFFFFF User virtual address space useg Mapped 2 0GB 0x00000000 Figure 1 Kernel Mode Virtual A
20. RC64474 RC64475 DC Electrical Characteristics Commercial Temperature Range RC64474 64475 Voc 3 345 Tease 0 C to 85 C RC64474 RC64475 RC64474 RC64475 RC64474 RC64475 180MHz 200MHz 250MHz Parameter Conditions Minimum Maximum Minimum Maximum Minimum Maximum VoL 0 1V 0 1V 0 1V 200A Vou Vec 0 1V Vec 0 1V Vec 0 1V VoL 0 4V 0 4V 0 4V 4mA 24 24 24 VL Q 5V 0 2Vcc Q 5V 0 2Vcc 0 5V 0 2Vcc Vig 2 0V Voc 0 5V 0 7Vcc Voc 0 5V 2 0V Voc 0 5V lin 100 100 100 0 lt Vin lt Vec ON 10pF 10pF 10pF E Cour 10pF 10pF 10pF 20uA 200 20uA Input Output Leakage Power Consumption RC64474 RC64474 180MHz RC64474 200MHz RC64474 250MHz Parameter Conditions Typical Max Typical Max Typical Max System Condition 180 90MHz 200 100MHz 250 125MHz Es standby 60 mA 60 mA 100 mA C 110 mA2 110 mA 110 mA C 50 active 530 mA 630 mA 600mA 700 mA 700 mA 850mA C OpF No SysAd activity 630mA 750 mA 700 mA 850 mA 850mA 1000 2 C 50 R4x00 compatible writes 25 750 mA 1050 850 mA 1200 1000mA 1400mA C 50pF Pipelined writes or write re issue 25 C Typical integer instruction mix and c
21. S gt 4 TDS B gt 64K cycles ColdReset __ 64 cydles 5 gt TDS IV Reset Figure 6 Cold Reset E MCIk MECOK 256 cycle ModeClock ColdReset _ TDS TDS gt Reset gt 64 cycles Figure 7 Warm Reset 18 of 25 April 10 2001 RC64474 RC64475 lt 500 ANA RC64474 RC64475 500 5 Equivalent Limp Signal Capacitance Signals 25 pF Figure 8 Output Loading for AC Timing 19 of 25 April 10 2001 64475 Physical Specifications The RC64475 is available in a 208 pin power quad PQUAD package 61478 00 INITIAL RELEASE 09 20 98 D A D1 6172 072 LEAD SIDES ODD LEAD SIDES 2 de E EXPOSED HEAT SINK pe ES 7 ES BOR D A ss A BE SS DETAIL A E i FU SL PJE zz SEE DETAIL ES
22. ache miss rates These are not tested They are the resu 3 Guaranteed by design 4 These are the specifications IDT tests to insure compliance 14 of 25 April 10 2001 ts of engineering analysis and are provided for reference only RC64474 RC64475 Power Consumption RC64475 RC64475 180MHz RC64475 200MHz RC64475 250MHz Parameter Conditions Typical Max Typical Max Typical Max System Condition 180 90MHz 200 100MHz 250 125MHz standby 60 mA 60 mA 100 mA C 110 m A 110 mA 110 mA C 50pF active 720 mA 850 mA 850 mA 1000 mA 935 mA 1100 mA C OpF 64 bit bus No SysAd activity v option 850 mA 1000 mA 1000 mA 1200 mA 1100mA 1360mA C R4x00 compatible writes Tc 25 C 1000 mA 1200 mA 1200 mA 1400 mA 1360 mA 1600 mA C 50 Pipelined writes or write re issue Te 25 C Typical integer instruction mix and cache miss rates These are not tested They are the results of engineering analysis and are provided for reference only 3 Guaranteed by design n 32 bit bus option use RC64474 power consumption values 5 These are the specifications IDT tests to insure compliance Timing Characteristics RC64474 RC64475 Cycle 1 MasterClock GENE E EE MEINEN MEM A won J i SysAD SysCmd
23. and any operating mode selections are controlled RISCore4000 RISCore5000 Family of Socket Compatible Processors 32 bit Processors 64 bit Processors RC4640 RC64474 RC64574 RC4650 RC64475 RC64575 CPU 64 bit RISCore4000 64 bit RISCore4000 64 bit RISCore5000 w 64 bit RISCore4000 64 bit RISCore4000 64 bit RISCore5000 w DSP extensions DSP extensions w DSP extensions w DSP extensions Performance gt 350 5 gt 330 5 gt 440 5 gt 350 5 gt 330 5 gt 440 5 89 mflops single pre 125 mflops single and 666 mflops single and 89 mflops single pre 125 mflops single 666 mflops single cision only double precision double precision cision only and double precision and double precision Caches 8kB 8kB 2 way lock 16 16 2 way 32kB 32kB 2 way 8kB 8kB 2 lock 16 16 2 way 32kB 32kB 2 way able by set lockable by set lockable by line able by set lockable by set lockable by line External Bus 32 bit 32 bit Superset pin 32 bit Superset pin 32 or 64 bit 32 or 64 bit Super 32 or 64 bit Super compatible w RC4640 compatible w RC4640 set pin compatible w set pin compatible w RC64474 RC4650 RC4650 RC64475 Voltage 3 3V 3 3V 2 5V 3 3V 3 3V 2 5V Frequencies 100 267 MHz 180 250 MHz 200 333 MHz 100 267 MHz 180 250 MHz 200 333 MHz Packages 128 PQFP 128 QFP 128 QFP 208 QFP 208 QFP 208 QFP MMU Base Bounds 96 page TLB 96 page TLB Base Bounds 9
24. but can issue an additional write after WrRdy de asserts Choosing a 32 or 64 bit wide system interface dictates whether a cache line block transaction requires 4 double word data cycles or 8 single word cycles as well as whether a single data transfer larger than 4 bytes must be divided into two smaller transfers Board level testing during Run Time mode is facilitated through the full JTAG boundary scan facility Six pins TDI TDO TMS TCK TRST and JTAG32 have been incorporated to support the standard JTAG interface System Enhancement To facilitate discrete interface to SDRAM the RC64474 475 bus interface is enhanced during write cycles with a programmable delay that is inserted between the write address and the write data for both block and non block writes The bus delay can be defined as 0 to 7 MasterClock cycles and is activated and controlled through mode bit 17 15 settings selected during the reset initialization sequence The 000 setting provides the same write operations timing protocol as the RC4640 RC4650 and RC5000 processors 4 of 25 April 10 2001 RC64474 RC64475 TA Description Value amp Mode Setting 255 18 Reserved Must be 0 17 15 WAdrWData Del 000 0 cycles Write address to write data delay in Master 001 1 cycle Clock cycles amp 010 2 cycles 011 cycles 100 4 cycles 101 5 cycles 110 6 cycles 1
25. d or data iden tifier on the SysCmd bus ValidOut 0 Valid output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus SysAD 63 0 System address data bus A 64 bit address and data bus for communication between the processor and an external agent During address phases only SysAd 35 0 contains valid address information The remaining SysAD 63 36 pins are not used The whole 64 bit SysAD 63 0 may be used during the data transfer phase In 32 bit mode and in the RC64474 SysAD 63 32 is not used regardless of Endianness A 32 bit address and data com munication between processor and external agent is performed via SysAD 31 0 SysADC 7 0 System address data check bus An 8 bit bus containing parity check bits for the SysAD bus during data bus cycles In 32 bit mode and in the RC64474 SysADC 7 4 is not used The SysADC 3 0 contains check bits for SysAD 31 0 SysCmd 8 0 System command data identifier bus A 9 bit bus for command and data identifier transmission between the processor and an external agent SysCmdP System Command A single even parity bit for the Syscmd bus This signal is always driven low Clock Control Interface MasterClock Master Clock Master clock input establishes the processor and bus operating frequency It is multiplied internally by 2 3 4 5 6 7 8 to gen erate the pipeline clock PClock This clock
26. ddressing 32 bit Mode The RC64474 RC64475 s Memory Management Unit MMU controls the virtual memory system s page mapping and consists of a translation lookaside buffer TLB used for the virtual memory mapping subsystem This large fully associative TLB maps 96 virtual pages to their corresponding physical addresses The TLB is organized as 48 pairs of even odd entries and maps a virtual address and address space identi fier into the large 64GB physical address space To assist in controlling the amount of mapped space and the replacement characteristics of various memory regions two mechanisms are provided First the page size can be configured on a per entry basis to map a page size of 4KB to 16MB in increments of 4x The second mechanism controls the replacement algorithm when a TLB miss occurs A random replacement algorithm is provided to select a TLB entry to be written with a new mapping however the processor provides a mechanism whereby a system specific number of mappings can be locked into the TLB and avoid being randomly replaced which facilitates the design of real time systems by allowing deterministic access to critical software The TLB also contains information to control the cache coherency protocol and cache management algorithm for each page However hardware based cache coherency is not supported The RC64474 and RC64475 enhance IDT s entire RISCore4000 series through the implementation of features suc
27. e typical power dissipation of the device Airflow ft min 200 400 600 800 1000 128 16 10 9 7 6 5 208 20 13 10 9 8 7 Table 4 Thermal Resistance at Various Airflows Data Sheet Revision History December 1998 Changed ordering code on 128 pin package from DQ DQI Industrial to DZ DZI Industrial January 1999 Removed 5V tolerance capability and deleted 5V tolerant pin February 1999 Changed the package drawings to reflect the new 208 pin DP DPI and 128 pin DZ DZI packages May 1999 Removed Preliminary status from data sheet Changes in DC Electrical Characteristics table Changes in Pin Description table Changes in Clock Parameters table Changes in System Interface Parameters table September 1999 Updated Revision History section January 17 2000 Added with DSP extensions in the CPU row under RC64574 and RC64575 columns in Table 1 Added lockable by line in the Caches row under RC64574 and RC64575 columns in Table 1 Revised Data Output and Data Output Hold rows in System Interface Parameters table February 10 2000 Revised values in Table 4 Thermal Resistance Old values were Airflow ft min 200 400 600 800 1000 128 20 12 9 8 7 6 208 20 12 9 8 7 6 March 13 2000 Replaced existing figure in Mode Configuration Interface Reset Sequence
28. h as boundary scan to facilitate board level testing enhanced support for SyncDRAM to simplify system implementation and improve performance The RC64474 475 processors offer a direct migration path for designs based on IDT s RC4640 RC4650 processors through full pin and socket compatibility Also full 64 bit family software and bus protocol compatibility ensures the RC64474 475 access to a robust development tools infrastructure allowing quicker time to market Development Tools An array of hardware and software tools is available to assist system designers in the rapid development of RC64474 475 based systems This accessibility allows a wide variety of customers to take full advan tage of the device s high performance features while addressing today s aggressive time to market demands Cache Memory To keep the RC64474 and RC64475 s high performance pipeline full and operating efficiently on chip instruction and data caches have been incorporated Each cache has its own data path and can be accessed in the same single pipeline clock cycle The 16KB two way set associative instruction cache is virtually indexed physically tagged and word parity protected Because this cache is virtually indexed the virtual to physical address translation occurs in parallel with the cache access further increasing performance by allowing both operations to occur simultaneously The instruction cache provides a peak instructio
29. king per set per set Table 2 RC64474 RC64475 Instruction Data Cache Attributes System Interfaces The RC64475 supports a 64 bit system interface that is bus compat ible with the RC4650 and RC64575 system interface The system inter face consists of a 64 bit Address Data bus with 8 check bits and a 9 bit command bus that is parity protected During 64 bit operation RC64475 system address data SysAD transfers are protected with an 8 bit parity check bus SysADC When initialized for 32 bit operation the RC64475 s SysAD can be viewed as 32 bit multiplexed bus that is protected by 4 parity check bits The RC64474 supports a 32 bit system interface that is bus compat ible with the RC4640 During 32 bit operation SysAD transfers are performed on a 32 bit multiplexed bus SysAD 31 0 that is protected by 4 parity check bits SysADC 6 0 Writes to external memory whether they are cache miss write backs stores to uncached or write through addresses use the on chip write buffer The write buffer holds a maximum of four 64 bit addresses and 64 bit data pairs The entire buffer is used for a data cache write back and allows the processor to proceed in parallel with memory updates Included in the system interface are six handshake signals RdRdy WrRdy ExtRqst Release ValidOut and Validln six inter rupt inputs and a simple timing specification that is capable of trans ferring data between the processor a
30. mmnmmmmmmmn 2 9NUv3S C3NI SBISO 38 OL 3 ANY SNOISNGIIG H 1v 38 OL d anv 857 swruva GL 3OVwOVd NYHL 38 AVN JOvMOVd 40 ES ES 66L NG tLA 3NSV OL NYOINOD 9 01 ONY 9NINOISN3HIQ TIY Co Co E E 540 Co 5 Eric MEM LY Se 6 Sp 6 e 258 08 3 821 5 4234 0012 H 268 00782 13 a 058 0215 3 ca cS 258 00792 o te o D 058 0712 oge Ore oze ev 8 00000000000000000000000000000000 Se N 079 6 OWN NON d Bi 1 80 S iQ a 2303 SNOISNAWIG O 2 EE lt 86 02 0 35 3134 JVILINI 1 919 3iva 42534 Ada Nog e SNOISIAGH RC64474 RC64475 Ordering Information T9RCXX 999 Product Operating Type Voltage Temp range Speed Package Process Commercial Temperature Blank 0 C to 85 C Case Industrial Temperature 40 C to 85 C Case DZ 128 pin QFP DP 208 pin QFP 180 180 MHz 200 200 MHz 250 250 MHz 474 Embedded Processor 475 V 3 3V 5 T9RC64 64 bit Embedded Microprocessor Valid Combinati
31. must be driven by 3 3V Vcc clock signals regardless of the 5V tolerant pin setting VccP Quiet VCC for PLL Quiet Vcc for the internal phase locked loop VssP Quiet Vss for PLL Quiet Vss for the internal phase locked loop Interrupt Interface Int 5 0 Interrupt Six general processor interrupts bit wise ORed with bits 5 0 of the interrupt register Table 5 Pin Descriptions Page 1 of 2 7 of 25 April 10 2001 RC64474 RC64475 Pin Name Type Description NMI Non maskable interrupt Non maskable interrupt ORed with bit 6 of the interrupt register Initialization Interface Vccok Vecis OK When asserted this signal indicates to the processor that the power supply has been above the Vcc minimum for more than 100 milliseconds and will remain stable The assertion of Vccok initiates the initialization sequence ColdReset Cold reset This signal must be asserted for a power on reset or a cold reset ColdReset must be de asserted synchronously with Mas terClock Reset Reset This signal must be asserted for any reset sequence It can be asserted synchronously or asynchronously for a cold reset or synchronously to initiate a warm reset Reset must be de asserted synchronously with MasterClock ModeClock Boot mode clock Serial boot mode data clock output at the system clock frequency divided by two hundred fifty six Modeln Boot mode data in Serial boot mode data input
32. n bandwidth of 1000MB sec at 250MHz The 16KB two way set associative data cache D cache is byte parity protected and has a fixed 32 byte eight words line size Its tag is protected with a single parity bit To allow simultaneous address transla tion and data cache access the D cache is virtually indexed and physi cally tagged The data cache can provide 8 bytes each clock cycle for a peak bandwidth of 2GB sec To lock critical sections of code and or data into the caches for quick access a cache locking feature has been implemented Once enabled a cache is said to be locked when a particular piece of code or data is loaded into the cache and that cache location will not be selected later for refill by other data This feature locks a set 8KB of Instructions and or Data Table 2 lists the RC64474 475 Instruction and data cache attributes 2 To ensure socket compatibility refer to Table 8 and Table 9 at back of data sheet 3 of 25 April 10 2001 RC64474 RC64475 Characteristics Instruction Data Size 16KB 16KB Organization 2 way set 2 way set associative associative Line size 32B 32B read unit 32 bits 64 bits write policy na write back write through with or without write allocate Line transfer order sub block order sub block order for load for refill sequential order for store Miss restart entire line miss word after transfer of Parity per word per byte Cache loc
33. nal cache bandwidth for these devices is over 3GB second The 64 bit external bus bandwidth is at more than 1000MB s and the 32 bit external bus bandwidth is at 500MB s The RC64474 is packaged in a 128 pin QFP footprint package and uses a 32 bit external bus offering the ideal combination of 64 bit processing power and 32 bit low cost memory systems The RC64475 is packaged in a 208 pin QFP footprint package and uses the full 64 bit external bus The RC64475 is ideal for applications requiring 64 bit performance and 64 bit external bandwidth IDT s 5 4000 is a 250MHz 64 bit execution core that uses 5 stage pipeline eliminating the issue restrictions associated with other more complex pipelines RISCore4000 implements the MIPS III Instruction Set Architecture ISA and is upwardly compatible with applications that run on earlier generation parts Implementation of the MIPS III architecture results in 64 bit opera tions improved performance for commonly used code sequences in 1 Detailed system operation information is provided in the RC64474 RC64475 user s manual operating system kernels and faster execution of floating point intensive applications The RISCore4000 integer unit implements a load store architecture with single cycle ALU operations logical shift add subtract and an autonomous multiply divide unit The ALU consists of the integer adder and logic unit The adder performs address calculations
34. nd memory at a peak rate of 1000MB sec A boot time selectable option to run the system interface as 32 bits wide using basically the same protocols as the 64 bit system is also supported A boot time mode control interface initializes fundamental processor modes The boot time mode control interface is a serial inter face that operates at a very low frequency MasterClock divided by 256 This low frequency operation allows the initialization information to be kept in a low cost EPROM alternatively the twenty or so bits could be generated by the system interface ASIC or a simple PAL The boot time serial stream and configuration options are listed in Table 3 The clocking interface allows the CPU to be easily mated with external reference clocks The CPU input clock is the bus reference clock and can be between 25 and 125MHz An on chip phase locked loop PLL generates the pipeline clock PClock through multiplication of the system interface clock by values of 2 3 4 5 6 7 or 8 as defined at system reset This allows the pipeline clock to be implemented at a significantly higher frequency than the system interface clock The RC64474 475 support single data one to eight bytes and 8 word block transfers on the SysAD bus The RC64474 475 implement additional write protocols that double the effective write bandwidth The write re issue has a repeat rate of 2 cycles per write Pipelined writes have the same 2 cycle per write repeat rate
35. nt1 13 SysCmd4 45 MasterClock TT Vss 109 SysAD16 Table 7 RC64474 128 pin QFP Package Pin out Page 1 of 2 11 0125 10 2001 RC64474 RC64475 Pin Function Pin Function Pin Function Pin Function 14 Vcc 46 VssP 78 Vec 110 Int2 15 Vss 47 VccP 79 SysAD24 111 Vcc 16 SysAdCO 48 TDO 80 SysADC2 112 Vss 17 SysCmd5 49 TMS 81 Vss 113 Int3 18 SysAD8 50 TCK 82 Vcc 114 SysADO 19 Vcc 51 TRst 83 NMI 115 Int4 20 Vss 52 TDI 84 SysAD23 116 Vcc 21 SysCmd6 53 Vss 85 Release 117 Vss 22 SysAD9 54 SysADC3 86 Vss 118 SysAD1 23 Vec 55 VccOK 87 Vcc 119 Int5 24 Vss 56 Vss 88 SysAD22 120 SysAD2 25 57 Vcc 89 Modein 121 Vcc 26 SysAD10 58 SysAD31 90 RdRdy 122 Vss 27 SysCmd8 59 Vss 91 SysAD21 123 SysCmd0 28 Vcc 60 Vcc 92 Vss 124 SysAd3 29 Vss 61 SysAD30 93 Vcc 125 Vcc 30 SysAD11 62 SysAD29 94 ExtRqst 126 Vss 31 SysCmdP 63 Reset 95 SysAD20 127 SysCmd1 32 SysAD12 64 Vss 96 ValidOut 128 SysAD4 Table 7 RC64474 128 pin QFP Package Pin out Page 2 of 2 Socket Compatibility RC64474 amp RC4640 To ensure socket compatibility between the RC4640 and the RC64474 devices several pin changes are required as shown below Pin RC4640 2 Comments 1 N C JTAG32 Yes Pin has an internal pull down to enable 32 bit scan Can also be left a N C 48 Vas TDO Yes Can be driven
36. ons T9RC64V474 180 200 250 DZ 128 pin QFP package Commercial Temperature 79RC64V475 180 200 250 DP 208 pin QFP package Commercial Temperature T9RC64V474 180 200 250 021 128 pin QFP package Industrial Temperature T9RC64V475 180 200 250 DPI 208 pin QFP package Industrial Temperature CORPORATE HEADQUARTERS for SALES for Tech Support 6024 Silver Creek Valley Road 800 345 7015 or 408 284 8200 fax 408 284 2775 www idt com email rischelp idt com phone 408 284 8208 DT San Jose CA 95138 The IDT logo is a trademark of Integrated Device Technology Inc 25 of 25 April 10 2001
37. section with 3 reset figures March 28 2000 Removed the symbol tpz from Figure 3 April 17 2000 Changed value in 200MHz column from 2 0V to 0 7 April 10 2001 In the Data Output and Data Output Hold categories of the System Interface Parameters table changed values in the Min column for all speeds from 1 0 to 0 Deleted Output for Loading AC Testing diagram and added Output Loading for AC Timing diagram Figure 8 6 of 25 April 10 2001 RC64474 RC64475 Pin Description Table The following is a list of system interface pins available on the RC64474 475 Pin names ending with an asterisk are active when low Pin Name Type Description System Interface ExtRqst External request An external agent asserts ExtRqst to request use of the System interface The processor grants the request by asserting Release Release 0 Release interface In response to the assertion of ExtRqst or a CPU read request the processor asserts Release and signals to the request ing device that the system interface is available RdRdy Read Ready The external agent asserts RdRdy to indicate that it can accept a processor read request WrRdy Write Ready An external agent asserts WrRdy when it can now accept a processor write request ValidIn Valid Input Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid comman
38. ved Must be zero 5 of 25 April 10 2001 Table 3 Boot time Mode Stream RC64474 RC64475 Power Management Executing the WAIT instruction enables the processor to enter Standby mode The internal clocks will shut down thus freezing the pipeline The PLL internal timer and some of the input pins Int b O NMI ExtReq Reset and ColdReset will continue to run Once the CPU is in Standby Mode any interrupt including the internally gener ated timer interrupt will cause the CPU to exit Standby Mode Thermal Considerations The RC64474 475 come in a QFP with a drop in heat spreader and are guaranteed in a case temperature range of 0 to 85 C for commercial temperature devices 40 to 85 for industrial tempera ture devices The type of package speed power of the device and airflow conditions affect the equivalent ambient temperature conditions that will meet this specification The equivalent allowable ambient temperature Ta can be calculated using the thermal resistance from case to ambient Oca of the given package The following equation relates ambient and case tempera tures Tc P where P is the maximum power consumption at hot temperature calculated by using the maximum Icc specification for the device Typical values for at various airflows are shown in Table 4 Note that the RC64474 475 processors implement advanced power manage ment which substantially reduces th
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