USER`S MANUAL
Contents
1. 16 A SINGLE ENDED VOLTAGE INPUT CONNECTION DIAGRAM P2 BORNE 5 2 ESO E 5061 ES1 CH39 80839 ES39 1 SENSE EARTH GROUND ANALOG COMMON DIGITAL CONNECTION AT SHIELD ji COMMON POWER SUPPLY SEE NOTE 2 TYPICAL SEE NOTE 1 gt B DIFFERENTIAL VOLTAGE INPUT CONNECTION DIAGRAM E324 CARRIER BQARD a P 50 DCH00 1 222 ES1 DCHO1 DCHe1 i 7 519 DCH19 i A CH19 DCH19 Le EARTH GROUND BNALOGICOMMON DIGITAL CONNECTION AT SHIELD COMMON POWER SUPPLY SEE NOTE 2 A i TYPICAL Mors SEE NOTE 1 7 1 SHIELDED CABLE IS RECOMMENDED FOR LOWEST NOISE SHIELD IS CONNECTED TO GROUND REFERENCE AT ONE END ONLY TO PROVIDE SHIELDING WITHOUT GROUND LOOPS 2 REFERENCE CHANNELS TO ANALOG COMMON IF THEY WOULD OTHERWISE BE FLOATING CHANNELS ALREADY HAVING A GROUND REFERENCE MUST NOT BE CONNECTED TO ANALOG COMMON TO AVOID GROUND LOOPS 450 1 A 35 3 EXTERNAL SUPPLIES BE USED BY JUMPERING IT IS RECOMMENDED THAT THE SUPPLY COMMONS CONNECTED TO ANALOG COMMON LOGIC J1 amp J2 P1 CALIBRATION CONFIG VOLTAGES M INST S H amp DATA BUS MUX AMP amp 12 BIT PGA ADC t CONTROL LOGIC EXTERNAL TRIGGER INPUT CONTROL gt f Y REGISTER SS L ANALOG COMMON V2. The function of each register noted in Table 3 1 will be discussed in the following sections IP Identification PROM Read Only 32 odd byte addresses Each IP module contains an identification ID PROM that resides in the ID space per the IP module specification This area of memory contains 32 bytes of information at most Both fixed and variable information may be present within the ID PROM Fixed information includes the IPAC identifier model number and manufacturer s identification codes Variable information includes unique information required for the module The IP320 ID PROM does not contain any variable e g unique calibration information ID PROM bytes are addressed using only the odd addresses in a 64 byte block The IP320 ID PROM contents are shown in Table 3 2 Note that the base address for the IP module ID space see your carrier board instructions must be added to the addresses shown to properly access the ID PROM Execution of an ID PROM Read requires 0 wait states Table 3 2 IP320 ID Space Identification PROM Hex Offset From ID PROM Base Character Value Address Equivalent Hex NONE NEUE m ASCII Numeric Field Description All IP s have Acromag ID Code IP Model Code Not Used Revision Not Used Driver ID Low Byte Not Used Driver ID High Byte ID PROM Bytes Notes Table 3 2 1 The IP model number is represented by a two digit code within
3. CHO0 19 em 20 39 Auto Zero input is enabled by the mode bits overriding all channel selection bits Control the programmable gain setting as described in the following table Desired Gain GSEL1 GSELO Bit 1 Bit 1 Not used if read will return data written to the bit position The SEL HIGH bit acts as the MSB for analog input channel selection As such its action is grouped with that of bits 3 0 see following Control the selection of analog input channels per the following table Note that the SEL HIGH bit and MODE bits are also shown to completely define the channel selection When MODE 1 amp MODE 0 are both 0 differential channels 0 19 and calibration voltages 0 3 may be selected when MODE 1 is 0 and MODE 015 1 single ended channels 0 19 may be selected when MODE 1 is 1 and MODE 0 is 0 single ended channels 20 39 may be selected when both MODE 1 amp MODE 0 are 1 the Auto Zero input is selected regardless of any other bit levels CH3 CH2 CH1 CHO Mode Mode 1 0 Bit Bit Bit Bit Bit Bit DO3 DO2 DO1 DOO D09 D08 o o o fof 0 0 0 0 1 0 for 0 o for o of t 1 0 122282 for a o0 for o AO 1 31 96 o 7 _ 0 0 1 1 1 o o 0 1 01 o oi 0 1 90 1 E o o to J 1 0 21 50 0 Bt saan aaa o 1 1 a
4. o 0 dep cde 0 1 o o 4_ 0 p 1 1 0 o o 5 1 1 1 1 o 16 ti toetoe oj of o ae Zero ADC Convert Command Write Base 10H The ADC Convert Command is a write only register will not respond to reads that is used to trigger a conversion The data written to this location should be all ones to reduce digital noise although the write action alone is sufficient to trigger the conversion Execution of this command requires 0 wait states SERIES IP320 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD 015 000 FFFF NOTE FFFF means that all bits are programmed as ones Read ADC Data Read Base 20H Use the Read ADC Data command to read the results of the last ADC conversion This command should be used following the ADC Convert command or an external trigger input Bit 15 CTRIG in the Control Register can be used to determine if a conversion has been triggered either by software command or external trigger input If the Read ADC Data command is executed while the ADC conversion is taking place then the IP320 will institute wait states until the data is available up to 8 5 uS before providing the ADC data and completing the cycle Execution of the read command requires 3 wait states if the ADC conversion completed prior to initiating the read command The execution of this command will reset the CTRIG bit in the Control Register The 12 bits
5. 2510425 4 21 0057 125104125 8 25 006 085 2 22 005 01025 4 31 007 004255 8 510 125 4 0 THEORY OPERATION This section describes the functionality of the IP320 circuitry Refer to the block diagram of Drawing 4501 436 as you study the following paragraphs ANALOG INPUTS The field I O interface via the carrier board is through connector P2 Field analog inputs are non isolated This means that the field analog return and logic common have a direct electrical connection Care must be taken to avoid ground loops and excessive common mode voltage see Section 2 for connection recommendations These can cause measurement error and with extreme abuse circuit damage Analog inputs and calibration voltages are selected via CMOS analog multiplexers MUX s A software programmable control register contains gain acquisition mode e g single ended or differential and channel selection information to control the multiplexers Up to 40 single ended inputs can be monitored where each channel s input is individually selected along with a single sense lead for all channels Up to 20 differential inputs can be monitored where each channel s and inputs are individually Selected Single ended and differential channels cannot be mixed i e they must all be single ended or differentially wired A Programmable Gain Instrumentation Amplifier PGA takes as input the
6. README TXT file in the root directory and the INFO320 TXT file in the IP320 subdirectory on the diskette for more details 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product Inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment It is recommended that the board be visually inspected for evidence of mishandling prior to applying power The board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS V Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed IP modules within the voltage tolerances specified
7. 5 to 2 5 to 2 5 1 25 to 1 25 0 625 to 0 625 10 to 10 5 to 2 2 5 to 4 2 5 1 25 to 2 4500 CAL1 1 2250 CAL2 1 25 0 to 1 0 to 0 6125 CAL3 4 9000 CALO 10 10 The following equation 1 is used to correct the actual ADC data i e the uncorrected bit count read from the ADC making use of the calibration voltages and range constants 0 to 4 2 5 0 to 1 25 Volts Corrected Count 4096 m Ideal Volt Span Count Actual Voltc A Gain Ideal Zero CountcA 1 where m represents the actual slope of the transfer characteristic as defined in equation 2 SERIES IP320 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD m Gain VoltcaLHI VoltcaLLo CountcA HI s CountcA o 2 Gain Programmable Gain Amplifier Setting Used See Previous Table Voltc A ni High Calibration Voltage See Previous Table VoltcaLLo Low Calibration Voltage See Previous Table Countc A ni Actual ADC Data Read With High Calibration Voltage Applied CountcA Actual ADC Data Read With Low Calibration Voltage Applied Ideal ADC Voltage Span See Following Table Ideal Volt Span the ADC and averaged to reduce the measurement uncertainty Calibration Programming Example 1 Assume that the input range is 10 to 10 volts Channel 0 is connected differentially and corrected input channel data is desired Fr
8. Base 20H Note that See Following Table the 12 bit data is left justified within the 16 bit word 10 Repeat steps 8 and 9 several times e g 16 and take the Table 3 5 Ideal Voltage Span and Zero For Input Ranges average of the ADC results Save this number as Counto ADC Ideal Volt Ideal 11 Calculate m actual slope from equation 2 since all parameters Volts Volts Volts Volts It is now possible to correct input channel data from any input 25t0 425 2 channel using the same input range i e 10 to 10 volts with a 1250 6 4 5 4 e 1 PGA gain 1 Repeat steps 1 11 periodically to re measure 062510 40625 8 the calibration parameters Counto al and CountcaA Lo as E 505 2 12 To prepare to measure channel 0 differentially write to the 194 3 4 sto 1 Control Register Base OOH to setup the differential input 5t0 1 25 8 o channel 0 acquisition mode and PGA gain 1 by writing 0000H Note that not used bits are set to zero 006 2 13 Delay to allow for input settling 0t 25 581 14 Execute ADC Convert Command Base 10H 010104125 8 15 Execute Read ADC Data Command 9 Base 20H Note that the 12 bit data is left justified within the 16 bit word This data The calibration parameters Counta jjj and f
9. ID PROM 111 15 SUPPLIES J3 amp J4 12 SUPPLIES SUPPLY SELECTION IP32 BLOCK DIAGRAM 4501 436 SERIES 20 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD O 4 o 50 OF P1 amp P2 CONNECT TO GROUND SHIELD EL 5025 550 SCH EMAT 3 O 4 lt o YL EL 5025 551 SCHEMAT P2 P1 To AVME9630 9660 MODEL 5025 552 CARRIER BOARD 1 0 TERMINATION OR P4 P5 P6 KY PANEL ini X FEET TOP VIEW 50 PIN CONNECTOR 1004 512 STRAIN RELIEF 1004 534 NON SHIELDED RIBBON CABLE 2002 211 POLARIZING KEY 50 1994 512 PIN 1 PIN 1 ON CABLE NO MARKINGS FRONT VIEW NOTE SEVEN DIGIT PART NUMBERS ARE ACROMAG PART NUMBERS XXXX XXX C MODEL 5025 551 SIG
10. IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature The dense packing of the IP modules to the carrier board restricts air flow within the card cage and is cause for concern Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS BOARD CONFIGURATION The board may be configured differently depending on the application All possible jumper settings will be discussed in the following sections The jumper locations are shown in Drawing 4501 433 Power should be removed from the board when configuring hardware jumpers installing IP s cables termination panels and field wiring Refer to Drawing 4501 434 and IP documentation for IP configuration and assembly instructions SERIES IP320 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD Default Hardware Jumper Configuration A board shipped from the factory is configured as follows Analog input range is configured for a 10V bipolar input span i e an ADC input range of 5 to 5 Volts 9 Internal 12 Volt
11. the ID PROM the IP320 model is represented by 32 Hex Control Register Read Write Base 00H The IP320 Control Register reflects and controls analog input channel data acquisition functions This register must be written read one word D16 at a time Execution of a Control Register read write requires 0 1 wait states The function of each bit is described as follows EVEN Byte MSB LSB D15 14 D13 D12 11 D10 008 CTRIG Not Not Not Not Not MODE MODE used used used used used 1 0 SERIES 20 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD ODD Byte MSB D07 001 GSEL in Not SEL CH3 CH2 CH1 1 used HIGH RESET CONDITION all bits are undefined Registers should be programmed to the desired configuration before starting ADC analog input acquisition Bit 15 Bits 14 10 Bits 9 amp 8 Bits 7 amp 6 Bit 5 Bit 4 Bits 3 0 When read the CTRIG bit indicates whether an ADC conversion has been triggered either by software command or external trigger input If the bit reads high the conversion could be taking place or has been completed CTRIG is cleared by reading the ADC data Writing to this bit position will have no effect Not used if read will return data written to those bit positions Control the input acquisition mode as described in the following table Acquisition Mode Bit D09 Bit 008 enano p 19 amp CALO 3
12. INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD In Table 2 5 channel designations are abbreviated to save space For example single ended channel 0 is abbreviated as SCHOO the input for differential channel 0 is abbreviated as Both of these labels are attached to pin 1 but only one applies according to whether the input is single ended or differential i e if your inputs are applied differentially follow the differential channel labeling for each channel s and input leads Table 2 5 IP320 Field Pin Connections P2 Pin Description Number Pin Description Number SCH22 DCHO2 6 SCH23 DCHO3 8 SCHO4 DCHO4 9 Indicates an Active Low Signal Analog Input Noise and Grounding Considerations Differential inputs require two leads 4 and per channel and provide rejection of common mode voltages This allows the desired signal to be accurately measured However the signal being measured cannot be floating it must be referenced to analog common on the IP module and be within the normal input voltage range Differential inputs are the best choice when the input channels are sourced from different locations having slightly different ground references See Drawing 4501 435 for analog input connections for differential and single ended inputs Single ended inputs only require a single lead per channel with a shared sense reference lead for all cha
13. and must be zeroed or ignored in calculations made with the data returned from the IP module Table 2 4 Bipolar Offset Binary BOB Analog Data Format Volts Hex 0 0024 8010 0 0000 8000 0 0024 7FFO For Table 2 4 it is assumed that the analog input range bipolar is 5 to 5 Volts i e with a programmable gain of 1 The BOB 12 bit data is left justified within the 16 bit word The 4 Least Significant Bits LSB s are shown as zero in the table Actually they are undefined and must be zeroed or ignored in calculations made with the data returned from the IP 5 IP Field I O Connector P2 P2 provides the field I O interface connector for mating IP modules to the carrier board P2 is a 50 pin receptacle female header AMP 173279 3 or equivalent which mates to the male connector of the carrier board 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the module to provide additional stability for harsh environments see Mechanical Assembly Drawing 4501 434 The field and logic side connectors are keyed to avoid incorrect assembly P2 pin assignments are unique to each IP model see Table 2 5 and normally correspond to the pin numbers of the front panel field I O interface connector on the carrier board you should verify this for your carrier board SERIES 20
14. are used typically to 9 Volt maximum inputs The user has the option of providing 15 Volt external supplies to fully utilize input ranges to 10 Volts These supplies are selected via hardware jumpers J3 and J4 as detailed in Section 2 Note that jumper selection should be made prior to powering the unit Further internal and external supplies should not be mixed e g do not use 12 Volts with 15 Volts The board contains four precision voltage references and a ground autozero reference for use in calibration These provide considerable flexibility in obtaining accurate calibration for any desired ADC range and gain combination when compared to fixed hardware potentiometers for offset and gain calibration of the ADC and PGA The calibration signals are selected multiplexed into the PGA like any other input channel LOGIC POWER INTERFACE The logic interface to the carrier board is made through connector P1 Not all of the IP logic P1 pin functions are used refer to Table 2 6 P1 also provides 5V and 12V to power the module A programmable logic device installed on the IP Module provides the control signals required to operate the board It decodes the selected addresses in the I O and ID spaces and produces the chip selects control signals and timing required by the ADC control register and ID PROM as well as the acknowledgement signal required by the carrier board per the IP specification The control logic also provides
15. supplies are normally supplied through P1 logic interface connector Optionally jumper selectable on the IP the user may connect external 15 volt supplies through the field I O interface connector P2 ANALOG INPUTS Input Channels Field Access 40 Single ended or 20 Differential Ended Input Signal Type Voltage Non isolated Input Ranges jumper selectable Bipolar 5 to 5 Volts See Note 2 Bipolar 10 to 10 Volts See Notes 2 amp 3 Unipolar 0 to 10 Volts See Notes 2 amp 3 Programmable Gains x1 X2 x4 x8 SERIES IP320 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD Input Overvoltage Protection 32 Volts with power applied 20 Volts unpowered Input Resistance 1000 Typical Input Bias Current 1nA Typical Common Mode Rejection Ratio 71dB Typical 60Hz CH to CH Rejection Ratio 71 dB Typical 60Hz Resistance to RFl Error is less than 0 25 of FSR with field strengths up to 10V m at frequencies of 27MHz 159MHz 460MHz A D Resolution 12 bits Data Format left justified Bipolar Bipolar Offset Binary BOB Unipolar Unipolar Straight Binary USB No Missing Codes No Missing Codes Over Temperature 12 bits A D Integral Linearity Error 31 2
16. table IN means that the pins are shorted together with a shorting clip OUT means that the clip has been removed Table 2 2 Power Supply Selections Pins of J3 and J4 Selection 1 amp 2 2 amp 3 182 2 amp 3 12 Volt Internal P1 15 Volt External P2 nternal and external supplies should not be mixed e g do not use 12 Volts with 15 Volts Control Register Configuration The control register is software configurable There are no hardware jumpers associated with it Control register bits are undefined at reset and must be programmed to the desired gain acquisition mode and channel configuration before starting ADC analog input acquisition refer to Section 3 for details inc 1 amp 2 2 amp 3 Analog Input Data Format The analog input data will appear as Unipolar Straight Binary USB for unipolar input ranges e g 0 to 10V it will appear as Bipolar Offset Binary BOB for bipolar input ranges e g 5 to 5V The following tables indicate the relationship between data format and the ideal analog input voltage to the module Table 2 3 Unipolar Straight Binary USB Analog Data Format Volts Hex For Table 2 3 it is assumed that the analog input range unipolar is 0 to 10 Volts i e with a programmable gain of 1 The 12 bit USB data is left justified within the 16 bit word The 4 Least Significant Bits LSB s are shown as zero in the table Actually they are undefined
17. 1 25 Note that the worst case non linearity error is 1 LSB the sum of the 1 2 LSB non linearities of the PGA and ADC Calibrated Performance Very accurate calibration of the IP320 can be accomplished by using calibration voltages present on the board The four voltages and the analog ground reference are used to determine the endpoints of a straight line which defines the analog input characteristic The calibration voltages are precisely adjusted at the factory to provide optimum performance as detailed in the following table LSB Ideal Value Volts Maximum Temperature Drift ppm C Maximum Tolerance 25 C Volts Calibration Signal 0 0000 0 0002 CA 1250 00 cas 06125 002 Worst case temperature drift is the sum of the 15 9 drift of the calibration voltage reference plus the 5 ppm 9C drift of the resistors in the voltage divider The calibration voltages are used with the auto zero signal to find two points that determine the straight line characteristic of the analog front end for a particular range The recommended calibration voltage selection for each range is summarized in the following table Table 3 4 Recommended Calib Voltages For Input Ranges Rec Low Rec High Calib Voltage Calib Voltage VoltcAr io Volte ar Volts Volts 7777
18. 2 INDUSTRIAL I O PACK aia atlas CABLE MODEL 5025 550 CABLE MODEL 5025 551 TERMINATION PANEL MODEL 5025 552 TRANSITION MODULE MODEL TRANS GP DRAWINGS 4501 433 IP320 JUMPER 5 15 4501 434 IP MECHANICAL ASSEMBLY 15 4501 435 ANALOG INPUT CONNECTION DIAGRAM 16 4501 436 BLOCK 0 16 4501 462 CABLE 5025 550 NON SHIELDED 4501 463 CABLE 5025 551 SHIELDED des 4501 464 TERMINATION PANEL 5025 552 TS 18 4501 465 TRANSITION MODULE TRANS GP 18 IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall System design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The Industrial I O Pack IP Series IP320 module is a 12 bit high density single size IP analog input board with the capability to monitor 20 differential or 40 singl
19. 59 1 2 3 48 49 59 K CONNECTORS MODEL TRANS GP ON PE BOARD MODULE SCHEMATIC 1 2 3 48 49 50 1 2 3 48 49 50 1 2 3 48 49 50 1 2 3 48 49 50 amp CONNECTORS ON FRONT PANEL TOP VIEW A B D lt 9 19 233 4 gt CH ie CM E 5 15 lt ilo o 110 3 35 80 0 il li B5 1 n E a EE 1 MED 2 HH Hn nnum siglo Hun 1111111111 ER T Y 0 78 19 8 ME 10 31 261 9 NOTE DIMENSIONS ARE IN INCHES MILLIMETERS TRANS GP MECHANICAL DIMENSIONS AND SIMPLIFIED SCHEMATIC 4501 465A TRANS GP 18
20. Acromag Series IP320 Industrial I O Pack 12 Bit High Density Analog Input Board USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 1994 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 484 F00J005 SERIES IP320 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents 1 0 GENERAL KEY ANALOG INPUT INDUSTRIAL I O PACK INTERFACE FEATURES SIGNAL INTERFACE PRODUCTS INDUSTRIAL I O PACK SOFTWARE LIBRARY 2 0 PREPARATION FOR UNPACKING AND INSPECTION CARD CAGE CONSIDERATIONS BOARD CONFIGURATI
21. LSB Maximum System Accuracy See Note 4 The maximum corrected i e calibrated error is summarized in the following table as the worst case accuracy possible for each range It is the sum of error components due to ADC quantization of the low and high calibration signals PGA and ADC linearity error and the absolute errors of the recommended calibration voltages at 259C Typical accuracies are significantly better Maximum Overall Calibrated Error 25 C Max Error Input Range ADC Range Gam vons 38855 25 5 2 1 21 0051 1251004125 4 25 000 062510 0 625 8 29 007 605 2 18 004 25025 4 21 005 1204255 8 25 006 00095 2 22 0055 0025 4 31 007 0075 1 8 510125 Settling Time 10V step 8 5uS to 0 01 of FSR A D Conversion Time 8 5uS Maximum includes S H acquisition A D Triggers External and Software Maximum Throughput Rate 100K conversions second Maximum with 10 uS per conversion read in pipelined mode Input Noise 0 2 LSB rms Typical with PGA Gain 1 Temperature Coefficient See specification of calibration voltages 13 Notes 2 Range assumes the programmable gain is equal to one Additional ranges are created with other gains Divide the listed range by the programmable ga
22. NAL CABLE SHIELDED WAS ES MX 55 2 2 Z 7 SSS PIN 1 50 PIN CONNECTOR 140 512 cn IS DESIGNATED WITH B RM EA RED INK FRONT VIEW NOTE SEVEN DIGIT PART NUMBERS ARE ACROMAG PART NUMBERS XXXX XXX C MODEL 5025 550 SIGNAL CABLE NON SHIELDED 4501 462 P2 P1 To AVME9630 9660 MODEL 5025 552 CARRIER BOARD 1 0 TERMINATION P3 OR P4 P5 PANEL x gt FEET TOP VIEW STRAIN 50 PIN RELIEF RIBBON CABLE BLACK LINE ON CABLE CONNECTOR 1004 534 2002 261 INDICATES PIN 50 1604 512 POLARIZING KEY PIN 1 STRAIN RELIEF 1004 534 4501 463A SERIES IP320 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD 1 2 3 4 5 6 7 9 10111213 1415 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 23 34 35 36 37 28 39 40 41 42 43 44 45 46 47 48 49 59 P1 12 54 5 6 7 8 9 10 111213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 59 MODEL 5 25 552 TERMINATION PANEL SCHEMATIC RAIL DIN MOUNTING SHOWN HERE TERMINATION DIN 50055 32mm 2 NUMBER 4001 0490 C 3 032 77 0 Lj RAIL DIN MOUNTING SHO
23. ON Default Hardware Jumper Configuration Analog Input Range Hardware Jumper Configuration Power Supply Hardware Jumper Configuration Control Register Analog Input Data Format CONNECTORS SENSO RRR IP Field Connector Analog Input Noise and Grounding Considerations External Trigger IP Logic Interface Connector P1 3 0 PROGRAMMING INFORMATION ADDRESS MAPS IP Identification Control 1 61 10 ADC Convert Command Read ADC Doata 2 eene ts PROGRAMMING CONSIDERATIONS Using the Separate ADC Convert amp Read Command Using External Conversion Triggers USE OF CALIBRATION SIGNALS Uncalibrated Performance Calibrated Performance 4 0 THEORY OF ANALOG INPUTS LOGIC INTERFACE 52 5 0 SERVICE AND SERVICE AND REPAIR PRELIMINARY SERVICE PROCEDURE 6 0 GENERAL SPECIFICATIONS ANALOG
24. TS M2 x 6 gt FLAT HEAD SCREW Lr L we SIDE OF IP MODULE THREADED M2 gt COMPONENT SIDE SPACER i OF CARRIER BOARD Es rur m 1 FRONT PANEL CONNECTOR og x M2 x 6 PAN HEAD SCREW P MODULE TO CARRIER ASSEMBLY PROCEDURE 1 THREADED SPACERS ARE PROVIDED IN TWO DIFFERENT LENGTHS THE SHORTER LENGTH IS FOR USE WITH AVME 9630 9660 CARRIER BOARDS SHOWN CHECK YOUR CARRIER BOARD TO DETERMINE ITS REQUIREMENTS MOUNTING HARDWARE PROVIDED MAY NOT BE COMPATIBLE WITH ALL TYPES OF CARRIER BOARDS 2 INSERT FLAT HEAD SCREWS ITEM A THROUGH SOLDER SIDE OF IP MODULE AND INTO HEX SPACERS ITEM B AND TIGHTEN 4 PLACES UNTIL HEX SPACER IS COMPLETELY SEATED 3 CAREFULLY ALIGN IP MODULE TO CARRIER BOARD AND PRESS TOGETHER UNTIL CONNECTORS AND SPACERS ARE SEATED 4 INSERT PAN HEAD SCREWS ITEM C THROUGH SOLDER SIDE OF CARRIER BOARD AND INTO HEX SPACERS ITEM B AND TIGHTEN 4 PLACES 15 BOARD MECHANICAL ASSEMBLY 4501 434 SERIES 20 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD P2
25. WN HERE DIN EN 50022 35mm 81 oogooogooogoooooooo2ooogooqo 200000000200 000000000000000 E E SCREWDRIVER SLOT FOR 5 315 REMOVAL FROM T RAIL 135 0 TOP VIEW SIDE VIEW NOTES DIMENSIONS ARE IN INCHES MILLIMETERS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 TOLERANCE 40 020 40 5 1 3 5 7 9 1113 15 17 19 2123 25 27 29 31 33 35 37 39 41 43 45 47 49 MODEL 5025 552 TERMINATION PANEL 2 203 58 5 4501 464 FRONT VIEW A B D 1 2 3 48 49 50 12 3 48 49 50 1 2 3 48 49
26. ans for accurate and reliable software calibration of the module SERIES 20 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD INDUSTRIAL I O PACK INTERFACE FEATURES High density Single size industry standard IP module footprint LocalID Each IP module has its own 8 bit ID PROM which is accessed via data transfers in the ID Read space e 16 bit I O Control register Read Write and A D Conversion Read are performed through 16 bit data transfer cycles in the IP module I O space e High Speed Access times for all data transfer cycles are described in terms of wait states typically O to 3 wait states are required for data transfer see specifications for detailed information e Wait Hold State Support This IP module supports both wait states generated by the IP module and Hold states generated by the carrier board SIGNAL INTERFACE PRODUCTS See Appendix for more information on compatible products This IP module will mate directly to any industry standard IP carrier board including Acromag AVME9630 9660 3U 6U non intelligent carrier boards Consult the documentation of your carrier board to ensure compatibility with the following interface products since all connections to field signals are made through the carrier board which passes them to the individual IP modules Cables Model 5025 551 X Shielded Cable or Model 5025 550 X Non Shielded Cable A Flat 50 pin cable wit
27. are calibration code The functions are written in the C programming language and can be linked into your application Refer to the README TXT file in the root directory and the INFO320 TXT file in the IP320 subdirectory on the diskette for details SERIES 20 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD Uncalibrated Performance The uncalibrated performance is affected by two primary error sources These are the Programmable Gain Amplifier PGA and the Analog to Digital Converter ADC The untrimmed PGA and ADC have the following performance PGA203KP 25 C Linearity Error is 0 012 Maximum i e 1 2 LSB Offset Error RTI is 0 5mV 5 Gain Typical 2mV 24 Gain Maximum This is summarized as Max Offset Max Offset Error RTI mV Error RTO mV 26 26 Gain Error is 0 05 typical 0 25 maximum for all gains ADC ADS774KE 25 C Linearity Error is 0 5 LSB Maximum Unipolar Offset Error is 2 LSB Maximum Bipolar Offset Error is 4 LSB Maximum Full Scale Calibration Error is 0 25 of span Maximum Table 3 3 summarizes the maximum uncalibrated error combining the PGA and the ADC errors Table 3 3 Maximum Overall Uncalibrated Error Max Offset Error LSB Gain Input Range Error Volts 5 to 5 1 2 5 to 5 15 4 2 amp 1 vi 1 1 1 62 4 1 8 2 4 1 8 8 0 to
28. ble Model 5025 550 x or 5025 551 x The P3 P6 connectors on the carrier board connect the field I O signals to the P2 connector on each of the Industrial I O Pack modules Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 50 correspond to P2 pins 1 50 on the Industrial I O Pack IP Each Industrial I O Pack IP has its own unique P2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG Connections to AVME9630 9660 P1 50 pin male header with strain relief ejectors Use Acromag 5025 550 x or 5025 551 x cable to connect panel to VME board Keep cable as short as possible to reduce noise and power loss Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 to 100 C Shipping Weight 1 25 pounds 0 6kg packed 14 TRANSITION MODULE MODEL TRANS GP Type Transition module for AVME9630 9660 boards Application To repeat field I O signals of IP modules A through D for rear exit from VME card cages This module is available for use card cages which provide rear exit for I O connections via transition module
29. e ended analog input channels The IP320 utilizes state of the art Surface Mounted Technology SMT to achieve its high channel density It offers a variety of features which make it an ideal choice for many industrial and Scientific applications as described below Model Operating Temperature Range IP320 0 to 70 C IP320E 40 to 85 C KEY ANALOG INPUT FEATURES e High Channel Count Monitors up to 20 differential or 40 single ended analog inputs acquisition mode and channels are Selected via a programmable control register Up to four units may be mounted on a carrier board providing up to 80 differential inputs or 160 single ended inputs in a single System slot 12 bit Accuracy Contains an enhanced 12 bit successive approximation Analog to Digital Converter ADC with an 8 5uS conversion time e High Speed A maximum system throughput rate of 100K samples per second can be obtained using the pipelined mode of operation Multiple Input Range Three hardware jumper selectable ranges capture both bipolar and unipolar voltage inputs 5 to 10 to 10V and 0 to 10V Programmable Gain Gains of 1 2 4 and 8 programmable via the control register 9 Software Hardware Trigger Input acquisition can be triggered via software or by an external hardware input for synchronization to external events Precision References On board high precision voltage references provide the me
30. ed Replacement of the module with one that is known to work correctly is a good technique to isolate a faulty module CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS Acromag s Applications Engineers can provide further technical assistance if required When needed complete repair services are also available from Acromag 6 0 SPECIFICATIONS GENERAL SPECIFICATIONS Operating 0 to 70 C 40 to 85 C E Version Relative Humidity 5 95 non condensing Storage Temperature 40 to 100 C ET 55 to 105 C E Version Single Industrial I O Pack Module 9 900 99 0 mm 1 800 in 45 7 mm 0 062 in 1 59 mm Max Component Height 0 314 in 7 97 mm Connectors P1 IP Logic Interface 50 pin female receptacle header AMP 173279 3 or equivalent P2 Field l O 50 pin female receptacle header AMP 173279 3 or equivalent Power 5 Volts 5 270mA Typical 350mA Maximum 12 Volts 5 from P1 or 12mA Typical 20mA Maximum 15 Volts 5 from P2 See Note 1 12 Volts 5 from P1 or 8mA Typical 20mA Maximum 15 Volts 5 from P2 See Note 1 Non Isolated Logic and field commons have a direct electrical connection Note 1 The 12 volt power
31. h female connectors at both ends for connecting AVME9630 9660 or other compatible carrier boards to Model 5025 552 termination panels The shielded cable is recommended for optimum performance with precision analog I O applications while the unshielded cable is recommended for digital I O Termination Panel Model 5025 552 DIN rail mountable panel provides 50 screw terminals for universal field I O termination Connects to Acromag AVME9630 9660 or other compatible carrier boards via flat 50 pin ribbon cable Model 5025 550 or 5025 551 X Transition Module Model TRANS GP This module repeats field 1 connections of IP modules A through D for rear exit from the card cage It is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to AVME9630 9660 boards via a flat 50 pin ribbon cable within the card cage cable Model 5025 550 X or 5025 551 X INDUSTRIAL I O PACK SOFTWARE LIBRARY Acromag provides an Industrial Pack Software Library diskette Model IPSW LIB M03 MSDOS format to simplify communication with the board AII functions are written in the C programming language and can be linked to your application Refer to the
32. in to determine the actual input range Input signal ranges may actually fall short of reaching the specified endpoints due to hardware limitations For example if an input may reach zero volts or less a bipolar input range should be selected 3 These ranges can only be achieved with 15 Volt external power supplies The input ranges will be clipped if 12 Volt supplies are used typically to 9 Volt maximum inputs 4 Follow the input connection recommendations of Section 2 because input noise and non ideal grounds can degrade overall System accuracy For critical applications multiple input samples can be averaged to improve performance Accuracy is specified for the software conversion command Use of the external hardware trigger input with software polling may degrade accuracy Accuracy versus temperature depends on the temperature coefficient of the calibration voltage Ideal Programmable Calibration Voltages follow Maximum Value Tolerance Calib Signal Volts 25 C Volts 0 0000 30 0002 Temperature Drift ppm C 0 CA2 1220 s0004 ca 0615 0002 Worst case temperature drift is the sum of the 15 9 drift of the calibration voltage reference plus the 5 ppm C drift of the resistors in the voltage divider INDUSTRIAL I O PACK COMPLIANCE Specification This module meets or exceeds all written Industrial Pack specifications per
33. isition It must not stay low for more than 5uS or additional unwanted acquisitions may be triggered See Section 3 for programming information IP Logic Interface Connector P1 The pin assignments of P1 are standard for all IP modules according to the Industrial Pack Specification see Table 2 6 Note that the IP320 does not utilize all of the logic signals defined for the P1 connector Logic lines NOT USED used by this model are indicated in BOLD ITALICS Table 2 6 Standard Logic Interface Connections P1 Pin Description Number Pin Description Number 27 Rw 28 IDSEL 29 DMARego 30 MEMSEL 91 DMAReqi 92 33 DMAck0 54 Do 210 55 RESERVED 36 7 13 DwAEnd 38 9 3 39 ERROR 40 A A 42 INTReqi 44 20 5 45 STROBE 46 RESERVED Asterisk is used to indicate an active low signal BOLD ITALIC Logic Lines are NOT USED by this IP Model SERIES 20 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD P1 of the IP module provides the logic interface to the mating connector on the carrier board see Table 2 6 This connector is a 50 pin female receptacle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integ
34. nnels and can be used when a large number of input channels come from the same location e g printed circuit board The channel density doubles when using single ended inputs and this a powerful incentive for their use However caution must be exercised since the single sense lead references all channels to the same common which will induce noise and offset if they are different The 20 is non isolated since there is electrical continuity between the logic and field I O grounds As such the field I O connections are not isolated from the carrier board and backplane Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections This is particularly important for analog inputs when a high level of accuracy resolution is needed 12 bits or more Contact your Acromag representative for information on our many isolated signal conditioning products that could be used to interface to the IP320 input module External Trigger Input The external trigger signal on P2 is an active low input which may be used for synchronizing the ADC conversion of analog inputs from several IP modules to external events The external trigger must be a 5 Volt logic TTL compatible debounced signal referenced to analog common The conversion is triggered on the falling edge of a normally high signal The trigger pulse must be low for a minimum of 250nS to guarantee acqu
35. o 13 Delay to allow for input settling Execute ADC Convert Command Base 10H 15 Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word This data represents the uncorrected Count Actual term in equation 1 Since all parameters on the right hand side of equation 1 are known Calculate the calibrated value Corrected Count This is the desired corrected value for input channel 39 16 Repeat steps 12 15 to re measure channel 39 s data as desired Error checking should be performed on the Corrected Count value to make sure that calculated values below 0 or above 4095 are restricted to those end points Note that the software calibration cannot recover signals near the end points of each range which are clipped off due to the uncalibrated hardware e g PGA and ADC The maximum corrected i e calibrated error is summarized in Table 3 6 as the worst case accuracy possible for each range It is the sum of error components due to ADC quantization of the low and high calibration signals PGA and ADC linearity error and the absolute errors of the recommended calibration voltages at 259C Typical accuracies are significantly better 11 Table 3 6 Maximum Overall Calibrated Error 25 C Input Range ADC Range Max Error ote Gam ote 16869 25100425 2 21 005 1250 15 4 25 006 06251040625 8 29 007 St 2 18 004
36. of data are left justified within the 16 bit word D16 The four LSB s are not driven by the ADC and are undefined typically passive pull ups on the carrier board will cause undriven bits to read high Data format is either Bipolar Offset Binary BOB or Unipolar Straight Binary USB see Section 2 for details MSB 15 14 13 12 11 10 9 X means Don t Care the bit value does not matter PROGRAMMING CONSIDERATIONS FOR ACQUIRING ANALOG INPUTS The 20 provides two different methods of analog input acquisition to give the user maximum flexibility for each application The following sections describe the features of each and how to best use them Using the Separate ADC Convert and Read Commands Use of the separate convert and read commands is a straighforward and accurate way to acquire data This method is useful for most applications Programming Example Separate ADC Convert amp Read NOTE For this example it is assumed that the external trigger input is NOT being used to trigger conversions 1 Write to the control register to configure the acquisition mode gain and channel selections Delay to allow for input settling Execute the ADC Convert command Write to the control register to configure the acquisition mode gain and channel selections for the next acquisition if they are different This may be done while the conversion is in progress because the ADC is in the hold mode 5 The ADC c
37. om Tables 3 4 amp 3 5 several calibration parameters can be determined Gain 1 From Table 3 4 Volto At 4 9000 volts CALO From Table 3 4 VolCALLO 0 0000 volts Auto Zero From Table 3 4 Ideal_Volt_Span 20 0000 volts From Table 3 5 Ideal_Zero 10 0000 volts From Table 3 5 The calibration parameters jjj and Counte ay remain to be determined before uncorrected input channel data can be taken and corrected 10 1 To prepare to measure write to the Control Register Base 00H to setup the auto zero acquisition mode and PGA gain 1 by writing 0300H Note that not used and don t care bits are set to zero Delay to allow for input settling Execute ADC Convert Command Base 10H Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word 5 Repeat steps 3 and 4 several times e g 16 and take the average of the ADC results Save this number as CountcA 6 To prepare to measure Countg write to the Control Register Q Base 00H to setup the CALO acquisition mode and PGA gain 1 by writing 0014H Note that not used bits are set to zero 3 Count_Actual Actual Uncorrected ADC Data For 7 Delay to allow for input settling Input Being Measured 8 Execute ADC Convert Command Base 10H Ideal_Zero Ideal ADC Input For Zero Count 9 Execute Read ADC Data Command
38. onversion takes several microseconds This time can be put to use for other purposes e g calibration of ADC channel data 3 6 Read ADC Data if the conversion is still in progress the read command will generate wait states until it can deliver the data 7 Repeat steps 3 6 as required to acquire additional analog input samples Note that the input settling delay does not have to be inserted since writing to the control register to configure for the next acquisition immediately after initiating the previous conversion will allow the input to adequately settle before the next conversion is started The overlapping of these tasks with the ADC conversion cycle is what gives rise to pipelined operation and maximum system throughput Using External Conversion Triggers External hardware triggers are generated by the user via an external TTL compatible input through the field I O connector see Section 2 make sure that all pertinent voltage and pulse width constraints are met The conversion is initiated on the falling edge of the external trigger signal This type of conversion triggering is useful for synchronizing the ADC conversion of analog inputs e g several IP320 s to external events Precise time intervals between conversions can be achieved with an external timing device Programming Example External Conversion Trigger NOTE For this example it is assumed that the external trigger input is being used to
39. or represents the uncorrected Count Actual term in equation 1 each active input range should be determined at startup and updated Since all parameters on the right hand side of equation 1 are periodically e g once an hour or more often if ambient known Calculate the calibrated value Corrected Count This temperatures change to obtain the best accuracy Note that several is the desired corrected value for input channel 0 readings e g 16 of the calibration parameters should be taken via 16 Repeat steps 12 15 to re measure channel zero s data as desired Calibration Programming Example 2 Assume that the input range is 0 to 1 25 volts Channel 39 is connected single ended and corrected input channel data is desired From Tables 3 4 and 3 5 several calibration parameters can be determined Gain 8 From Table 3 4 Volte A 1 2250 volts CAL2 From Table 3 4 Volto Ai 0 0 6125 volts CAL3 From Table 3 4 Ideal Volt Span 10 0000 volts From Table 3 5 Ideal Zero 0 0000 volts From Table 3 5 The calibration parameters jjj and CountcaA remain to be determined before uncorrected input channel data can be taken and corrected SERIES 20 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD 1 To prepare to measure write to the Control Register Base 00H to setup the CAL3 acquisition mode and PGA gain 8 by writing 00D7H Note that not used bit
40. power supplies are used sourced from P1 connector Programmable software control register bits are undefined at reset The control register should be programmed to the desired gain mode and channel configuration before starting ADC analog input acquisition Analog Input Range Hardware Jumper Configuration The ADC input range is programmed via hardware jumpers J1 and J2 J1 controls the input voltage span J2 controls the selection of unipolar or bipolar input ranges The configuration of the jumpers for the different ranges is shown in the following table IN means that the pins are shorted together with a shorting clip OUT means that the clip has been removed Table 2 1 Analog Input mange Pins of J1 72 Desired Required J1 Reqd B 1 amp 2 ADC Input Input Span Input Pins Range VDC Volts 2 amp 3 Type Out 6 1 Out Out These ranges can only be achieved with 15V external power supplies The input ranges will be clipped if 12V supplies are used typically to 9 V maximum inputs Power Supply Hardware Jumper Configuration The selection of internal or external analog power supplies is accomplished via hardware jumpers J3 and J4 J3 J4 controls the selection of either the internal 12 12 Volt supply sourced from P1 connector or the external 15 15 Volt supply sourced from the P2 connector The configuration of the jumpers for the different supplies is shown in the following
41. rcuit board 0 063 inches thick Operating Temperature 40 to 85 C Storage Temperature 55 C to 105 C Shipping Weight 1 25 pounds 0 6Kg packed SERIES 20 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD LOGIC INTERFACE 170 INTERFACE 1 2 1122 1 800 020 J3 1 5 Y E id gt 9 104 COMPONENT SIDE VIEW 0 2125 3 900 0 020 gt ANALOG INPUT RANGE SELECTION PINS J1 AND J2 DESIRED REQUIRED REQUIRED ADC INPUT INPUT 1 INPUT J2 2 RANGE SPAN 1 amp 2 2 amp 3 TYPE 1 amp 2 2 amp 3 VOLTS VOLTS 5 10 5 18 IN OUT BIPOLAR OUT IN 10 TO 10 28 OUT IN BIPOLAR OUT IN 10 18 OUT UNIPOLAR IN OUT THESE RANGES CAN ONLY BE ACHIEVED WITH 15 VOLT EXTERNAL POWER SUPPLIES THE INPUT RANGES WILL BE CLIPPED IF 12 VOLT SUPPLIES ARE USED TYPICALLY TO 9 VOLT MAXIMUM INPUTS POWER SUPPLY SELECTIONS PINS OF J3 AND J4 POWER SUPPLY 3 J3 4 4 SELECTION 1 amp 2 2 amp 3 1 amp 2 2 amp 3 12 VOLT INTERNAL P1 OUT IN OUT IN 15 VOLT EXTERNAL P2 IN OUT IN OUT INTERNAL AND EXTERNAL SUPPLIES SHOULD NOT BE MIXED E G DO NOT USE 12 VOLTS WITH 15 VOL
42. revision 0 7 1 Electrical Mechanical Interface Single Size IP Module IP Data Transfer Cycle Types Supported Input Output IOSel 16 bit word read of 12 bit left justified ADC data 16 bit read write of control register conversion request write ID Read IDSel 32x8 ID PROM read on DO D7 Access Times 8MHz Clock ID PROM Read 0 wait states 250ns cycle Control Register Read 0 wait states 250ns cycle Control Register Write 1 wait state 375ns cycle Conversion Request Write 0 wait states 250ns cycle Read ADC Data Note 5 3 wait states 625ns cycle Note 5 The 3 wait states specified assumes that the previous conversion has been completed and that data is available to be read If a conversion is in progress the command will institute wait states until the data can be delivered This could take up to 8 5 5 maximum SERIES IP320 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD APPENDIX CABLE MODEL 5025 550 x Non Shielded MODEL 5025 551 x Shielded Type Flat Ribbon Cable 50 wires female connectors at both ends The x suffix designates the length in feet 12 feet maximum Choose shielded or unshielded cable according to model number The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O application
43. rity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the IP module to provide additional stability for harsh environments see Drawing 4501 434 for assembly details Field and logic side connectors are keyed to avoid incorrect assembly 3 0 PROGRAMMING INFORMATION ADDRESS MAPS This board is addressable in the Industrial Pack I O space to control the acquistion of analog inputs from the field The I O space may be as large as 64 16 bit words 128 bytes using address lines A1 A6 but the IP320 only uses a portion of this space The I O space address map for the IP320 is shown in Table 3 1 Note the base address for the IP module I O space see your carrier board instructions must be added to the addresses shown to properly access the I O space All accesses are performed on a 16 bit word basis DO D15 Table 3 1 IP320 Space Address Memory Map Base Even Byte Odd Byte Address D15 08 07 D Hex R W Control Register Repeated Control Register 10 W ADC Convert Command 4 Repeated ADC Convert Command 20 R Read ADC Data 22 Repeated Read ADC Data Not Used Not Used 7E Notes Table 3 1 1 Registers appear in multiple locations in the memory map because of simplified address decoding these locations can be ignored 2 The IP will not respond to addresses that Not Used 00 02 0 12 1 ALO wo 1 1
44. s Application Used to connect Model 5025 552 termination panel to the AVME9630 9660 non intelligent carrier board P3 P6 connectors Both have 50 pin connectors Length Last field of part number designates length in feet user specified 12 feet maximum It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 wire flat ribbon cable 28 gage Non Shielded cable model uses Acromag Part 2002 211 3M Type C3365 50 or equivalent Shielded cable model uses Acromag Part 2002 261 3M Type 3476 50 or equivalent Headers Both Ends 50 pin female header with strain relief Header Acromag Part 1004 512 3M 3425 6600 or equivalent Strain Relief Acromag Part 1004 534 3M Type 3448 3050 or equivalent Keying Headers at both ends have polarizing key to prevent improper installation Schematic and Physical Attributes For Non Shielded cable model see Drawing 4501 462 For Shielded cable model see Drawing 4501 463 Shipping Weight 1 0 pound 0 5Kg packed TERMINATION PANEL MODEL 5025 552 Type Termination Panel For AVME9630 9660 Boards Application To connect field I O signals to the Industrial I O Pack IP Termination Panel Acromag Part 4001 040 Phoenix Contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field I O signals and connects to the AVME9630 9660 3U 6U non intelligent carrier boards P3 P6 connectors only via a flat ribbon ca
45. s are set to zero Delay to allow for input settling Execute ADC Convert Command Base 10H Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word 5 Repeat steps 3 and 4 several times e g 16 and take the average of the ADC results Save this number as Countca o 6 To prepare to measure Count A write to the Control Register Q Base 00H to setup the CAL2 acquisition mode and PGA gain 8 by writing OOD6H Note that not used bits are set to zero 3 7 Delay to allow for input settling 8 Execute ADC Convert Command Base 10H 9 Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word 10 Repeat steps 8 and 9 several times e g 16 and take the average of the ADC results Save this number as Counto 11 Calculate m actual_slope from equation 2 since all parameters are known It is now possible to correct input channel data from any input channel using the same input range i e 0 to 1 25 volts with a PGA gain 8 Repeat steps 1 11 periodically to re measure the calibration parameters Countc and Count aj as required 12 To prepare to measure channel 39 single ended write to the Control Register Base 00H to setup the single ended input channel 39 acquisition mode and PGA gain 8 by writing 02D3H Note that not used bits are set to zer
46. s transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to Acromag termination panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 Schematic and Physical Attributes See Drawing 4501 465 Field Wiring 50 pin header male connectors 3M 3433 D303 or equivalent employing long ejector latches and 30 micron gold the mating area per MIL G 45204 Type Grade C Connects to Acromag termination panel 5025 552 from the rear of the card cage or to AVME9630 9660 boards within card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Connections to AVME9630 9660 50 pin header male connectors 8M 3433 1302 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type Il Grade C Connects to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Mounting Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Printed Circuit Board Military grade FR 4 epoxy glass ci
47. selected channel s and inputs or and sense and outputs a single ended voltage proportional to it The gain can be 1 2 4 or 8 and is selected through the control register The output of the PGA feeds the Analog to Digital Converter ADC The ADC is a state of the art 12 bit successive approximation converter with a built in Sample and Hold S H circuit The S H goes into the hold mode when a conversion is initiated This maintains the selected channel s voltage constant until the ADC has accurately digitized the input Then it returns to the sample mode to acquire the next channel Once a conversion has been started the control register can be updated for the next channel This allows the input to settle for the next channel while the previous channel is converting which gives rise to the pipelined mode of operation and maximum system throughput SERIES 20 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG INPUT BOARD Hardware jumpers J1 and J2 control the range selection for the ADC 5 to 5 10 to 10 or 0 to 10 Volts as detailed in Section 2 Jumper selection should be made prior to powering the unit Thus all channels will use the same ADC range However the analog input range can vary on an individual channel basis depending on the programmable gain selection The logic interface provides 12 Volt supplies to the analog circuitry The 10 to 10 and 0 to 10 Volt ADC ranges will be clipped if these supplies
48. the trigger to start an ADC conversion This may be initiated by software commands or by a user generated external trigger input from connector P2 see Sections 2 and 3 for details The ID PROM read only installed on the IP module provides the identification for the individual module per the IP specification The programmable control register is read write and has been described with the analog input circuitry The ID PROM control register and ADC data are all accessed through the 16 bit data bus interface to the carrier board 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment 12 Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configur
49. trigger conversions 1 Write to the control register to setup the acquisition mode gain and channel selections 2 Delay to allow for input settling 3 Poll Bit 15 CTRIG in the control register to determine when an ADC conversion has been triggered this assumes some prior knowledge in the application program that a hardware external trigger will occur for a particular channel s conversion 4 Read ADC Data if the conversion is still in progress the read command will generate wait states until it can deliver the data The Read ADC Data command will reset the CTRIG bit in the control register to prepare for the next external trigger 5 Repeat steps 3 4 for acquisition of the same input Otherwise repeat steps 1 4 as required USE OF CALIBRATION SIGNALS Reference signals for analog input calibration have been provided to improve the accuracy over the uncalibrated state The use of software calibration allows the elimination of hardware calibration potentiometers traditionally used in precision analog front ends comparison of the uncalibrated and software calibrated performance is shown to illustrate the importance of the software calibration Software calibration uses some fairly complex equations Acromag provides you with the Industrial I O Pack Software Library diskette to make communication with the board and calibration easy It relieves you from having to turn the equations of the following sections into debugged softw
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