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78K0R/LH3 Sample Program(Sound Output) Playing Back Sound

1. 01111 ADDDDDDDDDDD 10000 DDDDDDDDDDDD dl Az Be sure to set 000 OAC 1 0 Operational amplifier AMP1 disable 98 Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST OAC 2 0 Operational amplifier AMP2 disable j pov D DCUM PME Module fn_InitDac Es Description Setting of D A Converter parameter al return A A A Ss a a tt a ere static void fn InitDac void DAM 0b01000101 D A Converter Mode Register DAMDO D A converter operation mode selection es DAMD1 D A converter operation mode selection 0 Normal mode 1 Real time output mode L 7 pz 4 DARESO D A converter resolution selection 4 DARES1 D A converter resolution selection JA 0 8 bit y 1 12 bit 3 D A conversion operation Control channel 0 D A conversion operation Control channel 1 0 Stops conversion operation JE 1 Enables conversion operation 1 R4 f e Positive reference voltage supply selection of D A converter 0 AVDD1 power supply for D A converter analog circuit 1 VREFOUT voltage reference output AVREFP external voltage reference input el Reference voltage supply negative side is AVSS positive side is AVREFP gt
2. NEC ELECTRONICS CONFIDENTIAL AND PROPRIETARY All rights reserved by NEC Electronics Corporation This program must be used solely for the purpose for which it was furnished by NEC Electronics Corporation No part of this program may be reproduced or disclosed to others in any form without the prior written permission of NEC Electronics Corporation Use of copyright notice dose not evidence publication of the program Seca a Rr ie ce a acs ak ese dm on e rude Ri week sc RE ume qu open esc Cag sens AA a a ats CIA Sa pnb E es ums sn e E AA ERA pragma directive for CC78K0 E OT A A A a AURI PEU Nl S SD Pr RIP REOPERUP a a Re ISP ed E rd ESTIS pragma SFR pragma DI pragma El pragma HALT pragma NOP KE So A ECT dim a a e SE NE E TEN E ee th ee eal to E rete quer Include files Ted sia sn S pd Sch Ke Me ced edt a a ld Pe Dan ls sc c nck sed Woh em RAE PUER A IU Inr Mer aS poe qe gmk S RUP Nees ete PIRE CU EPIS Tek RE A POCO IM er es Fa a ee Re Pe re rn ER ah CR Rr ee Eee Ze Function prototyps dl p e E E I ee Nn A A a et Pr e static void fn _InitPort void Setting of I O ports static void fn_InitLvi void Low voltage detection static void fn_InitKr void Setting of Key Interrupt Function static void fn_InitTau0 void Setting of Timer array unit 0 static void fn_InitVr void Setting of Voltage r
3. Disable all interrupts Application Note U20028EJ1VOAN 49 50 APPENDIX A PROGRAM LIST DI Set register bank SEL RBO Use register bank 0 A Set stack pointer MOVW SP LOWW STACKTOP A Initialization of port A CALL STNITPORT Low voltage detection CALL SITINITLVI Ensures 2 7 V to VDD E Initialization of clock MOV CMC 01000011B Clock Operation Mode Control Register il control of high speed system clock oscillation frequency sll ii 0 2 MHz lt fMX lt 10 MHz III 1 10 MHz lt MX lt 20 MHz XT1 oscillator oscillation mode selection 1111 0 0 Low consumption oscillation 11 PI 0 1 Normal oscillation EHE 1 x Super low consumption oscillation LLL x don t care 7 Be sure to set 0 Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST P 4 1 Subsystem clock pin operation mode 2 XT1 P123 pin and XT2 P124 pin 0 1 Input port mode 2 Input port E 1 1 XT1 oscillation mode 2 Crystal resonator connection eo IEEE Be sure to set 0 pta 1 EXCLK OSCSEL High speed system clock pin operation mode 2 X1 P121 pin 3 X2 EXCLK P122 pin 0 0 1 Input port mode 2 3 Input port 01 1 X1 oscillation mode 21 3 Crystal ceramic resonator connection 1 0 1 Input port mode i 2 3 Input port 11 1
4. Copyright C NEC Electronics Corporation 2006 NEC ELECTRONICS CONFIDENTIAL AND PROPRIETARY All rights reserved by NEC Electronics Corporation This program must be used solely for the purpose for which it was furnished by NEC Electronics Corporation No part of this program may be reproduced or disclosed to others in any form without the prior written permission of NEC Electronics Corporation Use of copyright notice dose not evidence publication of the program EXTRN adpcm init ADPCM process initialize EXTRN adpcm 132 dec ADPCM data decode EXTRN TPLAYDATA Sound data EXTRN TPLAYSIZE Size of sound data TVCT1CSEG AT 000000H DW IRESET 00H RESET POC LVI WDT TRAP TVCT2CSEG AT 000004H DW IRESET 04H INTWDTI DW IRESET 06H INTLVI DW IRESET 08H INTPO Application Note U20028EJ1VOAN 47 48 DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET
5. parameter E return y E cM A A RM AM PUDE ED MEUM qo POL LCS OO ADR Bd static void fn InitLvi void unsigned char ucCounter Counter Setting of Low Voltage Detector LVIMK 1 Disable LVI interrupt VISEL 0 Detects level of VDD LVIS 0b00001001 Low Voltage Detection Level Select Register Detection lev 1 7 0 0 0 0 VLVIO 4 22 V 0 0 0 1 VLVI1 4 07 V 0010 VLVI2 3 92 V Application Note U20028EJ1VOAN 87 APPENDIX A PROGRAM LIST 0 011 VLVI3 3 76 V 0 1 0 0 VLVIA 3 61 V 0 1 0 1 VLVI5 3 45 V 0 1 1 0 VLVIG 3 30 V 0111 VLVI7 3 15 V 1000 VLVI8 2 99 V II 1001 VLVI9 2 84 V III 1010 VLVI10 2 68 V 1 1 11 1011 VLVI11 2 53 V 1111 1100 VLVI12 2 38 V 1111 1101 VLVI13 2 22 V 11210 VLVI14 2 07 v I 1111 VLVI15 1 91 V 7d AN cia Be sure to set 0000 LVIMD 0 Generates an internal interrupt signal when detect the low voltage LVION 1 Enables low voltage detection operation Software to wait for the operation stabilization time over 10 us for ucCounter 0 ucCounter lt 4 ucCounter NOP Wait for VDD to become VLVI or more while LVIF NOP LVION 0
6. x don t care Application Note U20028EJ1VOAN 29 CHAPTER 4 SETTING METHODS 2 D A conversion value setting register WO DACSWO This register is used to set an analog voltage value to be output to the ANOO pin when the D A converter is used DACSWO and DACSW1 can be set by a 16 bit memory manipulation instruction Figure 4 13 Format of D A Conversion Value Setting Register WO DACSWO DACS DACS DACS DACS DACS DACS DACS DACS DACS DACS DACS DACS wo11 W010 WO9 WO08 WO07 WO06 WO5 WO4 Wo3 wo2 wo1 woo SL a B uM FFF59H FFF58H Caution Rewriting D A conversion value setting register Wn DACSWn during A D conversion is prohibited when both the positive reference voltage of the A D converter ADrerP and the positive reference voltage of the D A converter DAnerP are the voltage reference output Vngrour VRSEL 1 and DAREF 1 Rewrite it when conversion operation is stopped ADCS 0 Remarks 1 The relations between the resolutions and analog output voltages Vanon of the D A converter are as follows e 8 bit resolution DARESn 0 Vanon Reference voltage for D A converter x DACSWn7 to DACSWn0 256 e 12 bit resolution DARESn 1 VaNon Reference voltage for D A converter x DACSWn11 to DACSWn0 4096 2 n 0 1 30 Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS 4 6 Software Coding Examples The settings to be specified for timer array unit 0 voltage reference ope
7. 1 Onecountmode Counting down impossible a 3 o o Capture amp one oount made counting up Posse CIS001 CIS000 Selection of valid edge of TIOO pin input signal fsue 2 fsus 4 or INTRTC1 the timer input used with channel 0 is selected by using TISO register 0o o Fating edge o 1 Rising edge 1 Both edges when low level width is measured Start trigger Falling edge Capture trigger Rising edge Both edges when high level width is measured Start trigger Rising edge Capture trigger Falling edge If both the edges are specified when the value of the STSO02 to STS000 bits is other than 010B set the CIS001 and CIS000 bits to 10B Note f the start trigger TS00 1 is issued during operation the counter is cleared an interrupt is generated and recounting is started Caution Be sure to clear bits 14 13 5 and 4 to 0 Remark The values written in red in the above figure are specified in this sample program 18 Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS Figure 4 4 Format of Timer Mode Register 04 TMR04 1 2 CKS CCS MAST STS STS STS CIS CIS MD MD MD MD 04 04 ERO4 042 041 040 041 040 043 042 041 040 STS042 STS041 STS040 Setting of start trigger or capture trigger of channel 4 0 0 Only software trigger start is valid other trigger sources are unselected 1 Valid edge of Tlpq pin input signal fsus 2 fsus 4 or INTRTC1 is used as
8. 720 2 Yeoksam Dong Kangnam ku Seoul 135 080 Korea Tel 02 558 3737 http www kr necel com G0706
9. AVREFP Reference voltage supply negative side is AVREFM positive side is VREFOUT VREFOUT ERES eic eee Be sure to set 0 DACSWO 0x0800 Set initial data Application Note U20028EJ1VOAN 99 APPENDIX A PROGRAM LIST 22S See SOS QR Seo e See A eee eo E Module fn PlayDac Description Play PCM data by D A eL PA parameter T return a A d e mis mr static void fn_PlayDac void 100 unsigned char pucPlayData Start playing addr unsigned short ushPlayCount Output data counter unsigned short ushData Decompression data unsigned short loop Waiting counter A A A sony Sank eg es des eas ls A A A JS Prepare for playing A A it a de Se n Cm set play data addr and size pucPlayData aPlayData Set start playing address adpcm_init ushAdpcmWork ADPCM process Initialization Operational amplifier setting OAC 1 1 Operational amplifier AMP1 enable OAC 2 1 Operational amplifier AMP2 enable Use software to wait until the operational amplifier stabilizes for loop 40 loop gt 0 loop NOP D A converter setting DACEO 1 D A converter CHO enable TAUO CH4 setting for output timing TMIFO4 0 Clear interrupt request flag TSOL 4 1 Start TAUO CH4 FRERERRARA RARE ERE RE RAR ARRE ko kc kc ko RARAS A
10. NOP BF TMIFO4 SJPDAC230 The output to be completed No CLR1 TMIFO4 Clear interrupt request flag ckckck ck ck ck ck ck ck ck ck ck ck k ck kk kk kk H Play high 4 bits Ckckck ck ckck ck ck ck ck ck ck ck k ck kk kk kk Decompression of ADPCM data high 4 bits 16 bits MOVW AX LOWW RADPCMWORK Set work area for _adpcm_132_dec PUSH AX MOV A ES HL Get compressed data SHR A 4 MOV X A CLRB A CLR1 DIVMODE Set multiplication mode for _adpcm_132_dec CALL adpcm 132 dec Decompression of PCM data POP AX Pop argument MOVW AX BC Get decompression data Adjust play data ADDW AX 8000H Adjust sign SHRW AX 16 12 Right align data JPDAC270 MOVW DACSWO AX Set play data Waiting for the output to be completed JPDAC280 NOP BF TMIFO4 SJPDAC280 The output to be completed No CLR1 TMIFO4 Clear interrupt request flag INCW RPLAYCOUNT Update play counter INCW HL Next play data BR JPDAC200 Application Note U20028EJ1VOAN 75 JPDAC300 APPENDIX A PROGRAM LIST LR1 S e CLR1 C LR1 JPDAC900 end 76 RET TTOL 4 DACEO OAC 1 OAC 2 Stop TAUO CHA D A converter CHO disable Operational amplifier AMP1 disable Operational amplifier AMP2 disable Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST main c C language version Copyright C NEC Electronics Corporation 2006
11. Real time output mode 1 DARESO D A converter resolution selection DARES1 D A converter resolution selection 0 8 bit sll J 1 12 bit D A conversion operation Control channel 0 D A conversion operation Control channel 1 0 Stops conversion operation 1 Enables conversion operation A Positive reference voltage supply selection of D A 0 AVDD1 power supply for D A converter analog circuit Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST reference input is AVREFP gt AVREFP H is VREFOUT VREFOUT jt Be sure to set 0 MOVW DACSWO 0800H Set initial data RET Module SPLAYDAC Description Play PCM data by D A i parameter A return A 1 VREFOUT voltage reference output AVREFP external voltage Reference voltage supply negative side is AVSS positive side Reference voltage supply negative side is AVREFM positive side MOVW HL LOWW TPLAYDATA Set start playing addr low 16 bits MOV ES HIGHW TPLAYDATA Set start playing addr high 4 bits JPDAC100 MOVW AX LOWW RADPCMWORK CALL adpcm init ADPCM process Initialization Operational amplifier setting SET1 OAC 1 Operational amplifier AMP1 enable SET1 OAC 2 Operational amplifier AMP2 enable 1 MOV B 80 JPDAC150 DEC B BNZ JPD
12. data_playrom c which must be externally referenced To use the ADPCMlibrary adpcmsp h must be included by include static void fn_PlayDac void unsigned char pucPlayData Start playing addr unsigned short ushPlayCount Output data counter unsigned short ushData Decompression data unsigned Waiting counter Set play data addr and size pucPlayData aPlayData Set start playing address adpcm init ushAdpcmWork ADPCM process Initialization operational amplifier setting OAC 1 1 Operational amplifier AMP1 enable OAC 2 1 Operational amplifier AMP2 enable Use software to wait until the operational amplifier stabilizes 20 us max for loop 40 loop gt 0 loop NOP D A converter setting DACEO 1 D A converter CHO enable TAUO CHA setting for output timing TMIF04 0 Clear interrupt request flag TSOL a ie 7 Start TAUO CHA 7 Application Note U20028EJ1VOAN 43 CHAPTER 4 SETTING METHODS FRERERREERE RARE RERERA RAR ERE RA E RA EK EK J FRERERERR ERE RAE R RAR ARE RE RA E RA EK EK for ushPlayCount 0 ushPlayCount lt ushDataSize ushPlayCount FRERERERAE RR RAR RARE RAR f ES Play low 4 bits FREE kckck kckckckckck kc kck kc RR Decompression of ADPCM data low 4 bits 16 bits DIVMODE 0 Set multiplication mode for adpcm 132 dec ushData unsigned
13. p The D A converter is in the reset status 1 Supplies input clock yis SFR used by the D A converter can be read and written T m A ES Control of real time counter RTC input clock 0 Stops input clock supply Le SFR used by the real time counter RTC cannot be written PE The real time counter RTC is in the reset status 1 Supplies input clock fe SFR used by the real time counter RTC can be read and written Initialize of Key Interrupt Function mcr cT eH a a aca IEA cht a hl BN ein AA fn_InitKr cs pe ele ged ab ae ean gel shes ea ess a aac cea ah ae dea a als WON Gehl ee a ms Nigel Mes eed a Initialization of timer EY sen sy E ta ii an ag ty Tg a ea Cem Ts at e EE E ah aya anh wee A dessa EOI a a Sab A A WS mek arg E eee a fn_InitVr e Er Rec Er MOST ger od nee IP RN E Pde feces be J fn InitAmp Application Note U20028EJ1VOAN 83 xy A E el APPENDIX A PROGRAM LIST jicszco SCS Le See See A NS Initialization of D A Converter E E A E A fn_InitDac j O E E E E Module fn_InitPort Description Setting of I O ports fE parameter Jet return Jia e nene aiaee essct elle Ac i A M leu LL s doe ce static void fn InitPort void E LINEE eee Soke Seek ee eae A Eee Sees MISC ET pe Setting of Port 0 El eS Se te ee A eee EM et Kx eee te Se PO 0b00000000 Set
14. y 4 Timer interrupt is not generated when counting is started Le timer output does not change either ye l yes 0101 1 Capture mode d 2 Counting up pe 3 Possible ys 4 Timer interrupt is generated Application Note U20028EJ1VOAN 93 94 7 Z Zel 75 1 f 1 FE 4x 1 ke z 1 7x APPENDIX A PROGRAM LIST when counting is started timer output also changes 0110 1 Event counter mode 2 Counting down 3 Possible 4 Timer interrupt is not generated when counting is started timer output does not change either x 1000 1 One count mode 2 Counting down 3 Impossible 4 Start trigger is invalid during counting operation At that time interrupt is not generated either A 1001 1 One count mode 2 Counting down 3 Impossible 4 Start trigger is valid during counting operation At that time interrupt is also generated of 1100 1 Capture amp one count mode 2 Counting up 3 Possible 4 Timer interrupt is not generated when counting is started timer output does not change either Start trigger is invalid during counting operation At that time interrupt is not
15. Disables low voltage detection operation S E E EE eee E ele eee E ee ees Module fn InitKr f Description Setting of Key Interrupt Function y3 parameter ies return el A ose CR PDC c static void fn_InitKr void KRMK 1 Disable key interrupt 88 Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST KRM 0b00000001 Key Return Mode Register yox KRO interrupt mode control KR1 interrupt mode control KR2 interrupt mode control ha KR3 interrupt mode control KR4 interrupt mode control KR5 interrupt mode control KR6 interrupt mode control KR7 interrupt mode control 0 Does not detect key interrupt signal 1 Detects key interrupt signal NOP 250 ns interval from set KRM to clear KRIF NOP KRIF 0 Clear key interrupt request flag Module fn InitTauO Description Setting of Timer array unit 0 parameter return static void fn_InitTau0 void TPSOL 0500000010 Timer Clock Select Register 0 Selection of operation clock CK00 e ii Selection of operation clock CK01 0 0 0 0 CKOm CLK 0001 CKOm CLK 2 JE c0 0 7 101 CK0m fCLK 222 7 0 0 1 1 CKOm CLK 2 3 01 00 CKOm
16. IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET IRESET n n E n n i n e x n d n n n n a n n E n n x n n n n a n k n APPENDIX A PROGRAM LIST 18H INTSRE3 1CH INTDMA1 1EH INTSTO INTCSIOO 20H INTSRO INTCSIO1 22H INTSREO 24H INTST1 INTCSI10 26H INTSR1 2AH INTIICA 2CH INTTMOO 2EH INTTMO1 30H INTIMO2 32H INTIMO3 34H INTAD 36H INTRTC 38H INTRTCI 3CH INTST2 INTCSI20 3EH INSR2 40H INTSRE2 42H INTTMO4 44H INTTMO5 46H INTTMO6 48H INTTMO7 52H INTP10 54H INTP11 56H INTTM10 Application Note U20028EJ1VOAN INTIIC10 INTIIC20 APPENDIX A PROGRAM LIST DW IRESET 58H INTTM11 DW IRESET 5AH INTTM12 DW IRESET 5CH INTTM13 DW IRESET 5EH INTMD TVCT3CSEG AT 00007EH DW IRESET 7EH BRK Stack area definition DSTK DSEG IHRAM Stack Area address STACKEND DS 60H STACKTOP DPMAIN DSEG SADDRP RADPCMWORK DS 32 Work area for ADPCM process RPLAYCOUNT DS 2 Play data counter Code Hardware initialization D PUBLIC IRESET IRESET
17. O MOV B 2 SET1 TSOL 0 JINIVR100 CLR1 TMIFOO JINIVR200 NOP BF TMIFOO SIINIVR200 DEC B BNZ SJINIVR100 CLR1 TMIFOO SET1 TTOL 0 RET Module SINITAMP Description parameter 2 return TE SINITAMP MOV ADPC 00000000B ANI8 AMP2 P150 ANTO AMPO P20 0 0 0 0 0 0 0 0 0 0 i 0 0 0 0 0 0 A D Port Configuration Register Analog input A digital I O D switching inesse ee eae ANI15 AVREFM P157 4 ANI10 P152 ANI7 AMP20 P27 0 0 AAAAAAAAAAAA 01 A AA AAAAAAAAD TO AAAAAAAAAADD t i AAAAAAAAADDD 0 0 AAAAAAAADDDD 01 AAAAAAADDDDID 10 AAAAAADDDDDILD YA AAAAADDDDDDD Application Note U20028EJ1VOAN 71 CLR1 OAC 1 CLR1 OAC 2 RET APPENDIX A PROGRAM LIST i 01000 AAAADDDDDDDD i 01001 AAADDDDDDDDD aN 01010 AADDDDDDDDDD i Hl 01111 ADDDDDDDDDDD i 10000 DDDDDDDDDDDD i AR A N E Be sure to set 000 Operational amplifier AMP1 disable Operational amplifier AMP2 disable Module SINITDAC Description A parameter H return Setting of D A Converter SINITDAC MOV DAM converter 72 01000101B D A Converter Mode Register gt DAMDO D A converter operation mode selection LL DAMD1 D A converter operation mode selection LI III 0 Normal mode sl 1
18. Setting up voltage reference e Selecting the voltage reference as a reference voltage source e Setting the output voltage of voltage reference to 2 0 V e Using channel 0 of timer array unit O to wait for about 20 ms until the operation of the voltage reference is stabilized Setting up operational amplifiers 1 and 2 Setting up D A converter e Selecting the real time output mode as the operation mode e Setting the resolution to 12 bits e Selecting Vnerour AVnere pin as the voltage reference source of the D A converter HALT mode INTKR interrupt No input Avoiding chattering of key Key input Outputting ADPCM a7 D data from D A f converter oe Application Note U20028EJ1VOAN 9 CHAPTER 3 SOFTWARE 3 4 Flow Chart A flow chart for the sample program is shown below lt Settings during initialization immediately after a reset ends gt The option byte is referenced Disable interrupts Set up the register ban Processing overview This processing makes initial settings of the peripheral functions to be used after a reset ends The settings are mainly for the CPU clock I O port timer array unit 0 voltage reference operational amplifiers and converter k Note 2 Specify the stack pointer o Secure a supply voltage of 2 7 V by low voltage detector Specify the CPU clock to Channel 0 is set in the interval timer mode of about 10 ms to avoid chatter
19. d p pra paN ESQ AMPOO AMPO Se ae EN zm EH EET BEBE AECA E Eu ura RE ES d E jojolo aJ a a A aaa A A 6 m5 4 3 2 AD AD AD AD AD ee input A digital I O D switching 0 Other than above Setting prohibited Cautions 1 Set pins to be used with operational amplifiers in the input mode by using port mode registers 2 and 15 PM2 PM15 2 Be sure to clear bits 7 to 5 to 0 Remark The values written in red in the above figure are specified in this sample program Application Note U20028EJ1VOAN 25 CHAPTER 4 SETTING METHODS 3 Port mode registers 2 15 PM2 PM15 When using AMP1 ANI3 P23 AMP10 ANI4 P24 AMP1 ANI5 P25 AMP2 ANIG P26 AMP20 ANI7 P27 and AMP2 ANI8 P150 pins for the operational amplifiers set PM23 to PM27 and PM150 to 1 The output latches of PM23 to PM27 and PM150 at this time may be 0 or 1 If PM23 to PM27 and PM150 are set to 0 they cannot be used as the pins of the operational amplifiers Figure 4 10 Format of Port Mode Register 2 PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 P2n pin I O mode selection n 3 to 7 0 Output mode output buffer on 4 Input mode output buffer off Caution Ifa pin is set as an analog input port not the pin level but 0 is always read Remark The values written in red in the above figure are specified in this sample program Figure 4 11 Format of Port Mode Register 15 PM15 P150 pin I O mode selection o Output m
20. 0 1 AVRI be set in conversion mode 1 EFP external voltage reference input 2 Stops operation Hi Z Application Note U20028EJ1VOAN 69 selection 70 un E ET1 ADVRC 0 SET1 ADVRC 1 HI 0 A E a APPENDIX A PROGRAM LIST 3 2 0 V 4 Enables operation 5 Can be set in conversion mode 2 or 3 00 1 VREFOUT voltage reference output 2 Stops operation pull down output 3 2 5 V 4 Stops operation Lo 01 1 VREFOUT voltage reference output 2 Enables operation 312 5 V 4 Enables operation 5 Can be set in conversion mode 2 or 3 10 1 VREFOUT voltage reference output 2 Stops operation pull down output 3 2 0 V 4 Enables operation LS 11 1 VREFOUT voltage reference output 2 Enables operation 312 0 V 4 Enables operation 5 Can be set in conversion mode 2 or 3 ther than the above Setting prohibited Be sure to set 0000 Reference voltage supply negative side of A D converter 0 AVSS 1 AVR EFM external voltage reference input Enables operation Output 2 0 V Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST Wait for settling time to 20 ms over 17 msec Set counter Start TAUO CHO Clear interrupt request flag Wait 10 msec 20 msec elapsed No Clear interrupt request flag Stop TAUO CHO Setting of Operational amplifier xod sO 0 0
21. 2 fSUB 4 or INTRTC1 valid edge LIN the timer input used with channel 0 ILI is selected by using TISO register III 0 0 Falling edge ILL 01 Rising edge 10 Both edges when low level width is measured INI Start trigger Falling edge Capture trigger Rising edge IF III 11 Both edges when high level width is measured ILI Start trigger Rising edge Capture trigger Falling edge PEL DE 4 Setting of start trigger or capture trigger of channel 0 0 0 0 Only software trigger start is valid 1411111 other trigger sources are unselected 0 0 1 Valid edge of TI00 pin input signal fSUB 2 fSUB 4 or 211111 INTRTC1 is used as both the start trigger and capture trigger 0 1 0 Both the edges of TI00 pin input signal fSUB 2 fSUB 4 or 141111 INTRTC1 are used as a start trigger and a capture trigger 1 0 0 Interrupt signal of the master channel is used 1411111 when the channel is used as a slave channel I with the combination operation function Other than above Setting prohibited FS EE Selection of slave master of channel 0 0 Operates as slave channel with combination operation function 1 Operates as master channel with combination operation function Ter 7 Select
22. 84 V 1111 1010 VLVI10 2 68 V 60 Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST i 1011 VLVI11 2 53 V i 1100 VLVI12 2 38 V Ll l1 0 1 VLVI13 2 22 V ake ug VLVI14 2 07 V 1 4 X E VLVI15 1 91 V AA AH A Be sure to set 0000 CLR1 LVIMD Generates an internal interrupt signal when detect the low voltage SET1 LVION i Enables low voltage detection operation Software to wait for the operation stabilization time over 10 us MOV B 10 i HRES100 NOP i DEC B BNZ SHRES100 Set counter Finished waiting Wait for VDD to become VLVI or more HRES300 NOP BT LVIF SHRES300 i CLR1 LVION i RET VDD VLVI Yes 1 clk 1 clk No 2 clk 4 clk Disables low voltage detection operation Module SINITKR Description Setting of Key parameter A return Se Interrupt Function SINITKR SET1 KRMK MOV KRM 00000001B n O ALLEUR eee Application Note U20028EJ1VOAN Disable key interrupt Key Return Mode Register KRO KR1 KR2 KR3 interrupt mode interrupt mode interrupt mode interrupt mode control control control control 61 APPENDIX A PROGRAM LIST KR4 interrupt mode control 4 KR5 interrupt mode control KR6 interrupt mode control Ppt KR7 interrupt mode control 0 Does not detect key interrupt signal 1 Detects key
23. CHAPTER 3 SOFTWARE 3 3 Initial Settings and Operation Overview In this sample program the main system clock is selected and the I O port timer array unit O voltage reference operational amplifiers and D A converter are set up as initial settings After completion of the initial settings ADPCM data is played back by input of a key The details are described in the state transition diagram shown below Initial settings lt Option byte settings gt e Disabling the watchdog timer e Setting the internal high speed oscillator frequency to 8 MHz e Disabling LVI from being started by default e Enabling on chip debug to operate lt Settings during initialization immediately after a reset ends gt e Setting up I O ports e Setting P23 P25 P26 and P150 to input data to operational amplifiers e Setting P24 and P27 to output data from operation amplifiers e Setting KRO to input key and detect key interrupt signal Securing a supply voltage of 2 7 V or more by using the function of low voltage detector Specifying that the CPU clock run on the X1 oscillator 20 MHz Stopping the internal high speed oscillator Setting up timer array unit O e Setting channel O of timer array unit O in a mode in which it operates as an interval timer of about 10 ms to set settling time of the voltage reference and avoid chattering of a key input e Setting channel 4 in interval timer mode to set the sampling frequency for playing back ADPCM data to 8 kHz
24. CLK 2 4 02101 CKOm CLK 2 5 0110 CKOm CLK 2 6 0111 CKOm CLK 2 7 JN 1000 CKOm fCLK 2 8 Application Note U20028EJ1VOAN 90 ji T m m m T m T CHO TMROO 4x 1 ke z 1 7x CKOm CKOm CKOm CKOm CKOm CKOm CKOm For timing fC LE C fC fC fC EC APPENDIX A PROGRAM LIST LK 2 9 LK 2 10 LK 2 11 LK 2 12 LK 2 13 LK 2 14 LK 2 15 0b0000000000000000 Timer Mode Register 00 0000 0001 0100 0101 1 Operation mode of channel 0 2 Count operation of TCR 3 Independent operation 4 Setting of starting counting and interrupt 1 Interval timer mode 2 Counting down 3 Possible 4 Timer interrupt is not generated when counting is started timer output does not change either 1 Interval timer mode 2 Counting down 3 Possible 4 Timer interrupt is generated when counting is started timer output also changes 1 Capture mode 2 Counting up 3 Possible 4 Timer interrupt is not generated when counting is started timer output does not change either 1 Capture mode 2 Counting up 3 Possible Applica
25. P110 Play back output ANOO P111 Unused A Tack eae es a d eee ey ae eed Er ae er es ee ee ee eee ee eee es oe eee aie Setting of Port 12 A A ves ee tah aca ag sek Vga ese EN es as E E REV TOL S P12 0b00000000 Set P120 Output latch to Low PM12 0611111110 Set P120 to output port P120 to P124 Unused P121 to P124 Input port 86 Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST Jus Setting of Port 13 P13 0b00000000 Set P130 Output latch to Low P130 Unused PE deh sees A ck feng ek ce PE a HIN st A aes aN A NER eh Kast feel RS cop ls Spach lan POPE LANES E gc la hse eles Setting of Port 14 J Ama v P14 0b00000000 Set P140 to P147 Output latches to Low PM14 0500000000 Set P140 to P147 to output port P140 to P147 Unused EROR OMS OPNS VERLORENE A a a ERES ARUM ETE a al NL POP S PSAL ate DRUSI eres Nel a A Setting of Port 15 d ocu es do MA Sa cd ns SS a dh essed EAE Sex he tal ck Do A ech Vahl od ech Ve ed Sch ens emt te ake Anl nae a a el et ie a aid ee ee A a P15 0b00000000 Set P150 to P152 and P157 Output latches to Low PM15 0b11111111 Set P150 to P152 and P157 to input port PM150 Filter circuit AMP2 P151 to P152 and P157 Unused j p DEC Module fn_InitLvi El Description Ensures 2 7 V to the power supply voltage 7
26. POO to P02 Output latches to Low PMO 0b11111000 Set POO to P02 to output port P00 to P02 Unused is ibd Ss aaa GS es a a asad ad ase at i Ll Sr gs a ah a ae a a A ae a a E aa a la pd NS a dae AS Setting of Port 1 T aUe me un A eb us T TRE RE oo prem e B LI a MEE me ep Eus EEEE E e Ren E ue be DY Ri CE Ent iind ee li qd Patios Pl 0b00000000 Set P10 to P17 Output latches to Low PM1 0b00000000 Set P10 to P17 to output port P10 to P15 Unused i kad Sag aN es A a ii ECL s Setting of Port 2 Refs a mien e fed exa or el ido De ee T me ue Es EEE Ld Er e Eug al ar zu mea ee Pee o E DPEN dd ear quce e Rak ER Ens a li d itd P2 0b00000000 Set P20 to P27 Output latches to Low PM2 0b11111111 Set P20 to P27 to input port PM23 Filter circuit AMP1 PM24 Filter circuit AMP10 PM25 Filter circuit AMP1 PM26 Filter circuit AMP2 PM27 Filter circuit AMP20 84 Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST P20 to P22 Unused A RA vere A a ND A a hai pvp EN Je Setting of Port 3 A NU tU e OUR A Sek Sa tem a a e Fa uo SC USER ed mien a ee A PB rr cep S o lo EM ee Be as P3 0b00001000 Set P30 to P32 and P34 Output latches to Low Set P33 Output latch High PM3 0b11100000 Set P30 to P34 to output port P30 to P34 Unused ei at ee acta A
27. before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries Note 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E0909 Application Note U20028EJ1VOAN CHAPTER 1 OVERVIEW This sample program outputs and plays back ADPCM format sound data by using a 12 bit D A conver
28. by changing the system clock control register CKC value stop the timer array unit TTO OOFFH TT1 OOOFH 2 Only in the case of SDIV 0 CCSmn 1 and TISmn 1 continuously use of TAUm is allowed even when changing CPU clock m 0 1 mn 00 to 07 10 to 13 However the following limitation is existing e When changing CPU clock source clock decrease increase occurs as follows Main system clock gt Subsystem clock CSS 0 gt 1 1 clock Subsystem clock gt Main system clock CSS 1 gt 0 1 clock Caution Be sure to clear bits 15 to 8 to 0 Remarks 1 fcik CPU peripheral hardware clock frequency 2 The values written in red in the above figure are specified in this sample program Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS 2 Timer mode registers 00 04 TMROO TMR04 TMROO and TMR04 set an operation mode of channels 0 and 4 of timer array unit O These registers are used to select an operation clock MCK a count clock whether the timer operates as the master or a slave a start trigger and a capture trigger the valid edge of the timer input and an operation mode interval capture event counter one count or capture amp one count Figure 4 3 Format of Timer Mode Register 00 TMROO 1 2 CKS CCS MAST STS STS STS CIS CIS MD MD MD MD 00 00 EROO 002 001 000 001 000 003 002 001 000 STS002 STS0O01 STSO000 Setting of start trigger or capture trigger of channe
29. development environment PM are included LE Application Note U20028EJ1VOAN 7 CHAPTER 3 SOFTWARE 3 2 Internal Peripheral Functions to Be Used The following internal peripheral functions of the microcontroller are used in this sample program Channel 0 of timer array unit O TAUO Channel O of timer array unit O is used as an interval timer to avoid chattering of key input and to wait for stabilization of the voltage reference Channel 4 of timer array unit O TAUO Channel 4 of timer array unit O is used as an interval timer to generate a sampling frequency of 8 kHz for playing back ADPCM data Voltage reference Generates a reference voltage of 2 0 V for the D A converter D A converter Outputs ADPCM data as sound data Operational amplifiers Used as filter circuits for the sound data output from the D A converter Low voltage detector Used to check that Voo is 2 7 V or more Pin function The pin functions to be used are listed below Pin Function When External Device Is Connected Alternate Function Function Pin Analog output of D A converter P111 Operational amplifier input positive P25 ANI5 Operational amplifier input negative P23 ANI3 Operational amplifier output P24 ANI4 Operational amplifier input positive P150 ANI8 Operational amplifier input negative P26 ANI6 Operational amplifier output P27 ANI7 Key input P70 Application Note U20028EJ1VOAN
30. figure are specified in this sample program Application Note U20028EJ1VOAN 19 CHAPTER 4 SETTING METHODS Figure 4 4 Format of Timer Mode Register 04 TMRO4 2 2 CKS CCS MAST STS STS STS CIS CIS MD MD MD MD 04 04 ERO4 042 041 040 041 040 043 042 041 040 Operation mode MD040 Setting of starting counting and interrupt set by MD043 to MD041 e Interval timer mode Timer interrupt is not generated when counting is started timer output does not change either 1 Timer interrupt is generated when counting is started timer output also changes e Event counter mode Timer interrupt is not generated when counting is started timer output does not change either e One count mode Start trigger is invalid during counting operation At that time interrupt is not generated either Note Start trigger is valid during counting operation At that time interrupt is also generated e Capture amp one count mode Timer interrupt is not generated when counting is started timer output does not change either Start trigger is invalid during counting operation At that time interrupt is not generated either Other than above Setting prohibited MD043 MD042 MD041 MDO40 Operation mode of channel 4 Count operation of TCR Independent operation o o Trainer meno Couningaown Possbie o 1 o capture mode Counting up ossi o 1 o event counter mode Counting down Possiie a
31. generated either xr Other than above Setting prohibited af Application Note U20028EJ1VOAN A APPENDIX A PROGRAM LIST Be sure to set 00 4 pz HA Selection of TIO04 pin input signal fSUB 2 f SUB 4 or INTRTC1 valid edge the timer input used with channel 4 if is selected by using TISO register X 0 0 Falling edge IE 0 1 Rising edge 10 Both edges when low level width is measured E Start trigger Falling edge Capture trigger Rising edge 1 1 Both edges when high level width is measured ys Start trigger Rising edge Capture trigger Falling edge iat 4 4 Setting of start trigger or capture trigger of channel 4 Ke 000 Only software trigger start is valid other trigger sources are unselected ee 001 Valid edge of TI04 pin input signal fSUB 2 fSUB 4 or INTRTC1 is used as both the start trigger and capture trigger Vit 010 Both the edges of TI04 pin input signal fSUB 2 fSUB 4 or INTRTC1 are used as a start trigger and a capture trigger JA 100 Interrupt signal of the master channel is used when the channel is used as a slave channel with the combination operation function pz Other than above Setting prohibited y j EE A aS Selection of slave master of channel 4 Lx 0 Ope
32. interrupt signal NOP 250 ns interval from set KRM to clear KRIF CLR1 KRIF Clear key interrupt request flag Module SINITTAUO i Description Setting of Timer array unit 0 parameter E r return a SINITTAUO MOV TPSOL 00000010B Timer Clock Select Register 0 Selection of operation clock CK00 AA A A Selection of operation clock CK01 0000 CKOm CLK i 0001 CKOm CLK 2 0010 CKOm CLK 2 2 A 0011 CKOm fCLK 2 3 i 0100 CKOm CLK 2 4 7 0101 CKOm fCLK 2 5 0110 CKOm fCLK 2 6 0111 CKOm fCLK 2 7 1000 CKOm fCLK 2 8 1001 CKOm fCLK 2 9 1010 CKOm f CLK 2 10 1011 CKOm CLK 2 11 110 0 CKOm CLK 2 12 7 121021 CKOm CLK 2 13 62 Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST 1110 CKOm CLK 2 14 1111 CKOm CLK 2 15 CHO for timing MOVW AX 0000000000000000B Timer Mode Register 00 Movw TMROO AX 1 0peration mode of channel 0 LEEEEEEEEL I 2 Count operation of TCR LEEEEEEEEL I 3 Independent operation LLL EL I 4 Setting of starting counting and interrupt III 1 0 0 0 0 11Interval timer mode SULLEI 2 Counting down LEE IL I 3 Possible HEEE 4 Timer interrupt is not generated HEEE EE DS when counting is started LEEEEEEEEL I timer output does not change either LILLE LE 0 0 0 1 1 Interval timer mode LI
33. o 9 vo Onecountmode Counting down impossible a 3 o o Capture amp one oount made counting up Posse CIS041 CIS040 Selection of valid edge of TIO4 pin input signal fsue 2 fsus 4 or INTRTC1 the timer input used with channel 4 is selected by using TISO register o o Fating edge o 1 Rising edge 1 Both edges when low level width is measured Start trigger Falling edge Capture trigger Rising edge Both edges when high level width is measured Start trigger Rising edge Capture trigger Falling edge If both the edges are specified when the value of the STS042 to STS040 bits is other than 010B set the CIS041 and CIS040 bits to 10B Note f the start trigger TS04 1 is issued during operation the counter is cleared an interrupt is generated and recounting is started Caution Be sure to clear bits 14 13 5 and 4 to 0 Remark The values written in red in the above figure are specified in this sample program 20 Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS 3 Timer data registers 00 04 TDROO TDR04 TDROO and TDR04 are 16 bit registers from which a capture function and a compare function can be selected In this sample program TDROO and TDRO4 are used as comparison registers Counting down is started from the value set to TDROO or TDRO4 When the count value reaches 0000H an interrupt signal INTTMOO or INTMMO4A is generated TDROO and TDRO4 hold their value unt
34. short adpcm 132 dec pucPlayData ushPlayCount amp Ox0f ushAdpcmWork Adjust sign amp right align data ushData unsigned short ushData 0x8000 gt gt 16 12 Set play data DACSWO ushData Waiting for the output to be completed while TMIFO4 NOP SEMSEER 0 Clear interrupt request flag f RERERRERERERERERERERER ok f Play high 4 bits ERRERRERERERERERERERER E f Decompression of ADPCM data high 4 bits gt 16 bits DIVMODE 0 Set multiplication mode for adpcm 132 dec ushData unsigned short adpcm 132 dec pucPlayData ushPlayCount 4 amp OxOf ushAdpcmWork Adjust sign amp right align data ushData unsigned short ushData 0x8000 gt gt 16 12 Set play data DACSWO ushData Waiting for the output to be completed while TMIFO4 NOP TMIFOA 0 Clear interrupt request flag Stop TAUO CH4 D A converter CHO disable Operational amplifier AMP1 disable Operational amplifier AMP2 disable Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS Here is a timing chart for the playback processing INTTMO4 ANOO DACSWO Software processing 125 us 125 us 125 us Hi z X Defaulllvalue A Default value D About 30 ys ower Expan sion Wait DiL SEND GE US C D1H D2L Expan Expan j Expan sion Wait sion Wai
35. up resistor is connected to the P70 pin 2 2 Used Devices Other than Microcontroller The following devices are used in addition to the microcontroller 1 Power amplifier A power amplifier is used to amplify the value of the output sound data In this application example the LM4890M is used 2 Variable resistor This is used to adjust the volume of the output sound data 3 Speaker Outputs sound data 4 Key A key is used to start playing back sound data 2 3 Pin Function List The pin functions to be used are listed below Pin Function When External Device Is Connected Alternate Function Function Pin Analog output of D A converter P111 Operational amplifier input positive P25 ANI5 Operational amplifier input negative P23 ANI3 Operational amplifier output P24 ANI4 Operational amplifier input positive P150 ANI8 Operational amplifier input negative P26 ANI6 Operational amplifier output P27 ANI7 Key input P70 6 Application Note U20028EJ1VOAN CHAPTER 3 SOFTWARE This chapter describes the configuration of the files included in the compressed file to be downloaded internal peripheral functions of the microcontroller to be used initial settings and operation overview of the peripherals to be used by the sample program a and flow chart 3 1 Included Files The following table shows the files included in the compressed file to be downloaded File Name Description
36. using timer data register 00 TDROO Select CK01 as the operating clock of channel 4 and the interval timer mode as the operation mode by using timer mode register 04 TMR04 Set the interval of channel 4 to about 125 ws by using timer data register 04 TDR04 Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS 1 Timer clock select register 0 TPSO TPSO is a 16 bit register that is used to select two types of operation clocks CK00 CK01 that are commonly supplied to each channel of timer array unit O CKO1 is selected by bits 7 to 4 of TPSO and CKOO is selected by bits 3 to 0 Rewriting of TPSO during timer operation is possible only in the following cases Rewriting of PRSOOO to PRS003 bits Possible only when all the channels set to CKSOn 0 are in the operation stopped state TEOn 0 Rewriting of PRSO10 to PRS013 bits Possible only when all the channels set to CKSOn 1 are in the operation stopped state TEOn 0 Figure 4 2 Format of Timer Clock Select Register 0 TPSO PRS PRS PRS PRS PRS PRS PRS PRS 013 012 011 010 003 002 001 000 Selection of operation clock CK00 Poo o o j o re A Lo jo o j t mec 5 o1 o iwz foul fcu 2 1 foLx 2 foLx 2 foLx 2 foLx 2 1 foLx 2 foLx 2 1 fcu 2 fox 2 fcu 2 Application Note U20028EJ1VOAN 15 16 CHAPTER 4 SETTING METHODS Notes 1 When changing the clock selected for fcik
37. 0000000B Set P110 and P111 Output latches to Low MOV PM11 11111101B Set P110 to input port P111 to output port P110 Play back output ANOO P111 Unused MOV P12 00000000B Set P120 Output latch to Low MOV PM12 11111110B Set P120 to output port P120 to P124 Unused P121 to P124 Input port MOV PI3 00000000B Set P130 Output latch to Low P130 Unused Application Note U20028EJ1VOAN 59 APPENDIX A PROGRAM LIST Setting of Port 14 MOV P14 00000000B Set P140 to P147 Output latches to Low MOV PM14 00000000B Set P140 to P147 to output port P140 to P147 Unused MOV P15 00000000B Set P150 to P152 and P157 Output latches to Low MOV PM15 11111111B Set P150 to P152 and P157 to input port PM150 Filter circuit AMP2 P151 to P152 and P157 Unused RET Module SINITLVI Description Ensures 2 7 V to the power supply voltage parameter 7 return vemm SINITLVI Setting of Low Voltage Detector SET1 VIMK Disable LVI interrupt CLR1 VISEL Detects level of VDD MOV LVIS 00001001B Low Voltage Detection Level Select Register Detection level sll 0 0 0 0 VLVIO 4 22 V il 0 0 0 1 VLVIL 4 07 V il 0 0 1 0 VLVI2 3 92 V Pa 0 0 f VLVI3 3 76 V il 01 00 VLVI4 3 61 V ll e e d VLVI5 3 45 V III 0110 VLVI6 3 30 V snb Va W fecal bao e a VLVI7 3 15 V 2111 1000 VLVI8 2 99 V ERN 1001 VLVI9 2
38. 1 n 1 2 2 The values written in red in the above figure are specified in this sample program Caution When an operational amplifier is used AMPn AMPn and AMPnO pins are used so the alternative analog input functions cannot be used The operational amplifier output signals however can be used as analog inputs Application Note U20028EJ1VOAN 27 CHAPTER 4 SETTING METHODS 4 5 Setting Up D A Converter The following three registers are used to set up the D A converter 28 e Peripheral enable register 0 PERO e D A converter mode register DAM e D A conversion value setting register WO DACSWO Example of procedure for setting up D A converter to play back sound data 1 2 3 4 Set bit 6 DACEN of peripheral enable register 0 PERO to 1 see 4 1 By using the D A converter mode register DAM select the real time mode as the operation mode of the D A converter a resolution of 12 bits and Vrerout as the positive reference voltage source of the D A converter Set bit 4 DACEO of the D A converter mode register DAM to 1 to enable the D A conversion operation of channel 0 of the D A converter Set 800H P P 1 2 of 2 0 V sound amplitude 0 as the default value of the D A conversion value to the D A conversion value setting register WO DACSWO Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS 1 D A converter mode register DAM This register controls the operation of the D A c
39. 1x011 fMX 2 3 01x100 fMX 2 4 01x101 fMX 2 5 1x0xxx fSUB A 1xi1xx x fSUB 2 Other than above Setting prohibited x don t care Status of Main system clock fMAIN 0 Internal high speed oscillation clock fIH 1 High speed system clock fMX T Status of CPU peripheral hardware clock fCLK Application Note U20028EJ1VOAN HRST100 BT BF SET1 MOV MOV APPENDIX A PROGRAM LIST Main system clock fMAIN Subsystem clock fSUB CPU is operating on a High speed system clock CLS SHRST MCS SHRST HIOSTOP OSTS 0000 ie PERO 0110 100 No 100 No Internal high speed oscillation stopped 0111B Oscillation Stabilization Time Select Register Oscillation stabilization time selection 000 2 8 X 001 2 9 fX 010 2 10 f X 011 2 11 fX 100 2 13 fX t 0 1 2 157 fX 1 1 0 2 17 X 111 2 18 fX EE Be sure to set 0000 0001B Peripheral Enable Register 0 Control of timer array unit 0 input clock 0 Stops input clock supply SFR used by timer array unit 0 cannot be written Timer array unit 0 is in the reset status 1 Supplies input clock SFR used by timer array unit 0 can be read and written Control of timer array unit 1 input clock 0 Stops input clock supply SFR used by timer array unit 1 cannot be written Timer array unit 1 is in the reset status 1 Supplies inp
40. 7 0 0 key input Sa ik tt ch a fa eit cs hi Pc sup a ep eh es aN ah as em Play melody R HA em ep en eg cee ai gt fn PlayDac fORCKCKCKCk kckckckckckckckckckckckckckckckckckckckck kckckckckckckckck ck kckckck k kk AN ES ye The main processing writes here if there is something uA E o FERRERA RE RARA RARE RRA RARE RE RRA RARA kk ko kk Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST 103 APPENDIX B REVISION HISTORY Date Published Sembra P 104 Application Note U20028EJ1VOAN For further information please contact NEC Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki Kanagawa 211 8668 Japan Tel 044 435 5111 http www necel com America NEC Electronics America Inc 2880 Scott Blvd Santa Clara CA 95050 2554 U S A Tel 408 588 6000 800 366 9782 http www am necel com Europe NEC Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 0211 65030 http www eu necel com Hanover Office Podbielskistrasse 166 B 30177 Hannover Tel 0 511 33 40 2 0 Munich Office Werner Eckert Strasse 9 81829 M nchen Tel 0 89 92 10 03 0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel 0 711 99 01 0 0 United Kingdom Branch Cygnus House Sunrise Parkway Linford Wood Milton Keynes MK14 6NP U K Tel 01908 691 133 Succursale Francaise 9 rue Paul Dautier B P 52 78142 Velizy Villacoublay
41. AC150 20 us elapsed No D A converter setting Application Note U20028EJ1VOAN Use software to wait until the operational amplifier stabilizes 20 us max 73 APPENDIX A PROGRAM LIST SET1 DACEO D A converter CHO enable TAUO CH4 setting for output timing CLR1 TMIFO4 Clear interrupt request flag SET1 TSOL 4 Start TAUO CH4 ek ck ckckckockock ck ckockckock ck ck ck ck ck ckck ck ck kck kc k ck kk k kk kk 1 a KKKKKKKKKKKKEKKKKKKEKKKKKKKKEKKKKKKK 7 MOVW RPLAYCOUNT 0 Clear output data counter JPDAC200 MOVW AX RPLAYCOUNT Get number of output times CMPW AX ITPLAYSIZE Finished all data output BNC SJPDAC300 Yes ckckckockckck ck ckck ck ck ck ck k ck kk kk kk 7 1 A Play low 4 bits a ckckckockckckck ck ck ck ck kc ck kc ck k k kk kk 1 Decompression of ADPCM data low 4 bits gt 16 bits MOVW AX LOWW RADPCMWORK Set work area for _adpcm_132_dec PUSH AX MOV A ES HL Get compressed data AND A 00FH Clear high 4 bits MOV X A CLRB A CLR1 DIVMODE Set multiplication mode for adpcm 132 dec CALL adpcm 132 dec Decompression of PCM data POP AX MOVW AX BC Get decompression data Adjust play data ADDW AX 8000H Adjust sign SHRW AX 16 12 Right align data JPDAC220 MOVW DACSWO AX Set play data 74 Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST Waiting for the output to be completed JPDAC230
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43. Capture amp one count mode LEER 2 Counting up LEE T I 3 Possible HEEE 4 Timer interrupt is not generated LEEEEEEEEL I when counting is started HEEE timer output does not change either LEEEEEEEEL I Start trigger is invalid HEEE EE during counting operation SILILI At that time interrupt sIIIIIIIIIII is not generated either IIIIIIII Other than above Setting prohibited I IIIII Be sure to set 00 sl Idd Selection of TI00 pin input signal EEES fSUB 2 SUB 4 or INTRTC1 valid edge 64 Application Note U20028EJ1VOAN edge edge channel 0 trigger trigger or INTRTC1 register APPENDIX A PROGRAM LIST the timer input used with channel 0 is selected by using TISO register 0 Falling edge Rising edge Eto 3S B 0 Both edges when low level width is measured Start trigger Falling edge Capture trigger Rising 11 Both edges when high level width is measured LI Start trigger Rising edge Capture trigger Falling Setting of start trigger or capture trigger of 0 00 Only software trigger start is valid other trigger sources are unselected 00 1 Valid edge of TIOO pin input signal fSUB 2 fSUB 4 or INTRTC1 is used as both the start trigger and capture 010 Both the edges of TI00 pin input signal fSUB 2 fSUB 4 or INT
44. Compressed zip File i Included main asm Source file for hardware initialization processing and main Assembly language version processing of microcontroller C language version data playrom asm ADPCM data table file Assembly language version data_playrom c C language version op asm Assembler source file for setting the option byte This file is used for setting up the watchdog timer selecting the internal high speed oscillation clock frequency setting up the LVI default start function and setting up the on chip debug operation 78KOR_Lx3_PlayBack prw Work space file for integrated development environment PM 78KOR Lx3 PlayBack prj Project file for integrated development environment PM Notes 1 main asm is included with the assembly language version and main c with the C language version 2 data playrom asm is included with the assembly language version and data playrom c with the C language version Caution This sample program uses an ADPCM library Therefore the standard header library adpcmsp h and library file adpcmsp lib of ADPCM SP are necessary for a program in C and the library file adpcmsp lib of ADPCM SP is necessary for a program in assembly language Obtain ADPCM SP from the download site of development tools http necel com micro ja development asia 78k0r htm Remark ZTE Only the source file is included a The files to be used with integrated
45. E LL E 2 Counting down HIDE 3 Possible LLL I 4 Timer interrupt is generated LILIA I when counting is started LILLE LL TTA timer output also changes IlIlIlIlIl 0100 1 Capture mode HEEE 2 Counting up HIDE 3 Possible LHEEEEEEEEL I 4 Timer interrupt is not generated III when counting is started LHEEEEEEEEL I timer output does not change either IlIlIlIlIl 0201 1 Capture mode LEEEEEEEEL I 2 Counting up LEE TL I 3 Possible EEES 4 Timer interrupt is generated when LEEEEEEEEL I counting is started HEEE timer output also changes LIPEEEEE EE 0 1 1 0 1 Event counter mode Application Note U20028EJ1VOAN 63 APPENDIX A PROGRAM LIST HEEL LL LN I 2 Counting down HIDE 3 Possible LHEEEEEEEEL I 4 Timer interrupt is not generated LLL I when counting is started HEEE timer output does not change either III III 1 00 0 1 0ne count mode III EII A LN I 2 Counting down HEEL LL A I 3 Impossible HEEE 4 Start trigger is invalid LEEEEEEEEL I during counting operation III At that time interrupt LEEEEEEEEL I is not generated either ILL ELE 200 1 110ne count mode AMUUA NA SMAN 2 Counting down EPERE TEEN 3 Impossible sIIIIIIIIIII 4 Start trigger is valid sIIIIIIIIIII during counting operation LLL I At that time interrupt LEEEEEEEEL I is also generated bHEEELEEELELLE L 1200 1
46. E ee i pce i ia See a sel et Seren epi al ae psn spc ac Semester pa Ge nano gcse a Setting of Port 4 j FREIE A EEUU a REED TREE CP ESSERI RS cerco ale ga a ee TD ORO OECD pet a a PES P4 0b00000000 Set P40 and P41 Output latches to Low PM4 0b11111100 Set P40 and P41 to output port P40 and P41 Unused edet an EE gp le aes en deo op Reape E A ep pt ee SS ype AA PA AI Se hn eg Ce ae i E yis Setting of Port 5 aa ME RUM ENS A E gi A Se SOR ERE ES ON ee EE P5 0b00000000 Set P50 to P57 Output latches to Low PM5 0b11110000 Set P50 to P57 to output port P50 to P57 Unused EET A CEP EIC moa ee ce a Pees ange SAPE EE UR Ter i o POE MORS eec RR 2E lk gee EE Setting of Port 6 Es Sa ROME NN TAR ee RS E OE I M RENE E SI E E E ER E ION oem EE P6 0b00000000 Set P60 and P61 Output latches to Low PM6 0b11111100 Set P60 and P61 to output port P60 and P61 Unused A oou uA pd Pars cio fud catur a ad Pa gno espe ca ded Duca sud nd out eed Pe eui laxe Egi fas a ge es ata au T tei aap Tr me e e e ed LE Setting of Port 7 E7 FORET MEE CRDI CRUS MU e ROS URS PES RESCUE Ne MU e a e B QE LER ah E M e EE SR NER ES JO e EE J P7 0b00000000 Set P70 to P77 Output latches to Low PM7 0b00000001 Set P70 to input port P71 to P77 to output port FU q ll 0b00000001 P70 on chip pull up resistor connected
47. ETHODS 4 3 Setting Up Voltage Reference The following register is used to set up the voltage reference e Analog reference voltage control register ADVRC Example of procedure for setting up voltage reference to play back sound data lt 1 gt Set bit 5 ADCEN of peripheral enable register 0 PERO to 1 see 4 1 lt 2 gt Set bit 3 VRSEL of the analog reference voltage control register ADVRC to 1 lt 3 gt Set bits 1 and 0 VRGV VRON of the analog reference voltage control register ADVRC to 1 lt 4 gt Wait for about 20 ms by software until the operation of the voltage reference is stabilized 1 Analog reference voltage control register ADVRC This register is used to select the reference voltage supplies of the A D and D A converters control the operation of the input gate voltage boost circuit for the A D converter and control the voltage reference VR operation ADVRC can be set by a 1 bit or 8 bit memory manipulation instruction Figure 4 7 Format of Analog Reference Voltage Control Register ADVRC VRSEL VRGV VRON Positive reference Operation control Output voltage Operation Relationship voltage supplies of voltage selection of control of input with the selection of A D reference voltage gate voltage conversion and D A converters reference boost circuit for mode used A D converter AVnerP Stops operation Stops operation Can be set in external voltage Hi Z conversion reference input mode 1 Enabl
48. External clock input mode 2 Input port 3 uw External clock input CLR1 MSTOP X1 oscillator operating MOV OSMC 00000001B Operation Speed Mode Control Register 3 CLK frequency selection 00 Operates at a frequency of 10 MHz or less 0 1 Operates at a frequency higher than 10 MHz E 10 Operates at a frequency of 1 MHz Pi pttt Be sure to set 00000 jt Setting in subsystem clock HALT mode 0 Enables subsystem clock supply to peripheral functions Application Note U20028EJ1VOAN 51 52 APPENDIX A PROGRAM LIST See Table 21 1 Operating Statuses in HALT Mode 2 3 for the peripheral functions whose operations are enabled 1 Stops subsystem clock supply to peripheral functions except real time counter clock output buzzer output and LCD controller driver BF OSTC 0 X1 oscillation stabilization finished No eS Caution krts naaa o Hesiodus pS Tur To increase fCLK to 10 MHz or higher set FSEL to 1 then change fCLK after two or more clocks have elapsed A Se AA eb es NOP NOP MOV CKC 00010000B System Clock Control Register Selection of CPU peripheral hardware clock fCLK i 00x00 0 IH 00x00 1 fIH 2 default 00x010 fIH 2 2 00x011 IH 2 3 0 0x100 fIH 2 4 i 00x101 fIH 2 5 E 01x000 fMX i 01x00 1 fMX 2 01x010 fMX 2 2 i O
49. M26 filter circuit AMP2 PM27 filter circuit AMP20 P20 to P22 Unused MOV P3 00001000B Set P30 to P32 and P34 Output latches to Low Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST Set P33 Output latch High MOV PM3 11100000B Set P30 to P34 to output port P30 to P34 Unused MOV PA 00000000B Set P40 and P41 Output latches to Low MOV PM4 11111100B Set P40 and P41 to output port P40 and P41 Unused MOV P5 00000000B Set P50 to P57 Output latches to Low MOV PM5 11110000B Set P50 to P57 to output port P50 to P57 Unused MOV P6 00000000B Set P60 and P61 Output latches to Low MOV PM6 11111100B Set P60 and P61 to output port P60 and P61 Unused MOV P7 00000000B Set P70 to P77 Output latches to Low MOV PM7 00000001B Set P70 to input port P71 to P77 to output port MOV PUT 00000001B P70 on chip pull up resistor connected P70 Key input port P71 to P77 Unused MOV P8 00000000B Set P80 to P88 Output latches to Low MOV PM8 00000000B Set P80 to P88 to output port 58 Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST P80 to P88 Unused MOV P9 00000000B Set P90 to P97 Output latches to Low MOV PM9 00000000B Set P90 to P97 to output port P90 to P97 Unused MOV P10 00000000B Set P100 to P102 Output latches to Low MOV PM10 11111000B Set P100 to P102 to output port P100 to P102 Unused MOV P11 0
50. OGRAM LIST while TMIFO4 NOP TMIFO4 0 Clear interrupt request flag erri A A A eger ea ei mar ep AER usi em EN EN Finish playing E Cu eh Spe Sa ac ak ae ad Sa aay eed CENT EP TTOL 4 1 Stop TAUO CH4 DACEO 0 D A converter CHO disable OAC 1 0 Operational amplifier AMP1 disable OAC 2 0 Operational amplifier AMP2 disable Module Main Description Main process sd parameter return 102 2222222222222222222222222222222222 gcn pidiendo cer Main Loop uaa p n E EE io E 2222222222222222222222222222222222 while 1 f kk kk kk kk EERE RA RARE RARA kc kc kokckckckckck ck ckck ck k ko ko ko kk J EJ Play melody when the key is input Joe Sif fk ke kk kk kk RAR RR RAR RARA kokckokckckckckckckckck ck ck ko ko ko kk J So UE Tcp ash us agin ab em ce fb ook baile SER ge PA Wait key input T pe AP ID a EDT A a KRMK 0 Clear key interrupt Application Note U20028EJ1VOAN ty d A el KRIF 0 Clear key interrupt request flag HALT Sets the HALT mode KRMK 1 Set key interrupt KRIF 0 Clear key interrupt request flag PA AA MEE API ETE RUIN DA if P7 0 0 Key input TSOL O 1 Start TAUO CHO TMIFOO 0 while TMIFOO NOP Wait 10 msec TMIFOO 0 TTOL O 1 Stop TAUO CHO 1 P
51. Oscillation stabilization time selection ya 000 2 8 X Lx 0 0 2 9 X 0 410 BALO SES y 0 1 1 2 TL EX PE T9700 ts AA EX E ye ilo 2 15 fX s 110 2 17 X yop ROICA T s 2 18 4 X X R Be sure to set 000000 PERO 0b01100001 Peripheral Enable Register 0 Control of timer array unit 0 input clock Application Note U20028EJ1VOAN 81 7 Z Zel 75 1 f 7E 4x 1 f x be Jo APPENDIX A PROGRAM LIST 0 Stops input clock supply LLLI SFR used by timer array unit 0 cannot be written LI Timer array unit 0 is in the reset status 1 Supplies input clock LL I SFR used by timer array unit 0 can be read and written Control of timer array unit 1 input clock 0 Stops input clock supply LI SFR used by timer array unit 1 cannot be written BE Timer array unit 1 is in the reset status 1 Supplies input clock LI SFR used by timer array unit 1 can be read and written Control of serial array unit 0 input clock 0 Stops input clock supply LI SFR used by the serial array unit 0 cannot be written LI The serial array unit 0 is in the reset status 1 Supplies
52. P70 Key input port P71 to P77 Unused Application Note U20028EJ1VOAN 85 APPENDIX A PROGRAM LIST SS ge ak Sa A is A a El N ee RA dd E id pE Setting of Port 8 E un at Se hts A A IIA de PAE RNA MAA TA AAA E RDA ees A pe ee p aD P8 0b00000000 Set P80 to P88 Output latches to Low PM8 0b00000000 Set P80 to P88 to output port P80 to P88 Unused i id Sa NG i ak A A E PEE EEE EE a a i rr EI a ETC Setting of Port 9 El ces Gum edo cad e rures uno uy enu E E ea Eo ues eb RE eb rnt heed A Gm RES Gg Ern ae fadi qt rir era A au nut eite ii uel ee ee P9 0b00000000 Set P90 to P97 Output latches to Low PM9 0b00000000 Set P90 to P97 to output port P90 to P97 Unused SS a Sa a AS e A Si A a a a E A iS i A Setting of Port 10 Ef ce So Sa iere tk ce et cle Sa a np a hg ce aia gta en ee we A Ce hy gee Rar mr aen fee pe ug IA ee A NEN P10 0b00000000 Set P100 to P102 Output latches to Low PM10 0611111000 Set P100 to P102 to output port P100 to P102 Unused is ibd Ss aa Al A al Sa i aah a ae a al EN E E EE E ng lay aa E tpl gee a dae ect AS Setting of Port 11 Un Ed o eb rr T E vun Fas fs uir ca dal od ipe pw ua t aee T aa es EEE erst Le ee ens GS War GS Eu iae tpl d eid P11 0b00000000 Set P110 and P111 Output latches to Low PM11 0511111101 Set P110 to input port P111 to output port
53. RTC1 are used as a start trigger and a capture 100 Interrupt signal of the master channel is used when the channel is used as a slave channel with the combination operation function Other than above Setting prohibited Selection of slave master of channel 0 0 Operates as slave channel with combination operation function 1 Operates as master channel withcombination operation function Selection of count clock TCLK of channel 0 0 Operation clock MCK specified by CKS00 bit 1 Valid edge of input signal input from TI00 pin fSUB 2 SUB 4 the timer input used with channel 0 is selected by using TISO a aa te Be sure to set 00 Application Note U20028EJ1VOAN 65 66 CKOO MOVW SET1 CH4 MOVW MOVW APPENDIX A PROGRAM LIST t Selection of operation clock MCK of channel 0 Operation clock CK00 set by TPSO register 1 Operation clock CK01 set by TPSO register fCLK 2 3 5 MHz gt 10 ms 0 2 us clk 50000 count TDROO 50000 1 Set interval time to 10 ms TMMK00 Disable interrupt For play back sampling timing AX 1000000000000000B Timer Mode Register 04 TMRO4 AX 1111111 1 0peration mode of channel 4 EHE AN I 2 Count operation of TCR HEEL AG I 3 Independent operation EHE I I 4 Setting of starting counting and interrupt A 0000 1 Inte
54. Setting Up Timer Array Unit O 4 3 Setting Up Voltage Reference 4 4 Setting Up Operational Amplifier 4 5 Setting Up D A Converter sss 4 6 Software Coding Examples 4 7 Playback Processing CHAPTER 5 RELATED DOCUMENTS APPENDIX A PROGRAM LIST APPENDIX B REVISION HISTORY esses seien ennt tente The information in this document is current as of July 2009 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property right
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56. ait until data is output Stop operation of D A converter Update position of reading ADPCM data Stop operation of operational amplifiers 1 and 2 Note For details of the function refer to ADPCM SP Sound Compression Expansion Software Package 78KOR Microcontroller User s Manual Playback ends Caution Do not allow any other processing to interrupt until the processing to play back ADPCM data is completed Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS This chapter describes how to set up peripheral hardware macros timer array unit 0 voltage reference operational amplifiers and D A converter It also provides software coding examples and details about playback processing For other initial settings refer to the 78KOR Kx3 Sample Program Initial Settings LED Lighting Switch Control Application Note For how to set register refer to the User s Manual For assembler instructions refer to the 78KOR Microcontroller Instructions User s Manual 4 1 Setting to Use Peripheral Hardware Macros Use of the peripheral hardware macros is specified by using the following register e Peripheral enable register 0 PERO 1 Peripheral enable register 0 PERO This register is used to enable or disable use of each peripheral hardware macro Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise PERO can be set by a 1 bit or 8 bit memory manipu
57. ampling frequency 8 kHz number of quantized bits 4 The ADPCM data table TPLAYDATA table in an assembly language and the size of the ADPCM data table are defined in data playrom asm which must be externally referenced Clear the higher 4 bits of the final data of the ADPCM table to O so that the amplitude of the sound data output from the D A converter is O To use the ADPCM library function the function must be externally referenced Externally reference the function by prefixing to the function name as shown below adpcm init adpcm 132 dec When the ADPCM library function is used a C routine is called For how to call the C routine from an assembly language refer to CC78KOR C Compiler Language User s Manual Application Note U20028EJ1VOAN 39 CHAPTER 4 SETTING METHODS The multiplier divider is used in the multiplication mode during processing for expanding the ADPCM library function Immediately before calling the expansion processing therefore set the operation mode of the multiplier divider to the multiplication mode The ADPCM library used in this sample program is for the 78KOR Kx3 Therefore the operation mode is not changed during expansion processing For details of the ADPCM library function refer to ADPCM SP Sound Compression Expansion Software Package 78KOR Microcontroller User s Manual SPLAYDAC tty LOWW TPLAYDATA Set start playing addr low 16 bits d ES HIGHW TPLAYDATA Se
58. ational Amplifier Control Register OAC loo o j o o oae oa ORENO OAEN1 Operational amplifier 1 operation control lo Stops operational amplifier 1 operation 13 Enables operational amplifier 1 operation OAEN2 Operational amplifier 2 operation control o Stops operational amplifier 2 operation Enables operational amplifier 2 operation Cautions 1 Use the ADPC register to specify as analog inputs the pins to be used with operational amplifiers 2 When using as digital inputs the pins of ports 2 and 15 which are not used with operational amplifiers when the operational amplifiers are used make sure that the input levels are fixed 3 Be sure to clear bits 7 to 3 to 0 Remark The values written in red in the above figure are specified in this sample program 24 Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS 2 A D port configuration register ADPC This register switches the ANIO AMPO P20 to ANI7 AMP20 P27 ANI8 AMP2 P150 to ANI10 P152 and ANI15 AVrerm P157 pins to analog input of A D converter or digital I O of port Set pins to be used with operational amplifiers to the analog input Figure 4 9 Format of A D Port Configuration Register ADPC oo o o ApPc4 ADPC3 ADPC2 ADPC1 ADPCO PC PC PC PC PC Pott5 15 Port 2 ANI15 ANI10 ANI9 ANI8 ANI7 ANI6 ANI5 ANI4 ANIS ANI2 ANI1 ANIO AVnere P152 P151 AMP2 AMP20 AMP2
59. both the start trigger and capture trigger 1 Both the edges of Tlpq pin input signal fsus 2 fsus 4 or INTRTC1 are used as a start trigger and a capture trigger 1 Interrupt signal of the master channel is used when the channel is used as a slave channel with the combination operation function Other than above Setting prohibited MASTEROA Selection of slave master of independent operation or combination operation function of channel 4 Operates as slave channel with independent operation or combination operation function Operates as master channel with combination operation function Only the even channel can be set as a master channel MASTER04 1 Be sure to use the odd channel as a slave channel MASTERO4 0 Clear MASTERO4 to 0 for a channel that is used with the independent operation function Selection of count clock TCLK of channel 4 Operation clock MCK specified by CKS04 bit 1 Valid edge of input signal input from Tlpq pin fsus 2 fsus 4 or INTRTC1 the timer input used with channel 4 is selected by using TISO register Count clock TCLK is used for the timer counter output controller and interrupt controller Selection of operation clock MCK of channel 4 Operation clock CKOO set by TPSO register 1 Operation clock CK01 set by TPSO register Operation clock MCK is used by the edge detector A count clock TCLK is generated by setting CCS04 bit Remark The values written in red in the above
60. converter Enabling the operation of channel 4 of timer array unit O Initializing a counter that reads the ADPCM data The ADPOM data is read its lower 4 bits are expanded and modified and the resultant data is output from b c d e f the D A converter a Reading the ADPCM data and expanding the lower 4 bits to signed 16 bit data by using an ADPCM library function Adding 8000H to the expanded signed 16 bit data to modify it to unsigned 16 bit data c Shifting the modified unsigned 16 bit data two times to the right to modify it to unsigned 12 bit data Setting the modified unsigned 12 bit data to D A conversion value setting register WO DACSWO e Waiting until the data set to D A conversion value setting register WO DACSWO is output from the D A converter The ADPOM data is read its higher 4 bits are expanded and modified and the resultant data is output from the D A converter The details of this processing are the same as steps a to e in 2 above The counter that reads the ADPCM data and the position of reading the ADPCM data are updated Steps 3 to 5 are repeated until all the ADPCM data defined in the ROM area are output The operation of the hardware is stopped as playback end processing a Stopping the operation of channel 4 of timer array unit O b Stopping the operation of the D A converter c Stopping the operation of operational amplifiers 1 and 2 The ADPOM data to be played back is of 32 kbps s
61. eference static void fn_InitAmp void Setting of Operational amplifier static void fn_InitDac void Setting of D A Converter SS a IET erred cA Mu oS cae Extern variables constants Application Note U20028EJ1VOAN 77 APPENDIX A PROGRAM LIST extern const unsigned char aPlayData Sound data extern unsigned short ushDataSize Size of sound data So iE eL CEU POP ac tU Rer E ms A aE ain ea abs es DELIS Se Yee ad ERE TERT ek seat ech Sc Seek CE Heh gp spe POE UE Tem oio uon Local constants DC ed ceed eye es eS oe ee r eP m A AE AA NAS AI RU NOAA teed MAN ANO IA ec ed GUN ek Dal tel ie Docs hems fe St A A E Global variables A OVI MY WR PER Er RR VPE dt en GER merui uS russi on ies uy rupis ded cu om E PAR ai uo ee E eig enr E cd pee ao Gn Rh ces E ud E O au Bat Dep aite euh a doen sa sui a E e E E E p e Local variables T MO TORT PS RESET ca ata ea ah SPEC THEATRE SOS PS EE IE IS A TE EPOR EN IA DE A a SS RD RU a II O for play unsigned short ushAdpcmWork 16 Work area for ADPCM process ce em o Teo T cr ses Ste i cal Gas Aes eo P NE N Code Ef UOCE A A A A vw RP ERSCHIENEN NERO A SS A a IE a gna GY Ramee Pa A a th ch AE AMAS AE EN GS E MP TA EN O MS ER SR Mae st ele ca Hardware initialization NENA NA A MAI AR i
62. es Can be set in operation conversion mode 2 or 3 VREFOUT Stops operation E Stops operation voltage reference pull down output output Enables operation Enables Can be set in operation conversion mode 2 or 3 Stops operation pull down output Enables operation Can be set in conversion mode 2 or 3 Other than above Setting prohibited Note This is a function of the A D converter and is not used in this sample program Cautions and Remark are given on the next page 22 Application Note U20028EJ1VOAN Cautions 1 2 CHAPTER 4 SETTING METHODS Be sure to clear bits 6 to 4 and 2 to 0 During voltage reference operation be sure to connect a tantalum capacitor capacitance 10 HF 30 ESR 2 Q max ESL 10 nH max and a ceramic capacitor capacitance 0 1 UF 30 96 ESR 2 Q max ESL 10 nH max to the Vnerour AVnere pin for stabilizing the reference voltage Furthermore do not apply a voltage from the Vnerour AVnere pin during voltage reference operation To use voltage reference output VnErour to the positive reference voltage of the A D converter ADrerr and the positive reference voltage of the D A converter DAner be sure to set VRON to 1 after setting VRSEL to 1 Rewriting DACSWn n 0 1 during A D conversion is prohibited when both the positive reference voltage of the A D converter ADrerP and the positive reference voltage of the D A converter DArerr are the voltage re
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64. ey interrupt request flag O E O Remove key input noise PEN PN re a EE E A ATEN BT P7 0 SLMAIN200 Key input No SET1 TSOL 0 Start TAUO CHO CLR1 TMIFOO Clear interrupt request flag LMAIN100 NOP BF TMIFOO SLMAIN100 Wait 10 msec CLR1 TMIFOO Clear interrupt request flag SET1 TTOL 0 Stop TAUO CHO BT P7 0 SLMAIN200 Key input No SP VOTUM NE QUIS MENS IA ESE Sail TS T EA E P Play melody x pM A bcbo Ro ce ur E Es CALL SPLAYDAC LMAIN200 e KKK KKKKKKK KKK KK KKK KKK ck ckck ck ck ck ck ck ck ck ckck ck ck ck k ck k KK 7 i p The main processing writes here bin pr if there is something Jus ek ck ck ck ck ok ck ck ck ck ckockckckck ck ck ck ckck ck ck ckck ck ck ck ck ck ckck ck ck ck ck ck ck k kk kk 7 1 56 Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST BR MMAIN Continue main process Module SINITPORT Description Setting of I O ports A parameter E A return y PE MOV PO 00000000B Set POO to P02 Output latches to Low MOV PMO 11111000B Set POO to P02 to output port POO to P02 Unused MOV Pl 00000000B Set P10 to P17 Output latches to Low MOV PM1 00000000B Set P10 to P17 to output port P10 to P15 Unused MOV P2 00000000B Set P20 to P27 Output latches to Low MOV PM2 11111111B Set P20 to P27 to input port PM23 filter circuit AMP1 PM24 filter circuit AMP10 PM25 filter circuit AMP1 P
65. ference output Vrerour VRSEL 1 and DAREF 1 Rewrite it when conversion operation is stopped ADCS 0 Do not change the output voltage of the reference voltage by using VRGV during the voltage reference operation VRON 1 Remark The values written in red in the above figure are specified in this sample program Application Note U20028EJ1VOAN 23 CHAPTER 4 SETTING METHODS 4 4 Setting Up Operational Amplifier The following four registers are used to set up the operational amplifiers Peripheral enable register 0 PERO e Operational amplifier control register OAC e A D port configuration register ADPC e Port mode registers 2 15 PM2 PM15 Example of procedure for setting up operational amplifiers to play back sound data lt 1 gt Set bit 5 ADCEN of peripheral enable register 0 PERO to 1 see 4 1 2 By using the ADPC register specify the pins to be used AMP1 AMP1 AMP10 AMP2 AMP2 AMP20 as analog input pins lt 3 gt By using the PM2 and PM15 registers set the pins to be used AMP1 AMP1 AMP10 AMP2 AMP2 AMP20 in the input mode 4 Enable operational amplifiers 1 and 2 to operate by setting the OAEN1 and OAEN bits of the OAC register to 1 5 Wait for about 20 ws until the operation of the operational amplifiers is stabilized 1 Operational amplifier control register OAC The OAC register controls the operations of operational amplifiers O to 2 Figure 4 8 Format of Oper
66. gger is invalid during counting operation At that time interrupt is not generated either Other than above Setting prohibited Application Note U20028EJ1VOAN 67 edge edge channel 4 trigger or INTRTC1 68 APPENDIX A PROGRAM LIST Be sure to set 00 Selection of TI04 pin input signal LI fSUB 2 SUB 4 or INTRTC1 valid edge LI the timer input used with channel 4 LLLI is selected by using TISO register 0 0 Falling edge II 0 1 Rising edge 1 0 Both edges when low level width is measured LI Start trigger Falling edge Capture trigger Rising 11 Both edges when high level width is measured Start trigger Rising edge Capture trigger Falling 4 4 Setting of start trigger or capture trigger of 000 Only software trigger start is valid other trigger sources are unselected 001 Valid edge of TI04 pin input signal fSUB 2 SUB 4 or INTRTC1 is used as both the start trigger and capture 010 Both the edges of TI04 pin input signal fSUB 2 SUB 4 or INTRTC1 areusedasastart trigger andacapturetrigger 100 Interrupt signal of the master channel is used when the channel is used as a slave channel with the combination operation function Other than above Setting prohibited T Selection of slave master of channel 4 0 Operates as slave channel with combina
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68. il it is rewritten Figure 4 5 Format of Timer Data Registers 00 04 TDROO TDR04 FFF19H TDROO FFF18H TDROO FFF69H TDRO4 FFF68H TDRO04 TNT AR A E ER NE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IE ES A A 4 Timer channel start register 0 TSO TSO is a trigger register that is used to clear a timer counter TCROn and start the counting operation of each channel When each bit TSOn of this register is set to 1 the corresponding bit TEOn of timer channel enable status register O TEO is set to 1 TSOn is a trigger bit and cleared immediately when TEOn 1 Figure 4 6 Format of Timer Channel Start Register 0 TSO o oj ojo o j o o 1807 1806 1808 rs04 7803 1802 Sot soo TS00 Operation enable start trigger of channel 0 0 No trigger operation 1 TEOO is set to 1 and the count operation becomes enabled TS04 Operation enable start trigger of channel 4 oo No trigger operation TE04 is set to 1 and the count operation becomes enabled Note n the interval timer mode nothing is performed until a count clock is generated after the start trigger has been detected TSOn 1 The value of TDROn is loaded to TCROn at the first count clock and counting down is performed at the following count clocks Caution Be sure to clear bits 15 to 8 to 0 Remarks 1 n 7to0 2 When the TSO register is read O is always read Application Note U20028EJ1VOAN 21 CHAPTER 4 SETTING M
69. ing of a key the X1 oscillator 20 MHz Channel 4 is set in the interval timer mode so that the sampling frequency for playing back Set up timer array unit O ADPCM data is 8 kHz Set up f The D A converter is set so that its reference voltage reference T M IOS 20V Set up operational amplifiers Set up D A converter Notes 1 The option byte is automatically referenced by the microcontroller immediately after a reset ends In this sample program the following settings are specified using the option byte e Disabling the watchdog timer e Setting the internal high speed oscillator frequency to 8 MHz e Disabling LVI from being started by default e Enabling on chip debug to operate 2 The general purpose registers of 78KOR LH3 are configured in four register banks so that the registers used for normal processing and those used when an interrupt occurs can be changed on a bank basis in order to create an efficient program In this sample program only register bank O is used Caution With the sample program of the C language version the settings of register banks and stack pointer are not described in the source program main c because they are made by the start up routine For details of the start up routine refer to the CC78KOR Operation User s Manual 10 Application Note U20028EJ1VOAN CHAPTER 3 SOFTWARE lt Main processing gt Processing overview When a key is input ADPCM data is played back The device i
70. input clock BE SFR used by the serial array unit 0 can be read and written Control of serial array unit 1 input clock 0 Stops input clock supply SFR used by the serial array unit 1 cannot be written The serial array unit 1 is in the reset status 1 Supplies input clock SFR used by the serial array unit 1 can be read and written Control of serial interface IICA input clock 0 Stops input clock supply SFR used by the serial interface IICA cannot be written The serial interface IICA is in the reset status 1 Supplies input clock SFR used by the serial interface IICA can be read and written Control of A D converter operational amplifier and voltage reference input clock 0 Stops input clock supply SFRused by the A Dconverter operational amplifier andvoltage reference cannot be written 82 Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST Jos The A D converter operational amplifier and voltage reference is in the reset status pe 1 Supplies input clock pe SFRused by the A Dconverter operational amplifier andvoltage reference can be read and written ES j Control of D A converter input clock 0 Stops input clock supply PR SFR used by D A converter cannot be written
71. ion of count clock TCLK of channel 0 0 Operation clock MCK specified by CKS00 bit 1 Valid edge of input signal input from TI00 pin fSUB 2 fSUB 4 or INTRTC1 the timer input used with channel 0 is selected by using TISO register ZELLE Be sure to set 00 fpes e Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST o Selection of operation clock MCK of channel 0 0 Operation clock CK00 set by TPSO register 1 Operation clock CK01 set by TPSO register CK00 fCLK 2 3 5 MHz gt 10 ms 0 2 us clk 50000 count TDROO 50000 1 Set interval time to 10 ms TMMKOO 1 Disable interrupt CH4 For play back sampling timing TMRO4 0b6b1000000000000000 Timer Mode Register 04 1 Operation mode of channel 4 yes 2 Count operation of TCR 3 Independent operation AUR 4 Setting of starting counting and interrupt 0000 1 Interval timer mode LA 2 Counting down L 3 Possible f 4 Timer interrupt is not generated when counting is started timer output does not change either d 0001 1 Interval timer mode je 2 Counting down 3 Possible Jos 4 Timer interrupt is generated when counting is started IR timer output also changes AX 7 Ke 0100 1 Capture mode As 2 Counting up E 3 Possible
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73. l O 0 o Only software trigger start is valid other trigger sources are unselected 1 Valid edge of Tlpq pin input signal fsus 2 fsus 4 or INTRTC1 is used as both the start trigger and capture trigger 1 Both the edges of Tlpq pin input signal fsus 2 fsus 4 or INTRTC1 are used as a start trigger and a capture trigger pp Interrupt signal of the master channel is used when the channel is used as a slave channel with the combination operation function Other than above Setting prohibited MASTEROO Selection of slave master of independent operation or combination operation function of channel O zz Operates as slave channel with independent operation or combination operation function Operates as master channel with combination operation function Only the even channel can be set as a master channel MASTEROO 1 Be sure to use the odd channel as a slave channel MASTEROO 0 Clear MASTEROO to 0 for a channel that is used with the independent operation function o Operation clock MCK specified by CKSOO bit 1 Valid edge of input signal input from Tlpq pin fsus 2 fsus 4 or INTRTC1 the timer input used with channel 0 is selected by using TISO register CCS00 Selection of count clock TCLK of channel 0 Count clock TCLK is used for the timer counter output controller and interrupt controller ET o Operation cock CK00setby TPSO register SSCS Remark The values written in red in the above figu
74. lation instruction Figure 4 1 Format of Peripheral Enable Register 0 PERO RTCEN DACEN ADCEN IICAEN SAU1EN SAUOEN TAU1EN TAUOEN TAUOEN Control of timer array unit O input clock 0 Stops input clock supply 1 Supplies input clock Control of A D converter operational amplifier and ADCEN voltage reference input clock 0 Stops input clock supply 1 Supplies input clock Control of D A converter input clock Stops input clock supply Supplies input clock Remark The values written in red in the above figure are specified in this sample program Application Note U20028EJ1VOAN 13 CHAPTER 4 SETTING METHODS 4 2 Setting Up Timer Array Unit 0 14 The following five registers are used to set up timer array unit O Peripheral enable register O PERO e Timer clock select register O TPSO e Timer mode registers 00 04 TMROO TMRO4 e Timer data registers 00 04 TDROO TDR04 e Timer channel start register 0 TSO Example of procedure for setting up timer array unit 0 to play back sound data 1 2 3 4 5 6 Set bit O TAUOEN of peripheral enable register O PERO to 1 see 4 1 Set CKOO to fc k 2 and CKO1 to fc by using timer clock select register O TPSO Select CKOO as the operating clock of channel O and the interval timer mode as the operation mode by using timer mode register 00 TMROO Set the interval of channel 0 to about 10 ms by
75. le operation of operational OAC 1 amplifiers 1 and 2 when operational OAC 2 amplifiers are to be used Use amplifier stabilizes 20 us max for loop 40 ay loop gt 0 loop NOP Wait for about 20 ws until operation of operational amplifier is stabilized l Application Note U20028EJ1VOAN 37 CHAPTER 4 SETTING METHODS lt 4 gt Setting up D A converter static void i fn InitDac void Set real time output mode as operation mode of DAM 0501000101 channel 0 of D A converter resolution of 12 bits and Vnerour as positive reference voltage source of D A converter eee Omitted e e o Specify default value of analog DACSWO 0x0800 voltage to be output from ANOO Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS 4 7 Playback Processing This section explains playback processing As playback processing in an assembly language the following operations are performed 1 2 lt 3 gt lt 4 gt lt 5 gt lt 6 gt As preparations for playback the ADPCM library and variables are initialized and the hardware is enabled to operate a Specifying the start address of the ADPCM data table TPLAYDATA table defined in the ROM area as the position of reading ADPCM data Calling initialization processing to use the ADPCM library functions Enabling the operations of operational amplifiers 1 and 2 Enabling the operation of the D A
76. low Vo RC filter 0 0039 u 1 i I 330p i I L 0 0082u Presse soc ose Ss eo 4 C La i A Secondary lowpass filter U oS KRO L L 43K i L L LI VREFOUT 150p 0 1 uF Pese QOL UM ndr t E L doge aca 2 0 1u VR 1K 0 1u 78KOR LH3 E T fero microcontroller Owetzamplier peaker LM4890M 0 47 to 1 uF 20 MHz CJ Cautions 1 Use the microcontroller at a voltage in the range of 2 7 V lt Vpp lt 5 5 V 2 Make EVpp AVppo and AVpp the same potential as Vpp 3 Make AVss the same potential as EVss or Vss and connect it directly to GND 4 During voltage reference operation be sure to connect a tantalum capacitor capacitance 10 HF 30 ESR 2 Q max ESL 10 nH max and a ceramic capacitor capacitance 0 1 uF 30 ESR 2 Q max ESL 10 nH max to the Vnerour AVnere pin for stabilizing the reference voltage Furthermore do not apply a voltage from the Vrerout AVrere pin during voltage reference operation Cautions are continued on the next page Application Note U20028EJ1VOAN 5 CHAPTER 2 CIRCUIT DIAGRAM 5 Connect REGC to Vss via a capacitor 0 47 to 1 uF 6 Handle unused pins that are not shown in the circuit diagram as follows e I O ports Set them to output mode and leave them open unconnected e Input ports Connect them independently to Voo or Vss via a resistor 7 In this sample program the P40 TOOLO and P41 TOOL1 pins are used for on chip debugging 8 An on chip pull
77. lt 4 gt Setting up D A converter DAM 01000101B e e o Omitted e e o DACSWO 0800H Set real time output mode as operation mode of channel 0 of D A converter resolution of 12 bits and VnErour as positive reference voltage source of D A converter Specify default value of analog voltage to be output from ANOO Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS 2 C language lt 1 gt Setting up timer array unit 0 static void fn_InitTau0 void TPSOL 0b00000010 Timer Clock Select Register 0 Set CKOO to fcLk 2 e Omitted and CKO1 to fcuk CHO Fob timing os Specify CK00 as operating clock of channel 0 and interval timer mode as operation mode TMROO 0b0000000000000000 e e o Omitted e e e Set interval of channel 0 i to about 10 ms setting up o channel O CKO0 ECLK 2 3 5 MHz gt 10 ms 0 2 us cue 50000 egune TDROO 50000 1 Set interval time to 10 ms Mask timer interrupt of channel 0 Specify CK01 as operating clock of channel 4 and interval timer mode as operation mode 0b1000000000000000 e e o Omitted e e o Set interval of channel 4 Setting up o to 125 us 8 kHz channel 4 ESCROW Chk TDRO4 2500 1 ae Mask timer interrupt of channel 4 TMMK04 1 Disable Application Note U20028EJ1VOAN 35 36 CHAPTER 4 SETTING METHODS lt 2 gt Setting up voltage reference
78. n use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics
79. nce voltage supply negative side of A D converter selection PERO AVSS E7 1 AVREFM external voltage reference input ADVRC 0 1 Enables operation ADVRC 1 1 Output 2 0 V Wait for settling time to 20 ms over 17 msec TSOL O 1 Start TAUO CHO for work 2 work gt 0 work Wait 10 msec 2 Application Note U20028EJ1VOAN 97 APPENDIX A PROGRAM LIST TMIFOO 0 Clear interrupt request flag while TMIFOO NOP Wait 10 msec TMIFOO 0 Clear interrupt request flag TTOL O 1 Stop TAUO CHO j poo nm Module fn_InitAmp Description Setting of Operational amplifier parameter AR return el A A A E E ese he Sea cokes static void fn_InitAmp void ADPC 0b00000000 A D Port Configuration Register Analog input A digital I O D switching Zee es 4 ANI15 AVREFM P157 zT s 4 ANI10 P152 ANI8 AMP2 P150 ANI7 AMP20 P27 ANIO AMPO P20 l 00000 AAAAAAAAAAAA l 00001 AAAAAAAAAAARD l 00010 AAAAAAAAAADD l 00011 AAAAAAAAAD DoD l 00100 AAAAAAAADDDD l 00101 AAAAAAADDDDD S SA 00110 AAAAAADDDDDOD l 00111 AAAAADDDODODDD l 01000 AAAADDDDODDDD Je 01001 AAADDDDDDDDD z 01010 AADDDDDDDDDD
80. ode output buffer on as Input mode output buffer off Caution Ifa pin is set as an analog input port not the pin level but 0 is always read Remark The values written in red in the above figure are specified in this sample program Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS The AMP1 ANI3 P23 AMP10 ANI4 P24 AMP1 ANI5 P25 AMP2 ANI6 P26 AMP20 ANI7 P27 and AMP2 ANI8 P150 pins are as shown below depending on the settings of ADPC ADS PM2 PM15 OAENn bit and ADREF bit Table 4 1 Setting Functions of ANI3 AMP1 P23 ANI5 AMP1 P25 ANIG AMP2 P26 and ANI8 AMP2 P150 Pins ADPC PM2 PM15 OAENn ADS Register Setting Functions of ANI3 AMP1 P23 Register Registers Bit ANI5 AMP1 P25 ANI6 AMP2 P26 and ANI8 AMP2 P150 Pins 4 4 Digital 1 O Input mode Digital input Setting prohibited selection Output mode i a E s s CTE a p sn rias Fw Setting prohibited Output mode Remarks 1 n 1 2 2 The values written in red in the above figure are specified in this sample program Caution When an operational amplifier is used AMPn AMPn and AMPnO pins are used so the alternative analog input functions cannot be used Table 4 2 Setting Functions of ANI4 AMP10 P24 and ANI7 AMP20 P27 Pins Register Registers Bit and ANI7 AMP20 P27 Pins selection Does not select ANI Does not select ANI Analog input Input mode DN Selects ANI Analog input to be converted Remarks
81. of PCM data AX Pop argument MOVW AX Be Get decompression data Adjust play data AX 8000H Adjust sign AX 16 12 Right align data JPDAC220 MOVW DACSW0 AX Set play data Waiting for the output to be completed NOP BF TMIF04 SJPDAC230 The output to be completed No CLR1 TMIFO4 Clear interrupt request flag ckck ck ck ck ck ck ck ck ck ck ck k ck k kk kk kkt 1 f P Play high 4bit a ckck ck ckck ck ck ck ck ck ck ck k ck k kk kk kkt r Decompression of ADPCM data high 4 bits 16 bits MOVW AX LOWW RADPCMWORK Set work area for _adpcm_132_dec PUSH Push argument ES HL Get compressed data HR 4 A LRB LR1 DIVMODE Set multiplication mode for _adpcm_132_dec CALL adpcm 132 dec Decompression of PCM data POP AX Pop argument MOVW AX B Get decompression data Adjust play data AX 8000H Adjust sign AX 16 12 Right align data DAC270 MOVW DACSWO AX Set play data Waiting for the output to be completed MIF04 SJPDAC280 The output to be completed No l MIF04 Clear interrupt request flag Application Note U20028EJ1VOAN 41 CHAPTER 4 SETTING METHODS 42 Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS Playback processing in C performs operations similar to those of processing in an assembly language The ADPCM data table aPlayData table in C and the size of the ADPCM data table are defined in
82. ontrol of input gate voltage boost circuit for A D converter 14111 5 Relationship with the conversion mode used LEA 000 1 AVREFP external voltage reference input 2 Stops operation Hi Z A 312 5 V l 4 Stops operation l 5 Can be set in conversion mode 1 ZR AN 010 1 AVREFP external voltage reference input 2 Stops operation Hi Z 00 312 0 V l 4 Enables operation l 5 Can be set in conversion mode 2 or 3 Te y 96 Application Note U20028EJ1VOAN aT APPENDIX A PROGRAM LIST 100 1 VREFOUT voltage reference output AE 2 Stops operation pull down output 3 2 5 V y 4 Stops operation via 5 mY sy JE 101 1 VREFOUT voltage reference output 2 Enables operation jt 3 2 5 V 4 Enables operation ee 5 Can be set in conversion mode 2 or 3 haa JX 1 1 0 1 VREFOUT voltage reference output AA 2 Stops operation pull down output 312 0 V 4 Enables operation L 5 9 4 pt ef 111 1 VREFOUT voltage reference output 2 Enables operation 3 12 0 V 4 Enables operation Jet 5 Can be set in conversion mode 2 or 3 ye Other than the above Setting prohibited E Be sure to set 0000 fx 4 Refere
83. onverter DAM can be set by a 1 bit or 8 bit memory manipulation instruction Figure 4 12 Format of D A Converter Mode Register DAM 0 DAREF DACE1 DACEO DARES1 DARESO DAMD1 DAMDO NENNEN DAMDO Selection of D A converter 0 operation mode o romam za Real time output mode DARESO Selection of D A converter 0 resolution o fsb od ETS DACEO Control of D A converter 0 conversion operation o Stops conversion operation Enables conversion operation DAREF Positive reference voltage supply selection of D A converter o Ww S 3 Vnerour AVrerP Notes 1 The reference voltage of the D A converter cannot be specified separately for each channel because it is common to both channels 2 To use an output voltage of the voltage reference for the positive reference voltage of the D A converter DArerr start operating the voltage reference before setting the D A conversion operation refer to the 78KOR Lx3 User s Manual Furthermore do not change the voltage reference setting during the D A conversion operation Remarks 1 The values written in red in the above figure are specified in this sample program 2 The positive reference voltage of the D A converter is as follows according to the DAREF VRSEL and VRON settings Table 4 3 Settings of DAREF VRSEL and VRON AVop1 Positive Reference Voltage of D A Converter DArerr AVnerP VREFOUT
84. operational amplifier and be read and written Control of D A converter input clock 0 Stops input clock supply SFR used by D A converter cannot be written The D A converter is in the reset status 1 Supplies input clock SFR used by the D A converter can be read and written Control of real time counter RTC input clock 0 Stops input clock supply Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST SFR used by the real time counter RTC cannot be written gt The real time counter RTC is in the reset status 1 Supplies input clock P SFR used by the real time counter RTC can be read and written Initialize of Key Interrupt Function i CALL SINITKR CALL SINITTAUO Initialization of voltage reference CALL SINITVR Initialization of Operational amplifier CALL SINITAMP ek ck ck ck ck ck ck KKK KKK KKK KEKE ck ck ck ck ck ck ckck ck ckck k ck ck k ck k ck k kk kk 7 1 7 t 7 Play melody when the key is input Er Application Note U20028EJ1VOAN 55 APPENDIX A PROGRAM LIST ex ko H H ek ck ckck ck ck ck ckckockckckckock ck ck ck ckckck ck ck ck ck ck ck ckck ck ckck ck ck ck k ck k ck kk kk H A cre Pcr Wait key input K O AE eid sau CLR1 KRMK Clear key interrupt CLR1 KRIF Clear key interrupt request flag HALT Sets the HALT mode SET1 KRMK Set key interrupt CLR1 KRIF Clear k
85. playing back ADPCM data to 8 kHz e Setting up voltage reference e Selecting the voltage reference as a reference voltage source e Setting the output voltage of voltage reference to 2 0 V e Using channel 0 of timer array unit O to wait for about 20 ms until the operation of the voltage reference is stabilized e Setting up operational amplifiers 1 and 2 e Setting up D A converter e Selecting the real time output mode as the operation mode e Setting the resolution to 12 bits e Selecting Vrerout AVrerr pin as the voltage reference source of the D A converter Note For details of the low voltage detector refer to the User s Manual Application Note U20028EJ1VOAN 3 CHAPTER 1 OVERVIEW 2 Contents following main loop After initial settings have been completed the microcontroller is put in the HALT mode The HALT mode is released by occurrence of interrupt INTKR Chattering of keys is avoided and whether a key is being input is decided If a key is being input ADPCM data is played back Note that the ADPCM data to be played back is of 32 kbps sampling frequency 8 kHz number of quantized bits 4 If key input is not detected or after ADPCM data has been played back the device is put in the HALT mode again Application Note U20028EJ1VOAN CHAPTER 2 CIRCUIT DIAGRAM This chapter provides a circuit diagram and describes the devices used in this sample program other than the microcontroller 2 1 Circuit Diagram A circuit diagram is shown be
86. pplication Note U20028EJ1VOAN 20 us max rh APPENDIX A PROGRAM LIST Decode and play PCM data RRR kckckckck kk ko kckokokckckckckckckckckockckck RR RRA RRA for ushPlayCount 0 ushPlayCount lt ushDataSize ushPlayCount f EEkek kk kc k ko ko ko kc kk kk ke ke ke e k x 1E Play low 4 bits KY RRR RKERKKKRE KKK KKK KKK KKK Decompression of ADPCM data low 4 bits gt 16 bits DIVMODE 0 Set multiplication mode for _adpcm_132_dec ushData unsigned short adpcm_132_dec pucPlayData ushPlayCount amp OxOf ushAdpcmWork Adjust sign amp right align data ushData unsigned short ushData 0x8000 gt gt 16 12 Set play data DACSWO ushData Waiting for the output to be completed while TMIFO4 NOP j TMIF04 0 Clear interrupt request flag f Rkk k kk kc kok ko kc kk kk ck ke ke e k x Play high 4 bits RRRRRRREERERKEREREE e ek ke Decompression of ADPCM data high 4 bits 16 bits DIVMODE 0 Set multiplication mode for adpcm 132 dec ushData unsigned short adpcm 132 dec pucPlayData ushPlayCount gt gt 4 amp OxOf ushAdpcmWork Adjust sign amp right align data ushData unsigned short ushData 0x8000 gt gt 16 12 Set play data DACSWO ushData Waiting for the output to be completed Application Note U20028EJ1VOAN 101 APPENDIX A PR
87. products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics Application Note 78KOR LH3 ENESAS Sample Program Sound Output Playing Back Sound Data by Using D A Converter and Operational Amplifier This application note describes how to output ADPCM format sound data by using a 12 bit D A converter The ADPCM data is transferred at 32 kbps when sampled at 8 kHz and quantized with 4 bits Target devices 1PD78F1506 78F 1507 78F1508 Document No U20028EJ1VOANOO 1st edition Date Published September 2009 N NEC Electronics Corporation 2009 Printed in Japan CONTENTS CHAPTER 1 OVERViE Wenn anna rra arar 3 CHAPTER 2 CIRCUIT DIAGRAM enne crn orcas 5 2 1 Circut Dia Grain iii aris eree ai ENEAN 5 2 2 Used Devices Other than Microcontroller 2 3 Pin Function List esee CHAPTER 3 SOFTWARE seeseessese etes tnsens tnn ttn atenta sanata atn a tasa taa tna tua Silt Included Elles ennt tte ette tae 3 2 Internal Peripheral Functions to Be Used 9 8 Initial Settings and Operation Overview 3 4 Flow Chart tenentes CHAPTER 4 SETTING METHODS 4 1 Setting to Use Peripheral Hardware Macros 4 2
88. rates as slave channel with combination operation function L 1 Operates as master channel with combination operation function EX ous USE Selection of count clock TCLK of channel 0 f 0 Operation clock MCK specified by CKS04 bit Jk 1 Valid edge of input signal input from TI04 pin fSUB 2 SUB 4 or INTRTC1 the timer input used with channel 4 is selected by using TISO register A le Be sure to set 00 FEY oc Selection of operation clock MCK of channel 4 Application Note U20028EJ1VOAN 95 APPENDIX A PROGRAM LIST 0 Operation clock CK00 set by TPSO register 1 Operation clock CK01 set by TPSO register CK01 CLK 2 20 MHz gt 8 kHz 0 125 ms 0 05 us clk 2500 count TDRO4 2500 1 Set interval time to about 125 us 8 kHz TMMKO4 1 Disable interrupt j E aoe A Ree Sa eet el e s Module fn InitVr E Description Setting of Voltage reference El ee parameter return x a static void fn_InitVr void unsigned char work ADVRC 0500001000 Analog reference voltage control register 1 Positive reference voltage supplies selection of A D and D A converters z 2 Operation control of voltage reference l 3 Output voltage selection of voltage reference 4 Operation c
89. rational amplifiers and D A converter in the sample program are shown below as a software coding example 1 Assembly language lt 1 gt Setting up timer array unit 0 SINITTAUO MOV TPSOL 00000010B Timer Clock Select Register 0 Set CKOO to fcLk 2 Xx Omitted lolo and CK01 to feck 7 CHO For timing MOVW AX 0000000000000000B Timer Mode MOVW TMR00 AX Specify CK00 as operating clock of channel 0 and interval timer mode as operation mode Setting up o eS channel 0 CK00 fCLK 2 3 5 MHz gt 10 Set interval of channel O to about 10 ms MOVW TDROO 50000 1 Set int SET1 TMMKO00 Mask timer interrupt of channel 0 CH4 For play back sampling timing MOVW AX 1000000000000000B Timer Mode MOVW TMRO4 AX Specify CK01 as operating clock of channel 4 and interval timer mode as operation mode Setting up o VUES ses channel 4 CK01 fCLK 2 20 MHz 8 Set interval of channel 4 2500 count to 125 us 8 kHz MOVW TDR04 2500 1 t 8 kHz 5 Mask timer interrupt of channel 4 Application Note U20028EJ1VOAN 31 CHAPTER 4 SETTING METHODS 32 lt 2 gt Setting up voltage reference SINITVR MOV e e o Omitted e e e Wait for settling time to 20 ms MOV SET1 JINIVR100 CLR1 JINIVR200 NOP BF ADVRC 00001000B Specify VnErFour voltage reference output Select 2 0 V as reference voltage of D A converter as ou
90. re are specified in this sample program Application Note U20028EJ1VOAN 17 CHAPTER 4 SETTING METHODS Figure 4 3 Format of Timer Mode Register 00 TMROO 2 2 CKS CCS MAST STS STS STS CIS CIS MD MD MD MD 00 00 EROO 002 001 000 001 000 003 002 001 000 Operation mode MD000 Setting of starting counting and interrupt set by MD003 to MDO01 e Interval timer mode Timer interrupt is not generated when counting is started timer output does not change either 1 Timer interrupt is generated when counting is started timer output also changes e Event counter mode Timer interrupt is not generated when counting is started timer output does not change either e One count mode Start trigger is invalid during counting operation At that time interrupt is not generated either Note Start trigger is valid during counting operation At that time interrupt is also generated e Capture amp one count mode Timer interrupt is not generated when counting is started timer output does not change either Start trigger is invalid during counting operation At that time interrupt is not generated either Other than above Setting prohibited MD003 MD002 MD001 MD000 Operation mode of channel O Count operation of TCR Independent operation o o o Trainer meno Counangaown Posse o 1 o capture mode Counting up ossi o 1 1 o event counter mode Counting down Possiie a o o
91. rval timer mode 2 Counting down 3 Possible 4 Timer interrupt is not generated when counting is started timer output does not change either 0001 1 Interval timer mode 7 2 Counting down 3 Possible 4 Timer interrupt is generated when counting is started timer output also changes A 0100 1 Capture mode i 2 Counting up 3 Possible 4 Timer interrupt is not generated when counting is started timer output does not change either 0101 1 Capture mode i 2 Counting up 3 Possible Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST 4 Timer interrupt is generated when counting is started timer output also changes 0110 1 Event counter mode 2 Counting down 3 Possible 4 Timer interrupt is not generated when counting is started timer output does not change either 1000 1 One count mode 2 Counting down 3 Impossible 4 Start trigger is invalid during counting operation At that time interrupt is not generated either 1001 1 One count mode 2 Counting down 3 Impossible 4 Start trigger is valid during counting operation At that time interrupt is also generated 1100 1 Capture amp one count mode 2 Counting up 3 Possible 4 Timer interrupt is not generated when counting is started timer output does not change either Start tri
92. s ds s Nel Gs fe Sap Sah a INTERNAS Se ested NN Se EE aah ome RR rok td ESAS void hdwinit void DI Disable all interrupts A T UPS S SU HT PT PRIORES Sigel solar Was werent seb Pett en EN Initialization of port ERAS MIE uu cR Wir Pert Tore TOK te Ses saga Rsk Pad a steel ac EE ms a o a SR a RUP PEE cR eS Low voltage detection A IPIE BRUT T e MD ie Sa eal oan ah MES DP SPEC PE RE aa SII eh aaa od tl eet fn InitLvi Ensures 2 7 V to VDD E lar av eo os a id Vaan Us a de gis eto gg ah esc bi Sees eh SIN Initialization of clock y mcd do eke ux pie SACD a ma cs s a aene MU Cal aai e mes ams ie Sl utc es il ly SE s es ne 78 Application Note U20028EJ1VOAN CMC Ji Y A ja jx z ja z y us jx T z me pe jx T7 3x z m A je jx js z 5 fa a m T ps APPENDIX A PROGRAM LIST 0501000011 Clock Operation Mode Control Register el od y Control of high speed system clock oscillation frequency 0 2 MHz lt fMX lt 10 MHz 1 10 MHz lt fMX lt 20 MHz XT1 oscillator oscillation mode selection 00 Low consumption oscillation 01 Normal oscillation 1x Super low consumption oscillation x don t care paisas Be sure to set 0 1 Subsystem clock pin operation mode 2 XT1 P123 pin and XT2 P124 pin 0 1 Inp
93. s in the HALT mode until interrupt INTKR is generated The device is released from the HALT mode when the INTKR interrupt is generated waits for about 10 ms to avoid chattering of a key and decides whether a key is being input If a key is being input processing to play back ADPCM data is called Enter the HALT mode Key being input Wait for 10 ms Key being input Playback of ADPCM data Application Note U20028EJ1VOAN 11 CHAPTER 3 SOFTWARE lt Playback processing gt Processing overview ADPCM data defined in the ROM area is expanded by an ADPCM library function and modified to 12 bit data This data is output from the D A Start converter The ADPCM data defined in the ROM area is of 32 kbps sampling frequency 8 kHz number of quantized bits 4 Enable operational amplifiers 1 and 2 to operate Enable channel 4 of TAUO to operate Start operation of D A converter Read lower 4 bits of ADPCM data T Output Expand lower 4 bits of lower of ADPCM data 4 bits Modify expanded data to 12 bit data and set it to D A converter Wait until data is ADPOM library function adocm 132 dec is used Note Read higher 4 bits of ADPCM data Expand higher 4 bits of ADPCM data Output Modify expanded data of higher to 12 bit data and set it 4 bits to D A converter Stop operation of channel 4 of TAUO W
94. s of NEC Electronics or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product
95. stabilization NOP Roo iO dit TOn 22 222 009 ohana Ss ciu coe Sah See es wee To increase fCLK to 10 MHz or higher set FSEL to 1 then change fCLK after two or more clocks have elapsed CKC 0000010000 System Clock Control Register Selection of CPU peripheral hardware clock fCLK Jes 00x000 IH 002x001 fIH 2 default 000x010 fIH 2 2 zj 00x01 1 fIH 2 3 00x 100 fIH 2 4 Le e c 00x10 1 fIH 2 5 fx c 01x000 fMX P2 01x00 1 fMX 2 Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST es O1x 0210 MX 2 2 A5 O1x 02121 MX 2 3 EX zo qx E 00 00 fMX 2 4 pe OR 60 LL EMILIA Jos y A SOV e ESUBE 7 Z 1x 1x x x fSUB 2 X Other than above Setting prohibited LF x don t care 2s EL JR a Status of Main system clock fMAIN 0 Internal high speed oscillation clock fIH 1 High speed system clock fMX T Se 4 Status of CPU peripheral hardware clock fCLK 0 Main system clock fMAIN 1 Subsystem clock fSUB Confirming the CPU clock status while CLS O MCS 1 NOP CPU is operating on a High speed system clock HIOSTOP 1 Internal high speed oscillation stopped OSTS 0500000111 Oscillation Stabilization Time Select Register 5
96. static void fn_InitVr void Specify VnErour voltage reference output as reference voltage of D A converter ADVRC 0b00001000 Analog reference voltage control register Select 2 0 V as output eee Omitted e voltage of voltage reference Enable operation of voltage reference Wait for settling time to 20 ms over 17 msec TSOL 0 1 Start TAUO CHO for work 2 work gt 0 work Wait 10 msec 2 TMIFOO 0 Clear interrupt request flag while TMIFOO NOP Wait 10 msec mois d 5 Wait for about 20 ms until P operation of voltage reference is stabilized TMIF00 0 Clear interrupt request flag TTOL O 1 Stop TAUO CHO Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS lt 3 gt Setting up operational amplifiers static void fn_InitPort void e e o Omitted e e o PM2 0b11111111 Set P20 to P27 to amput port Set P23 to P27 and P150 in e e o Omitted input port mode for operational amplifier input output PM15 0b11111111 Set P150 to P152 and P157 to input port e e o Omitted e e o static void ii fn Initamp void Set pins used for operational amplifier input output AMP1 AMP1 AMP10 AMP2 AMP2 ADPC 0b00000000 and AMP20 in analog input mode e e o Omitted e o o Stop operation of operational amplifiers 1 and 2 as default assumption disable Enab
97. t sion About 30 us About 30 us igher ower gt it gt P1 playback processing A P2 playback processing D A converter starts operating TAUO CH4 starts operating Pn playback processing D A converter stops operating TAUO CH4 stops operating Caution Clear the higher 4 bits of the final data of the ADPCM table to 0 so that the amplitude of the sound data output from the D A converter is 0 Remarks 1 2 3 n Size of ADPCM data table Pm ADPCM data of 1 byte in ADPCM data table Default value D 800H DmL Expanded and modified value of lower 4 bits of Pm DmH Expanded and modified value of higher 4 bits of Pm Default value A Analog voltage output when the set value of DACSWO is default value D 800H Amk Analog voltage output when the set value of DACSWO is Dmk m 1 to Size of ADPCM data table k L H Application Note U20028EJ1VOAN 45 CHAPTER 5 RELATED DOCUMENTS RA78KOR Assembler Package User s Manual omen EI 46 ADPCM SP Sound Compression Expansion Software Package 78KOR Microcontroller User s PDF Manual LN PM Project Manager User s Manual Application Note U20028EJ1VOAN APPENDIX A PROGRAM LIST As a program list example the source program is shown below However the source program of data_playrom asm and data_playrom c that define the ADPCM data table is omitted main asm assembly language version 1
98. t start playing addr high 4 bits JPDAC100 b lease MOVW AX LOWW RADPCMWORK adpcm init ADPCM process Initialization i Operational amplifier setting 9 SETI AG Operational amplifier AMP1 enable TE SETI OAC 2 Operational amplifier AMP2 enable Use software to wait until the operational amplifier stabilizes 20 us max MOV B 80 JPDAC150 DEC B SJPDAC150 20 us elapsed No D A converter setting d eee SET1 DACEO D A converter CHO enable TAUO CH4 setting for output timing o Uc cane CLR1 TMIF04 Clear interrupt request flag d SETI TSOL 4 Start TAUO CH4 ockckckck ckck ck ckck ck ckck ck ckck ck ck ck ckck kck k k kk kk KA KA D 7 i ockckckck ckck ck ARA KAR ck ck ck ck ckck kck k k kk kk KA KA e 1 f x MOVW RPLAYCOUNT 0 Clear output data counter lt 2 gt AX RPLAYCOUNT Get number of output times AX ITPLAYSIZE Finished all data output SJPDAC300 Yes 40 Application Note U20028EJ1VOAN Sra b c d b CHAPTER 4 SETTING METHODS Ckckckck ck ko kckckckck ck ck ck k ck k kk kk a f pa Play low 4 bits RARER WORK KK Re K AAR K AK KK A Decompression of ADPCM data low 4 bits gt 16 bits AX LOWW RADPCMWORK Set work area for _adpcm_132_dec AX Push argument A ES HL Get compressed data A 00FH Clear high 4 bits Dor A A DIVMODE Set multiplication mode for adpcm 132 dec adpcm 132 dec Decompression
99. ter The ADPCM data to be played back is transferred at 32 kbps when sampled at 8 kHz and quantized with 4 bits The ADPCM data is decompressed by an ADPCM SP library function and output by the D A converter It is then sampled at a frequency of 8 kHz which is controlled by a timer array unit The data then passes through a low pass filter that incorporates an operational amplifier Playback of the data is triggered by a key stroke 1 Primary initial settings lt Option byte settings gt e Disabling the watchdog timer e Setting the internal high speed oscillator frequency to 8 MHz e Disabling LVI from being started by default e Enabling on chip debug to operate lt Settings during initialization immediately after a reset ends gt e Setting up I O ports e Setting P23 P25 P26 and P150 to input data to operational amplifiers e Setting P24 and P27 to output data from operation amplifiers e Setting KRO to input key and detect key interrupt signal e Securing a supply voltage of 2 7 V or more by using the function of low voltage detector e Specifying that the CPU clock run on the X1 oscillator 20 MHz e Stopping the internal high speed oscillator e Setting up timer array unit O e Setting channel 0 of timer array unit O in a mode in which it operates as an interval timer of about 10 ms to Set settling time of the voltage reference and avoid chattering of a key input e Setting channel 4 in interval timer mode to set the sampling frequency for
100. tion Note U20028EJ1VOAN 2 7 yk a is jx A ji z y T jn jx T x 7 yk js T 7 3s z me fa jx je T ie z te pe T 7 3 pe APPENDIX A PROGRAM LIST 4 Timer interrupt is generated when counting is started timer output also changes 0110 1 Event counter mode 2 Counting down 3 Possible 4 Timer interrupt is not generated when counting is started timer output does not change either 1000 1 One count mode 2 Counting down 3 Impossible 4 Start trigger is invalid during counting operation At that time interrupt is not generated either y 1001 1 One count mode 2 Counting down 3 Impossible 4 Start trigger is valid during counting operation At that time interrupt is also generated 1100 1 Capture amp one count mode 2 Counting up 3 Possible 4 Timer interrupt is not generated when counting is started timer output does not change either Start trigger is invalid during counting operation At that time interrupt is not generated either Other than above Setting prohibited Application Note U20028EJ1VOAN 91 PA 92 APPENDIX A PROGRAM LIST Tq MS VSM 7 IF TTT LLL Be sure to set 00 TG 97 7 111 4 Selection of TIOO pin input signal AN fSUB
101. tion operation function 1 Operates as master channel withcombination operation function T Selection of count clock TCLK of channel 0 0 Operation clock MCK specified by CKS04 bit 1 Valid edge of input signal input from TI04 pin fSUB 2 SUB 4 the timer input used with channel 4 is selected by using TISO Application Note U20028EJ1VOAN APPENDIX A register PROGRAM LIST Be sure to set 00 Selection of operation clock MCK of channel 0 Operation clock CK00 set by TPSO register 1 Operation clock CK01 set by TPSO register CK01 CLK 2 20 MHz gt 8 kHz MOVW TDRO4 2500 1 SET1 TMMK04 0 125 ms 0 05 us clk 2500 count Set interval time to about 125 us 8 kHz Disable i nterrupt Module SINITVR Description Setting of Voltage reference i parameter A return pe SINITVR MOV ADVRC 00001000B and D A converters for A D converter 0 1 Analog re 1 Positiv ference voltage control register e reference voltage supplies selection of A D 2 Operation control of voltage reference 3 Output voltage selection of voltage reference 4 Operation control of input gate voltage boost circuit 5 Relationship with the conversion mode used EFP external voltage reference input 2 Stops operation Hi Z V 4 Stops operation 0 1 AVRI 3 2 5 5 Can
102. tput voltage of voltage reference peration Enable operation of voltage reference B 2 TSOL O TMIFOO TMIFOO JINIVR200 B JINIVR100 TMIFOO TTOL 0 over 17 msec Set counter Start TAUO CHO Clear interrupt request flag Wait for about 20 ms until operation of voltage reference is stabilized Clear interrupt request flag Stop TAUO CHO Application Note U20028EJ1VOAN CHAPTER 4 SETTING METHODS lt 3 gt Setting up operational amplifiers SINITPORT eee Omitted e e o MOV PM2 11111111B Set P20 to P27 to input port Set P23 to P27 and P150 in e e Omitted e input port mode for operational amplifier input output 11111111B Set P150 to P152 and P157 to input port Set pins used for operational amplifier input output AMP1 AMP1 AMP10 AMP2 AMP2 SINITAMP and AMP20 in analog input mode MOV 00000000B A D Port Configuration Register Stop operation of operational amplifiers 1 and 2 as default assumption er AMP1 disable amplifier AMP2 disable Enable operation of operational amplifiers 1 and 2 when operational amplifiers are to be used Use software to wait until the operational amplifier stabilizes 20 us max MOV B JPDAC150 Wait for about 20 ws until operation DEC B of operational amplifier is stabilized BNZ JPDAC150 20 us elapsed No Application Note U20028EJ1VOAN 33 34 CHAPTER 4 SETTING METHODS
103. ut clock SFR used by timer array unit 1 can be read and written Control of serial array unit 0 input clock 0 Stops input clock supply Application Note U20028EJ1VOAN 53 APPENDIX A PROGRAM LIST LI SFR used by the serial array unit 0 cannot be written LI The serial array unit 0 is in the reset status 1 Supplies input clock SFR used by the serial array unit 0 can be read and written Control of serial array unit 1 input clock 0 Stops input clock supply SFR used by the serial array unit 1 cannot be written The serial array unit 1 is in the reset status 1 Supplies input clock SFR used by the serial array unit 1 can be read and written Control of serial interface IICA input clock 0 Stops input clock supply SFR used by the serial interface IICA cannot be written The serial interface IICA is in the reset status 1 Supplies input clock SFR used by the serial interface IICA canbe read andwritten Control of A D converter operational amplifier and voltage reference input clock 0 Stops input clock supply SFR used by the A D converter operational amplifier and voltage reference cannot be written n The A D converter operational amplifier and voltage reference is in the reset status a voltage reference can 54 1 Supplies input clock SFR used by the A D converter
104. ut port mode 2 Input port 1 1 XT1 oscillation mode 2 Crystal resonator connection Be sure to set 0 1 EXCLK OSCSEL High speed system clock pin operation mode 2 X1 P121 pin 3 X2 EXCLK P122 pin 00 1 Input port mode 2 3 Input port 01 1 X1 oscillation mode 2 3 Crystal ceramic resonator connection 10 1 Input port mode 2 3 Input port 11 1 External clock input mode 2 Input port 3 External clock input Application Note U20028EJ1VOAN 79 80 APPENDIX A PROGRAM LIST MSTOP 0 X1 oscillator operating OSMC 0b00000001 Operation Speed Mode Control Register CLK frequency selection 0 0 Operates at a frequency of 10 MHz or less 0 1 Operates at a frequency higher than 10 MHz 1 0 Operates at a frequency of 1 MHz VERE PIT Bab Be sure to set 00000 E E s H SRS SeeS Setting in subsystem clock HALT mode 0 Enables subsystem clock supply to peripheral functions See Table 21 1 Operating Statuses in HALT Mode 2 3 A for the peripheral functions whose operations are enabled 1 Stops subsystem clock supply to peripheral functions except real time counter clock output buzzer output Lt and LCD controller driver while OSTC 0 1 Wait X1 oscillation

78K0R/LH3 Sample Program(Sound Output) Playing Back Sound

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