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V850ES/Jx3-L Real-Time Counter (RTC Backup Mode)

1. Declare function prototypes void main void Main processing static void fn InitFirst void Specify the settings of the registers to be set first static void fn InitPort void Specify the initial settings for the ports static void fn InitLvi void Perform low voltage detection processing static void fn InitClock void Specify the initial settings for the clock static void fn InitRtc void Specify the initial settings for the real time counter static void fn InitRtcBum void Specify the initial settings for RTC backup mode static void fn WriteRtcCounter unsigned char ucinc Processing to overwrite RTC count static void fn WriteRtcAlerm unsigned char ucinc Processing to overwrite RTC alarm Static void fn RtcCorrect unsigned char ucReg Watch error correction processing static void fn KeySampling void Perform key sampling static void fn SetStandby void Shift to standby static void fn Display void Refresh the display static unsigned char fn BcdCount unsigned char ucNum unsigned char ucInc unsigned char ucMin unsigned char ucMax Count the BCD value External reference extern
2. 10 al Sl wl rm l p 6 00 1 00 2 00 3 00 ala ila NIO NS c T Nol PM ND Kl A oO I r cr N N I The RCIHOUR register value is displayed in 12 hour format if the AMPM bit is 0 and in 24 hour format if the AMPM bit is 1 In 12 hour format a m or p m is indicated by the fifth bit of RCIHOUR with indicating before noon a m and 1 indicating noon or afternoon p m R01ANO193EJ0100 Rev 1 00 Sep 30 2010 13 NESAS Page 31 of 90 V850ES Jx3 L Real Time Counter RTC Backup Mode 8 Day count register RCIDAY The RCIDAY register is an 8 bit register that takes a value of 1 to 31 decimal and indicates the count value of the day This register can be read or written in 8 bit units This register counts up when the hour counter overflows This counter counts as follows 01 to 31 January March May July August October December 01 to 30 April June September November 01 to 29 February in a leap year 01 to 28 February in a normal year When data is written to this register it Is written to a buffer and then to the counter up to 2 clocks 32 768 kHz later Set a decimal value of 00 to 31 to this register in BCD code Caution Setting a value other than 01 to 31 to the RCIDAY register is prohibited Setting a value outside the above mentioned count range such as February 30 is also prohibited Remarks 1 This register is reset to
3. Operation clock selection Select fxr as operating clock 1 Select farg as operating clock Note If fxr is selected as the operating clock be sure to set the RCICKS bit to 0 while the system 15 preparing to enter RTC backup mode while RTCBUMCTLO RBMSET is set to 1 Cautions 1 Follow the description in 11 4 8 Initializing real time counter in the user s manual when stopping the real time counter while it is operating by changing the RC1PVVR bit from 1 to 0 The RCICKS bit can be rewritten only when the real time counter is stopped RCIPWR 0 Furthermore rewriting the RC1CKS bit at the same time as changing the RCIPWR bit from 0 to 1 is prohibited Be sure to set bits 0 to 5 to 0 Remarks1 This register is reset to 00H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained The parts written in red in the above figure are the values set by using this sample program RO1ANO193EJ0100 Rev 1 00 Page 25 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 2 Real time counter control register 1 RCICCI The RCICCI register is an 8 bit register that starts or stops the real time counter controls the RTCCL and RTCIHZ pins selects the 12 hour or 24 hour system and sets the fixed cycle interrupt This register can be read or written in 8 bit or 1 bit units Figure
4. Switch to post reset display Start blinking display again Turn on or off display of Issue display refresh request Switch to watch display Alarm interrupt processing INTRTC1 No Normal operation Start buzzer output Start counting by buzzer timer Key interrupt processing INTKR Issue key detection notification R01ANO193EJ0100 Rev 1 00 Sep 30 2010 13 NESAS Page 22 of 90 V850ES Jx3 L Real Time Counter RTC Backup Mode lt Low voltage detection interrupt processing Processing if low voltage is detected INTLVI No ow voltage detection in progress Disable PLL and set CPU clock to 5 MHz Disable DMA processing Disable edge detection for NMI pin Set subclock to normal oscillation mode Cancel the preparation to enter RTC backup mode Processing when restoring Enable interrupts to be used from low voltage except INTLVI Set CPU clock to 20 MHz by using PLL Issue display refresh request Disable all interrupts except INTLVI Set subclock to ultra low power oscillation mode Prepare to enter RTC backup mode Note 2 Shift to stop mode Notes 1 This setting must be specified to use the subclock s ultra low power feature but it is not necessarily required to enter RTC backup mode 2 Ifsupply of the power supply voltage Vpp stops in stop mode the system shifts to RTC back
5. Key code buffer Off ucKeyCode KEYCODEOFF Key code Off ucKeyEdgeInfo 0 Key detection None ucKeyValidInfo 0 Valid key input None ucBuzzerTimer 0 Buzzer timer stopped ucSetupTime SETUP_TMNONE No time set ucSetupAlarm SETUP_ALNONE No alarm set ucColonBlink 1 i display on ucMode MODE RESET Set to post reset ucDisplay DISP RESET Switch to post reset display ucBlinkDispTimer BLINKDISPTIME Timer for blinking display Start counting ucDispReq 1 Issue display refresh request nannini Specify settings for interrupts rrr un rm E c ns nn KRM 0600001111 Enable key interrupts KRO to KR3 KRIF 0 Clear INTKR interrupt request flag RTCOIF 0 Clear INTRTCO interrupt request flag RTCIIF 0 Clear INTRTCI interrupt request flag RTC2IF 0 Clear INTRTC2 interrupt request flag LVIIF 0 Clear INTLVI interrupt request flag KRMK Enable INTKR interrupt RTCOMK 0 Enable INTRTCO interrupt RTC1MK Dj Enable INTRTC1 interrupt RO1AN0193EJ0100 Rev 1 00 Page 60 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode RTC2MK 1 Disable INTRTC2 interrupt LVIMK 0 Enable INTLVI interrupt CB3RMK 0 Enable INTCB3R interrupt for on chip debugging EI Enable acknowledgment of i
6. TQ z Il PCM 1 0 2 0 8 0 i PMCM 1 0 2 0 LE PCT 0600000000 PMCT 0b10101100 3 R01ANO193EJ0100 Rev 1 00 Sep 30 2010 Set Real Time Counter RTC Backup Mode to P42 Not used the output data of P50 to P53 to 1 the output data of P54 and P55 to 0 P50 to P53 to input mode P54 and P55 to output mode Specify P50 to P53 to be used as KRU to KR3 P50 P54 P90 P97 to P53 Used as key inputs and P55 Not used the output data of P70 to 1 the output data of P71 to P77 to 0 the output data of P78 to P711 to 0 P70 to P77 to output mode P78 to P711 to output mode Used for buzzer control to P711 Not used the output data of P90 to P915 to 0 P90 to P915 to output mode to P96 Used for LCD module to P915 Not used When using CSIB3 for communication during on chip debugging do not change the settings of PFC910 to PFC912 or PMC910 to PMC912 Set the output data of PCMI to 0 the output data of PCM2 to 0 the output data of PCM3 to 0 1 to output mode PCM2 to output mode PCM3 to output mode PCMO to PCM3 Not used When using CSIB3 for communication during on chip debugging do not change the settings of PCMO or PMCMO Set Set the output data of PCTO PCTI PCT4 and PCT6 to 0 PCTO PC
7. 1 Specify the PLL mode ucDispReq 1 Issue the display refresh request JAKKKKAKKAKKKAKKKAKKAKKKAKKKKKKAKKKAKKKAKKAKKKAKKKAKKKKKKAKKKKKKAKKKAKKAK Title Key interrupt processing using the INTKR interrupt ck ck ck ck ck kk kk e e KKK KKK KKK KH KH KH KH kk kk x kk x kk kk kk KKK KKK KKK x kx x kx kx kx kx kx kx kx kx kx ok Module interrupt void fn IntKr void Arg Ret Note This processing issues a key detection notification KKAKKKKAKKKAKKKAKKKAKKAKKKAK kk Ck KKAKKKAKKKKAKKAKKKAKKKAKKKAKKKAKKKKKKKKKKKKKJ interrupt void fn IntKr void ucKeyEdgeInfo 1 Issue a key detection notification Yxxxk kxkxxkxkxkxkxkkkkkkkkkkikkkkkkkikkkkikkkikkkkkkkkkkkkkkkkkkkikkkikkkkikkkk ki xo k Title Key sampling processing ck ck ck ck ck kk e kk KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK x kx kx kx kx kx kx kx kx Module static void fn KeySampling void Arg Ret Note This processing samples the key input ports FR A yk x kk x kk Lk Kk Ck Kk Ck Ck Kk Ck KK x k ok x x kk XL RA AA 2 22 2 222 2 22 2 2 22 2 2 22 2 22 2 kk x static void fn KeySampling void unsigned char ucWork Obtain the status of the key input ports and convert it into the key code switch P5 6 x f Active level No data case 0b00001111 Code Off ucWork KEYCODEOFF break Active level Bit 0 case 0b00001110 Code Key 1 ucWork 1
8. 11 Year count register RCIYEAR The RCIYEAR register is an 8 bit register that takes a value of 0 to 99 decimal and indicates the count value of the year It counts up when the month counter overflows The values 00 04 08 92 and 96 indicate a leap year When data is written to this register it is written to a buffer and then to the counter up to 2 clocks 2 x 32 768 kHz later Set a decimal value of 00 to 99 to this register in BCD code This register can be read or written in 8 bit units Caution Setting a value other than 00 to 99 to the RCLYEAR register is prohibited Remarks 1 This register is reset to 00H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained 2 This register is set to an initial value of 10H in this sample program Figure 4 1 11 Format of Year Count Register RC1YEAR Year count register RC1 YEAR Address FFFFFAD8H RO1ANO193EJ0100 Rev 1 00 Page 34 of 90 Sep 30 2010 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 12 Alarm minute setting register RCIALM The RCIALM register is an 8 bit register that is used to set the minutes of the alarm This register can be read or written in 8 bit units Cautions 1 Set a decimal value of 00 to 59 to this register in BCD code If a value outside the range is set the alarm is not detected 2 See the V850ES Jx3
9. break Active level Bit 1 case 05000001101 Code Key 2 ucWork KEYCODE2 break Active level Bit 2 case 0500001011 Code Key 3 RO1AN0193EJ0100 Rev 1 00 Sep 30 2010 ENESAS Page 78 of 90 V850ES Jx3 L Real Time Counter RTC Backup Mode ucWork KEYCODE3 break Active level Bit 3 case 05000000111 Code Key 4 ucWork KEYCODE4 break Active level Multiple data default Code More than one key pressed at the same time ucWork KEYCODEMLT break If the code does not match the previous code if ucCodeBuffer ucWork Reset the sampling count ucKeySamplingCounter KEYSAMPLINGCOUNT Save the current code ucCodeBuffer ucWork If the code matches the previous code else Count the number of samplings sampling count ucKeySamplingCounter If the sampling count has reached the specified number if ucKeySamplingCounter Reset the sampling count ucKeySamplingCounter KEYSAMPLINGCOUNT To update the key code if ucCodeBuffer ucKeyCode To update the key code because more than one key was pressed at the same time if ucKeyCode KEYCODEMLT To turn the key off after more than one key was pressed at the same time if ucCodeBuffer KEYCODEOFF Updated key code Key code off ucKeyCode KEYCODEOFF Otherwise else If t
10. static void fn InitPort void poc Specify the setting of port 0 EINEN et e PO 05000000000 Set the output data of P02 to P06 to 0 PMO 0010000011 Set P02 to P06 to output mode P02 to P06 Not used Specify the setting of port 1 Po 9 P1 0000000000 Set the output data of P10 and P11 to 0 PM1 0511111100 Set P10 and P11 to output mode P10 and P11 Not used aaa a a a ii ee Specify the setting of port 3 Y s A P3 0b0000000000000000 Set the output data of P30 to P39 to PM3 0b1111110000000000 Set P30 to P39 to output mode P30 to P39 Not used Specify the setting of port 4 P4 0b00000000 Set the output data of P40 to P42 to 0 PM4 0b11111000 Set P40 to P42 to output mode R01AN0193EJ0100 Rev 1 00 Page 64 of 90 Sep 30 2010 ENESAS V850ES Jx3 L P5 05000001111 ye PM5 0b11001111 i PFCE5 0600000000 E PFC5 0b00001111 PMC5 0b00001111 P7L 0500000001 JE P7H 0500000000 ce PM7L 0500000000 LE PM7H 0b11110000 Specify the setting of port 9 P9 000000000000000000 050000000000000000
11. ur Eo e Esc LE EM Specify the number of bus waits when accessing a peripheral I O register ie eee Eel ole seruo oim n e een n n e m ne n enn n eun e ine n a er E n n y VSWC 0x01 Set the number of waits to 1 M H QR Specify the settings for the on chip debug mode register rea c cr see t eee asm st b r0 PRCMD Set to normal mode asm st b r0 OCDM Sire Se Dus ien ex Qe las que Gas E ieu des iow Gus dew den Voy lag Don ias er len ay leo ee EE lan ow ing dew ee ee EEE EEE Specify the settings for watchdog timer 2 M M s R RSTOP 1 Specify stopping the internal oscillator WDTM2 0b00000000 Specify stopping the operation of watchdog timer 2 Yxxxk kxkk kkkkkkkkkkkkkkkkkkikkkkkkkkkkkikkkkkkkkkkkkkkkikkkkikkkkkkkki kii ke ke ke Title Processing to specify the initial settings of the ports ok ck ck Xk k ck ck ck ck ck kc ck ck ck kek kk A HK HI A A k KH AH KH A KH TA k TH AH KH A KH TA k TH AH ck kek kk TH KK A KK A TH TH k ck ko ko A KH A ko ko ko ko ko Module static void fn InitPort void Arg Ret nn Note This processing specifies the settings of the I O ports FRR ok kk k yk A 2 2 202 222 2 AE 222 2 A 222 2 kk e 22 2 kk XL x kk 2 22 2 22 2 kk x
12. 79 Preprocessing directive pragma directive pragma ioreg Enable peripheral I O registers to be described x Define instructions define NOP asm nop Enable NOP instruction to be defined as NOP a Specify interrupt handlers pragma interrupt INTRTCO fn IntRtcO Fixed cycle interrupt processing pragma interrupt 1 fn IntRtcl Alarm interrupt processing pragma interrupt INTLVI fn IntLvi Low voltage detection interrupt processing pragma interrupt INTKR fn IntKr Key interrupt processing 79
13. ck ck ck ck ck ck ck A ck ck kc ck k ck kek ck k ck HK kek kk ka AH k A A k ck AH KH A AA AH KH A KH A KH A k ck A KK A KH A k ck A ko A KH A ko ko ko ko ko Module static void fn RtcCorrect unsigned char ucReg Arg Set value Ret Note This processing specifies settings for the watch error correction feature of the real time counter KKAAKKKKKKAKKKAKKKAKKAKKKAKKKKKKAKKKAK k e ok xx 222 2 22 2 2 ok x x 222 2 222 2 ok x 2 22 2 2 e x x static void fn RtcCorrect unsigned char ucReg RCISUBU ucReg RCLSUBU Obxxxxxxxx 5 0 ae F6 Set the watch error correction value 0 Increment the RC1SUBC count value by the value set to the F5 to FO bits positive correction Expression for calculating increment Value set to bits F5 to FO 1 x 2 1 Decrement the RC1SUBC count value by the value set to bits F5 to FO negative correction Expression for calculating decrement Inverted value of value set to bits F5 to FO 1 x 2 If the value set to bits F6 to FO is 1 0 0 0 0 0 0 1 0 watch error correction is not executed de M DEV Specify the watch error correction timing 0 Execute watch error correction when RC1SEC second counter is 00 20 and 40 every 20 seconds 1 Execute watch error correction when RC1SEC second counter is 00 every 60 seconds ARR K k e k e EEE KKK KKK KKK ke kk Ck 2 2 222 2 222 222 2 222 2 22 2 222 2 222 2 22 2 22 2 2 22 2 AAA Title Fixed
14. lt 6 gt asm st bELO BSG asm pop r10 nur R01AN0193EJ0100 Rev 1 00 Page 46 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Notes 1 In this sample program low voltage is defined as 2 2 V lt Vpp x 2 8 V 2 Ifa DMA occurs before DMA is disabled in the INTLVI interrupt routine and the power supply voltage reaches the minimum guaranteed voltage level it will not be possible to set RTC backup mode Caution The subclock low power operation control register SOSCAMCTL and RTC backup control register 0 RTCBUMCTLO are special registers that can only be written in a specific sequence For details about special registers see the V850ES Jx3 L user s manual RO1ANO193EJ0100 Rev 1 00 Page 47 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode c Settings when cancelling the preparation to shift to RTC backup mode In the INTLVI interrupt processing routine check whether the system is returning from the low voltage state that is whether the LVIM LVIF bit is 0 V and then specify the following settings lt 1 gt Set SOSCAMCTL AMPHS to 0 to specify normal oscillation for the subclock fxr 2 Set RTCBUMCTLO RBMSET to 0 to prepare to exit the RTC backup mode 3 Execute NOP 4 Enable the maskable interrupts to be used interrupts other than INTLVI 5 Specify the normal clock 5 MHz x 4 20 MHz as the CPU clock interrupt vord fn ni vi vord j
15. 0 5 second eycle INTRTCO interrupt is generated processing such as updating the watch display is executed If the INTRTCI interrupt is triggered by the occurrence of an alarm buzzer output processing is executed If the INTKR interrupt is triggered by the occurrence of a key input key sampling starts using the 3 9 millisecond cycle INTRTC2 interrupt If sampling results in the detection of a valid key input processing to refresh the watch display and the real time counter count value is executed f the INTLVI interrupt is triggered by the detection of low voltage the system prepares to enter the RTC backup mode and then shifts to stop mode If supply of the power supply voltage Vpp then stops the system shifts to the RTC backup mode However if the INTLVI interrupt is triggered by the power supply voltage being restored from the low voltage state after the system has shifted to stop mode the system cancels the preparation to enter the RTC backup mode and then returns to the normal operation mode R01ANO193EJ0100 Rev 1 00 Page 5 of 90 Sep 30 2010 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 1 2 Watch Display This sample program specifies the use of the LCD module character display 20 characters x 2 rows as a watch display 1 Display The day year month day day of week time hour minute second and alarm setting day of week hour minute are displayed Month Da ei of week Year Hour inate
16. 01H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained 2 This register is set to an initial value of 01H in this sample program Figure 4 1 8 Format of Day Count Register RC1DAY Day count register RCIDAY Address FFFFFAD6H 7 6 5 4 3 2 1 0 Lo Joy dl i RO1ANO193EJ0100 Rev 1 00 Page 32 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 9 Day of week count register RCIWEEK The RCIWEEK register is an 8 bit register that takes a value of 0 to 6 decimal and indicates the count value of the day of the week It counts up in synchronization with the day counter When data is written to this register it is written to a buffer and then to the counter up to 2 clocks 2 x 32 768 kHz later Set a decimal value of 00 to 06 to this register in BCD code If a value outside this range is set the register value returns to the normal value after 1 period This register can be read or written in 8 bit units Figure 4 1 9 Format of Day of Week Count Register WEEK Day of week count register RC1 WEEK Address FFFFFADSH 7 6 5 4 3 2 1 0 o jo po jo Cautions 1 Setting a value other than 00 to 06 to the RCIWEEK register is prohibited 2 Values corresponding to the month count register and day count register are not automatically stored in the day of week
17. 1 break Month is being set case SETUP TMMONTH Cursor position Lower digit of month fn LcdCurDisp 4 break Day is being set case SETUP TMDAY Cursor position Lower digit of day fn LcdCurDisp 7 break Day of week is being set case SETUP TMWEEK Cursor position First letter of day of week fn LcdCurDisp 8 break Hour is being set case SETUP TMHOUR Cursor position Lower digit of hour fn LcdCurDisp 13 break Minute is being set case SETUP TMMIN Cursor position Lower digit of minute fn LcdCurDisp 16 break Second is being set case SETUP TMSEC Cursor position Lower digit of second fn LcdCurDisp 19 break default break RO1AN0193EJ0100 Rev 1 00 Page 84 of 90 Sep 30 2010 ENESAS V850ES Jx3 L switch ucSetupAlarm Real Time Counter RTC Backup Mode Alarm day of week is being set case SET Cursor position First letter of alarm day of week UP ALWEEK fn LcdCurDisp 28 break Alarm hour is being set case SET UP ALHOUR Cursor position fn LcdCurDisp 33 break Alarm minute is being set case SET default break UP ALMIN Cursor position fn LcdCurDisp 36 break break Lower digit of alarm Lower digit of alarm hour minute Post reset
18. 4 Post reset Shift to normal operation Switch to watch display Stop blinking display Issue display refresh request Determine key code Shift to normal operation Overwrite alarm value count down Overwrite alarm yale Specify setting next item count up Issue display refresh request R01AN0193EJ0100 Rev 1 00 Page 20 of 90 Sep 30 2010 13 NESAS V850ES Jx3 L Overwrite count value Overwritten Note Disable count register Counting stopped Overwrite date and time registers according to item to be set and up down specification Enable count register Real Time Counter RTC Backup Mode Overwrite alarm value Disable INTRTC1 interrupt Disable alarm interrupt Overwrite alarm day and time registers according to item to be set and up down specification Clear INTRTC1 interrupt request Enable INTRTC1 interrupt Enable alarm interrupt Note Check that the previous processing to write the count register is complete R01ANO193EJ0100 Rev 1 00 Sep 30 2010 ENESAS Page 21 of 90 V850ES Jx3 L Real Time Counter RTC Backup Mode Fixed cycle interrupt processing INTRTCO No Is the buzzer operating Buzzer timer counts up End of buzzer output Stop buzzer output Is the display blinking Blinking display timer counts up Time to switch display Watch display
19. 4 1 2 Format of Real Time Counter Control Register 1 RC1CC1 Real time counter control register 1 RCICCI Address FFFFFADEH 7 6 5 4 3 2 1 0 Lm o cioe GLOEO Aww cm cr Tem RTCE Control of operation of each counter top counter operation 1 Enable counter operation CLOE1 RTC1HZ pin output control Disable RTC1HZ pin output 1 Hz Enable RTC1HZ pin output 1 Hz CLOEO RTCCL pin output control Disable RTCCL pin output 32 768 kHz Enable RTCCL pin output 32 768 kHz AMPM 12 hour system 24 hour system selection 12 hour system a m and p m are displayed 1 24 hour system Fixed cycle interrupt INTRTCO selection Do not use fixed cycle interrupts 1 1 1 Once every 0 5 seconds synchronous with second count up BEE 0 Jonce a second simultaneous with second countup E nute at 0 E Fo x Once a month one day every month at 00 hours E minutes 00 seconds a m Cautions 1 Writing 0 to the RTCE bit while the RTCE bit is 1 is prohibited Clear the RTCE bit by clearing the RC1PVVR bit according to 11 4 8 Initializing real time counter in the user s manual 2 The RTC1HZ output operates as follows when the CLOE1 bit setting is changed e When changed from 0 to 1 RTC1HZ outputs a 1 Hz pulse within two clocks 2 x 32 768 kHz e When changed from 1 to 0 RTC1HZ output is stopped fixed to low level within two clocks 2 x 32 768 kHz Specify the RCIHOUR register
20. L user s manual for details about how to change the alarm minute setting register RCIALM while the real time counter is operating Remarks 1 This register is reset to 00H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained 2 This register is set to an initial value of 00H in this sample program Figure 4 1 12 Format of Alarm Minute Setting Register RC1ALM Alarm minute setting register RCIALM Address FFFFFADAH 7 6 5 4 3 2 1 0 xp sp 13 Alarm hour setting register RC1ALH The RCIALH register is an 8 bit register that is used to set the hour of the alarm This register can be read or written in 8 bit units Cautions 1 Set a decimal value of 00 to 23 01 to 12 or 21 to 32 to this register in BCD code If a value outside the range is set the alarm is not detected 2 Bit 5 of the RCIALH register indicates a m 0 or p m 1 if the AMPM bit 0 12 hour system is selected 3 See the V850ES Jx3 L user s manual for details about how to change the alarm hour setting register RC1ALH while the real time counter is operating Remarks 1 This register is reset to 00H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained 2 This register is set to an initial value of 14H i
21. backup mode KKAAKKAKKKAKKKAKKKAKKAKKKAKKKKKKAKKKAKKKA ok x x 22 2 2 22 2 2 22 2 222 2 22 2 2 kx ke x ke e x x interrupt void fn_IntLvi void 1 If the voltage has dropped from the normal operating voltage level to the low voltage detection level if LVIF Set the operating clock to a frequency that accords with the low voltage detection state SELPLL PLLON 0 Specify clock through mode 0 Stop the PLL Disable DMA E00 E11 E22 E33 cC o o oC Disable NMI pin edge detection INTFO amp 05001111000 INTRO amp 05001111000 RO1AN0193EJ0100 Rev 1 00 Page 76 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Always set to NMI INTPO INTP1 INTP2 INTP3 Disable all interrupts except INTLVI IMR3 0b1111111111111111 IMR2 0b1111111111111111 IMR1 0b1111111111111111 IMRO 0b1111111111111110 Set the subclock to ultra low consumption mode asm push rl0 asm mov 0x01 r10 asm st b r10 PRCMD asm st b r10 SOSCAMCTL asm pop r10 Ya vg tg E Set the state in which the system is preparing to enter RTC backup mode asm mov 0x81
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23. cycle interrupt processing using the INTRTCO interrupt ck ck ck ck ck eee ee ee e KKK KKK KKK KKK KKK KKK x k kk kk kk kk KKK KKK KKK kx kx kx kx kx kx kx RO1AN0193EJ0100 Rev 1 00 Page 74 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Module interrupt void fn IntRtco void Arg Ret Note This processing executes INTRTCO interrupt processing KKAAKKKKKKAKKKAKKKAKKAKKKAK KKK KKAKKKAKKKKKKAKKKAKKKAKKKAKKKAKKKKKKKKKKKKKJ interrupt void fn IntRtco void I the buzzer is being output if ucBuzzerTimer ucBuzzerTimer Count the value of the buzzer timer If the buzzer output period has ended if lucBuzzerTimer P7L 0 1 Stop buzzer output If the display is blinking if ucBlinkDispTimer ucBlinkDispTimer Count the value of the timer for blinking display If it is time to switch the display if ucBlinkDispTimer Switch the watch display to the post reset display if ucDisplay DISP WATCH ucDisplay DISP_RESET Switch the post reset display to the watch display else ucDisplay DISP WATCH Resume counting the value of the timer for blinking display ucBlinkDispTimer BLINKDISPTIME ucColonBlink 1 Switch the display from on to off and vice versa ucDispReg 1 Issue display refresh request ys Add any processing using
24. display xd 444444444444 ICIPIUI IRIEISIEITI 444444444444 444444444444 4444444 4444 444 4444444 case DISP RESET fn En fn fn fn Ene fn fn fn Ino fn fn fn fn fn fn Led LcdC LcdC nedc Lodc LcdC HE fn fn LcdC LcdC _Lcdc fn in LcdC LcdC Lede LcdC LcdC LcdC fn Tf LcdC LcdC Lest tn fn LcdC LcdC _Lcdc fn fn LcdC LcdC Led LcdC hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp TOT UcPostt C uePostt P ucPostt U oPostt Ty bcPostty R ucPostt E ucPostt S ucPostt E ucPostt T ucPostt OT XGPOsPE UOPOSTE 1 bicPostty 1 T 4 T Sy mePost 5 Ty bePos t Ty bcPostt nePost ot bcPos r Ty bcPostty t4 uoPostb T bcPostt 1 DoPosTt OT ucPostt Ty uePost R01ANO193EJ0100 Rev 1 00 Sep 30 2010 pa pa A BP PP pa pa pa pa pa pa pa A 131 NESAS KI Page 85 of 90 V850ES Jx3 L fn LcdC fn LcdC fn LcdC fn LcdC
25. fn LcdC fn LcdC fn LcdC fn LcdC fn LcdC fn LcdC fn LcdC fn LcdC fn LcdC fn LcdC break default break R01ANO193EJ0100 Rev 1 00 Sep 30 2010 hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp hrDisp ucPostt ucPostt ucPostt ucPostt ucPostt ucPostt ucPostt ucPostt ucPostt ucPostt ucPostt ucPostt ucPostt ucPostt PRP PPP Real Time Counter RTC Backup Mode ENESAS Page 86 of 90 V850ES Jx3 L Website and Support Renesas Electronics Website http www renesas com Inquiries http www renesas com inquiry R01ANO193EJ0100 Rev 1 00 Sep 30 2010 Real Time Counter RTC Backup Mode RENESAS Page 87 of 90 Revision Record Rev Date Description Page Summary 1 00 Sep 30 2010 First edition issued NOTES EOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between VIL MAX and VIH MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area bet
26. is Low voltage is detected detected If low voltage is Prepare to enter RTC backup mode detected post reset Cancel the preparation to enter RTC backup mode processing is Restoring from low voltage state performed again Enter stop mode Supply of Von is stopped Enter RTC backup mode Supply of Vpp resumes external reset is cancelled If low voltage is detected restore normal processing RO1ANO193EJ0100 Rev 1 00 Page 16 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 3 4 Flow Charts The processing performed by this sample program is illustrated in the following flow charts Main processing RESET Reference the P E E Note 1 option byte Disable acknovvledgment of interrupt request signals Perform initial setting processing for RTC backup mode Enable counting by date and time count registersh8 7 Specify settings for registers to be set first Specify I O port settings Perform low voltage detection te 5 Specify clock 226 No s RTC initialized Perform real time counter initial setting Initial settings for processing peripheral I O circuits Perform LCD module initial Note 8 setting processing Specify initial settings for variables to be used Perform post reset processing Switch to reset restoration display Start blinking display Issue display refresh requires Specify the key interrupt settings En
27. other settings The value being set is incremented CO NORRIS BERG LINHA Hie bbi TT KKR OD RS BT Prop gt Hz lu bis ib ARM JAI lal Key 2 Note ALL indicates everyday Caution The day of week must be set manually in accordance with the actual year month and day Remark The settings being specified are ringed in black RO1ANO193EJ0100 Rev 1 00 Page 8 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 3 Key 3 operation Key 3 is used to decrement the value down key lt Specifying the alarm day of week setting The value being set is switched as follows ALLN S SAT FRI THU WED TUE MON SUN ALL isi ol Asa BG S TT a CORONE irili p E laam RST d lil Key 3 a UBU iri np uu pe LIAM ERL fel Key 3 lt Specifying other settings The value being set is decremented OO RORE ONT BUE EGRE PLS Pik PAEL deb TRA TA LLISTUARIM TRES TT Key 3 LEN Note ALL indicates everyday Caution The day of week must be set manually in accordance with actual the year month and day Remark The settings being specified are ringed in black RO1ANO193EJ0100 Rev 1 00 Page 9 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 4 Key 4 operation Key 4 is used to switch items Specifying the day and time setting The items being set are switched as fol
28. processing is complete NOP RC1CC2 0 1 Stop the count registers counting while RC1CC2 1 Check the wait status of the counter NOP Determine the setting item switch ucSetupTime Year case SETUP TMYEAR RCIYEAR fn BcdCount RC1YEAR ucInc 99 break Month case SETUP TMMONTH RCIMONTH fn BcdCount RCIMONTH ucInc 1 12 break Day case SETUP TMDAY Convert month to integer value ucWork RCIMONTH gt gt 4 10 RCIMONTH amp x f February if it is a leap year if RCIYEAR gt gt 4 10 RCIYEAR amp 0x0f 4 amp amp RCIMONTH 0x02 R01ANO193EJ0100 Rev 1 00 Page 70 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode RCIDAY fn BcdCount RCIDAY Otherwise else RCIDAY fn BcdCount RCIDAY break Day of week case SETUP_TMWEEK RC1WEEK fn BcdCount RCINEEK break Hour case SETUP TMHOUR RCIHOUR fn_BedCount RCIHOUR break Minute case SETUP TMMIN RCIMIN fn BcdCount RCIMIN break Second case SETUP TMSEC RCISEC fn BcdCount RC SEC break default break RC1CC2 0 0 ucInc 1 aDays ucWork 1 1 ucInc 1 aDays ucWork 1 ucInc 0 6 ucInc 0 23 ucInc 0 59 ucInc 0 59 Enable count register counting Yxkxxk kxkkxkkkkkkkkkkkkkk
29. setting again if the AMPM bit is rewritten Be sure to set bit 6 to 0 1 Once a minute every minute at 00 seconds 0 7 0 0 o 1 EE 1 tt lo Remarks 1 In RTC backup mode mask the fixed cycle interrupt by setting the RTCOMK bit to 1 and stop output from the RTCCL and RTCIHZ pins 2 This register is reset to 00H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained The parts written in red in the above figure are the values set by using this sample program RO1ANO193EJ0100 Rev 1 00 Page 26 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 3 Real time counter control register 2 RC1CC2 The RC1CC2 register is an 8 bit register that controls the alarm interrupt and counter waits This register can be read or written in 8 bit or 1 bit units Figure 4 1 3 Format of Real Time Counter Control Register 2 RC1CC2 Real time counter control register 2 RC1CC2 Address FFFFFADFH 7 6 5 4 3 2 1 0 MET v T 1 9 0 0 RWsr T RWAT Do not generate interrupt upon alarm match 1 Generate interrupt upon alarm match RWST Real time counter wait state Counter operating Counting up of date and time counters stopped Reading and writing of counter values enabled 0 Sets counter operation 1 Stops count operation of dat
30. stop mode An interrupt is then generated and program execution starts according to the generated interrupt e Ifthe 0 5 second cycle INTRTCO interrupt is generated processing such as updating the watch display is executed e Ifthe INTRTCI interrupt is triggered by the occurrence of an alarm buzzer output processing is executed e Ifthe INTKR interrupt is triggered by the occurrence of a key input key sampling starts using the 3 9 millisecond cycle INTRTC2 interrupt If sampling results in the detection of a valid key input processing to refresh the watch display and the real time counter count value is executed e Ifthe INTLVI interrupt is triggered by the detection of low voltage the system prepares to enter the RTC backup mode and then shifts to stop mode If supply of the power supply voltage VDD then stops the system shifts to the RTC backup mode However if the INTLVI interrupt is triggered by the power supply voltage being restored from the low voltage state after the system has shifted to stop mode the system cancels the preparation to enter the RTC backup mode and then returns to the normal operation mode lt I O port settings RO1ANO193EJ0100 Rev 1 00 Page 57 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Input pins P50 to P53 Output pins P70 P90 to P96 Specify all unused pins as output pins AKKAAKKKKKKAKKKAKKKAKKKKKKAKKKAKKKKKKAKKKAKKKAKKKKKKAKKKAKKKAKKKKKKAKKKKKKKKKKKKK
31. the fixed cycle interrupt here i Yxkxxk kxkkkkkkkkkkkkkkkkkikkkikkkkikkkkikkkikkkkkkkkkkkkkkkkkkkkkkkkkkikkkkki ke k RO1AN0193EJ0100 Rev 1 00 Page 75 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Title Alarm interrupt processing using the 1 interrupt ok ck ck Ck Ck Ck Ck Ck Ck Ck Ck Ck ok Ck ck ok ck Ck Ck Ck Ck Ck Ck Ck ck ck ck ck ck ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ok ok ck ck ck ck ck ck ko ck ck ck ck kk Module interrupt void fn IntRtcl void Arg Ret Note This processing executes INTRTC1 interrupt processing KAKKAKKKKKKKAKKAKKKAKKKAKKAKKKAKKKAKKKKKKAKKKAKKKAKKAKKKAKKKKKKKKKKKKK f interrupt void fn IntRtcl void If normal operation if ucMode MODE WATCH P7L 0 0 Start buzzer output ucBuzzerTimer BUZZER TIME Start counting value of timer for buzzer output ys Add any processing using the alarm interrupt here x JAKKKKAKKAKKKAKKKAKKAKKKAKKKKAKKAKKKAKKKKAKKAKKKAKKKA Title Low voltage detection interrupt processing using the INTLVI interrupt KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Module __interrupt void fn_IntLvi void Arg Ret Note This processing sets the state in which the system is preparing to enter or cancel the preparation to enter the RIC
32. void fn InitLcd void Specify the initial settings for the LCD module extern void fn LcdChrDisp unsigned char ucChar unsigned char ucPos unsigned char ucType Perform character display processing extern void fn LcdCurDisp unsigned char ucPos Perform cursor display processing RO1AN0193EJ0100 Rev 1 00 Page 58 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Define variables and constants unsigned char ucMode MODE WATCH MODE TIMESETUP MODE ALARMSETUP MODE RESET define define define define unsigned char ucDisplay define define DIS DIS P WATCH P RESET unsigned char ucSetupTime define define define define define define define define define SET SET SET SET SET SET SET SET SET unsigned char define define define define define unsigned c unsigned c define unsigned c unsigned c define unsigned c unsigned c define define define define define define SET SET SET SET SET har nar BL PID 7 _TMNONE PIID T PIID 7 TMMONTH PIID T 1 1 1 PIID 7 TMYEAR TMDAY TMNEEK TMHOUR IMMIN MSEC UP ALARM IME NUM ucSetupAlarm UP ALNONE UP ALWEEK UP ALHOUR UP ALMIN NUM ucColonBlink 0x00 0x01 Oxff 0x00 0x01 0x02 0x03 0x04 0x05 0x06 Oxff 0x00 0x01 0x02 ucBlinkDispTimer NKDISPTIME har ucDi
33. x f ucPostt RC1CC2 0 0 Enable count register counting Fixed alarm display fn LcdChrDisp ucPostt 1 fn LcdChrDisp ucPostt 1 fn LcdChrDisp A ucPostt 1 fn LcdChrDisp L ucPostt 1 fn LcdChrDisp A ucPostt 1 fn LcdChrDisp R ucPostt 1 fn LcdChrDisp M ucPostt 1 fn LcdChrDisp ucPostt 1 Alarm day of week switch RCIALIN R01ANO193EJ0100 Rev 1 00 Sep 30 2010 13 NESAS Upper digit Lower digit Upper digit Lower digit Upper digit Lower digit Page 82 of 90 V850ES Jx3 L Everyday case 0b01111111 fn LcdChrDisp A fn LcdChrDisp L fn LcdChrDisp L break Sunday case 0500000001 fn LcdChrDisp S fn LcdChrDisp U fn LcdChrDisp N break Monday case 0500000010 fn LcdChrDisp M fn LcdChrDisp O fn LcdChrDisp N break Tuesday case 0500000100 fn LcdChrDisp T fn LcdChrDisp U fn LcdChrDisp E break Wednesday case 0500001000 fn LcdChrDisp W fn LcdChrDisp E fn LcdChrDisp D break Thursday case 0500010000 fn LcdChrDisp T fn LcdChrDisp H fn LcdChrDisp U break Friday case 0500100000 fn LcdChrDisp F fn LcdChrDisp R fn LcdChrDisp I break Saturday case 0501000000 fn LcdChrDisp S fn LcdChrDisp A fn LcdChrDisp T break default brea
34. 0100 Rev 1 00 Sep 30 2010 ENESAS Page 55 of 90 V850ES Jx3 L Real Time Counter RTC Backup Mode APPENDIX A PROGRAM LIST An excerpt from the sample program is provided below 6 main c C language Yxkxxk kxkxxkxkxxkxkxkkxkkkkkkkkikkkkikkkikkkkikkkkikkkkkkkkkkkikkkkkkkkkkkikkkkkkkikkkkikkkkki kok Renesas Electronics V850ES Jx3 L Series KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKAKAKAKAAAAAAA V850ES JG3 L Series Sample Program KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKAKAKAKAKAAAAAAA Real Time Counter RTC Backup Mode KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKAKKAKAKAKAKAKAAAAAAAA Revision History July 2010 152 edition KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKAAAAAA Overview By using the watch feature alarm feature and RTC backup mode as specified in this sample program you can achieve a watch with alarm that continues operating even if the supply voltage VDD stops lt Main initial settings gt Specification using option byte Specify the oscillation stabilization time after a reset Settings for initialization after a reset e Specify the Initial settings for RTC backup mode Set the subclock oscillation mode to normal oscillation Enable the RTC backup mode e Set the system wait control register to 1 wait e Set the on chip debug mode register to normal operation mode e Sp
35. 1 Correct watch errors when RC1SEC second counter is at 00 seconds every 60 seconds Setting of watch error correction value Increment the RC1SUBC count value by the value set by using the F5 to FO bits positive correction Expression for calculating increment value Setting value of F5 to FO bits 1 x 2 Decrement the RC1SUBC count value by the value set by using the F5 to FO bits negative correction Expression for calculating decrement value Inverted value of setting value of F5 to FO bits 1 x 2 Caution H the F6 to FO bit values are 1 0 0 0 0 0 0 1 0 watch error correction is not performed Remarks 1 Watch error correction is disabled in RTC backup mode 2 This register is reset to 00H when the RVpp power supply is applied If a reset 1s triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained This register is set to an initial value of 00H in this sample program RO1ANO193EJ0100 Rev 1 00 Page 49 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 2 Watch error correction example The watch can be accurately counted by incrementing the RCISUBC count value if a positive error faster than 32 768 kHz occurs at the resonator Similarly if a negative error slower than 32 768 kHz occurs at the resonator the watch can be accurately counted by decrementing the RCISUBC count value The RCISUBC correc
36. 1CC2 RWST 0 Check whether the previous write to RC1SEC to RC1YEAR is completed Yes RC1CC2 RWAIT 1 Stop the RC1SEC to RC1YEAR counters Set the counter value write read mode Check the counter wait status oie Read RC1SEC Read each count register Read RC1MIN Read RC1HOUR Read RC1WEEK Read RC1DAY Read RC1MONTH Set RC1YEAR RC1CC2 RWAIT 0 Start the RC1SEC to RC1YEAR counters Note Be sure to confirm that RWST 0 before setting the stop mode Caution Ensure that the series of operations from setting RWAIT to 1 to clearing RWAIT to 0 is completed within 1 second If RWAIT lis set the operation of RCISEC to RCIYEAR is stopped If a carry occurs from RCISUBC while RWAIT 1 one carry can be internally retained However if two or more carries occur the number of carries cannot be retained Remark RCISEC RCIMIN RCIHOUR RCIWEEK RCIDAY RCIMONTH and RCIYEAR may be read in any sequence Not all the registers have to be set or read RO1AN0193EJ0100 Rev 1 00 Page 39 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 16 Software coding example A section of the sample program is given below as an example of how to write the software code for setting the real time counter The following operations are specified in this sample code Setting the subclock fxr as the real time operating clock Setting the fixed cycle interrupt to be generated every 0 5 seconds Setting the count star
37. 2 8 V or higher Specify PLL mode 5 MHz x 4 20 MHz operation Set the CPU clock oscillation stabilization time after the standby mode is released to about 1 6 ms Specify the real time counter settings Set the count start time to 13 00 00 on April 1 2010 Thursday Set the alarm time to 14 00 everyday Set the fixed cycle interrupt operation to a cycle of 0 5 seconds Enable the alarm interrupt Set the interval operation to about 3 9 ms Start the count operation Specify the initial settings for the LCD module Enable the key interrupt KRO to KR3 operation Specify the interrupt settings Enable the INTKR interrupt Enable the INTRTCO interrupt RO1ANO193EJ0100 Rev 1 00 Page 4 of 90 Sep 30 2010 13 NESAS V850ES Jx3 L Enable the INTRTC1 interrupt Real Time Counter RTC Backup Mode Enable the INTLVI interrupt Enable acknowledgment of maskable interrupt request signals Notes 1 For details about the low voltage detector see the V850ES Jx3 L user s manual 2 This wait state is for satisfying the operating condition of a supply voltage of 2 7 V or higher 3 After a reset this setting is omitted if the real time counter has already started operating 2 Processing after specifying initial settings After specifying the initial settings the system shifts to stop mode An interrupt is then generated and program execution starts according to the generated interrupt e If the
38. 67 of 90 Sep 30 2010 ENESAS V850ES Jx3 L RCICKS Select the operating clock 0 The operating clock is fXT 1 The operating clock is fBRG 4 RC1PWR Enable or disable the real time counter 0 Disable 1 Enable f RC1CC0 7 1 Enable the real time counter RCICCI 0b00001001 CT2 CT0 Select the cycle of the fixed cycle interrupt 000 Not used counter day 00 minutes and 00 seconds 4 AMPM Select the 12 hour format or 24 hour format 0 12 hour format AM and PM are displayed 1 24 hour format 0 Disable output from the RTCIHZ pin 1 Hz 1 Enable output from the RTCIHZ pin 1 Hz Always set to 0 4 RTCE Enable or disable the counters 0 Disable the counters 1 Enable the counters Specify the settings for the watch error correction feature fn RtcCorrect 0500000000 Set the initial value of the count start time to 13 00 00 on April 1 2010 011 Occurs once a minute at 00 seconds every minute CLOEO Enable or disable output from the RTCCL pin 0 Disable output from the RTCCL pin 32 768 kHz 1 Enable output from the RTCCL pin 32 768 kHz CLOE1 Enable or disable output from the RTC1HZ pin Real Time Counter RTC Backup Mode INTRTCO 001 Occurs once every 0 5 seconds synchronized with the second 010 Occurs once a second whe
39. 78 8001 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 JIn Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2010 Renesas Electronics Corporation All rights reserved Colophon 1 0
40. ALM and RC1ALH registers is reached while RC1WEEK is set to 04H Thursday RC1ALW3 Alarm interrupt day of week bit 3 Do not generate alarm interrupt if RC1WEEK 03H Wednesday 1 Generate an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 03H Wednesday RC1ALW2 Alarm interrupt day of week bit 2 Do not generate alarm interrupt if RC1WEEK 02H Tuesday Generate an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 02H Tuesday RC1ALW1 Alarm interrupt day of week bit 1 Do not generate alarm interrupt if RC1WEEK 01H Monday 1 Generate an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RCTWEEK is set to 01H Monday RC1ALWO Alarm interrupt day of week bit 0 Do not generate alarm interrupt if RC1WEEK 00H Sunday 1 Generate an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RCTWEEK is set to 00H Sunday Cautions 1 Be sure to set bit 7 to 0 2 See the V850ES Jx3 L user s manual for details about how to change the alarm day of vveek setting register RC1ALVV while the real time counter is operating Remarks 1 This register is reset to 00H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the re
41. IMK 1 Disable the INTLVI interrupt LVIIF 0 Clear the INTLVI interrupt request flag asm st b r0 PRCMD Specify that low voltage detection is to be used as an interrupt asm st b r0 LVIM XE LVIS 0b00000000 Set the low voltage detection level to 2 80 V Enable low voltage detection asm push r10 22 asm mov 0x80 r10 asm st b r10 PRCMD m asm st b r10 LVIM ns asm pop r10 m Wait for the low voltage detector to stabilize about 0 2 ms for ucCounter 0 ucCounter lt 15 ucCountertt NOP Wait until the power supply voltage is higher than the low voltage detection level while LVIF NOP RO1AN0193EJ0100 Rev 1 00 Page 66 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Ykxkxxk kxkkkkkkkkkkkkkkkkkikkkikkkkkkkkikkkkkkkkkkkkkkikkkkkkkkkkkkkkkikkkki ki ke Title Processing to specify the initial settings of the clock KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKAKAKAKAK Module static void fn InitClock void Arg Ret Note This processing specifies the clock IE RE A E A k yk A 2 22 2 e e 2 ok AE 222 2 22 2 22 2 2 222 2 22 2 222 2 kk 2 222 2 22 x kk 2 e x x static void fn InitClock void SELPLL 1 Specify the PLL mode Specify no division of the CPU clock and specify normal oscillation for the subclock asm st b r0 PRCMD ys s
42. RC1SUBC Correction Value Frequency of Connected Clock Including Steady State Deviation B 1000000 Nocomedan FCCC D 1000001 Nocomedion T S D 1000010 ncrements RCTSUBC count value by 2 once every 60 seconds 326803533 KHz D 1000011 increments RCTSUBC count value by 4 once every 60 seconds 3276806667 kHz 0 000100 ncrements RCTSUBC count value by 6 once every 60 seconds 32 76810000 KHz 111011 Increments RC1SUBC count value by 120 once every 60 32 77000000 kHz seconds poss Increments RC1SUBC count value by 122 once every 60 32 77003333 kHz seconds 111111 Increments RC1SUBC count value by 124 once every 60 32 77006667 kHz upper seconds limit 1000000 Nocmedon 9 1000001 Jo eorreciion TT 000010 Decrements RC1SUBC count value by 124 once every 60 32 76593333 kHz lower seconds limit 000011 Decrements RC1SUBC count value by 122 once every 60 32 76596667 kHz seconds 000100 Decrements RC1SUBC count value by 120 once every 60 seconds 32 76600000 kHz 111011 Decrements RC1SUBC count value by 6 once every 60 seconds 111110 Decrements RC1SUBC count value by 4 once every 60 seconds 111111 Decrements RC1SUBC count value by 2 once every 60 seconds 2 76790000 kHz 2 76793333 kHz 2 76796667 kHz RO1ANO193EJ0100 Rev 1 00 Page 53 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 3 Software coding example This sample program provides a
43. RENESAS V850 Microcontrollers ROTANG 8360100 ev 1 V850ES Jx3 L Sep 30 2010 Real Time Counter RTC Backup Mode Introduction This application note is about a sample program that can be used to shift the V850ES Jx3 L microcontroller to RTC backup mode so that the real time counter used for the watch feature can continue operating if the power supply voltage Vpp stops The application note describes how the sample program works how the program should be used and how to set and use the real time counter Target Devices uPD70F3792 uPD70F3793 uPD70F3794 uPD70F3795 uPD70F3796 RO1ANO193EJ0100 Rev 1 00 Page 1 of 90 Sep 30 2010 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Contents 12 OVERVIEW 3 1 1 Overview of Sample Programin za ea 4 1 2 Watch Display eee ete teen tee eee enne nennen nnns 6 2 CIRCUIT aaa nanen eseve eee even ee vene eee eee ee eee eee ere RK nennen eene enne nene 11 2 1 ee aer ed as 11 2 2 Devices Used Other Than Microcontroller sse eee 13 pco gni ae i nk PO dt dh 14 3 1 FUS Organization ener a d 14 23 2 On Chip Peripherals USE nuancave reet tte eerte tne ke er r 15 3 3 Initial Settings and Operation Overview aaa even ee vene eee 15 S ME Ee aa
44. RTC backup control register 0 RTCBUMCTLO Subclock low power operation control register SOSCAMCTL 1 RTC backup control register 0 RTCBUMCTLO The RTCBUMCTLO register controls the RTC backup mode Figure 4 2 1 Format of RTC Backup Control Register 0 RTCBUMCTLO RTC backup control register 0 RTCBUMCTLO Address FFFFFBOOH 7 6 5 4 3 2 1 0 FSMEN 0 To To To 0 9 Tremser Sne Using RTC backup mode is disabled 1 Using RTC backup mode is enabled RBMSET RTC backup mode setting Exiting the RTC backup mode Setting the RTC backup mode When the RBMSET bit is set to 1 switch the RTC status to the following e Select a divided subclock fxr as the RTC input clock e Stop RTC pin output e Stop RTC time error correction Cautions 1 Do not set the RBMEN and RBMSET bits to 1 at the same time If they are set to 1 at the same time the RTC backup mode might not operate correctly Set the RBMEN bit to 1 first and then set the RBMSET bit to 1 Do not set the RBMSET bit to 1 while the RBMEN bit is 0 If the RBMSET bit is set to 1 at this time the bit is set to 1 but the RTC backup mode is not specified The RTCBUMCTLO register is a special register that can only be written in a specific sequence For details about special registers see the V850ES Jx3 L user s manual Be sure to set bits 1 to 6 to 0 Remarks 1 This register is reset to 00H when the RVpp power supply is applied If a reset is tri
45. RTCIIF and INTRTC2 interrupt request flag RTC2IF lt 12 gt Enable the INTRTCO and INTRTCI interrupts 13 Enable the real time counter count operation by using bit 7 RTCE of the RCICCI register RO1AN0193EJ0100 Rev 1 00 Page 40 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode pragma interrupt INTRTCO fn IntRtcO0 Fixed cycle interrupt processing Le pragma interrupt INTRTC1 fn IntRtcl Alarm interrupt processing dee E EE d n o o RCICCD 0500000000 RCICECO T 1 Enable real time counter RCICCI 0500001001 le Set count start time to 13 00 00 on April 1 2010 Thursday RCISEC 0x00 RCIMIN 0x00 RC1HOUR RCINEEK 0x04 RC1DAY z L RCIMONTH 0x04 RCIYEAR Specify initial setting for alarm time 14 00 everyday RClALW Ox7F RCIALH 0x14 lt 8 gt RCIALM 0200 RE RTCOIF 0 Clear INTRTCO interrupt request flag RECHTE tp Clear INTRTC1 interrupt request flag RIC2TE 0 Clear INTRTC2 interrupt request flag RTCOMK OF Enable INTRTCO interrupt RTCIMK OF Enable 1 interrupt RTC2MK HZ Disable INTRTC2 interrupt EI Enable acknowledgment of interrupt request signals RC1CC1 7 1 2 RO1ANO193EJ0100 Rev 1 00 Page 41 of 90 Sep 30 2010 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 4 2 Setting RTC Backup Mode The following registers control the RTC backup mode
46. Second em 7 Er Al rm Alarm hour minute Remarks 1 When the current time and day values match the alarm settings a buzzer sound is output for 1 second 2 After a reset an indication that the system has been restored from the reset state alternates with the watch display every 1 5 seconds Inputting any key sets the display to the watch display m RO1ANO193EJ0100 Rev 1 00 Page 6 of 90 Sep 30 2010 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 2 Key operation Day time and alarm settings are changed by key operations keys 1 to 4 lt 1 gt Key 1 operation Key 1 is used to specify the mode as follows setting key Normal operation watch display date and time setting alarm setting normal operation watch display 511 HRGS Hi bbi TT Normal operation vvatch display m TT TED Date and time setting eir SES Pe Llisiiarisi ED Pele 11 Alarm setting gt rm gt gt rm m gt Remark The settings being specified are ringed in black RO1ANO193EJ0100 Rev 1 00 Page 7 of 90 Sep 30 2010 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 2 Key 2 operation Key 2 is used to increment the value up key Specifying the alarm day of week setting The value being set is switched as follows ALL SUN MON TUE WED THU FRI SAT ALL po LS bihi r ee NE lt Specifying
47. Setting a value other than 01 to 12 21 to 32 AMPM bit 0 or 00 to 23 AMPM bit 1 to the RCIHOUR register is prohibited Remarks 1 This register is reset to 12H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained 2 This register is set to an initial value of 13H AMPM bit 1 in this sample program Figure 4 1 7 Format of Hour Count Register RC1HOUR Hour count register RCIHOUR Address FFFFFAD4H 7 6 5 4 3 2 1 0 Lo oj j j RO1AN0193EJ0100 Rev 1 00 Page 30 of 90 Sep 30 2010 132 NESAS V850ES Jx3 L Table 4 1 Time Digit Display Time RC1HOUR Register Value 00 a m 00 a m 00 a m 00 a m 00 a m 00 a m 00 a m 00 a m 00 a m 00 a m 0 00 a m 1 00 a m 00 p m 00 p m 00 p m 00 p m o N I ololo DAD o I NIN NR N I r r cr 2 Hour Display AMPM Bit 0 oj IN o o do ZI IT k l AT A CO N Oil BR oO olo olojo olo Ol lO Real Time Counter RTC Backup Mode Table 4 1 shows the relationship between the AMPM bit value the RCIHOUR register value and the time 24 Hour Display AMPM Bit 1 i RC1HOUR Register Value e e 3 e o olo o N e o o N I ololo DAD o N o I e a
48. TI PCT4 and PCT6 to output mode PCTO PCTI PCT4 and PCT6 Not used Page 65 of 90 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode a EIE EIE IESU EIE ie et ness Specify the setting of port DH r s P H PDH 00500000000 Set the output data of PDHO to PDH4 to 0 PMDH 0b11100000 Set PDHO to PDH4 to output mode PDHO to PDH4 Not used mmm ae Nee Uses esee ARE p Specify the setting of port DL nese PDL 0b0000000000000000 Set the output data of PDLO to 15 to PMDL 0b0000000000000000 Set PDLO to PDL15 to output mode PDLO to PDL15 Not used JAKKKKAKKKAKKKAKKKAKKKK KKK KKKAKKAKKKAKKKKAKKAKKKAKKKAKKKAKKKAKKKKAKKAKKKAKKAK Title Low voltage detection processing ck ck ck ck ck ck k k ck ck Xk k ck k ck kek A kk ck ck HI kc ck k ck AH ck ck ck TA ck AH ck A A ck AH KH A ck k k k KH A KH ck k ck ko ko A kc A ko ko ko ko ko Module static void fn InitLvi void Arg Ret Note This processing starts low voltage detection by checking k whether the power supply voltage is within the range required to operate the CPU clock KAKKKAKKKAK KKK ke kk ke kk ko ke kk ke ke kk ke kk 2 2 2 22 2 2 212 2 222 2 212 2 2 22 2 222 2 22 2 2 22 2 2 2 2 2 22 2 2007 static void fn InitLvi void unsigned char ucCounter LV
49. V pin output Enable RTCDIV pin output CKDIV RTCDIV pin output frequency selection Output 512 Hz 1 95 ms from RTCDIV pin 1 Output 16 384 kHz 0 061 ms from RTCDIV pin ICT2 ICT1 ICTO Interval interrupt INTRTC2 selection 277 xr 1 953125 ms 2 3 90625 ms 2 fxr 7 8125 ms 2 fxr 31 25 ms fxr 62 5 ms Hyr 125 ms o jar 1 1 1 Z k 15 625 ms Lo o 1 x fp Cautions 1 The RTCDIV output operates as follows when the CLOE2 bit setting is changed When changed from 0 to 1 A pulse set by the CKDIV bit is output within two clocks 2 x 32 768 kHz e When changed from 1 to 0 Output of the RTCDIV output is stopped within two clocks fixed to low level 2 x 32 768 kHz Be sure to set bits 3 and 4 to 0 Remarks1 In RTC backup mode disable the interval interrupt and RTCDIV pin output 2 This register is reset to 00H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained The parts written in red in the above figure are the values set by using this sample program RO1ANO193EJ0100 Rev 1 00 Page 28 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 5 Second count register RCISEC The RCISEC register is an 8 bit register that takes a value of 0 to 59 decimal and indicates the count value of th
50. able the maskable interrupts to be used Enable acknowledgment of interrupt request signals Start real time counter count operation Can shift to standby Note 10 Shift to standby Cycle of about 3 9 ms Clear INTRTC2 interrupt request Key detected Main loop Perform key sampling processing 1 Valid key input detected Clear notification of valid key input Key processing j Display refresh request issued Clear display refresh request Perform display refresh processing R01ANO193EJ0100 Rev 1 00 Sep 30 2010 Page 17 of 90 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Notes 1 Referencing the option byte is performed automatically by the microcontroller after the reset is cancelled In this sample program the oscillation stabilization time after reset 1s cancelled is set to 6 554 ms 2 If the real time counter is already operating after reset is cancelled the date and time registers might have stopped counting due to the processing that was executed before the reset signal was input The count operation of the date and time registers is therefore enabled here 3 Specify the settings of the VSWC OCDM RCM and WDTM 2 registers These registers should be set as follows Set the system wait control register VSWC to 1 wait Set the on chip debug mode register OCDM to normal operation mode Stop internal oscillat
51. ail iatale ciliegia 17 4 SPECIFYING S TITIN G Sa cast nd k st dd sh yn tr me e ede t EE ER ee 24 4 1 Selling the Real Time Counter cioe a 24 4 2 Setting RTO Backu p MOde t each 42 4 3 Watch Error CorrectlOri n ra ree kn ah 49 5 RELATED DOCUMENTS ee een lilla 55 APPENDIX A PROGRAMILIS Ta eset ai ee end 56 RO1AN0193EJ0100 Rev 1 00 Page 2 of 90 Sep 30 2010 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 1 OVERVIEW This document describes the real time counter of the V850ES JG3 L uPD70F3792 uPD70F3793 uPD70F3794 4PD70F3795 and uPD70F3796 including the watch feature alarm feature watch error correction feature and RTC backup mode By using the watch feature alarm feature and RTC backup mode as specified in the sample program you can achieve a watch with alarm that continues operating even 1f the supply voltage Vpp stops Operational overview slo eee T l iz LINHA Hia bbi TL Watch display 4 Na Key operation Buzzer output AL Vpp supply stopped RTC backup mode AL Vpp supply resumed external reset input El LSR Ha bbi TT i Counting continues Watch display while Vpp supply is stopped H 17 Key operation Buzzer output Remarks 1 In the RTC backup mode the subclock and real time counter use the RTC backup power supply RVpp 2 Inthis sample program it is assumed that an electric double layer capa
52. ak Hour case SETUP_ALHOUR RCIALH fn BcdCount RCIALH break Minute case SETUP ALMIN RC1ALM fn BcdCount RC1ALM break default break 11 1 0 Il e RC1CC2 7 1 Everyday Previous day ucInc 0 23 clne 0 59 y Clear the INTRTC1 interrupt request flag Enable the INTRTCI interrupt Enable the alarm interrupt JAKKKKAKKKKKKAKKKAKKAKKKAKKKKKKAKKKAKKKAKKAKKKAKKKAKKKKKKAKKKAKKKAKKKKKKK Title Processing to count the BCD value KKEKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Module static unsigned char fn BcdCount unsigned char ucNum unsigned char ucInc ik E unsigned char ucMin unsigned char ucMax Arg ucNum Added value BCD format x ucInc Inc Dec True Increment False Decrement R01ANO193EJ0100 Rev 1 00 Sep 30 2010 13 NESAS Page 72 of 90 V850ES Jx3 L Real Time Counter RTC Backup Mode ucMin Minimum value ucMax Maximum value Ret Calculation result BCD format Note This processing increments and decrements the BCD value KKAAKKAKKKAKKKAKKKAKKAKKKAKKKAKKAKKKAKKKAKKKKKKAKKKAKKKKKKAKKKKKKKKKKKKKJ static unsigned char fn BcdCount unsigned char ucNum unsigned char ucInc unsigned char ucMin unsigned char ucMax unsigned char ucWork Convert the added value to an integer value ucWork ucNum amp
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54. c The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designe
55. cautions need to be taken for PW boards with mounted semiconductor devices 4 STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions 5 POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power
56. cdChrDisp R01ANO193EJ0100 Rev 1 00 Sep 30 2010 Ul UN M ro TN T VE EU m m D UD PEN YOE TREE R sr ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 131 NESAS Lower digit Upper digit Lower digit Upper digit Lower digit Page 81 of 90 V850ES Jx3 L Real Time Counter RTC Backup Mode fn LcdChrDisp A ucPost 1 fn LcdChrDisp T ucPostt 1 break default break Blank fn LcdChrDisp ucPostt 1 Ho r fn LcdChrDisp 1 gt gt 4 amp x f ucPostt fn LcdChrDisp RCIHOUR amp x f ucPostt 0 te on if ucColonBlink fn LcdChrDisp ucPostt 1 VE else fn LcdChrDisp ucPostt 1 Minute fn LcdChrDisp RCIMIN gt gt 4 6 0x0f ucPost fn LcdChrDisp RCIMIN 6 x f ucPos NEN son Sf if ucColonBlink fn LcdChrDisp ucPostt 1 fe 17 BE else fn LcdChrDisp ucPostt 1 Second fn LcdChrDisp RC1SEC gt gt 4 amp x f ucPostt 0 fn LcdChrDisp 15 6
57. cify the I O port settings eSpecify the low voltage detector settings eSpecify PLL mode 5 MHz x 4 20 MHz operation eSet the CPU clock oscillation stabilization time after the standby mode is 77777 about 1 6 ms If the real time counter is If the real time counter is stopped operating Specify the real time counter settings Set the count start time to 13 00 00 on April 1 2010 Thursday Set the alarm time to 14 00 everyday Set the fixed cycle interrupt to occur every 0 5 seconds Enable the alarm interrupt Set the interval operation to about 3 9 ms Start the count operation eSpecify the initial settings for the LCD module eEnable the key interrupt KRO to KR3 operation Settings 2 eSpecify the interrupt settings Enable the INTKR interrupt Enable the INTRTCO interrupt Enable the INTRTC1 interrupt Enable the INTLVI interrupt Enable acknowledgment of maskable interrupt request signals Perform post reset processing Key Execute normal processing An indication that the system has been restored input Display the watch data from the reset state alternates with the watch Refresh the watch display every 0 5 seconds display every 1 5 seconds Refresh the watch display when a key is The watch display is refreshed every 0 5 manipulated seconds once the watch display has been set Output a buzzer when an alarm is generated Low voltage
58. citor 0 1 F is used so that the power supply to the RTC backup power supply RVpp can continue for a certain period if the supply voltage Vpp stops For details about the circuits see 2 1 Circuit Diagram RO1ANO193EJ0100 Rev 1 00 Page 3 of 90 Sep 30 2010 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 1 1 Overview of Sample Program This sample program is used to specify the initial settings for the real time counter fixed cycle interrupt alarm interrupt interval interrupt RTC backup mode and key interrupt features Details are provided below 1 Main initial settings The main initial settings are as follows Specification using option byte 6 Specify the oscillation stabilization time after a reset Settings for initialization after a reset Specify the initial settings for RTC backup mode Set the subclock oscillation mode to normal oscillation Enable the RTC backup mode Set the system wait control register to 1 wait Set the on chip debug mode register to normal operation mode Specify stopping the internal oscillator Stop watchdog timer 2 Specify the I O port settings Specify P50 to P53 KRO to KR3 as key input Specify P70 as buzzer control Specify P90 to P96 as LCD module control Set the unused ports Specify the low voltage detector settings Set the low voltage detection level to 2 8 V Enable low voltage detection e Wait until the supply voltage becomes
59. ck Operation E RC1CC2 RWST 0 Check whether the previous write to RC1SEC to RC1YEAR counters is completed Yes RC1CC2 RWAIT 1 Stop the RC1SEC to RC1YEAR counters Set the counter value write read mode Check the counter wait status Note Select the watch counter display method Write RC1SEC Write to each count register Write RC1MIN Write RCTHOUR Write RCTWEEK Write RC1DAY Write RC1MONTH Set RC1YEAR RC1CC2 RWAIT 0 Start the RC1SEC to RC1YEAR counters Note Be sure to confirm that RWST 0 before setting the stop mode Caution Ensure that the series of operations from setting RWAIT to 1 to clearing RWAIT to 0 are completed within 1 second If RWAIT 1 is set the operation of RCISEC to RCIYEAR is stopped If a carry occurs from RCISUBC while RWAIT 1 one carry can be internally retained However if two or more carries occur the number of carries cannot be retained Remark RCISEC RCIMIN RCIHOUR RCI WEEK RCIDAY RCIMONTH and RCIYEAR may be rewritten in any sequence Not all the registers have to be set or read RO1AN0193EJ0100 Rev 1 00 Page 38 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 3 Reading counters during real time counter operation Set as follows when reading the counters RCISEC RCIMIN RCIHOUR RCIWEEK RCIDAY RCIMONTH RCI YEAR during real time counter operation RCIPWR 1 RTCE 1 Figure 4 1 15 3 Reading Counters During Clock Operation RC
60. ckup Mode Perform real time counter initial setting processing Stop real time counter Set real time counter operating clock to fxr Enable real time counter operation Set fixed cycle interrupt to be issued every 0 5 seconds Specify settings for watch error correction Set count start time to 13 00 00 on April 1 2010 Thursday Disable alarm interrupt Set alarm time to 14 00 everyday Enable alarm interrupt Set interval interrupt generation cycle to about 3 9 ms and enable interval interrupt Perform RTC backup mode initial setting Enable use of RTC backup mode 2 Set subclock fxr to normal oscillation mode Notes 1 The watch error correction feature is disabled in this sample program 2 Ifthe system enters the state in which it is preparing to enter RTC backup mode after reset is canceled it exits this state here R01ANO193EJ0100 Rev 1 00 Sep 30 2010 Page 19 of 90 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Perform key processing Determine operating status Normal operation Setting date and time Is key code key 1 Shift to setting date and time Issue display refresh request Determine key code Shift to alarm setting Specify setting next item Overwrite the count Specify setting alarm value count down Overwrite the count value count up Issue display refresh request Alarm setting Key
61. d for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life 8 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 9 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and m
62. dy State Deviation 0 1000000 Nocomedan o 1000001 Nocomedon D 1000010 ncrements RCTSUBC count value by 2 once every 20 seconds 3276810000 kz D 1000011 increments RCTSUBC count value by 4 once every 20 seconds 32 76820000kHz 6 000100 ncrements RCTSUBC count value by 6 once every 20 seconds 32 76830000 kHz 111011 Increments RC1SUBC count value by 120 once every 20 32 77400000 kHz seconds DE Increments RC1SUBC count value by 122 once every 20 32 77410000 kHz seconds 111111 Increments RC1SUBC count value by 124 once every 20 32 77420000 kHz upper seconds limit 1000000 No corea CI H 1000001 Jo eorreciion F 4 000010 Decrements RC1SUBC count value by 124 once every 20 32 76180000 kHz lower seconds limit 000011 Decrements RC1SUBC count value by 122 once every 20 32 76190000 kHz seconds 000100 Decrements RC1SUBC count value by 120 once every 20 seconds 32 76200000 kHz 111011 Decrements RC1SUBC count value by 6 once every 20 seconds 111110 Decrements RC1SUBC count value by 4 once every 20 seconds 111111 Decrements RC1SUBC count value by 2 once every 20 seconds 2 76770000 kHz 2 76780000 kHz 2 76790000 kHz RO1ANO193EJ0100 Rev 1 00 Page 52 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Table 4 4 Range of Frequencies That Can Be Corrected When DEV Bit 1 F6 5 to FO
63. e seconds It counts up when the sub counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks 2 x 32 768 kHz later Set a decimal value of 00 to 59 to this register in BCD code If a value outside this range is set the register value returns to the normal value after one period This register can be read or written in 8 bit units Note The sub count register RCISUBC is a 16 bit register that holds a value of between 0000H and 7FFFH and counts up every second based on a 32 768 kHz clock For details of this register see the V850ES Jx3 L user s manual Caution Setting the RCISEC register to values other than 00 to 59 is prohibited Remarks 1 This register is reset to 00H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained 2 This register is set to an initial value of 00H in this sample program Figure 4 1 5 Format of Second Count Register RC1SEC Second count register RCISEC Address FFFFFAD2H 7 6 5 4 3 2 1 0 ppp 6 Minute count register RC1MIN The RCIMIN register is an 8 bit register that takes a value of 0 to 59 decimal and indicates the count value of the minutes It counts up when the second counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks 2 x 32 768
64. e an interrupt upon an alarm match Set the initial value of the alarm time to 14 00 everyday RCIALW Ox7F Day of week RCIALH Dal4 Hour RC1ALM 0x00 Minute RC1CC2 7 1 Enable the alarm interrupt RC1CC3 0510000001 ICT2 ICTO Select the interval of the interval interrupt INTRTC2 000 2 6 fXT 1 953125 ms 001 277 fXT 3 90625 ms 010 278 1XT 7 9125 ms 011 2 9 fXT 15 625 ms 100 2710 fXT 31 25 ms 101 2 11 fXT 62 5 ms lix 2712 1XT 125 ms Always set to 0 CKDIV Select the output frequency of the RTCDIV pin 0 Output 512 Hz 1 95 ms from the RTCDIV pin 1 Output 16 384 kHz 0 061 ms from the RTCDIV pin CLOE2 Enable or disable RTCDIV pin output 0 Disable RTCDIV pin output 1 Enable RTCDIV pin output 4 RINTE Enable or disable generation of the interval interrupt INTRTC2 1 0 Do not generate interrupt 1 Generate interrupt SY JAKKKKAKKKKKKAKKKAKKAKKKAKKKAKKKAKKKAKKKAKKAKKKAKKKAKKKAKKKAKKKKAKKAKKKAKKAK Title Processing to specify the initial settings of RTC backup mode ck ck ck ck ck ck ck ck ck ck kc ck ck ck kek kk A kek kk ck k ck A KH TA ck k ck kk A ck k ck k ck A KH TA ck k ck AH KH A KH ck k KA ko A kc A ko ko ko ko KK Module static void fn InitRtcBum void Arg Ret Note This processing enables the use of RTC backup mode IE x kk kCkCk kk Ck Ck k
65. e and time counters Counter value read write mode Cautions 1 Confirm that the RWST bit is set to 1 when reading or writing each counter value 2 The RWST bit does not become 0 while each counter is being written even if the RWAIT bit is set to 0 It becomes 0 when writing to each counter is completed Be sure to set bits 2 to 6 to 0 RWAIT Real time counter wait control Remarks 1 In RTC backup mode mask the alarm interrupt by setting the RTCIMK bit to 1 2 This register is reset to 00H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained The parts written in red in the above figure are the values set by using this sample program RO1ANO193EJ0100 Rev 1 00 Page 27 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 4 Real time counter control register 3 RC1CC3 The RC1CC3 register is an 8 bit register that controls the interval interrupt and RTCDIV pin This register can be read or written in 8 bit or 1 bit units Figure 4 1 4 Format of Real time Counter Control Register 3 RC1CC3 Real time counter control register 3 RC1CC3 Address FFFFFAEOH 3 7 6 5 4 2 1 0 SNS T coe KON 0 T 0 RINTE Interval interrupt INTRTC2 control Do not generate interval interrupt 1 Generate interval interrupt CLOE2 RTCDIV pin output control Disable RTCDI
66. e e e 22 2 2 222 2 22 2 2 22 2 222 2 222 22 2 2 22 2 2 22 2 2 22 2 22 2 2 22 2 2 22 2 22 2 2 2 2 2 2 o kok Title Main processing KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKAAAAAKAA Module Arg Ret void main void R01AN0193EJ0100 Rev 1 00 Sep 30 2010 Page 59 of 90 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Note This is the main processing executed by this sample program AKKAAKKAKKKAKKKAKKKAKKKA ok e 222 2 22 2 222 2 222 2 222 2 2 2 2 22 2 2 kok XL 22 2 22 22 kk XL 22 2 222 2 2 ke e e x x void main void DI Disable acknowledgment of interrupt request signals fn InitRtcBum Specify the initial settings for RTC backup mode RC1CC2 0 0 Enable count register counting In case the CPU is reset while counting is stopped fn InitFirst Specify the settings of the registers to be set first fn InitPort Specify the initial settings for the ports fn InitLvi Perform low voltage detection processing fn InitClock Specify the initial settings for the clock If the real time counter is initialized if RC1CC1 7 fn InitRtc Specify the initial settings for the real time counter in InitLod Specify the initial settings for the LCD module ucKeySamplingCounter KEYSAMPLINGCOUNT Key sampling count is reset ucCodeBuffer KEYCODEOFF
67. ecify stopping the internal oscillator e Stop watchdog timer 2 e Specify the I O port settings Specify P50 to P53 KRO to KR3 as key input Specify P70 as buzzer control Specify P90 to P96 as LCD module control Set the unused ports Specify the low voltage detector settings Set the low voltage detection level to 2 8 V Enable low voltage detection Wait until the supply voltage becomes 2 8 V or higher e Specify PLL mode 5 MHz x 4 20 MHz operation e Set the CPU clock oscillation stabilization time after the standby mode is released to about 1 6 ms e Specify the real time counter settings Set the count start time to 13 00 00 on April 1 2010 Thursday Set the alarm time to 14 00 everyday Set the fixed cycle interrupt operation to a cycle of 0 5 seconds Enable the alarm interrupt RO1AN0193EJ0100 Rev 1 00 Page 56 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Set the interval operation to about 3 9 ms Start the count operation e Specify the initial settings for the LCD module e Enable the key interrupt KRO to KR3 operation e Specify the interrupt settings Enable the INTKR interrupt Enable the INTRTCO interrupt Enable the INTRTCI interrupt Enable the INTLVI interrupt Enable acknowledgment of maskable interrupt request signals Processing after specifying initial settings After specifying the initial settings the system shifts to
68. efault NOP break break A At Setting date and time m v am va v vi van ve vum v vum m e p i r r p i p i case MODE TIMESETUP Determine key code switch ucKeyCode Key 1 case KEYCODE1 Shift to setting alarm ucMode MODE_ALARMSETUP Specify alarm day of week as setting item ucSetupAlarm SETUP_ALWEEK ucSetupTime SETUP_TMNONE break Key 2 case KEYCODE2 Increment time fn WriteRtcCounter 0 break Key 3 case KEYCODE3 Decrement time fn WriteRtcCounter 1 break Key 4 case KEYCODE4 Change to next item ucSetupTime ucSetupTime SETUP TIME NUM break default break ucDispReq 1 Issue display refresh request break 5 c o o r n p x Setting alarm case MODE ALARMSETUP Determine key code switch ucKeyCode Key 1 case KEYCODE1 Shift to normal operation ucMode MODE WATCH Setting item None RO1AN0193EJ0100 Rev 1 00 Page 62 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode ucSetupAlarm SETUP ALNONE break Key 2 case KEYCODE2 Increment alarm fn WriteRtcAlerm 0 break Key 3 case KEYCODE3 Decrement alarm fn WriteRtcAlerm 1 break Key 4 case KEYCODE4 Cha
69. ettings Xn while RC1CC2 1 NOP RCICC2 0 1 while NOP Year RC1CC2 1 Stop the count registers counting Check the wait status of the counters Check that the previous overwrite processing is complete fn LcdChrDisp RCIYEAR gt gt 4 6 0x0f ucPostt Upper digit RO1ANO193EJ0100 Rev 1 00 Page 80 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode fn LcdChrDisp RCIYEAR 6 Ox0f ucPostt 0 Eom fn LcdChrDisp ucPostt 1 Month fn LcdChrDisp RCIMONTH gt gt 4 amp x f ucPostt fn LcdChrDisp RCIMONTH amp x f ucPostt 0 fn LcdChrDisp ucPostt 1 Day fn LcdChrDisp RCIDAY gt gt 4 6 x f ucPostt fn LcdChrDisp RCIDAY 6 x f ucPostt Day of week switch RCIWEEK Sunday case 0x00 fn LcdChrDisp fn LcdChrDisp fn LcdChrDisp break Monday case 0x01 fn LcdChrDisp fn LcdChrDisp fn LcdChrDisp break Tuesday case 0x02 fn LcdChrDisp fn LcdChrDisp fn LcdChrDisp break Wednesday case 0x03 fn LcdChrDisp fn LcdChrDisp fn LcdChrDisp break Thursday case 0x04 fn LcdChrDisp fn LcdChrDisp fn LcdChrDisp break Friday case 0x05 fn LcdChrDisp fn LcdChrDisp fn LcdChrDisp break Saturday case 0x06 fn L
70. ettings is not required When specification of the initial settings is complete an interrupt is generated to start program execution The processing that is executed differs depending on the generated interrupt The interrupts generated to start program execution include the 0 5 second cycle INTRTCO interrupt the alarm triggered INTRTCI interrupt the 3 9 millisecond interval interrupt and the key input triggered INTKR interrupt The processing executed by the generation of these interrupts includes key manipulation LCD module control and buzzer control Another interrupt the INTLVI interrupt which is triggered by the detection of a low voltage or by the restoration of the voltage to a specific level is also used to prepare the system to enter the RTC backup mode or to cancel the preparation to enter the RTC backup mode For details about the processing flow see the status transition diagram and flow charts below RO1ANO193EJ0100 Rev 1 00 Page 15 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Specify the initial settings Settings 1 Specification using option byte eSpecify the oscillation stabilization time after a reset Settings for initialization after a reset eSpecify the initial settings for RTC backup mode eSet the system wait control register to 1 wait eSet the on chip debug mode register to normal operation mode eSpecify stopping the internal oscillator eStop watchdog timer 2 eSpe
71. f semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 5 When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations 6 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 7 Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specifi
72. function for setting the watch error correction feature This function is used to set the 1 byte data specified by the argument to the watch error correction register RCISUBU Figure 4 3 2 Function for Setting Watch Error Correction static void fn RtcCorrect unsigned char ucReg RCISUBU ucReg An example of using this function is shown below To increment the RCISUBC count by 2 every 20 seconds when the frequency of the connected clock is 32 76810000 kHz specify as follows fn RtcCorrect 0500000010 e To decrement the RCISUBC count by 4 every 60 seconds when the frequency of the connected clock is 32 76793333 kHz specify as follovvs fa RteCorrect pd 9 0 No RO1ANO193EJ0100 Rev 1 00 Page 54 of 90 Sep 30 2010 RENESAS V850ES Jx3 L 5 RELATED DOCUMENTS Real Time Counter RTC Backup Mode Document Name PDF Document No V850ES JG3 L Hardware User s Manual U20305J V850ES JG3 L On chip USB Controller Hardware User s Manual U20305E V850ES Architecture U15943E PM Ver 6 30 User s Manual U18416E CA850 Ver 3 20 C Compiler Package Operation U18512E CA850 Ver 3 20 C Compiler Package C Language U18513E CA850 Ver 3 20 C Compiler Package Link Directive U18515E QB MINI2 On Chip Debug Emulator with Programming Function U18371E ID850QB Ver 3 40 Integrated Debugger Operation U18604E Document search URL http www2 renesas com micro en documentation html R01ANO193EJ
73. ggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained The parts written in red in the above figure are the values set by using this sample program RO1ANO193EJ0100 Rev 1 00 Page 42 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 2 Subclock low power operation control register SOSCAMCTL The SOSCAMCTL register is used to set the subclock fxr to perform low power operations in the RTC backup mode Figure 4 2 2 Format of Subclock Low Power Operation Control Register SOSCAMCTL Format of subclock low power operation control register SOSCAMCTL Address FFFFFBO3H 7 6 5 4 3 2 1 0 po 0 o o j o 5 AMPHS Subclock fyr oscillation mode selection S Normal oscillation 1 Ultra low consumption oscillation Cautions 1 The SOSCAMCTL register is a special register that can only be written in a specific sequence For details about special registers see the V850ES Jx3 L user s manual 2 Be sure to set bits 7 to 1 to 0 Remarks 1 When the subclock fxr is oscillating in the ultra low consumption mode the effects of noise can more easily cause an incorrect number of oscillation cycles to be counted Before deciding to use this mode thoroughly evaluate the effects of noise This register is reset to 00H when the RVpp power supply is applied If a reset is triggered by a factor other than a
74. gister at the time the reset was triggered are retained This register is set to an initial value of 7FH Friday in this sample program RO1ANO193EJ0100 Rev 1 00 Page 36 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 15 Setting the registers Set the registers used by the real time counter as described below lt 1 gt Initial settings Specify the initial settings for the watch feature and fixed cycle interrupt as follows Figure 4 1 15 1 Initial Setting Procedure Stop the counter Select the real time counter RTC operation clock Enable real time counter RTC internal clock operation Select the 12 hour system or 24 hour system and interrupt INTRTCO Set watch error correction Set RC1SEC Set each count register Clear RC1SUBC Set RC1MIN Set RC1HOUR Set RC1WEEK Set RC1DAY Set RCIMONTH Set RC1YEAR Clear interrupt IF flag Clear the interrupt request flag RTCOIF Clear interrupt MK flag Clear the interrupt mask flag RTCOMK RC1CC1 RTCE 1 Start counter operation INTRTCO occurred Yes RO1ANO193EJ0100 Rev 1 00 Page 37 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 2 Rewriting counters during real time counter operation Set as follows when rewriting the counters RCISEC RCIMIN RCIHOUR RCIWEEK RCIDAY RCIMONTH RCIYEAR during real time counter operation RCIPWR 1 Figure 4 1 15 2 Rewriting Counters During Clo
75. he key code is not off and more than one key was not pressed at the same time if ucCodeBuffer KEYCODEOFF amp amp ucCodeBuffer KEYCODEMLT Issue a valid key input notification ucKeyValidInfo 1 RO1AN0193EJ0100 Rev 1 00 Page 79 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Update the key code ucKeyCode ucCodeBuffer To turn off the key code if ucKeyCode KEYCODEOFF Clear the key detection notification ucKeyEdgelnfo 0 KK AA AAC RR A AAC KKK 2 22 AAC RA AR 2 22 2 2 2 2 2 KKK 22 2 222 2 ke ke ke ke ke ek Title Processing to refresh the display KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKAKKAKAKAKAKAKAAKAAAAAAAA Module Arg Ret Note static void fn_Display void This processing applies display data to the display device KKAAKKKAKKKAKKKAKKKAKKKAKKKAKKKAKKAKKKAKKKAKKKAKKKAKKKAKKKKKKAKKKKKKKKKKKKKJ static void fn Display void unsigned char ucPos ucPos 0 switch ucDisplay ucBar Specify the initial display position setting x Watch display x 44 44 4444 4444444444444 11101 10141 10111 1 0 11131 10101 10101 44 44 4444 4444444444444 JAILIAIRIM A L L 1141 10101 I 44 44 4444 4444444444444 x case DISP WATCH cr cr ee tt ococvc Specify the character display s
76. if LVIF asm st b r0 PRCMD asm st b r0 SOSCAMCTL asm push r10 27 asm mov 0x80 r10 INA as n ust alloy PRCMD asm st b r10 RTCBUMCTLO asm pop 2140 NOP be KRIF RTCOIF ESGISEE KRMK RTCOMK REGIME S ode while LOCK NOP Smeg aly Caution The subclock low power operation control register SOSCAMCTL RTC backup control register 0 RTCBUMCTLO and processor clock control register PCC are special registers that can only be written in a specific sequence For details about special registers see the V850ES Jx3 L user s manual RO1ANO193EJ0100 Rev 1 00 Page 48 of 90 Sep 30 2010 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 4 3 Watch Error Correction The watch error correction feature of the real time counter is described below 1 Watch error correction register RCISUBU The watch error correction register RC1SUBU is used when the watch error correction feature of the real time counter is used RCISUBU is an 8 bit register that accurately corrects the watch when the watch is fast or slow by changing the value reference value 7FFFH overflowing from the sub count register RC1SUBC to the second counter register Figure 4 3 1 Format of Watch Error Correction Register RC1SUBU Watch error correction register RCISUBU Address FFFFFAD9H 7 6 5 4 3 2 1 0 Correct watch errors when RC1SEC second counter is at 00 20 or 40 seconds every 20 seconds
77. ion by using the RCM register Stop operation of watchdog timer 2 by using the WDTM2 register 4 Set P50 to P53 KRO to KR3 to key input P70 to buzzer control and P90 to P96 to LCD module control Set all unused ports to low level 5 Enable operation of the low voltage detector and wait until the power supply voltage reaches 2 8 V 6 Set the clock mode to PLL mode 5 MHz x 4 20 MHz Also set the CPU clock oscillation stabilization time after the system exits standby to about 1 6 ms 7 Determine whether the real time counter is in the initial state If it is already operating the initial settings are omitted 8 This processing specifies the initial settings for the LCD module used 9 Enable the INTRTCO INTRTCI INTKR and INTLVI interrupts 10 Ifno key was detected or no display refresh processing is to be performed it is possible to shift to standby 11 The system exits standby if the INTRTCO INTRTCI INTKR or INTLVI interrupt is generated 12 In this processing the key input pins are sampled three times at an interval of about 3 9 ms The sampling processing returns the key code key 1 key 2 key 3 or key 4 and a notification that a valid key input has been detected If a key is off the key detection notification for that key is cleared 13 In this processing new display data is applied to the LCD module RO1AN0193EJ0100 Rev 1 00 Page 18 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Ba
78. k Blank fn LcdChrDisp ucPost Alarm time Real Time Counter RTC Backup Mode ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 ucPostt 1 1 fn LcdChrDisp RCIALH gt gt 4 R01AN0193EJ0100 Rev 1 00 Sep 30 2010 K x f ucPos ENESAS 0 Upper digit Page 83 of 90 V850ES Jx3 L Real Time Counter RTC Backup Mode fn LcdChrDisp amp x f ucPostt Lower digit vor fn LcdChrDisp ucPostt 1 Alarm minute fn LcdChrDisp RCIALM gt gt 4 amp x f ucPos 0 Upper digit fn LcdChrDisp amp x f ucPostt Lower digit Blank fn LcdChrDisp ucPostt 1 fn LcdChrDisp ucPostt 1 fn LcdChrDisp ucPostt 1 o au Specify the cursor display settings Determine the setting item switch ucSetupTime Year is being set case SETUP_TMYEAR Cursor position Lower digit of year fn LcdCurDisp
79. k Ck k kk Ck kk A Kk Ck yk e yk xx Ck Kk Xok kk Ck KKAKKKAKKKAKKKKKKAKKKKKKKKKKKKKJ Static void fn InitRtcBum void Enable the use of RTC backup mode If the system is in the state in which it is preparing to enter backup mode after reset is cancelled exit this state here asm push r10 asm mov 0x80 r10 RO1AN0193EJ0100 Rev 1 00 Page 69 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode asm st b r10 PRCMD asm st b 210 RTCBUMCTLO asm pop rl0 27 Set the subclock to normal oscillation mode asm st b ro PRCMD s asm st b ro SOSCAMCTL ss NOP Yxxxk xkxkxkxkxkkkkkkkkkkkkikkkikkkkkkkkikkkikkkkkkkkkkkkkkkkkkkikkkikkkkkkkk ki ke k Title Processing to overwrite the real time counter count values ck ck ck ck ck kk kk e kk kk KKK KKK x x KKK KKK KKK KKK KKK KKK KKK kx x x kx kx kx ko ko ko ko kx Module static void fn WriteRtcCounter unsigned char ucInc Arg False Increment True Decrement Ret Note This processing overwrites the count values of the real time counter KKAAKKKAKKKAKKKAKKKAKKAKKKAKKKKKKAKKKAKKKAKKAKKKAKKKAKKKAKKKAKKKKKKKKKKKKKJ Static void fn WriteRtcCounter unsigned char ucinc Specify the number of days based on the month const unsigned char aDays 12 31 28 31 30 31 30 31 31 30 31 30 31 unsigned char ucWork ucRet while RC1CC2 1 Check that the previous overwrite
80. kHz later Set a decimal value of 00 to 59 to this register in BCD code This register can be read or written 8 bit units Caution Setting a value other than 00 to 59 to the RCIMIN register is prohibited Remarks 1 This register is reset to 00H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained 2 This register is set to an initial value of 00H in this sample program Figure 4 1 6 Format of Minute Count Register RC1MIN Minute count register RC1 MIN Address FFFFFAD3H 7 6 5 4 3 2 1 0 LD RO1ANO193EJ0100 Rev 1 00 Page 29 of 90 Sep 30 2010 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 7 Hour count register RCIHOUR The RCIHOUR register is an 8 bit register that takes a value of 0 to 23 or 1 to 12 decimal and indicates the count value of the hour It counts up when the minute counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks 2 x 32 768 kHz later Set a decimal value of 00 to 23 01 to 12 or 21 to 32 to this register in BCD code If a value outside this range is set the register value returns to the normal value after 1 period This register can be read or written 8 bit units Cautions 1 Bit 5 of the RCIHOUR register indicates a m 0 or p m 1 if AMPM 0 if the 12 hour system is selected 2
81. kikkkikkkkkkkkikkkikkkkkkkkikkkkkkkkkkkkkkkkikkki kok 2 ke ke ek Title Processing to overwrite the alarm setting of the real time counter KKEKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Module static void fn WriteRtcAlerm unsigned char ucInc Arg False Increment True Decrement Ret Note This processing overwrites the alarm setting of the real time counter KKAAKKKAKKKAKKKAKKKAKKAKKKAKKKAKKKAKKKAKKKAKKAKKKAKKKAKKKKKKAKKKKKKKKKKKKKJ static void fn WriteRtcAlerm unsigned char ucInc unsigned char ucCnt RTCIMK 1 RC1CC2 7 0 Determine the setting item switch ucSetupAlarm Day of week case SETUP_ALWEEK I incrementing if lucinc If everyday if RCIALN 0b01111111 Disable the INTRTC1 interrupt Disable the alarm interrupt R01AN0193EJ0100 Rev 1 00 Sep 30 2010 Page 71 of 90 13 NESAS V850ES Jx3 L RCIALN 00500000001 If Saturday Real Time Counter RTC Backup Mode Sunday else if RCIALN 00501000000 RCIALN 0501111111 Otherwise else RClALW lt lt 1 If decrementing else If everyday if RClALW 0501111111 RC1ALW 0b01000000 If Sunday Everyday Next day Saturday else if RCIALN 00500000001 RCIALN 0501111111 else RClALW gt gt 1 bre
82. lows Year month day day of week hour minute second year VSE UU A LLINERRM Pi hia bl l G iH Tele ECOLE jo iol LE T r pee T Key 4 S Pere 4 ALARM ALL 14 00 Specifying the alarm setting The items being set are switched as follows Day of week hour minute day of week DOBDCNOUUCONUEBOOBEO I TAA Brad Pee TT a a 11 d sepes Key rec Aus Top 11 Key 4 Remark The settings being specified are ringed in black RO1ANO193EJ0100 Rev 1 00 Page 10 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 2 CIRCUIT DIAGRAM This chapter shows the circuit diagram and describes the devices other than the microcontroller used in this sample program 2 1 Circuit Diagram The circuit diagram is shown below 0 1 E V850ES JG3 L VDD microcontroller A 3 KRO P50 RESET KR1 P51 REGC KR2 P52 a nu N module c S dn o A I N RO1ANO193EJ0100 Rev 1 00 Page 11 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Cautions 1 In normal operation mode use Vpp in the range of 2 8 V lt Vpp x 3 6 V Directly connect the EVDD AVREFO and AVREFI pins to Y nn Directly connect the EVSS and AVSS pins to GND Connect the REGC to GND via a capacitor recommended value 4 7 uF Connect the FLMDO pin to GND in normal operation mode Leave all the unused p
83. m st b 0 PCC Specify the CPU clock oscillation stabilization time after the system exits standby mode OSTS 0000000011 OSTS2 OSTSO Select the oscillation stabilization time setup time 000 2 10 fX 001 2 117 fX 010 2 12 fX 0112 2 137 X 100 2 14 fX 101 2 15 fX 110 2 16 fX 111 Setting prohibited Always set to 0 f Yxkxkxk kxkxkxkkkkkkkkkkkkkkkikkkkkkkkkkkkkkikkkkikkkkikkkkkkkkkkkkkkkkkkkkkk AAA Title Processing to specify the initial settings of the real time counter KKEKKKKKKKKKKKKKKKKKKKKKKKKKKKKK ck KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK kx Sk ko ko ko Module static void fn InitRtc void Arg Note This processing does the following Sets the count start time to 13 00 00 on April 1 2010 Thursday Li Specifies that the fixed cycle interrupt INTRTCO occurs every 0 5 seconds Specifies that the alarm interrupt 1 occurs at 14 00 everyday ik Specifies that the interval interrupt INTRTC2 occurs about every 3 9 ms KKAAKKKAKKAKKKAKKKAKKAKKKAKKKKAKKAKKKAKKKAKKAKKKAKKKAKKKKKKAKKKKKKKKKKKKK static void fn InitRtc void RC1CC0 7 0 Stop the real time counter EEE OE ORO RO EE Specify the setting of the fixed cycle interrupt S SO I I RI SIR SERE urat ur wr rr RE RC1CCO 0000000000 III Always set to 0 RO1AN0193EJ0100 Rev 1 00 Page
84. n the second counter increments 100 Occurs once an hour at 00 minutes and 00 seconds every hour 101 Occurs once a day at 00 hours 00 minutes and 00 seconds every 11x Occurs once a month on the first day of the month at 00 hours Thursday RC1SEC 0x00 RCIMIN 0x00 RC1HOUR 0x13 RCLWEEK 0x04 RCIDAY 0x01 RCIMONTH 0x04 RClYEAR 0x10 er Vor tur io iud Di ius Uy ius iow quy Qo iuo Qu iur doe Que dew tuu Qu Qd iow teer iow ius eu tes tow E er rg Uns Uer y Gen ias Des ion Qa Ss Dew ios Qon Qs Qe ien ES EHE Specify the settings for the alarm interrupt a i Rer H M r SP RC1CC2 0000000000 III III I RWAIT Specify the wait condition for the real time counter III 0 Counter operation enabled bli 1 Date and time counter operation stopped III II II The count value is read out and the system shifts to write mode II 111 I RWST The wait status of the real time counter R01ANO193EJ0100 Rev 1 00 Sep 30 2010 ENESAS Page 68 of 90 V850ES Jx3 L Real Time Counter RTC Backup Mode ENSEM 0 Counter is operating III 1 Date and time counters have stopped counting The count value III has been read out and the system is in vrite mode Always set to 0 WALE Enable or disable generation of the alarm interrupt INTRTC1 0 Do not generate an interrupt upon an alarm match 1 Generat
85. n this sample program Figure 4 1 13 Format of Alarm Hour Setting Register RC1ALH Alarm hour setting register RC1ALH Address FFFFFADBH 7 6 5 4 3 2 1 0 Le k RO1AN0193EJ0100 Rev 1 00 Page 35 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 14 Alarm day of week setting register RCIALW The RCIALW register is an 8 bit register that is used to set the day of week of the alarm This register can be read or written in 8 bit units Figure 4 1 14 Format of Alarm Day of Week Setting Register RC1ALW Alarm day of week setting register RCIALW Address FFFFFADCH 7 6 5 4 3 2 1 0 o ROTALW6 RCTALWS RCTALWA RCTADWS ROTALW2 RCTALW 1 RCTALWO Saturday Friday Thursday Wednesday Tuesday Monday Sunday RC1ALW6 Alarm interrupt day of week bit 6 Do not generate alarm interrupt if RC1WEEK 06H Saturday 1 Generate an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RC1WEEK is set to 06H Saturday RC1ALW5 Alarm interrupt day of week bit 5 Do not generate alarm interrupt if RC1WEEK 05H Friday 1 Generate an alarm interrupt if the time specified by using the RC1ALM and RC1ALH registers is reached while RCTWEEK is set to 05H Friday RC1ALWA Alarm interrupt day of week bit 4 Do not generate alarm interrupt if RC1WEEK 04H Thursday 1 Generate an alarm interrupt if the time specified by using the RC1
86. nge to next item ucSetupAlarm ucSetupAlarm SETUP_ALARM_NUM break default break ucDispReq 1 Issue display refresh request break Rr ad ent ves at ad at oh et act aa Hr 1 1 Post reset Vul ved uud vd pad vwd nd ved Ded ved ad o case MODE RESET ucMode MODE WATCH Shift to normal operation ucDisplay DISP WATCH Change to watch display ucBlinkDispTimer 0 Stop blinking display ucDispReq 1 Issue display refresh request break default break yx Display refresh processing ye There is a display refresh request if ucDispReq ucDispReq 0 Clear the display refresh request fn Display Refresh the display Ykxkxxk kkkkkkkkkkkkkkkkkkikkkikkkkkkkkkkkikkkkkkkkkkkkkkkkkkkkkkkkkkkkkkki ek Title Processing to specify the settings of the registers to be set first ok ck ck ck ck A E ck ck ck kc ck k ck kek A ck ke kek A ka AH KH A ck k ck AH KH A A ck ka AH KH A ck k k A kk kk A ko A kc A ko ko ko ko ko Module static void fn InitFirst void Arg Ret Note This processing sets the VSWC OCDM RCM and WDTM2 registers KKAAKKAKKKAKKKAKKKAKKAKKKAKKKAKKAKKKAKKKA KKK KKAKKKAKKKKKKAKKKKKKKKKKKKKJ RO1AN0193EJ0100 Rev 1 00 Sep 30 2010 ENESAS Page 63 of 90 V850ES Jx3 L Real Time Counter RTC Backup Mode static void fn InitFirst void ieu uei uiii War
87. nterrupt request signals RC1CC1 7 1 Enable real time counter e P rr m nc Ke ee Oe SER CE ee GES Mo Main loop P M H M 0 while 1 Confirm no key detection or display refresh if ucKeyEdgeInfo amp amp ucDispReq fn SetStandby Shift to standby Key sampling 24 Cycle of about 3 9 ms if RTC2IF RTC2IF 0 Clear INTRTC2 interrupt request flag Key detected if ucKeyEdgeInfo fn_KeySampling Perform key sampling at A Key processing There is a valid key input if ucKeyValidInfo ucKeyValidInfo 0 Clear valid key input notification Determine status switch ucMode Normal operation case MODE WATCH Determine key code switch ucKeyCode Key 1 case KEYCODE1 Shift to setting date and time ucMode MODE_TIMESETUP Specify year as setting item RO1ANO193EJ0100 Rev 1 00 Page 61 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode ucSetupTime SETUP TMYEAR Issue display refresh request ucDispReq 1 break Key 2 3 4 d
88. orts open so that they are handled as output ports When using the main clock oscillator and or subclock oscillator wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as V ss Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator 8 Connect an electric double layer capacitor 0 1 F to the RVpp pin so that supply of power to the RTC backup power supply RVpp can continue for a period if the supply voltage V pp is stopped NAM BR WN Remark For the resonator selection and oscillator constant customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation RO1ANO193EJ0100 Rev 1 00 Page 12 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 2 2 Devices Used Other Than Microcontroller The following shows devices other than the microcontroller used in this sample program 1 LCD module An LCD module character display 20 characters x 2 rows is used as the display device 2 Push keys KEY1 KEY2 KEY3 KEY4 Push keys are used fo
89. pplication of RVpp the values of the register at the time the reset was triggered are retained The parts written in red in the above figure are the values set by using this sample program RO1ANO193EJ0100 Rev 1 00 Page 43 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 3 Software coding example A section of the sample program is given below as an example of the software code for setting the RTC backup mode a Initial settings Make the following initial settings after a reset has occurred lt 1 gt Define the interrupt processing routine 2 Set RTCBUMCTLO RBMEN to 1 to enable use of the RTC backup mode If the system has entered the state in which it is preparing to enter RTC backup mode after reset is canceled exit this state here 3 Set SOSCAMCTL AMPHS to 0 to specify normal oscillation for the subclock fxr lt 4 gt Execute NOP lt 5 gt Specify use of the low voltage detector as an interrupt Set the low voltage detection level to 2 8 V lt 6 gt Specify the operation of the real time counter s fixed cycle interrupt Specify the subclock fxr as the operating clock T Enable the INTLVI interrupt lt 8 gt Enable the real time counter RO1ANO193EJ0100 Rev 1 00 Page 44 of 90 Sep 30 2010 ENESAS V850ES Jx3 L pragma interrupt INTLVI fn IntLvi static void fn InitRtcBum void asm push asm mov asm st p asm st p asm pop mami ste
90. ption is checked MINICUBE2 segments will be automatically added to this link directive file If the default installation path is selected the reference file will be C Program Files NEC Electronics Tools PM version used bin w_data V850_i dat Remark f Includes only source files Includes source files used by PM integrated development environment RO1ANO193EJ0100 Rev 1 00 Page 14 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 3 2 On Chip Peripherals Used This sample program uses the following on chip microcontroller peripherals Peripheral I O circuits Real time counter Used to trigger fixed cycle interrupts alarm interrupts and interval interrupts Also operates in RTC backup mode Low voltage detector Used to detect a low voltage and to check whether Vpp is 2 7 V or higher Pins KRO to KR3 Used for key input P70 Used for buzzer control P90 to P96 Used to control the LCD module 3 3 Initial Settings and Operation Overview This sample program is used to specify initial settings such as selecting the clock frequency stopping watchdog timer 2 the I O port and external interrupt pin settings the low voltage detector settings the real time counter settings the RTC backup mode settings and the LCD module settings Note that if the real time counter 1s already operating when specification of the initial settings starts specifying the real time counter s
91. r key operation 3 Electronic buzzer An electronic buzzer is used to output the alarm sound RO1ANO193EJ0100 Rev 1 00 Page 13 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 3 SOFTWARE This chapter describes the organization of the compressed files that are downloaded the on chip microcontroller peripherals used and the initial settings and operation of the sample program which are also shown in a flow chart 3 1 File Organization The compressed files that are downloaded are organized as follows File Name Tree Structure Description Compressed zip File dim crtE s Startup routine file AppNote RTC BUM dir Link directive file s la iP environment PM AppNote RTC BUM prw Workspace file for integrated development environment PM main c C source file containing code for microcontrollers v V hardyvare initialization processing and main processing C source file containing code for LCD module y V NHD 0220FZ FSW GBW P 3V3 control processing minicubezs si Notes 1 This is the startup file copied if Copy Sample C is selected for Specify Startup File when creating a new workspace If the default installation path is selected the file that is copied will be C Program Files NEC Electronics Tools CA850 version usedlib850 r32 crtE s 2 If Copy Sample C is selected for Specify Link Directive File when creating a new workspace and the Memory Usage Internal Memory Only 1 o
92. r10 Ty asm st b r10 PRCMD asm st b r10 RTCBUMCTLO Shift to standby fn SetStandby uni val osi nd Cub vul ou ud cud FU Fd Sud P Pa AAA AIA ses armes esr o o fag f If the voltage has risen from the low voltage detection level to the normal operating voltage level else Set the subclock to normal oscillation mode asm st b asm st b r ro PRCMD SOSCAMCTL Set the state in which the system is preparing to exit RTC backup mode asm push r10 asm mov 0x80 El 2 asm st b r10 PRCMD Mi asm st b r10 RTCBUMCTLO asm pop r10 yg NOP Disable all KRIF RTCOIF 11 RTCIMK Specify the PLLON 0 0 0 0 0 0 1 Clear the INTK Clear the INTR Clear the INTR Enable the INT Enable the INT Enable the INT normal clock as t interrupts used except INTLVI R interrupt request flag TCO interrupt request flag TC1 interrupt request flag KR interrupt RTCO interrupt 1 interrupt he operating clock Enable the PLL RO1AN0193EJ0100 Rev 1 00 Sep 30 2010 13 NE SAS Page 77 of 90 V850ES Jx3 L Real Time Counter RTC Backup Mode while LOCK NOP Wait for PLL operation to stabilize SELPLL
93. register Be sure to set as follows after applying RVpp Remarks 1 This register is reset to 00H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained 2 This register is set to an initial value of 04H in this sample program RO1AN0193EJ0100 Rev 1 00 Page 33 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 10 Month count register RCIMONTH The RCIMONTH register is an 8 bit register that takes a value of 1 to 12 decimal and indicates the count value of the month It counts up when the day counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks 2 x 32 768 kHz later Set a decimal value of 01 to 12 to this register in BCD code This register can be read or written in 8 bit units Caution Setting a value other than 01 to 12 to the RCIMONTH register is prohibited Remarks 1 This register is reset to 01H when the RVpp power supply is applied If a reset is triggered by a factor other than application of RVpp the values of the register at the time the reset was triggered are retained 2 This register is set to an initial value of 04H in this sample program Figure 4 1 10 Format of Month Count Register RC1MONTH Month count register RCIMONTH Address FFFFFAD7H 7 6 5 4 3 2 1 0 Eos px c pw po pops qp
94. rrupt request signals Esen Enable real time counter Cautions 1 R01ANO193EJ0100 Rev 1 00 Sep 30 2010 Page 45 of 90 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode b Settings when preparing to shift to RTC backup mode In the INTLVI interrupt processing routine check whether the voltage 1s low that is whether the LVIM LVIF bit is 1 N and then specify the following settings lt 1 gt Stop the PLL and specify the low voltage clock 5 MHz as the CPU clock lt 2 gt Disable DMAN 3 Disable all maskable interrupts except the NMI and INTLVI interrupts 4 Set SOSCAMCTL AMPHS to 1 to specify ultra low consumption oscillation for the subclock fxr 5 Set RTCBUMCTLO RBMSET to 1 to prepare to shift to RTC backup mode 67 Specify the normal stop mode If the supply of Vpp stops shift to RTC backup mode interrupt void fn IntLvi void if LVIF SELPLL en PLLON INTFO amp 0501111000 INTRO amp 0501111000 3 IMR3 0b1111111111111111 IMR2 0b1111111111111111 IMR1 0b1111111111111111 IMRO 0b1111111111111110 asm push r v E asm mov 1210 asm st b PRCMD asm st b SOSCAMCTL asm pop asm mov r10 nr asm st b PRCMD asm st b RTCBUMCTLO ee KOHK o Static void fn Setstandby void PSMR 0b0000001 asm pushr10 asm mov 0x02 KO asm st br10 PRCMD
95. spReq har ucKeyCode KEYCODEOFF KEYCODE1 KEYCODE2 KEYCODE3 KEYCODE4 KEYCODEMLT unsigned char ucKeyEdgelnfo unsigned char ucKeyValidInfo unsigned char ucBuzzerTimer BUZZER TIME define 3 har ucKeySamplingCounter KEY SAMPLINGCOUNT har ucCodeBuffer 3 0x00 0x01 0x02 0x03 0x04 Oxff Real Time Counter RTC Backup Mode Status classification Normal operation Setting date and time Setting alarm Post reset Display classification Watch display Post reset display Watch setting items No items Year Month Day Day of week Hour Minute Second Number of items Alarm setting items No items Alarm day of week Alarm hour Alarm minute Alarm second display False Off True on Timer for blinking display Switching interval n 0 5s Display refresh request False No request True Request Counter for key sampling Sampling count at 3 9 ms approx intervals Code buffer Key code DEE x Key 1 Key 2 Key 3 Key 4 I I More than one key pressed at the same time Key detection notification False No notification True Notification Valid key input notification False No notification True Notification Buzzer timer n 0 5 5 Buzzer output period KK RAT AAC AAC 2
96. supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Notice 1 All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website 2 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation o
97. t asm st b r10 0x80 r19 rig Ig 0 m r pe static void fn InitLvi void LVIMK LVIIF asm st b asm st b 20 LVIS 0500000000 r10 PRCMD RTCBUMCTLO PRCMD SOSCAMCTL PRCMD LVIM Real Time Counter RTC Backup Mode Low voltage detector interrupt processing ES Disable INTLVI interrupt Clear INTLVI interrupt request flag Specify use of low voltage detector as interrupt Set low voltage detection level to 2 8 V Enable low voltage detector 10 v 0x80 rro yg ale PRCMD 210 LVIM m 1 asm pop aeo d eS TG O static void fn UnitRte void f asm push asm mov asm s 5 asmi sth TSE o OF Stop real time counter 0b00000000 de Enable real time counter Gel 0600001001 Set count start time to 13 00 00 on April 1 2010 Thursday 02904 0x00 0x13 0x04 0x01 0x04 0x10 Enable INTLVI interrupt T le RTC backup control register 0 RTCBUMCTLO the subclock low power operation control register SOSCAMCTL and the low voltage detection register LVIM are special registers that can only be written in a specific sequence For details about special registers see the V850ES Jx3 L user s manual 2 For details about the low voltage detector see the V850ES Jx3 L user s manual EL Enable acknovledgment of inte
98. t time to 13 00 00 on April 1 2010 Thursday Enabling the alarm interrupt and setting the alarm time to 14 00 everyday Setting the interval operation to about 3 9 ms Enabling the INTRTCO and INTRTCI interrupts lt l gt Specify the interrupt handlers of the INTRTCO and INTRTC1 interrupt 2 Stop the real time counter by using bit 7 RCIPWR of the RCICCO register 3 Specify fxr as the real time counter operating clock by using bit 6 RCICKS of the RCICCO register lt 4 gt Enable the real time counter by using bit 7 RCIPWR of the RCICCO register 5 Specify the 24 hour format by using bit 3 AMPM of the RCICCI register Set the generation cycle of the fixed cycle interrupt INTRTCO to 0 5 seconds by using bits 0 to 2 CTO to CT2 of this register 6 Set the count start time to 13 00 00 on April 1 2010 Thursday by using the RCISEC RCIMIN RCIHOUR RCIWEEK RCIDAY RCIMONTH and RC YEAR registers T Disable alarm matching by using bit 7 WALE of the RCICC2 register 8 Set the alarm time to 14 00 on Friday by using the RCIALM RCIALH and RCIALW registers 9 Enable alarm matching by using bit 7 WALE of the RCICC2 register lt 10 gt Set the cycle of the interval interrupt INTRTC2 to about 3 9 ms by using bits 0 to 2 of the RC1CC3 register Enable the interval interrupt by using bit 7 RINTE of this register lt 11 gt Clear the INTRTCO interrupt request flag RTCOIF INTRTCI interrupt request flag
99. t timing not every time Table 4 2 DEV Bit Setting DEV Bit Value Timing of Applying Value to RC1SUBC 0 When RC1SEC is 00 20 or 40 seconds 1 When RC1SEC is 00 seconds Example when F6 to F0 bits are set to 0010101B Ifthe DEV bit is 0 The RCISUBC count value is 32 808 at 00 20 or 40 seconds Otherwise it is 32 768 e IF DEV bit is 1 The RCISUBC count value is 32 808 at 00 seconds Otherwise it is 32 768 As described above the RCISUBC count value is corrected every 20 seconds or 60 seconds instead of every second in order to match the RCISUBC count value with the deviation of the resonator The range in which the resonator frequency can be actually corrected is shown below e Ifthe DEV bit is 0 32 76180000 kHz to 32 77420000 kHz e Ifthe DEV bit is 1 32 76593333 kHz to 32 77006667 kHz The range in which the frequency can be corrected when the DEV bit is 0 is three times wider than when the DEV bit is 1 However the accuracy of setting the frequency when the DEV bit is 1 is three times that when the DEV bit is 0 Tables 4 3 and 4 4 show the setting values of the DEV and F6 to FO bits and the corresponding frequencies that can be corrected RO1ANO193EJ0100 Rev 1 00 Page 51 of 90 Sep 30 2010 RENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Table 4 3 Range of Frequencies That Can Be Corrected When DEV Bit 0 F6 F5 to FOIRCISUBC Correction Value Frequency of Connected Clock Including Stea
100. tion value is determined by using the RCISUBU F6 to RCISUBU FO bits The F6 bit is used to determine whether to increment or decrement RCISUBC and the F5 to FO bits are used to determine the RCISUBC value 1 Incrementing the RCISUBC count value The RCISUBC count value is incremented by the value set by using the F5 to FO bits by setting the F6 bit to 0 Expression for calculating the increment value F5 to FO bit value 1 x 2 Example of incrementing the RCISUBC count value F6 bit 0 If 15H 010101B is set to the F5 to FO bits 15H 1 x 2 40 increments the RCISUBC count value by 40 RCISUBC count value 32 768 40 32 808 2 Decrementing the RCISUBC count value The RCISUBC count value is decremented by an inverted value of the value set by using the F5 to FO bits by setting the F6 bit to 1 Expression for calculating the decrement value Inverted value of F5 to FO bit value 1 x 2 Example of decrementing the RCISUBC count value F6 bit 1 If 15H 010101B is set to the F5 to FO bits Inverted data of 15H 010101B 2AH 101010B 2AH 1 x 2 86 decrements the RCISUBC count value by 86 RCISUBC count value 32 768 86 32 682 RO1AN0193EJ0100 Rev 1 00 Page 50 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 3 DEV bit The DEV bit determines when the setting by the F6 to FO bits is enabled The value set by the F6 to F0 bits is applied to the RCISUBC count value at the nex
101. uage code see the following user s manual CA850 C Compiler Package for C Language 4 1 Setting the Real Time Counter In this sample program the real time counter is controlled by using the following registers Real time counter control register 0 RCICCO e Real time counter control register 1 RCICCI Real time counter control register 2 RC1CC2 Real time counter control register 3 RC1CC3 e Second count register RCISEC e Minute count register RCIMIN Hour count register RCIHOUR e Day count register RCIDAY Day of week count register RCIWEEK Month count register RCIMONTH Year count register RCI YEAR Watch error correction register RCISUBU Alarm minute setting register RCIALM Alarm hour setting register RCIALH e Alarm day of week setting register RCIALW RO1ANO193EJ0100 Rev 1 00 Page 24 of 90 Sep 30 2010 ENESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 1 Real time counter control register 0 RCICC The RC1CCO register selects the real time counter input clock This register can be read or written in 8 bit or 1 bit units Figure 4 1 1 Format of Real Time Counter Control Register 0 RC1CCO Real time counter control register 0 RC1CCO Address FFFFFADDH 7 6 5 4 3 2 1 0 LRCTPVVR rocks o o o o RC1PWR Real time counter operation control Stop real time counter operation 1 Enable real time counter operation RC1CKS
102. up mode On the other hand if the voltage rises again from the low voltage state to the normal operating voltage level the processing in lt 1 gt to 4 below is executed lt 1 gt The INTLVI interrupt is generated and the system exits stop mode Note that at this time acknowledgment of the INTLVI interrupt is held pending 2 The RETI instruction is issued to restore the system from low voltage interrupt processing 3 After the system is restored the pending INTLVI interrupt is acknowledged and low voltage interrupt processing is executed again 4 The processing branches to the processing when restoring from low voltage shown in the figure above and the system cancels the preparation to enter RTC backup mode RO1ANO193EJ0100 Rev 1 00 Page 23 of 90 Sep 30 2010 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode 4 SPECIFYING SETTINGS This chapter describes the settings to be specified for the real time counter RTC backup mode and watch error correction feature For details about the initial settings of the low voltage detector see the application note entitled V850ES Jx3 L Sample Program Low Voltage Detector LVI Reset Generation When Low Voltage Detected For details about other initial settings see the application note entitled V850ES Jx3 L Sample Program Initial Settings LED Lighting Switch Control For details about registers see the V850ES Jx3 L user s manual For the extended C lang
103. ween VIL MAX and VIH MIN 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device 3 PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar pre
104. xf0 554 10 ucNum amp x f Increment if lucerne 3 ucWork If the maximum value is exceeded if ucWork gt ucMax ucWork ucMin Set the minimum value Decrement else I the value is the minimum value if ucWork ucMin ucWork ucMax Set the maximum value Otherwise else ucWork Convert the calculation result to the BCD format ucWork ucWork 10 lt lt 4 ucWork 10 return ucWork Yxxxk kxkxkxkkkxkokkkkkkkkkkkikkkkkkkkkkkikkkikkkkkkkkkkkkkkkkkkkkkkkkkkkkkk ki oo k Title Processing to shift to standby KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKAKAAKAKAKAK Module static void fn SetStandby void Arg Ret Note This processing shifts the system to standby KKAKKKKAKKKAKKKAKKKAKKAKKKAKKKKKKAKKKAKKKKKKAKKKAKKKAKKKKKKAKKKKKKKKKKKKK f static void fn SetStandby void R01ANO193EJ0100 Rev 1 00 Sep 30 2010 Page 73 of 90 13 NESAS V850ES Jx3 L Real Time Counter RTC Backup Mode Standby mode used Normal stop mode PSMR 000000001 Shift to stop mode asm push r10 asm mov 0x02 rro 27 asm st b r10 PRCMD ys asm st b r10 PSC 2 asm pop r10 ms NOP NOP NOP NOP NOP d b b b 2 22 2 2 2 2 2 22 2 2 22 2 2 2 2 2 22 2 2 2 2 2 3 Title Watch error correction processing

V850ES/Jx3-L Real-Time Counter (RTC Backup Mode)

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