CDP1802 - Taylor Electronics Home
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1. CDP1802A CDP1802AC CDP1802BC Dynamic Electrical Specifications T 40 C to 85 C 50pF 5 Except as Noted Continued TEST CDP1802A CONDITIONS CDP1802AC CDP1802BC NOTE 1 NOTE 1 PARAMETER SYMBOL a V a V TYP TYP UNITS EF1 4 Set Up EFT Minimum Pulse Width Times CLEAR Pulse Width CLOCK Pulse Width NOTES 1 Typical values are for TA 259C and nominal Vpp 2 Maximum limits of minimum characteristics are the values above which all devices function Timing Specifications as a function of T T masmi at TA 40 to 85 C Except as Noted CDP1802A mem CONDITIONS CDP1802AC 1 1 5 SYMBOL Vcc V Vpp V UNITS High Order Memory Address Byte 2T 550 2T 400 2T 325 2T 275 SetUptoTPA X Time ves weis 1225 veis Low Order Memor Adress EE High Order Memory Address Byte Hold After TPA Time pe s s mm gt o e ee CPU Data to After WR Time 3 10 CDP1802A CDP1802AC CDP1802BC Timing Specifications as a function of T T 1 fcLock at Ta 40 to 85 C Except as Noted CDP1802A TEST CONDITIONS CDP1802AC 802 1 1 5 SYMBOL Vcc Vpp V UNITS ns Required Memory Access Time Ad 5T 375 5T 250 5T 225 5T 175 dress to2. M R P gt R P 0 ELSE R P 1 gt R P IF DF 1 M R P gt R P 0 ELSE R P 1 gt R P D 0 IF D SHORT BRANCH IF DF 1 SHORT BRANCH IF POS OR ZERO SHORT BRANCH IF EQUAL OR GREATER SHORT BRANCH IF DF 0 IF DF 0 M R P R P 0 ELSE R P 1 gt R P SHORT BRANCH IF MINUS SHORT BRANCH IF LESS SHORT BRANCH IF Q 1 SHORT BRANCH IF Q 0 UJ 00 2 2 UJ N Note 2 w 31 IF Q 1 M R P gt 0 ELSE R P 1 gt R P 39 0 M R P gt R P 0 ELSE R P 1 gt R P 3 24 CDP1802A CDP1802AC CDP1802BC TABLE 1 INSTRUCTION SUMMARY SEE NOTES Continued OP INSTRUCTION CODE SHORT BRANCH IF EF2 1 EF2 Vss IF EF2 1 M R P P 0 ELSE R P 1 gt R P SHORT BRANCH IF EF2 0 EF2 Vcc IF EF2 0 M R P P 0 ELSE R P 1 gt R P FER MRI RIS T AP P P P P P P P P SHORT BRANCH IF 0 EF3 IF 0 0 ELSE R P 1 gt R P 1 LONG M R P R P 1 R P 0 P 2 gt DELI NO LONG BRANCH See LSKP NLBR R P Note 2 LONG BRANCH IF D 0 LBZ C2 IFD 2 0 M R P gt R P 1 M R P 1 gt R P 0 ELSE R P 2 R P LONG BRANCH IF D NOT 0 LBNZ IF D Not 0 M R P R P 1 M R P 1 R P 0 ELSE LO
3. 1 4 MEMORY READ CYCLE lt MEMORY READ CYCLE _ NOTE 1 USER GENERATED SIGNAL AE DON T CARE OR INTERNAL DELAYS HIGH 1 STATE FIGURE 11 OUTPUT CYCLE TIMING WAVEFORMS 3 15 CDP1802A CDP1802AC CDP1802BC Machine Cycle Timing Waveforms Propagation Delays Not Shown Continued hs CYCLE 2 7777 MRD MWR AYI yY VALID OUTPUT DATA BUS PPP DATA FROM INPUT DEVICE NOTE 1 MEMORY READ CYCLE MEMORY READ WRITE i MEMORY WRITE CYCLE OR NON MEMORY CYCLE i NOTE 1 DON T CARE OR INTERNAL DELAYS HIGH IMPEDANCE STATE USER GENERATED SIGNAL FIGURE 12 DMA IN CYCLE TIMING WAVEFORMS MACHINE CYCLE CYCLE CYCLE 1 CYCLE n 2 INSTRUCTION FETCH 50 EXECUTE S1 DMA S2 SMOTE AN MRD MWR MEMORY OUTPUT DATA VALID OUTPUT VALID DATA FROM MEMORY STROBE 52 NOTE 1 I lt MEMORY READ CYCLE lt MEMORY READ WRITE lt MEMORY READ CYCLE gt OR NON MEMORY CYCLE NOTE 1 USER GENERATED SIGNAL OS DON T CARE OR INTERNAL DELAYS HIGH IMPEDANCE STATE FIGURE 13 DMA OUT CYCLE TIMING WAVEFORMS 3 16 CDP1802A CDP1802AC CDP1802BC Machine Cycle Timing Waveforms Propagation Delays Not Shown Continued MACHINE CYCLE CYCLE CYCLE 1 CYCLE
4. DF DF MSB D Note 2 D SHIFT LEFT SHL SHIFT D LEFT MSB D DF 0 gt LSB D SHIFT LEFT WITH CARRY SHLC SHIFT D LEFT MSB D gt DF DF LSB D Note 2 7E RSHL SHIFT D LEFT MSB D 2 DF DF LSB D Note 2 D D 1 gt R P D DF gt DF D D DF gt DF D R P 1 gt R P D DF D D gt DF D R P 1 gt R P D NOT DF gt DF D D Not DF gt DF D R P 1 gt R P RING SHIFT LEFT ARITHMETIC OPERATIONS Note 1 DD gt n A E 5 Z 21212 x 0 gt ADD WITH CARRY IMMEDIATE SUBTRACT D SUBTRACT D IMMEDIATE SUBTRACT D WITH BORROW SUBTRACT D WITH BORROW IMMEDIATE SUBTRACT MEMORY SUBTRACT MEMORY IMMEDIATE SUBTRACT MEMORY WITH BORROW SUBTRACT MEMORY WITH BORROW IMMEDI gt 2 93235235 E n gt l c m zl a lt lt m D 5 gt DF D R P 1 gt R P NOT DF DF D NOT DF DF D R P 1 R P P 52 rl gt SMBI Z R 4 2 2 2 2 gt ADD IMMEDIATE ADD WITH CARRY BRANCH INSTRUCTIONS SHORT BRANCH SHORT BRANCH NO SHORT BRANCH See SKP 0 M R P R P 0 38 R P 1 2 R P Note 2 32 0 M R P gt R P 0 ELSE R P 1 gt R P
5. 2 3 4 5 6 7 8 9 Vps DRAIN TO SOURCE VOLTAGE V Vps DRAIN TO SOURCE VOLTAGE V lt 5 9 z 5 a 5 a 2 OUTPUT HIGH SOURCE CURRENT mA FIGURE 19 CDP1802A AC MINIMUM OUTPUT LOW SINK FIGURE 20 CDP1802BC MINIMUM OUTPUT HIGH SOURCE CURRENT CHARACTERISTICS CURRENT CHARACTERISTICS 3 18 CDP1802A CDP1802AC CDP1802BC Performance Curves continued LT i GATE TO SOURCE 5V OUTPUT LOW SINK CURRENT mA 0 1 2 3 4 5 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 21 CDP1802BC MINIMUM OUTPUT LOW SINK CURRENT CHARACTERISTICS Atpy_ A PROPAGATION DELAY TIME ns 100 150 A LOAD CAPACITANCE pF NOTE ANY OUTPUT EXCEPT XTAL FIGURE 22 TYPICAL CHANGE IN PROPAGATION DELAY AS A FUNCTION OF A CHANGE IN LOAD CAPACITANCE FOR ALL TYPES 2E UE oa 0 2o 55 gt a 0 1 CLOCK INPUT FREQUENCY MHz NOTE IDLE 00 M 0000 BRANCH 3707 AT M 8107 CL 50 FIGURE 23 TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY FOR BRANCH INSTRUCTION AND IDLE INSTRUCTION FOR ALL TYPES Signal Descriptions Bus 0 to Bus 7 Data Bus 8 bit bidirectional DATA BUS lines These li
6. 1 R X 0 IE INPUT OUTPUT BYTE TRANSFER OUTPUT 1 R X gt BUS R X 1 2 R X N LINES 1 X OUTPUT 2 R X gt BUS R X 1 gt R X N LINES 2 OUTPUT 3 R X gt BUS R X 1 gt R X N LINES 3 OUTPUT 4 R X gt BUS R X 1 gt R X N LINES 4 5 OUT 5 BUS R X 1 2 R X N LINES 5 OUTPUT 6 OUT 6 M R X gt BUS R X 1 gt R X N LINES 6 BUS gt M R X BUS gt D N LINES 1 INPUT 1 INPUT 2 INPUT 3 INPUT 4 INPUT 5 INPUT 6 INPUT 7 3 26 CDP1802A CDP1802AC CDP1802BC TABLE 1 INSTRUCTION SUMMARY SEE NOTES Continued OP INSTRUCTION MNEMONIC CODE OPERATION NOTES For Table 1 1 The arithmetic operations and the shift instructions are the only instructions that can alter the DF After an add instruction DF 1 denotes a carry has occurred DF 0 Denotes has not occurred After a subtract instruction DF 1 denotes no borrow D is a true positive number DF 0 denotes a borrow D is two s complement The syntax not DF denotes the subtraction of the borrow 2 This instruction is associated with more than one mnemonic Each mnemonic is individually listed 3 idle instruction initiates a repeating S1 cycle The processor will continue to idle until an I O request INTERRUPT DMA IN or DMA OUT is activated When the request is acknowledg
7. 0 Lower order byte of R W R W 1 Higher order byte of R W Operation Notation M R N 2 D RIN 1 R N This notation means The memory byte pointed to by R N is 3 22 CDP1802A CDP1802AC CDP1802BC loaded into D and R N is incremented by 1 IDLE DMA INT NG FORCE S1 LONG BRANCH LONG SKIP NOP ETC INT DMA DMA IDLE INT PRIORITY FORCE 50 51 INT DMA OUT INT FIGURE 25 STATE TRANSITION DIAGRAM TABLE 1 INSTRUCTION SUMMARY SEE NOTES INSTRUCTION MNEMONIC CODE OPERATION MEMORY REFERENCE LOAD VIA N o M R N D N not 0 LOAD ADVANCE N M R N D R N 1 gt DADA ux m ques LOAD VIA X AND ADVANCE LDXA DAD MEDIE us m STORE VIAN D R X 1 R X LOGIC OPERATIONS 1 OR IMMEDIATE M R P OR D gt D R P 1 gt R P 3 23 CDP1802A CDP1802AC CDP1802BC TABLE 1 INSTRUCTION SUMMARY SEE NOTES Continued OP INSTRUCTION CODE OPERATION EXCLUSIVE OR M R X XOR D gt D EXCLUSIVE OR IMMEDIATE M R P XOR D gt D R P 1 gt R P HOH ANDDD AND IMMEDIATE M R P AND D 2 D R P 1 gt R P SHIFT RIGHT SHIFT D RIGHT LSB D gt DF 0 gt MSB D SHIFT RIGHT WITH CARRY SHRC 76 SHIFT D RIGHT LSB D DF DF MSB D Note 2 RING SHIFT RIGHT RSHR 76 SHIFT D RIGHT LSB D
8. 00 at M 0000 C 50pF Dynamic Electrical Specifications T 40 C to 85 C C 50pF Vpp 5 Except as Noted om CDP1802A om CDP1802AC CDP1802BC NOTE 1 NOTE 1 PARAMETER SYMBOL Vcc V Vpp V TYP TYP UNITS PROPAGATION DELAY TIMES Clock to Memory High Address Byte Clock to Memory Low Address Byte Valid Clock to MRD Clock to MRD Clock to MWR Clock to CPU DATA to BUS Valid CDP1802A CDP1802AC CDP1802BC Dynamic Electrical Specifications T 40 C to 85 C 50pF 5 Except as Noted Continued CDP1802A CDP1802AC CDP1802BC NOTE 1 NOTE 1 PARAMETER SYMBOL Vcc V TYP TYP UNITS Clock to State Code 5 5 0 Clock to 0 2 SET AND HOLD TIMES Data Bus Input Set Up E Data Bus Input Hold 2 Set Up i DMA Hold tH Note 2 Interrupt Set Up Interrupt 2 WAIT Set Up A are A 300 250 150 250 150 100 300 200 150 20 10 150 100 75 150 100 75 75 50 25 100 75 50 10 10 EE 5m GN EE UM Im CARE E ZR UN CORE SESE UN Oe ZEE UN MEM CER UM
9. VALID ALLOWABLE MEMORY ACCESS VALID OUTPUT OUTPUT OUTPUT SSS DON T CARE OR INTERNAL DELAYS yy HIGH IMPEDANCE STATE FIGURE 8 MEMORY READ CYCLE TIMING WAVEFORMS INSTRUCTION FETCH 50 EXECUTE S1 EXECUTE S1 FETCH 50 MEMORY READ CYCLE MEMORY READ CYCLE MEMORY READ CYCLE FL ff L eO T LNL MWR HIGH MEMORY output 1 12221 12221 1222 1 wn HH ALLOWABLE MEMORY ACCESS VALID OUTPUT vALID OUTPUT VALID OUTPUT SS DON T CARE OR INTERNAL DELAYS HIGH IMPEDANCE STATE FIGURE 9 LONG BRANCH OR LONG SKIP CYCLE TIMING WAVEFORMS 3 14 CDP1802A CDP1802AC CDP1802BC Machine Cycle Timing Waveforms Propagation Delays Not Shown Continued MACHINE CYCLE CYCLE n CYCLE n 1 INSTRUCTION FETCH 50 EXECUTE S1 MRD NO N2 MWR MEMORY output 1 ALLOWABLE MEMORY ACCESS VALID OUTPUT DATA woes PA FROMNPUTDEVICE NOTE 1 MEMORY READ CYCLE lt MEMORY WRITE CYCLE NOTE 1 USER GENERATED SIGNAL DON T CARE INTERNAL DELAYS HIGH IMPEDANCE STATE FIGURE 10 INPUT CYCLE TIMING WAVEFORMS MACHINE CYCLE CYCLE CYCLE n 1 INSTRUCTION FETCH 50 EXECUTE S1 NO N2 ______ qx ALLOWABLE MEMORY ACCESS VALID OUTPUT VALID DATA FROM MEMORY d DATA STROBE l MRD TPB N
10. or they may be decoded to connect to up to seven devices When the output instruction is executed the data is moved onto the bus from the memory position pointed to R X and R X is incremented The automatic incrementing of R X allows sequential data to be output quickly 1 The input works in much the same way as the output The instructions to perform output are 69 6F The lower three bits of these instructions are output on the N0 N1 and N2 lines in the same way as the output and like the output they can be decoded or connected directly to external devices The X register points to the R register which contains the address of where to output but unlike the output instructions the value in R X is not incremented after execution 1 There is a simple implementation of on the chip The 1802 has IN pin and pin The DMA pins act the same as interrupts When a signal is received on the pin a machine cycle is used by the CPU to perform the input or output 6 This cannot be defined as a true implementation of DMA because the CPU is involved in the data transfer but it is referredto as DMA If more than one signal is received DMA IN has priority over DMA OUT which has priority above the Interrupt line When the DMA IN signal is receive the data from the bus is moved into the address pointed to by R 0 and R 0 is incremented When the DMA Out signal is received by the CPU the byte in memory pointed to my
11. 10MQ typ Frequency trimming capacitors may be required at terminals 1 and 39 For addi tional information see Application Note AN6565 WAIT CLEAR 2 Control Lines Provide four control modes as listed in the following truth table Vpp Vss Power Levels The internal voltage supply Vpp is isolated from the Input Output voltage supply Vcc so that the processor may operate at maximum speed while interfacing with peripheral devices operating at lower voltage Vcc must be less than or equal Vpp All outputs swing from Vss to The recom mended input voltage swing is Vss to Vcc Architecture The CPU block diagram is shown in Figure 2 The principal feature of this system is a register array R consisting of six teen 16 bit scratchpad registers Individual registers in the array R are designated selected by a 4 bit binary code from one of the 4 bit registers labeled N P and X The con tents of any register can be directed to any one of the follow ing three paths 1 The external memory multiplexed higher order byte first on to 8 memory address lines The D register either of the two bytes can be gated to D The increment decrement circuit where it is increased or decreased by one and stored back in the selected 16 bit register 3 20 CDP1802A CDP1802AC CDP1802BC The three paths depending on the nature of the instruction may operate independently or in various combinations in the
12. CMOS 8 Bit Microprocessor Features For Use In Aerospace Military and Critical Industrial Equipment Minimum Instruction Fetch Execute Time of 4 5us Maximum Clock Frequency of 3 6MHz at 25 C Operation Over the Full Military Temperature Range to 125 C Any Combination of Standard RAM and ROM Up to 65 536 Bytes 8 Bit Parallel Organization With Bidirectional Data Bus and Multiplexed Address Bus 16 x 16 Matrix of Registers for Use as Multiple Pro gram Counters Data Pointers Data Registers On Chip DMA Interrupt and Flag Inputs High Noise Immunity Ordering Information TEMP RANGE PACKAGE c 3 2MHz SBDIP 55 to 125 CDP1802ACD3 D40 6 30 of Pinout Description The CDP1802A 3 High Reliability LSI CMOS 8 bit register oriented Central Processing Unit CPU is designed for use as a general purpose computing or control element in a wide range of stored program systems or products The CDP1802A 3 includes all of the circuits required for fetching interpreting and executing instructions which have been stored in standard types of memories Extensive input output I O control features are also provided to facili tate system design The 1800 Series Architecture is designed with emphasis on the total microcomputer system as an integral entity so that systems having maximum flexibility and minimum cost can be realized The 1800 Series CPU also provides a sy
13. Input Current any One Input vg 10mA Operating Temperature Range Ta Package Type D 55 C to 125 C Storage Temperature Range 65 C to 150 C Lead Temperature During Soldering At distance 1 16 1 32 In 1 59 0 79 from case for 10s max CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Recommended Operating Conditions Full Package Temperature Range For maximum reliability operating conditions should be selected so that operation is always within the following ranges Maximum Clock Input Rise or Fall Time Performance Specifications PARAMETER Vpp V 55 C TO 25 C 125 C UNITS Maximum Clock Input Frequency 5 DC 3 6 DC 2 7 MHz Load Capacitance 50pF NOTE 1 Equals 2 machine cycles one Fetch and one Execute operation for all instructions except Long Branch and Long Skip which require 3 machine cycles one Fetch and two Execute operations Static Electrical Specifications All Limits are 100 Tested CONDITIONS 55 C 25 C 125 C Vout PARAMETER V Vin V MAX UNITS Output Low Drive Sink Current Except XTAL lo Output High Drive Source Current Except XTAL CDP1802AC 3 Stat
14. designate a new register to be used as the program counter R P Indicate the value to be loaded into X to designate a new register to be used as data pointer R X The registers in R can be assigned by a programmer in three different ways as program counters as data pointers or as scratchpad locations data registers to hold two bytes of data Program Counters Any register can be the main program counter the address of the selected register is held in the P designator Other reg isters in R can be used as subroutine program counters By single instruction the contents of the P register can be changed to effect a to a subroutine When interrupts are being serviced register R 1 is used as the program counter for the user s interrupt servicing routine After reset and during DMA operation 0 is used as the program counter At all other times the register designated as gram counter is at the discretion of the user Data Pointers The registers in R may be used as data pointers to indicate a location in memory The register designated by X i e R X points to memory for the following instructions see Table 1 1 ALU operations F1 F5 F7 74 75 77 2 Output instructions 61 through 67 3 Input instructions 69 through 6F 4 Certain miscellaneous instructions 70 73 78 60 FO The register designated by N i e R N points to memory for the load D from memory instructions ON and 4N an
15. same machine cycle With two exceptions CPU instruction consists of two 8 clock pulse machine cycles The first cycle is the fetch cycle and the second and third if necessary are execute cycles During the fetch cycle the four bits in the P designator select one of the 16 registers R P as the current program counter The selected register R P contains the address of the mem ory location from which the instruction is to be fetched When the instruction is read out from the memory the higher order 4 bits of the instruction byte are loaded into the register and the lower order 4 bits into the N register The content of the program counter is automatically incremented by one so that R P is now pointing to the next byte in the memory The X designator selects one of the 16 registers R X to point to the memory for an operand or data in certain ALU or I O operations The N designator can perform the following five functions depending on the type of instruction fetched 1 Designate one of the 16 registers in R to be acted upon during register operations Indicate to the I O devices a command code or device selection code for peripherals Indicate the specific operation to be executed during the ALU instructions types of test to be performed during the Branch instruction or the specific operation required in a class of miscellaneous instructions 70 73 and 78 7B Indicate the value to be loaded into P to
16. with 16 bit addressing It was extremely simple and had the flexibility of a large register set The 1802 had a single accumulator register and a 16x16 register file 10 This versatile chip was the first microprocessor used in space and RCA produced videogames based on it The 1802 reached its peak of popularity in 1977 and at that time sold for a little less than 30 00 as stated by Popular Mechanics 11 The last commercial microcomputer produced with the 1802 was a 1983 machine named the Comx 35 By 1983 the 1802 was no longer cutting edge technology and the slow speed of the machine made it less efficient We will now look the 1802 microprocessor in more detail including its inner workings such as registers and instructions Architectural Classification The RCA 1802 has an extremely simple design is a textbook example of the Von Neumann architecture has a single bus for instructions and data and addresses a single memory The processor does not have temporal or spatial parallelism I performs instruction to completion before it fetches and executes the next instruction 1 The 1802 has many characteristics that would later be implemented in RISC processors It is not however a RISC chip The CPU has a relatively large set of 16 general purpose 16 bit registers The instruction set with only 91 instructions is very simple Despite these traits the 1802 cannot be classified as a RISC processor for several reasons The loa
17. 8 Sept 1976 pgs 37 40 Mar 1977 pgs 63 67 July 1977 pgs 41 46 12 Online Computing Dictionary http Awww instantweb com foldoc foldoc cgi RCA 1802 current Nov 2002 13 COSMAC ELF The 1802 s Place in Microcomputer History http homepage mac com ruske cosmacelf history1 htm current Nov 2002 14 The Antique Chip Collector s Page http www antiquetech com chips RCA1802 htm current Nov 2002 15 http groups yahoo com group cosmacelf message 138 current Nov 2002 16 User Manual for the RCA CDP1802 COSMAC Microprocessor No 1 Vol 1 RCA 1977
18. AM Pause Stops the internal CPU timing generator on the first negative high to low transition of the input clock The oscillator contin ues to operate but subsequent clock transitions are ignored Run May be initiated from the Pause or Reset mode functions If initiated from Pause the CPU resumes operation on the first negative high to low transition of the input clock When initi ated from the Reset operation the first machine cycle follow ing Reset is always the initialization cycle The initialization cycle 15 then followed by a DMA 52 cycle or fetch 50 from location 0000 in memory Run Mode State Transitions The CPU state transitions when in the RUN and RESET modes are shown in Figure 25 Each machine cycle requires the same period of time 8 clock pulses except the initializa tion cycle which requires 9 clock pulses The execution of an instruction requires either two or three machine cycles 50 followed by a single 51 cycle or two 51 cycles S2 is the response to a DMA request and S3 is the interrupt response Table 2 shows the conditions on Data Bus and Memory Address lines during all machine states Instruction Set The CPU instruction summary is given in Table 1 Hexadeci mal notation is used to refer to the 4 bit binary codes In all registers bits are numbered from the least significant bit LSB to the most significant bit MSB starting with 0 R W Register designated by W where W Nor X or P R W
19. ATA MEMORY STATE SYMBOL OPERATION BUS ADDRESS 5 X P gt T MR2 P gt X R2 1 R2 5 ES Float D 1 SDBI MRP D DFN gt DF D 1 Pe sur ma w 5 amp Fig 8 SMBI D MRP DEN gt DF D 1 ws mes HE EXC S12 C 3 Long Branch Taken MRP gt RP 1 Taken B gt RP 1 M RP 1 1 MRP 5 0 Not Taken 1 Not Taken 1 1 SU 2 2 5 Long Skip Taken RP 1 RP ar 2 1 1 1 51 1 Taken Operation 2 Not Taken Operation F 4 2 1 1 1 Ty my 1 4 co cO olol O F F F 1 1 Fig 9 Fig 9 5 D 1 5 Sx q N q RN TOUT Fig 6 d 5141 No Operation Operation Fig 6 Fig 8 1 ele Fig 8 DX OR MRXORD gt D 1 AND D gt D XOR MRX XOR D gt D ADD MRX D gt DF D En D gt DF D D gt DF D MCN 3 29 TABLE 2 CONDITIONS BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES Continued DATA MEMORY N STATE SYMBOL OPERATION BUS ADDRES
20. CO STATE CONTROL AND el CODES TIMING LOGIC Q LOGIC TPA TPB SYSTEM MWR TIMING TO INSTRUCTION MRD DECODE D als als ojo DI gt lt N N gt gt ER INCR DECR 8 BIT BIDIRECTIONAL DATA BUS mm mim olo P gt gt N1 COMMANDS gt 2 Figure 5 Internal Structure of the CDP1802 microprocessor The RCA 1802 Chip used 8 bit parallel organization with bi directional data bus and multiplexed address bus The 1800 series CPU utilizes a synchronous interface to memories and external controllers for devices The interface allowed support of devices operating in polled interrupt driven or direct memory access DMA modes The 1802 used to pins s 17 19 control lines 1 These lines can address up to 8 Input Output devices to I O or vice versa usually indicated by N3 internally 16 The INTERRUPT DMA IN and are 3 Requests that be sent on the bus The 8 bit data bus serves a dual function The data bus provides for not only external communication but also internal communication within the processor As Figure 5 shows the data bus is directly connected to the ALU and all of the registers except DF IE and A This provides the main source of communication within the processor Intermittent individual connections connect th
21. Data MRD to TPA x _ T 2 18 2 20 1 Typical values are for T4 25 C and nominal Timing Waveforms FETCH READ lt EXECUTE WRITE CLOCK 00401410411 1200121 0300310 401 419 50 51 160 61 70 71 00 101 1108 11 1201218301 31 40141050151 60061170471 00 ADDRESS HI BYTE LOW BYTE HI BYTE LOW BYTE VALID INPUT DATA VALID OUTPUT DATA FIGURE 3 BASIC DC TIMING WAVEFORM ONE INSTRUCTION CYCLE CDP1802A CDP1802AC CDP1802BC Timing Waveforms Continued 1 lt MEMORY ADDRESS MRD MEMORY READ CYCLE MWR MEMORY WRITE CYCLE DATA FROM CPU TO BUS N1 N2 VO EXECUTION t CYCLE Y LATCHED CPU amt _ DMA SAMPLED 51 S2 S3 I tsu M tH DMA I lt 4 REQUEST INTERRUPT 51 52 gt x tsu INTERRUPT FLAG LINES REQUEST SANPLED IN S1 lt tsu ANY NEGATIVE lt lt TRANSITION tw lt NOTES 1 This timing diagram is used to show signal relationships only and does not represent any specific machine cycle 2 All measurements are referenced to 50 point of the waveforms 3 Shaded areas indicate Don t Care or undefined state Multiple transitions may occur during this period FIGURE 4 TIMING WAVEFORM 3 12 CDP1802A CDP1802AC CDP1802BC Machine Cycle Timing Wa
22. NG BRANCH IF DF 1 LBDF IFDF 1 M R P gt 1 M R P 1 gt R P 0 ELSE R P 2 R P oR oR gt gt gt gt gt R R P 2 gt R P LONG BRANCH IF DF 0 LBNF IF DF 0 M R P gt R P 1 M R P 1 R P 0 ELSE R P 2 gt R P LONG BRANCH IF 1 LONG 0 LBNQ IF Q 0 M R P gt R P 1 M R P 1 gt R P 0 EISE R P 2 gt R P SKIP INSTRUCTIONS SHORT SKIP See NBR SKP 38 R P 1 gt R P Note 2 LONG SKIP See NLBR LSKP C8 R P 2 gt R P Note 2 LONG SKIP IF D NOT 0 IF D Not 0 R P 2 R P ELSE CONTINUE LONG SKIP IF DF 0 IF DF 0 R P 2 R P ELSE CONTINUE IF Q 1 M R P 2 R P 1 M R P 1 gt R P 0 ELSE R P 2 gt R P LONG SKIP IF Q 1 IF Q 1 R P 2 2 R P ELSE CONTINUE LONG SKIP IF Q 0 LSNQ IF Q 0 R P 2 ELSE CONTINUE LONG SKIP IF IE 1 LSIE IF IE 1 R P 2 2 R P ELSE CONTINUE CONTROL INSTRUCTIONS IDLE 00 WAIT FOR OR INTERRUPT M R 0 BUS Note 3 NO OPERATION CONTINUE SETX SETQ 3 25 CDP1802A CDP1802AC CDP1802BC TABLE 1 INSTRUCTION SUMMARY SEE NOTES Continued OP INSTRUCTION CODE OPERATION pom res PUSH X P STACK MARK X P T X P M R 2 THEN P X R 2 1 R 2 RETURN M R X 2 X P R X 1 gt R X 1 S IE DISABLE M R X X P R X
23. Pinouts 40 LEAD PDIP PACKAGE SUFFIX E 44 LEAD PLCC 40 LEAD SBDIP PACKAGE SUFFIX D PACKAGE TYPE Q TOP VIEW TOP VIEW XTAL DMA IN DMA OUT INTERRUPT MWR TPA TPB 7 5 4 2 EF2 EF3 EF4 CLEAR WAIT CLOCK 2 NC DMA OUT INTERRUPT o gt e gt A ADDRESS BUS CDP1852 INPUT PORT cs2 51 MRD CDP1802 CDP1824 8 BIT CPU 32 BYTE RAM CS1 CS2 PORT CLOCK FIGURE 1 TYPICAL CDP1802 SMALL MICROPROCESSOR SYSTEM 3 4 CDP1802A CDP1802AC CDP1802BC Block Diagram VO REQUESTS MEMORY ADDRESS LINES FLAGS n MA6 MA4 MA2 MAO EF DMA MA7 5 MA1 2 IN CLOCK XTAL Sco STATE SCI CODES CONTROL AND TIMING LOGIC QLOGIC TPA TPB SYSTEM MWR TIMING TO INSTRUCTION MRD DECODE REGISTER ARRAY R N E yo COMMANDS o E EI 8 BIT BIDIRECTIONAL DATA BUS FIGURE 2 3 5 CDP1802A CDP1802AC CDP1802BC Absolute Maximum Ratings Thermal Information DC Supply Voltage Range Vpp Thermal Resistance Typical Note 4 9C W C W All Voltages Referenced to Vss Terminal N A CDP1802A 0 5V to 11V 46 N A CDP1802AC CDP1802BC 0 5V to 7V Input Voltage Range All Inputs 0 5V to 0 5V Device Dissipation Per Output
24. R 0 is moved onto the data bus and R 0 is incremented 1 There are several chips in the 1800 series designed to support The 1852 is 8 bit input output port When the mode pin is set to 0 the port acts as an input When the mode pin is set to 1 the port acts as an output 7 The 1861 is a video output chip that uses the DMA OUT and INT lines to output a 64x128 bitmap image to an output screen 8 The 1871 is a support chip that senses input from a mechanical keyboard and outputs the appropriate code to the bus 9 Instruction Set The 1802 RCA processor has an instruction set consisting of 91 opcodes which are software compatible with 1801 instructions 59 opcodes The 91 single byte commands are grouped into five basic types register memory and logic arithmetic branch skip and control byte transfer instructions Most instructions require two machine cycles 5 The only exception to this are the long branch and long skip instructions which take 3 machine cycles 1 Each instruction is broken into 4 bit hex digits designated so that is the higher order digit and N is the lower order digit The word specifies the instruction type and N word either specifies which register is to be used or acts as a special code Register operation include instructions that count data between internal registers Memory refers to the commands that provide directions on how to load or store memory bytes Branching ope
25. S LINES NOTES F 8 _ 1 gt Fig 8 9 ORD D RP 1 MRP AND D gt D RP 1 MRP XOR D 2 D RP 1 gt C ADI MRP D gt DE D 1 gt SDI MRP D gt DF D 1 gt MRP gt DF D 1 gt MSB D gt DF 0 gt 1580 B D gt DF 0 2 LSB D Fig 6 6 RO 1 RO mm from ee 12 Device DMAOUT MRO BUS RO 1 RO 742 6 Fig 13 X P gt T 0 1 gt P Lm Fig 14 2 Ls o 5 1 IE 1 TPB suppressed state 1 BUS 0 for entire cycle Next state always S1 Wait for DMA or INTERRUPT Suppress TPA wait for DMA IN REQUEST has priority over OUT REQUEST See Timing Waveforms Figure 5 through Figure 14 for machine cycles Operating and Handling Considerations Handling Input Signals To prevent damage to the input protection circuit input signals should never be greater than Vpp nor All inputs and outputs of Intersil CMOS devices have net less than Input currents must not exceed 10mA even work for electrostatic protection during handling Operating Operating Voltage During operation near the maximum supply voltage limit care should be taken to avoid or suppress power supply turn on and turn off transi
26. Transistor DC Input Current any One Input Q NL 10 Full Package Temperature Range Operating Temperature Range TA Package Type D 559C to 125 C Package Type E and Q 409 to 85 Storage Temperature Range 659C to 150 Lead Temperature During Soldering At distance 1 16 1 32 In 1 59 0 79mm from case for 10s max Lead Tips Only CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Recommended Operating Conditions T 40 C to 85 C For maximum reliability operating conditions should be selected so that operation is always within the following ranges Vpp PARAMETER Operating Voltage Range Maximum Clock Input Rise 4 to 6 5 4 to 6 5 Fall Time 4 to 10 5 4 to 10 5 Minimum Instruction Time Note 3 us Maximum DMA Transfer Rate KBytes s Maximum Clock Input Frequency Load Capacitance 50pF 0 0 5 Printed circuit board mount 57 x 57 minimum area x 1 thick 210 epoxy glass equivalent must never exceed Vpp Equals 2 machine cycles one Fetch and one Execute operation for all instructions except Long Branch and Long Sk
27. URE 5 MINIMUM OUTPUT HIGH SOURCE CURRENT CHARACTERISTICS OUTPUT HIGH SOURCE CURRENT AMBIENT TEMPERATURE Ta TYPICAL POWER DISSIPATION Pp mW 5 CLOCK INPUT FREQUENCY MHz 6 Idle 00 at M 0000 7 Branch 3707 at M 8107 FIGURE 7 TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY FOR BRANCH INSTRUCTION AND IDLE INSTRUCTION CDP1802AC 3 Performance Curves continued 150 AMBIENT TEMPERATURE 125 Ta 25 C 100 A PROPAGATION DELAY TIME AtpHL ns A LOAD CAPACITANCE pF NOTE Any output except XTAL FIGURE 8 TYPICAL CHANGE IN PROPAGATION DELAY AS A FUNCTION OF A CHANGE IN LOAD CAPACITANCE Burn In Circuit i lt lt o S H 2 3 4 5 6 8 9 10 11 12 13 14 15 16 18 19 20 Dp ALL RESISTORS ARE 47kQ 20 CDP1802AC 125 C 160 Hours FIGURE 9 BIAS STATIC BURN IN CIRCUIT All Intersil U S products are manufactured assembled and tested utilizing 1309000 quality systems Intersil Corporation s quality certifications be viewed at www intersil com design quality Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or s
28. US AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES DATA MEMORY STATE SYMBOL OPERATION BUS ADDRESS tines NOTES a RESET 0 5 N Q X 1 E XXXX Initialize Not Programmer 0000 XXXX Accessible so MRP 1 1 maraisi dr sense EY RN 1298RN 1 gt 6 6 ara 0 hort Branch Taken MRP RP O Fig 8 4 MRN D RN 1 ORN Fes ur eee eee Pe ane ours 7 7 Fig 11 3 e 7 E X P RX 1 1 gt X RX 1 gt RX 0 L2 ue esce pm epo C fer 3 roe es usco ooo s sme mes m ew uw s s s s ow T e To A ez e es e we o we 7 Fe 7 Fig 10 3 28 CDP1802A CDP1802AC CDP1802BC TABLE 2 CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES Continued D
29. a LT rei Digi rs CDP1802 Control Modes The WAIT and CLEAR lines provide four control modes as listed in the following truth table cuam The function the modes are defined as follows Load Holds the CPU in the IDLE execution state and allows an I O device to load the memory without the need for a bootstrap loader It modifies the IDLE condition so that DMA IN opera tion does not force execution of the next instruction Reset Registers are reset IE is set and 0 s VSS are placed on the data bus TPA and TPB are suppressed while reset is held and the CPU is placed in S1 The first machine cycle after ter mination of reset is an initialization cycle which requires 9 clock pulses During this cycle the CPU remains in S1 and register X P and R 0 are reset Interrupt and DMA servicing are sup pressed during the initialization cycle The next cycle is an SO 1 or an S2 but never an S3 With the use of a 71 instruction followed by 00 at memory locations 0000 and 0001 this feature may be used to reset IE so as to preclude interrupts until ready for them Power up reset can be realized by connecting an RC network directly to the CLEAR pin since it has a Schmitt trig gered input see Figure 24 CDP1802 THE RC TIME CONSTANT SHOULD BE GREATER THAN THE OSCILLATOR START UP TIME TYPICALLY 20ms FIGURE 24 RESET DIAGR
30. byte position of the current program counter This effects a branch within the current 256 byte page of the memory i e the page which holds the branching address If the tested condition is not met the branching address byte is skipped over and the next instruction in sequence is fetched and executed This same action is taken in the case of unconditional no branch NBR 6 The skip instructions are one byte long There is one Unconditional Short Skip SKP and eight Long Skip instructions The Unconditional Short Skip instruction takes 2 cycles to complete 1 fetch 1 execute Its action is to skip over the byte following it Then the next instruction in sequence is fetched and executed This SKP instruction is identical to the unconditional no branch instruc tion NBR except that the skipped over byte is not considered part of the program The Long Skip instructions take three cycles to complete 1 fetch 2 execute They can Skip unconditionally Testfor 0or Dz 0 Test for DF 0 or DF 1 Test forQ O0orQ 1 Test for IE 1 If the tested condition is met then Long Skip takes place the current program counter is incremented twice Thus two bytes are skipped over and the next instruction in sequence is fetched and executed If the tested condition is not met then no action is taken Execution is continued by fetching the next instruction in sequence 3 27 CDP1802A CDP1802AC CDP1802BC TABLE 2 CONDITIONS ON DATA B
31. d store trait of RISC is not present Many of the instructions such as ADI access memory directly 1 The instruction size is not the same for all instructions Most instructions are one byte but any instruction that includes data is two bytes and any instruction that contains an address is three bytes The 1802 is unable to perform any instructions in a single clock cycle In fact most instructions took two machine cycles of eight clock pulses to perform their intended task and in some cases the instruction took three machine cycles 6 Intended Applications The 1802 was designed for use as general purpose computing or control elements in a wide range of stored program systems or products It was designed with emphasis on maximum flexibility and minimum cost thus this chip was used ina wide range of devices The 1802 was the first microprocessor in space via the Defense Meteorological Satellite Program 5D 1 spacecraft launched 1976 It was also included on the following spacecrafts OSCAR satellite Ug SAT 1 U SAT 2 Voyager Viking and Galileo 1 One reason for its space use was that the 1802 was fabricated on sapphire which leads to radiation and static resistance ideal for space travel 12 This versatile chip was also used in Chrysler electronic ignitions RCA and Radio Shack video games RCA video terminals and 660 computers 14 Swiss payphone manufacturer Sodeco Sia used it for phones in France Austria and t
32. d the Store D instruction 5N The register designated by P i e the program counter is used as the data pointer for ALU instructions F8 FD FF 7C 7D 7F During these instruction executions the operation is referred to as data immediate Another important use of R as a data pointer supports the built in Direct Memory Access DMA function When DMA In or DMA Out request is received one machine cycle is stolen This operation occurs at the end of the execute machine cycle in the current instruction Register R 0 is always used as the data pointer during the DMA operation The data is read from DMA Out or written into DMA In the memory location pointed to by the R 0 register At the end of the transfer R 0 is incremented by one so that the cessor is ready to act upon the next DMA byte transfer request This feature in the 1800 series architecture saves a substantial amount of logic when fast exchanges of blocks of data are required such as with magnetic discs or during CRT display refresh cycles Data Registers When registers in R are used to store bytes of data four instructions are provided which allow D to receive from or write into either the higher order or lower order byte portions of the register designated by N By this mechanism together with loading by data immediate program pointer and data pointer designations are initialized Also this technique allows scratchpad registers in R to be used to h
33. during the interval between the leading edge of TPB and the leading edge of TPA Interrupt Action X and P are stored in T after executing current instruction designator X is set to 2 designator P is set to 1 interrupt enable is reset to 0 inhibit and instruction execution is resumed The interrupt action requires one machine cycle S3 DMA Action Finish executing current instruction 0 points to memory area for data transfer data is loaded into or read out of memory and increment R 0 NOTE In the event of concurrent DMA and Interrupt requests DMA IN has priority followed by DMA OUT and then Interrupt SCO 5 1 2 State Code Lines These outputs indicate that the CPU is 1 fetching an instruction or 2 executing an instruction or 3 processing a DMA request or 4 acknowledging an interrupt request The levels of state code are tabulated below All states are valid at H Vcc L Vss STATE CODE LINES STATE TYPE SC1 SC0 TPA TPB 2 Timing Pulses Positive pulses that occur once in each machine cycle TPB follows They are used by controllers to interpret codes and to time interaction with the data bus The trailing edge of TPA is used by the memory system to latch the higher order byte of the 16 bit memory address TPA is sup pressed in IDLE when the CPU is in the load mode to 7 8 Memory Address Lines In each cycle the higher order byte of a 16 bit CPU memory addres
34. e control logic to the functional units of the processor Note The following figures are given for operation at 10 V The maximum data transfer rate for the data bus occurs during DMA transfers This rate is 800 KB sec The bus does include some minimum set up and hold times which are as follows data bus set up 40 ns data bus Input Hold 100 ns 1 Expandability is a feature For a cost of 20 the 1802 could interface with RCA s 1861 PIXIE graphics chip using its interrupt line and one of the four external flag input lines This graphics capability utilized the DMA feature of the 1802 13 Attaching cascading CD4515 s to the data bus permitted a large number of I O lines to be handled well over 128 17 The potential large number of I O lines allowed for a wide range of I O devices including cassette interface audio circuitry monitors keyboards and even joystick 13 Performing I O The RCA 1802 performs through an 8 bit data bus connecting the registers ALU and external bus To output a memory address the 4 bit X register is given a value which points to one of the sixteen R registers which contains the memory address The output instructions are 61 67 The lower three bits of the instruction are used to choose one of seven possible devices This value is output on the lines NO N1 and N2 The lines may be connected directly to an external device and output only for the instructions 61 62 and 64
35. e registers Figure 5 shows the general organization of the registers in the CPU The following is a description of the registers and their purpose R 0x0 R OxF The general purpose registers are all 16 bit registers R 3 designates the register selected by the binary code 0011 They can also be accessed as 32 eight bit registers R 3 0 refers to the low order byte of R 3 R 3 1 refers to the high order byte of R 3 These registers have wide variety of uses One of them will be pointed to by the P register to become the program counter Another may be pointed to by the X register to be a data pointer In each case the register will hold the address of a location in memory The N register may also point to one of these registers to be used in an instruction The registers can also hold data that can be sent along to data bus to the D register to be used by the ALU One of the registers can also be used as a counter by being sent through the incrementer attached to the A register The 1802 does not have a stack pointer but clever use of one the general purpose registers can allow the user to implement a stack 16 A The A register is a 16 bit register It is a temporary storage register that is connected to the general registers and the incrementer decrementer holds data from one of the general registers It can then send it through the incrementer decrementer to be operated upon Then it can either put the data back into a re
36. ed the idle cycle is terminated and the I O request is serviced and then normal operation is resumed Long Branch Long Skip and No Op instructions require three cycles to complete 1 fetch 2 execute Long Branch instructions are three bytes long The first byte specifies the condition to be tested and the second and third byte the branching address The long branch instructions can Branch unconditionally Test D 0or D z 0 Test for DF 0 or DF 1 Test forQ O0orQ 1 e Effect an unconditional no branch If the tested condition is met then branching takes place the branching address bytes are loaded in the high and low order bytes of the current program counter respectively This operation effects a branch to any memory location If the tested condition is not met the branching address bytes are skipped over and the next instruction in sequence is fetched and exe cuted This operation is taken for the case of unconditional no branch NLBR 5 The short branch instructions are two bytes long The first byte specifies the condition to be tested and the second specifies the branching address The short branch instruction can Branch unconditionally Test OorD 0 Test for DF 0 or DF 1 Test 1 Test the status 1 or 0 of the four EF flags Effect an unconditional no branch If the tested condition is met then branching takes place the branching address byte is loaded into the low order
37. ents power supply rip ple or ground noise any of these conditions must not cause Vpp Vss to exceed the absolute maximum rating when the power supply is off Unused Inputs A connection must be provided at every input terminal All unused input terminals must be connected to either Vpp or Vss whichever is appropriate Output Short Circuits Shorting of outputs to or Vss may damage CMOS devices by exceeding the maximum device dissipation All Intersil U S products are manufactured assembled and tested utilizing ISO9000 quality systems Intersil Corporation s quality certifications can be viewed at www intersil com design quality Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com 3 30 imtersil CDP1802AC 3 March 1997 High Reliability
38. ext available instruction Finally if the ret instruction was used then a 1 is placed in the IE register to enable interrupts If the dis instruction was used then 0 is placed in the IE register to disable interrupts device caused the interrupt then the to EF4 flags are used in conjunction with the interrupt pin to determine the priority level of the interrupt Once the priority level has been determined the CPU loads the address of the handler into R 1 and executes these instructions Before the completion of the routine the values of X and P are restored 1 Memory System The memory system of the CDP1802 is divided into three different components RAM ROM and an optional PROM The general layout of a CDP1802 system is given in the following diagram 1 ADDRESS BUS CDP1852 INPUT PORT cs2 51 MRD CDP1802 CDP1824 8 BIT CPU 32 BYTE RAM DATA CS1 CDP1852 cs2 OUTPUT PORT CLOCK FIGURE 6 TYPICAL CDP1802 SMALL MICROPROCESSOR SYSTEM As bee seen from this diagram there exits single multiplexed address bus that feeds into each memory component This address bus consists of sub buses labeled 7 There is also a bi directional data bus that runs from each memory chip to each I O device and the 8 bit 1802 CPU 1 In addition unlike the 1804 and 1806 microprocessors the 1802 does not come bundled with the RAM and ROM on the microprocessor chip Rather each component must be purc
39. gister or send it to the data bus The A register is instrumental in the implementation of a stack The address held in the general register that is being used as the stack pointer can be sent to the A register to be decremented for a stack push or incremented for a stack pop The new address would then be stored back in the original general register 1 lo The D register is the accumulator It is one byte or eight bits in length The D register holds all data to be manipulated by the ALU 16 P The P register is a four bit register that contains the address of one of the general purpose registers Four bits are all that is needed to address 16 individual registers or memory addresses The register pointed to by the P register becomes the program counter The program counter holds the address of the next instruction to be executed in RAM 6 X The X register is a four bit register that contains the address of one of the general purpose registers The register pointed to by the X register becomes a data pointer The register holds the address of data that can be used in some ALU operations input operations output operations and miscellaneous operations 1 The T register is an eight bit register I is used to temporarily hold the values of the X and P register when an interrupt occurs If the processor is currently executing an instruction when an interrupt occurs the instruction completes execution before X and P are loaded
40. hased and installed separately 1 Since the 1802 decodes the high order address bits to select between memory chips it uses a high order memory interleaving scheme 1 RAM The 1802 s RAM takes the form of a CDP1824 chip s The 1824 is a 32 word by 8 bit fully static CMOS random access memory The time it takes to access RAM is about 320ns There are three signals that are associated with the 1824 MRD MWR and CS 1 The CS signal acts as a chip select and is present for memory expansions and MWR signals indicate whether a memory read or write has been requested 2 A 1802 memory address consists of 16 bits During the memory R W cycle the high order bytes are placed on the address bus first there are more than one random access memory chip installed the upper two bits are used for the chip selection otherwise they are not used The remaining high order bits are latched via the TPA clock timing pulse However if all the 8 high order bits are latched then 64K of memory can be obtained Following the completion of the TPA timing pulse the lower order bytes appear on the address bus 1 The lower five low order address bits are then used as the address within the selected chip 2 ROM ROM can be implemented in a variety of ways One of the most common ways is indicated in the below figure 3 CDM5354 Figure 7 Typical CDP1802 ROM Layout A 1883 latch decoder is used to select be
41. hird world countries where its low power allowed the unit to work entirely from the power of the phone line 13 In August amp September of 1976 and also March amp July of 1977 Popular Mechanics ran a series of articles written by Joseph Weisbeckes on how to build a hobbyist computer Mr Weisbeckes called this computer the COSMAC ELF 17 Figure 1 1802 Pin Layout Pinouts 40 LEAD PDIP PACKAGE SUFFIX E 44 LEAD PLCC 40 LEAD SBDIP PACKAGE SUFFIX D PACKAGE TYPE Q TOP VIEW TOP VIEW 7 WAIT z gt 5 c 5 SC1 Voo XTAL DMA OUT INTERRUPT gt CLEAR 9 w CLOCK NC gt gt gt gt N gt 7 Te m 7 BUS 7 9 MAG BUS 6 5 BUS 5 MA4 BUS 4 7 MA2 BUS 3 1 MA1 BUS 2 BUS 1 BUS 0 Due to its age any specific information concerning the inner workings of the RCA 1802 s control unit is very hard to find the information accumulated points to a simple non pipelined hardwired control unit A single machine cycle consists of eight pulses of the clock following is discussion of the communication lines entering and leaving the control unit 1 The control unit has two state code lines SCO and SC1 which provide information on its current activity Figure 2 provides a state table of their outputs and what they represen
42. ic Electrical Specifications All Limits are 100 Tested Continued CONDITIONS EIE 25 C 125 C Se d PARAMETER V Vin V V UNITS NN Leakage Current Input Three State Output Leakage Current IOUT NOTE 2 5V level characteristics apply to Part No CDP1802AC 3 and 5V and 10V level characteristics apply to part No CDP1802A 3 Timing Specifications As a Function of T T 1 CLOCK 50 pF LIMITS NOTE 3 PARAMETER Vpp V 559 25 C 1259 UNITS ome _ me ee o NOTE 3 These limits are not directly tested Implicit Specifications Note 4 TA 559C to 259C TYPICAL PARAMETER SYMBOL Vpp V VALUES UNITS Typical Total Power Dissipation f 2MHz mW Idle 00 at 0000 50pF NOTE 4 These specifications are not tested Typical values are provided for guidance only CDP1802AC 3 Dynamic Electrical Specifications C 50pF Timing Measurement at 0 5 Vpp Point PARAMETERS Progagation Delay Times Clock to TPA TPB Clock to Memory High Address Byte Clock to Memory Low Address Byte Valid 5 Clock to MRD Clock to MWR Clock to CPU DATA to BUS Valid Clock to State Code Clock to tpi n Clock to 0 2 tpi n Interface Timing Requireme
43. imtersil March 1997 Features Maximum Input Clock Maximum Frequency Options At Vpp 5V CDP1802A AC 3 2MHz CDP1802BC 5 0MHz Maximum Input Clock Maximum Frequency Options At Vpp 10V CDP1802A AC 6 4MHz Minimum Instruction Fetch Execute Times At Vpp 5V CDP1802A AC CDP1802BC Any Combination of Standard RAM and ROM Up to 65 536 Bytes 8 Bit Parallel Organization With Bidirectional Data Bus and Multiplexed Address Bus 16 x 16 Matrix of Registers for Use as Multiple Program Counters Data Pointers or Data Registers On Chip DMA Interrupt and Flag Inputs Programmable Single Bit Output Port 91 Easy to Use Instructions Ordering Information PART NUMBER 5V 3 2MHz 5V 2 TEMPERATURE RANGE PACKAGE CDP1802ACE CDP1802BCE CDP1802ACEX CDP1802BCEX 40 C to 85 C CDP1802A CDP1802AC CDP1802BC CMOS 8 Bit Microprocessors Description The CDP1802 family of CMOS microprocessors are 8 bit register oriented central processing units CPUs designed for use as general purpose computing or control elements in a wide range of stored program systems or products The CDP1802 types include all of the circuits required for fetching interpreting and executing instructions which have been stored in standard types of memories Extensive input output I O control features are also provided to facili tate system desig
44. into T After the interrupt is handled X and P are restored 1 LN The registers are both four bits in length They are used together as makeshift Instruction Register The N register holds the low order bits of the instruction These bits either point to a general purpose register or act as a special code The register holds the high order bits of the instruction These bits designate the type of instruction 16 DF register is a single bit register Technically it is named the Data Flag but it operates similarly to a carry flag It contains the carry out of an ALU operation 6 The IE register is a single bit register It is the Interrupt Enable flag If it is one then the processor accepts interrupts the flag is zero the processor denies interrupts 6 Internal Structure See Bus Structure Functional Unit The functional unit of the RCA 1802 consists of a single eight bit ALU The ALU performs arithmetic and logical operations on data It receives one operand from the D register and the other operand from the data bus The result of the operation is placed in the D register If there is carry a one is placed in the DF register Otherwise the DF register remains zero 16 REQUESTS MEMORY ADDRESS LINES IO FLAGS DMA CONTROL OUT A MA6 4 2 EF1 EF3 DMA CLEAR MA7 5 MA1 2 EF4 IN INT WAIT MUX CLOCK Bus Structure XTAL S
45. ip which require 3 machine cycles one Fetch and two Execute operations 9jA is measured with component mounted on an evaluation board in free air CDP1802A CDP1802AC CDP1802BC Static Electrical Specifications at omy 40 C to 85 C Except as Noted PARAMETER Quiescent Device Current Output Low Drive Sink Current Except XTAL Output High Drive Source Current Except XTAL Output Voltage Low Level Output Voltage High Level Input Low Voltage Input High Voltage CLEAR Input Voltage Schmitt Hysteresis Input Leakage Current Three State Output Leakage Current Operating Current CDP1802A AC at f 3 2MHz CDP1802BC at f 5 0MHz Minimum Data Retention Voltage Data Retention Current pm CONDITIONS CDP1802A Eos Vour SYMBOL V a x oa a CDP1802AC CDP1802BC 1 1 gt gt 3 gt 3 gt gt 0 55 gt 3 gt E F gt CDP1802A CDP1802AC CDP1802BC Static Electrical Specifications at poem 40 C to 85 C Except as Noted Continued CDP1802AC pu CONDITIONS CDP1802A CDP1802BC XS Vour Vim NOTE 1 1 SYMBOL V a TYP UNITS EO T EE ES 5 1 Typical values for TA 25 C and nominal Vpp 2 Idle
46. n The 1800 series architecture is designed with emphasis on the total microcomputer system as an integral entity so that systems having maximum flexibility and minimum cost can be realized The 1800 series CPU also provides a synchro nous interface to memories and external controllers for I O devices and minimizes the cost of interface controllers Fur ther the I O interface is capable of supporting devices oper ating in polled interrupt driven or direct memory access modes The CDP1802A and CDP1802AC have a maximum input clock frequency of 3 2MHz at 5V The CDP1802A and CDP1802AC are functionally identical They differ in that the CDP1802A has a recommended operating voltage range of 4 to 10 5V and the CDP1802AC a recommended operat ing voltage range of 4V to 6 5V The CDP1802BC is a higher speed version of the CDP1802AC having a maximum input clock frequency of 5 0MHz at 5V and a recommended operating voltage range of 4V to 6 5V PDIP 406 6 Burn In LM CDP1802ACQ CDP1802BCQ CDP1802ACDX CDP1802BCDX 409 to 85 PLCC N44 65 409C to 85 SBDIP D40 6 Burn In D40 6 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 321 724 7143 Intersil and design is a trademark of Intersil Americas Inc Copyright Intersil Americas Inc 2002 All Rights Reserved 3 3 1305 2 File Number CDP1802A CDP1802AC CDP1802BC
47. n 2 INSTRUCTION FETCH 50 EXECUTE S1 INTERRUPT S3 MRD MWR KI gt OUTPUT MEMORY READ WRITE MEMORY READ CYCLE NON MEMORY NON MEMORY CYCLE NOTE 1 USER GENERATED SIGNAL DON T CARE INTERNAL DELAYS HIGH IMPEDANCE STATE FIGURE 14 INTERRUPT CYCLE TIMING WAVEFORMS Performance Curves 1 1 1 1 1 1 LOAD CAPACITANCE 50pF SYSTEM MAXIMUM CLOCK FREQUENCY MHz SYSTEM MAXIMUM CLOCK FREQUENCY MHz 35 45 55 65 75 85 95 105 115 125 TA AMBIENT TEMPERATURE C 45 55 65 75 85 95 105 115 125 AMBIENT TEMPERATURE C FIGURE 15 CDP1802A AC TYPICAL MAXIMUM CLOCK FIGURE 16 CDP1802BC TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF TEMPERATURE FREQUENCY AS A FUNCTION OF TEMPERATURE 3 17 CDP1802A CDP1802AC CDP1802BC Performance Curves continued Vps DRAIN TO SOURCE VOLTAGE V 83 7 6 5 4 TRANSITION TIME ns 50 75 100 125 150 175 200 AMBIENT TEMPERATURE 40 C TO 85 CL LOAD CAPACITANCE pF OUTPUT HIGH SOURCE CURRENT FIGURE 17 TYPICAL TRANSITION TIME vs LOAD CAPACI FIGURE 18 CDP1802A AC MINIMUM OUTPUT HIGH SOURCE TANCE FOR ALL TYPES CURRENT CHARACTERISTICS 252421 Vas GATE TO SOURCE 10V F I ATIT ERR E DER
48. nation of the TPA 1 The Q flip flop is a single bit output from the control unit that can be set or reset by a program It can then be checked to see if a conditional branch is to be taken by the system 1 The XTAL output is to be used in conjunction with an external clock crystal if the on board oscillator is used It is used with the clock input terminal 1 There are two control lines CLEAR and WAIT that lead into the control unit Figure 4 provides a state table for these inputs and the functions they execute 1 Figure 4 Control Line State Table There are three input lines that lead into the control unit that concern requests IN OUT INT line signals an interrupt The DMA IN and DMA OUT lines signal that DMA action is requested 1 There are four flags attached to the control unit EF1 EF4 These flags are used by the controllers to transfer status information to the control unit They can also be used along with the interrupt line to establish a priority system among the interrupts They can also be used by the I O devices to alert the control unit that they need attention The flags are sampled at the beginning of the S1 cycle 1 The N and registers are connected to the instruction logic of the control unit 1 CPU Registers Registers The key feature of the RCA 1802 was its large register set The 1802 had 16 sixteen bit general purpos
49. nchronous interface to memories and external controllers for I O devices and minimizes the cost of interface controllers Further the interface is capable of supporting devices operating in polled interrupt driven or direct memory access modes The CDP1802AC 3 is functionally identical to its predeces sor the CDP1802 The A version includes some perfor mance enhancements and can be used as a direct replacement in systems using the CDP1802 This type is supplied in 40 lead dual in line sidebrazed ceramic packages D suffix CDP1802AC 3 SBDIP TOP VIEW 36 INTERRUPT CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 321 724 7143 Intersil and design is a trademark of Intersil Americas Inc Copyright Intersil Americas Inc 2002 All Rights Reserved 1 1441 2 File Number CDP1802AC 3 ADDRESS BUS CDP1852 INPUT PORT 52 CS1 CDP1802 CDP1824 8 CPU 32 BYTE RAM DATA CS1 8 DATA BUS FIGURE 1 TYPICAL CDP1802A 3 SMALL MICROPROCESSOR SYSTEM CDP1802AC 3 Absolute Maximum Ratings Thermal Information DC Supply Voltage Range Vpp Thermal Resistance Typical 9C W All Voltages Referenced to Vss Terminal SBDIP Package 1802 0 5V to 7 Device Dissipation Per Output Transistor Input Voltage Range All Inputs 0 5V to Vpp 0 5V TA Package Temperature Range DC
50. nes are used for transferring data between the memory the microprocessor and devices NO to N2 I O Control Lines Activated by an instruction to signal the control logic of a data transfer between memory and interface These lines can be used to issue command codes or device selec tion codes to the I O devices independently or combined with the memory byte on the data bus when instruction is being executed The N bits are low at all times except when an instruction is being executed During this time their state is the same as the corresponding bits in the N register The direction of data flow is defined in the I O instruction by bit N3 internally and is indicated by the level of the MRD signal MRD Vcc Data from I O to CPU and Memory MRD Vgg Data from Memory to EF1 to 4 Flags These inputs enable the controllers to transfer status information to the processor The levels can be tested by the conditional branch instructions They can be used in con junction with the INTERRUPT request line to establish inter rupt priorities These flags can also be used by I O devices call the attention of the processor in which case the pro gram must routinely test the status of these flag s The flag s are sampled at the beginning of every S1 cycle 3 19 CDP1802A CDP1802AC CDP1802BC INTERRUPT DMA IN DMA OUT 3 I O Requests These inputs are sampled by the CPU
51. nts Note 5 Data Bus Input Setup tsy Data Bus Input Hold tH Setup Hold tH Interrupt Setup tsy Interrupt Hold ty WAIT Setup tsy EF1 4 Setup tsy 5 EF1 4 Hold ty 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Required Pulse Width Times CLEAR Pulse Width tw 5 Pulse Width twL 5 Minimum input setup and hold times required by Part CDP1802AC 3 CDP1802AC 3 Performance Curves LOAD CAPACITANCE C_ 50pF SYSTEM MAXIMUM CLOCK FREQUENCY MHz 45 75 105 115 125 AMBIENT TEMPERATURE Ta qme FIGURE 2 TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF TEMPERATURE 3 9 o z 50 75 100 125 150 LOAD CAPACITANCE C pF FIGURE 4 TYPICAL TRANSITION TIME vs LOAD CAPACITANCE OUTPUT LOW SINK CURRENT mA DRAIN TO SOURCE VOLTAGE Vps V FIGURE 6 MINIMUM OUTPUT LOW SINK CURRENT CHARACTERISTICS LOAD CAPACITANCE C 50 AL I TA 1259 SYSTEM MAXIMUM CLOCK FREQUENCY MHz 10 SUPPLY VOLTAGE Vpp V FIGURE 3 TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE GATE TO SOURCE VOLTAGE Vgs 5V ea AMBIENT TEMPERATURE 40 85 C dez e 0 9 8 7 6 5 4 3 2 0 DRAIN SOURCE VOLTAGE Vps FIG
52. old general data By employing increment or decrement instructions such registers may be used as loop counters The Q Flip Flop An internal flip flop Q can be set or reset by instruction and can be sensed by conditional branch instructions The output of Q is also available as a microprocessor output 3 21 CDP1802A CDP1802AC CDP1802BC Interrupt Servicing Register R 1 is always used as the program counter when ever interrupt servicing is initiated When interrupt request occurs and the interrupt is allowed by the program again nothing takes place until the completion of the cur rent instruction the contents of the X and P registers are stored in the temporary register T and X and P are set to new values hex digit 2 in X and hex digit 1 in P Interrupt Enable is automatically deactivated to inhibit further inter rupts The user s interrupt routine is now in control the con tents of T may be saved by means of a single instruction 78 in the memory location pointed to by R X At the conclusion of the interrupt the user s routine may restore the pre inter rupted value of X and P with a single instruction 70 or 71 The Interrupt Enable flip flop can be activated to permit fur ther interrupts or can be disabled to prevent them CPU Register Summary D 885 Data Register Accumulator ss Ts Sepe Regis LT rei wien regir Fug
53. pecifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com RCA 1802 Microprocessor Prepared By Ben Knox Henna Karim Micah Sumner Morgan Grinstead John Redmon Prepared For Dr Joe Dumas College of Engineering and Computer Science University of Tennessee at Chattanooga November 13 2002 Computer Science 460 Section 001 Table of Contents Introduction Architectural Classification Intended Applications Control Unit Registers Bus Structure Performing VO Instruction Set Instruction Fetch and Decode Interrupt Processing Memory System Conclusion Bibliography Appendix Introduction The RCA 1802 was designed and introduced in 1974 The chip was capable of running at a clock frequency of 6 4 MHz using a 10V power supply The processor was designed and fabricated in CMOS The chip utilized 16 16 bit registers that could be accessed as 32 8 bit registers 10 It was 8 bit processor
54. rams The initial steps take by the processor for each type are the same First the interrupt request is sent by the device or program across a shared interrupt request line to the predefined interrupt pin number 36 on the CPU Second the X and P registers saved in the register However the registers only saved after the current instruction is finished executing Next Interrupt Enable is set to 0 to inhibit further interrupts from being processed lt is at this point that the handling of the interrupt differs If a user program caused the interrupt then the scratch pad register R 1 is set as the program counter and the address of the user defined instruction is loaded into it Next the user routine must save the value of T by using the sav instruction The sav instruction saves the value of T to the memory position pointed to by R X From this point forward the user program has full control on how the interrupt is to be handled Once the user routine is done executing then it is responsible for reloading the values of X and P The user routine restores the values of X and P by using either the ret or dis The ret and dis instruction work in almost the exact same way First they access memory at the address pointed to by the R X register Next using the data that is found at this address the instructions restore the X and P registers The instructions then increment the R X register so that it points to the n
55. rations provide conditional and unconditional branch instructions Arithmetic logic instructions provide the common operations add subtract AND OR EX OR and shift while control and I O commands that take care of the timing and data operations 5 The control functions facilitate the program interrupts operations selection branch and link operations and control the Q flip flop 2 The I O functions handle memory loading and data transfer operations into and out of the 1802 See Appendix A for a complete set of 1802 instructions Instruction Fetch and Decode Each CPU instruction is fetched on the first machine cycle and executed during the second machine cycle except for long branch and long skip instructions that require the first machine cycle to fetch the nd rd and 3 are designated to select one of the 16 bit registers as the current program counter The selected register instruction and on the 2 cycle fetch the address execute During the fetch cycle the 4 bits in P contains the address of the memory location to be fetched When the instructions are read out of memory the high 4 bits of the instruction are loaded into the register and the low 4 bits of the instruction are put into the N register The content of the program counter is automatically incremented by one so that it is now pointing to the next byte in memory 1 Interrupt Processing Interrupt services can originate from either I O devices or user defined prog
56. s appears on the memory address lines 7 first Those bits required by the memory system can be strobed into external address latches by timing pulse TPA The low order byte of the 16 bit address appears on the address lines after the termination of TPA Latching of all 8 higher order address bits would permit a memory system of 64K bytes MWR Write Pulse A negative pulse appearing in a memory write cycle after the address lines have stabilized MRD Read Level A low level on MRD indicates a memory read cycle It can be used to control three state outputs from the addressed mem ory which may have a common data input and output bus memory does not have a three state high impedance output MRD is useful for driving memory bus separator gates It is also used to indicate the direction of data transfer during an I O instruction For additional information see Table 1 Q Single bit output from the CPU which can be set or reset under program control During SEQ or REQ instruction exe cution Q is set or reset between the trailing edge of TPA and the leading edge of TPB CLOCK Input for externally generated single phase clock The clock is counted down internally to 8 clock pulses per machine cycle XTAL Connection to be used with clock input terminal for an exter nal crystal if the on chip oscillator is utilized The crystal is connected between terminals 1 and 39 CLOCK and XTAL in parallel with a resistance
57. t 91 different instructions These features along with its short instruction time were a milestone on the road to RISC chip design Bibliography 1 CDP1802A CDP1802AC CDP1802BC 1 vol 1 Intersil http Awww intersil com data fn fn1305 pdf 1997 2 CDP1824 CDP1824C no 1 vol 1 Intersil http www intersil com data FN fn1103 pdf Mar 1997 3 CDP1883 CDP1883C no 1 vol 1 Intersil http www intersil com data FN FN1 fn1507 FN1507 pdf 1997 4 PR CMOS PROM Interfaces with COSMAC Electronic Engineering vol 57 no 1 July 1985 pp 36 38 5 Unknown CDP1802 programming methods and mnemonic definitions Electronic Design vol 51 no 1 May 24 1978 pp 122 130 6 Pittman Tom A Short Course in Programming http Awww sbuniv edu tpittman IttyBitty ShortCor htm Current 1980 7 CDP1851 CDP1851C no 1 vol 1 Intersil http www intersil com Data fn fn1 fn1056 FN1056 pdf 1997 8 RCA CMOS LSI Products CDP1861C 1 vol 1 RCA http www cosmacelf com cdp1861 pdf 9 CDP1871A CDP1871AC 1 vol 1 Harris Semiconductor http Awww cosmacelf com cdp1871 pdf Aug 1996 10 1802 Microprocessor Core no 1 vol 1 Sierra Circuit Design Inc home teleport com scd IP IP1802 pdf 11 Joseph Weisbecker Build the COSMAC ELF A Low Cost Experimenter s Microcomputer Parts 1 4 Popular Electronics Aug 1976 pgs 33 3
58. t The control unit generally alternates between the 50 an instruction fetch and S1 instruction execution states takes one complete machine cycle to fetch or execute an instruction The only exceptions are the long branch and the long skip instructions These instructions require a single machine cycle to be fetched and two machine cycles to be executed Figure 3 provides a state transition diagram for the states of the control unit The minimum instruction time for 2 machine cycle instruction executed on the CDP1802 running at 6 4 MHz and 10v is 2 5 microseconds 1 Figure 2 State Table STATECODELNES CODE LINES Figure 3 State Transition Diagram IDLE FORCE 51 LONG LONG 5 V DMA INT PRIORITY 50 51 INT DMA DMA OUT INT The control unit has write pulse MWR and read level MRD output The tilde represents A negative pulse on the MWR represents a write cycle negative pulse the MRD represents a read cycle 1 The TPA and TPB timing pulses are sent out from the control unit These are the positive pulses that are sent out once in a machine cycle They are used by the controllers to synchronize interaction with the data bus trailing edge of the TPA signals the memory system to latch the high bits on the address bus The low order bits are placed on the bus at the termi
59. tween an array of ROM chips In this case the ROM chips are CDM5364 chips The CDM5364 chips are 8K by 8 bits in size and have roughly the same access time as the RAM The 1883 latch is 7 bit latch used to select between multitudes of different memory chips The latch uses to the upper 7 bits of the address The upper 2 high order address bits are decoded by the latch and used to select between the ROM chips The lower 5 high order address bits coupled with all the low order bits are used to access a particular memory address within the selected ROM chip 3 PROM An optional CMOS PROM can be added to the memory system of the 1802 architecture The HM6641 chip is usually used for this type of memory The HM6641 is a 512 byte by 8 bit CMOS PROM with a maximum access time of 250ns This PROM has an integrated address latch which allows easy interfacing to the multiplexed address bus of the 1802 4 Conclusion While the RCA 1802 is considered by today s standards a simplistic example of a CMOS processor it was considered cutting edge technology in 1974 With its single address space for both data and instructions and its single bi directional data bus the RCA 1802 can be classified as a Von Neumann or Princeton architecture machine The simplicity of the design and its low cost allowed for great flexibility and a cornucopia of applications It has a large register set 16 16 bit general purpose registers and a small instruction se
60. veforms Propagation Delays Not Shown MACHINE CYCLE CYCLE CYCLE n 1 CYCLE n 2 MA HIGH ADD LOW ADDRESS HIGH ADD LOW ADDRESS HIGH ADD LOW ADDRESS FIGURE 5 GENERAL TIMING WAVEFORMS INSTRUCTION FETCH 50 EXECUTE S1 FETCH 50 lt _ MEMORY READ CYCLE lt MEMORY CYCLE MEMORY READ CYCLE T _________ MWR HIGH MEMORY output P 4_ VALID OUTPUT K VALID ALLOWABLE MEMORY ACCESS OUTPUT DON T CARE OR INTERNAL DELAYS Wf HIGH IMPEDANCE STATE FIGURE 6 NON MEMORY CYCLE TIMING WAVEFORMS INSTRUCTION FETCH 50 EXECUTE S1 FETCH 50 EXECUTE lt _ MEMORY READ CYCLE MEMORY WRITE CYCLE MEMORY READ CYCLE MWR 4 r F MEMORY output _____ VALID OUTPUT K VALID OUTPUT To MEMORY OFF oF SSS DON T CARE OR INTERNAL DELAYS 2 HIGH IMPEDANCE STATE FIGURE 7 MEMORY WRITE CYCLE TIMING WAVEFORMS lt gt ALLOWABLE MEMORY ACCESS 3 13 CDP1802A CDP1802AC CDP1802BC Machine Cycle Timing Waveforms Propagation Delays Not Shown Continued INSTRUCTION FETCH 50 EXECUTE S1 FETCH 50 EXECUTE 4 MEMORY READ CYCLE 4 MEMORY READ CYCLE gt 4 MEMORY READ CYCLE MRD 1 MWR HIGH MEMORY output j L VALID
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