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Integration of a Data Acquisition System Based On FlexRIO

1. nds658lacqgen db O linux x86 64 Makefile nds658lacqgen db d I Makefile scripts Makefile nds658lacqgenADIOChannel cpp nds658lacqgenADIOChannel h nds658lacqgenChannelGroup cpp nds658lacqgenChannelGroup h nds658lacqgenDevice cpp nds658lacqgenDevice h nds658lacqgenDIChannel cpp nds658lacqgenDIChannel h nds658lacqgen h nds658lacqgenImageChannel cpp nds658lacqgenImageChannel h nds658lacqgenMain cpp nds658lacqgenNDArrayChannel cpp nds658lacqgenNDArrayChannel h O Common nds6581acqgen dbd nds658lacqgenInclude dbd O linux x86 64 libnds6581acqgen a libnds658lacqgen so Makefile nds658lacqgen nds658lacqgenADIOChannel d nds658lacqgenADIOChannel o nds6581acqgenChannelGroup d nds6581acqgenChannelGroup o nds658lacqgen dbd d nds6581acqgenDevice d nds6581acqgenDevice o nds6581acqgenDIChannel d nds6581acqgenDIChannel o nds658lacqgenlmageChannel d nds6581acqgenImageChannel o nds6581acqgenMain d nds6581acqgenMain o nds6581acqgen registerRecordDeviceDriver cpp nds658lacqgen registerRecordDeviceDriver d nds658lacqgen register RecordDeviceDriver o nds6581acqgen ioc unitenv epics test sh test template pl test template sh util sh LISTING 5 5 EPICS driver tree after compilation 48 Now the labour of the designer is to configure t
2. TON Rest of the world ITER Control Group x 18 CODAC Server Channel Access Gateway gt T TCN TCN DAN TCN DAN Fast Fast Controller Controller Sensors Actuators FIGURE 3 1 Physical Architecture of ITER I amp C System In the following sections the most capital pieces of CODAC and the important parts for the document scope are described giving an outline for the subsequent chapters 3 2 Plant System I amp C Design ITER I amp C System wrap all hardware and software required to operate the IT ER ma chine it comprises plant systems IEC Central IBC Systems and JC Networks Some entities have to be defined to understand the Instrumentation and Control architecture seen in figure 3 1 e A Plant System I amp C can be defined as all hardware and software required to control a plant system including local protection and safety functions Plant oystem I amp C encloses Plant Control System Plant Interlock System and Plant Safety Systems It has one plant system host and an arbitrary number of controllers called control units Controllers are divided into slow and fast depending on the process characteristics determining different technologies used for implementation PLCs for slow processes and Linux based computers running EPICS with PCI PXI I O for fast processes Slow controllers are programmed with Siemens SIMATIC STEP 7 and PCF and PSH are configured usin
3. iocnds658lacqgen 43 envPaths envSystem 45 Makefile I d README 47 st cmd _ Makefile 49 lib _ linux x86_64 51 libnds6581acqgen a libnds658lacqgen so 53 Makefile nds658lacqgenApp 55 Db Makefile 57 nds6581acqgenAnalogChannelEx template nds6581acqgenAnalogChannel template 59 nds658lacqgenAnalogInputChannel template nds6581acqgenAnalogOutputChannel template 61 nds658lacqgenChannelGroup template nds6581acqgenChannel template 63 nds6581acqgenDevice template nds6581acqgenDigitalChannel template 65 J nds6581acqgenDigitallnputChannel template J nds658lacqgenDigitalInputOutputChannel template 67 nds658lacqgenDigitalOutputChannel noparent template nds658lacqgenDigitalOutputChannel template 69 nds658lacqgenFFT template nds658lacqgenImageChannelRBV template 71 nds658lacqgenImageChannel template nds6581acqgenNDArrayChannel template 73 nds658lacqgen substitutions O Common N al 89 91 93 99 101 103 105 107 109 111 113 115 117 119 Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System Q
4. Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System LabVIEW DESIGN COMPILATION Compiler tools and C API GENERATION Files for the IOC to N configure the FPGA B and map the Ma resources Bitfile Mapped resources N EPICS Nominal Device Support Execution of the IOC PEN 3 PCI PCIe PCXI PXIe chassis Y 1 SCIENTISTS Control and monitor RIO Digital I O devices through FIGURE 5 1 Main schema of the design cycle workflow Adapted from Sanz et al 1 Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 34 5 2 Hardware Description Two hardware configurations are used for the fulfilment of the DAQ system as depicted in figure 5 3 and figure 5 4 One for local test and debug of the hardware deployed on the FPGA and the other one is the final hardware architecture of the system with an ITER Cubicle in the role of Fast Controller 5 2 1 NI 6581 I O Adapter Module The NI 6581 is a 100 MHz digital I O adapter module for NI FlexRIO This adapter module features 54 single ended digital I O lines with software selectable voltages of 1 8 2 5 and 3 3 5 V tolerant An external voltage can be referenced ranging from 1 8V to 5 5V independently for each of the two connectors combining it with an NI FlexRIO FPGA module creates an NI FlexRIO digital instrument NI PXI 6581R for a wide variety of applicati
5. e Nomenclature for FPGA registers and resources The NI C API Generator gen erates the C header file containing the information to access to the hardware in the FPGA with the same names of the LabVIEW FPGA controls indicators and DMA FIFOs the aforementioned driver seek these elements if they follow an specific nomenclature 1 Names of elements with no indexed postfix Global elements of the DAQ system e g DAQStartStop DeviceTemp DMAsOverF low etc 2 Names of elements with indexed postfix When more than one elements of the same type exist e g three digital inputs DIO DIL and DR e Mandatory registers and resources T here are some mandatory resources to build the CoreDAQ 1 Mandatory information Registers Divided into two subcategories attending at the moment that the driver seek them ones read in the initialization process e g total number of channels for the data acquisition and others checked at runtime e g status flags for FIFO overflow 2 Mandatory control registers Registers used to configure and control the CoreDAQ in runtime e g control to start and stop the acquisition 3 Mandatory resources These consist on FIFO DMAs used to transfer the acquired data from the FPGA to the host e Extra functionalities of the CoreDAQ Extra functionalities can be implemented depending on the requirements of the scientist e g data preprocessing in the CoreDAQ For more information about this see 1
6. so Listing 5 5 shows the target subdirectory structure To abbreviate the contents of src are not displayed because they suffer no modification once compilation is performed Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System m nds6581acqgen 3 pom xml src 5 7 target I main 9 epics A 11 _ linux x86_64 nds658lacqgen 13 configure CONFIG 15 INE SON IES DE Makefile 17 O Common O linux x86 64 19 _ Makefile RELEASE 21 RULES RULES DIRS 23 RULES ioc RULES TOP 25 db nds6581acqgenAnalogChannel template 20 nds658lacqgenAnalogInputChannel template I nds658lacqgenAnalogOutputChannel template 29 nds6581acqgenChannelGroup template nds6581acqgenChannel template 31 nds6581acqgen db nds658lacqgenDevice template 33 nds6581acqgenDigitalChannel template nds658lacqgenDigitallnputChannel template 35 I nds6581acqgenDigitallnputOutputChannel template nds658lacqgenDigitalOutputChannel noparent template 37 I nds6581acqgenDigitalOutputChannel template _ nds658lacqgenImageChannel template 39 I dbd nds6581acqgen dbd 41 iocBoot
7. LLLI IINE courses 26 A A 21 4 3 2 RIO for Compact Embedded Aplications 27 1221 Compet RIO 222 8 a nu a eee oa 27 44 LabVIEW fo FPGA euo ans AAA 28 5 Integration of NI 6581 and NI PXIe 7965R in CODAC Core System 31 5 1 DAQ System Design methodology used 31 SLI CODA Rul lt lt 0 8 nsr ss eee Ree bi 32 5 2 Hardware Description 2 2 2 0a 0 0 u 0 a a ka wa 2 o o 4 34 5 2 1 NI 6581 I O Adapter Module o o 34 5 2 2 Development and Test Platform 39 5 2 3 Final DAQ Architecture for ITER 39 5 3 Software description uoo ss sir moy xo e Owe we ow OE Ewe dH 39 54 LabVIEW project uos 08 3 8 8 ROS EE REDE ES EE we X6 SG 38 Do POWO LOPES ka da ne ER Ee Oe AA ade eS Al BE CIAL caras ee 42 5 7 ITER CODAC Maven 2 oo on 44 5 8 Nominal Device Support 2 a a llle 46 DS MM MU kaz B a OR x4 3 NOB 3085 40 DII IOC Gist Flle xx eo Hee SE SE Sew woo 49 342 EPICS database soso bk o3 ono Xo 9o X Xo w OS Wok x d o ow A 50 5 9 3 Device and Channels of the IOC 51 5 10 The Channel Access Operator Interface Clent 55 6 Results 57 D l 57 6 2 Future Work 1 cence oxomoxkRor a 9 ox as 59 List of Figures 2d 22 3 1 3 2 3 3 d l 4 2 4 3 4 4 4 5 9 1 9 2 5 3 5 4 5 9 5 6 5 7 5 8 9 9 9 10 5 11 5 12 5 13 Experimental Physics and Industrial Control System Logo 5 G
8. communicate with CODAC through the PSH it s configuration will be generated for each Plant System I amp C The communication with STEP 7 PLCs will be done through TCP IP Socket communication 3 3 2 Fast Controllers A fast controller is a control system component defined as a plant system controller used to implement control loops or data acquisition in Plant System Instrumentation 4 Control at a rate faster than 100 Hz In the current design it is implemented using PXI Express ATCA or uTCA based solutions the first ones to carry the I O boards and the last one proposed for diagnostics Figure 3 2 maps the fast controller in the ITER Plant System I amp C High Performance Networks HPN CODAC Terminal Time Communication Network TCN Synchronous Data Network SDN Data Archive Network DAN Audio video Network AVN Plant Operation Network PON Central Interlock Network CIN Central Safety Network CIN Plant System I amp C Plant Operation Network PON 8 Fast Fast Slow Slow Controller Controller Controller Controller miu Remote Signal Interface BE Interface mm Actuators and Sensors FIGURE 3 2 Fast Controller in the ITER I amp C System for PCIe technology The intended capabilities for a PCF are Chapter 3 ITER s CODAC 17 e Data acquisition with accurate time stamping e Actuation with precise timing e Real time exchange of data
9. Host The plant System Host is a system that is part of a plant system I amp C and is supplied and maintained by CODAC In the I amp C integration kits the PSH is configured in a computer that will be installed in one of the I amp C cubicles Each PSH belongs to one plant system I amp C it is connected to the PON network and belongs to the same sub network as the other controllers of the same I amp C The PSH has no I O board and cannot interface to any hardware It provides command dispatching state monitoring overall coordination health monitoring and optionally communication with slow controllers Each plant system I amp C can only have one PSH 3 3 4 CODAC Terminal A CODAC terminal is an operation station providing I O to from an operator through the human machine interface HMI CODAC terminals are close to local plant sys tem equipment for integration commissioning troubleshooting and maintenance of that equipment Control Room CODAC terminals use software deployed and configured us ing the CODAC Core System 3 3 5 CODAC Server A central CODAC server is a standard server class computer running either CODAC run time applications or CODAC support services Run time server applications include common EPICS applications such as archiving and alarm handling and common site specific applications including plant wide supervision monitoring and control global operational state management and interfaces to the CIS and CSS In
10. LHC NI NIC Abbreviations Application Specific Integrated Circuit Advanced Telecommunications Computing Architecture Channel Access Channel Access Client Channel Access Server Control Breakdown Structure CODAC Core System fr Conseil Europ en pour la Recherche Nucl aire Configurable Logic Block Control Data Access and Communication Control System Studio Data Archive Network Direct Memory Access Experimental Physics and Industrial Control System Fusion for Energy General Purpose Instrumentation Bus Hardware Description Laguages High Level Synthesis Human Machine Interface Instrumentation amp Control Input Output Controller International Thermonuclear Experimental Reactor Large Hadron Collider National Instruments Network Insterface Card XV Abbreviations OPI PCF PCDH PCF PCI PCIe PICMG PLC PON PSH PV PXI RCP RHEL RTOS SCTL SDN SoC XVI Operator Interface Plant Breakdown Structure Plant Control Design Handbook Plant Cotroller Fast Peripheral Component Interconnect PCI express PCI Industrial Computer Manufacturers Group Programmable Logic Controller Plant Operation Network Plant System Host Process Variable PCI eXtensions for Instrumentation Rich Client Platform Red Hat Enterprise Linux Real Time Operating System Single Cycle Timed Loop Synchronous Databus Network System on Chip Dedicated to Rebeca Jorge Pilar and Clara XVII Chapter 1 ITER t
11. SEER EEE MASSES ASSESSES SESE SEES SEP SESE ESSE EEE ESSE ESSE ESSE EE e FPGA Buffer Host Buffer gt kd AAA AAA AA AL A IIS FIGURE 5 5 DMA engine mechansim in RIO technology Extracted from 5 Depicted in figure 5 5 this mechanism work like a producer consumer mechanism NI recommends the host side buffer to be greater of 10 000 elements and twice the FPGA side buffer size That recommendations comes from the point that the consumption of the elements of the buffer are slower than the generation of them Figure 5 6 outline the data flow through the FlexRIO 7965R and NI 6581 adapter module to the host computer for local test where a simple LabVIEW Virtual Instrument manages the hardware and plots the acquired data orkStation m a NI PXle 1062Q NI PXle 8370 Nm vum Local W NI PCle 8371 FPGA Clock d kroomi gt w JN Backplane ee NI 6581 NI 0 i zn M ME E Read Write control functions Invoke Method Read FPGA DMA Configuration Parameters amp Indicators 64 bit word Digital Inputs NI 6581 NI 6581 CLIP sag r a Adapter Module FIGURE 5 6 Local Architecture With flux The final software architecture figure 5 7 differs from the other in the use of a Linux based platform where an EPICS IOC is created to control the instrument the EPICS Chapter 5 Integration of NI 65
12. System based on RHEL Red Hat Enterprise Linux operating system and by the plant design speci fications in which every CCS element is defined either hardware firmware or software In this degree final project the methodology proposed in Implementation of Intelligent Data Acquisition Systems for Fusion Experiments using EPICS and FlexRIO Technology Sanz et al 1 is used The final objective is to provide a document describing the fulfilled process and the source code of the data acquisition system accomplished The use of the proposed methodology leads to have two different stages The first one consists of the hardware modelling with graphic design tools like LabVIEW FPGA which later will be implemented in the FlexRIO device In the next stage the design cycle is completed creating an EPICS controller that manages the device using a generic device support layer named NDS Nominal Device Support This layer integrates the data acquisition system developed into CCS Control data access and communication Core System as an EPICS interface to the system The use of FlexRIO technology drives the use of LabVIEW and LabVIEW FPGA respectively UNIVERSIDAD POLIT CNICA DE MADRID Resumen Escuela T cnica Superior de Ingenier a y Sistemas de Telecomunicaci n Departamento de Ingenier a Telem tica y Electr nica Grado en Ingenier a Electr nica de Comunicaciones Integration of a Data Acquisition System Based On FlexRIO Technolo
13. addition CODAC servers run special applications such as pulse scheduling and scientific data archiving CODAC support services include directory services software download to plant systems and software configuration management 3 3 6 Storage Systems There are several storage categories attending to different functionalities such as the reliability high availability and high degree of integration with the servers other used for the CODAC System database services like alarms and error logs and other accom plishing requirements to evacuate data in quasi real time for visualisation and for long term archiving Chapter 3 ITER s CODAC 19 3 3 7 I O Boards I O boards are important components for CODAC A controller supervises one or many I O boards Each I O board has a set of channels that can be associated with plant sys tem signals and can be used to generate the I O configuration data for fast controllers There are a limited number of I O boards in the ITER Catalogue For Fast Controllers 110 The ITER standard Fast Controller catalogue describes the hardware accepted to be part of the experiment 3 4 CODAC software tools 3 4 1 Self Description Data toolkit Self Description Data SDD is an ITER concept designating the static data that de scribes the plant system characteristics in a unified way in order to facilitate configu ration of the Central I amp C systems software for operation with the given plant sys
14. by operating system and hardware Event driven Events request from another record via links EPICS Events and Channel Access Puts I O Event processing records based on external interrupts Passive records are processed as a result of linked records being processed or as a result of external changes such as Channel Access puts Scan Once Makes a record to be processed one time Chapter 2 EPICS 9 e Record support routines device support routines and device drivers for accessing to external devices for each record Record types not associated with hardware do not have device support or device drivers e The interface between the external world and the IOC via Channel Access e Database monitors provide a callback mechanism for database value changes This allows the caller to be notified when database values change without constantly polling the database e Tools to implement state machines Sequencer The IOC Core consists of the core software of EPICS that EPICS would not run without that are Channel Access IOC Database Scanners Monitors Database Definition Tools and Source Release folders containing the raw code and the compiled code respectively 2 4 The Channel Access The Channel Access Protocol is a client server TCP IP based communication protocol of EPICS The protocol defines how Process Variable data is transferred between a server and client in any IOC database and also
15. is developed One of the contributions of this De gree final work is to provide the aforementioned methodology one of the templates for acquiring and generating digital signals through a NI 6581 Adapter Module as a basic template for the DAQ system designer The next step for the designer is to generate the LabVIEW Bitfile with the synthesized hardware for the FlexRIO using LabVIEW compiler tools Parsing this Bitfile with C API Generator 13 produce one of the output files the C header file h that contains specific information to access to the hardware in the FPGA At this point the system designer labour focuses on the creation of the EPICS IOC application relying on the Nominal Device Support as a driver to the DAQ device The EPICS IOC is in charge of publishing through the CA the records for managing the DAQ device The EPICS device support created by Sanz et al 1 is able to adapt itself 31 Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 32 to the resources and functionalities found in the FPGA This driver is developed as a library and it is added to this EPICS IOC application to control the hardware of the developed DAQ system The main schema of the aforementioned process is depicted in figure 5 1 5 1 1 CoreDAQ Rules The minimal unit implemented having the mandatory requirements is the CoreDAQ The following rules have to be followed to interact to the hardware from an EPICS IOC application
16. nips cds view p lang en nid 202664 115 Isaev S ITER editor Nominal Device Support User s Manual Guide ITER IDM IDM UID A6LWQ8 1 2 edition 2014 16 Teske K ITER editor NIRIO Device Driver User manual ITER IDM IDM UID LW3UFH 2 1 edition 2014 117 Meyer K ITER editor ITER CODAC Maven Framework Guideline ITER IDM IDM UID 2AGGSG 1 0 edition 2013 118 Bustos A Ruiz M Sanz D Bernal E Di Maio F Barrera E Esquembri S Castro R and Vega J Symposium on fusion technology book of abstracts In tegration of advanced data acquisition applications using fpga based flexrio de vices in iter s codac core system Abstract Number P4 057 Sep 2014 URL http www soft2014 eu book_of_abstracts pdf
17. with other systems e Locally closed control loops in hard real time In the specific case of the PXIe the chassis is separated from the CPU standard industrial computer and interconnected using a PCle link As depicted in figure 3 3 the fast contolled is composed by an industrial PC with two separated Network Interface Cards NIC one for Data Archive Network DAN and Synchronous Databus Network SDN and the other for the Plant Operation Network PON All the hardware metioned for the PCF is integrated in a single I C Cubicle The link to the PXIe chassis is with a PCIe PXIe bridge The PXIe chassis will be covered in detail in chapter 4 and 5 since the Fast Controller is the target hardware for the DAQ system designed Fast Controller Industrial PC CPU 1 Hard disk O O U U Be PCI Express bus 1Gbps PON PCI Express PXle bridge Ethernet NIC ji SDN NI PCle 8361 MXI Express 10Gbps Ethernet NIC DAN PXI Chassis 18 Slot 3U NI PXle 1065 PCI Express PXle bridge Timing module TCN NI PXle 8361 MXI Express NI PXl 6682 PXle bus PXI 9x hybrid 4x PXle 3x PXle timing 1x n General purpose A D I O NI PXI 6259 HI Signal concentrator o o o total of 22 connectors o o o Signal concentrator o o 9 total of 22 connectors 9 o 9 FIGURE 3 3 Fast Controller Physical Architecture Scheme Chapter 3 ITER s CODAC 18 3 3 3 Plant System
18. 1acqgenChannelGroupDO cpp 284 lines nds6581acqgenChannelGroupDO h 69 lines nds6581acqgenChannelGroup h 47 lines nds658lacqgenDevice cpp 1037 lines I nds658lacqgenDevice h 141 lines nds6581acqgenDIChannel cpp 880 lines nds6581acqgenDIChannel h 133 nds6581acqgenDOChannel cpp 281 lines nds658lacqgenDOChannel h 81 lines nds6581acqgen h 22 lines nds658lacqgenMain cpp 23 lines NiFpga FPGA6581PXIe7965R h 420 lines NiFpga FPGAG6581PXIe7965R lvbitx 79134 lines niriodatatypes h 420 lines resources scripts test epics LISTING 6 1 Resumed tree of the directories for the DAQ system device support 6 2 NI 6581 Adapter Module and NI PXIe 7965R are part of ITER s catalogue for fast controllers 10 This work contributes to being the first case of use of the integration methodology proposed involving NI 6581 adapter module NI PXlIe 7965R Nominal Device Support and EPICS This development is accepted to be in the 28th Symposium On Fusion Technology SOFT materialised as a poster presentation with the tittle Integration of advanced data acquisition applications using FPGA based FlexRIO devices in ITER s CODAC Core System and presented in the Book of Abstracts of the Symposium on Fusion Technology with the reference number P4 057 18 Future Work To ease t
19. 3 Creation update of the software unit with dedicated commands The sequence of calls is produced by the SDD translator according to the I amp C project definition Chapter 3 ITER s CODAC 21 4 Edition of user defined files with test editor or specific editors such as the CSS SNL editor and VDCT 5 Compilation of the EPICS IOC processes and of the real time programs with the Maven compile command 6 Test of the project with the start stop status and test commands 7 Creation of the software packages for distribution with the package command As described in CODAC Plant Control Design Handbook 12 The graphical tool maven editor provides the user a graphical HMI for executing the commands This is also integrated in SDD tools so user can build test package the applications from the SDD editor or the SDD web application Chapter 4 National Instruments FlexRIO Technology 4 1 Brief FPGA basis Field Programmable Gate Arrays FPGAs are programmable semiconductor devices that are based around a matrix of Configurable Logic Blocks CLBs connected through programmable interconnections As opposed to Application Specific Integrated Circuits ASICs where the device is custom built for the particular design FPGAs can be programmed to the desired application or functionality requirements Although One Time Programmable OTP FPGAs are available The common type of FPGAs are SRAM based which the modelled hardware h
20. 32 SE and 16 LVDS Channel Digital I O NI 6584 16 Mbit s 16 Ch RS 422 RS 485 Digital I O NI 6585 200 Mbit s 32 Channel LVDS Digital I O NI 6587 1 Gbit s 20 Channel LVDS Digital I O NI 1483 Full Configuration Camera Link TABLE 4 2 NI FlexRIO Adapter Modules 9 processor running a real time operating system RTOS a reconfigurable FPGA and interchangeable industrial I O modules The CompactRIO system includes an embedded controller and reconfigurable chassis The embedded controller can host LabVIEW Real Time applications and can accomplish floating point math and analysis The embedded chassis contains the reconfigurable I O FPGA core directly connected to I O modules that deliver diverse high performance I O capabilities 4 4 LabVIEW for FPGA As mentioned in section 4 2 the use of a HLS design tool like NI LabVIEW leverages the complexity of the hardware modelled and makes easier the abstraction of following the dataflow of the modelled hardware To achieve high performance applications some specific techniques have to be followed understanding the performance as four different dimensions interrelated among each other these are throughput timing control FPGA resource use and numerical precision as proposed in the NI Lab VIEW High Performance FPGA Developer s Guide 5 Chapter 4 National Instruments FlerRIO Devices 29 Most of the issues related to high performance LabVIEW FPGA modelling involve the effective
21. 4B5 typedef enum NiFpga FPGA6581PXIe7965R IndicatorBool InitDone 0x2E NiFpga_FPGA6581PXIe7965R_IndicatorBool_RIOAdapterCorrect 0x12 NiFpga_FPGA6581PXIe7965R_IndicatorBool_auxDIO 0x4E NiFpga FPGA6581PXIe7965R IndicatorBool debug OxlE NiFpga_FPGA6581PXIe7965R_IndicatorBool typedef enum NiFpga_FPGA6581PXIe7965R_IndicatorU8_DeviceType 0x26 NiFpga_FPGA6581PXIe7965R_IndicatorU8_NoOfWFGen OxE NiFpga FPGA6581PXIe7965R IndicatorU8 typedef enum NiFpga_FPGA6581PXIe7965R_IndicatorI16_DeviceTemp 0x36 NiFpga FPGA6581PXIe7965R Indicatori16 typedef enum NiFpga FPGA6581PXIe7965R IndicatorU32 ExpectedIOModulelD 0x18 NiFpga FPGA6581PXIe7965R IndicatorU32 Fref 0x28 NiFpga_FPGA6581PXIe7965R_IndicatorU32_InsertedIOModulelD 0x14 NiFpga_FPGA6581PXIe7965R_IndicatorU32_auxAlO 0x40 NiFpga FPGA6581PXIe7965R IndicatorU32 typedef enum NiFpga_FPGA6581PXIe7965R_ControlBool_DAQStartStop 0x32 NiFpga_FPGA6581PXIe7965R_ControlBool_auxDOO 0x52 NiFpga_FPGA6581PXIe7965R_ControlBool typedef enum NiFpga_FPGA6581PXIe7965R_ControlU16_SamplingRateO 0x6 NiFpga FPGA6581PXIe7965R ControlU16 tvpedef enum i NiFpga_FPGA6581PXIe7965R_ControlU32_auxAOO 0x54 NiFpga FPGAG6581PXIe7965R ControlU32 auxAO1 0x48 NiFpga FPGA6581PXIe7965R ControlU32 auxAO2 0x0 NiFpga_FPGA6581PXIe7965R_ControlU32_auxAO3 0x44 NiFpga FPGA6581PXIe7965R ControlU32 auxAO4 0x38 NiFpga FPGA6581PXIe7965R Co
22. 81 NI PXIe 7965R in CODAC Core System 38 IOC will be detailed in section 5 9 In short the acquisition from EPICS is materialized with an EPICS thread in the Digital Input Channel Group then the Digital Input Channel Group transfers the acquired data to each Digital Input Channel Every Digital Input Channel has its own buffer of acquired data corresponding to each line of the digital input port of the NI 6581 adapter module NI PXle 8370 NI PXle 1062Q Fasten re re NI PCle 8371 ae Nake e Ye c e ma K P ee NI 6581 NI PXle 7965R s A Host DMA to Channel 1 8 Indicators uisition ule ord Raw data Digital Inputs INI 6581 CLIP Data Acq R NI 6581 NI 6581 CLIP Adapter Module FIGURE 5 7 Final Architecture With Data Flux 5 4 LabVIEW project The LabVIEW project consist in two main elements the host and the target see 5 8 The LabVIEW host is only used for local development tests Each FPGA target holds the same structure and elements then depending on the FlexRIO board one of the hardware pieces is selected to be the target for the synthesis In this case the target is FlexRIO 7965R device Figure 5 8 depicts the multi FPGA target solution for the DAQ system with the NI 6581 adapter module Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 39 Er 5 Proje
23. 81 Digital Adapter Module and with the benefit of being an instrument fully reconfigurable hardware and software it is decided to create an EPICS device sup port following NDS methodology for a device with two channel groups one for input channels acquisition and other for output channels test patterns generation The input channel group consist of 8 1 Bit channels FlexRIO devices are the bus master of the data transfer from the FPGA to the host therefore is equivalent to a Direct Memory Access engine mechanism DMA This is an unidirectional transfer mechanism A DMA channel consists of two FIFO buffers one on the host computer and one on the FPGA target Each side operates on its respective buffer and the DMA engine transfers data from one to the other once any of the following conditions are met e The FPGA side buffer is one quarter full e The FPGA side buffer has at least 512 bytes a full PCI Express packet e The timeout of the DMA controller fires This timer has a period of approximately one microsecond Once the transfer has started the host reads from the host side buffer by calling the Read method If the host side buffer fills up the DMA engine stops transferring data and the FPGA side FIFO reports the overflow as a timeout condition Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 37 gt FO Read Number of Elements Elements Remaining NI DMA Engine pS PSS RSS S ESSE SESS SEES
24. 975R PXle Kintex 7 XC7K410T 63 550 1 540 28 620 kbits PXIe 7966R PXle Virtex 5 SX95T 2 14 720 640 8 784 kbits PXIe 7965R PXle Virtex 5 SX95T 14 720 640 8 784 kbits PXIe 7962R PXle Virtex 5 SX50T 8 160 288 4 752 kbits PXle 7961R PXle Virtex 5 SX50T 8 160 288 4 752 kbits PXI 7954R PXI Virtex 5 LX110 17 280 64 4 608 kbits PXI 7953R PXI Virtex 5 LX85 12 960 48 3 456 kbits PXI 7952R PXI Virtex 5 LX50 1 200 48 1 728 kbits PXI 7951R PXI Virtex 5 LX30 4 800 32 1 152 kbits TABLE 4 1 NI FlexRIO Cards 8 define the I O in the LabVIEW FPGA programming environment NI FlexRIO FPGA modules feature as seen in table 4 1 Xilinx Virtex 5 and Kintex 7 FPGAs onboard dynamic RAM DRAM and an interface to NI FlexRIO adapter modules that provide I O to the FPGA The adapter module interface consists of 132 lines of general purpose digital I O directly connected to FPGA pins in addition to the power clocking and supplementary circuitry necessary to define the interface Adapter modules are instantiated as a part of the LabVIEW project in a Component Level Intelectual Property CLIP and the I O interaction is provided by LabVIEW interfaces Table 4 2 shows the full range of adapter modules provided 4 3 1 2 R Series Multifunction DAQ boards can measure and generate a wide variety of signals at dif ferent sampling rates R Series multifunction RIO devices integrates FPGA technology with analog inputs analog outputs and digital I
25. A designs To simulate and verify the behavior of your FPGA logic LabVIEW offers features directly in the development environment LabVIEW FPGA compilation tools automate the compilation process highlighting errors if occur and critical paths if timing errors occur to debug the design 4 3 RIO Platform Architecture The reconfigurable I O architecture combines the graphical programming environment with Processor a reconfigurable FPGA I O Modules for measurement and or acquisition see figure 4 3 The advantages of FPGAs for creating highly customizable and reconfigurable platforms implementing processing and control tasks with hardware circuitry and the capacity to perform multiple parallel operations within a single clock Chapter 4 National Instruments FlexRIO Devices 26 cycle Orchestrate with a processor offloaded by the FPGA and used to configure the FPGA interface with other peripherals log data run aplications etc and I O Modules directly connected to the FPGA for interfacing with other devices The reconfigurable FPGA is the core of the RIO hardware system architecture it is directly connected to the I O modules for high performance access to the I O circuitry of each module and unlimited timing triggering and synchronization flexibility Because each module is connected directly to the FPGA rather than through a bus there is almost no control latency for system response compared to other industrial controlle
26. O lines into a single device This devices support the PCI PCI Express PXI and USB buses with enclosed and board only options available Also feature a dedicated ADC per channel providing multirate sampling and individual channel triggering 4 3 2 RIO for Compact Embedded Aplications 4 3 2 1 Compact RIO CompactRIO is a small rugged RIO system for embedded and prototyping applications Onboard Memory 912 MB 912 MB 912 MB 912 MB 0 MB 128 MB 128 MB 128 MB 0 MB Configurable with four and eight slot backplanes It contains three components a Chapter 4 National Instruments FlerRIO Devices 28 NI 5791 100 MHz Bandwidth RF Transceiver NI 5792 200 MHz Bandwidth RF Receiver NI 5793 200 MHz Bandwidth RF Transmitter NI 5781 100 MS s Baseband Transceiver NI 5782 250 MS s IF Transceiver NI 5731 12 Bit 40 MS s 2 Channel Digitizer NI 5732 14 Bit 80 MS s 2 Channel Digitizer NI 5733 16 Bit 120 MS s 2 Channel Digitizer NI 5734 16 Bit 120 MS s 4 Channel Digitizer NI 5751 14 Bit 50 MS s 16 Channel Digitizer NI 5752 12 Bit 50 MS s 32 Channel Digitizer NI 5761 14 bit 250 MS s 4 Channel Digitizer NI 5762 16 Bit 250 MS s 2 Channel Digitizer NI 5771 8 Bit 3GS s 2 Channel Digitizer NI 5772 12 Bit 1 6GS s 2 Channel Digitizer AT 1120 14 Bit 2GS s 1 Channel Signal Generator AT 1212 14 Bit 1 2GS s 2 Channel Signal Generator NI 6581 200 Mbit s 54 Channel Single Ended Digital I O NI 6583 300 Mbit s
27. ONFIG 29 lines 18 CONFIG SITE 31 lines Makefile 8 lines 20 RULES 6 lines RULES DIRS 2 lines 22 RULES ioc 2 lines RULES TOP 3 lines 24 iocBoot iocnds658lacqgen 26 envSystem 5 lines Makefile 5 lines 28 I d README st cmd 68 lines 30 _ Makefile 6 lines Makefile 18 lines 32 nds6581acqgenApp I D 34 Makefile nds658lacqgenChannelGroup template 664 lines 36 nds6581acqgenChannel template 261 lines I nds658lacqgenDevice template 255 lines 38 nds6581acqgenDIChannelGroup template 6 lines nds658lacqgenDigitalChannel template 26 lineas AO nds658lacqgenDigitalInputChannel template 71 lines nds658lacqgenDigitalInputOutputChannel template 6 lines A2 nds658lacqgenDigitalOutputChannel noparent template 52 lines nds658lacqgenDigitalOutputChannel template 16 lines 44 nds658lacqgenDOChannelGroup template 667 lines _ nds658lacqgen substitutions 47 lines 46 Makefile 8 lines src 48 finder c 1309 lines Bibliography 59 nds6581acqgenChannelGroupDI cpp 271 lines nds6581acqgenChannelGroupDI h 73 lines nds658
28. T jwhile nds CHANNEL STATE PROCESSING get CurrentState LISTING 5 10 Acquisition Handle Implemented in Digital Input Channel Group 5 10 The Channel Access Operator Interface Client To manage the DAQ device through CA the Control System Studio provides a tool for Operator Interface OPI development and runtime environment called Best OPI Yet BOY This is graphical user interface that displays live control system data to operators and data can be written to the controls The BOY interface created has all the functionalities to interface with the DAQ system as a final product its features are Access to channels channel groups and device through messages e Indicators for the status of the channels channel groups and device e Control the type of acquisition Continuous or Finite e Control to perform a software trigger to start the acquisition e Control to the number of samples per trigger at finite acquisition e Internal loopback to acquire test patterns generated by the digital output channel The test patterns implemented are an static value from 0 to 255 a toggle of every line of the acquisition port and a 8 bit counter incremented every FPGA clock cycle from 0 to 255 Figure 5 13 shows the OPI panel developed to interface to the device performing a continuous acquisition with the output channel configured with the count up test pattern bypassed to the input channel Therefore the digital input
29. UNIVERSIDAD POLIT CNICA DE MADRID ESCUELA T CNICA SUPERIOR DE INGENIER A Y SISTEMAS DE TELECOMUNICACI N PROYECTO FIN DE GRADO Integration of a Data Acquisition System Based On FlexRIO Technology With EPICS Author Supervisor lvaro Bustos Benayas Dr Mariano Ru z Gonz lez A degree final project submitted in fulfilment of the requirements for the degree of Grado en Ingenier a Electr nica de Comunicaciones in the Departamento de Ingenier a Telem tica y Electr nica September 2014 UNIVERSIDAD POLIT CNICA DE MADRID Abstract Escuela T cnica Superior de Ingenier a y Sistemas de Telecomunicaci n Departamento de Ingenier a Telem tica y Electr nica Grado en Ingenier a Electr nica de Comunicaciones Integration of a Data Acquisition System Based On FlexRIO Technology With EPICS by lvaro Bustos Benayas EPICS Experimental Physics and Industrial Control System lies in a set of software tools and applications which provide a software infrastructure for building distributed data acquisition and control systems Currently there is an increase in use of such systems in large Physics experiments like ITER ESS and FREIA In these experiments advanced data acquisition systems using FPGA based technology like FlexRIO are more frequently been used The particular case of ITER International Thermonuclear Experimental Reactor the instrumentation and control system is supported by CCS CODAC Core
30. What the reader is going to find in the next sections is an example of an EPICS driver for reconfigurable hardware based on FlexRIO technology This driver is created following given LabVIEW FPGA design rules and using an EPICS driver able to find itself the resources and functionalities found in the FPGA at runtime as proposed by Sanz et al 1 To create the EPICS Device Support the Nominal Device Support common interface is used and documented as use case for later and more complex developments As an interface to the driver an EPICS client BOY panel is provided The hardware architecture is composed by FlexRIO devices in PXle chassis and a host computer connected to the chassis by a PCIe expansion link detailed afterwards 1 4 1 Content e Chapter 1 Global framework and introduction to the thesis topic e Chapter 2 EPICS the basis e Chapter 3 ITER s Control Data Access and Communication e Chapter 4 National Instrument s FPGA based FlexRIO devices e Chapter 5 Integration of NI 6581 and NI PXIe 7965R in CODAC Core System e Chapter 6 Results Obtained Chapter 2 EPICS 2 1 Introduction to EPICS EPICS 2s an open source distributed control system toolkit that consists of a set of soft ware tools and applications which provide a software infrastructure that application developers can use for building distributed control systems to operate devices such as Particle Accelerators Large Experiments and major Telescope
31. ano ceso AAA 1 1 3 The Machine 2029 eo 99 he ee a 2 1 4 Document Outline 0 nn 3 LII TUBAE a aria e ee AAA A 3 2 EPICS o 21 Introduction to EPIS o x xoxo DHE ER be KEE b 5 2 4 Process Variable 5 4 4 44 66 we bad Rew x GLO do OR mo ej 6 2 3 The Input Output Controller 8 2 4 The Channel Access ren 9 0 5 Device SUPPO ob he boa Ro bee d a FSP ERS e He sanum 40979 EG Hs 9 2 6 Tools alarms archiver and EPICS Clients o aoa a a a 10 3 ITER s CODAC 13 3 1 Control Data Access and Communication 13 3 2 Plant System I amp C Design nn 14 3 3 Hardware Components 16 vil Contents viii GO Slow Controllers uuu e ouo woo kom ox dp ok Ro a y ae eos 16 Bd Fast Controllers or ipods Xo 93 x43 x43 16 S Ilse Hose so co 8 ww o9 x x X Saar ni ow ox 18 3 3 4 CODAC Terminal 4 2 7 18 335 CODAC Server 44 ens 18 D Dtorape SYSTEME auos 665 u bb 4 Ew ehe 18 mar RI AI 19 3 4 CODAC software tools Em nn 19 3 4 1 Self Description Data toolkit 19 3 4 2 Control System Studie 34 looo ex oom es Roo RUE 20 odo Maven Elite ao rosdan eraketak be 9 dor neh 20 4 National Instruments FlexRIO Technology 23 Al Bue FPGA DOS eos ow xo rra AAA 29 42 FPGA Design Tools gt s 4399 RR ATE VE x OE SR o xU MD B 24 4 3 RIO Platform Architecture llle rn 25 4 3 1 RIO for PXIe anda PU o a ren haare 26
32. bVIEW FPGA Posteriormente se completa el ciclo de dise o creando un controlador EPICS que maneja cada dispositivo creado utilizando una capa software gen rica de manejo de dispositivos que se denomina NDS Nominal Device Support Esta capa integra la soluci n en CCS realizando la interfaz con la capa EPICS del sistema El uso de la tecnolog a FlexRIO conlleva el uso del lenguaje de programaci n y descripci n hardware LabVIEW y LabVIEW FPGA respectivamente Acknowledgements I would like to thank Dr Mariano Ru z Gonz lez Full professor at Technical University of Madrid colleague and friend His aptitude and experience are inspiring for the rest Prof Dr Alberto Mart n Dr Eduardo Barrera Full professor at Technical University of Madrid PH D s colleagues and friends Jes s Alonso Diego Sanz and Sergio Esquembri Nestor Fern ndez Paul Guill n Enrique Bernal Raul Melendez for sharing precious moments of despair happiness shouts and specially not very fortunate coffee flavour but by contrast very good beer Infinitely patient Rebeca Mom Dad Daughter and my hardy Granddad for being always present throughout the very time consuming musts and hobbies lvaro Bustos Benayas September 2014 Contents Abstract 111 Resumen iv Acknowledgements V Contents vi List of Figures ix List of Tables xi Contents xiii Abbreviations XV 1 ITER the experiment 1 1 1 The Organization and the project m a 1 L2 The SOU
33. channel is acquiring data containing values of a counter from 0 to 255 The chart displayed in the figure 5 13 contains the integer value representing the 8 bit acquired Considering that the FPGA frequency is 100MHz each 10ns the FPGA is acquiring a sample therefore each 80ns the system has acquired a 64 bit word Trying to publish every single data acquired through the Channel Access will collapse the network Consequently some decimation has to be done to the acquired data to publish it through CA The OPI panel graph Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 56 the way to new energy china eu india japan korea russia usa Data Acquired Samples Value 1970 01 01 00 060 00 090 00 120 00 150 00 180 00 210 00 240 00 270 00 300 00 330 00 360 00 390 00 420 00 450 1970 01 01 01 00 00 000 01 00 00 511 samples 83 84 65 82 PROCESSIN 83 84 65 82 PROCESSIN FIGURE 5 13 Operator Interface of the system of figure 5 13 is plotting 1 of each 32 samples acquired for this reason every slope is composed only by 8 samples Chapter 6 Results 6 1 Conclusions e A hardware for FlexRIO devices have been designed and synthesized with Lab VIEW FPGA The subsequent tables 6 1 6 2 6 3 6 4 and 6 5 extracted from Xilinx compilation chain tool specifies the resources and the maximum clock fre quency for PXIe 7965R FPGA Device Utilization Used Total Percent Slice Registe
34. ct NI6581 Continuous Acquisition Internal Clock lvproj E E My Computer MI 6581 adq gen lbyte Host wi T PXI 7952R RIOO Hf PXI 7953R RICO PXI 7954R R100 TE PXIe 7961R R100 t Hef PXIe 7962R RIOO gt 1 PXIe 7965R RIOO i FIFOs 3 B LJ IO Module Status j P g 10 ModulelO Enabled Pd Expected IO Module ID Pod Inserted IO Module ID 2 2 is FAA IO Module Present EG Board IO 1c l g PXLTrigl l g Device Temperature fi Mk 10 Module NI6581 NI6581 Port l dib DMATtoHOSTO xl 8 40 MHz Onboard Clock mil NI6581 adq_gen_1byte vi id El Control 1 ctl 2 id Dependencies E El 4 Build Specifications EEE PXIe 7966R RIO EE E Dependencies is E Build Specifications T FIGURE 5 8 LabVIEW Multi target FPGA Project The device behaviour acts as the automata depicted in figure 5 9 the transition among states is achieved with input signals of the FPGA Figure 5 10 shows the main Single Cycle Timed Loop SCTL for test pattern generation through connector B port 0 and the continuous acquisition state materialized in labVIEW code data is acquired through connector A port 0 As explained in section 5 1 the name of the controls and indicators with the exception of the mandatory ones is preceded by auz and the type of data followed by a number The device has two working modes one mode acquires data continuously Continuous Acquisition and the other on
35. data communication functions Communicates with CODAC System using CODAC Networks Comprises Plant System Host and plant system controller s Plant System Host Provides asynchronous communication from CODAC System to Plant Control System and vice versa Provides command dispatch ing state monitoring data flow and configuration functions Plant System Controller Provides plant system specific data acquisition control monitoring alarm handling logging and event handling functions Interfaces the Central IC systems through I amp C networks and plant system equipment through signals and fieldbuses Plant Interlock System PIS Provides Investment Protection functions for plant system Interfaces to Central Interlock System Plant Safety Systems PSS Provide Safety functions for plant system Interfaces to Central Safety Systems Chapter 3 ITER s CODAC 16 3 3 Hardware Components 3 3 1 Slow Controllers The term Slow Control is used for controllers that their reactivity is extremely slow in comparison to acquisition systems dedicated to the observation of the experiment They are in charge of the industrial services of the experiment that are not expected to change fast like vacuums cooling and control loops providing a control loop performance of 100 Hz or less Via a network connection to the controller they are programmed with STEP 7 engineering software from a Windows development system The PLCs will
36. ecord A particular instance of a Record Type with appropriate values entered into the relevant fields e Database A collection of records e Scanned processed Executing the record processing routine unique to a record type for a particular record 2 3 The Input Output Controller The EPICS software processes are called IOCs The main responsibility of the EPICS Input Output Controller IOC is to input data from the local process and or the operator manipulate convert compute it update the PV value time stamp and alarm status severity and optionally output data to the local control process EPICS PVs become part of an IOC s database The IOC scans the database deciding when and how to process a predefined record IOCs can run in the same environment as which it was compiled or can run in a different environment that where compiled using cross software development tools An IOC contains the following software components e The IOC Database The main element of an IOC is a database together with some structures that describe the contents of the database the first field of a database record contains the record name e Database access routines via channel or database access routines e Mechanisms for deciding when to process a record Scanners Periodic To process a record periodically standard scan rates are 10 5 2 1 0 5 0 2 and 0 1 seconds and custom scan rates can be configured up to speeds allowed
37. els bufSize amp RIOdevicedata registerChannelGroup channelGroupDI for int i 0 i lt nChannels i Creating input channel channel new acqgenExDIChannel channelType file CHANNEL TYPE_SUFFIX channelType i bufSize amp RIOdevicedata channelGroupDI gt registerChannel channel else if channelType CHANNEL TYPE DO l nds ChannelGroup xchannelGroupDO new acqgenExChannelGroupDO CHANNEL TVPE SUFFIXJI channelType 0 nChannels registerChannelGroup channelGroupDO for int i 0 i lt nChannels i channel new acqgenExDOChannel channelType file CHANNEL TYPE SUFFIX channelType i bufSize amp RIOdevicedata channelGroupDO gt registerChannel channel LISTING 5 9 Extract of Device Code Digital Input Channel Group and Channels creation Listing 5 10 shows the part of the acquisition handle implemented in the digital input channel group in charge of reading from the DMA the acquired data by the FlexRIO 7965R device NDS defines some basic states for managing internally channels channel groups and devices CHANNEL_STATE_PROCESSING is the functional state of every channel channel group and device The ring buffers for the digital input channels are created and the elements acquired are inserted in aforementioned ring buffers in the startCONTINUOUS Acquisition case nds CHANNEL STATE PROCESSING Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core Syste
38. eneric IOC Exploited View in the Channel Access Network 11 Physical Architecture of ITER I amp C System 0000 14 Fast Controller in the ITER I amp C System for PCIe technology 16 Fast Controller Physical Architecture Scheme 2 22 2222 2 17 Scheme of the elements of a FPGA 2 o 23 Configurable Logic Block Structural Scheme 3 24 NI FlexRIO Architecture Diagram 4 26 LabVIEW FPGA While Loop with each function registered Tclk is the clock period of the system Extracted from 15 aaa 29 LabVIEW FPGA Single Cycle Timed Loop Telk is the clock period of the system Extracted from 5 oo o 30 Main schema of the design cycle workflow Adapted from Sanz et al l 33 NI 6581 Adapter Module Specifications table extracted from 6 34 Local tests architecture e 39 Final Ae AAA 36 DMA engine mechansim in RIO technology Extracted from 5 37 Local Architecture With flux L 37 Final Architecture With Data FIX 38 LabVIEW Multi target FPGA Project 2 004 39 Automata of the hardware behaviour implemented in the PXIe7965R FPGA 40 Hardware implemented in the PXIe7965R FPGA 40 Software layers of the EPICS driver developed Yellow coloured boxes correpond to parts of the ndsRIO driver Figure based on T 41 Data Acquisition Software State Machine 52 Opera
39. ensures an interface between the CODAC central control system and the local control systems Each IOC provides a Channel Access Server which is prepared to establish communication with an arbitrary number of Channel Access Clients The main benefits of the CA are Provides transparency from the Operating System Network transparency equal access to remote and local channels CPU architecture independence isolation from software changes The software architecture paradigm is based on a publish subscribe messaging through out the control network The requests are based on the PV name and that requests include Search Get Put and Add Event methods 2 5 Device Support Device support is the interface between record and the hardware it hides hardware specific details from record processing routines Device support routines are the interface Chapter 2 EPICS 10 between hardware specific fields in a database record and device drivers or the hardware itself Device support modules can be divided into two basic classes synchronous and asyn chronous Synchronous device support is used for hardware that can be accessed without delays for I O Many register based devices are synchronous devices Other devices for example all General Purpose Instrumentation Bus GPIB devices can only be accessed via I O requests that may take large amounts of time to complete Such devices must have associated asynchronous device supp
40. f the hardware behaviour implemented in the PXIe7965R FPGA DAQStartStop B Esa bii Acquired Data buffer filled 8bits per Tclk o y Counter to fill all the u64 words DMAtoHOSTO JO Sample Counter For decimation ET pe E q a g Bas q E E 2 3 i FifoOverfolw pe Sample Counter for finite acquisition ExpectedIOModulelD EN l 84 Expected IO Module ID5 gt at Ban Inserted IO Module ID hua FPGA VO Node InsertedlOModulelD CountUp Default y SamplingRate0 DeviceTemp FIGURE 5 10 Hardware implemented in the PXIe7965R FPGA Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 41 5 5 Software Layers Figure 5 11 show the different user space and kernel space software layers involved in the operation of the EPICS driver developed The next sections will describe the different pieces of this driver departing from the hardware implemented in the RIO device to the Channel Access client created to interface with the driver The developed driver interfaces with the hardware through the NIRIO user library Channel Access A Record Support Device Support with MRT AsynDriver EPICS IOC NIRIO User mode library Operating system user Operating system Kernel NIRIO Kernel modules space driver FIGURE 5 11 Software layers of the EPICS driver developed Yellow coloured boxes correpond to parts of the ndsRIO drive
41. fied on ITER Catalog of 16 C products Fast Controllers 10 In this case the NI PXIe 7965R plus the NI 6581 Adapter Module is placed in a NI PXIe 1065 18 slot chassis designed for a wide range of test and measurement applications providing up to 1 GB s per slot dedicated bandwidth with nine PXI peripheral slots on the chassis A PCI Express extension NI PXIe 8370 linked with a MXI Express x4 copper cable to the NI PCIe 8371 Remote PCI Express x4 Control of PXI Express expansor see 5 4 The CPU is PICMG industrial computer 5 3 Software description The EPICS device support for this device is implemented using a software layer that generalizes the EPICS device support for DAQ and Timing devices called Nominal Device Support NDS 7 15 The motivation of having a common interface for all Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 36 NI PXle 1065 Chassis NI PXle 8370 PICMG NI PCle 8371 74546 0407 Molex Cable a LSI Has cabe PEN NI 6581 NI PXle 7965R w Mors EN those devices eases the labour of engineers to handle them This generalization is based EPICS FIGURE 5 4 Final architecture on names of functions provided by the device and also in terms of behaviour and usage of such device The DAQ system implemented is different from non FPGA based devices where hard ware functionalities are fixed by the manufacturer Being conscious of the input output ports of the NI 65
42. from the implemented hardware to change some controls of the implemented hardware or to write data to an EPICS record To accomplish that the designer has to register new records in the device template and create the aforementioned getters and setters to manage them The next sections get down to this processes 5 9 1 IOC Startup File The IOC startup file st cmd contains the IOC shell command in charge of defining the structure of the device With this command the device constructor is called which is in charge of creating the channel groups and channels ndsCreateDevice nds6581acqgen PORT FILE tmp q N AI 0 N AO 0 N_DI 8 N_DO 1 N_DIO 0 NIMAGE 0 RIOSERIAL 1666c59 RIOVI FPGAG6581PXIe7965R RIOMODEL P XIe 7965R LISTING 5 6 Creation of the device and its channels Listing 5 6 shows the st cmd line corresponding to the NDS call for the creation of the device each parameter corresponds to e nds658lacqgen is the name of the created device e N_AI 0 N_AO 0 N_DI 8 N_DO 1 N_DIO 0 N_IMAGE 0 are the declarations of the device channels in this case eight digital input channels inside a channel group and one digital output channel inside a channel group are going to be created Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 50 N_AI 0 Number of Analog Input channels for the device N_ AO 0 Number of Analog Output channels for the device N_DI 8 Number of Digital I
43. g EPICS tools under RHEL Chapter 3 ITER s CODAC 15 Each plant system I amp C implements one or many functions For each function the variables and commands have to be declared to operate in CODAC Each functional variable is instantiated by one control unit and maps directly to one EPICS Process Variable if the control unit is a PLC to one program variable in a PLC e Central I amp C Systems All hardware and software required to coordinate all plant systems I amp C including protection and safety functions and to provide the human machine interface HMI It comprises the CODAC System Central Inter lock System and Central Safety Systems Central Interlock System CIS Provides protection functions from ma terial damage which would result insignificant cost or schedule implications Communicates with Plant Interlock Systems using Central Interlock Network Provides status to CODAC System Central Safety Systems CSS Provide plant wide nuclear and occupa tional safety functions Communicate with Plant Safety Systems using Cen tral Safety Network Provide status to Central Interlock System and CODAC System e I amp C Networks Provide physical interface between Central I amp C Systems and plant systems I amp C Comprises CODAC Networks Central Interlock Network and Central Safety Networks e I amp C Plant Control System Provides local data acquisition control monitor ing alarm handling logging event handling and
44. generate documentation or deploy the finished product to a repository ITER CODAC Maven framework documentation 117 Projects created by a Maven plugin are called Maven projects The basic configuration file of each Maven project is named the pom rml Although the name of the file may be changed if needed it s required that each project have one of these configuration files With a combination of internal and external plugins the ITER Plugin was able to e Enable quick configuration of software projects at ITER CODAC e Create empty projects e Manipulate project files e Start and stopping IOCs e Manage CODAC servers such as beast and beauty e Handle dependencies e Check the environment sanity e And finally to deploy the project to a repository Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 45 The make base app plugin is used for creating EPICS applications from a template It is invoked as a command from the console and the result will be a new directory containing a Maven project set up to build EPICS applications e pom zml was generated specifically for the new project e Directory src main epics contains the source code e Directory src test epics contains the skeleton of automated test e Directory target will contain the compiled code and the generated RPMs mvn iter newunit Dunit m nds 6581acqgen cd m nds6581acqgen mvn iter newapp Dapp nds658lacqgen Dtype nds mvn i
45. gy With EPICS by lvaro Bustos Benayas EPICS Experimental Physics and Industrial Control System es un conjunto de her ramientas software utilizadas para el desarrollo e implementaci n de sistemas de adquisici n de datos y control distribuidos Cada vez es m s utilizado para entornos de experi mentaci n f sica a gran escala como ITER ESS y FREIA entre otros En estos exper imentos se est n empezando a utilizar sistemas de adquisici n de datos avanzados que usan tecnolog a basada en FPGA como FlexRIO En el caso particular de ITER el sistema de instrumentaci n y control adoptado se basa en el uso de la herramienta CCS CODAC Core System basado en el sistema operativo RHEL Red Hat y en las especificaciones del dise o del sistema de planta en la cual define todos los elementos integrantes del CCS tanto software como firmware y hardware En este proyecto utiliza la metodolog a propuesta para la implementaci n de sistemas de adquisici n de datos inteligente basada en EPICS y FlexRIO Se desea generar una serie de ejemplos que cubran dicho ciclo de diseno completo y que ser n propuestos como casos de uso de dichas tecnolog as Se proporcionar un documento en el que se describa el trabajo realizado as como el c digo fuente del sistema de adquisici n La metodolog a adoptada consta de dos etapas diferenciadas En la primera de ellas se modela el hardware y se sintetiza en el dispositivo FlexRIO utilizando La
46. he experiment 1 1 The Organization and the project Internationa Thermonuclear Experimental Reactor ITER is an international research and engineering international project with the intention to proof the viability of fusion as commercial energy source The scientific goal of the ITER project is to deliver ten times the power it consumes The consortium formed by China the European Union India Japan Korea Russia and the United States is officially signed on 21th November 2006 and assuming the cost the theoretical ten year construction stage and twenty year operational stage The members are organized locally in Domestic Agencies in the case of Europe the agency in charge is Fusion for Energy F4E to act as a nexus between their governments and the ITER Organization located adjacent to CEA Cadarache research center in Saint Paul lez Durance France 1 2 The Science As said previously ITER s final objective is to provide the mankind a cleaner safer and unlimited source of energy In fusion reactions lighter atomic nuclei fuse to form a heavier nucleus releasing a large amount of energy The most efficient fusion reaction to produce in a laboratory is the reaction between two hydrogen isotopes deuterium and tritium producing the highest gain of energy at the lowest temperatures compared with other elements requiring 150 Million degrees Celsius to produce Chapter 1 ITER the experiment 2 In ITER the fu
47. he labour of the system designer one of the future lines to work with is developing more LabVIEW templates for FlexRIO devices thus the designer will only have to focus on adapting the right template to the requirements of the experiment From the Operator Interface point some improvements have to be done specially in the plotter of the data acquired since BOY does not provide any suitable chart for digital signals To extend the idea of test pattern generation that can be used to emulate several devices connected to the system an interface to the user can be accomplished to configure user defined test patterns and load them into the hardware Bibliography 11 D Sanz M Ruiz R Castro J Vega J M Lopez E Barrera N Utzel and P Makijarvi Implementation of intelligent data acquisition systems for fusion experiments using epics and flexrio technology Nuclear Science IEEE Transactions on 60 5 3446 3453 2013 ID 1 2 National Instruments Fpga fundamentals Sep 2014 URL http www ni com white paper 6983 en 3 Xilinx Inc What is a fpga 2014 URL http www xilinx com fpga 4 National Instruments An introduction to the ni labview rio architecture Jan 2014 URL http www ni com white paper 10894 en 5 National Instruments NI LabVIEW High Performance FPGA Developer s Guide 1 1 edition 2014 URL http download ni com pub gdc tut labview_ high perf_fpga_v1 1 paf 6 National Instrume
48. he templates to create the EPICS driver fitting the requirements The files that have to be modified are contained in the following directories e m nds 658 lacqgen src main epics iocBoot iocnds658 lacqgen This directory contains the startup file st cmd to run de IOC e m nds 6561acqgen src main epics nds6581acqgenApp Db This directory contains the database of all records of the device Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 49 e m nds 6561acqgen src main epics nds6581acqgenApp src This directory contains the IOC sources where the DAQ functionality have to be implemented The next section covers in detail the creation of the EPICS device support for the DAQ system 5 9 EPICS IOC Doing an abstraction exercise and imaging the device as a black box with the EPICS IOC element in charge of the interface with the user through a Channel Access Client the DAQ system has to be seen as a device with a digital input channel group with eight channels inside and a digital output channel group with a channel inside although the configuration and the control lines of the device have to be taken also into account To implement such interfaces to the device and from the device to EPICS CA several EPICS records have to be created at device level the NDS proposed method for Process Variable handling through getters setters and callback functions is used respectively to get some parameters
49. ice 8 field DTYP asynInt32 field INP Qasyn ASYN PORT ASYN_ADDR State 10 field ZRVL 0 field ZRST UNKNOWN 12 field ONVL 1 field ONST IOCINIT 14 field TWVL 2 field TWST OFF 16 field THVL 3 field THST INIT 18 field FRVL 4 field FRST ON 20 field FVVL 5 field FVST ERROR 22 field SXVL 6 field SXST FAULT 24 field SVVL 7 field SVST RESETTING 26 field SCAN I O Intr T 28 record waveform PREFIX MSGS 4 field DESC Send message to device driver 30 field DTYP asynOctetWrite field INP asyn ASYN_ PORT ASYN_ADDR Command 32 field FTVL UCHAR field NELM 255 34 36 record waveform PREFIX MSGR field DESC Receive message from device driver 38 field DTYP asynOctetRead field INP asyn ASYN_ PORT ASYN ADDR Command 40 field SCAN 7 1 0 Intr field FTVL UCHAR 42 field NELM 255 LISTING 5 8 EPICS Database directory 5 9 3 Device and Channels of the IOC The Input Output Controller have to manage the hardware of the device implemented in the FexRIO 7965R Figure 5 12 depicts the acquisition software state machine This Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 52 acquisition state machine is materialized in the digi
50. it is guaranteed that the signal propagation between combinational blocks between circuitry inside it must not exceed one clock cycle The one cycle iteration latency of the SCTL is depicted in 4 5 where in a single clock cycle Telk the input signals are propagated to the outputs Once the LabVIEW data flow is understood the hardware architect shall follow the specific techniques for throughput optimization timing optimization and resource op timization covered in 5 depending on the design requisites Chapter 4 National Instruments FlerRIO Devices 30 Tak TIT E U Digital Input 0 YA B nni Digital Output i 2 g put IR B u Digital Input X M S oye a e FIGURE 4 5 LabVIEW FPGA Single Cycle Timed Loop Tclk is the clock period of the system Extracted from 5 Chapter 5 Integration of NI 6581 and NI PXIe 7965R in CODAC Core System 5 1 DAQ System Design methodology used As described in Sanz et al 1 the design cycle workflow for implementing DAQ systems based on FlexRIO technology there are different actors each one in charge of different parts of the design and implementation Once the scientist describes the diagnostics requirements the system designer labour focuses on adapting among the provided RI O FlexRIO LabVIEW templates more suitable for the particular case and following the rules for implementation called CoreDA Q rules Based on this methodology this DAQ system described in this document
51. it to configure the FPGA e NiFpga h file and NiF pga c The first one is a C header file It is identical for all generated C APIs It declares all the errors types constants and functions needed to write an application Most of these functions are defined in NiF pga c which defines all the functions that the application can call NiFpga c loads and unloads the NiFpga library at runtime and forwards function calls to that library NiFpga h and NiF pga c files are not used with the open source NI RIO driver hosted in the ITER CCS for more information go to 16 Genera hed with the FEGA Interface ARI Cenecerator s P for NI RIO 13 0 0 or later 5 ifndef __NiFpga_FPGA6581PXIe7965R_h__ define __NiFpga_FPGA6581PXIe7965R_h__ ifndef NiFpga_Version 9 11 13 N al N N 41 43 al al N OT 61 63 67 69 N al N Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System define NiFpga_Version 1300 endif include Nibpsa h Ir The filename of the FPGA bitfile x This is a fdefime to allow for string literal concatenation For example static const chart const Bittile Cs UNSXEDpea cEPGAO5SUPXIeSTOSObDE Bitfile define NiFpga FPGA6581PXIe7965R Bitfile NiFpga_FPGA6581PXIe7965R LY bit x I ri The signature of the FPGA bitfile uy static const charx const NiFpga_FPGA6581PXIe7965R_Signature 918 E43A425432733E2C0410D9D771
52. its e TIME Timestamp e HOPR High Operator Range e LOPR Low Operator Range e STAT Alarm Status e SEVR Alarm Severity The database db file can be used to get and set the contents of the fields of a record These values and attributes of Process Variables are defined by the CA Servers The Channel Access network protocol gives access to Channels A particular Channel has properties such as value time stamp units upper control limit lower control limit status and severity Main element s definition e A Process Variable Typed structure according to a record type and the in puts data manipulation and outputs are defined by EPICS records in the EPICS Database These EPICS variables are exchanged between servers and clients a PV is a typed structure according to a record type like binary input binary output analog input analog output calculation and the inputs data manip ulation and outputs are defined by configuring each record e A Record Type Predefined building block with a unique structure of fields and a unique processing routine to accomplish a specific function e Record support Refers to a processing routine and the definition of the structure i e an analog input record is used to monitor an analog signal convert it to engi neering units check the value against alarm limits and notify interested channel access clients of any significant change Chapter 2 EPICS 8 e R
53. le Specifications table extracted from 6 NI 6581 Adapter Module has two Digital Data Connectors DDC with three 8 channel bidirectional ports and three Programmable Function Interface PFI lines per connec tor These PFI lines serve as connections to timing signals you can connect a trigger connect or output a reference clock or output various signals Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 35 5 2 2 Development and Test Platform The hardware architecture used to implement the hardware deployed in the FPGA based NI PXIe 7965R device consist of a NI PXIe 1062Q Chassis 14 with a NI PXIe 7965R connected to its backplane and a NI 6581 Adapter Module Also connected to the backplane a PCI Express extension NI PXIe 8370 and linked with a MXI Express x4 copper cable The other extreme of the cable is connected to a NI PCIe 8371 PCI Express expansor hosted in the local workstation As depicted in the figure 5 3 The operating system of the workstation is Windows 7 and hosts LabVIEW 2013 and LabVIEW FPGA 2013 NI PXle 1062Q NI PXle 8370 Yo rm Local WorkStation NI PCle 8371 de e ke ke Ke c e 74546 0407 Molex Cable i m l mmm mp me me ue 3m l NI 6581 NI E LabVIEW FPGA FIGURE 5 3 Local tests architecture 5 2 3 Final DAQ Architecture for ITER The hardware architecture used by ITER for fast controllers where the DAQ system is placed is speci
54. ly acquires the number of samples commanded by the user Finite Acquisition The acquisition can be fired by software or by the PXI trigger line 1 useful if the acquisition wants to be started by other device The test pattern generator can be bypassed to the acquiring section of the hardware useful if the user wants to perform acquisition tests with known patterns Operationally the hardware works as explained below Every FPGA clock cycle 8 bits of data are acquired and stored in a 64 bit word by the iterative process of shifting the 64 bit word and inserting the new 8 bits acquired in the less significant byte Each clock cycle this process is repeated until the 64 bit word is filled then the data is written in the DMAToHost FIFO The aforementioned process is analogue in the two working modes the main difference of the finite acquisition state is that every 64 bit word is Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 40 counted down and compared with the input control implementing the value of number of data per trigger to acquire DAQ Start Stop 0 DAQ Start Stop 1 Elements remainning 0 Trigger 0 Wait for Trigger Trigger 1 amp amp Finite Acq Elements remainning 1 Finite Acquisition Trigger 1 amp amp DAQ Start Stop 0 Continuous Acq Continuous Acquisition DAQ Start Stop 1 FIGURE 5 9 Automata o
55. m 54 2 dof switch _RIOdevicedata gt DMAs 0 acquisitionType acquisitionType indicates the type of acquisition continuous or finite 4 case continuousacq Streaming to EPICS 6 lt Parameters Configuration RIOdevicedata gt DMAs 0 NwordU64 4096 Number of 64 bits words to read 8 RIOdevicedata gt DMAs 0 pdata uint64 t malloc RIOdevicedata DMAs 0 NwordU64x sizeof uint64_t lt Creation of one tinebutter for each channel 10 for j 0 j lt _RIOdevicedata gt NCHperDMAarray 0 j 12 RIOdevicedata gt DMAs 0 IdRing j epicsRingBytesCreate _RIOdevicedata gt DMAs 0 NwordU64x100 lt Ring buffer to store raw data NDS_NF n Info acqgen s It has been created an EPICS Ring buffer for channel d of DMAO n _RIOdevicedata gt RIOidentifier j 14 NDS_INF nContinuous Acquisition n 16 lt The DMA FIFO Configuration configDMAFifo 18 lt The Start DMA FIFO startDMAFifo 20 Cleaning DMA FIFO cleanDMAFifo 22 lt DAQStartstop gt gt gt 5tart DaqStartStop 1 24 lt START ACQUIsition DATA Continuous Mode start CONTINUOUSAcquisition lt Acquiring loop 26 lt STOP Data Acquisition DaqStartStop 0 28 lt Cleaning DMA FIFO cleanDMAFifo 30 lt Stop DMA FIFO stopDMAFifo 32 Free pointers free _RIOdevicedata gt DMAs 0 pdata 34 free paux8 36 break 38 case finiteacq lt Parameters Co
56. munication between PSH and PLC e The configuration for alarms archiving HMIs for the supported I O boards and the cubicles that shall be monitored from 4 0 e The mapping of Common Operating State variables into plant system specific ones from 4 0 3 4 2 Control System Studio Control System Studio CSS is part of CODAC Core System and is a collection of software built on Eclipse that provide an application framework for control systems Operator interface data archiving and monitoring alarm handling and data plots can be configured The CSS applications connect themselves to the IOC processes using EPICS Channel Access protocol CCS comes with an integrated tool to support the CODAC I amp C development life cycle create compile run and package I amp C applications 3 4 3 Maven Editor The CODAC build tool is an ITER s proprietary version of Apache Maven a software build automation framework All the EPICS development tools described in EPICS Application Developer s Guide 11 are valid but all of them are included in CODAC encapsulated within specific commands I amp C projects are developed using an ITER specific work flow that is supported by the SDD tools and by commands implemented using Maven The CODAC development work flow comprises 1 Creation of the I amp C project with the SDD Editor or SDD web application 2 Generation of the EPICS CSS STEP 7 configuration files with the SDD transla tor
57. nel template nds6581acqgenDevice template nds6581acqgenDIChannelGroup template nds6581acqgenDigitalChannel template nds658lacqgenDigitallnputChannel template nds6581acqgenDigitallnputOutputChannel template nds658lacqgenDigitalOutputChannel noparent template nds658lacqgenDigitalOutputChannel template nds6581acqgenDOChannelGroup template nds6581acqgenFFT template nds658lacqgenImageChannelRBV template nds658lacqgenlmageChannel template nds6581acqgenNDArrayChannel template nds6581acqgen substitutions Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 51 LISTING 5 7 EPICS Database directory For instance listing 5 8 is an extract of the record database file for the device The first record depicted is the one in charge of publishing the state of the device its name depends on the variable PREFIX set in the st cmd file NDS provides a way to connect EPICS record to C call back functions called record s handlers For each record NDS provides two functions a getter and a setter Getter and setter are used for record processing 7 2 f Device II IANAAANNN lt lt gt 2 gt Template file nds658lacqgenDevice template 11 6 record mbbi PREFIX field DESC The state of the dev
58. nfiguration 40 RIOdevicedata gt DMAs 0 NwordU64 _RIOdevicedata gt DMAs 0 samples_per _trigger Number of 64 bits words to read RIOdevicedata gt DMAs 0 pdata uint64_t malloc RIOdevicedata gt DMAs 0 NwordU64 xsizeof uint64_t 42 RIOdevicedata DMAs 0 DownFactor 1 TODO by now this is not used RIOdevicedata DMAs i BlockDF 200 Initialization of Block data decimation Every 200 data blocks only 1 is published 44 lt Creation of one ringbuffer for each channel for j 0 j lt RIOdevicedata gt NCHperDMAarray 0 j 46 RIOdevicedata DMAs 0 IdRing j 2epicsRingBytesCreate RIOdevicedata DMAs 0 NwordU64x100 lt Ring buffer to store raw data 48 NDS_NF n Info acqgen s It has been created an EPICS Ring buffer for channel d of DMAO n _RIOdevicedata gt RIOidentifier j 50 NDSAINE a Finite Acquisition n lt The DMA FIFO Configuration 52 configDMAFifo lt The Start DMA FIFO 54 startDMAFifo lt Cleaning DMA FIFO 56 cleanDMAFifo Ap i DAOStartstop Stop 58 Daqstartotop 1 lt START ACQUIRING DATA FINITE CASE 60 startFINITEAcquisition STOP Data Acquisition 62 Dadqstartotop 0 Cleaning DMA FIFO 64 cleanDMAFifo Stop DMA FIFO 66 stopDMAFifo Free pointers Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 05 free RIOdevicedata DMAs 0 pdata free paux8 break
59. nput channels for the device N_ DO 1 Number of Digital Output channels for the device N_DIO 0 Number of Digital Input Output channels for the device N_IMAGE 0 Number of Image channels for the device e RIOSERIAL 1666c59 corresponds to the serial number of the FlexRIO device used e RIOVI FPGA6581PXIe7965R is the name of the LabVIEW bitfile Ivbitx that has to be downloaded to the FPGA e RIDMODEL PXIe 7965R is the NiFlexRIO card model The A and the lvbitx in this case NiFpga_ FPGA6581PXIe7965R h and NiFpga_ FPGA6581PXIe7965R lvbitx files have to be copied manually inside the EPICS IOC source code directory m nds 6581acqgen src main epics nds6581acqgenApp src 5 9 2 EPICS database The IOC database folder named in this case m nds 658 lacqgen src main epics nds6561acqgenApp Db hosts the NDS templates for the device records the channel groups and the channels as seen in listing 5 7 It is automatically generated when the application is created with the commands explained above 5 2 The developer only has to edit the files to add the records required not being specified by default and delete the records that will not be used in the device Makefile nds6581acqgenAnalogChannelEx template nds6581acqgenAnalogChannel template nds6581acqgenAnalogInputChannel template nds6581acqgenAnalogOutputChannel template nds6581acqgenChannelGroup template nds6581acqgenChan
60. nternal signals which ultimately are wired to the modelled hardware entities However the modelled hardware behaviour is hard to be visualized in a sequential line by line flow textual language To then verify the logic created it is common practice to write test benches in HDL to wrap around and exercise the FPGA design by asserting inputs and verifying outputs The test bench and FPGA code are run in a simulation environment that models the hardware timing behaviour of the FPGA chip and displays all of the input and output signals to the designer for test validation The process of creating the HDL test bench and executing the simulation requires at least four times more than creating the original FPGA HDL design itself Once verified the text based model of the hardware through several steps synthesizes the HDL down into a configuration file or bitstream that contains information on how the components should be wired together As part of this multi step process a mapping of signal names to the pins on the FPGA chip have to be done The rise of high level synthesis HLS design tools such as NI LabVIEW system de sign software changes the rules of FPGA modelling and delivers new technologies that convert graphical block diagrams into digital hardware circuitry The LabVIEW pro gramming environment is suited for FPGA modelling being easier for the designer to recognize parallelism and data flow Also VHDL can be integrated into LabVIEW FPG
61. ntly reducing design complexity I Os in FPGAs are grouped in banks with each bank independently able to support different I O standards Today s FPGAs provide over a dozen I O banks thus allowing flexibility in I O support Embedded Block RAM memory is available in most FPGAs which allows for on chip memory in your design Digital clock management is provided by most FPGAs in the industry and also phase looped locking that provide precision clock synthesis combined with jitter reduction and filtering Memory resources are another key specification to consider when selecting FPGAs De pending on the FPGA family the on board RAM can be configured in different block sizes Digital signal processing algorithms often need to keep track of an entire block of data or the coefficients of a complex equation and without on board memory many processing functions do not fit within the configurable logic of a FPGA chip 4 2 FPGA Design Tools The way to build the logic that will be placed in the FPGA is modelling the behaviour of the system using development tools and then compile them down to a configuration file Chapter 4 National Instruments FlerRIO Devices 25 or bitstream that contains information on how the components should be wired together Hardware description languages HDLs such as VHDL and Verilog are textual lan guages for architecting a circuit Ihe syntax requires signals to be mapped or connected from external I O ports to i
62. ntrolU32 auxAO5 0x3C NiFpga FPGA6581PXIe7965R ControlU32 typedef enum NiFpga FPGA6581PXIe7965R IndicatorArravU8 FPGAVIversion 0x22 NiFpga FPGA6581PXIe7965R IndicatorArravU8 tvpedef enum NiFpga_FPGA6581PXIe7965R_IndicatorArrayU8Size_FPGAVIversion 2 L NiFpga_FPGA6581PXIe7965R_IndicatorArrayU Size typedef enum NiFpga_FPGA6581PXIe7965R_IndicatorArrayl16_NCHperDMATtoHOST OxA NiFpga_FPGA6581PXIe7965R_IndicatorArrayl16 typedef enum 43 Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 44 83 NiFpga_FPGA6581PXIe7965R_IndicatorArrayl16Size_NCHperDMATtoHOST 1 NiFpga_FPGA6581PXIe7965R_IndicatorArrayl16Size 85 typedef enum l 87 NiFpga_FPGA6581PXIe7965R_Target ToHostFifoU64_DMATtoHOSTO 0 NiFpga FPGA6581PXIe7965R TargetToHostFifoU64 89 fendif LISTING 5 1 C header file example generated from an FPGA VI bv C API Generator As shown in listing 5 1 the indicators and controls are arranged in different C enumer ated data types depending on the type of data each one has its own offset value to be accessed This h file and lubitx file will be part of the driver source files once created by the Maven linux shell commands 5 7 ITER CODAC Maven Maven is a software management and build automation tool The core of Maven is a framework for plugins With plugins any task can be performed to automate the build ing of a project as well as analyze the source code
63. nts 100 MHz Digital Adapter Module for NI FlerRIO Datasheet 1 1 edition 2009 URL http www ni com pdf products us cat ni6581 pdf 7 Isaev S editor Nominal Device Support EPICS Device Support Developers Guide ITER IDM IDM UID 66BSTM 2014 URL IDMITER66BSTM 8 National Instruments Components of a ni flexrio system Technical report Aug 2013 URL http ww ni com white paper 10800 en 9 National Instruments Ni flexrio adapter modules Sep 2014 URL http sine ni com nips cds view p lang en nid 206645 110 Makijarvi P ITER Catalog of IEC products Fast Controllers 2013 URL https www iter org org team chd cid codac plantcontrolhandbook 11 LL Andrew N Johnson Argonne National Laboratory W Eric Norum Lawrence Berkeley Laboratory Jeffrey O Hill Los Alamos National Laboratory Ralph Lange Benjamin Franksen Helmholtz Zentrum Berlin Peter Denison Diamond 61 Bibliography 62 Light Source Martin R Kraimer Janet B Anderson EPICS Application Devel oper s Guide 14 Jan 2014 URL http www aps anl gov epics base R3 14 12 php 112 Codac plant control design handbook web page URL https www iter org org team chd cid codac plantcontrolhandbook 113 National Instruments Introduction to the fpga interface c api generator May 2014 URL http www ni com white paper 9036 en 114 National Instruments Ni pxie 1062q 8 slot 3u pxi express chassis Sept 2014 URL http sine ni com
64. of plasma physics This include measurements of temperature density impurity concentration and particle and energy confinement times The diagnostic system will comprise modern techniques including lasers X rays neutron cameras impurity monitors particle spectrometers radiation bolometers pres sure and gas analysis and optical fibres Because of the harsh environment inside the vacuum vessel these systems will have to cope with a range of phenomena with great accuracy and precision Control Data Access and Communication CODAC is the central control system re sponsible for operating the ITER device CODAC interfaces to more than 30 ITER plant systems containing actuators sensors and local Instrumentation and Control I amp C For the machine protection interlock system and safety personnel and environment sys tems are explicitly decoupled from CODAC and act fully independently Control System Division incharge of aforementioned tasks is also responsible for the central interlock system and central safety system CODAC Core System CCS is the operating system for ITER and is based on Experimental Physics and Industrial Control System EPICS and Control System Studio CSS Users who contribute to the development of ITER Chapter 1 ITER the experiment 3 I amp C System such as ITER Domestic Agencies or industries working for ITER through contracts uses CODAC and dedicated software distribution 1 4 Document Outline
65. ons from high speed communication with a device under test to custom protocol emulation NI 6581 DDC Connector Pins Signal Name Pin s Signal Type Signal Description GLOBAL CLOCK 0 67 on DDCA Control Input terminal for the external sample clock source which can he used for dynamic acquisition GLOBAL CLOCK 1 67 on DDCB P0 0 7 25 27 29 31 59 61 63 65 Data Control Bidirectional Port 0 digital 1 0 data channels 0 through 7 P1 lt 0 7 gt 17 19 21 23 51 53 55 57 Data Control Bidirectional Port 1 digital 1 0 data channels O through 7 P2 lt 0 7 gt 9 11 13 15 43 45 47 49 Data Control Bidirectional Port 2 digital 1 0 data channels 0 through 7 CLOCK OUT PH 0 33 Control Output terminal for the exported sample clock PFI lt 1 3 gt 26 30 64 Data Control Bidirectional digital 1 0 channels 1 through 3 GND 2 4 6 8 10 12 14 16 18 20 22 24 28 32 34 Ground Ground reference for signals 36 38 40 42 44 46 48 50 52 54 56 58 62 66 RESERVED 1 3 5 7 35 37 39 41 N A These terminals are reserved for future use Do not connect to these pins No Connect 60 N A Do not connect to this pin lable 1 Pin Location and Signal Information for the NI 6581 NI 6581 Power Connector Terminals External Power Terminal Name Terminal Description GND Ground reference for external power VA External power terminal for DDCA connector VB External power terminal for DDCB connector FIGURE 5 2 NI 6581 Adapter Modu
66. ort Asynchronous device support makes it more difficult to create databases that have linked records 2 6 Tools alarms archiver and EPICS Clients EPICS version 3 14 provides a number of Operator Interface OPI based tools that can be divided into two groups based on whether or not they use Channel Access Channel Access tools are real time tools i e they are used to monitor and control IOCs e Channel Access Tools Display Managers like EDM MEDM read one or more display list files created by the Display Editor establishes communication with all necessary IOCs establishes monitors on process variables accepts operator control requests and updates the display to reflect all changes Alarm handlers archivers and probes allows the user to monitor and or change a single process variable specified at run time e Other OPI tools Database configuration tools like VDCT JDCT GDCT Display editor EDD used to create a display list file for the Display Manager State Notation Compiler that generates a C program representing the states for the IOC Sequencer tool The graphic 2 2 depict the environment of the Channel Access network with some ele ments suscribed as CACs and CASs Exemplifying five generic elements in the network coloured boxes and a the description of the elements within a generic IOC gray box MEDM yellow box is a display manager editor for EPICS LabView red box acts as Process Variable publi
67. osted can be changed as the design evolves Figure 4 1 depicts the main elements which the FPGA is composed by eo So Os 9 ma cee ri m ls 09000005 o066000002 e er 000000 S SSSR OODODODOZS AMMABLE 5 Ck 05 5 INTERCONNECT 3 2 A gt 2 a 000000003 2000000025 tra Cm bi cem ms on em om LOGIC BLOCKS FIGURE 4 1 Scheme of the elements of a FPGA 2 23 Chapter 4 National Instruments FlerRIO Devices 24 The configurable logic blocks CLBs slices or logic cells depicted in figure 4 2 are the basic logic unit of an FPGA They are made up of a configurable switch matrix with 4 or 6 inputs some selection circuitry like multiplexers and flip flops Various FPGA families differ in the way flip flops and LUTs are packaged together Ihe switch matrix is highly flexible and can be configured to handle combinatorial logic shift registers or RAM 5 Register Fast CY Latch Connects to neighbors Arithmetic Logic CIN FIGURE 4 2 Configurable Logic Block Structural Scheme 3 The flexible interconnection of the FPGA routes the signals between CLBs and I Os There are different types of routing from the interconnection between CLBs to fast horizontal and vertical lines crossing the device to global low skew routing for clocking and other global signals The design software makes the interconnect routing task hidden to the user unless necessity significa
68. pp nds658lacqgenChannelGroup h nds658lacqgenDevice cpp nds6581acqgenDevice h nds6581acqgenDIChannel cpp nds6581acqgenDIChannel h nds6581acqgen h nds658lacqgenImageChannel cpp nds658lacqgenImageChannel h nds658lacqgenMain cpp nds658lacqgenNDArrayChannel cpp nds658lacqgenNDArrayChannel h test_template pl test_template sh util sh LISTING 5 3 EPICS driver tree before compilation 5 8 Nominal Device Support As introduced in section 5 3 the Nominal Device Support NDS provides core for device integration to EPICS control system It defines EPICS database interfaces which intend to be common for the all devices of similar type To ease the developing labour NDS provides sets of EPICS templates and empty ap plication templates for EPICS device support module The output of these templates is a system library The templates include the skeleton for a full driver the developer must then edit the database template files and the C code of the driver to match the functionalities of the particular device Listing 5 3 shows the file structure of a NDS generic DAQ Once the fuctionalities of the device have been created the compilation is performed using the command Sm comple O O LisTING 5 4 Compilation Maven command The compilation creates a copy of all the directories of the project from src to target and compiles the application creating the EPICS database and the libraries of the application a and
69. r Figure based on 7 Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 42 5 6 C API The FPGA C API Interface is a C API for communication between processor and FPGA within NI reconfigurable I O RIO hardware such as NI CompactRIO NI Single Board RIO NI FlexRIO NI R Series multifunction RIO and NI MXI Express RIO for embed ded control and acquisition applications With the FPGA Interface C API developers can use LabVIEW graphical tools to con figure the field programmable gate array FPGA within NI hardware and choose either LabVIEW or C C tools to program the processor within the system The generated FPGA Interface C API of the FPGA application consists of the following files h file lubitx file NiFpga h and NiFpga c Unless you specify a custom prefix the FPGA Interface C API Generator names the h file the lvbitx file and the constants in the h file based on the name of the FPGA VI from which the application bitfile was compiled e Generated h File It is a C header file that contains all the constants required by function calls in the application The LabVIEW controls indicators and FIFOs present in the FPGA are represented by register offsets e Generated lvbitx Bitfile This is a version of the original bitfile created by LabVIEW renamed to match the prefix of the constants in the h header file This file has all the information of the digital circu
70. red for Mini CODAC PSH and PCF The EPICS framework is the base for the Fast Controllers and PSH and the EPICS CA protocol for access to plant system I amp C over the Plant Operation Network PON The ITER project is broken down into plant systems known as the Plant Breakdown Structure PBS The plants have specific functional requirements each requirement has to be treated separately with its own I amp C System called Plant System I amp C In order to facilitate integration and control CODAC has a functional categorization named Control Breakdown Structure Plant System I amp Cs are grouped into hierarchical control groups Each of these control groups can have a number of servers dedicated to runtime activities such as archiving control group management and configuration management for the control group Figure 3 1 illustrates the physical architecture of the ITER I amp C system A plant system includes a set of controllers with a PSH implementing a set of functions A control group is an assembly of plan system I amp Cs and central coordination 13 Chapter 3 ITER s CODAC 14 Legend E PON Plant Operation Network DAN Data Archive Network i TCN Time Communication Network CIN Central Interlock Network SDN Synchronous Databus Network CSN Central Safety Network Central supervision amp automation monitoring and data handling Human Machine Interface I Terminal E CODAC HPC Plasma Control
71. rs 1 0 Modules Signal Scrow Conditioning Terminals TT Signal Conditioning gt BNC PCI Bus Real Time High Speed Reconfigurable Digitizers Attenuation Connector Sensors Processor Bus FPGA and Isolation and Filters Block and Actuators FIGURE 4 3 NI FlexRIO Architecture Diagram 4 4 3 1 RIO for PXIe and a PC PXI PCI eXtensions for Instrumentation is a rugged modular instrumentation plat form designed for high performance applications It combines PCI and PCI Express bus technologies with a specialized synchronization bus PXI Express takes advantage of the PCI Express bus to offer a point to point bus topol ogy that gives each device its own direct access to the bus with up to 4 GB s of through put The integrated timing and synchronization lines are used to route synchronization clocks and triggers internally A PXI chassis incorporates a dedicated 10 MHz system reference clock PXI trigger bus star trigger bus and slot to slot local bus while a PXI Express chassis adds a 100 MHz differential system clock differential signaling and differential star triggers for advanced timing and synchronization 4 3 1 1 FlexRIO FlexRIO devices consist of a large FPGA as well as adapter modules that provide high performance analog and digital I O The adapter modules are interchangeable and Chapter 4 National Instruments FlerRIO Devices 27 Model Bus FPGA FPGA FPGA FPGA Memory Slices DSP Slices Block RAM PXIe 7
72. rs 5699 58880 9 7 Slice LUTs 4799 58880 8 2 TABLE 6 1 Report of the estimated device utilization at pre synthesis Device Utilization Used Total Percent Slice Registers 6105 58880 10 4 Slice LUTs 5802 58880 9 9 TABLE 6 2 Report of the estimated device utilization at synthesis Device Utilization Used Total Percent Total Slices 3107 14720 21 1 Slice Registers 5630 58880 9 6 Slice LUTs 5542 58880 9 4 DSP48s 0 640 0 0 Block RAMs 130 244 53 3 TABLE 6 3 Report of the estimated device utilization at mapping ov Chapter 7 Results 58 Clocks Requested MHz Maximum MHz 40 MHz Onboard Clock 40 00 55 49 100 MHz 100 00 113 06 TABLE 6 4 Report of the estimated timing performance at mapping Clocks Requested MHz Maximum MHz 40 MHz Onboard Clock 40 00 54 82 100 MHz 100 00 101 32 TABLE 6 5 Report of the estimated timing performance at place and route e The EPICS device support developed using the Nominal Device Support abstrac tion layer is made of the files shown in listing 6 1 the number of lines of each file is displayed afterwards the name I finder h 62 lines I Makefile 153 lines 2 m nds 658lacqgen I pom xml 73 lines 4 rE main 6 beast beauty 8 boy 6581 acqgen opi 10 pictures gt top logo png 12 _ scripts I eL 14 databrowser epics 16 configure C
73. s Such distributed con trol systems typically comprise a large amount of computers networked together to allow communication among them and to provide control and feedback of the various parts of the device from a central control room or even remotely over the internet EPICS uses a network based client server model Large scale scientific applications often require hundreds of devices to communicate over a single network to form large distributed con trol systems EPICS provides the standards and tools necessary to make this kind of EPICS communication possible FIGURE 2 1 Experimental Physics and Industrial Control System Logo The EPICS logo figure 2 1 represents the main idea of EPICS each coloured box represents a client or a server connected through a network For EPICS the Channel 5 Chapter 2 EPICS 6 Access CA role can be Channel Access Client CAC or Channel Access Server CAS CACs are programs that require access to the Process Variables to carry out their purpose and the service provided by Channel Access Servers is the access to Process Variables This chapter describes the main components the variables exchanged between clients and servers Process Variables 2 2 the element that manipulates this variables Input Output Controllers 2 3 backbone of the control network CA protocol 2 4 and some tools used to monitor archive and edit these exchanged variables 2 6 2 2 Process Variable Proces
74. s Variables PVs in the CODAC context often used in a narrower sense of EPICS PV are EPICS variables that are exchanged between servers and clients and are defined by EPICS records in the EPICS Database A process variable can give a computerised representation of a plant signal EPICS database is a process database running on a CAS also known as the Input Output Controller IOC this database consists of records which represent data points of control system Records consists of number of attributes fields and code that defines the records behaviour when active Most EPICS applications require only basic record types such as e ai ao Analog input output e bi bo Binary input output e longin longout Long integer value input output e mbbi mbbo Multi bit binary input output e stringin stringout String input output e calc Record that performs algebraic relational and logical operation e waveform Data in arrays Records can be connected among each other to exchange information and can be con nected to hardware devices Records can define database links to e Exchange data among each other records connected among each other Chapter 2 EPICS 7 e Implement closed loop control e Records can connect to hardware devices and or other records The IOC database manages Records A Record has Fields for instance a particular an analog input record can have fields such as e VAL value e EGU Engineering Un
75. sher subscriber My Data Collection Program blue box is Channel Access Client implementing a program iocCore green box is an IOC without any connection to hardware Simulator Code dark yellow box acts as a Process Variable Server in the network and the JOC gray box showing its internal structure Chapter 2 EPICS 11 ca CAS Channel Access Channel Access Server Client CAS Database Access Library IOC Database Scanners Driver or Devi pt saves 2 Library Routines Record Support Device Support Device Drivers HHT Instrumentation and control hardware FIGURE 2 2 Generic IOC Exploited View in the Channel Access Network Chapter 3 TER CODAC 3 1 Control Data Access and Communication As introduced in section 1 3 CODAC designates the central control system that operates in ITER The CODAC Core System is a software package that is distributed by CODAC Section of ITER Organization for the development of the Plant System I amp C It includes the software for Mini CODAC Plant System Host PSH and Plant Controllers Fast PCF and it provides the plant system I amp C developers the environment required to develop and test the software satisfying the ITER requirements The operating system for Mini CODAC PSH and PCF is an officially supported version of Red Hat Enterprise Linux RHEL The EPICS base is included in the distribution and is requi
76. sion reaction will be achieved in a tokamak device that uses magnetic fields to contain and control the plasma The helium nucleus carries an electric charge which will respond to the magnetic fields of the tokamak and remain confined within the plasma However some 80 percent of the energy produced is carried away from the plasma by the neutron which has no electrical charge and is therefore unaffected by magnetic fields The neutrons will be absorbed by the surrounding walls of the tokamak transferring their energy to the walls as heat the heat will be used to produce steam and electricity by way of turbines and alternators 1 3 The Machine The plasma will be confined by magnets in a torus hermetically sealed steel container named vacuum vessel holds the fusion reaction In order for the gas to reach the plasma state three external heating sources The ITER magnets will be cooled at 4 K in order to create the magnetic fields necessary for the plasma confinement that temperature will be created by an external cryogenic system after the Large Hadron Collider LHC at Conseil Europ en pour la Recherche Nucl aire CERN french acronym of European Council for Nuclear Research it will be the largest cryogenic system ever built An extensive diagnostic system will be installed on the ITER machine to provide the measurements necessary to control evaluate and optimize the performance of the exper iment and to further the understanding
77. tal input channel group using the mechanisms explained in section 5 3 After that every digital input channel buffer is filled with the acquired data Hardware initialization Wait for Trigger Hardware of Software Trigger Stop Acquisition command or Finite Acquisition Finalization Acquisition FIGURE 5 12 Data Acquisition Software State Machine Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 53 Listing 5 9 is an extract of the device creation process where the parameters from the ndsCreateDevice command are evaluated to create channel groups and channels for channelType 0 channelType lt 6 channelType 1 Getting int parameter nChannels getIntParam CHANNEL TYPE PARAM NAME channelType 0 if nChannels gt 0 nds Channelx channel Creating Channel Group object NDS C requires Channel Group object For this oject AsynPort will be created to support new NDS asyn addressing see documentation for details From base templates makeBaseApp top ndsApp src APPNAME h define CHANNEL TYPE AI 0 define CHANNEL TYPE AO 1 define CHANNEL TVPEDI 2 define CHANNEL TYPE DO 3 4 5 define CHANNEL TYPE DIO define CHANNEL_TYPE IMAGE define CHANNEL TYPE COUNT CHANNEL TYPEIMAGE 1 if channelType CHANNEL_TYPE_DI nds ChannelGroup xchannelGroupDI new acqgenExChannelGroupDI CHANNEL_TYPE_SUFFIX channelType 0 nChann
78. tem The SDD tool kit has been developed by ITER Organization in order to allow the user to configure the plant system I amp C and is a set of tools to support top down configuration and the programming of I amp C components SDD is part of the CODAC Core System The data created is then used to configure and program underlying Plant System I amp C hardware and software This includes e The SDD Editor to define the plant system interface the I amp C components the interfaced signals and to configure variables alarms archiving etc The editor is an Eclipse Rich Client Platform RCP application e The SDD translator to convert the SDD into the required EPICS configuration data for Mini CODAC PSH and fast controllers and into the required STEP 7 files for PLCs e The SDD sync tool to save and loading SDD data to from XML files and to synchronize local SDD databases with IO databases as well as local files with the IO source repository e The SDD parser to parse user provided or user modified EPICS configuration files EPICS record definition and retrofit changes into the SDD database The SDD tools provide the user with creation editing and saving features for Chapter 3 ITER s CODAC 20 e The list of signals interfaced by the plant system I amp C list of functions and vari ables implemented by the plant system I amp C and the list of control units PSH controllers that belongs to the plant system I amp C e The com
79. ter newioc Dioc nds658lacqgen LISTING 5 2 Creation of the main skeleton of the EPICS driver To create a new directory structure for the EPICS driver Maven plugin is invoked from a Linux shell after entering the commands listed in 5 2 if the tree bash command is performed the file structure generated can be seen in listing 5 3 2 m nds 658lacqgen pom xml 30 32 34 36 38 40 CONFIG CONFIG_SITE Makefile RULES RULES_DIRS RULES ioc RULES_TOP iocBoot iocnds658lacqgen Makefile envSystem Makefile README st cmd Makefile nds658lacqgenApp Makefile nds658lacqgenAnalogChannelEx template nds658lacqgenAnalogChannel template nds658lacqgenAnalogInputChannel template nds658lacqgenAnalogOutputChannel template nds658lacqgenChannelGroup template nds658lacqgenChannel template nds658lacqgenDevice template nds658lacqgenDigitalChannel template nds658lacqgenDigitallnputChannel template nds6581acqgenDigitallnputOutputChannel template nds658lacqgenDigitalOutputChannel noparent template nds6581acqgenDigitalOutputChannel template nds658lacqgenFFT template nds658lacqgenImageChannelRBV template nds658lacqgenImageChannel template Chapter 5 Integration of NI 6581 NI PXIe 7965R in CODAC Core System 46 nds658lacqgenNDArrayChannel template nds658lacqgen substitutions Makefile Makefile nds658lacqgenADIOChannel cpp nds658lacqgenADIOChannel h nds658lacqgenChannelGroup c
80. tor Interface of the system 22r 56 1X List of Tables 4 1 4 2 6 1 6 2 6 3 6 4 6 5 BIIIBIRO Cards S cnc bho eta ew eR dw 1B ESE SAS 21 NI FlexRIO Adapter Modules cen 28 Report of the estimated device utilization at pre synthesis 57 Report of the estimated device utilization at synthesis 57 Report of the estimated device utilization at mapping 57 Report of the estimated timing performance at mapping 58 Report of the estimated timing performance at place and route 58 xi Listings 5 1 C header file example generated from an FPGA VI by C API Generator 42 5 2 Creation of the main skeleton of the EPICS driver A5 5 3 EPICS driver tree before compilation 04 45 5 4 Compilation Maven command 0 002 ee eee 46 5 5 EPICS driver tree after compilation 47 5 6 Creation of the device and its channels 000000 49 5 7 EPICS Database directory 0 0 0 00 eee ee ee 50 5 8 EPICS Database directory 2 0 0 0 eee ee 51 5 9 Extract of Device Code Digital Input Channel Group and Channels creation 53 5 10 Acquisition Handle Implemented in Digital Input Channel Group 53 6 1 Resumed tree of the directories for the DAQ system device support 58 x111 ASIC ATCA CA CAC CAS CAS CCS CERN CLB CODAC CSS DAN DMA EPICS FAE GPIB HDL HLS HMI I amp C IOC ITER
81. use of the Single Cycle Timed Loop SCTL The SCTL is a key LabVIEW FPGA structure that reduces resource use and allows for higher throughput and more precise timing control The SCTL provides a different paradigm compared with a Lab VIEW While loop or For loop The traditional execution model followed by LabVIEW is called Structured data flow where a function must have all of its input parameters before it executes and the caller blocks until the function returns The way that LabVIEW FPGA accomplish that when translated to hardware is adding circuitry needed to make sure that the components only outputs valid data when they have valid data at all of their inputs T his is materialised connecting every block output to a register As depicted in 4 4 red boxes with an R inside symbolises the existent registers that LabVIEW internally adds for accomplishing its paradigm with the system pipelined every clock cycle Telk the signals are only propagated from one register to the next one Tak Tak Tak A Digital Input 0 y y i P JNU Digital Output DAR TUU Digital Input 155 CAUse rs aa e Drivelmar gui DEAL ps e e BAA Analog Output 0 FIGURE 4 4 LabVIEW FPGA While Loop with each function registered Tclk is the clock period of the system Extracted from 5 In contrast the SCTL is a structure unique to LabVIEW FPGA applications The synthesis of what is placed inside a SCTL differs from While Loop in

Integration of a Data Acquisition System Based On FlexRIO

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