XEM6310MT User`s Manual
Contents
1. All dimensions in mm2. CY men Mawa OC LQ 4 015988 OO 666 6 4 OO 88 006 GG GONG r Ugen 00 GH O ear Io 1018 OO CL CG 99 O Hi 6 6 11 16 1099 dk UU 0 DINGS 13990 00 r oo THOR 2 00116 Gei Gei Zeit Tr Or O E OO LE Yar 0 r E We lt 4 C 1 Ke L 1 IKO Si 00 1 52 mil OGL SE oo ool lo 060 ats OO L A moO m OECD OECD 300 G et a i i i mmm fb SHH HR R HHEH GA O S UU Q a 29 Og SRR E UN as ja 00 71 0 Senne b Seno 00200 000219 SI axed aaa 00 S x O_O O_O O_O O_O Ou CG G 6 6 6 Yzal 526 OC OIO OILO OILO OILO Ee se DEE n 0 U O O O O O O O OO O O O O OO OOO O LO O O WO NO O mR CH N N LO SO LO CN O O O O N LO LO CN N www opalkelly com 26 XEM6310MT Users Manual XAEM6310MT Quick Reference DL pagi Ei Pin Connection FPGA Pin mm INE pap W22 W20 Y22 7 928 gt U22 U20 T22 12 N19 9 989 P20 7 420 M19 0 0
3. 21 PANA E ove ciu Ot usa Sd 21 Pee does es SEN Si dhe a Bd Es ee 22 DOOR EE 22 Export PDF CSV Constraints Files 22 Peripherals 22 PCB Version History 24 24 XEM6310MT Mechanical Drawing 25 BRK6310MT Mechanical Drawing 26 XEM6310MT Quick Reference 27 XEM6310MT Quick Reference 28 XEM6310MT Quick Reference 29 4 www opalkelly com XEM6310MT Users Manual Introducing the XEM6310MT The XEM6310MT is a compact FPGA board featuring the Xilinx Spartan 6 FPGA and Super Speed USB 3 0 connectivity via a USB 3 0 Micro B receptacle Designed as a full featured integration system the XEM6310MT provides access to over 120 I O pins on its 484 pin Spar tan 6 device in addition to two dual transceiver tiles and has a 128 MiByte DDR2 SDRAM avail able to the FPGA Two SPI Flash devices provide a total of 32 MiB of non volatile memory one attached to the USB microcontroller and one attached to the FPGA Available with LX45T and LX150T FPGA densities the XEM6310 is designed for medium to large sized FPGA designs with a wide variety of external interface requirements PCB Footprint A mechanical drawing of the XEM6310MT is shown at the end of this manual The PCB is 60mm x 75m
4. Opal Kelly XEM6310MT User s Manual A compact 60mm x 75mm integration board featuring the transceiver capable Xilinx Spartan 6 LXT FPGA SuperSpeed USB 3 0 on board DDR2 memory and two 16 MiB Flash memories The XEM6310MT is a compact USB 3 0 SuperSpeed FPGA integration module featuring the Xilinx Spartan 6 LXT FPGA 1 Gib 64 Mx16 bit DDR2 SDRAM two 128 Mib SPI Flash devices high effi ciency switching power supplies and three high density 0 5 mm expansion connectors The USB 3 0 SuperSpeed interface provides fast configuration downloads and PC FPGA communication as well as easy access with our popular FrontPanel application and SDK Two low jitter 100 MHz crystal oscillators are attached to the FPGA for fabric and transceiver clocking Software documentation samples and related materials are Copyright 2014 2015 Opal Kelly Incorporated Opal Kelly Incorporated Portland Oregon http www opalkelly com All rights reserved Unauthorized duplication in whole or part of this document by any means except for brief excerpts in published reviews is prohibited without the express written permission of Opal Kelly Incorporated Opal Kelly the Opal Kelly Logo and FrontPanel are trademarks of Opal Kelly Incorporated Linux is a registered trademark of Linus Torvalds Microsoft and Windows are both registered trademarks of Microsoft Corporation All other trademarks referenced herein are the property of their respective owner
5. JP2 6 3 3vpp 3 3VDD JP1A 6 7 JP2 JTAG_TMS JP3 4 Filters You can hide or show the additional information associated with each signal by clicking on the icon at the top left Toggle Filters Use these filters to limit the visible pin listing to particular subsets of signals you are interested in Search You can search the pin list using the search entry at the top right Click on the magnifying glass drop down to adjust the function of the search to one of e Highlight Highlights search results only e Hide Matching Hides rows where search matches are found Show Only Matching Shows only rows where a search match is found Export PDF CSV Constraints Files The export button near the search entry allows you to export the pin list in several formats PDFs can be viewed or printed CSV can be loaded into a spreadsheet application or manipulated with scripts Constraints files can be used as inputs to Xilinx and Altera synthesis and mapping tools The constraints files include additional mapping information for other peripherals on the module such as memory clock oscillators and LEDs Peripherals A Pins Peripheral is a project definition where you can enter your top level HDL design nets to have Pins generate a complete constraint file for you When you create a Peripheral you will select a target integration module The Peripheral is paired to this module so that the design parameters match the features a
6. www opalkelly com A O O 1 A 7 AL LU up Imo 00D 0 D a IP I A 47 00 1 B EE 0 D el Wo oe i yw hm o 40 07 L US e como EAN te FE SR ec 7 Em 0 g i E BB DEED el 5 BD Ke TS ge La HCH d e Ze al 13 00 em D Lg Bes Bl TH H E Kelly E i 2888883 ee eee 0 OO o KOK ONY o O o NN wT LO ON LO CN OK KK 03 65 O O g wT E F vn 1 1 11 rm AN ee PUP tach HR Oo Tg Ban Deg ch om BAB BABE 2 ECKE e a Be 3 go fa ZE R SI z G u x B ES n ICH EL 7 B S Sg 0 8383 EBT Reg a HHHH HHHHHHHHHHHHHHH 9 eee eg 11111111 O O O OC 5 LO O d dee Kerg KA Po s OP EN RET BRK6310MT Mechanical Drawing XEM6310MT Users Manual A c cO E 00 06
7. 2 vecoo lt Q Q O mamo aao pp DD co ira L64P_0 66 977 L64N_0 64 444 C17 L50P 0 51 818 2 NO 29 117 36 002 53201 22 653 30 429 33384 34 084 77 825 76 684 L66P 0 76 936 L66N_0 77 180 LN U 46 088 L7P_0 45 513 L38P_0 65 023 L49P_0 58 343 L49N_0 59 729 L37P GCLK13 0 67 989 67 275 55535 56435 61 776 60 975 59 658 57 204 62 361 62 766 L38N_VREF_0 64 538 N N All N ojlo aloalo ml FF b ololololleolirsirso aN cola CH RIN o Sl oleo N O SMOKIN O llo AINIS TIT 2 IO gt gt UO m S 5 RIS S www opalkelly com XEM6310MT Users Manual XAXEM6310MT Quick Reference JP1 Length Pin Connection FPGA Pin mm s ps EN 7 meroon Im e e menoon Ise T o TT m o merero 5001 24786 Cc 2 jo J T as op T JP1 Length Pin Connection FPGA Pin mm e pop 8 D15 MOTRXP1 123 2658 25397_ 12 pop 18 pop _ 24 pop 2 pop 2 pop 3 pop 3 pop TT www opalkelly com 29
8. for generating constraint files for place and route tools Pins can be found at the URL below http www opalkelly com pins Toolbar The toolbar at the top of a Pins product page has a number of features Explore a bit you won t break it vs Click for column selection and filters Y sar Export PDF CSV or constraints file XEM6310 Click for symbol legend Drop down for search behaviors Pin Lists As the primary reference for Opal Kelly integration module expansion connectors Pin Lists con tain a comprehensive table of the FPGA to Connector data including connector pin FPGA pin signal description routed length when applicable breakout board pin mapping FPGA I O bank and other properties By default not all data columns are visible Click on the Toggle Filters icon at the top left to se lect which columns to show Depending on the specific module several additional columns may be shown The data in these columns is always exported when you export the pin list to CSV www opalkelly com 21 XEM6310MT Users Manual m XEM6310 CHOOSE PRODUCT Reset filters Connector all Power all Ground all 1 Power all MO all MO Bank all JTAG all Clock all FPGA Clockin all CONNECTOR PIN FPGA PIN DESCRIPTION LENGTH MM BRK6110 Connector FPGA Pin Description Length mm BRK6110 JP2 1 DGND JP1A 1 JP2 2 3 3VDD JP1A 2 JP2 3 Vbatt VBATT JP2 4 EET 3 3VDD JP1A 4 JP2 5 JTAG_TCK JP3 6
9. included the lengths of the board routes for these connections to help you equalize lengths in your final application Due to space constraints some pairs are better matched than others Reference Voltage Pins VREF The Xilinx Spartan 6 supports externally applied input voltage thresholds for some input signal standards The XEM6310MT supports these Vrer applications for banks 0 and 1 www opalkelly com 19 XEM6310MT Users Manual For Bank 0 the four VREF pins are routed to expansion connector JP2 on pins 27 35 40 and 52 Note that all four must be connected to the same voltage for proper application of input thresh olds Please see the Xilinx Spartan 6 documentation for more details For Bank 1 the four VREF pins are connected to a single pin on expansion connector JP3 pin 71 IBERT Configuration Xilinx provides the IBERT tool to test and experiment with gigabit transceivers The settings below are compatible with the XEM6310MT and BRK6310MT combination Generate Bitstream Enabled Add RXRECCLK Probe Not checked GTP Dual Naming Style MGTm n system Clock Use External Clock Source Checked Frequency 100 MHz Pin Location Y11 Pin Input Standard LVCMOS25 Number of Protocols 1 Line Rate Settings Name Protocolo Custom_1 Max Rate Gbps 2 5 Gbps Data Width 20 Refclk 100 MHz GTP Dual Count 2 MGT DUAL 123 Custom 1 2 5 Gbps MGT DUAL 101 Custom 1 2 5 Gbps MGT DUAL 123 MGTREFCLKO 101 MGT DUAL 101 MGTREFCLKO 101 B
10. interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules It provides additional information on pin capabilities pin character istics and PCB routing Additionally Pins provides a tool for generating constraint files for place and route tools Pins can be found at the URL below http www opalkelly com pins JP2 is an 80 pin high density connector providing access to FPGA Banks 0 and 1 Several pins 45 47 53 55 58 60 77 and 79 of this connector are wired to global clock inputs on the FPGA and can therefore be used as inputs to the global clock network Pin mappings for JP2 are available on the XEM6310MT product page on our website For each pin the corresponding board connection is listed For pins connected to the FPGA the corre sponding FPGA pin number is also shown Finally for pins routed to differential pair I Os on the FPGA the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs JP3 is an 80 pin high density connector providing access to FPGA Bank 1 Several pins 2 A 21 23 25 27 42 and 44 of this connector are wired to global clock inputs on the FPGA and can therefore be used as inputs to the global clock network Pin JP3 71 is connected to the Vrer pins of Bank 1 Pin mappings for JP2 are available on the XEM6310MT product page on our website For each pin the corresponding board connection is listed For
11. pins connected to the FPGA the corre sponding FPGA pin number is also shown Finally for pins routed to differential pair I Os on the FPGA the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs JP1 Transceiver Access Access to four high speed serial transceivers pairs 4 Rx and 4 Tx corresponding to GTP tiles 101 and 123 on the FPGA are available on the JP1 REFCLKO and REFCLK1 of tile 123 as well as REFCLK1 of tile 101 are also routed to JP1 REFCLKO of tile 101 is connected to a low jitter 100 MHz LVDS oscillator AC Coupling 0 1uF AC coupling capacitors are installed between JP1 and the FPGA for all REFCLK signals AC coupling capacitors are also installed for all GTP receive pairs www opalkelly com XEM6310MT Users Manual AC coupling capacitors are not installed for any of the GTP transmit pairs If AC coupling is de sired or required for the serial application they should be installed on the expansion side of JP1 your board Setting I O Voltages The Spartan 6 FPGA allows users to set I O bank voltages in order to support several different I O signalling standards This functionality is supported by the XEM6310MT by allowing the user to connect independent supplies to the FRGA VCCO pins on two of the FPGA banks By default ferrite beads have been installed that attach each VCCO bank to the 3 3VDD supply If you intend to supply power to a particular UO b
12. 64 M20 7 873 N15 1 033 M16 L17 117 HG EF o o o o H22 H21 F22 St C22 C20 vecot 1 RFUSE LX150T only VREF Bank 1 3 3VDD 3 3VDD 77 3 3VDD 9 3 3VDD 3 DGND 5 022 7 Wo y2 13 u22 15 uo 17 2 19 2 21 N9 2 P20 25 M19 2 M20 2 N15 31 m6 3 t7 Fm 37 IT 3 16 177 43 Ko 45 117 47 JH 29 Ing 51 Ing 53 H22 55 In 57 22 CN CNN 61 22 63 20 65 Deco 69 71_ VREF Bank 1 73 33 75 33 30 77 333 79 33 300 N JP3 Pin Connection FPGA Pin L20 L43P GCLK5 1 beo DGND L50N_1 N Say L 5 C 0 O AIN Oo O gt O Oo O NI OOO INI ICO O 1 O N O O O IN IO 212121 N N gt gt gt gt S N SIS 4101010 A 4 4 en g ol u N K O N LX150T only www opalkelly com Length mm L43N_GCLK4_1 33 930 35 043 20 673 21 939 21 910 23 003 21 951 23 216 21 175 23 443 31 702 9 176 8 876 9 112 5 923 25 432 26 532 6 538 N N N FPGA Pin 21 XEM6310MT Users Manual XAEM6310MT Quick Reference JP2 Length Pin Connection FPGA Pin mm H a jp AN See j s vxo f 7 faso Sid o faso o mua f j m eso SiS is fesa oo feo Pa 51957 FEN pp E E AA 28 JP2 Length Pin Connection FPGA Pin mm
13. FlashRead Please refer to the FrontPanel User s Manual and the FrontPanel API Reference for information about applying these methods Layout The Numonyx N25Q128A11B1240E is a 16 MiB Flash memory arranged into 256 64 kiB sectors Each sector contains 256 256 byte pages Sectors 0 15 are reserved for device firmware and settings and are not accessible to user software The remaining 15 MiB may be erased written and read using the FrontPanel API at any time even without a valid FPGA configuration Full 64 kiB sectors must be erased at a time However contents may be read or written on any page address boundary Loading a Power On FPGA Configuration The user area in System Flash may be used to store a Xilinx bitfile to configure the FPGA at power on Power on configuration takes approximately 6 10 seconds from when power is ap plied A full Reset Profile may also be performed after configuration The API is used to erase and program the power on bitfile and the Flashloader sample is pro vided to perform these steps from a simple command line utility Source code to the Flashloader sample is included with the FrontPanel SDK Called with a single argument the filename for a valid Xilinx bitfile the Flashloader sample will erase the first sectors in the System Flash user area then write the bitfile It will also setup the Boot Reset Profile to point to this area on power on No Power On Configuration Called with no arguments the Fl
14. In and User Lead Out R LEDs sections allow you to add custom pay SE e e as loads your own constraints that will be a added to the exported constraints file Additional timing constraints or com ments can be added here User Lead Out Add payload www opalkelly com 23 XEM6310MT User s Manual PCB Version History 20130814 First production PCB 24 www opalkelly com 4 57 1 749 3 28 60 00 1 61 48 00 44 00 24 08 17 66 11 23 2 33 60 00 57 00 55 00 30 00 5 00 3 00 ciel XEM6310MT Users Manual XEM6310MT Mechanical Drawing 5
15. PGA Configuration User Guide UG380 for more details Alternatively VBATT may be provided through JP3 80 In this case BT1 should not be installed The applicable schematic section and components required to support this functionality are shown below RefDes Manufacturer Manufacturer P N Seiko Instruments MS412FE FL26E 3V 1mAh lithium battery BAS40 04 TP Schottky Diode SOT23 C118 0 1 uF SM 0402 Decoupling R5 R6 4 7 kO 5 SM 0402 0 Q SM 0402 Connects VBarr to JP3 80 D10 _ R5 BAS40 04 TP 47k NoLoad S NoLoad R6 VBATT 47k 5 NoLoad DGND BTl MS412FE FL26E NoLoad DGND Non Volatile Encryption Key Storage eFUSE Non volatile storage of the encryption key is also possible by programming the Spartan 6 eFUSE via JTAG Please see the Xilinx Spartan 6 FPGA Configuration User Guide UG380 for more details To program the eFUSE you must first install the components listed in the table below You must also provide an external resistor RFUSE between JP3 69 and GND The value of this resistor is specified in the Xilinx Spartan 6 Datasheet DS162 between 1129 0 and 1151 RefDes Manufacturer Manufacturer P N 0 1 UF SM 0402 Decoupling R9 o Geeic 0 Q SM 0402 Connects FPGA Vrs to 3 3v www opalkelly com 17 XEM6310MT Users Manual RefDes Manufacturer Manufacturer P N 0 Q SM 0402 Connects FPGA Rrusz to JP3 69 Expansion Connectors 18 JP2 JP3 Opal Kelly Pins is an
16. RK6310MT Breakout Board 20 The BRK6310MT Breakout Board provides convenient access to signals on the XEM6310MT s high density connectors in prototype situations The PCB is designed as a 4 layer impedance controlled board to reduce losses on the transceiver signals which may be accessed via 22 SMA connectors Please visit the Pins reference for the XEM6310MT for pin mapping details Schematics and layout files for the BRK6310MT are available for download from the Opal Kelly website Connections JP2 on the XEM6310MT is pinned out to two 2 mm headers JP2A and JP2B JP3 on the XEM6310MT is pinned out to two 2 mm headers JP3A and JP3B JP1 on the XEM6310MT is the high frequency transceiver connector Each transceiver pair connects to two SMA connectors that are appropriately labeled Connectors marked with a are wired to the P terminal on the transceiver pair Connectors marked with a are wired to www opalkelly com Pins XEM6310MT Users Manual the N terminal on the trnasceiver pair Note that termination resistors are not present on the BRK6310MT Please see the transceiver information earlier in this document for details on the termination resistors on the XEM6310MT Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules It provides additional information on pin capabilities pin character istics and PCB routing Additionally Pins provides a tool
17. ank you MUST remove the appropriate ferrite beads Power can then be supplied through the expansion connectors The table below lists details for user supplied 1 bank voltages UO Bank Ferrite Bead 3P365 67 Considerations for Differential Signals The XEM6310MT PCB layout and routing has been designed with several applications in mind including applications requiring the use of differential LVDS pairs Please refer to the Xilinx Spartan 6 datasheet for details on using differential I O standards with the Spartan 6 FPGA Note LVDS output on the Spartan 6 is restricted to banks 0 and 2 LVDS input is available on all banks For more information please refer to the Spartan 6 FPGA SelectlO Resources User Guide from Xilinx FPGA I O Bank Voltages In order to use differential I O standards with the Spartan 6 you must set the VCCO voltages for the appropriate banks to 2 5v according to the Xilinx Spartan 6 datasheet Please see the sec tion above entitled Setting I O Voltages for details Characteristic Impedance The characteristic impedance of all routes from the FPGA to the expansion connector is approxi mately 50 Q Differential Pair Lengths In many cases it is desirable that the route lengths of a differential pair be matched within some specification Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible We have also
18. ashloader sample will clear the existing Boot Reset Profile This has the effect of preventing an FPGA configuration from being loaded at power on This func tionality may also be accomplished from the API by setting an empty okTFPGAResetProfile using the API SetFPGAResetProfile See the FrontPanel API Reference for details FPGA Flash 14 The SPI Flash attached to the FPGA is a Numonyx N25Q128A11B1240E or equivalent It pro vides non volatile storage for use by the FPGA It may not be used for FPGA configuration stor age The System Fash is used to store FPGA boot configurations The Flash FPGA pin mappings are shown in the table below Flash Pin FPGA Pin www opalkelly com LEDs XEM6310MT Users Manual There are eight LEDs on the XEM6310MT in addition to the power LED Each is wired directly to the FPGA according to the pin mapping tables at the end of this document The LED anodes are connected to a pull up resistor to 3 3VDD and the cathodes wired directly to the FPGA on Bank 2 with a bank I O voltage of 1 8v To turn ON an LED the FPGA pin should be brought low To turn OFF an LED the FPGA pin should be at logic 1 DDR2 SDRAM The Micron DDR2 SDRAM is connected exclusively to the 1 8 v I O on Bank 3 of the FPGA The tables below list these connections e Clock Configuration Source Synchronous D 2 w m p m The DDR2 clocking is designed to be source
19. er Mated Height QTE 040 01 F D A 5 00mm 0 198 QTE 040 02 F D A 8 00mm 0 316 One high density 40 pin expansion connector also provides access to the transceiver signals on two GTP DUAL transceiver tiles on the FRGA This connector is Samtec part number QSE 040 01 H D A The table below lists the appropriate Samtec mating connectors along with the total mated height Samtec Part Number Mated Height QTE 020 01 F D A 5 00mm 0 198 QTE 020 02 F D A 8 00mm 0 3167 FrontPanel Support The XEM6310MT is fully supported by Opal Kelly s FrontPanel Application FrontPanel aug ments the limited peripheral support with a host of PC based virtual instruments such as LEDs hex displays pushbuttons toggle buttons and so on Essentially this makes your PC a recon figurable I O board and adds tremendous value to the XEM6310MT as an experimentation or prototyping system Programmer s Interface In addition to complete support within FrontPanel the XEM6310MT is also fully supported by the FrontPanel SDK a powerful C class library available to Windows Mac OS X QNX and Linux programmers allowing you to easily interface your own software to the XEM In addition to the C library wrappers have been written for C Java and Python making the API available under those languages as well Sample wrappers unsupported are also provided for Matlab and LabVIEW www opalkelly com 116310117 User s Manual Comple
20. ficiency they are very compact and consume a small amount of PCB area for the current they can provide If you plan to put the module in an enclosure be sure to consider heat dissipation in your design Host Interface There are 41 signals that connect the on board USB microcontroller to the FPGA These signals comprise the host interface on the FPGA and are used for configuration downloads After con figuration these signals are used to allow FrontPanel communication with the FPGA If the FrontPanel okHost module is instantiated in your design you must map the interface pins to specific pin locations using Xilinx LOC constraints This may be done using the Xilinx constraints editor or specifying the constraints manually in a text file Please see the sample projects includ ed with your FrontPanel installation for examples Reset Profile RESET Pin AB14 of the FPGA is an active high RESET signal from the host interface This signal is as serted when configuration download begins and is deasserted during the execution of the Reset Profile For more information on the timing of this deassertion event see the FrontPanel User s Manual www opalkelly com 13 XEM6310MT Users Manual System Flash The Flash memory attached to the USB microcontroller stores device firmware and settings as well as user data that is accessible via the FrontPanel API The API includes three methods for accessing this memory FlashEraseSector FlashWrite and
21. hms default DCI for DQ DQS CHECKED DCI for address control CHECKED ZIO pin W4 RZQ pin R7 Calibrated Input Selection Yes Class for address control Class Debug signals Your option System clock Differential The JTAG connections on the FPGA are wired directly to the expansion connector JP3 on the XEM6310MT to facilitate FPGA configuration and ChipScope usage using a Xilinx JTAG cable The BRK6310MT has these signals connected to a 2 mm header compatible with the Xilinx JTAG cable Key Memory Storage LX150T only 16 The Spartan 6 FPGA supports design security using AES decryption logic and provides two methods for encryption key memory storage The first is a volatile memory storage supported by an external battery backup supply voltage VBaTT The second is a one time programmable eFUSE The XEM6310MT design supports both types of key storage with user modification required For quantity purchases of 50 or more units please contact Opal Kelly sales opalkelly com to discuss factory installation of these components www opalkelly com XEM6310MT Users Manual Volatile Encryption Key Storage VBATT A small lithium rechargeable battery and three support components can be installed to provide VBATT to the FPGA when the XEM is unpowered This will preserve the contents of the FPGA volatile key storage so long as VBATT remains over the threshold specified in the Spartan 6 docu mentation Please see the Xilinx Spartan 6 F
22. l Block Diagram FPGA Host Interface System Flash FPGA Flash DDR2 SDRAM 16 MiB 16 MiB 128 MiB USB 3 0 8 LEDs Spartan 6 FPGA XC6SLX45T 2FGG484 or Samtec Expansion D XC6SLX1 501 2 FGG484 41x pairs Connector JP1 100 MHz 4 Rx pairs Clock x2 Samtec Expansion Connector JP2 Samtec Expansion Connector JP3 The XEM6310MT is available in two variants These two variants are identical except for the FPGA provided The table below lists some of the differences between the two devices Consult the Xilinx documentation for a more thorough comparison Note that the LX150T variant is lim ited availability and may have minimum order requirements and lead times Please contact Opal Kelly Sales for more information Feature XEMG310MT LX45T XEM6340MT LX150T_ _ Clock Management Ties 4 07 www opalkelly com XEM6310MT Users Manual Power Supply The XEM6310MT is designed to be operated from a 5 volt power source supplied through the DC power points on the device or the expansion connectors on the bottom of the device This provides power for the three high efficiency switching regulators on board to provide 3 3v 1 8v and 1 2v Each of the three switching regulators can provide up to 2A of current DC Power Points In most applications VDC 4 5 to 5 5 will be delivered to the module from the expansion con nector However DC power points are also provided at the northwest corner of the device fr
23. m with four mounting holes M2 metric screws spaced as shown in the figure These mounting holes are electrically isolated from all signals on the XEM6310MT The USB connector overhangs the PCB by approximately 1mm in order to accommodate mounting within an enclo sure The XEM6310MT has two high density 80 pin connectors and one high density 40 pin connec tor on the bottom side which provide access to many FPGA pins transceivers power and JTAG BRK6310MT Breakout Board A simple breakout board the BRK6310MT is provided as an optional accessory to the XEM 6310MT This breakout board provides DC power JTAG connector and easy access to the high density connectors on the XEM6310MT by routing them to lower density 2mm spaced thru holes Additionally 22 SMA connectors provide access ot the FPGA transceiver tiles The www opalkelly com 5 XEM6310MT Users Manual breakout board also provides a convenient reference for building boards that will mate to the XEM6310MT Opal Kelly reserves the right to change the form factor and possibly pinout of the BRK6310 Therefore unlike the XEM6310MT it is not intended or recommended for production integration Full schematics and Gerber artwork files for the BRK6310MT are provided free of charge If your application depends on the existing form factor you may reproduce this board from these docu ments A mechanical drawing of the BRK6310MT is also shown at the end of this document Functiona
24. nd expansion capabili ties of the module 22 www opalkelly com XEM6310MT Users Manual L38P_0 25 099 0 1728 63 SDATA pix_sdata IOSTANDARD LVCMOS33 L37P_GCLK130 20 996 0 JP2B 64 NCMOS33 L38N_VREF_0 22 706 0 JP2B 65 SE VCMOS33 L37N_GCLK12_0 20 055 0 JP2B 66 1 533 L51P_0 25 362 0 1728 67 pix_reset x 1 533 L50P_0 21 102 0 JP2B 68 wa x CM0S33 L51N_0 23 293 0 JP2B 69 RESET pix_reset IOSTANDARD LVCMOS33 L50N_0 19 964 0 JP2B 70 PIX6 pix_data 6 IOSTANDARD LVCMOS33 Specifying Net Names The Pin List view for a Peripheral includes three additional editable columns e Design Net The name of the signal as it appears in your top level HDL e Constraints Text that is inserted into the constraints file for that signal Comment Additional comment text that is added to the constraints file These additional data are merged with the default Pin List constraints file prior to export The re sult is a constraints file complete with net names that can be used with your FPGA development flow Export Features Constraint file template Default Enable the specific module features you would like to appear in the exported con GO straints file When a feature is enabled Pins will export the constraints appropri Export features vd Lead in ate to that feature such as pin locations FrontPanel When a feature is disabled Pins will skip G s n that portion System Clock Reset d dd load The User Lead
25. om the perspective shown on the mechanical drawing These are small vias that can be used to deliver power to the module SuperSpeed USB 3 0 Interface The XEM6310MT uses a Cypress FX3 USB microcontroller to make the XEM a USB 3 0 periph eral AS a USB peripheral the XEM is instantly recognized as a plug and play peripheral on mil lions of PCs More importantly FPGA downloads to the XEM happen quickly virtual instruments under FrontPanel update quickly and data transfers are blazingly fast On board Peripherals The XEM6310MT is designed to compactly support a large number of applications with a small number of on board peripherals These peripherals are listed below Low Jitter Oscillator FPGA Fabric A fixed frequency 100 MHz low jitter oscillator is included on board and outputs LVDS to the FPGA The Spartan 6 FPGA can produce a wide range of clock frequencies using the on chip DCM and PLL capabilities Low Jitter Oscillator FPGA GTP Transceivers A second dedicated 100 MHz low jitter oscillator is also provided and is connected at MGTREF CLKO_ 101 128 MByte Word Wide DDR2 Synchronous DRAM The module includes a 128 MiByte DDR2 SDRAM with a full 16 bit word wide interface to the FPGA This SDRAM is attached exclusively to the FPGA and does not share any pins with the expansion connector The maximum clock rate of the SDRAM is 333 MHz With the 2 speed grade of the Spartan 6 the maximum clock rate is 312 5 MHz for a supp
26. orted peak memory bandwidth of 10 Gb s The DDR2 SDRAM is a Micron MT47H64M16HR 3 H or compatible FPGA Flash 16 MiB Serial Flash Memory A 128 Mib serial flash device Numonyx N25Q128A11B1240E or equivalent provides on board non volatile storage for the FPGA This device is attached directly to the FPGA for use in your design www opalkelly com XEM6310MT Users Manual system Flash 16 MiB Serial Flash Memory LEDs A 128 Mib serial flash device Numonyx N25Q128A11B1240E or equivalent provides on board non volatile storage accessible to the USB microcontroller This device is used to store device firmware and configuration settings as well as other user assets such as FPGA configuration files or calibration data Erase read and write functions are available at all times with or without a configured FPGA through the use of FrontPanel API methods Eight LEDs and are available for general use as indicators Expansion Connectors Two high density 80 pin expansion connectors are available on the bottom side of the XEM 63101 1 PCB These expansion connectors provide user access to several power rails on the XEM6310MT the JTAG interface on the FPGA and 122 exclusive I O pins on the FPGA includ ing several GCLK inputs The general purpose connectors on the XEM6310MT are Samtec part number QSE 040 01 H D A The table below lists the appropriate Samtec mating connectors along with the total mated height Samtec Part Numb
27. pation IMPORTANT 13 aia a a aaa ee 13 Reset Profile RESET 13 SSS nese KE wk hen Q saq 14 Tn ME 14 Loading a Power On FPGA Configuration 14 PEGA Flac SS ES aka S kaqka SE ane aes ST 14 EE SS a wawas a u eee eee eases ee 15 BIB PE NE 15 Clock Configuration Source Synchronous 15 Memory Controller Blocks 16 NS EE 16 AIT E EE pa bom w Qos ae SE 16 Key Memory Storage LX150T ont 16 Volatile Encryption Key Storage VBATT 17 Non Volatile Encryption Key Storage eFUSE 17 Expansion Connectors 18 OF aysana E SS 18 R EE 18 JP1 Transceiver Access 18 Setting I O Voltages 19 Considerations for Differential Signals 19 BERT Configuration 20 XEM6310MT User s Manual BRK6310MT Breakout Board 20 COMME CUONS v6 at ESS chunk Sod eee ku 20 i ee abdae dea I deen sees a sss 21 TOOD ce z
28. r approxima tions based on Xilinx power estimator results Shaded boxes represent unconnected rails to a particular component Empty boxes represent data that the user must provide based on power estimates The user may also need to adjust parameters we have already estimated such as FPGA Vcco values where appropriate The values provided below for MGT include four transceivers running at 2 5 Gb s muer ison me omw omw FPA jr EPGAV NT ETH FPGA Vecos DRA 2somw FPGA Voooe USB est mw J FPGAMGTAw omw FFAMSTAT lesen www opalkelly com XEM6310MT Users Manual Example FPGA Power Consumption LX150T XPower Estimator version 12 3 was used to compute the following power estimates for the Vc CINT supply These are simply estimates your design requirements may vary considerably The numbers below indicate approximately 70 to 80 utilization Logic LUT NS Tota EET able 2 400 mv Supply Heat Dissipation IMPORTANT Due to the limited area available on the small form factor of the XEM6310MT and the density of logic provided heat dissipation may be a concern This depends entirely on the end applica tion and cannot be predicted in advance by Opal Kelly Heat sinks may be required on any of the devices on the XEM6310MT Of primary focus should be the FPGA U6 and SDRAM U9 Although the switching supplies are high ef
29. s and no trademark rights to the same are claimed Revision History Date Description eee 20130620 Initial release 20130906 Update Quick Reference with VBaTT and Rruse connections and fixed incorrect mappings for JP2 pins 73 and 75 Contents Introducing the XEM6310MT 5 PCB ee l T aaa SEES ddd 5 BRK6310MT Breakout Board 5 Functional Block Diagram 6 4554664024 ko kaqmaqa i arsa g eg 6 Power Supply 7 DC Power Points 7 SuperSpeed USB 3 0 Interface _ 7 On board Peripherals 7 Low Jitter Oscillator FPGA Fabric 7 Low Jitter Oscillator FPGA GTP Transceivers 7 128 MByte Word Wide DDR2 Synchronous DRAM 7 FPGA Flash 16 MiB Serial Flash Memory 7 System Flash 16 MiB Serial Flash Memory 8 ED a AE EAE eae een a dee eas 8 Expansion Connectlors 8 FrontPanel Support 8 Programmer s Interface 8 Applying the XEM6310MT 11 Powering the XEM6310MT 11 Power Distribution System 11 Power Budget 12 Example FPGA Power Consumption LX150T 13 Supply Heat Dissi
30. synchronous from the FPGA This means that the FPGA sends the clock signal directly to the SDRAM along with control and data signals allowing very good synchronization between clock and data www opalkelly com 15 XEM6310MT Users Manual JTAG Memory Controller Blocks Spartan 6 has integrated memory control blocks to communicate with the external DDR2 mem ory on the XEM6310MT This is instantiated using the Xilinx Core Generator memory interface generator or MIG to create a suitable memory controller for your design You should read and become familiar with the DDR2 SDRAM datasheet as well as MIG and the core datasheet Al though MIG can save a tremendous amount of development time understanding all this informa tion is critical to building a working DDR2 memory interface The XEM6310MT provides 1 2v as Vccint According to the memory controller block documenta tion the Spartan 6 2 speed grade can operate memory to 312 5 MHz with this internal voltage MIG Settings The following are the settings used to generate the MIG core for our RAMTester sample using Xilinx Core Generator These settings were used with ISE 12 2 and MIG 2 3 Note that settings may be slightly different for different versions of ISE or MIG Frequency 312 5 MHz Memory Type Component Memory Part MT47H64M16XX 3 1Gb x16 Data Width 16 Enable DQS Enable CHECKED High temp self refresh DISABLED Output drive strength Reducedstrength RT T nominal 50 o
31. te documentation and several sample programs are installed with FrontPanel www opalkelly com 9 XEM6310MT User s Manual 10 www opalkelly com 116310117 User s Manual Applying the XEM6310MT Powering the XEM6310MT The XEM6310MT requires that this supply be clean filtered and within the range of 4 5v to 5 5v This supply must be delivered through the VDC pins on the two device s two expansion connec tors or the two pins near the northwest corner of the device Power Distribution System A diagram of the power distribution system on the XEM6310MT is shown below Details for ap plying this system follow throughout this document Note that some system supply outputs are unavailable to the user www opalkelly com 17 XEM6310MT Users Manual 12 Linear Supply Fei Switching Supply Jumper VDC VDC JP2 1 3 5 4 5 to 5 5v 3 3 JP2 11 13 15 3 3V 2A 3 3 JP3 73 5 77 79 System Controller FPGA Vccio U JN DUUN VCCOO JP2 2 4 DDR2 Termination a VCCO1 JP3 65 67 GTP Transceiver Core GTP Transceiver Termination 1 8v 2A 1 8 JP2 7 9 DDR2 Memory FPGA Vccio DDR2 1 2v 2A 1 2 JP2 6 8 System Controller FPGA Vccint Power Budget The table below can help you determine your power budget for each supply rail on the XEM 6310MT All values are highly dependent on the application speed usage and so on Entries we have made are based on typical values presented in component datasheets o
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