Errata to MPC8240 Integrated Processor User`s Manual, Rev. 1
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3. Freescale Semiconductor Document Number MPC8240UMAD Addendum Rev 1 2 3 2008 Errata to MPC8240 Integrated Processor User s Manual Rev 1 This errata describes corrections to the MPC8240 Integrated Processor User s Manual Revision 1 For convenience the section number and page number of the errata item in the reference manual are provided Items in bold are new since the last revision of this document To locate any published updates for this document visit our website listed on the back cover of this document AY N Freescale Semiconductor Inc 2008 All rights reserved 2 freescale semiconductor Section Page No 3 1 3 2 Changes In Table 3 1 Address Map B Processor View in Host Mode the PCI address range for the processor address range 8000_0000 through FDFF FFFF should read as follows 8000_0000 FDFF_FFFF 2G 4G 32M 1 8000_0000 FDFF_FFFF PCI memory space 4 8 2 4 38 4 10 4 43 Remove the unmarked figure that is above Table 4 33 Bit Settings for Error Enabling Register 2 ErrEnR2 0xC4 and below the introduction sentence for Table 4 33 In Table 4 38 Bit Settings for MCCR1 OxFO0 the description of bits 22 21 DBUS_SIZ 0 1 For FPM EDO systems only RAM_TYPE 1 should be on the same line with Ox 32 bit data bus The description should read as follows 00 32 bit data bus x1 8 bit da
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5. t States for ROM High Impedance Reads with Gather ane 1 2 Bits Reads with Wide Data Path in All Writes cand Reads with Gather Data Path Data Path Flow Through or 3 in In Line Buffer Mode 32 or 64 Bit Registered Buffer 8 16 32 Bit Mode 8 16 32 Bit s 000 2 clocks 5 clocks 6 clocks 001 2 clocks 5 clocks 6 clocks 010 3 clocks 5 clocks 6 clocks 011 4 clocks 5 clocks 6 clocks 100 5 clocks 6 clocks 7 clocks 101 6 clocks 7 clocks 8 clocks 110 7 clocks 7 clocks 7 clocks 111 8 clocks 9 clocks 10 clocks Notes aea ee 1 In this context Flash writes are defined as any write to RCSO or RCS1 2 For Flash writes add the write recovery time ROMNAL to the given wait states for ROM high impedance time 5 4 2 3 5 23 Replace information regarding AN1767 with AN2129 as follows Instruction and Data Cache Locking on the e300 Processor Core application note order number AN2129 Errata to MPC8240 Integrated Processor User s Manual Rev 1 Freescale Semiconductor How to Reach Us Home Page www freescale com Web Support http Awww freescale com support USA Europe or Locations Not Listed Freescale Semiconductor Inc Technical Information Center EL516 2100 East Elliot Road Tempe Arizona 85284 1 800 521 6274 or 1 480 768 2130 www freescale com support Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 4
6. ta bus 10 64 bit data bus 1x 64 bit data bus 22 21 DBUS_SIZ 0 1 XX Read only This field indicates the state of the ROM bank 0 data path width configuration signals DL 0 FOE at reset as follows For ROM Flash chip select 0 RCSO For ROM Flash chip select 1 RCS1 and S DRAM Ox 32 bit data bus For FPM EDO systems only RAM_TYPE 1 4 10 4 46 In Table 4 40 Bit Settings for MCCR3 OxF8 replace the Wait States for ROM High Impedance table in the description for bits 3 1 29 with the following Note the addition of rows for 011 and 110 Errata to MPC8240 Integrated Processor User s Manual Rev 1 Freescale Semiconductor Section Page No Changes Bits Name Reset Description Value 31 29 TS_WAIT_ 000 Transaction start wait states timer The minimum time allowed for ROM Flash Port X TIMER 0 2 devices to enter high impedance is two memory system clocks TS_WAIT_TIMER 0 2 adds wait states before the subsequent transaction starts in order to account for longer disable times of a ROM Flash Port X device This delay is enforced after all ROM and Flash accesses delaying the next memory access from starting for example DRAM after ROM access SDRAM after Flash access ROM after Flash access Note that this parameter is supported for SDRAM systems only For EDO FPM DRAM systems TS_WAIT_TIMER 0 2 must 000 Wai
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