Home

User`s Manual - Cru Power Oy

1. 80 3 4 CS FOR ZS INOA CO RTT 83 3 4 1 Modify Waveform Display MOde cccccceeccceceeeeeeeaeeeeeeseeeeeeseeeeeeseeeeeseaeeeeesaeeeesnaneeeesaes 84 34 2 eedem soeareae le 85 3 4 3 Modify Waveform Height amp Correlated Setting seeesseeseseeeseneenree 86 3 5 PEO SAN s a T 89 3 6 Solo dein NEM PIETROSN 90 3 6 1 Modify Workaround Color eeesssssssssssssseseseee nennen nennen nnne nnn nena nnns na nnns nna nnn 92 3 6 2 Modify Waveform Color ccccccccccsssececcessceccesceeceeececsaueeeseaeeecsageeeessaseeessaseeesegeeesssaeeneseas 93 3 7 The Flow Of Software OperallOFi ua codo tbt ino rh p pen ainai aa aaa adaa 94 introduc on to LOGIC ARlySISiusoisesatbeszua arb riu brad epus Cup aaiae Bia dui aara idaan a ai 95 4 1 EOOICUARSIVSIS acts tc pasts mp cate tate cnn ita oe on th peels er AU E end cera 96 4 2 sies lw T c 108 4 3 PUGANAI aeo T m 110 4 4 w rde c T K c Hm 113 4 5 BEDS ARIS VISCONTI E RT E 120 2C MEETS RON E E EE 121 Ta STI us RER n 124 AS UAISEABS SIS erinorm beasts ennte cou bacmtesdamnases Lessetut asstedibanciu R 130 2 0o dE Nic 135 FMO7IAA 2P BETIS RE 2 ARAS Th
2. Bus Signal Trigger Filter 62587 303 63447 552 64307 8 65168 0493 ecd 296 66888 547 67748 7968 68509 045 69469 294 70328 A0 SYNC x eet e Al 1 490 490 489 490 489 491 460 518 es os 980 9 a2 2 262144 w A3 A3 262144 d A4 Ad 262144 a5 45 LL 282348 g 6 56 ir NN gw a7 47 S e 262144 B0 5o X 262144 Bi 51 262144 B2 82 262144 B3 B3 262144 B4 B4 X e 262144 uL bis qus l xj STEP 4 Display the function of Multi stacked Logic Analyzer in the Channel Stack Tip There are two Logic Analyzers for Channel Stack the Synchronous Channel is AO the Synchronous Trigger Condition is the Rising Edge the former 32 channels A0 A7 BO B7 CO C7 DO D7 change into the 64 channels AO A7 BO B7 CO C7 DO D7 EO E7 FO F7 HO H7 l0 17 channels 186 FMO7IAA 2P BETIS BR 0 BPRS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 ixi File Bus Signal Trigger Run Stop Data Tools Window Help m laj xi ih oe 7 lR pb 128K site i 200MHz mw 50 ie 4 Page fi count fi zJ E ZEROPLUS LAP C 32128 Standard 3 11 CNO1 5 N 000000 0000 LaDoc1 R Ri 0v p 5e12272 R z 8e B Te t Bb le l l o Height Trigger Delay Scale 10ns Display Pos Ons A Pos 150ns Y A T 150ns v A B 300ns v Total 81 92us Display Range 250ns 280ns B Pos 150ns
3. ZEROPLUS Logic Analyzer 2 Slave Host a DSO is the Host LA is the Slave Connect the Trigger Out of DSO with the Trigger In of LA and the LA uses external trigger When DSO has been triggered it will inform LA to capture signal LAP B Series support b DSO is the Host LA is the Slave Connect the Trigger Out of DSO with any channel of LA users can define which occupies one channel When DSO has been triggered it will inform LA to capture signal LAP C series V3 11 higher version support 188 FMO7IAA 2P BE HS BR 0 3 ER 23 SI The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Computer Device Under Test V ZEROPLUS ZEROPLUS Logic Analyzer Operating Instructions STEP 1 Confirm the DSO is connected correctly STEP 2 Click the Tool on the Menu Bar than select DSO stacked Settings to open the dialogue box Customize Color Setting EUS Bus Property 7 Refresh Protocol 4nalyzer gu Multi stacked Logic Analyzer Settings Analog waveform D5O sbacked Settings 189 FM0714A PREP i BPR The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 STEP 3 Set the Channel V Div in the dialogue box DSO stacked Settings X Channel v Div Setting DSO CH1VvjDiv 2wvfDiv D5O CH wjDiv 2wvfDivy D5O CH3 VjDiv zvipie D5O CH4 WiDiv zvipiv Channel Setting only display O50 psa
4. Packet Name TimeStamp ADDRESS Read DATA D NACK DESCRIBE A ACK Fig 4 53 Waveform and Packet Synchronization Interface 119 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 Bus Analysis The setup is correlated to the Bus which needs to be made up for example Bus Protocol Analyzer Open the dialog box BUS STEP 1 Click Tools on the Menu Bar and then select Bus Property or select to set up Bus Property Customize Color Setting GEE Bus Property Refresh Protocal Analyzer gg Multi stacked Logic Analyzer Settings Analog waveform k D50 stacked Settings Fig4 54 Bus Property on Menu Bar Fig4 55 Bus Property on Tool Bar STEP 2 Click the Right Key on the Bus Signal column and then select Bus Property Tip The signals must be grouped into Bus or the Bus Property can not have effect Y Bas ws TIT wm Tie i Sampling Setup i Channels Setup za Bus Property Analog Waveform k O A3 Reverse sS A4 Group into Bus trl g a5 LIngraup Fram Bus Ctrl U A6 Add Channel AF Gopy Ghannel g B0 Delete channel vw E Delete All Channels or Re Restore Default Channels g B3 Format Row k PIT Rename Fig4 56 Right Key to Set Bus Property 120 FMO7IAA 2P BETIS AR ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 1 Bus Analysis The B
5. ZEROPLUS L CCIR656 MODULE V1 31 00 CN01 Bi Bi e ZEROPLUS LA Compact Flash 4 1 MODULE V1 01 00 CNO1 gt A TTD EMT A RAN TRA BASDI dt 00 Ome oR B2 52 e IV Use the DsDp Find B3 B3 More Protocol Analyzer B4 B4 Cancel Help e Ee en Eg 87 57 9 g co o m j AIK J Ready End DEMO h Fig4 132 CAN 2 0B Bus Property Setup Double click the ZEROPLUS LA CAN 2 0B MODULE V1 32 00 CN01 to set the Protocol Analyzer CAN 2 0B dialog box PROTOCOL ANALYZER CAN 2 06 x Configuration Packet Data Format Register Pin Assignment Start Packet Format Protocol Analyzer Mame Bus 111Bit Start Hoe ae e Protocol Analyzer Property Data Reverse Decoding Percentage Sample BU After End Packet happens just begin to analyze Baud Fate 125000 Auto C When CAN Data for expansion combine Basic ID and ID Min 1bps Max 10Mb Min Tbps Mas ps v The Del is displayd in the CRC Field Protocol Analyzer Color Stark Control Error CRAC End ID Data Overload Cancel Default Help Fig4 133 Protocol Analyzer CAN 2 0B Setup 164 FMO7IAA 2P BET AR ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Click OK in the Protocol Analyzer CAN 2 0B dialog box to complete the CAN 2 0B Setting We ZEROPLUS LAP C 32128 Standard 3 11 CHO1 S 000000 0000 CAH2 0B So File Bus Signal Trigger Run
6. 2P BETIS BR 03 ER 23 8j The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 message data can be separated into Start of Frame SOB Arbitration Field Control Field Data Field CRC Field Ack Field End of Frame EN 0 A 8 Data Field fad Ign A3 ERES aaa eae Sennen A EHH He o3 ppm e eee in MEA A i AEA a ET Pcl Ka gu psp ent ale Fe ins si ost nd ats ql 1 Fig4 120 Basic Data Frame Start of Frame Every Start of Frame must be 0 which means asking far data to come back Arbitration Field Identifier is 11bits its function is the sequence when transmitting signal numerical value is lower the priority is higher and the array is from ID 10 to ID 0 and the numerical value is not all from ID 10 to ID 4 finally RTR Remote Transmit Request is the judgment bit of transmission or Remote Transmit Request When RTR 0 it denotes that the data goes out when RTR 1 it means asking far data to come back Control Field Control Field consists of 6 bytes including Data Length Code and two Reserved Bits as Peli frame for future expansion The transmission reserved bit must be 0 Receiver receives all bits combining 1 with O As the below figure IDE and RBO of Control Field are Reserved Bits which must be 0 and the latter 4bits are only 0 8 which denotes the data behind will transmit several bytes data Fig4 121 Control Field Data Field The Data Field consists of the data
7. A Statistics o Fig 3 122 Waveform Find Dialog Box of the I2C Signal Waveform Find x Waveform Find l x Activate the function of Chain Data Find Activate the function of Chain Data Find Busisianal Mame E ignaLName rc hi Next Previous close Busz X Next Previous Close Min Value Max Value Bus Item Find Min Value Max Value uu ee fr When Found Uninow When Found Start Data A b Odd Part y Statistics Statistics Statistics Statistics RN Fig 3 123 Waveform Find Dialog Box of the Protocol Analyzer UART x x Activate the Function of Chain Data Find Activate the Function of Chain Data Find Bus Signal Name AAEE Next Previous Close v Next Previous Close Min Value Max Value ind Min Value Max Value D is La When Found Statistics Start At al Statistics la Statistics Ds i Statistics NN NN Fig 3 124 Waveform Find Dialog Box of the UART Signal TT x Activate the Function of Chain Data Find Activate the Function of Chain Data Find as Siora t ame E ignal Name usi Next Previous Close Next Previous Close Pusl C d Min Value Max Value Bus Item Find Min Value Max Value m oooco000000 F A3 When Found Statistics d At When Found Statistics A4 TRES pul A Statistics A Statistics A6 o o A7 Wavef
8. E TE tho sta ot Lun nar t HORTA i Time Format Settings Cancel Default Help Fig 4 69 Protocol Analyzer I2C Timing dialog box Waveform Image Describe the position of the set time Time Format Settings When the Time Settings is activated the set time will become the condition of judging decoding For example when you want to decode START you should judge whether the conditions of START are satisfied firstly and then judge whether the set time of tHD STA is coincident with the factual waveform If the two conditions are satisfied the START can be decoded Other segments decoding of the packet is the same with that of the START 127 FMO7IAA O 2P BETIS AR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 2 3 Protocol Analyzer I2C Packet Analysis xl Configuration Timing Facket Data Format Register Item Color Item Color m ieia H ANACK E Read EN V D ACK B Write EN V D NAEK so M Data EN v Describe mE IV A ACK EMO 4 RegAddr E Cancel Default Help Fig4 70 Protocol Analyzer I2C Packet dialog box In the Packet dialog box users can select the set item to be displayed and the color of item It is a Bus Packet List view which includes 4 formats which I2C happens as follows H Setting Refresh Expert Synch Parameber Packet Name Timestamp ADDRESS Write LT CATA ESRC CaTa DRAGER DAT
9. This Unknow register is Unknow End Flag 4 5 2 4 Protocol Analyzer I2C Data Format Analysis x Configuration Timing Facket Data Format Register Data Binary C Decimal Hexadecimal C ASCII Slave Addr Binary Decima Hexadecimal ASCII Reg Addr Binary Decimal Hexadecimal ASCII Cancel Default Help Fig4 73 Protocol Analyzer I2C Data Format dialog box Users can set the Data Format of the Data Slave Addr and Reg Addr as their requirements When selecting the option Activate the data formats are decided by the settings in the Protocol Analyzer when not selecting the option Activate the data formats are decided by the settings in the main program 129 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 3 UART Analysis UART Introduction The UART which stands for Universal Asynchronous Receiver Transmitter is a serial asynchronous protocol The UART is often time integrated into PC communication devices and it usually equips an EEPROM Electronic Erasable Programmable Read Only Memory for error checking proposes with other chips There are two concepts about UART which must be understood before performing any further tasks The UART protocol will first translate a parallel data into serial data for the UART requiring only one wire to transmit signals The transmission starts at a triggered Low position and there are 7 or
10. Tip Click icon to view all data and then select the waveform analysis tools to analyze the waveforms Step5 Click the compression icon again or click off the compression function to stop compression Tip Compression cannot be applied with the signal filter function at the same time 168 FMO7IAA O 7P BE TFS AR 00 BBR ul The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 7 Signal Filter and Filter Delay The function of the Signal Filter and Filter Delay allow the system to keep the required waveform and filter out the waveforms that aren t required 4 7 1 Basic Setup of Signal Filter and Filter Delay Software Basic Setup of Signal Filter and Filter Delay Step1 Set up RAM Size Frequency Trigger Level and Trigger Position as described in Section 4 1 Step2 Set up the trigger edge on the signal or the Bus to be triggered Step3 Click icon or click the Signal Filter Setup button on the Sampling Setup dialog box or select the item form the pull down menu of the Bus Signal and then the Signal Filter Setup dialog box will appear Tue nea na ee x Bust rud or Iz NR x Cox Source EA Sampling Setup Argrchroreus iei Bus Signal Trigger Run Stop Data 7t Channek Sehm f intemal Codd Sig iy Setup Frequency iore Wl Sampling Setup ug Signal Filter Setup wu Channels Setup XE BETER a i Group into Bus Crs Shee Ce ki Signal Filter Setup SUME TR
11. A few users have reported similar problems We are not certain what causes it or how to fix it However we have found that if there is a defective address within 128 MB to 512 MB in your physical memory your software might signal End of memory Thus the program will warn you about insufficient memory Test your memory with a varied memory testing program Or take a screenshot close the program paste it to the graphing program and re open the program A part of the background picture remains within the Waveform Display Area especially when running the program in demo mode What s wrong with it Your machine may have a memory management problem with either your physical RAM onboard or the RAM on your video card Turn off any other multimedia of graphic programs and then re run the software If this does not work restart your system This should temporarily fix the problem However we highly recommend terminating all irrelevant programs while working with the Logic Analyzer Try not to burn DVDs not listen to music or watch movies while working with the Logic Analyzer The default color setting of the Waveform Display Area is very cool but don t see anything when print my work out with my black and white laser printer What can I do Refer to Section 3 6 it should have clear understandable instructions about changing the color of the user interface See Fig 3 153 this color setting should give a clear view of the Wavefor
12. 7 J Oo j 1 j Packet Name Timestamp Data Data Data Data Data Data Data Data Data Data Length L2 3 4 s 6 7 I O 1 2 3 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length L4 s 6 7 o 1 2 3s 4 j 5 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length A J ed a te Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Length Co a tes fs ts fe 7 ofa Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length 6 jBuiBu 973 2 3 4 5 6 7 o i 2 3 jJ 100ms __ Fig4 49 Bus Packet List Tip The Protocol Analyzer Packet will be explained in the following plug 5 Packet and Waveform Synchronization For the convenience of fast corresponding between packet data and waveform data and what is more in order to make it easier for users to look up data we add the Packet and Waveform Synchronization function In order to operate conveniently we add a Synch Parameter button on the BUS Packet List as the image below 117 FMO7IAA O 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 nt Setting Refresh Export Packet Name TitmieS ii up E piss i Pees Pesos Pees Pens bem E o 1 2 3 j 4 5 6 7 j O 1 jJ Packet Name TimeStamp Data Data Data Data Data Data
13. Ltd User s Manual V3 11 Setting Lu Export Synch Parameter x acke acket Name TimeStamp ADDRESS Write 4 ACK DATA c c DATA o o DATA c co DATA c DATA y 50 Write A ACK OO D ACK 75 D ACK O1 D ACK 23 D ACK 45 D ACK DATA IDAK Packet Name TimeStamp Packet Name TimeStamp Packet Name Timestamp TE Busl I2C 10 3554ms ADDRESS Write A ACK DATA DRACK DATA LD ACK S0 Write A ACK DO D ACK 75 D ACK ADDRESS Read 4 ACK DATA DENACK DESCRIBE S0 Read A ACK O1 D NACK DATA NACK ADDRESS Read A4 ACK DATA DRACK DATA DBSACKO DATA DNACK DESCRIBE 50 Read A ACK 23 D ACK 45 D ACK 67 D NACK DATA NACK acket Name TimeStamp ADDRESS Write 4 ACK DATA 0o DATA 0 DATA 0 0 DATA E DATA DEACK PS P hung 20 4778 SO Write A ACK OO D ACK 79 D ACK 89 D ACK AB D ACK CD D ACK DATA D amp ACK al Fig4 42 Protocol Analyzer I2C Packet List Setting It is used to open Packet List Setting dialog box Refresh Press this button the list view can renew automatically Export Export the workspace into Text txt and CSV Files csv Synch Parameter Open the synch parameter setting dialog box and activate the packet and waveform synch function 2 Display Protocol Analyzer Packet in Order Tip The below view are Protocol Analyzer I2C the packet is determined by the position of the TimeStamp
14. The document includes the version information ofthe software s Detailed description invites reference company website Copyright C 1997 2011 ZEROPLUS TECHNOLOGY CO LTD Website Atos Swi zeroplus com tw Fig 6 4 The circled information is the version number SW10 How may I upgrade my software interface program A Visit our website at http www zeroplus com tw and follow the instructions for the English version You may also use the following address for English updates http www zeroplus com tw logic analyzer en technical support php SW11 Can I save my signal data to a separate pure text file txt A This feature is available in this version SW12 Why is the text display covered by other text or outside the display width A At this stage our software interface program has missing code for multilingual support You will have to ensure your system default encoding is one of the following languages 1 any English Encoding en en XX 2 Traditional Chinese zh zh XX 3 Simplified Chinese zh zh CN in HZ GB2312 GB18030 Double check the language configuration in Regional and Language Options a QuickTime Regional and Language Options EE Documents gt MEL Outlook VisualBoy E Settings control Panel C EET ae Customize settings for the display of languages J2 Search CJ Windows Security CA Schedinumbers times and dates Network Connections gt
15. Ts 85ERLLA m Sore AFes 04 9 A fet Pa o NP IL PPE See SE FUNP Se See FUR E s L E jux zj ere scm ft zf 32 SEEDLA mu R2 Tigger Oeiay 59 A fe e Tet e A petete e Comp P ate New Fig3 109 Reverse Function Displayed in the Waveform Window FM0714A 73 Phe AR AR BR Zeroplus Technology Co Ltd Add Channel Copy Channel Delete Channel Delete All Channels Restore Default Channels The Zeroplus Logic Analyzer User s Manual V3 11 Add Channel X Channel fao Cancel Fig 3 110 Add the required channel in the Bus Signal column ZEROPLUS Logic Analyzer X AN Do you want to copy the channel i Cancel Fig 3 111 Copy the selected channel in Bus Signal column ZEROPLUS Logic Analyzer EE xj AN Do you want to delete the channel i Cancel Fig3 112 Delete the selected channel in Bus Signal column ZEROPLUS Logic Analyzer X AN All the Buses and channels will be deleted Da you want bo continue i Cancel Fig 3 113 Delete all Buses and channels in Bus Signal column ZEROPLUS Logic Analyzer xj A All the Buses and channels will restore to the default Do you want to continue E Cancel Fig3 114 Restore the deleted Buses and channels in Bus Signal Column FM0714A Phe AR AR 2 ARAS Zeroplus Technology Co Ltd Right Key Menu on the Waveform Area Tip
16. g B t Delete All Ghannels or B3 E Restore Default channels was As A6 AE armat Row a g B4 E Format R r B5 Rename aA aA Fig4 65 Group into Bus Step4 Select Bus 1 then press Right Key on the mouse to list the menu Next click Bus Property or click Tools and the select Bus Property or click to open Bus Property dialog box Bus Signal ue pne NT I I og d Eres rne m v Busi Em ii Sampling Setup e t wy Channels Setup ea EI Bus Property g a3 A3 Analog waveform g az a2 Reverse Ad a4 Group into Bus Ghi G was 45 Ungroup From Bus Ctrl U a6 46 Add Channel ar af Copy Channel g BO 50 Delete channel g El Bl Delete All Channels g B E Restore Default Channels g BS B3 Format Row F Ba B4 Rename Fig4 66 Step5 For Protocol Analyzer Setting select Protocol Analyzer Then choose ZEROPLUS LA I2C MODULE r Bus Setting Bus Color Config AQ Activate the Latch Function Yv Rising Edge r Protocol Analyzer Setting Protocol Analyzer Parameters Gontig s C ZEROPLUS LA 1 WIRE MODULE V1 10 00 CNO01 C ZEROPLUS LA 3 WIRE MODULE V1 04 00 CNO1 C ZEROPLUS LA AC97 MODULE V1 02 00 CNO1 ZEROPLUS L ARITHMETICAL LOGIC MODULE V1 51 00 CNO1 ZEROPLUS LA BUS MODULE v1 00 00 CNO1 C ZEROPLUS L CAN 2 068 MODULE v1 32 00 CN01 ZEROPLUS LA CCIR656 MODULE V1 31 00 CNO01 C ZEROPLUS L Compact Flash 4 1 MOD
17. 15us v iA oe Sh ISi v Total 20 48us Display Range 10 228032us B Pos 150ns v B T 150ns v aay 10 210826us 10 135613us 10 180413u 10 165206us Leos 10 134794u2710 113 Sgi 2 v eens ns nes ono ne arie JOroo Oros AOX Bus Signal Tave FAN xjhs Activate the function of Chain Data Find DIJ lial Name Previous Close was As Max Value wg 7 A Start At en Found Statistics BO B0 s zl Statistics g Bl b Address 1015 lea B2 2 De 24 na na KA sa Fig 3 128 The A Bar is placed at the 0X08 of Bus1 where the condition of the Waveform Find is set The Statistic of Waveform Find shows a 64 Scale 2 3576ns Display Pos 9 9Tus Pos 9 9Tus Y T 9 9Tus v Total 20 48us Display Range 10 02894us B Pos 150ns v B T 150ns v n mer e Bus Signal 710 017152us 10 005364us 3 3335T6us 73 981 T68us set in 358212us 3 346424u lOns 10ns lOns 10ns 10ns 10ns a 10ns ims 20 Taveform Find E B xi 20r E Activate the Function of Chain Data Find e A3 A3 ian h mue 644 A4 Previous Close 45 45 Bus Item Find Min Value Max Value y A7 47 Start At End at When Found Statistics g BD 5o Ds po F Statistics Bl Address 997 lea B2 B2 20 48us f AA m Fig 3 129 The A Bar is placed at the OX1A of Bus1 where the condition of the Waveform Find is set F
18. 2P BETIS HE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 1 2 Introduction 1 Zeroplus Logic Analyzer models LAP 16032U LAP 16064U LAP 16128U LAP 32128U A LAP 321000U A and LAP 322000U A all share the same external features as illustrated in the following figures Adjustable Base Stand Fig 1 9 A view of the Zeroplus Logic Analyzer LAP A Series See Fig 1 12 for detailed information on the Signal Connectors Fig 1 10 Side view of Zeroplus Logic Analyzer which draws its power from the USB connection Port A AO A7 Port B BO B7 Port C CO C7 Port D DO D7 p For extended modules or active other instruments l devices not designated to be analyzed connection For grounding test circuits Fig 1 11 Rear view of Zeroplus Logic Analyzer LAP A Series 8 FM0714A 2P BETIS HE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 2 Zeroplus Logic Analyzer LAP C Series share the same external features as illustrated in the following figures Semel LEI NY RUN READ TRIGGER POWER Sonal Connection NS iy Fig 1 12 A View of the Zeroplus Logic Analyzer LAP C Series See Fig 1 11 for detailed information on the Signal Connectors Fig 1 13 Side View of the Zeroplus Logic Analyzer the power of the Logic Analyzer is drawn from the USB connection PortA AO A7 Port B BO B7 Port C CO C7 Port D D
19. B T 150ns 7 Compr Rate No Trigger Filter 77599 088 5214 318 2829 548 444 T8 1939 991 4324 761 6709 531 3034 301 11479 071 1398 E fretis TZR Bus Signal WS aT m PULL Ee Tr ree GU g Alal e 56129 1960 1959 1962 1957 1963 1957 19 2 42 x 120195 f w A3 A3 g 120195 A4 a4 5 120195 45 45 amp 120195 Y 6 56 A 120195 y 757 s 120195 g 80 50 z 120195 Bi Bi e 120195 B2 82 z 120195 w B3 B3 g 120195 B4 B4 x 120195 E gt 4 xps jls 4 13 DSO stacked Settings To use the DSO stacked function between Logic Analyzer and DSO it is necessary to install specialized software to connect if using the DSOs produced by other manufactures except our company Bl 1o use the Tektronix DSOs to stack please download the TEKVISA CONNECTIVITY SOFTWARE V3 3 4 version or higher from the Tektronix Website Supported DSO Model TDS5000 Series GPIB Logic Analyzer software will be installed in the system of 5000 series LA is the Host DSO is the Slave Connect the Trigger Out of LA with the Trigger In of DSO when LA has been Operating Mode 1 Host Slave triggered it will inform DSO to capture signal 187 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Oscilloscope Computer Device Under Test p ZEROPLUS _
20. CCIR656 MODULE v1 31 000CN01 ZEROPLUS L Compact Flash 4 1 MODULE 1 01 0007 M01 ZEROPLUS L CMOS IMAGE MODULE v1 00 006 NOT ITM ag gug ag x Pea T Te bee ee RAAI Oa gud AORA Find Cancel Help Use the spp More Protocol Analvzer Fig4 58 Color Configuration 121 FMO7IAA 2P BET AR ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Bus Data Color X Bus Mame Busi Data Condition Data Min Data Max ES 1 T Cancel Default Help Fig4 59 Bus Data Color Bus Name Display the selected Bus name Data Condition Select the Data Condition to change the Bus data color There are four options which are In Range and Not In Range Data Min Enter the min data that is required by users Data Max Enter the max data that is required by users The max data can be used only when the set is In Range or Not In Range Select Color Select the changed color according to the Bus condition set by users the default is Green STEP 3 Click Color Configuration to open the Bus Data Color dialog box and set the Data Condition 0 and Select Color is Orange Kus Data Color x Bus Mame Busi Data Condition Data Min Data Max hs lo F Cancel Default Help Bus Signal i 2d 3 71 uu 5 0 Y Bus1 40 A0 4i l Fig4 61 Before the Bus Data Color Setting Bus Signal Y busi ig Cot Y 2 X
21. CE CICE MEZES ES IC E DE egi 26 Trigger Daisy Ts ront Gals RE E Capin Pow VI DO AFIE IOE rs aj A T 100m F B 10 J2cu Total 20 die Drmigplan Minga 10 HHM BPeriium B Twe bdw Tir aha th aL dels afe fiai 31 Channel Height Setting Set it from 30 to 400 DSO Settings when the button is pressed the below box will be displayed DSO Settings x Oscilloscope Brand Tektronix Online Made C TCPJIP Stack Parameters Current Online Model E Sampling Frequency Hz stacking Delay E Tigger Position Trigger channel Trigger Type Activate C Trigger Edge f Video C Pulse Oscilloscope Brand User can select the oscilloscope brand to stack such as Tektronix Then click the Online button to show the oscilloscope model None will be displayed if no oscilloscope is connected Online Mode Users can select USB TCP IP or Auto If selecting the USB the oscilloscope will connect with the PC by USB If selecting the TCP IP the oscilloscope will connect the PC by TCP IP and the IP needs to be set the same as the IP of current FMO7IAA P BE AIR AR 2 ARAE Zeroplus Technology Co Ltd The Zeroplus Logic Analyzer User s Manual V3 11 PC If selecting the Auto users can connect without any setting Current Online Model Display the oscilloscope s name Sampling Frequency It matches with the sec case spin button of oscilloscope Its value is the recip
22. Packet Length Fig4 91 Packet Length Packet Length From Packet s TimeStamp Data to next Packet s TimeStamp Data Packet Idling Length It is O The End dot is Unknown Unknow is registered ata s Timest aap is Packet s Unknow End Flag Timestamp Packet Length I Fig4 92 Packet Length Packet Length From Packet s TimeStamp Data to next Packet s TimeStamp Data Packet Idling Length It is 0 139 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 5 1 WIRE Analysis Preface To increase the Protocol Analyzer feature in order to analyze the Protocol Analyzer 1 WIRE transmission protocol data Using LA analysis function the required serial data can be converted and presented in the form of Bus Therefore the software needs to add a dialog box so as to set up a Protocol Analyzer 1 WIRE dialog box 1 WIRE Introduction 1 Brief Introduction Features 1 WIRE is a non synchronic half duplex serial transmission which requires only one OWIO to transmit data The typical 1 WIRE transmission structure is illustrated in Figure 4 95 During the 1 WIRE transmission the OWIO can be used to transmit data and supply power to all devices connected to the 1 WIRE OWIO will link to a 4 7K Ohm Pull High electric resistance which is linked to the power supply 3V 5 5V The transmission speed for 1 WIRE can be divided into two types standard and high speed Every 1 WIRE has
23. SO Start Out When a user initiates a sampling task by clicking the RUN FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 icon in the window or clicking the START button on the device the S O will send a Rising Edge signal of DC3 3V When the Logic Analyzer finishes uploading a Falling Edge signal is sent Table1 5 Definitions and Functions of Pins for Advanced Models 2 VDD Voltage Drain Provide 3 3 V for external modules by draining Semiconductor voltage from the Logic Analyzer Ext I O Module A Transmit signals between an external model or device and the Logic Analyzer Ext I O Module B Same as IOA Ext I O Module C Same as IOA GND Ground Ground external devices in sequence 1 3 Hardware Specifications Table 1 6A Hardware Specifications of LAP A Series LAP LAP LAP LAP LAP LAP Items Type 16032U 16064U 16128U 32128U A 321000U A 322000U A Operating System Windows 2000 Windows XP Windows Vista Windows 7 Power Supply USB 1 1 USB 2 0 Recommended EN a NENNEN NN Internal Clock Rate 100Hz 100MHz 100Hz 200MHz asynchronous Sampling Max ock synchronous Bandwidth 75MHz Memory 512K Bits 1M Bits 4M Bits 4M Bits 32M Bits 64M Bits Memory Memory 128k Depth Per 32K Bits 64K Bits 128K Bits 1M Bits 2M Bits Bits Channel Trigger 16 Channels 32 Channels Channel Trigger Trigger Pattern Edge Condi
24. The functions of the right key menu on the waveform area are similar to those of the Data menu The menu adds the functions such as Place Ds and Dp Add Bar in the waveform display area Place A Bar T Add Bar Place B Bar Place s Bar be Zoom E 2 E H Place p Bar ES Normal ESCAPE Place Mare Tip The right key menu on the waveform area adds the function of Place Ds and Place Dp However the functions are only used after the Ds and Dp bars are activated otherwise they will be disable These functions are the same as that of A Bar When the mouse is stopped at a special position click the right key on the mouse select the Place Ds or Place Dp the Ds or Dp bar will move to the special position For example Open Select an Analytic Range select the special position is 10 and then select Place Ds See the figure in the right column 74 AS Lace u 2 ea taur bAi Qaia jaa paie qd Dad SRR FAD Holm ia j The Zeroplus Logic Analyzer User s Manual V3 11 A Find Data value Ctrl F EA Find Pulse Width 0 To k Place k Te Add Bar AF be Zoom E em Hand H R Normal ESCAPE E Show all Data Fid eo Previous Zoom Ctrl 2 Data Format Waveform Mode k Color Bus Gabe Golat Bus Single Date Color Fig3 115 Right Key Menu on the Waveform Area E wl El r an Tr anms c x r aJ zi Odd S XAR FAm kO fe mae e Wee joe ft a E EEG ee eee eee ee E Megu Ero Tee
25. amp gy 0 gt gE ell b Db t28k site 100MHz an mu 5096 Page L Count sli ES EB e RP co fi 41 059697 7 Rz Be Be Te i PA re SIE Height 22 Trigger Delay Scale 24 355KHz Display Pos 27 0994ms APos 167 75851ms v A T 5 961Hz 7 A B 3 333MHz 7 Total 335 18149ms Display Range 26 072908ms BPos 167 75821m amp v B T 5 961Hz 7 Compr Rate 255 723 icon to view all data and then select the waveform analysis tools to analyze the waveforms Bus Signal Trigger Filter 20 15 10 5 D 5 10 15 25 E v Bus1 UART amp M E 40 40 Z g Al l g a5 45 g 6 6 wg 7 A B0 60 Bl Bi B2 B2 g B3 B3 B4 B4 B5 65 B6 B6 B 57 g co co g ci ci g c2 c wy C3 C3 C4 C4 goo g C6 c 7 pls aT 1 Fa Ready End DEMO Z Fig 4 77 Waveform Analysis FM0714A 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 3 2 Protocol Analyzer UART Packet Analysis xi Configuration Packet Data Format Register ltem Color Item Color Arnis Min 1 One M az 10s Mie UNKNOW LS Lu a ee Cancel Default Help Fig4 78 Protocol Analyzer UART Packet dialog box Data List Data field captured by Bus in the p
26. i i i Bus Signal LUSI LOYI LUS DOW T RA Se DE new Lo S LF DETIOWI CF DKNOWT 7 LIRTIOWT 7 DIK DOW Sa NENNEN DETIOWI TW yt S CT UB DOW HEN ie Bi 5 Se 5d DEDnowWr xXx x xD Tf o 4 g B3 B3 B4 B4 5 5 5 5 LUSTIOTWT LLS IS End Connected 167 FMO7IAA 2P BETIS AR ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Y ZEROPLUS LAP C 32128 Standard 3 11 CHO1 S H 00000000001 TT b File Bus Signal Trigger Run Stop Data Tjols Window Help 8 x Ee ee sje 8 EE cf ze 00MH 7 m zi e 5 Page fi Count a v R Ar Be T e BA le o FR ie Height Trigger Delay 10ns Bar Bar Bar Bar Bar ate 10 Display Pos Ons A Pos 150ns v T 150ns Di p Total 205 23us Display Range 250ns 270ns B Pos 150ns Di B T 150ns v E 021 Bus Signal Trigger Filter 200ns E in nz Gone i L 00ns 200ns i i i i i Ps TOW Pus OWT oce Pfc Komected 7 Fig 4 138 Before and After Compression Using 2K memory depth before Compression has been applied the total of the data was 20 48us after the Compression had been applied the total of the data was 205 23us therefore the compression rate is 10 021
27. if users don t want to understand more details you can know whether the signals of the two contrast files are completely the same or not Data Contrast Settings I X Active Data Contrast Contrast Files Basic File 23k Contrast File 1 alc Error Tolerance None C Beginning of Data Contrast Result Error Stat gt Contrast Beginning Point 7 Bar 1iraipraggaggagaga um H w Roll the contrast waveforms synchronization Pin Assignment v Display Files the contrast differences v Display Files horizontal Perform Contrast v Do contrast automatically when being run Apply Close Help Fig4 154 Display the Contrast Results in the Data Contrast Settings Dialog Box AO A0 FAIL It indicates that there are differences in the channels of the two files BO BO PASS It indicates that there is no difference in the channels of the two files STEP 3 Display the contrast results in the waveform windows See the figure below 177 FMO7IAA 2P RE TF AR 03 ER 23 8j The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Tip It contrasts the two data files in the waveform area The contrast waveform and the basic waveform are displayed horizontally we can roll the mouse to contrast the waveform files the difference of the waveforms will be lined out with the red wave line in the contrast files Es ZEROPLUS LAP C 3
28. special Unknow Flag to judge the timestamp and end of the packet which are Unknow Start Flag and Unknow End Flag 115 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 This Data Start is regarded as Packet Timestamp This Unknow register is Unknow_End Flag l Packet Length Fig4 44 Protocol Analyzer I2C Packet Length Tip Because I2C has started as the Packet TimeStamp it does not need to use Unknow Start Flag as the start 4 Bus Setting Refresh Export Synch Parameter Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length 1 jBusi Bus 1023s o 1 2 3 4 5 6 7 0 1 Jj 100ms Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data L2 3 4 5 986 j 7 0 j 1 2 3 j Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data i LS LS Le LLL LE LE Lo Le o acket Name TimeStamp Data Data Data Data Data Data Data Data Data I T aos OE ERNNCNNRERR EONRENNRCURUN Name TimeStamp Jata Data Data Data Data Data Data Data Data Length Poste eie 100ms Packet Name TimeStamp Length 6 Busi us 973s A de eede oaee 100ms Packet Name TimeStamp Jata Length 7 Busi us 9 63s 100ms Packet Name TimeStamp Data Data Data Data Date ta Dat ata Data 9 E Fig4 45 Bus Packet List Packet Length an
29. the Fig 4 5 dialogue box will appear Port A represents the pins from AO A7 on the signal connector of the Logic Analyzer and so do Port B C and D The voltage of each port can be configured independently 98 FMO7IAA 2P BETIS AR ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Trigger Property X Trigger Content Trigger Delay Trigger Range Trigger Level Trigger Court Part A n e EMOSIE 25 v thai d ka oe CERTEN Part B um ZEROPLLIS Logic Analyzer X TTL Port C AN Please enter a number between 6 0 and 6 0 TTL Fort D User D efi OK Cancel Default Help Fig 4 5 Trigger Level Error Step3 Trigger Count Type the numbers or select the number from the pull down menu of the Count Count zlon the Tool Bar or click the pull down menu of the Trigger Count on the Trigger Property dialog box as shown in Fig 4 6 The system will be triggered at the position where the Trigger Count is set as shown in Figs 4 6 4 7 and Fig 4 8 Trigger Count Fig 4 6 Trigger Count Pull down Menu Y ZEROPLUS LAP C 32128 Standard 3 11 CHO1 S N 00000000001 LaDoci E a File Bus Signal Trigger Run Stop Data Tools Window Help Dena ELS 4S E bk z oie Bi 00MH v aw w 109 vie 4 Page fi colt fi E Gal RE ev t421019u Rz Be E Te be e HR eoo Heient 30 Trigger Detayi mme Scale 228 192KHz Display Pos 8 T28003us
30. 2 Write 0 Send a 0 bit to Slave Write 1 time slot Write 1 Send a 1 bit to Slave Write 1 time slot 4 Read Data Read data sequences resembles Write time slot However when Master releases BUS and reads data from Slave devices Master creates samples from BUS status In this way Master can read any 0 or 1 bit from Slave devices e Four signal types are described respectively in the following 1 Reset 1 When Master starts communicating with Slave Master first sends a low count Reset Pulse TX t of STL Standard speed 480us High Speed 48us for a period of time MASTER TX RESET PULSE MASTER RX PRESENCE PULSE i b V PULLUP Vu LLUF MIN Vin MIN V L MAX OV RESISTOR mmm VAS TER DS2432 Fig4 94 Master TX Reset Pulse and Master RX Presence Pulse 2 Then Master releases Protocol Analyzer and enters the RX mode Through high pull resistor 1 WIRE Protocol Analyzer is pulled back to the high status 3 Then Master detects a rising edge from the Data Line when every slave will wait for a period of time PDH standard speed 15 60us high speed 2 6us and send back a Presence Pulse to Master PDL standard speed 60 240us high speed 8 24us 4 Finally the 1 WIRE Protocol Analyzer will be pulled back to the high status through the resistor G Meanwhile Master can detect any online Slave O From Fig4 95 the low count Reset Pulse and Presen
31. 8 bits of data following afterwards To halt a transmission it requires a signal or multiple bits of logic 1 Odd number bit transmission requires odd parity error checking and even number bit transmission requires even number error checking Following the parity check is another data translation from serial data to parallel data UART also generates an extra signal to indicate receiving and transmitting conditions Furthermore since UART is an asynchronous communication protocol and data transmission may not be in bytes a complete UART signal Packet must consist of Start Data Psrity Stop Baud and TXD segments They are as following Start When TXD is changing from HIGH to LOW voltage 1 bit Data Users must decide the size of signal Packet segment from 4 to 8bits Parity This performs three types of parity checks odd parity even parity and none parity Stop This occurs when TXD is at high voltage This is adjustable this is commonly set to 1 or 2 Baud This is the data transmission speed according to the initial condition of START TXD This is the transmission direction It is MSB LSB by default 130 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 3 1 Software Basic Setup of Protocol Analyzer UART Step1 Set up RAM Size Frequency Trigger Level and Trigger Position as described in Section 4 1 Tip The Setup of the Frequency should be higher but not
32. 851299us v B 16 182424us v Total 167 69579ms Display Range 48 682703us B Pos 104 033724us v B T 104 033724us v Compr Rate 255 883 Bus Signal Trigger Sr 48 682703us 3f 3694 OTus 146 0481 lus 134 730814us243 41 35113232 036221u 340 78324u 383 4616282438 1443 4 V sous CAN2 te Jou uwuulgu TUN LSL SL SU U UU U L a setting Refresh zh Export Synch Parameter a 31 EX RE OV ER Packet Name TimeStamp Basic ID SRR IDE ID RIOR PRED RBG DEC Data CRC ACK DESCRIBE Fig4 136 CAN 2 0B Packet List Displayed with the Waveform 166 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 6 Compression The compression function enables the system to compress the received signal and has more data stored in per channel 4 6 1 Software Basic Setup of Compression Step1 Set up RAM Size Frequency Trigger Level and Trigger Position as described in Section 4 1 Step2 Set up the trigger edge on the signal or the Bus to be triggered Step3 Click i icon or click the compression function from the Sampling Setup dialog box then click Apply and OK to run Sampling Setup x Clock Source Asynchronous Clack Frequency 1 mHz Synchronous Clock External Clack f Rising Edge Frequency 100r ea en Im aman ese ME MEC C Falling Edge Se File Bus Signal
33. AR D T3 PR 23 nl Zeroplus Technology Co Ltd Customize Export Waveform F2 E Customize The Zeroplus Logic Analyzer User s Manual V3 11 Fig 3 76 Auto Save Setting See Section 3 5 for detailed instructions FMO7IAA Phe AR AR 2 BPR Zeroplus Technology Co Ltd Color Setting BUS Bus Property See Section 4 5 for detailed instructions 58 The Zeroplus Logic Analyzer User s Manual V3 11 Color Setting xX Workaround Wi aveform Relating AHLHHLLHL k After the background is altered corresponding color fo Jal automatically changes according to the contrast ratio When being printed the r2 background iz white Cancel Default Help Fig 3 77 Color Setting See Section 3 6 for detailed instructions Bus Property x Bus Setting C Bus Color Config Activate the Latch Function AQ Rising Edge Protocol Analyzer Setting Parameters Configs C ZEROPLUS LA 1 WIRE MODULE 1 10 00 CNO1 C ZEROPLUS LA 3 WIRE MODULE 1 04 00 CNO1 C ZEROPLUS LA AC97 MODULE V1 02 00 CNO1 C ZEROPLUS LA ARITHMETICAL LOGIC MODULE V1 51 00 CNO1 C ZEROPLUS LA BUS MODULE V1 00 00 CNO1 c ZEROPLUS LA CAN 2 0B MODULE V1 32 00 CNO1 C ZEROPLUS LA CCIR656 MODULE V1 31 00 CN01 c ZEROPLUS LA Compact Flash 4 1 MODULE V1 01 00 CNO1 C ZEROPLUS LA CMOS IMAGE MODULE V1 00 00 CNO1 M Tnm dua PR ALT Teh Ce e
34. Asynchronous Transmission Protocol It costs low sky high use rate far data transmission distance 10KM very high data transmission bit 1M bit s sending information without appointed devices according to message frame dependable error disposal and detection error rule message automatism renewal after damage and node can exit Bus function on the serious error Applications CAN 2 0B is used for automotive electronics correlation systems connection 2 Protocol Analyzer Signal Specifications 100MHz 0 0 0 Appropriate Sampling Rate 100MHz Same Data Time Per Bit Name of Syn Signals CAN 2 0B Data Verification Point did 190us converts to High signals gt 3 Protocol Analyzer IO Description CANL The main signal source of transmission data CANH Signal is opposite to the signal source of transmission data 4 Protocol Analyzer Electrical Specifications EL C NN S Logic Input High Logic Input Low CAN 2 0B Frame Specification CAN 2 0B can separate into frames as follows Data Frame Remote Transmit Request Frame Error Frame Overload Frame Because CAN2 OB is transmitted by the format of different signals the signal can separate into CANL and CANH and the signal direction of CANH is opposite to that of CANL Next we analyze CAN 2 0B signal with the standard of CANL Basic Data Frame Data frame can be divided into Basic CAN and Peli CAN Data Frame of Basic CAN transmission As follows 157 FMO7IAA
35. Bits 128Kx255 32M Bits for each channel The chosen capacity of the memory 1MB means that the maximum data being sieved out arrives at 1MB 255 255M Bits Per Channel Note The rate will change depending on the data being analyzed FM0714A Zeroplus Technology Co Ltd O FP BBA 5 AS OS ER ZA 8j Tip 9 Signal Filter Setup Tip Select the Signal Filter Setup from the pull down menu of the Bus Signal or click the icon or the Button on the Sampling Setup dialog box to open the Signal Filter Setup dialog box Tip There are three modes of Signal Filter configuration for each channel 35 The Zeroplus Logic Analyzer User s Manual V3 11 Signal Filter Setup x Filter Condition Trigger Condition Port Filter Condition Trigger Condition PortB 7 Filter Condition BG Trigger Condition Porte F TE NX Filter Condition 5 Trigger Condition PortD z Filter Condition Filter Delay Setup Activate Filter Delay E Filter Delay Mode Select Delay Start Point m Delay Time Q According to Filter Gondition fs Start Edge 10us End Edge Min 10us Opposite of Filter condition C Period Delay Max 655 35ms Display Bar Setup Show Bar Bar Style o iginal 4 Bar Width 104s B Cancel Restore Defaults Help Fig 3 22 Signal Filter Setup Dialog Box The function of Signal F
36. Cancel Click Cancel to end the capture Chineset Si Chinese Tr iw English Fig 3 14 Choose among Chinese Simplified Si Chinese Traditional Tr and English EROPLUS Logic Analyzer The program needs to restart Do vau want bo save Ehe current document Fig 3 15 When changing languages the above screen will be displayed and the program will need to be restarted Status Ready Type hp LaserJet 1000 Where USBOO1 Comment All Number of copies 1 E C Pages from 1 to 272 p collate C Current Page omes Fig 3 16 Click to enter the Print dialog box aed Ces bem Fig 3 17 Click to show a Preview of the Print Recent File Exit Show the recently saved file Exit the program 31 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 2 Bus Signal Unoroup From Bus Chins Expand Collapse FU oa Auto Sce Fig 3 19 Trigger Tool Box 32 FMO7IAA Phe AIR Be 2 ARAE Zeroplus Technology Co Ltd The Zeroplus Logic Analyzer User s Manual V3 11 Menu Bar Bus Signal Menu Item Detail Menu amp Dialog Box xj Clock Source Asynchronous Clock Frequency S5MHz kai Synchronous Clock f External Clock Rising Edge Frequency rook Falling Edge Min 0 001Hz Max 100MHz Wy Sampling Setup Note The external clock voltage level is the same as the port A trigger
37. Complete the protocol analyzer HDQ decoding Fe ZEROPLUS LAP C 32128 Standard V3 11 CH01 S H 000000 0000 HDQ_SET X M i 57 6420621 T z co co O ARMEE Erge 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 695ms 695ms 695ms 695ms 695ms 695ms 695ms 695ms Fig4 118 Protocol Analyzer HDQ Decoding FMO7IAA PRET RAR 3 ER 23 8l The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 6 2 Protocol Analyzer HDQ Packet Analysis PROTOCOL ANALYZER HOQ Fig4 119 Protocol Analyzer HDQ Packet dialog box Item Select the content which needs to display in the Packet List which includes Break Recovery Address Data Read Write and Describe Color Set color for items which needs to display in the packet list 156 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 7 CAN 2 0B Analysis Preface Add Protocol Analyzer function to analyze CAN 2 0B transport protocols data CAN 2 0B serial transmission there are two signal channels CANH and CANL which match with baud ratio judge serial data If you want to change serial data into Bus format you need to analyze this function with LA a dialog box needs to be added you should set up a Protocol Analyzer CAN 2 0B dialog box CAN 2 0B Introduction 1 Brief Introduction Features CAN 2 0B Controller Area Network is an
38. Data Data Data Data 2 3 4 5 6 7 o 1 J 2 J 3 jJ Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length SL EE DE CN EN DT Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data L6 7 o 1 j 2 j 3 j 4 5 6 7 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length A BERE NER E E ITR cM Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length 6 BuiBu 973s 2 3 4 5 J 6 7 O 1 j 2 3 J 100m z Fig 4 50 Synch Parameter on the BUS Packet List At the same time a Synch Parameter Setting dialog box is added Synch Parameter Setting l xX Synch Point of Packet List Synch Point of Waveform Area Top C Left C Middle Middle Fig 4 51 Synch Parameter Setting Dialog Box Activate Packet and Waveform Synch The default is not activated Top When the Packet and Waveform Synch is activated the synch point in Packet List is the top packet segment which is displayed by list Middle When the Packet and Waveform Synch is activated the synch point in Packet List is the middle packet segment which is displayed by list Left When the Packet and Waveform Synch is activated the synch point in the waveform area is the left packet segment which is displayed by waveform Middle When the Packet and Waveform Synch is activated the synch point in the wavef
39. Export Packet List Export the active packet list Fal Capture Window Ctrl C Language p Language Allow users to change the language interface of menus tool boxes etc ej Print gus Print Preview Show three options Bus Signal amp Print Preview Trigger amp Filter Position Display Area and Waveform Display Area See Fig 3 17 1 LA 2 alc 2 lec Exit Exit Exit the program Fig 3 2 File menu Dea Fig 3 3 Standard Tool Bar Menu Bar File Menu Item Detail Menu amp Dialog Box C New Ctrl M Open a New file 26 FMO7IAA 2f ZPBETIHSHR T3 R2 S The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 t Open Close E Save Save as Suto Save 31 xl Look in E B11004 LAP 8DM er My Recent Documents Desktop B11004 LAP BDM M CHM SI v1 00 20110520 is BDM a gt My Documents jg a My Computer Ctr a uc LI EU Filename Places Files of type Logic Analyzer LAP C File alc J Cancel File Preview Project File Date Author File Time Title Module No Note Fig 3 4 Open an existing file Dur s c m ae ee oe ee EUM E ajja es ee Meg Heg Chrl Fe4 Ena wees d irk Ff Fig 3 5 Close the active workspace Save As 21 x Save in C3 B11004 LAP BDM er Fe B11004 LAP BDM M CHM SI v1 00 20110520 te BDM My Recent Documents t Desktop 4 A My Documents i Ctrles e
40. File and the Contrast File Wavelorm Find i xX Activate the Function of Chain Data Find Bus Signal Name Next Previous Clase Bus Item Find Min value Max Value Skart hal oF 0 E Stark AE End At When Found Statistics Statistics ps Dp Fig 3 47 Waveform Find Dialog Box without Activate FMO7IAA Phe AIR Be 2 ARAE Zeroplus Technology Co Ltd Tip Remember the final conditions When the find function is used the function of displaying the final conditions is added When you have closed the Waveform Find dialog box and you want to find the set conditions you can open the Waveform Find dialog box again for the system has saved the last set conditions 45 The Zeroplus Logic Analyzer User s Manual V3 11 the Function of Chain Data Find Use the pull down menu to select the Bus Signal Name The list of Find depends on whether it is a Bus or Signal that is being searched in Bus Choose among In Range and Not In Range enter the value for Min Value and Max Value Signal Choose among Rising Edge Falling Edge Either Edge High and Low Start At Choose the position to start our search by selecting one of the following Ds T A B ect select from the pull down menu When Found Choose A B or other bars to mark the position where it is coincident with the set conditions Statistics Show the number of instances of the sear
41. I x Bus Trigger Protocol Analyzer Trigger Bus Mame Operator Bust M Es Data Format C Binary C Decimal C Decimal Signed Hexadecimal ASCII C Gray Code C Complement Cancel Default Help Fig 4 18 Bus Trigger Dialog Box Tip The Bus Name item can be selected from the pull down menu It only displays the Bus name and also the Decimal signed Gray Code and Complement Modes are added 2 Protocol Analyzer Trigger Setup Tip This function can be used in the Modules LAP 16032U LAP 16064U LAP 16128U LAP 32128U A LAP 321000U A LAP C 16032 LAP C 16064 LAP C 16128 LAP C 162000 LAP C 32128 and LAP C 321000 after registering And for the LAP 322000U A and LAP C 322000 it is not necessary to register as they can be used for free Before registering the button OK in the Protocol Analyzer Trigger dialog box is the button Register when users press this button Register a Register dialog box will pop up Then users need to enter the correct Register Code so that they can use this function Protocol Analyzer Trigger 103 FMO7IAA 2P BETIS AR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Bus Trigger X Bus Trigger Protocol Analyzer Tigger Allow Pratecallemalyzer Trigger Protocol Analyzer Protocol Packet Data Format Binary C Decimal Decimal Signed C Hexadecimal IESSNI Gray Code Comp
42. Mode Select Delay Start Point Delay Time According to Filter Condition Start Edge ps o End Edge Min 100ns C Opposite of Filter Condition C Period Delay Max 553ms Display Bar Setup Bar Style original Bar width 1000s OK Cancel Restore Defaults n Fig 4 145 Filter Delay Setup The delay time of signal AO is 1 us which is the condition of the Filter Delay Setup Step 7 Signal Filter Time Interval 1 Click Show Bar to know the length of the tested and deleted signal as shown in Fig4 146 below Display Bar Setup I Show Bar Bar Style original Bar Width 1 ns OK Cancel Restore Defaults Fig4 146 Display Bar Setup 2 The bar has two styles which are Original and Bar the default is Original style which denotes the bar function cannot be used When selecting Bar style the bar function can be activated 3 Bar Width when Bar style is selected the bar width can be set by users Tip The minimum bar width is 1 the maximum bar width is 65535 If the value exceeds the range or the font is not according to the requirement a tip window will appear Signal Filter Time Interval is denoted by Bar Fig4 147 Signal Filter Time Interval 172 FMO7IAA 2PBETIBBS0 SIR al The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Tip The Signal Filter Time Interval is limited under the following situations A The Filter Delay and Dis
43. OG Y oa X O6 Y 06 Y OX di AD 40 Al l Fig4 62 After the Bus Data Color Setting Tip Reserve the original state by the above steps STEP4 Activate the Latch Function 122 FMO7IAA 2P BETIS BR 0 BPRS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Activate the Latch Function The default is not activated When the Latch function is activated the default channel is AO and there are three conditions for selecting Rising Edge Falling Edge and Either Edge the default is Rising Edge Tip The Latch function is available for the LAP 321000U A LAP 322000U A LAP C 162000 LAP C 321000 and LAP C 322000 Modules and it is not available for the LAP 16032U LAP 16064U LAP 16128U LAP 32128U A LAP C 16032 LAP C 16064 LAP C 16128 and LAP C 32128 Modules Set the Latch function for one Bus The setting of the Latch channel is A0 the analysis function adopts Rising Edge Bus Property X Bus Setting Bus Color Config v Activate the Latch Function Protocol Analyzer Setting Protocol Analyzer Parameters Con s ZEROPLUS LA 1 WIRE MODULE v1 10 006 C M01 ZEROPLUS LA 3 WIRE MODULE 1 04 0060 CMO1 ZEROPLUS LA ACSF MODULE v1 02 000 C NOT C ZEROPLUS L ARITHMETICAL LOSIC MODULE v1 51 0007 M01 i ZEROPLUS LA BUS MODULE v1 00 006 NOT i ZEROPLUS LA CAM 2 05 MODULE v1 32 000 C NOT i ZEROPLUS LA CCIR656 MODULE V1 31 D0 CNO1 ZEROPLU
44. The Logic Analyzer s Waveform Viewer Background Color List Background 1 The Logic Analyzer s First Listing Viewer Background Color List Background 2 The Logic Analyzer s Second Listing Viewer Background Color All optional items include the current color of Cursors Grid Unknown Line Default Bus Bus Text List Text and Time Text users can scroll the vertical wheel to view the selectable items Bus Error Users can configure the color of Bus Error Data from the Color Setting dialog box Bus Error Text Users can configure the color of Bus Error Text from the Color Setting dialog box Signal Filter Bar Users can configure the color of Signal Filter Bar from the Color Setting dialog box Relating When users select one item to change the color of the item and users want to change other items into the same color they can select other items at the same time in the Relating column then the selected items will be changed into the same color So it is convenient for users to change many items into the same color once After the background is altered corresponding color automatically changes according to the contrast ratio When users set the color for the workaround and select the option the system will switch other colors automatically to become the contrast color FMO7IAA PRET AR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 When being printed the background is white When being prin
45. The Zeroplus Logic Analyzer User s Manual V3 11 Multi stacked Logic Analyzer Settings X Memory Stack C Channel Stack Please select the Logic Analyzer for stacking MT S N 00000 0000 M2 S N 000000 0000 M3 3M O00000 0000 M4 S N 000000 0000 Synchronous Channel AD Synchronous Trigger Condition Rising Edge Cancel Help Fig 3 81 Multi stacked Logic Analyzer Settings Dialog Box See Section 4 12 for detailed instructions Analog Waveform The function of Analog Waveform means that the Display Mode of Bus Data is not the Pure Data Mode while it displays data change with the curve which looks like a waveform which in fact is a curve to describe the data change So it is called the Analog Waveform The Analog Waveform can be divided into two kinds namely Single Analog Display and Mixed Analog Display see the figures as below LAP ot TIT I LI J lax ta t Reto Uwe Rupe Qua jme we D SG 5 erum siti x Daa 45N4 cSsIB b ee amp meee e fax eja Pg cel E FRIAD N 5 Jj 4z5EDLLA go ew f2 ji Teewosey 5 S we 2OOMPS Crapies Pet Oru APes ira amp Te thee A Ort AT etal 1d us Dingin Hange T250a 13518 BPws Mas e Teti tine Compe Rate his a LE oe una n EF WE et tee 1 I Fig 3 82 Single Analog Display FMO7IAA 61 O ABATE AS HIRD Zeroplus Technology Co Ltd D5O stacked Settings The Zeroplus Logic Analyzer User s Manual V3 11
46. Why must reinstall the driver every time use a different Logic Analyzer A Since each Logic Analyzer has unique serial numbers you must reinstall the driver every time you change the Logic Analyzer H13 Whyis there no data Why does data sampling seem inconsistent A The reasons are varied but you may follow this checklist for troubleshooting 1 Always check the USB connection between the Logic Analyzer and your PC 2 We strongly recommend using USB ports in the rear panel of a PC these ports usually have better voltage stabilities than front panel ports However if front panel USB ports are directly soldered to the main board you can use them 3 Make sure the Logic Analyzer is directly connected with the PC without a USB hub 4 Inconsistent data display may indicate voltage irregularities in the main board examine capacitors on your main board or power supply 200 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 5 If the problem is the power supply we strongly recommend purchasing a power supply with a hardwired voltage transformer rather than a voltage regulator For power supplies with the same output power those built with hardwired voltage transformers are usually much heavier than those relying on voltage regulators H14 What are the time settings for Setup and Hold A Setup Time 0 05ns 0 25ns Hold Time 0 02ns 0 08ns Clock High
47. Write O or Write 1 Sequence 143 FMO7IAA 5 144 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 1 WIRE Serial Number 1 Every 1 WIRE Slave has a unique laser memory 2 The serial number is 64bits 3 The serial numbers are 8bytes in total located in three individual which are illustrated as below 64 bit Registration ROM number 8 bit CRC 48 bit Serial Number 8 bit Family Code M SB LSB NIST LSB 4 Starting from LSB the first byte is for family code which is used to identify product categories 5 Next the 48bits is the only address for storage 6 The last byte MSB is used to store CRC FMO7IAA O 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 5 1 Software Basic Setup of Protocol Analyzer 1 WIRE xi Configuration Packet Data Format Fiegister Pin Assignment Protocol Analyzer Color Owl Reset Pulse Presence Pulse Protocol Analyzer Property Connect Speed Standard 1 us Transmission MSB gt LSB Direction Data Length E bit Fin 1 bit M as 32bit Data Mind M as 120 Cancel Default Help Fig4 100 Protocol Analyzer 1 WIRE Configuration dialog box Set the 1 WIRE Configuration dialog box Pin Assignment 1 WIRE only needs one channel to decode the signals and the default is AO Connect Speed The Connect Speed c
48. about the grids in the waveform such as Address Time Frequency Trigger Bar A Bar B Bar and other Bar Details of the labels are below Scale Define the acquisition clock that controls the data sampling Total The period of time when Logic Analyzer captures data Display Pos The middle tip means the middle position of the waveform Display Range Display the waveform time range of the current waveform display area A Pos The main function is to set A Bar or the other Bar B Pos The main function is to set B Bar or the other Bar A B Press the under arrow to exchange and become the other Bar Moreover you also can execute this function from the other Bar 4 Ruler Waveform Display Listing Display Ruler shows the time position of the waveform shown in the waveform display area or the listing display area 24 FMO7IAA 25 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Bus Signal Waveform Display Listing Display Edit names of the measured channels color shown matches the trace color Trigger Column Trigger Column allows users to adjust signal trigger conditions Filter Column Filter Column allows users to set Bus or signal filter conditions Display Area Acquired data is displayed as a waveform or in a list format Waveform Display This interface shows the digital signals When the signal is logic 0 the waveform will be displayed as I If the signal is l
49. ange 40 92m 4155 GB Pos amp 00us Tz1857TKMr Compr R te N L3 m haiga Tagger Fa Y an GAI A d Md en ex MMT e MMMM MMM MMMM MMMM on MAUI es nnnnnnnnnnnnnnnn nnnnnnnnnnnnnnni n FLL LAL La an Fig 4 25 Click Icon to View All the Data 3 Stop to end Run Click the Stop icon to end the Run Tip If the status is Waiting with no signal outputting as shown in Fig 4 26 click the Stop icon to end the Run check the setup again and try the run process again EN Waiting Connected Zz Fig 4 26 Waiting Status 107 FMO7IAA 2P RE PF AR 03 ER 23 8j The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 2 Bus Logic Analysis Section 4 2 presents detailed instructions about logic analysis with a set of grouped signals which is known as Bus Logic Analysis Basic Software Setup of the Bus Logic Analysis Step1 Set up the RAM Size Frequency Trigger Level and Trigger Position as described in Section 4 1 Step2 Group signals into a Bus Click Channels Setup on Bus Signal of the menu bar or click i icon The dialog box shown in Fig 4 27 will appear Group int Exped Colapse Format R Ed Eg Pa bas bha ba bp Ru d Wu Eg Kg BABE iu Hu Fig 4 27 Channels Setup Rename the Bus and set up the channels of the Bus as shown in Fig 4 28 Boe DDE BAR Fig 4 28 Rename Bus 1 Click the colu
50. by using a clock pulse The Logic Analyzer is like a digital oscilloscope However it only shows two voltage states the logic status 1 and O differing from many voltage levels of an oscilloscope The Analyzer has more channels than an oscilloscope to analyze the waveform Since the Logic Analyzers obtains only signals 1 and 0 its sampling frequency is slower than an oscilloscope which needs many voltage ranks Moreover the Logic Analyzer can receive many signals during a test How does the Logic Analyzer operate The Logic Analyzer reserves trigger requirement setting for users and uses them on the test equipment for the value of the sampling signals and puts them into the internal memory The software of the Logic Analyzer will read out the value from the memory and switch it to the waveform or status shown for users analysis What is the asynchronous Timing Mode Since the sampling clock and tested objects are not directly related to each other and the former won t be controlled by the latter the sampling clock and the tested signals will not be done at the same time We call this Timing Mode which means that in the same time interval you can get sampling data from the test equipment at one time such as every 10 seconds The internal clock the Logic Analyzer s inner confirmed one is often for sampling in Timing Mode as is the logic waveform What is the synchronous State Mode Because the sampling clock and measured object c
51. chapter users will learn the functions of all defined hot keys in the software interface of the Logic Analyzer 7 1 Hot Keys Table 7 1 Hot Keys 1 Statement Move the A bar to the center of the waveform area select A bar by the cursor Move the B bar to the center of the waveform area select B bar by the cursor Move the T bar to the center of the waveform area select T bar by the cursor Change the mouse mode to Zoom Change the mouse mode to Hand Table 7 2 Hot Keys 2 Hot Key Equivalent Orders A Go to A Bar B Go to B Bar T Go to T Bar E Change to Zoom mode H Change to Hand mode Hot Key Equivalent Orders Ctrl A Go to A Bar Ctrl B Go to B Bar Ctrl C File gt Capture Window Ctrl E Data gt Zoom Ctrl F Data gt Find Data Value Bus Signal gt ae Group into Bus Ctrl N File gt New Ctrl O File gt Open Ctrl P File gt Print Ctrl S File gt Save Bus Signal gt SENS Ungroup from Bus Ctrl Z Data gt Previous Zoom Ctrl Shift E File gt Export Waveform Statement Center A bar Center B bar Open Capture Graph dialog box Change Mouse mode to Zoom mode Search specific data with predetermined conditions Group selected signals into a Bus Create a new file Open a saved file Print an active file Save an active file with its current name location and file format Ungroup signals Pins from a Bus Reverse the last zoom Op
52. display Move Left Up Move Right Down Hide Show All and Color Ungroup signals from Buses by pressing Ctrl U A Bus contains at least 1 channel In order to see these channels click the symbol before the name of the Bus Bus Signal FMO7IAA 3 Tip Phe AIR B2 2 ARAE Zeroplus Technology Co Ltd Collapse Format Pow k Format Row Auto Size it is not available in Waveform Display mode Move Left Up change to Move Left in Listing Display Move Right Down change to Move Right in Listing Display Hide Show All Color Rename The Zeroplus Logic Analyzer User s Manual V3 11 Fig 3 26 Expand If the Bus has been expanded click the V symbol before the Bus name to Collapse the Bus v Bus1 S An 40 Al Al az az 43 A3 A4 A4 was 45 5 46 Fig 3 27 Collapse Gute size Move LeftiLlp Move RightiDown Hide Shaw All Color Fig 3 28 Click to change the Bus or signal display Change the display of a Bus or a signal Size the signal columns automatically Highlight a signal or Bus and click Move Left Up to move the signal or Bus up left through the list of the Bus signal Highlight a signal or Bus and click Move Right Down to move the signal or Bus down right through the list of the Bus signal Highlight a signal or Bus and click Hide to hide it Click to show all signals and Buses that have been hidden Highlight a signal or Bus and click Colo
53. i 9 Help and Support a E 4 Sounds and Audio Devices LS Printers and Faxes gf Speech CF Run gi Taskbar and Start Menu FR Stored User Names and Passwords Symantec LiveUpdate XS System gil Taskbar and Start Menu 48 Windows Firewall Log Off king Fig 6 5 Windows Regional and Language Options SW13 Is there a Reset that restores the default color settings for signal output waveforms in the Position Signal Display Area 203 FMO7IAA 2P BETIS HE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 A Yes there is Click Tools from the menu bar and select Color Setting click Defaults However this restores everything in this window You must make a further adjustment if the color setting is the only thing you want to restore See Fig 6 6 Color Setting i X Workaround Waveform avetorm Background List Background 1 List Background 2 qmiman After the background iz altered corresponding color jo ee ee automatically changes according to the contrast ratia When being printed the M background is white Cancel pea He el Fig 6 6 Restore Color Defaults SW14 Can I change the displayed waveform mode A Yes you can There are two ways to do this First go through Data gt Waveform Mode and choose a waveform See Fig 6 7 k l Select an Analytic Range uk Noise Filter or Bus Width Filter lata Contrast P Fi
54. jo Bm Nom Ji ikke Bhan cic 3 Ma Dl Hes Biso Fig3 97 Display Packet List FM0714A Phe ARAL 0 ARAS Zeroplus Technology Co Ltd The Zeroplus Logic Analyzer E fi Statistics window S69 36 63 Oh 2 coocro oo oo z Fa em Pa cacgobDpocobpoo TUTTTUTVPTE 29992999925 2 coo ooo Oo ey cr Fig3 98 Statistics Window See Section 3 3 for detailed instructions 69 Cascade oie Jo afar J E mmm T SEENEL Bagam Pen Sma Horizontal x ae Jannanen en ESTER 7 DR nuu M PFLIIPLTLE rug E i L3 1 EE x HL m jj I x me CE E S M Vertical Nm i EET i EERE EEE KNN bbb Fig 3 101 Align Workspace s Vertically FMO7IAA 2P RE PF AR 03 ER 23 8j The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Screen Display When there are two displayers connecting users can select Screen Display k Double Screen Display to display waveforms on both B Double Screen Display Wi First Screen Display Wi Second Screen Display waveforms First Screen Display or e Second two displayers it is convenient for displaying more Screen Display can also be selected to display waveforms on the first displayer or the second displayer 8 Help Logic Analyzer Help Fl keyboard Map Problem Feedback P About ZEROPLUS Logic Analyzer About ZEROPLUS More Protocol Analyzer Fig 3 102 Help Menu Menu Bar Help Menu Item Det
55. oso cH pSo_cH3 DSO cH Channel Height Setting D50 CH1 Height a D50 CHz Height ol D5O0 CH3 Height a DSO CH4 Height au DSO Settings OK Cancel 191 FMO7IAA PREP i BPR The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 STEP 7 Press the DSO Settings button to open the dialogue box DSO stacked Settings X Channel v Div Setting D5O CH1 ViDiv zvipie D5o CH viv zvipiv D5O CH3 VjDiv zvipie DSO CH4 viDiv zvipiv Channel Setting only display O50 psa cHi oso cH psocHs DSO cH Channel Height Setting D50 H1 Height a D50 CHz Height ol D5O CH3 Height a DSO CH4 Height au STEP 8 Select the connected DSO Manufacturer Currently it only supports Tektronix Manufacturer xj Oscilloscope Brand Tektronix Online Made Stack Parameters Current Online Model Ss s Sampling Frequency fo Hz Stacking Delay nn Fs Trigger Position NENNEN ho Trigger Channel Trigger Type Activate C Trigger Edge C viden C Pulse STEP 9 Set the Connection Mode to USB or TCP IP according to the connection mode of DSO If selecting TCP IP it is necessary to key in the IP Address of current computer Users also can select AUTO to auto recognize the Online Mode Tektronix 1000 2000 series adopt the USB Interface to connect 192 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus L
56. red T Bar displays the trigger condition in order v Bus Signal Trigger Filter E m jM 24570 taal 32760 LAM L M Li Li Li i 1 1 1 Li Li 1 Li 1 Li 1 Li 1 Li Li Li Li 1 L 1 1 Li Li Li 1 i Li Li Li i 1 VW Busi I2O S le ea0 4 Ai A A2 42 C A3 A4 Fig 4 21 Protocol Analyzer Trigger Mark Tip The Trigger Mark function is available for the LAP 322000U A LAP C 162000 LAP C 322000 Modules and it is not available for the LAP 16032U LAP 16064U LAP 16128U LAP 32128U A LAP 321000U A LAP C 16032 LAP C 16064 LAP C 16128 LAP C 32128 and LAP C 321000 Modules FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Task 4 Bus Signal Trigger Condition Setup Highlight a designated signal and then set its required trigger condition 1 Left click to set the signal trigger condition as shown in Fig 4 22 2 Right click f to set the signal trigger condition as shown in Fig 4 23 3 Click Trigger on the Menu Bar and choose a trigger condition from the list of triggers as shown in Fig 4 24 Pus Signal Filter 200us T i hi Bus Trigger Setup ai Al og Channel Trigger Setup if Trigger Property 42 42 je Bus Signal Trigger PIENE DX Don t Care PITE Left Click poro rm 4 a4 Ge nn f Rising Edge a2 Az was as tN Falling Edge g ag
57. requires a minimum of 0 31ns Clock Low requires at least 0 47ns 201 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 6 2 Software SWO01 Why is the compression function not enabled by default A Mostly to avoid significant errors when testing signals with high variability or measuring a certain channel for a long time period SWO2 What is the purpose of the compression function A The compression function measures signals that vary slightly over a long period SWO3 Can I enable Trigger Page and Compression Function simultaneously A Yes you can SW04 When should I use the Bar function A This function allows you to highlight a segment of a waveform so that you can have a closer view Depending on the configuration of Waveform Display Mode under Tools Customize a more accurate numeric value of sampling site time or frequency difference will be calculated and displayed as shown in Fig 6 7 4 Pos O7Ous 4 T 69 s46us hs B 18845us BPos b us B T 50uz Compr Rate 1 000 Fig 6 1 Bar Function SW05 Can triggers be differentiated in Pre Trigger and Post Trigger A Yes they can SWO6 Are all setup parameters and configurations saved as save my work A Yes everything in your work space except signal graph will be saved SW07 If have the wheel feature with my mouse or other pointing devices may adjust the waveform displ
58. right corner of the bottom will display the Time Clock or Address of the selected area When selecting the Zoom function and users are pressing and dragging the left key the information on the right corner of the bottom will be changed and updated with the width of the selected area And the information is displayed on the right corner of the bottom in the way of Tooltip When users loosen the mouse the information will disappear Tooltip Time Frequency Sample xxx time ns unit Address xxx There is no unit with the address em Hand H 50 696 7185 5 694 Address 4 O 2G NEN Ere i i E E posee 329733 28175 23378 185 uudtiudulii LILILI LI I Fig 3 60 To Zoom Out left click and drag the mouse point from right to left jelai d od ed afa c i aj Fig 3 61 To display the Tooltip left click and drag the mouse point from right to left or from left to right Fig 3 62 Click Hand and then depress and hold the left mouse button to drag FMO7IAA Phe AIR AR 2 ARAE Zeroplus Technology Co Ltd The Zeroplus Logic Analyzer User s Manual V3 11 R Normal ESCAPE Reset the mouse function to the system default kg 2oom In F8 zoom Qut Fa Tip Zoom In and Out can be switched by changing the percentage value in the pull down list 1 The system can set the value of Zoom In and Out The default unit is ws When zooming in it will be a
59. rrr Moise Filter EE Bus Width Filter Data Contrast B Find Data value Ctrl F LA Find Pulse width l To the Previous Edge FII To the Next Edge pi coro 7 iii i Add Bar Alt A B Go To 4 Bar Delete Bar Alk B B Go To B Bar ik Zoom E Go To More 4 1 Hand H R Normal ESCAPE Binary Wem SCC F Decimal Signed I zoom Out ne r Hexadecimal aa Show all Data Fig ASCII KS Previous za CE HE UT TETTE Data Format Complement Square Waveform Sawkooth Waveform iw All Data Sampling Changed DotiCompression Data Changed Dati Cempressian Fig 3 41 Data Menu Ceea ue ae E LL Fig 3 42 Data Tool Box FMOT7IAA P BE AIR Be 2 ARAE Zeroplus Technology Co Ltd Menu Bar Data Menu Item Select an Analytic Range E Noise Filter ecd Bus Width Filter 43 The Zeroplus Logic Analyzer User s Manual V3 11 Detail Menu amp Dialog Box Check the box to enable the Analytic Range to be changed by dragging the Ds and Dp bars with the left mouse button Noise Filter It can filter 0 10 Clock s positive pulse width or negative pulse width signal Noise Filter E x Fig3 43 Noise Filter See Section 4 8 for detailed instructions Bus Width Filter X omn Fig3 44 Bus Width Filter Select the check box to activate the function of the Bus Width Filter in the dialog box and then users can input the corresponding value of the wi
60. sales representative will be happy to assist you H03 Is the memory size fixed If I just use one of the ports can expand the memory size A The Logic Analyzer s memory is fixed at 4 megabits Due to current hardware limitations the memory size cannot be modified even as the number of ports used changes H04 Are different external sampling frequencies for different channels possible A No there is only one external sampling frequency available H05 Can I disable or set a certain port to don t care while during compression A No during compression D Port will be set to be disabled H06 Why does the Logic Analyzer feature negative voltage calibration A This allows users to analyze any given signal H07 How dol adjust the Trigger Level A The adjustment of the trigger level is done with a port which consists of 8 channels The trigger lever can only be adjusted for an entire port H08 Does the Logic Analyzer use hardware or software compression technology A For time efficiency the Logic Analyzer uses hardware compression H09 Is planning an Analyzer that can handle more channels A Yes we are working in this direction H10 Does the memory page vary when the depth of the memory changes A Yes the depth of memory changes the memory page H11 Is the Logic Analyzer expandable How may I expand it A Yes the Logic Analyzer is expandable At this stage you can expand it with external module devices H12
61. same time 1 Trigger Page Click Trigger Page then type the numbers or select the numbers from the pull down menu of the Page Page fi lon the Tool Bar or click the pull down menu of the Trigger Page on the Trigger Delay page of the Trigger Property dialog box as shown in Figs 4 9 4 10 and 4 11 The selected page numbers will be displayed on the screen Tip The Trigger Bar T Bar will not be displayed when the setup of the Trigger Page is more than 1 Trigger Property x Trigger Content Trigger Delay Trigger Range Trigger Page C Delay Time and Clack Trigger Delay Time 200ns Min 200ns Max 3 355238s Trigger Delay Clock m Min 1 Max 16776191 T Pos Ons Start Pos 204 Bus End Pos 205us Note When more than one trigger pages are selected the trigger bar disappears from the view gy File Bus 5i pal Trigger Eun 5tee Data Toole Yindow Help ax Dsm alkaw como jaz i pome j fm alee re flea P E EH e eo nl g Lo E Seale 454 TOSI anlar Tos 10 Jle A Fox 85 EI l A T 8 566390 Total 1 310TZas Display Eange 35 415H358uz B Paz 120b Bene 7 R 7 6 2i r Conpr Eate Fo EN kiar Filter 714 656114u 13 3365940173 1870 7 6 Fur 18 HH363us 23 Adkas F3 Lda TO 550531uz EL AD3YSTuz TZ TASTE 5 LLLI ELL TULL JUUU UU UU UT m a OEN E Trigger Content Trigger Delay Trigger Fange iF Trigger Fara C Delay T
62. so it is it is the timestamp of data and data s timestamp the timestamp of next data Fig4 89 Packet Length Packet Length From Unknow Start Flag TimeStamp to Unknow End Flag TimeStamp Packet Idling Length From Unknow End Flag TimeStamp to Unknow Start Flag TimeStamp Virtual SS is activated 2 Data needs 8 bit the Idling Time is set as 3us Don t care data bit is not activated EE 3 155us is bigger The Unknow th Idli registers Unknow End F lag 3 575us is bigger than i i i ext dge is the timestamp of the data TMT LT l Packet Length Because the low level _ f f only has 196ns less Mae Qs 1950s x than Idling time T packet ends when the Low level ends 35w 25 Sie Fig4 90 Packet Length Packet Length From Unknow Start Flag TimeStamp to Unknow End Flag TimeStamp Packet Idling Length From Unknow End Flag TimeStamp to Unknow Start Flag TimeStamp Virtual SS is activated 3 Data needs 8 bit the Idling Time is set as 3us Don t care data bit is activated Data s Timestamp is packet s Tinestaap idling time so the nest rising edge is the timestamp of data time however the data s end of the informat ion only capture to the sisth bit so the data is not packet accord vith the virtual condition ofSPI ss the packet ends 3 575us is bigger than 3 155us is bigger than Idling That is the SEE NM M oA Ao
63. the license agreement and click Next Step 6 Enter User and Company names Step 7 Choose the setup type We recommend Complete for most users Step 8 Click Install to confirm settings and begin the actual installation Step 9 Click Finish to complete the installation 18 FMO7IAA Phe PER BR 1 T3 PR 23 nl Zeroplus Technology Co Ltd The Zeroplus Logic Analyzer User s Manual V3 11 Q zeropius Locic Lube Application Setup Driver Setup LAP C Standard InstallShield Wizard Welcome to the InstallShield Wizard for LAP C Standard The InstallShield Wizard will install L amp P C Standard on your computer To continue click Next LAP C Standard InstallShield Wizard InstallShield Wizard Complete Setup has finished installing LAP C_Standard on your computer Yes want to restart my computer now Remove any disks from their drives and then click Finish to complete setup LAP C Standard InstallShield Wizard Ready to Install the Program The wizard is ready to begin installation Installshield LAP C Standard InstallShield Wizard License Agreement Please read the following license agreement carefully LICENSE AGREEMENT software as a package product for certain computer products relevant fe Installshield IMPORTANT READ CAREFULLY This LICENSE AGREEMENT is entered into effect between ZEROPLUS Technology Co Ltd hereinafter ZEROPLUS and Cus
64. to be transferred within a Data Frame It can contain from O to 8 bytes and each contains 8 bits which are transferred MSB first CRC Field 16bits CRC the last is a delimiter and the default is 1 158 FMO7IAA J 7 BE F1 BR 2 T3 ER 23 81 The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Fig4 122 CRC Field Ack Field That is the return signal of Receiver which has 2 bits and the final is a delimiter whose default is 1 If receiving success Ack will send back 0 then the transmitter knows the Receiver has received the data End of Frame 1111111 denotes en Peli Data Frame In the Peli Data frame Data Frame as follows the frame of message is separated into Start of Frame SOB Arbitration Field Control Field Data Field CRC Field Ack Field End of Frame However the parts of Arbitration Field have much more than 18bits and the SRR and IDE are 1 Fig4 123 Peli Data Frame Remote Transmit Request Frame When RTR 1 it denotes Remote Transmit Request Frame at this time DLC3 DLCO are the Data bytes of return data And the frame doesn t have Data Field Fig4 124 Remote Transmit Request Frame 159 FMO7IAA o Pree ie BPR 8l The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Error Frame The Active Error Flag consists of six consecutive Data Field dominant bits Dominant bits violate the law of bit stuffing All bits can produce Error Frame af
65. too far away from the Baud Rate of the test board Step2 Set up Either Edge as the trigger condition on the signals which are connected to the Tx pin or the Rx pin of the tested UART board Step3 Set up the Protocol Analyzer UART dialog box The Protocol Analyzer UART dialog box is set as the steps of I2C PROTOCOL ANALYZER UART X Configuration Facket Data Format Register Pin Assignment Channel Protocol 4nalyzer Property Parity Check Mone Parity D ata E Baud Rate seno C e Length Stop Bit Percentage rox Min Tbps Max 1 Mbps Sample Transmission LSB gt MSB Data Reverse Decoding Direction Protocol Analyzer Color Cancel Default Help Fig 4 74 Protocol Analyzer UART Configuration dialog box Step4 Set the UART Configuration dialog box Pin Assignment UART only needs one channel to decode the signals the default is AO Protocol Analyzer Property Parity Check There are three options on the dropdown menu None Parity Odd Parity and Even Parity and the default is None Parity Data Length Set the Data Length in the range from 1 to 56 Stop Bit Select the Stop Bit from the three options 1 1 5 and 2 and it is stopped in the High Level Percentage Sample Users can select the Percentage from the options 5096 60 70 80 and 90 on the dropdown menu and the default is 70 Transmission Direction Set the Transmission Direction to MS
66. we apologize for any inconvenience caused by the lack of information pertaining to Logic Analyzers We are currently working very hard on multilingual information and documentations pertaining to the Logic Analyzer Visit our website for the latest drivers software and manuals http www zeroplus com tw logic analyzer en technical support php In the meantime we will have updates ready when verified error free OT03 What was the original intention of developing this item A Originally the Logic Analyzer was just for use by our engineering department Later on we saw the greater need for this kind of device We made numerous enhancements and made it available to the public Conclusion This chapter is full of hard facts for engineers The contents of this version of the User Manual may look more different than the one on the web Every engineer finds new problems new solutions or other issues during real life applications Though there are dozens of questions here we look forward to your feedback which is important for future versions It may help us produce more efficient and accurate devices so that we will offer you much better service 208 FMO7IAA Phe AIR Be 2 ARAE Zeroplus Technology Co Ltd 7 Appendix 1 1 Hot Keys 7 2 Contact Us The Zeroplus Logic Analyzer User s Manual V3 11 FMO7IAA Phe AIR Be 2 ARAE Zeroplus Technology Co Ltd Objective The Zeroplus Logic Analyzer User s Manual V3 11 In this
67. write O status continues through to the end of the t DW1 period the signal will convert to high and last throughout the period of t CYCD as shown by the dotted line in the following figure Conversely if it is the write 1 status after t DW1 period of time the signal will rise and last throughout the period of t CYCD which is of 1 bit and ranges from 190us to 260us The t DW1 ranges from 32us to 50us and no more than 50us The t DWO ranges from 80us to 145us j lapi 1 m Cowen a rc Fig4 111 Signal from BQ HDQ to Host 151 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 6 1 Software Basic Setup of Protocol Analyzer HDQ x Configuration Packet Data Format Register Pin Assignment Channel Time Settings us Break iso 1000000 Recover jo ionopon Host 1 fo pii Device 1 jo fo Host 0 so 18 Device D feo hea Host Bit 130 260 Device Bit 130 2000 I Response 799 Remark 1000000 is infinite Protocol Analyzer Color Break Recovery Address Head Write Data Cancel Default Help Fig4 112 Protocol Analyzer HDQ Configuration dialog box Set the HDQ Configuration dialog box Pin Assignment HDQ has only one signal channel therefore it only specifies the name of the channel and marks the selected channel Protocol Analyzer Name Display the name of the selected Bus Channel Pres
68. x 1E iM ie Delay hae 250us 200us dE B T 150us lv T YAU LU LU eo QU UU A 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2 hous 40us 40us 40us 40us S0us 40u 40us 40us 40us 4Cus 40us 40us 40h 80us 30us TOus BOUS 80us 80us 80us E S E 8 s 20 48ms 1 ots y o om LL Xm 000 totems 0000 00000 tm INNEN Oo o C 20 48ms 20 48ms 20 48ms E g nd DEMO Fig 3 1 Software Interface 1 Menu Bar All operations are performed directly from the menu bar including configure label rename execute and stop Pull down menus allow easy navigation through the measurement panel 2 Tool Bar The tool bar is the graphical user interface which can make you work with some of the more common applications From these icons you can change settings and operate the Logic Analyzer easily Note The prompting information of the shortcut keys has been added in the tooltips of the Tool Bar that is to say when users place the cursor on the icons the corresponding shortcut key information will appear For example the prompting information of the New button is New Ctrl N Ctrl N is the Shortcut Key of the function of New 3 Information Bar The Information Bar displays information
69. 0 Modules and it is not available for the LAP 16032U LAP 16064U LAP 16128U LAP C 16032 LAP C 16064 LAP C 16128 and LAP C 162000 Modules 4 12 1 Basic Software Setup of Multi stacked Logic Analyzer Settings STEP 1 Click Tools on the Menu Bar then select amp to activate the function of Multi stacked Logic Analyzer Settings E Customize Color Setting GUS Bus Property a Refresh Protocol 4nalyzer gu Multi stacked Logic Analyzer Settings Analog Waveform k D50 stacked Settings Fig4 168 Multi stacked Logic Analyzer Settings Interface STEP 2 Click amp to open Multi stacked Logic Analyzer Settings dialog box Multi stacked Logic Analyzer Settings X Memory Stack C Channel Stack M4 S N 000000 0000 Synchronous Channel AQ Synchronous Trigger Condition Cancel Help Fig4 169 Multi stacked Logic Analyzer Settings Dialog Box 185 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Activate Stack Click the checkbox to activate the function of the Multi stacked Logic Analyzer the default is non activated Stack Type Users can select the Memory Stack and Channel Stack the default is the Channel Stack Please select the Logic Analyzer for stacking It can display all the connected Logic Analyzers and the S N code of them The M1 indicates the first Logic Analyzer and the M2 indicates the second Logic Analyzer M3
70. 0 FMO7IAA 2P BE HS AR 03 ER 23 8j The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 S Fari BOE ee ra hut ay dee Quee demo d E l E ee ar O s 4 Pee REJ PMugc amp e gH Pg Pupd8B ga PlugInsA Beta io 12 080 E desc iota ag ales He Deer erty Ph Reece Penes B Tu mulis Fig4 33 PluglnsA Bus Property i Color Ganftig x Activate the Latch Function AQ E Rising Edge Protocol Analyzer Setting Protocol Analyzer Parameters Contig i ZEROPLUS LA 1 WIRE MODULE v1 10 0007 MO17 i EROPLLIS L 3 WIRE MODULE v1 04 0C NOT i ZEROPLLIS LA ACSF MODULE v1 02 00607 M01 i ZEROPLUS LA ARITHMETICAL LOGIC MODULE v 1 51 00 CNO1 i EROPLLIS LA BUS MODULE v1 00 0C NOT i z EROPLLIS LA CAM 2 06 MODULE v1 32 0007 M01 i EROPLLIS L CCIR656 MODULE v1 31 006CNO1 i ZEROPLLIS L Compact Flash 4 1 MODULE v1 01 0B0 c NOT i ZEROPLLIS L CMOS IMAGE MODULE v1 00 000 CMOT Se Se ed o AALT T L L EATEN OM DT bla mi m s RIS Find vw Use the DsDp More Protocol Analyzer Fig4 34 Bus Property Every Logic Analyzer Module can provide some basic Protocol Analyzer plugs When users need to use the analysis which is not provided by the basic Protocol Analyzer plugs you can purchase from our company and then you can get this Protocol Analyzer plug and the register code STEP 1 Put the CAN 2 0B Plug
71. 1 It is the covered file that is to say it is a new file 2 It can display the path of the Object File and the file name 3 It can open the Object File by clicking the Open option File to merge 1 It can create the new file with the object file 2 It can display the path of the File to merge and the file name 3 It can open the File to merge by clicking the Open option Refresh Rees Pressing this button can refresh the data status of each Address data when there are some alterations in the Bus Data Reset oem The data status of each Address will be cleaned out and returned to the original status by pressing the button 183 FMO7IAA PRET AR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Display Alteration l l l l l l The Data in the List Window of the Memory Analyzer will be cleared by pressing this button and the List Window will display the alteration status of each cell If the same Address has been written or read repetitively the background of the cell will be gray and the list window will display the Data of the last packet If the Address doesn t have any alteration the Address Data will display the data of the Address without the background color If it is the first time that the Address has been read we confirm that the data of the packet has been altered Al When users input the Address in this Edit Box and click the Find ico
72. 16 Disable 128K channels channels 1 16 2K 32 16 LAP C 321000 2K 1M 32 Available 2M 16 Disable channels channels LAP C 322000 2K 2M 32 Available AM 16 Disable channels channels Task2 Trigger Property Step1 Click 3 icon or click Trigger Property from the Trigger on the Menu Bar The dialog box will appear as shown in Fig 4 4 LAP 32128U A Disable M M 2 LAP 322000U 2K 2M Available LAP C 16032 2K 32K Available mM LAP 321000U A 2 kc E 16 LAP C 16064 2K e4k 16 Available channels 16 6 1M Trigger Property X x Bus Trigger Setup YT dg P Trigger Content Trigger Delay Trigger Range 4 Channel Trigger Setup n Trigger Property j Trigger Mark m Trigger Level Trigger Count ra IE i z Min 1 Max 65535 Dx Dont Gare ter Hight Bir Low we Rising Edge i Falling Edge esa Either Edge Cancel Default Help Fig 4 4 Trigger Property Reset Step2 Trigger Level Setup Click the pull down menu of Trigger Level on Port A B C and D to select the Trigger Level as the voltage level that a trigger source signal must reach before the trigger circuit initiates a sweep Tip There are four commonly used preset voltages for Trigger Level TTL CMOS 5V CMOS 3 3V and ECL Users also can define their own voltage from 6 0V to 6 0V to fit with their DUT if the number users define is not in the range
73. 22000 Standard 3 11 CH01 S 8 000000 0000 1 File Trigger ues Tools Window Tes Scale 1 837051us Display Pos 22T 693289us A Pos 120us v A T 120us Total 20 48ms Display Range 273 619564us B Pos 150us vw B T 150us v Scale 1 837051us Display Pos 227 693289us A Pos 150us A T 150us v Total 20 48ms Display Range 273 619564us B Pos 150us v B T 150us Compr Rate 1 000 Fig4 155 Display the Contrast Results in the Waveform Windows Tip The Data Contrast function is available for the LAP 321000U A LAP 322000U A LAP C 162000 LAP C 321000 and LAP C 322000 Modules and it is not available for the LAP 16032U LAP 16064U LAP 16128U LAP 32128U A LAP C 16032 LAP C 16064 LAP C 16128 and LAP C 32128 Modules 178 FMO7IAA O 2P BETIS RR 2 BPR uj The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 10 Refresh Protocol Analyzer The Refresh Protocol Analyzer function enables the system to analyze the data between Ds and Dp again 4 10 1 Basic Software Setup of Refresh Protocol Analyzer STEP 1 Click Tools on the Menu Bar then select Aj or click Ed on the Tool Bar directly to refresh Protocol Analyzer Customize Color Setting GUS Bus Property E Refresh Protocol Analvz ZE gg Multi stacked Logic TE Settings Analog Waveform k D5O stacked Settings Fig4 156 Refresh Protocol Analyzer STEP 2 Transmit the teste
74. 3 151 x 3 Hew Ctrl H Common Setup Toolbars Shortcut Key Auto Save 2 Open Peeler lEEEMw us P v Activate Close CtrltF4 Bere ee eeeeeeeseenene File Hame lA Save CtrltS Save As Save Path C Documents and Settings Administrator My fin Export Waveform CtrltShi fttE EUREN E Export Packet List Data Display Menu Renewal Mode Time Interval ix Capture Window CtrltC Every Renewal fi z Language Ld 7 Open the first file after stopping the Run amp Print CtrltP Print Preview 1 SPI PLUS Default 2 I2C 3 BDM 4 VP DOWN COUNTER Exit Fig 3 151 1 Auto Save on File Menu Fig 3 151 2 Auto Save Item of Customize Fig 3 151 Auto Save Auto Save The default is not activated after activating it keeps working and users also can choose Cancel to close it Activate The default is not activated after activating it keeps active and users also can choose Cancel to close it File Name Before users name the file the file name is defaulted as LA In fact the saved file name can add a serial number for the file automatically Save Path Name Users can enter the path directly or choose the path from the selected path button uiia Time Interval When the auto save function is activated the time interval from one finished sampling to the next activated sampling can be set according to users requirements the defau
75. 35 Threshold Working _6V 6V Voltage increasing T u 3 Free T LED Operating Interface Chinese Si Chinese Tr English Language Time Base 5ps 10M Sizing ane ree ups ME Eo p mis Software Waveform Width Yes Function Display Trigger Page 1 8192Page Pulse Width Free Trigger Latch Dala Option Free Option Free Contrast p P pes D o Free 13 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Analyzer Settings Protocol Analyzer Option Free Trigger Safety Certification FCC CE WEEE RoHS 1 4 System Requirements This section discusses basic operating system and hardware requirements for the Logic Analyzer Software and hardware capabilities may vary depending on PC configuration This manual assumes proper installation of a supported operating system as listed below 1 4 4 Operating System Requirements e Windows 2000 e Windows NT 4 0 Workstation amp Server Professional Server Family Service Pack 6 e Windows XP e Windows Server 2003 Operating System Home Professional Editions 32 Bit version Name e Windows VISTA 32 Bit and 64 Bit version e Windows 7 32 Bit and 64 Bit version 1 4 2 Hardware System Requirements Hardware Name Lowest Configuration Recommended Configuration CPU 166 MHz 900 MHz VGA Display Capability with VGA Display Capability with 1024x768 resolution or higher 1024x768 resolut
76. 40 The Zeroplus Logic Analyzer User s Manual V3 11 Set the trigger condition as Either Edge See Section 4 1 for detailed instructions Reset the trigger condition x Trigger Content Trigger Delay Trigger Range Trigger Level Trigger Count Port ss i MIE IV Port B Min 1 Max 65535 TTL fi 5 v Port C TTL f 5 v Port D TTL jf 5 v Cancel Default Help Fig 3 33 Set Trigger Content See Section 4 1 for detailed instructions Trigger Level The voltage level that a trigger source signal must reach before the trigger circuit initiates a sweep There are 4 ports available each port has the ability to assign different voltages to meet the users requirements Use the pull down menu to choose between TTL default TTL CMOS 5V CMOS 3 3V ECL and User Defined choose the value of the Trigger Level 6 0V to 6 0 V Fig 3 34 Trigger Position Trigger Page Trigger Count 1 Represents the Trigger Position of a memory page 2 Represents the Trigger Page 3 Represents the Trigger Count x Trigger Content Trigger Delay Trigger Range C Delay Time and Clock Trigger Page Trigger Delay Time fi 10us Min 1 Max 8192 Min 10us Max 167 761313 Trigger Position Trigger Delay Clock i 50 z Min 1 Max 15775131 T Pos Ons Start Pos 10 23ms End Pos 10 25ms Not
77. 64497 B T 64497 v Compr Rate No Bus Signal Trager Fiter suai Sue 207 465 69 s 67 836 205487 313 138 480788 618439 75609 893741 1031 38 F Y am wj oxi Yoxs oxi L A e0 x ga Bus Trigger Analyzer Trigger a2 Bus Name Operator Value A3 A Bust 2l A4 e Data Format gas 4 C Binary C Decimal C Decimal Signed 6 4 Hexadecimal ASCII C Gray Code vua E Complement g BOE 430 1 e B2 Cancel Default Help Fig 4 32 Bus Trigger Setup 4 3 Plug Analysis Plug Introduction Protocol Analyzer operates in the form of Plug every Protocol Analyzer has a plug per plug is independence modularization One Protocol Analyzer plug can analyze many Buses at the same time however because the independence of every plug the Protocol Analyzer plug only supports I2C UART SPI HDQ 1 WIRE CAN 2 0B at present In the future it will support more Buses and when the Protocol Analyzer renews it only needs to download the new Protocol Analyzer plug to cover the old Protocol Analyzer plug the speed is very fast Operating Instructions There are Plugins data file in the position of installing LA software All Protocol Analyzer plugs which are used at present are put in the data file the DLL file can be added or deleted in the content and in the Bus property all Protocol Analyzer plugs that can be used at present can be seen as the figure below 11
78. 7 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms Group into Bus Ungroup from Bus 167 695ms 167 695ns 167 695ns Be Sena 7 ez cone E s d j eai E E Fig4 115 Group into Bus Select Bus Property W ZEROPLUS LAP 32128U A Standard 3 11 CHO1 S H 000000 0000 HDQ SET 13 442ms MIN 13 528ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms BEN 2 xi af l L piled DA IKI j d o Beat mm 7 83 884ms i spie trli Fig4 116 Bus Property 154 FM0714A Phe PER BR D 3 P 23 nl Zeroplus Technology Co Ltd User s Manual V3 11 The Zeroplus Logic Analyzer 155 Select the decoding function of the protocol analyzer HDQ and select OK to confirm Bus Property Ld 13 442ms 13 528ms Activate the Latch Function ZEROPLUS LA DSI Bus MODULE 1 01 00 CNO1 ZEROPLUS L FWH MODULE V1 00 00 CM02 ZEROPLUS LA GPIB MODULE V1 00 00 CNO1 ZEROPLUS L HDQ MODULE 2 07 00 CNO1 ZEROPLUS LA HPI MODULE V1 01 00 CN01 ZEROPLUS LA I2C EEPROM 24LCS61 24LC562 MODULE 1 00 00 CNO1 i ZEROPLUS LA I2C EEPROM 24L MODULE V1 31 00 CN01 ZEROPLUS LA I2C MODULE V2 02 00 CN01 ow TTD IET A TOC RAS 4 40 oO TRIS 167 695ms 442 2 OIE e e A me 7 Fig4 117 Protocol Analyzer HDQ Setup
79. A CMOS IMAGE MODULE v1 00 00 CNO1 ICO AOL gw A PA ALT Te be nC se RATIS a 04 CO TRIS v Use the DsDp Find More Protocol Analyzer Fig 3 79 Find Editor Box When you input I in the Find editor box the Protocol Analyzer list displays all Protocol Analyzers with the initial character of I see the below picture Bus Property xj Golor Config Activate the Latch Function 40 Rising Edge Protocol Analyzer Setting Protocol Analyzer Parameters Config c ZEROPLUS LA I2C EEPROM 24LC561 24LC562 MODULE V1 00 00 CNO1 c ZEROPLUS LA I2C EEPROM 24L MODULE V1 31 00 CNO1 c ZEROPLUS LA I2C MODULE Vv2 02 00 CNO01 c ZEROPLUS LA 125 MODULE V1 13 00 CNO01 c ZEROPLUS LA 1507816 UART MODULE Vv1 02 00 CNO1 v Use the DsDp More Protocol Analyzer cancel Hep Fig 3 80 Find Result 4 Refresh Protocol Analyzer Refresh Protocol Analyzer data See Section 4 10 for detailed instructions FM0714A 2 RE AFH AS 1 BBR BS Zeroplus Technology Co Ltd gu Multi stacked Logic Analyzer Settings Analog Waveform m Single Analog Display Mixed Analog Display Tip When the function of Analog Waveform is activated the Analog Waveform will be displayed in the waveform area of the Bus s sub channel and take the space of four channels And four sub channels won t draw the waveform It notes that the sub channel of the Bus must be more than four channels 60
80. A GRRE DATA o XEM SL 1O BuslQzc wras A ACK D ACK 45 D ACK Packet amp Nare Timestamp ADDRESS Write se DATA Pesce DATA Do ee Do Tone Do lora Mane imestan ADRES rax MAE DATA aS UES iman RE aA DATA RR CATA ETE DATA TEENAGE E HINT RET HE HIT NEM Packet F Hane Timeztamp ADDPESS 4 Bued pa Warns 5 Bea 20 a F Fre DATA MA Packet Mame Timestamp Write AAE DATA RR DATA Hoe DATA E TAR DATA DAE ELNMLCONEICENONEI E lou os foax NOICNN CON EDS Isl Fig4 71 Protocol Analyzer I2C Packet List Packet1 It is commonly normal data which includes 1 Address and 6 Data Packet2 It is commonly normal data which includes 1 Address and 6 Data Packet3 It is commonly normal data which includes 1 Address and 14 Data Packet4 It is commonly normal data which includes 1 Address and 6 Data Packet Length When judging the start of I2C it is the Packet TimeStamp This Data Start is regarded This Unk T Tonnen is now register ls Packet od Unknow End Flag I2C T ADDRESS 0x50 WRA DaTA oxss ech sm SPA LUT 1 SCL Packet Length Fig4 72 Packet Length Packet Length From START Start s TimeStamp to STOP Unknow End Flag TimeStamp 128 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Packet Idling Length From Unknow End Flag TimeStamp to Start s TimeStamp
81. A Pos 120 98us v A T 8 266KHz v A B 3 333MHz v Total 1 31072ms Display Range 101 797465us B Pos 120 88us v B T 8 286KHz v Compr Rate Ho Bus Signal Filter 1 1 gao o ah xk d Ai l 2 212 C A3 A3 A4 A4 g 45 45 g 6 6 7 47 Sz BO B0 S Fig 4 7 Trigger Count Screen Shot 1 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 We ZEROPLUS LAP C 32128 Standard 3 11 CHO1 S H 00000000001 LaDoci Nim x a File Bus Signal Trigger Run Stop Data Tools Window Help l x Demla i AN EB p 128K z sie h 00MH x aw w10 vje 9 Page fi d j E 7 Sc ll 1 134396ur 6 R ae Ay Be Te be BB le ol oll o o Height 30 gt Trigger Dery rne Scale 881 526KHz Display Pos 6 120116us A Pos 120 98us v A T 8 266KHz v A B 3 333MHz v Total 1 310T2ms Display Range 22 239786us B Pos 120 68us v B T 8 286KHz M Compr Rate No Bus Signal n 18 Ser80Sus 10 835824us 5 223843 fast ops 84ns6 120118us il 792093us 17 46408us 23 136061us 28 808042us 34 4800238 gaoa wl g Al l A2 A2 A3 A At A4 w 45 45 g 6 4 P 7 47 B0 50 Fig 4 8 Trigger Count Screen Shot 2 Step4 Trigger Page Delay Time and Clock The Trigger Page and the Delay Time and Clock can t be applied at the
82. A3 a5 n 3G Either Edge g a4 a4 eua Color Fig 4 22 Left Click on Trigger Fig 4 23 Right Click on Trigger E Bus Trigger Setup Channel Trigger Setup Ji Trigger Property x Dont Care High Los Low ff Rising Edge Falling Edge X Either Edge Color Fig 4 24 Trigger Menu 106 FMO7IAA 2P BETIS HE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Task 5 Run to Acquire Data 1 Single Run Click the Single Run icon from the Tool Bar or press START button on the top of the Logic Analyzer or press F5 then activate the signal from the DUT to the Logic Analyzer to acquire the data shown in the waveform display area 2 Repetitive Run Click the Repetitive Run icon from the Tool Bar then activate continuous signal to the Logic Analyzer to acquire the repetitive data and then click the Stop icon to end the repetitive run Tip Click icon to view all the data and then select the waveform analysis tools to analyze the waveforms ITE AP C 377000 Standard V3 1 1 CN01 5 000000 0000 LaDocz J0 xj a De Saa Toa Runlgop Dita Took Window Hep ll xi Dee xwassmsZ ieb m x sex se Page fi Count fi i E 3 h hi W a I 1 80224ms XM T e E Ln i B le l m 5 Height 22 j Trager Delay 4 us Scale 554 B65Hz Display Pos Ons APos 600us A Tz1667KHr A Bz833333Hf Tot i 81 92m5 Display R
83. Area Fig3 157 presents how to change colors of a signal or some signals Repeat the following procedures if users need to change colors of many signals Step 2 Step 3 Step 1 Color Setting Workaround oly proe Cancel Default Help al 4 Fig 3 157 Stepwise Illustration of Changing Waveform Colors Step 1 Select several Optional Items Step 2 Select the corresponding items in the relating Step 3 Choose a color by following the method shown in Fig 3 157 Step 4 Click OK to change their colors into the same for example A1 A2 A3 and A4 Here is a sample of an altered Logic Analyzer software interface which will be used for further demonstrations in subsequent chapters See Fig 3 158 ET LCR P Lae mill Aj M Md uc Eee Ds Rb Wie RD abit x Qul CEI fas b a JLE EAE M sjicom sj mH ik 5g z Bs ahi oO E ferr p 24a Batya L1 wi ee E wa wa P Fig 3 158 An Altered Interface Sample to Be Used in Subsequent Chapters 93 FMO7IAA 2P BETIS RR 2 BPR uj The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 3 7 The Flow of Software Operation M o7 pelyTimeClek 7 Tani Lin a _ ft wo om Trigger Page hg I talec Analysis Finictioti Trigger Position 50 Hip Eh Trigger Count Activate Signal from Testing Hard UART Bus Analysis Acquire Wavefa SPI Bus An
84. B gt LSB or LSB gt MSB Bus 5ignal Y Bus UART e an 40 g 1 l 42 a2 Busy Signal v Busi UART ar A 40 UUU pag 2574 LS LIL 82 n DL E Fig 4 75 Data Waveforms MSB gt LSB and LSB gt MSB Baud Rate The dropdown menu has options as below 110 300 600 1200 2400 4800 9600 19200 131 FMO7IAA 2P BETIS AR ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 38400 57600 115200 230400 460800 and 921600 Users can select the desired value from the menu At the same time The Auto can be selected to calculate the Baud Rate automatically If the Auto is selected the Baud Rate will be calculated and displayed on the Configuration dialog box automatically Data Reverse Decoding When the option is selected the data will be decoded in reverse Bus 5Signal v Busi UART AD 0 Bus Signal Trigger W Busl UART 40 40 Using the reverse data level to decode Fig 4 76 Without With the Reverse Data Level for Decoding Protocol Analyzer Color Users can vary the colors of the decoded packet Step5 Press OK to exit the dialog box of Protocol Analyzer UART Step6 Click Run to acquire the UART signal from the tested UART circuit Refer to Fig 4 77 Tip Click gt ZEROPLUS LAP C 32128 Standard 3 11 CNO1 S N 000000 0000 UART E C x File Bus Signal Trigger Run Stop Data Tools Window Help 81 x Dc Bl
85. E EBRBSEIOBIIBTIZEI BIA ET BOBI B BH Fig 3 12 Pure Data Form BE Capture Window Capture En Mate Clipboard MsPaint Capture Region Ful Screen Select Region Z Select Line Color m Color af Ehe Mate gt M Opposite of Color Fig 3 13 Capture Window This feature is equivalent to Alt Print Screen or Print Screen Capture to File Save the captured image as either a jpeg or bmp Clipboard Copy the captured image to the clipboard for use in other applications MsPaint Directly start MsPaint to view the captured image Capture Region Full Screen Capture everything on the screen Select Region After pressing the capture button a cross hair will appear on the screen Left click the mouse button to drag an area to capture FMO7IAA 2P BE HS BR 03 ER 23 S The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Language d g Print Ctrl F Tip This function has been enhanced now users can select the pages which they want to print or only the Current Page Print Preview Select Line Color Click the color box to change the color Opposite of Color Click this check box to ensure that the note text will be the opposite of the line color Color of the Note Choose the color of the note text Note Type in a note to attach to the captured image Capture Click the button to capture the image
86. E5 5d ni Jl 78 603ms ol mii 4 gt 1 x E 5 lt gt gt Option Import Export _Merae _ Refresh Reset Display Alteration Bus1 I2C Write data Read data re Address Data _ Address Data _ Address Data Address Data Address Data Address Data Address Data _ Address Data Address Unused 0X00 0X4F oxso Oxoo mugs 0x52 Oxeo oxs3 OKAB OxCD 0x55 OMER oxs Oxs7 0x58 Unused 0X60 0X7F Fig4 167 Memory Analyzer Display FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 12 Multi stacked Logic Analyzer Settings The function of the Multi stacked Logic Analyzer Settings is mainly for connecting the hardware of many Logic Analyzers which are the same type and then use the software to stack the Logic Analyzers which are working independently It can improve the functions of the Logic Analyzer which are mainly manifested in two aspects expanding the RAM Size and adding the number of the test channels Tip 1 The max number of the Multi stacked Logic Analyzers is four The RAM Size of the four Logic Analyzers can reach to 128K 4 and the test channels of the four Logic Analyzers can reach to 32 4 2 The function of the Multi stacked Logic Analyzer Settings is available for the LAP 32128U A LAP 321000U A LAP 322000U A LAP C 32128 LAP C 321000 and LAP C 32200
87. LAP OTID Seni VAI DIL ais at mund te foie Dee Des eee I aifti x E E 448 46 2B P oi o o amp mee j s eo 4 Page ow f E RES HOD Me Priim JR sELDLA Go ew o o iTop Dey 5 Sta 294 4111 Draper Pet Pos 19ra amp Te 12200 wee Wwe Tta Tatai 10 Mus oiin Ts oTi casas amp Teti tie Compe R ate his Fig 3 83 Mixed Analog Display x Channel V Div Setting D5O CHl wjDiv B IDiv D5O CH ViDiv zvibis D5O CH3 wjDiv B IDiv D5O CH4 ViDiv zvtbis Channel Setting only display D50 M psocHi M pso cH2 M DSO_CHS M pso cH 4 Channel Height Setting D5O CH1 Height po D50 CH2 Height eo D5O CH3 Height eo D5O CH4 Height ao bso settings OK Cancel Channel V Div Setting Users can select the Options 3V Div 2V Div 1V Div 500mV Div 200mV Div 100mV Div 50mV Div 20mV Div omV Div and 2mV Div Channel Setting Users can set the DS0 CH 1 DS0 CH2 DS0 CH2 DSO CH4 the captured waveform will be displayed on the LA Software meanwhile the color of CH can be changed When selecting the item Only display DSO only the activated DSO CH can be displayed on the waveform The AO A7 can t be displayed see as below figure FMO7IAA 2P BETIS HR 0 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 LI LIRE ced Le Ali eR LIMIT i nl EMT tee hapa pe Aaa Dae lxk quum eds Lit n Dal d xu kW x dhi is ej om ea scam xi pee
88. M Size 120 s in Fig 4 3 LAP C 16064 Modules GR CF Note Sampling RAM Size RAM Size limited to 16 Exter 256K m Channel number will be or from the pull down menu in the Sampling Setup dialog box as shown x You have selected the Double Mode Port C Port D and the functions of Compression Signal Filter Delay and Signal Filter Display Bar are not available under this mode Don t show me this warning again Fig 4 3 RAM Size Tips 1 The Double Mode is available for the Modules in Table 4 1 except for the LAP C 16032 2 The relationship between RAM Size Signal Filter Mode Compression Mode and Channels as shown in Table 4 1 and Fig 4 3 Table 4 1 RAM Size vs Signal Filter Mode and RAM Size vs Compression Mode and Channels Normal Mode Double Mode RAM RAM Size Channels Model No LAP been Channels Available Compression Mode amp Signal Filter Mode Size nd Compression Mode amp Signal Filter Mode Channels Available 16 16 16 LAP 16064U 2K 64K Searels Available 128K channels Disable 2K 16 16 l LAP 16128U 128K damek Available 256K dirae Disable 97 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 2K 32 16 128K channels Available 256K channels 3 Available 2 16 Disable channels channels 3 16 LAP C 16128 2K Available 256K
89. ME amp ae oo EE o r Arco 50 He Pup DOM Group into Bus ChrlHG Niobe Tha itornal ie voltage lend int th damus i Hus pese A rigen lene Ungroup from Bus Etri PAM uw Compnevunn Mida ya Fb er Espar Format Row aaia E T ate Compress Spal Hor Seb Gollapse Rename Charra rakar wilbe us Format Row k RTENE Less S eee i Signal Filter Setup d E x Trigger condition Porta E Filter Condition Trigger Condition Filter Condition Trigger condition Patt Filter Condition Trigger Condition ilter Condition Filter Delay Setup vw Activate Filter Delay Select Filter Delay Mode Select Delay Start Point Delay Time According to Filter Condition f Start Edge 100ns End Edge Min 100s Opposite of Filter Condition C Period Delay Max 6 553ms Display Bar Setup Bar Style Original Bar Width 100ns OK Cancel Restore Defaults e e Fig 4 139 Signal Filter Setup Set the high level as Filter Condition on the signal A1 Step4 Signal Filter Setup 1 Setup the Filter Condition as or on the signal to be analyzed 2 Click OK then click Run to activate the signal from the tested circuit to the Logic Analyzer 169 FMO7IAA BE 32S BPR 8l The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 3 The system will display only the waveforms of the aid iai are by the Filter Condition BusSigna T
90. MO7IAA 19 Phe AR AR BPR Zeroplus Technology Co Ltd Scale 5 B5538525 Total 32TB58 Y ean 40 Bus eA Al BAZ A2 BA a3 aq A4 was 55 46 46 a ar e BO 50 Bi El g B2 B2 g B3 B3 g B4 B4 T Display Fas 0 Display Range 141 143 Fig 3 130 The B Bar is placed at the 0X12 of Data of Protocol Analyzer SPI where the condition of the Waveform Find is set A Fos 104 B Pos 0 113 0T73 84 8 3 56 54 28 2T l Doo i LIII Di n 0 nmn pg MINIEEENEUEEUEENNEEEELLLLLLLLLLLLAG A6GL SLUL L LIALG as Taveftors Find Activate the Function of Chain Data Find E N Next Previous Clase a ET me mede JE J mmm E if Stark AE End AE when Found statistics m Address 0 The Zeroplus Logic Analyzer User s Manual V3 11 A T 104 keys il 28 2T 56 54 24 309 13 0 l D n n qn Epor og AURI LLLA YUU MTM ERI FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 3 3 Statistics Feature Section 3 3 presents detailed information on the Statistics feature in the software interface The Statistics feature presents user information pertaining to nine periodicities Full Period Positive Period Negative Period Conditional Full Period Conditional Positive Period Conditional Negative Period Start Pos End Pos and Selected Data Click on the Stat
91. Navigator Window users can click the Left Key of the mouse to select the waveform randomly The selected waveform keeps pace with the waveform in the waveform display area The size of the selection frame is in inverse proportion to the Zoom Rate the larger the The Zeroplus Logic Analyzer User s Manual V3 11 TI H iad FA H 3E Bhp ae eed ogee Ines nac ne aH ey Oe Se BAN Fh ao apom few le ee ft elcome fF CE EE i fa EE TA E a Hegi ro Br ee Se Dr Erkbiin Pik amp Ta T3 dida As len GT Tem Vd Muri Coin agar DIE pesti B Ts eee Corer Pala Fas bera a Fig 3 92 Navigator Window under the waveform display area m 1 ie Fl BE MER Malet E ICH xj E V Mn RARE AX ETE EE I D SRA comm Ao alom j few aaj com fF mgSAUOGE Mm hes ru RELL Awe Mega ro E vage J Haw DOOR d Orie Pis A pr Xi A Ts StL A IINE Tebs ai Craps Pipes piai Fii e uL B TalllEMEeG Coma Palas Fin BR ol cU lll HU 8 Nc HRS S GE Zoom Rate is the smaller the size of the selection frame is Users can also click the Right Key of the mouse to select the displayed channel Fig3 93 Blue Frame in the Navigator Window There is a blue frame in the above Navigator Window Users can click the Left Key of the mouse to select the waveform randomly ullis Sure de OLE ap r 1 ajoi jj De bamya lyme Pagi Gate le dem He olf xi Dem ee Sn jo d pi eje i jo aj ca i CCEE Ee EEr Mes Maga 9 reper con Esm
92. O D7 lt or external modules or devices not designated to be analyzed For transmitting signals ta_ activate other instruments For connecting the External Clock Fig 1 14 Side View of the Zeroplus Logic Analyzer LAP C Series FMO7IAA 10 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Table 1 24 List of Functional Pins in Each Model LAP LAP LAP LAP LAP LAP ma 16032U 16064U 16128U 32128U A 32100U A 322000U A Port A EA o oo o c Port B BO B7 ER Table 1 2B List of Functional Pins in Each Model LAP C LAP C LAP C LAP C LAP C LAP C LAP C 16032 16064 16128 162000 32128 321000 322000 Port A us Port B am EB O UO a O lt a o O L Table1 3 Definitions and Functions of Pins for All Models Connect a given external module to be analyzed Two pins used for grounding the Logic Analyzer with a given Ground external module to be analyzed Table1 4 Definitions and Functions of Pins for Advanced Models 1 When the Logic Analyzer is about to upload data from the Read Out memory to the PC the R O will send a Rising Edge signal of DC3 3V When the upload is finished a Falling Edge signal is sent When a trigger condition is established the T O will send a T O Trigger Out Rising Edge signal of DC3 3V When the memory is full a Falling Edge signal is sent
93. R Fig 3 132 Logic Analyzer with Statistics Enabled There are four options for adjusting how statistical information may be presented These four options are Channel Selection Column Selection Condition Parameter and Warning Parameter Channel Selection x X ow FS aoa q I o qn q Xo Port Port B I xI xI I xI xI xI xl Ptc v VM v iv iviv iv IN Bar D pe C Fs e de ope e ep e e Port Ep oa es o pr Us proba es ons Ports qo ST ps s n s os Bore qus oes foes Sys jm ges ege ous oos Pot bets es copa opes Dos ies om E port Tested 2o oops vts Es us es Os pat xou s phe Poo is oes Css oq Port spa aa HESS ops oes Doe Os poret Es Os ss Dou LORS os s Poe parem T S SES OS LE ES EE pee port Neg fa S ee Ee Poe port cog E ES is ES S an Pap Te Duis Ale Dos es ors espe E i clear all OK Cancel Fig 3 133 Channel Selection Allow the choice of pins in which port will be included in the statistical analysis of a test run 80 FM0714A 2P BETIS HE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Column Selection Column Selection X Positive Period Jw Negative Period Jw Conditional Full Period Conditional Positive Period Conditional Negative Period Jw Start Pos End Pos Selected Data caa Fig 3 134 Column Selection Allow the choice of items which will be considered in the statistical results Conditi
94. R a Eh gd lol d ld etl Fi v d oy od FF FF M Ft FF oto uuuuuuuuuuuuuuuuuuuuuuuul Fig3 117 Add a Bar on the Waveform Area FMO7IAA 76 2P BETIS AR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 3 2 Find Data Value Find Data Value is a very useful tool to help the user to find data on the received signals Step1 Click the find data value pi icon the dialog box of Waveform Find will appear Step2 Using the pull down menu select the Bus Signal Name The Bus Signals listed on the pull down menu represent the status of the Bus Signal column as shown in Fig 3 118 Fig 3 118 Step3 Choose the character for Find The list of characters depends on whether it is a Bus Signal or the protocol analyzer such as I2C UART SPI etc which is being searched See Figs 3 119 3 120 3 121 3 122 3 123 3 124 3 125 3 126 and 3 127 Bus Choose among In Range and Not In Range Enter the Min Value or Max Value Protocol Analyzer Choose the segments bits of the protocol analyzer Select the protocol analyzer item and enter the value for Min Value or Max Value Signal Choose among Rising Edge Falling Edge Either Edge High or Low Waveform Find El Waveform Find x Activate the Function of Ghain Data Find Activate the Function of chain Data Find Bus Signal Name Fist Gigi pal Ha q Mext Previous Close jJ v Next Previous Close Min
95. RGO04A RGO5 RGO6 RGO07 RGO8 206 2P BETIS AR ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 6 3 Registration What is the significance of the hardware serial number Every product is assigned and engraved with a unique serial number which allows us to trace the original manufacturing date of a specific product How dol register online Visit our homepage at http www zeroplus com tw Choose the Instrument Department and click on English Once you finish membership registration proceeding with product registration After finishing product registration you will receive an email consisting of your product registration information A password may be required for further customer services and other inquiries What should I do if online registration fails Do a screen grab of the window including the error message and email our customer service dept A customer service representative will be glad to assist you as soon as possible once the email is correctly received How may register if the purchasing date was more than one month ago In this case fill in the registration card and send it via post fax or email to our customer service dept and a representative will process the registration for you What is the warranty length for my product A two year FACTORY WARRANTY is offered in which you will have to send the defective product to the closest branch an authorized ser
96. S LA Compact Flash 4 1 MODULE v1 01 000 CMO1 ZEROPLUS LA CMOS pida MODULE 1 00 00 CNO1 eee ee TT BRASS M ET 06104 ma mund RI Find v Use the Dstop More Protocol Analyzer Fig4 63 Activate the Latch Function The picture of the waveform analysis V5 zEROPLLES LAP C 3Z 120 Standard V3 1 LUCRO T 5 00000 0000 Lato 2 IEEE Ter Tue ae pres ape IDEST adigi xl Ota d d NSSSE D m meu ee 4 Pags 1 Count f JE BI 5 uod E Ems ET SERRE Be E Height 2 Trigger Delay 10s Siaa JOH Display Pasina A Pia Sima F z amp B5BTIHT F A BHz1333Hz F Totar20 485 Display Range A25m amp s l4 ma BPosl50mis x us BEBTHE Compr RaMcNa us cigeal Trigger Pe E 45 40 r 5 y 15 E 2 T am MT ox Yoox Y Qx ta x 7 Y Ux x ed s f LE x a c m Lf LfP1 1 L Lf 1 F1 wee AL Al Ls m l J Ld 1 E x em xm x ea a cs os a c PERCENT Ft ng J Es Fig4 64 The Latch Function Displayed on the Waveform Area Illustration The selected channel is AO the analysis mode is Rising Edge it indicates that the data of the AO is read at the Rising Edge See the T Bar in the above figure the data of Bus1 is OX3 123 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 2 12C Analysis I2C Introduction The I2C which stands for Inter Integrated Ci
97. Setting Refresh Exp ameter T ck Name TimeStamp 4DDRESS Write 4 ACK DATA DACKE DATA DACKE DATA DFACK DATA DPACK DATA D ACK Bee Per Tego s 50 write A Ack o oac 75 D AcK or oac 23 Dack 45 Dack DATA 67 D ACK Packet Name TimeStamp DDRESS Write A ACK DATA BBSeACKO DATA FDAK UTER ee f so write aac 00 o a 75 D ACK c Name TimeStarnp Z DDRESS Read 4 A4ck DATA DDIR DESCRIBE 3 Busi1 2c _ 10 2982ms MT so Read A ACK D NACK DATA NACK DDRESS Read A4 ACK DATA c DATA PODACI DATA DANACK DESCRIBE f so Read a ack 23 oac 45 D AcK 67 D NACK DATA NACK E Name TimeStamp 4 _ Busi 2c _ 10 3554ms_ Packet Name TimeStamp 4DDRESS Write A ACK DATA nua qM EES o DATA P 5 eusiqecy 20 477ms J so write aa oo D AcK 79 oac 89 D ACK AB D ACK CD D ACK DATA DCK E Fig4 43 TimeStamp Tip When the Display Bar of Signal Filter is activated the Bar should be displayed in the Bus Packet List and also the TimeStamp ADDRESS and length of the Bar will be displayed 3 Packet Idle and Packet Length Packet Idle Packet interval time Packet Length Packet time length When those above two items are to be displayed it only chooses one of them to display which is controlled by Plug Because it is impossible that every Protocol Analyzer packet has registered timestamp and end we add two
98. Stop Data Tools Window Help 18 x OS S fi ok Elp o af Oy Be Te te Mb e 2 Scale 9 T36541us Display Pos 194 T30814us A Pos 8T 851299us v A T 87 851299us v B 16 182424us v Total 167 69579ms Display Range 48 682703us B Pos 104 033724us v B T 104 033724us v Compr Rate 255 883 43 682703us 3T 36540Tus 146 04811us 134 730814u 243 413517u 292 096221u 340 778324u 383 461628u438 14433 j uU U UL JLIULI LJ LLL LE UU LIL 4 pn Fig4 134 CAN 2 0B Decoding 165 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 7 2 X Protocol Analyzer CAN 2 0B Packet Analysis PROTOCOL ANALYZER CAN 2 06 x Configuration Facket Data Format Register Item Iv ID m Iv NACK W Describe xl a EE Ca o a Cancel Default Help Fig4 135 Protocol Analyzer CAN 2 0B Packet dialog box Packet color can be varied by users The Packet displays with the waveform as below V ZEROPLUS LAP C 32128 Standard 3 11 CHO1 S N 000000 0000 CAH2 0B Oj x a File Bus Signal Trigger Run Stop Data Tools Window Help 18 x jae ll amp gy gk GT of esl gt Dd 128K Jr 200MHz v au 10 ie gt Page fi v Count ji ee TEE 9 736541u 7 4 R ae Be BY I6 ke B le o ES e Height Trigger Delay 5ns_ Scale 9 T36541us Display Pos 194 T30814us A Pos 87 851299us v A T 87
99. T I a1 20 Cancel Default Help Fig4 104 Protocol Analyzer 1 WIRE Transmission Direction Setup STEP 4 Set the Sampling Position Users can slightly adjust the sampling position of 1 WIRE This feature is applicable when the signal cannot be decoded The default value is 30us 147 FM0714A 3 P RET FRAR 1 BPR 8l The Zeroplus Logic Analyzer J Zeroplus Technology Co Ltd User s Manual V3 11 PROTOCOL ANALYZER 1 WIRE Fig4 105 Protocol Analyzer 1 WIRE Sampling Position Setup STEP 5 Set the Data Length This function decides how many bits of data can be combined as one set of figures The default is 8 bits and the maximum is 32bits PROTOCOL ANALYZER 1 WIRE Fig4 106 Protocol Analyzer 1 WIRE Data Length Setup 148 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 5 2 Protocol Analyzer 1 WIRE Packet Analysis PROTOCOL ANALYZER 1 WIRE X Configuration Packet Data Format Register Item Color W Describe O Cancel Default Help Fig4 107 Protocol Analyzer 1 WIRE Packet dialog box That is the new View the below View includes several formats that 1 WIRE can happen it describes Data number and their positions 149 BUS Packet List xj Setting Refresh Export Synch Parameter Packet Name TimeStamp Data 1 Bus 1 WIRE 4032363 33 96 30 96 03 90 02 48 B7 FF FF FF FF FF FF 04 00 P
100. Trigger Run Stop Data amg eag Min 0 001Hz Max 100MHz mc E Sampling Setup Note The external clock voltage level is the same as the port A trigger level E Ww Channels Setup a Signal Filter Setup Scale eee Compression Mode Signal Filter Tatal Group into Bus Ctrl t ae Sine x s r 2K Data Compression Ungroup fron Bus tri Signal Filter Setup ES Channel number will be 4 Expand limited to 32 Collapse 48 B Format Row d Apply Cancel Restore Defaults Help Rename Fig 4 137 Compression Mode Step4 Click Run and then activate the signal from the tested circuit to acquire the result on the waveform display area Fig 4 138 shows the result before and after compression has been applied V ZEROPLUS LAP C 32128 Standard 3 lt c 01 S N 00000000001 LaDoci BI x File Bus Signal Trigger Run Stop Djta Tools Window Help 8 x De S im A9 Sem zx vlei fomi v as mm 50 ie ss Page 1 T Comt fi ell aed ag is b dE ad BE 10s un aw fx Bo Tx i BA le gt Hl Height v Trigger Dela Uns Scale 10ns Display Pos Ons A Pos 150ns D A T 150ns v B 300ns v Total 20 48us Display Range 250ns 2TOns B Pos 150ns v B T 150ns v Compr Rate No 5 ns 100ns 1 F 200ns m Lu 1 1 Lu 1 Lu Lu L Lu il 1 Lu 1 Lu 1 Lu Li Trigger Filter 200ns 0 100ns 50ns i i i i 1 i i i
101. ULE v1 01 00 CNO01 ZEROPLUS LA CMOS IMAGE MODULE V1 00 00 CMO1 ws MAMII A AMAIT Mam HM m my y T v Use the DsDp More Protocol Analyzer Bus Property V2 02 00 CNO1 Next click Parameters Configuration The following image will appear FMO7IAA X 126 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 x f Configuration Timing Packet Data Format Register Pin Assignment Data Mode Item Name Data Length EC E SlveAdd Address 7 bi SCL A1 E Reg ddr Reg ddr 8 bit Data Data 8 bit Protocol Analyzer Property Write Bit Low Level Don t stop analyzing when NACK appears ACK v Low Level Add the Read Write Bit for Slave Address m Protocol Analyzer Color Start Data Slave Addr Read Write Reg Addr ACK A NACK D ACK D NACK Stop Cancel Default Help Fig 4 67 Protocol Analyzer I2C Configuration dialog box Step6 Set the I2C Configuration dialog box Pin Assignment SDA Channel It is the Data channel and the default is AO SCL Channel It is the Clock channel and the default is A1 Data Mode Set the Data Length used by the Slave Addr and the Data Protocol Analyzer Property Set the Write Bit or Read Bit to Low Level Set the ACK or NACK to Low Level Don t stop analyzing when NACK appears When the option is selected the data will be analyzed continuo
102. User Interface Sample the CAN 2 0B signal or open the sampled waveform fe ZEROPLUS LAP C 32128 Standard 3 11 CHO1 S H 000000 0000 CAH2_ 0B o File Bus Signal Trigger Run Stop Data Tools Window Help 18 x 0 eula ie 8 IB gt bd xi Ox Be ts Mile 91 Scale 9 T36541us Display Pos 194 ES A Pos 87 851299us v A T 87 851299us v A B 15 182424us v Total 167 69579ms Display Range 48 682703us B Pos 104 033T24us v B T 104 033724us v Compr Rate 255 883 36 dorus 146 04811us 134 730814us243 41351 7us292 0362212340 T78924us389 461628ust38 14433 Ud ee ILL JL f UU U L bila Fig4 129 CAN 2 0B Waveform 162 FMO7IAA PRET RAR i BPR 8l The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Group the signal channels into Bus We ZEROPLUS LAP C 32128 Standard Y3 11 CHO1 S E 000000 0000 CAH2 0B p i IL IL JD dj LIUULIL roa Fig4 130 Group into Bus Select the Bus Property to set up the Bus Property dialog box W ZEROPLUS LAP C 32128 Standard 3 11 CH01 S H 000000 0000 CAH2 0B Je E oxi yd oxi fy oxi Jy oxi yy oxi y ox Jy oxo Y XQ LULA U O U JUL TUUU 4 ut Ld IL JL JL Jj UUU BETIS ET MG Fig4 131 Bus Property 163 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Select the decoding function of the p
103. Value Max Value Bus Item Find Min Value Max Value Faling Edge D F Rising Edge i Falling Edae Statistics Statistics Waveform Find x Waveform Find x Activate the Function of Chain Data Find Activate the function of Chain Data Find Bus Signal Name grsstamatName psc Next Previous Close Previous Close Min Value Max Value Min Value Max Value When Found Statistics Statistics A Statistics Statistics o Fig 3 120 Waveform Find Dialog Box of the Logic Bus Waveform Find Ed wWaveform Find x Activate the function of Chain Data Find Activate the Function of Chain Data Find Bus Signal Name Bus Signal Name Next Previous Close Next Previous Close Min Value Max Value Min Value Max Value When Found Statistics ADDRESS E When Found Statistics I A Statistics Read m A X Statistics Write 0 0 A ACK Fig 3 121 Waveform Find Dialog Box of the Protocol Analyzer 12C FM0714A T 7 BE et FS he i BPR al The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Waveform Find x Waveform Find Activate the function of Chain Data Find Next Previous Close Next Previous Close Min Value Max Value Min Value Max Value o F r Faling Edge Rising Edge Start At napaea Edae g Either Edge x Low When Found Statistics
104. When measuring for a long period Compression makes memory more efficient Trigger condition depends on the testing board If triggering does not work well try to narrow the trigger conditions and optimize them repeatedly 8 Ifa testing board has a lower frequency than Logic Analyzer sample signals according to the external clock 9 When sampling from an external clock filter extra signals with the Signal Filter function 10 Unused channels may be removed from the Bus Signal display using Bus Signal Menu gt Channels Setup 22 FMO7IAA 23 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 3 User Interface 3 1 3 2 3 3 3 4 3 5 3 6 3 7 Menu amp Tool Bars Find Data Value otatistics Feature Customize Interface Auto Save Color Setting The Flow of Software Operation FMO7IAA 2P BETIS HE 0 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Objective Chapter 3 presents detailed information on the Logic Analyzer software interface in four sections Menu Bar Tool Bar Statistical Function and Interface Customization Basic Layout The layout of the Logic Analyzer software interface can be divided into nine sections as shown in the following figure W ZEROPLUS LAP 32128U A Standard 3 11 CNO1 S N 000000 0000 EE 31 lej x UU Z vijumu ur 1e 21 Height 10us v ix
105. a unique 64 bit code for the device to recognize Therefore the maximum number of link devices is 1 8 almost unlimited JV 1n 5 54 Host Micro C ontroller Fig4 93 Applications Applications 1 WIRE is commonly applied to the EEPROM and to certain sensor interfaces 2 Protocol Analyzer Signal Specifications Name of Protocol Analyzer 1 WIRE Required No of Channels Signal Frequency Not fixed around 10K Appropriate Sampling 1MHz Rate Nini Name of Syn Signals OW O Data Verification Point 20 US after the falling edge signals 3 Protocol Analyzer IO Description OWIO The only I O transmits Reset signals and data 4 Protocol Analyzer Electrical Specifications Parameter Min Typ Mex Unit Note Every IC varies High count Voltage 2 8 5 2 V according to the Pull High voltage LowcomtVotage 0 Vv 140 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Protocol Analyzer 1 WIRE Format Description Two speed types of 1 WIRE Standard 1MHz 1us High 5MHz 0 2us Four types of 1 WIRE Signals 1 Reset Every communications period starts with Reset signal Master will send a Reset Pulse so that all the Slave devices on the 1 WIRE Protocol Analyzer enter into recognition status When one or many Slaves receive Reset Pulse a Presence Pulse signal will be sent back from Slave indicating receipt of the signal
106. a i S1 ee f s Tapped 1 APes Tet Gets BPn14 p Te gt amp mme SBS HOD B 9 4 Peet Ae G Scww 4 5 260 s7 A Total 2048 Ospi Fos E Dingi Range 1023 102 Cargo Fate t s Lu au I zs e 1 m Ammmmmmimmmmmimmmummmmmmmmmmmmmmmmmm Fig 3 66 Show all Data Ctrl 2 Return to the last zoom Binary Decimal Decimal Signed Hexadecimal ASCII Gray Code Complement Fig3 67 Data Format Show numerical information in Binary Decimal Decimal signed Hexadecimal ASCII Gray Code or Complement FM0714A 53 P BE AIR Be ARAE Zeroplus Technology Co Ltd Waveform Mode w Square Waveform Sawtooth Waveform Pii Select an nalytic Range n Noise Filter E Bus Width Filter Data Contrast B Find Data Value EA Find Pulse Width l To the Previous Edge Tio the Next Edge n To P Add Bar Delete Bar Bar l zoom dmh Hand Normal TL K zoom In E Zoom Gut Show all Data x Previous zoom Data Farmat Waveform Mode List Data Mode Fig 3 68 k l Select an Analvtic Range un Noise Filter zz Bus Width Filter x Data Contrast B Find Data value EA Find Pulse Width l To the Previous Edge d To the Next Edge io To Add Bar ar Delete Bar Bar Fe Zoom em Hand R Mormal nr g zoom In E Zoom Out Ba Show all Data T Previous zoom Data Format waveform Mode Lis
107. acket Name TimeStamp Bus1 1 WIRE 8065053 Packet Name TimeStamp Busi 1 WIRE 12096936 Packet Name TimeStamp Data ji Busl 1 WIRE 20161527 Fig4 108 Protocol Analyzer 1 WIRE Packet List Packet 1 It is commonly normal Data which includes 1 Data Packet 2 It is commonly normal Data which includes 1 Data Packet 3 It is commonly normal Data which includes 1 Data Packet 4 It is commonly normal Data which includes 1 Data Packet 5 It is commonly normal Data which includes 1 Data Packet and Idling Length Packet s TimeStamp is Reset FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 6 HDQ Analysis Preface Increase the Protocol Analyzer feature to analyze the Protocol Analyzer HDQ transmission protocol data Using LA analysis function the required serial data can be converted and presented in the form of Protocol Analyzer Therefore the software needs to add a dialog box so as to set up a Protocol Analyzer HDQ dialog box HDQ Introduction 1 Brief Introduction Features Protocol Analyzer HDQ is a non synchronic half duplex serial transmission which requires only one HDQ and uses a quasi PWM Pulse Width Modulation to verify the serial data Applications HDQ is commonly applied to the display interface for battery management 2 Protocol Analyzer Signal Specifications Parameter Value Name of Protocol Anal
108. acket display Parity Display parity check in packet Describe Error description to any field format or data bit Packet Idle Time When the check box is selected the default value is 5ms Specifically when the Packet Idle Time is activated the packet will be divided again according to the Packet Idle Time If the Time Length between the previous packet and the next packet is more than 5ms the two packets will still be divided or the two packets will be merged into one packet It is a Bus Packet List view which includes 4 formats which UART happens below PARITY clews whether users start PARITY or not BUS Packet List 2 x Setting Refresh Export Synch Parameter Packet Name TimeStamp Busl UART 21927 Packet Name TimeStamp Busl UART 81164 Packet Name TimeStamp Busl UART 184247 Packet Name TimeStamp Busl UART 307617 Data Parity B6 Even Parity Data Parity DESCRIBE Data Par ity D9 Even Parity Data Par ity Fig4 79 UART Packet List Packet1 It is commonly normal Data which includes 1 Data and 1 Parity its parity is Even Parity Packet2 It is the state of Parity Error the DESCRIBE is Parity Error should Low Note Because the Even Parity and the Odd are impossible to present to the same Bus so we only take the Even Parity for an example here Packet3 It is commonly normal Data which includes 1 Data and 1 Parity
109. ail Menu amp Dialog Box Logic Snalyzer Help F1 E Hi FH User Manis file Keyboard Map 70 FMO7IAA 71 Phe AR AR 0 ARAS Zeroplus Technology Co Ltd Problem Feedback d About zEROPLLIS Logic Analyzer About ZEROPLLIS More Protocol Analyzer Tip The function of Software Version Information Display for ZEROPLUS LA means that the software will open a small window which displays the software version new functions and bug modifications when activating the software It is convenient for users to know the information of the present software version The Zeroplus Logic Analyzer User s Manual V3 11 Fig 3 104 The Table of Keyboard Map Machine sLAP CO321 28 Werner Standard V3 L10CNOLO df Fie gested on zOLIJOSI2S 044 UV Leger Ansira setup information 1f Samping mede Standard Ay aber tamping Frecuencia zODOODODD HF If FSM size XB Fig 3 105 Feedback Interface xl LAP A amp LAP C Series BESHSERR 0 8 PRG 8 Version Standard V3 11 CNO1 Zeropius Technology Co Ltd S N 000000 0000 The Information of the Version ZEROPLUS LAP C Series Standard V3 11 Welcome to use ZEROPLUS Logic Analyzer The document includes the version information ofthe software S b Detailed description invites reference company website Copyright C 1997 2011 ZEROPLUS TECHNOLOGY CO LTD Website http www zeroplus com tw Fig 3 106 Copyright About ZEROPLUS Logic Analyzer Op
110. alize the installation for hardware connection For further information refer to the Troubleshooting and Frequently Asked Questions FAQ chapters in the User Manual ip ZEROPLUS Loze Loi Fig 2 7 An Assembly of Laptop Logic Analyzer and Testing Board of LAP A Series 21 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 2 3 Tips and Advice 1 When testing a circuit board make sure that the internal sampling frequency within the Logic Analyzer is at least four times higher than the external board frequency 2 Ifthe signal connector does not work well with the pins on the test board try to use the supplied probes ZEROPLUS unm 3 Usages of probes 3 1 Take the loose end of the cable and Pte insert it into the clip Fig 2 9 ee ju TIT T i i E I C EUN B cT Fig 2 9 AAT wi 3 2 Compress the probe as shown to X EL E d reveal two metal prongs Fig 2 9 A ye 3 3 Place the metal prongs on a metal E F connector on the testing board and BE Pe release the fingers so that the prongs FP Enim can grip the metal connector Fig le us 2 10 a en amy i Tried rg et a amp xl Up TH sitet Has Fig 2 10 4 The Logic Analyzer will connect to the Zeroplus server for software updates if an internet connection is available 5 Unwanted signals can be filtered out using the Signal Filter or Filter Delay functions
111. alysis Tools to Annalee Data I1 Je gy BA te oll Baro Ber IC Bus Analysis UART Bus Analysis 4 SugE B SPI Bus Analysis H Sns Jo k Height 22 Fig 3 159 Software Flow Diagram Conclusion Information demonstrated in this chapter is only for entrance level There are more advanced approaches which may require fewer steps than those shown in this chapter This chapter is meant to equip users with sufficient grounding of the Logic Analyzer s software interface 94 FM0714A 95 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 Introduction to Logic Analysis 4 1 4 2 4 3 4 4 4 5 4 6 4 4 8 4 9 4 10 4 11 4 12 4 13 Logic Analysis Bus Logic Analysis Plug Analysis Bus Packet List Bus Analysis Compression Signal Filter and Filter Delay Noise Filter Data Contrast Refresh Protocol Analyzer Memory Analyzer Multi stacked Logic Analyzer Settings DSO stacked Settings FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Objective Chapter 4 gives detailed instructions on performing two basic analysis operations and other advanced analysis applications with the Logic Analyzer These two basic analysis operations are the Logic Analysis and the Bus Logic Analysis which are fundamental to all further applications The other advanced analysis applications are the I2C Inter Int
112. an be directly related and are controlled by the latter signals of the former and the latter can proceed simultaneously We call this State Mode In this mode the measured object provides the sampling clock State Mode is when the Logic Analyzer can obtain sampling data from the test equipment synchronously In other words when the test equipment has a signal or signal group this is the time to get the signal For example while the test equipment is sending out one rising edge the Logic Analyzer can start to obtain one signal What are A bar B bar and T bar The T bar A bar and B bar are labels T is the trigger label which cannot be removed when the waveform or the state is displayed which marks a pod When searching for or obtaining data the A and B labels can be set in any location Using the order of these markings you can return quickly to the desired position to analyze data This can also be a point to measure the interval between A B A T or B T What is a Trigger Gripper A gripper is the gathering point to collect the Logic Analyzer channels When a cable connector is not suitable for the test device a trigger gripper may be an alternative for connection What is a Channel The channel is the collection line of the input signal Each channel is responsible for linking the pin of the measured device Every channel is used to collect signals from the test equipment How can I display acquisition in the waveform captured by e
113. an be set to Standard 1 us or High 0 2 us Transmission Direction The Transmission Direction can be set to MSB gt LSB or LSB gt MSB MSB gt LSB From High Level to Low Level LSB gt MSB From Low Level to High Level Data Length The Data Length can be set in the range from 1 to 32 bit and the default is 8 bit Sampling Position The Sampling Position can be set in the range from 1 to 120us and the default is 30us Protocol Analyzer Color Users can vary the colors of the decoded packet 145 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 User Interface Instructions Set up the Protocol Analyzer 1 WIRE dialog box which is set as the steps of I2C PROTOCOL ANALYZER 1 WIRE E X Fin Assignment Protocol 4nalyzer Color Owl Reset Pulse Presence Pulse Protocol Analyzer Property Connect Speed Standardi us Transmission MSB LSB Direction Data Sampling Position a LL ka Min 1 bit Mas 32bit Min 1 Mas 120 Cancel Default Help Fig4 101 Protocol Analyzer 1 WIRE Configuration dialog box STEP 1 Select Channel 1 WIRE has only one OWIO Select the channel that it is to link the OWIO PROTOCOL ANALYZER 1 WIRE Configuration Packet Data Format Register Pin Assignment Protocol Analyzer Color Presence Pulse a Data Protocol Analyzer Property Connect Spe
114. an use icons on the tool bar box or menu For the menu go to Tools and click Customize See Fig 3 140 FE customize Se u Color Setting Common Setup Tocbars Shortcut Key Auto Save HUS Bus Property e ae Refresh Protocol analyzer Sampling Sate Display C Frequency Display Tine Display Fide ine woven gu Multi stacked Logic Analyzer Settings Analog waveform k Rider Mode Wawelom Setting C Regula Ruler W anvetoum Height 22 D SO sbacked Settings 8 Time Samping Site Rule Ford Size M Loeelated Setting h AoC Openi Compeestion wainna Show Gridins ME Show the T Bist in the midde area Show Toohp e Open Clore Double Waring pe When the roller amp moved toward back the Time loas in the vearnvedonm ansa vell move toward ight r Data Process What do you wart bo show when you press the Stop dunng the ung Keep the Present Data Read the Captured Data V Check for Update Bestore Delais Co cm or Fig 3 140 Customize the Display Mode by Using the Tool Bar E7 Sampling Site Display cij Time Display fay Sampling Site Display e Time Display Frequency Display Hide time of waveform Frequency Display al E Hide time of waveform Fig 3 141 Tool Bar Waveform Display Mode There are four display modes to determine the method of capturing data from sampling Sampling Site Display Time Display Frequency Display and Hide ti
115. ancel Default Fig4 166 Option Dialog Box Reaction Bar The default is the A Bar the added Bar can be displayed and selected in the pull down 182 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 menu if users have added a new Bar The data position of the Reaction Bar will be displayed in the List Window of the Memory Analyzer Note The Ds Dp Bar and T Bar can t be displayed in the pull down menu Display Width It is used to set the display width of the List Window of the Memory Analyzer the default is 16 Users can select the 4 8 16 and 32 from the pull down menu and they also can input a value between 1 and 100 Color Users can vary the color of Addr Data R Data W and Alteration as their requirements The default color of the Addr is black the default color of the Data R is blue the default color of the Data W is red and the default color of the Alteration is gray Import Export and The Export function can select the TXT or EXCEL format to store the Data of the List Window of the Memory Analyzer the Import function also can select the TXT or EXCEL formats to analyze the former export data Merge It can merge with the different export files See the Merge dialog box below Merge ee x 1 2 3 Object File E 10 txt Open File bo merge cu 111 bat Open Cancel Fig4 165 Merge Dialog Box Object File
116. and M4 are similar to the previous Users should select two or more Logic Analyzers but the most analyzers users can select is four Synchronous Channel Select the synchronous channel form the pull down menu The default synchronous channel is AO Synchronous Trigger Condition Select the synchronous trigger condition Users can select the Rising Edge Falling Edge High and Low from the pull down menu The default is the Rising Edge The function of the Synchronous Trigger Condition can only be used in the Channel Stack that is to say it is disabled in the Memory Stack STEP 3 Display the function of Multi stacked Logic Analyzer in the Memory Stack Tip There are two Logic Analyzers to do the Memory Stack the Synchronous Channel is A0 the data on the left of A Bar is captured by the first Logic Analyzer the data on the right of A Bar is captured by the second Logic Analyzer E ZEROPLUS LAP C 32128 Standard 3 11 CNO1 S N 000000 0000 LaDoc1 Bl x Elle Bus Signal Trigger Run Stop Data Tools Window Help 8 x Bc M ER S 66 EN bb jek js m f200MHz 5e z ie S Page fi Count fl JE ER 9 B c id fo serz2721 X Rz RE Be Te to BR le LU gt Height 28 7 Trigger Delay Scale 10ns Display Pos Ons APos 150ns v A T 150ns 7 A B 300ns 7 Total 81 92us Display Range 250ns 280ns B Pos 150ns v B T 150ns 7 Compr Rate Mo
117. ata in the following process There are two formats for selecting Report Form and Pure Data Form See the following picture r Bus Output Parameter Data Format Export Format Yes C No Hexadecimal pure Data Form Option r Output Range Pure Data Form To Final Packet E From First Packet 1 Fig 3 10 Export Format Pull down Menu In the part of the Export Format when the users select the Report Form the Option button can t be used when users select the Pure Data Form the Option button can be used The Option pops up the Option dialog box as follows where users can customize the export data items in the dialog box which are Packet Name TimeStamp Length and DESCRIBE FM0714A 30 2P RE EFS AS 1 BBR BS Zeroplus Technology Co Ltd je Capture Window Ctrl C The Zeroplus Logic Analyzer User s Manual V3 11 v Packets M Length v Mame v DESCRIBE wv Timestamp Fig 3 11 Option Dialog Box For instance all the export options are selected entirely See the below picture f Sampling mode Compression ji Internal sampling frequency SODOOCU Hz if RAM sime 2kR ji Trigger Properties Trigger position 5 2 095 dms Trigger level Pon A 1509 Post B 1 508 Port E 1 50V Trigger count 1 if Trager page ji Data Length 5 6034ms ji Total Length 403 Gus ji Channel mane ADAI AZ A3 AJAS AGAT AB AO ATOAN ALZ A13 A14 ADS BS EG
118. ay Time 200ns Min 200ns Max 3 355238s EEE Trigger Delay Clock m Min 1 Max 15775131 os 204 4us End Pos 205 2us an one trigger pages are selected the trigger bar disappears from Cancel Default Help Scale 464 TOSKHz Em Pos ns 2 Pos 10 m Da A T 99 206KHz v A B 3 333MHz Total 1 310T2ms Display Range Ons 53 827604us B Pos 10 38us v B T 96 339KHz v Compr Rate No Bus Si gnal ae us 038083us 32 278562us 21 513041u 10 F59521us M i 3521us 2a 513041us 32 278562us 43 038083us 53 79760dus BELLEN MUO en MTE ves cL 3 A l 4 2 I L B n Es 7 g 50 B0 g Bi Bi B2 B Fig 4 13 Trigger Position 0 FMO7IAA 2P BET AR ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 W ZEROPLUS LAP C 32128 Standard 3 11 CHO1 S H 00000000001 LaDoci AmE File Bus Signal Trigger Run Stop Data Tools Window Help 81 x Denai ms mb je m oomh fe 109 slit p Page 1 z Cot 5 z E ER A e l 21519040 6 Rz Re Be Te EPA le a 30 gt Trigger Delay 10ns Scale 464 TOSKHz Display Pos 17 9837Tus A Pos 120 98us v A T 8 266KHz i A B 3 333MHz v Total 1 310T2ms Display Range 35 813833us B P
119. ay zoom in the Waveform Display Mode by scrolling A This feature has been enhanced since V1 03 If your program version is prior to this version visit our website for the latest update at http www zeroplus com tw logic analyzer en technical support php SWO6 What are the extremes for Delay Time and Clock amp Trigger Delay Clock A The interface will inform you of the interval you may use However it varies from case to case depending on your test devices See Fig 6 2 Trigger Delay Time bns MincBng Max 83 880355ms Trigger Delay Clock R Min T Max 15 7 75131 Fig 6 2 Delay Time and Clock SWO9 How do know the version number of my software interface program A Click Help from the menu See Fig 6 3 and then select About ZEROPLUS Logic Analyzer See Figs 6 3 and 6 4 202 FMO7IAA O 2P BETIS AR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Logic Analyzer Help Fi keyboard Map Problem Feedback 8 About ZEROPLLS Logic Analyzer About ZEROPLLIS More Protocol 4nalyzer Fig 6 3 About ZEROPLUS Logic Analyzer About ZEEOPLUS Logic Analyzer LAP amp LAP C Series Version Standard v3 1107 M01 S 000000 0000 PRR TRIER 4S Zoroplus Technology Co Ltd The Information of Ehe version ZEROPLUS LAP C Series Standard V3 11 Welcome to use ZEROPLUS Logic Analyzer
120. bDacb z EIE IEEE ESTEE EESTI ERES ER ESJESTESTESEEESIEEESESESTES ESTESTE CETERI ESSE ERES EST Fig 3 87 Display Signals in Listing Window Help Waveform Display maj Listing Display Gal Ustna Diselay Pe ee te o Hot News Window Hot News Window Turn On Real time Monitoring V News Activity Sar Iw Production News Tip mm Memory Analvzer To let online users learn the 4 Bus Packet List latest news we add the Sar SEES Mna L dl Running Text Ads Function Cascade Horizontal Turn On Start the Running Text vertical Ads function Screen Display News Activity Let users learn v 1 LaDocS 1 the activities of our company 2 Labacs z Production News Let users learn Fig 3 88 Hot News Window and the Pull down Menu the latest products of our me Sa e ees r Oe OS SAN remm x afp j fg trej com fr E CE S M ps js See Ge wes mo reet re E irgge one see company Therein papin Rega 1t 1 era even erben A Curso Mata Pea Fatima ige fie 5 vas fie Ar a E are ay 2 o iU ea Perma LLL Ll LILIT Note m z If both News Activity and Production News are turned on z The Running Text Ads will play News Activity prior to Production za j News and play the news in order ea the whole process plays repetitively Fig 3 89 Display Hot News Window on the Software Interface he a yd a3 nen kha lratacal Analizer MWB Y1 07 00 Publish m Fig 3 90 R
121. cHi psoch ps0_cH3 DSO cH Channel Height Setting D50 H1 Height a D50 CHz Height ol D5O0 CH3 Height a DSO CH4 Height au DSO Settings OK Cancel STEP 4 Set the Channel Waveform Color and select the DSO Channel to be displayed on LA software DSO stacked Settings X Channel vIDiv Setting D5O CH1 V Div zv IDiv D5O CH2 V Div zv IDiv D5O CH3 V Div zv IDiv D5O0 CH4 Viiv zv IDiv Channel Setting only display D50 DEUS Iv OSO CH2 E DSO CH3 E DSO CH4 Channel Height Setting O50 CH1 Height al D50 CHz Height Bl O50 CH3 Height au D50 CH43 Height au 190 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 STEP 5 Select the Only display DSO according to users requirements D5 0 stacked Settings X Channel v Div Setting DS5O CHI WiDiv zii D5O CH VjDiv zvipiv D50 CH3WJDiv zvipiv D5O CH4 VDiv zvipie Channel Setting liz v DSC CH I oso cH psocHs Dpso cH Channel Height Setting DS _CH1 Height B Dp5o CHz Height B D5o0 CH3 Height 5p DSO CH4 Height S0 DSO Settings Ok Cancel STEP 6 Set the Channel Height DSO stacked Settings X Channel v Div Setting D5O CH1 Viiv B Div DSO_CH2 v Div zvipiv D5O CH3 VJDiv zv IDis 50 cH4 wii zvipiv Channel Setting only display O50 psa cHi
122. ce Pulse signals can be clearly seen 141 FMO7IAA BE 32S BPR 8l The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 M ee ee c ee i D a m a ih 1 amt nem EX am eui eni Hg 1 00 Y M Tous ChiX 4 52V Figure 2a You can clearly see the negative going reset and the presence pulse Fig4 95 Reset Presence Detect Sequence 2 Write Data 1 To initialize Write Data Master will convert the Data Line from the high logic to the low 2 There are two types of Write time slot Write 1 time slot and Write O time slot 3 During a write cycle all Write time slots must have duration of at least 60us and a recovery period of 1us 4 When the I O line goes down Slave devices create samples from 15 60 us A Write 0 If the sampling is low O is generated as in Fig4 98 Write zero Time Slot VeuLLue Veuwup MIN Vig MIN RES ISTOR MASTER Fig4 96 Write zero Time Slot B Write 1 If the sampling is high 1 is generated Note Read 1 is of a similar waveform pattern as in Fig4 99 Write one Time Slot Vuur V PULLUP MIN Vig MIN Vie MAX 0V meee RESISTOR ASTER Fig4 97 Wrote one Time Slot 142 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 3 Read Data 1 When Slave reads data Master will generate a Read time slot 2 To initialize Read Data Master
123. ch results Note It is available only when searching through a Bus Wavelorm Find xj W Activate the Function of Chain Data Find BusJ Signal Name Bust Next Previous Close Please key in a chain of data with a comma to compart them for example OX32 0 45 0 50 0 66 It needs to add the packet name in the Protocol Analyzer Far example ADDRESS 0XZA DATA Ux2D Start At End AE When Found Statistics ps pr Statistics Fig3 48 Waveform Find Dialog Box with Activate the Function of Chain Data Find Tip The function of Chain Data Find is mainly for finding the data in the packets of Bus and Protocol Analyzer which have some serial data For example it can start finding with the serial packet segments there are 0X01 0X02 and 0X03 in the Bus It improves the efficiency of Data Find See the following process FMO7IAA 46 3 PRET RAR BPR 8l The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Waveform Find Exi E Bust e ee Previous Cose Store O A S E E 03 T FERE Waveform Find Waveform Find Ps Fig 3 49 Process of Activating the Function of Chain Data Find Fig3 50 Function of Chain Data Find Displayed on the Waveform Window Pulse Width Find 40 z ves Previous __close_ LN e ps fl fs Fig3 51 Pulse Width Find Dialog Box GA Find Pul
124. clude ALL ALL BUS PROTOCOL HAS CHANNELS PROTOCOL NO CHANNELS Data Model Export data changed function the selected items inc lude ALL Data Sampling Changed Dot Compression Data Cha nged Dot Compression Some of the data value for the signal c hannels of sampling position are the same for example view the data changed and decrease export capacity this function will be good for users Output Range Choose the range of the data to export from the pull down menus Pop up an export file automatically The export file can be popped up automatically Users can decide whether to activate the function the default is selected See the export file below B ii siega o gt f DM ea yee ie Thanks lor using ZERDPLUS Logic Aral er Version V3 T1 FiFibenaewe wi File siro 903 KE PF created on MPI 105724 f Legic Amalzer setup information i Samping mode Standard T inher saenplang frequency OC Hz RAM sine ZR j None Use Data Compresion The number of Bus 0 ii The number of channel 37 Trigger Properties Tigger postion 17 i Trigger level 04 Port 0 8 Part 1 50 y IC Port 1 50V iD Post 130V Tigger court i Trigger page I Signal Filber sebup Filter Condition lengthens or shortens no T Delay tome Deabbe FT VAST stars for the segnal of high patem VL presens the segnal of low pattern amd UN means don t care H Semnal Tripet senap VIDT stands For dom cane 0H presents high pattern a
125. coded packet Step5 Click OK to exit the dialog box of Protocol Analyzer SPI Step6 Click Run to acquire the SPI signal from the tested SPI circuit Refer to the Fig 4 87 Tip Click icon to view all the data and then select the waveform analysis tools to analyze the waveforms We ZEROPLUS LAP C 322000 Standard V3 11 CN01 S N 000000 0000 LaDoc1 5 xl im Ele Bus Signal Trigger Run Stop Data Tools Window Help l8 xl De amp a Ples lpp p x vje i fa5KH2 see v ie ae Count ft z Eg gH Roo aa 26 573169 Rn Oe Eb Te Ble of Heim 30 TriggerDelay _40us _ Scale 50KHz Display Pos Ons APos 600us v A T 1 667KHz A B 833 333Hz v Total 81 92ms Display Range 500us 580us B Pos 600us v B T 21667KHz Compr Rate No W Bus SPI SCLK AO eSS Al DATA c A3 A3 EMM 5 55 w 6 55 euo g 80 amp Bi 8 B2 82 c B3 83 B4 84 g 55 55 g B6 B5 B 87 goo WUT UU AULT UU Ed id WL Cae LI LI LJ Pee speret Fig 4 85 SPI Signal FMO7IAA 2P BETIS RR 2 T3 ER 23 8j The Zeroplus Logic Analyzer User s Manual V3 11 Zeroplus Technology Co Ltd 4 5 4 2 Protocol Analyzer SPI Packet Analysis PROTOCOL ANALYZER SPI E X Configuration Packet Data Format Register Cancel Default Help Fig4 86 Protocol Analyzer SPI Packet dialog box DATA List Data field captured by Bus in the packet display BUS Pac
126. d Packet Idle Length Packet s TimeStamp is the start of Bus Data the default length is controlled by the setting dialog box If the input packet length isn t the end of data The software will prolong the length of Packet to end the data automatically as the figure below Height Bus co M Lf Fig4 46 Auto Prolong Packet The Fig4 46 is a Bus its first data is 0x00 and its length is 1023 If users input 20 as the Bus length But 20xaddress is not the end of this data so the software will prolong the length of the Packet to 1023 automatically 116 FMO7IAA BE PS BR 13 BPR Sl The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Bus Fig4 47 Packet End The Fig4 47 is a Bus If the Start of the packet is T bar and the set Bus length is 20 but the data 0x02 isn t the end at that time the Packet will be prolonged to the end dot automatically that is to say the Address 27 B bar is the End of the packet The above two data are made consecutively as the figure below 9s R ae Be ES Er is Ba e e m Eee A Pos 1023 T 1023 as BPoz27 B T 27 lc Fig4 48 Auto Prolong Packet The Packet List is displayed as the figure below x Setting Refresh Export Synch Parameter Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length ES o 1 2 3 4 5 6e
127. d Protocol Analyzer signal to the Logic Analyzer for example Protocol Analyzer SPI Buss Signal Trigger iu B Ls EE Dd m UNKNOW Loooooo0 UNKNOW dooooo00 0000000 UNKNOW Sf mem ANT RUD DORT DE Bites Fig4 157 Waveform before Refreshing Filter 3 10 I STEP 3 Choose Select an Analytic Range to select the analysis range and drag Ds Bar to B Bar B EH I I I I I I I I I Puss Signal Trigger Filter OME MOT 10000000 10000000 ONE NO LOLI eee ee LLL Fig4 158 Drag Ds Bar to B Bar ca STEP 4 Chic lite the Logic Analyzer will analyze the data between Ds and Dp 179 FMO7IAA Phe PR T3 ER 2x 8l The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 E 1 1 1 Uo d n i a UF ENO Looo0000 UNE WOM ce A ECCE i TTG LIL IL IU db Fig4 159 Analyze the Data Between Ds and Dp 5 STEP 5 Click Sl again the waveform return the original state B z Filter 1n I Buz Signal Trizger v Bus1 UAE A UME MOT TOO0D00DOO OME MOr AAN N OO A LE ST an LIL IL IL JL JL Fig4 160 Restore the Original State e AU eai cag Tip The Refresh Protocol Analyzer function can come into effect while the Ds and Dp are activated 180 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 11 Memory Analyzer Memory Analyzer enables the system to di
128. dge Tip In the above example when dragging the C Bar the A Bar will stop at the Raising Edge of A1 87 FMO7IAA 2P BETIS AR ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 LJ SEED Fig 3 149 Gridlines Show Gridline The gridlines will be displayed on the waveform area I L1 1 14 Lj SEEN A O 42 Time SOMHz Fig 3 150 Tooltips Show Tooltip Leave the mouse over a waveform and the description will be shown Show the T Bar in the middle area Show the T Bar in the middle of the Waveform Display Area after triggering When the roller is moved toward back the Time Axis in the waveform area will move toward right When the option is selected and users move the roller in the middle of Mouse directly toward back the scrollbar will move toward right correspondly Check for Update The Logic Analyzer software will automatically check for updates when being started Restore Defaults The Waveform Display Mode Ruler Mode Waveform Setting Correlated Setting and Data Process will return to the default setting 88 FMO7IAA 2P BETIS RR 2 BPR uj The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 3 5 Auto Save To save the captured data for a long time users can use icons on the tool bar box or menu For the dialog box go to File menu to click Auto Save or go to Tools menu to select Customize and select Auto Save See Fig
129. different figures 181 FMO7IAA 2P BET AR ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 lt lt lt gt gt option Import Export Merge Refresh Reset Display Alteration Ba Bus1 I2C Address Write data Read data ros Wr Peada 1 L T 9 TL 3 L 1 9 T L L 3 Unused 0X00 0X4F oxso oxoo Ox o oxe9 OXAB OXCD EPENEE NES es IEEE ee es ee v Compact Mode Unused 0X60 0X7F Complete Mode wf Fig 4 163 Compact Mode lt gt gt gt Option Import Export Merge Refresh Reset Display Alteration Ba Bus1 I2C Write data Read data A mee Unused 0xX00 0X4F 0x50 OX00 oxsi Og 0x52 0k89 oxs3 Compact Mode oxss OMEF Oxs6 Ox57 0x58 T Complete Mode Unused 0X60 0X7F Fig 4 164 Complete Mode 2 Buttons lt lt It is used to find the first packet EJ It is used to find the previous packet gt It is used to find the next packet gt It is used to find the last packet Option Opto It is used to set the relative parameters for the List Window of the Memory Analyzer see the following Option dialog box Option x Bar Assignment Reaction Bar la Active Display Assignment Display width Data W Alteration os 9 a a C
130. ditional StartPos EndPos SelectedData 4 0 0 A1 52 53 52 0 0 0 Ds Dp A2 0 0 1 0 0 Ds Dp A3 0 1 0 0 Ds Dp A4 0 1 Ds Dp AS 0 1 0 0 0 Ds Dp A6 0 1 0 0 Ds Dp A7 1 0 Ds Dp B 0 0 1 0 Ds Dp B1 0 1 0 Ds Dp Fig 3 138 The numbers of data qualified by warning conditions are printed in black otherwise in red 82 FMO7IAA 83 Fe FR AR D T3 ER 2S S Zeroplus Technology Co Ltd The Zeroplus Logic Analyzer User s Manual V3 11 3 4 Customize Interface 37178 Standard V3 1 100601 oe000000 0000 Labacz m Ele Dus sonsi Tagger Runfatep Qaa Took Window Section 3 4 presents detailed instructions pertaining to how to modify the Waveform Display Mode how to modify the Ruler Mode how to modify the Waveform Height and how to modify the Correlated Setting tee Oe So RAK D gt 10 x nl xi dex te 200mHz je se 4 Page 1 Coun fi i jgw ms mise Joo Oe BE Dr PA te 2108 s Heo f2 TaggerDetay Sns Scale 200MHz Display Pos Ons APos T5ns A T 13 339MHz 7 A Bz6857MHr 7 Total 10 24u5 Display Range 12606 1356 BPosTSes B T 13 333MHr Compr Rate No n P Fig 3 139 The Interface Layout Shown in Default Settings FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 3 4 1 Modify Waveform Display Mode To modify the display mode users c
131. dth to be filtered in the right edit box Input the time value of the width when the display is in the Time Display or the Frequency Display and the unit is based on time such as s ms us etc if the inputted value is out of the range it will switch to the best time value in range Input the clock value of the width when the display is in the Sampling Site Display and the range of the input is from 1 to 65535 For example after activating this function and then input the value 5ns The Bus Data which is less than or equal to 5ns will be filtered as the figure below FMO7IAA 44 Phe AR AR 2 f3 ER 23 8 Zeroplus Technology Co Ltd w Data Contrast B Find Data value Ctrl F The Zeroplus Logic Analyzer User s Manual V3 11 Fig3 45 Before and After Filtering Data Contrast Settings X Contrast Files Basic File LaDoci Contrast File LaDoci sl Contrast Beginning Point T Bar Error Tolerance None m t Beginning of Data Contrast Result Error Stat Roll the contrast waveforms synchronization Pin Assignment Perform Contrast E Close Help Display Files the contrast differences Display Files horizontal Fig3 46 Data Contrast Data Contrast It is used to contrast the difference for the two files of the same style One is the Basic File and the other is the Contrast File The contrast file can display the difference between the Basic
132. e When more than one trigger pages are selected the trigger bar disappears from the view Cancel Default Help Fig 3 35 Set Trigger Delay FMO7IAA Phe AIR Be 2 ARAE Zeroplus Technology Co Ltd Tip Trigger Range Icon Description N A Trigger Range 4 Run Stop 41 The Zeroplus Logic Analyzer User s Manual V3 11 See Section 4 1 for detailed instructions Trigger Delay Fig 3 36 Set up Trigger Delay clock under time display Trigger Delay Fig 3 37 Set up Trigger Delay clock under sampling site display The Trigger Delay setting in Tool Box equals to that in the above dialog box x Trigger Content Trigger Delay Trigger Range O Range Setting Time Sample Y fi minute Y Cancel Default Help Fig 3 38 Set Trigger Range b Single Run F5 bh Repetitive Run Fe Bg Stop F7 Fig 3 39 Run Stop Menu bbb Fig 3 40 Run Stop Tool Box FMO7IAA Zeroplus Technology Co Ltd User s Manual V3 11 O 2P BET AR ARAS The Zeroplus Logic Analyzer Menu Bar Run Sto 5 Data 42 Menu Item Detail Menu amp Dialog Box Click to run once peste un ut See Section 4 1 for detailed instructions i Click to run continuously until the Stop button is b Repetitive Run F pressed See Section 4 1 for detailed instructions Click to stop the repetitive run St Fr 9 5top See Section 4 1 for detailed instructions Pid Select an nalwtic Range
133. e OOS hypin Pra TORTE Poulin tui BmRHETMeE Tesi 10 34 Dipiy Benge dira i Tora Pitre me Te thine Comgpr Haie Aia p m au L vas EE Fig3 94 Select Channel button After clicking the Right Key of the mouse the Select Channel dialog box will pop up as below FMO7IAA 68 Phe AR AR 0 f3 ER 23 8 Zeroplus Technology Co Ltd mm Memory Analyzer Tip Setting Set up the packet list Refresh Click it the content in the packet list will be refreshed Export Users can use the fragment to work record and analyze the packet list data As Export according to the packet list arrangement it exports the text file and csv file Synch Parameter Open the Synch Parameter Setting dialog box The Zeroplus Logic Analyzer User s Manual V3 11 Select Channel x Cancel i Fig3 95 Select Channel dialog box In the Select Channel dialog box users can select the channel which users want to display users can select four channels at most the defaulted channels are AO A1 A2 and A3 there are four channels in total es n Jd OS PS CE al A Banjac Addere Vente is a Dg l a i L 8 I 9 a4 LB c 5 Une xa dii Oe e dace d e e xkk I I 1 T 1 Lira oai TE C 2 0 TF f Fig 3 96 Memory Analyzer Interface See Section 4 11 for detailed instructions d Bus Packet List CEEL Left mm SIN eM ME 4 Tea Biel FEF is Py EA Dey Ex
134. e RAE TT 104 04 ODECA N v Use the DsDp More Protocol Analyzer m oe Fig 3 78 Bus Property Bus Activate the function of analyzing the Bus Color Configuration Open the Color Configuration dialog box to set the conditions for the Bus Activate the Latch Function Activate the latch function Protocol Analyzer Activate the function of analyzing the Protocol Analyzer Use the DsDp Use the Ds and Dp to help analyze the Protocol Analyzer Find Find the desired Protocol Analyzer module Users can input the Protocol Analyzer name to quickly find the Protocol Analyzer module from many Protocol Analyzers After inputting the first character of the name in the Find box of Bus Property dialog box the corresponding module will be displayed in the Protocol Analyzer list box according to the input character See the figure below FMO7IAA 2P BETIS HR 0 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Bus Property E x Golor Gonfig AQ v Rising Edge Parameters config ZEROPLUS LA 1 WIRE MODULE V1 10 00 CNO1 C ZEROPLUS LA 3 WIRE MODULE 1 04 00 CNO1 ZEROPLUS LA AC97 MODULE v1 02 00 CNO1 C ZEROPLUS LA ARITHMETICAL LOGIC MODULE V1 51 00 CM01 ZEROPLUS LA BUS MODULE v1 00 00 CNO1 C ZEROPLUS LA CAN 2 05 MODULE V1 32 00 CN01 ZEROPLUS LA CCIR656 MODULE V1 31 00 CNO01 c ZEROPLUS LA Compact Flash 4 1 MODULE V1 01 00 CNO1 ZEROPLUS L
135. e Width Previous It can find the previous Pulse Width For example Find in the A1 channel the Pulse Width is equal to 20us take the A Bar as the mark See the below figure Se se i H e ETT Oe ll roe oW bk lpn dm iind sm Hair ZEIT i coum l so ILA 24 7 gt te mE kere iB rinse T E Li lt MIELE bimg ph ej Ta Pom Dome HEAT an Tibe Pri HOUR XT tei a Walbrmew tamer zi uinea tiia Rieger TNT B Teibii ed Ll a M T ETE a uem de DIL I E EHI EE ee eee UCEDURe Oe SUM Umen TIEN a pee xk m i 5 Mur ll SSS a pe ae E E cm mIE IRE uM cot Baa nass deter a z Manes 1 Tsi ai di banar i ae sh d EE FH em Fia ee Fi T 2j jur EET 2 Hd fuk r Fig 3 52 Pulse Width Find on the Waveform Window Go to the previous edge sweep of the indicated signal Go to the next edge sweep of the indicated signal 47 FMO7IAA P BET H3 Be 2 ARAE Zeroplus Technology Co Ltd 30 Ta k Tip Tx Go ToT Bar T xD A Go To A Bar B Go To B Bar B o i30 To More 1 Press T go to T Bar 2 Press A go to A Bar 3 Press B go to B Bar Add Bar AlE4 Bar Add user defined bars 1 Click the above menu item from Data menu or click Add Bar icon from Tool Bar 2 Give a Bar Name define a Bar Color and set a Bar Position 3 Define the Bar Key with the number b
136. e Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 o ore TAIRE i i TR Em 140 2S ME LOT c wedsetecuecseas 150 ASL CU EEUUSOIUIT 157 4 6 onere M 167 4 6 1 Software Basic Setup of COMPIeSSION ccccccceeccceececeeeeeeseeeeceeeeesaeeeeseeeeseeeeseeeessnees 167 4 7 Signal Filter and Filter Delay cccccccsescecceeseeeceesececceseeeceaeeecsageeecsaeeeeseseeessageesssaenes 169 4 7 1 Basic Setup of Signal Filter and Filter Delay seeeeseeeseeeeeeeeeeene 169 4 8 perge E 174 4 8 1 Basic Software Setup of Noise Filter ccccccceecceceeeeeseeeeseeecesseeeeseeeesaeeeseeeesseees 174 4 9 Data COSS er cess asta ss dete test dares Pee M ELEME UNIS buda NP MSS 176 4 9 1 Basic Software Setup of Data Contrast seesseesssessssssseseeee nennen 176 4 10 Refresh Protocol Analyzer cccccccscccccsssceecsesececeeuseecceseeeceueeecseseecssaeeessageeessegeesseaeenenss 179 4 10 1 Basic Software Setup of Refresh Protocol AnalyZer cccccccseeeeeeeseeeeeeeeeeeeeeeeeeeas 179 4 11 Memory MANY Z CM ERROR OCHO 181 4 11 1 Basic Software Setup of Memory AnalyZet cccccccccseeeeceeeeeeeeeeeeeesaeeeeeeeeeeeeeaeeeeeeas 181 4 12 Multi stacked Logic Analyzer Settings seeeesssessssseeeesee
137. e safety and accuracy when performing any operation with the Zeroplus Logic Analyzer 1 1 Package Contents Verify the package contents before discarding packing materials The following components should be included in your product For assistance please contact our nearest distributor Table 1 1 Accessories List LAP LAP LAP LAP LAP LAP 16032U 16064U 16128U 32128U A 321000U A 322000U A Logic Analyzer 1 1 1 1 16 Pin Testing 8 Pin Testing Testing Cable White 2 Pin Testing Cable Black LAP C LAP C LAP C LAP C LAP C LAP C LAP C 16032 UV 6064 16128 162000 E 28 mE 000 UV Logic Analyzer 16 Pin Testing Cable 8 Pin Testing Probe o xs USB eae 6 FMO7IAA Phe AIR Be 2 ARAE Zeroplus Technology Co Ltd 1 Pin Testing Cable White 2 Pin Testing Cable Black The Zeroplus Logic Analyzer User s Manual V3 11 This Driver CD consists of a multilingual software interface program as well as a multilingual User Manual The following is the accessory package of LAP C Series the LAP A Series is the same with LAP C Series S FEROPLUS P TEROPLLS L J M xxi Fig 1 3 Probe varied depending on models m LL i Usar nul Manua Fig 1 7 1 Pin External Clock Cable White M Uri i a i i iv Z 16 Pin x 1 8 Pin x 2 Fig 1 2 Testing Cable Fig 1 4 USB Cable Fig 1 8 2 Pin Ground Cable Black FMO7IAA
138. eDee 79 ices Orme Erigim Pri Bes aPeu Tint Tatil eT i Taam idhini CD Dess D niarasga Hilos Hiden Dua Tire T BoTR ITEM Cerrar Pata Bee baal Ta Fae m m n n m Mya a a m ee ee NE CM gt zm Spt ada gta UUU UU UU UUU UULU ale cal a ea oo ae wa Am ILI i EE M H Jp h a Lab z PIT ambe 3 EM yl 4 a dd L _ it FK 1 B i PAS LM 1 zi Fn 1 ve 1 gt h arm ro arm FE arc musuzogN ee Tee Pee OM m Bua T1 De Dupi Pos Dear AF ies E Md Eu a Daimi E prope ee Pa B Pec hives t hag ae Fis a EP kra qui mJ n Te e ee M ara 11 n PLUUUE ULI AU UE SU AAU w i F ar gigs Ss Fig3 116 Place Ds Bar FMO7IAA 19 P BE TS HS 0 BRS Bl Zeroplus Technology Co Ltd T Add Bar Tip When the mouse is located at a special position on the waveform area click the right key to select the Add Bar function a bar will be added automatically in the special position according to the sequence of the word and color See the C Bar in the position 5 in the right column The Zeroplus Logic Analyzer User s Manual V3 11 Sm mx o a ponm ed jare com I j aI zhbELbLM ENM o He xu EL eG me TS CERT Duar Panga A30 Ma 10 ene of Tenes Ce a ns ail z mw 8 all te Se UT sans MR a Ces m um ox EE ML Juil un i ET m DE L EE 5 NE L E
139. ect it FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 as their requirements and the default is non activated Display files the contrast differences It can line out the difference in the contrast waveform Users can select it as their requirements and the default is non activated Do Contrast automatically when being run The two files will be contrasted automatically when being run Tip For this function Data Contrast we provide the SDK Development Tool for users Users can customize the Data Contrast Interface according to their requirements We has packed the Data Contrast Ul as the GUI DLL and designed an interface which is used for the communication between the GUI DLL and Main Program The GUI adopts the Non modal Interface design which can make the GUI Interface and Main Program Interface switch freely When users activate the Data Contrast function the software will search whether there is a GUI DLL or not then it can judge whether there is a user defined Interface If there is a user defined Interface the GUI DLL will take effect if there isn t the embedded Data Contrast Interface will be activated STEP 2 Display the contrast results in the Data Contrast dialog box Tip After pressing Perform Contrast it will display the contrast information in the contrast result The below contents of the box are the contrast information The information is relative simpleness
140. ed Standart us 7T Transmission MSB gt LSB Direction Data Length E bit Min 7 bit Mas 32 bit Sampling Position n us Min 1 Max 120 usu gel Iss Aus Cancel Default Help Fig4 102 Protocol Analyzer 1 WIRE Channel Setup 146 FM0714A O 2P BETIS AR ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 STEP 2 Set the Connect Speed 1 WIRE has two modes Standard 1 us and High 0 2 us The speed setup according to the specifications of the object to be tested and the default mode is standard PROTOCOL ANALYZER 1 WIRE Configuration Packet Data Format Register Pin Assignment Protocol Analyzer Color OO Reset Pulse Presence Pulse Protocol Analyzer Property onnect Speed Standard 1 us ka Transmission MSB LSB Direction Data Length E bit Min 1 bit ha 32bit Data bin 1M as 1 20 Cancel Default Help Fig4 103 Protocol Analyzer 1 WIRE Connect Speed Setup STEP 3 Set the Transmission Direction Set the Transmission Direction as either MSB gt LSB or LSB gt MSB PROTOCOL ANALYZER 1 WIRE Configuration Packet Data Format Register Pin Assignment Protocol Analyzer Color Ol Reset Pulse Presence Pulse Data fansmission wsp LSE Direction Data Length E bit bin 1 Bit M ae 32bit Min
141. ee gcowzcle chon cl uu ce THE ipa amela F gt i x al E JA rui We io Sigaek Pelei SU ara ringing edga Happ ar Gieck Frame 4 whitia wave 2 yecle ri Mi duha aue ee ml s argie ui 17455 Kb ce Peder S wrens Halny Sa gies aia PON Gieck Frage 1 where wore Cycle end Fig 4 82 Clock Polarity and Clock Phases FMO7IAA 2P BETIS AR ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 4 1 Software Basic Setup of Protocol Analyzer SPI Step1 Set up RAM Size Frequency Trigger Level and Trigger Position as described in Section 4 1 Step2 Set up the Falling Edge on the signal of SS which connected to the Signal Selector SS pin of the SPI tested board Step3 Set up the Protocol Analyzer SPI dialog box the Protocol Analyzer SPI dialog box is set as the steps of I2C PROTOCOL ANALYZER SPI xX Configuration Facket Data Format Register Pin Assignment SECLE 55 Pin Assignment 55 Channel DATA 55 Channel Protocol Analyzer Property 55 Setting Mode CPHA 0 CPOL 0 Transmission MSB sLSE Direction Data Length fe bit Fill at the LSB when the bit count is nat enough Protocol Analyzer Color Cancel Default Help Fig 4 83 Protocol Analyzer SPI Configuration dialog box C Vitual SS Idling Time 20ns Mining Masi sd 1 mel I Dant care data bit Step4 Set the SPI Configu
142. eeen eene 185 4 12 1 Basic Software Setup of Multi stacked Logic Analyzer Settings 185 MNS dA OOPS AGRE SUNOS MENT TT 187 leues tt cdc tbe steele wa can arn dv Sc ad cnc atc clea aac las 195 5 1 Installation Troubleshooting ccccsesccceeseeceesceceeeeeceuececeueeeseseeesaseesaseeesceeseaeeenegeseneeeeens 196 5 2 vele ursi TrouDIeSHOONO Emm T 197 5 3 Hardware ITrOUDIeshOOlg sisccssisavcisssrcuniad aree dier miro derit bu ada ace a rtu bk Re ed bw edm bd 198 FAQ A co 9 E 199 6 1 geil T T 200 6 2 lec ERR 202 6 3 PRO GISU AUOM MET TE H 206 6 4 Technical ATOR MAO mm c 207 s 02 Cc eee 208 APPONI aa ot eet nee nie eee ee ee ee ee ee ee eee ee eee 209 7 1 FOE ING E AA E 210 7 2 Contaci Br X HH 213 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Preface This Quick Start Guide is designed to help new and intermediate users navigate and perform common tasks with the Zeroplus Logic Analyzer Despite its simple packaging and interface the Logic Analyzer is a sophisticated measurement and analysis tool It is also a highly sensitive electrical current sensin
143. egrated Circuit Analysis and the UART Universal Asynchronous Receiver Transmitter Analysis the SPI Synchronous Peripheral Interface Analysis Compression Signal Filter Setup and Filter Delay Setup etc 4 1 Logic Analysis Logic Analysis is meant for a single signal analysis Section 4 1 gives detailed instructions on the software s basic setup Basic Software Setup of the Logic Analysis Task 1 Clock Source Frequency and RAM Size Setup Fig 4 1 will appear Ji Sampling Setup X Ww Channels Setup mm UT M0 Signal Filter Setup Internal Clock E Frequency CHE Group into Bus Ctrl 6 Synchronous Check Ungroup From Bus Ert Estena Clock Expand E Min D DOL Hz Mace 100MHz Collapse Habe The external clock wolkage level iz the same as the port A bigger level Formak Row b Sargin RAM Sine Compressann Mote Sagal Filter enarne RAM Sine x Data Compression s Signal Piter Setup Channel putsber wil be katod to 32 Fig 4 1 Clock Source Step 2 Clock Source Frequency Setup Internal Clock Asynchronous Clock Click on Internal Clock and then select the Frequency from the pull down menu to set up the frequency of the device under test DUT The frequency of the Internal Clock must be at least four times higher than the frequency of the Oscillator on the DUT Or select the frequency zoownz o from the pull down menu on Tool Bar as Fig 4 2 shows Tip Connect the output pin of the
144. en Export Waveform dialog box FMO7IAA 211 Phe AIR AR 2 ARAE Zeroplus Technology Co Ltd Hot Key Page Down Page Up Home End Up Down Left Right ESC Space The Zeroplus Logic Analyzer User s Manual V3 11 Table 7 3 Hot Keys 3 Equivalent Orders Operate the position shown Operate the position shown Operate the position shown Operate the position shown Operate the position shown Operate the position shown Operate the position shown Operate the position shown Operate the position shown Change the trigger conditions Statement Go to next page of the data or the waveform Go to previous page of the data or the waveform Go to the beginning of the data or the waveform Go to the end of the data or the waveform Move the cursor up a grid Move the cursor down a grid Move the selected Bar or display left to prior the waveform or data Move the selected Bar or display right to posterior the waveform or data Release all selected bars and change Mouse mode to Normal Change trigger conditions FMO7IAA 212 P BET H3 AR 2 ARAE Zeroplus Technology Co Ltd Hot Key F1 F2 F3 F5 F6 F7 F8 F9 F11 F12 The Zeroplus Logic Analyzer User s Manual V3 11 Table 7 4 Hot Keys 4 Equivalent Orders Help gt Logic Analyzer Help Decrease the sampling rate Increase the sampling rate Run Stop gt Single Run Run Stop gt Repetitive Run Ru
145. en the website of Zeroplus Technology to know more modules PTE M cee Ahy ae ZEROPLUS LAP C Series Standard V3 11 E LLL Lnd Wiker bW uk ZEROFLLSE Log u Aene Tbe ocurren eclidei the cekgpmon a mien ol the eee j be iea a p a Timm Fig3 107 Software Version Information Display Window FMO7IAA Zeroplus Technology Co Ltd O FP BBA 5 AS OS ER ZA 8j Right Key 72 Menu Item Right Key Menu on the Bus Signal Column Tip The Right Key menu is added on the basis of the Bus Signal menu So the function of Sampling Setup Channels Setup Bus Property Group into Bus Ungroup from Bus Format Row and Rename are the same as those in the Bus Signal menu And the function of the Analog Waveform is the same as that in the Tools menu Reverse Tip This function of Reverse is used to reverse the collected signal Change the High Level into the Low Level change the Low Level into the High Level The Reverse of Waveform Mode displays with the dashed so it is easy to distinguish The Zeroplus Logic Analyzer User s Manual V3 11 Detail Menu amp Dialog Box im Sampling Setup iw Channels Setup BUS Bus Property Analog Waveform k Reverse Chrl 6 Gtr Group into Bus Ungroup From Bus Add Channel Copy Channel Delete Channel Delete All Channels Restore Default Channels Format Pow d Rename Fig 3 108 Right Key Menu on the Bus Signal Column
146. eroplus com tw ZEROPLUS TECHNOLOGY DONG GUAN CO LTD Room 2821 B2 Section Building 1 Hong Rong Square District 80 Bao an Shenzhen City Guangdong Province China Mainland Tel 86 755 2955 6305 6 Fax 86 755 2955 6306 808 ZIP Code 518102 ZEROPLUS TECHNOLOGY DONG GUAN CO LTD 101 No 172 Alley 377 Chen Hui Road Zhang Jiang Pudong New Area Shanghai City Tel 86 21 50278005 6 Fax 86 21 50278006 ZIP Code 201203 Users can download the newest Software and User Manual ZEROPLUS is the brand of ZEROPLUS TECHNOLOGY CO LTD The other brands and products are the brand or registered trade mark of the individual company or organization Conclusion The demonstrations in this User Manual will enhance users understanding of our products in future issues even though the manual ends here We thank you for choosing the Logic Analyzer Please contact us if you find anything that could be done better either in software or hardware We appreciate your feedback 213 FMO7IAA
147. et as AQ Timing Settings us Set the time for Break Address Read Write Data and Recovery Protocol Analyzer Color Users can vary the colors of the decoded packet 152 FM0714A 2 BETIS BR 0 ARAN The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Operating Instructions Open the LA operation interface P ZEROPLUS LAP C 322000 Standard V3 11 CN01 5 N 000000 0000 LaDoc4 cc aj fad J Li li Fig4 113 Operation Interface Sample the HDQ signal or open the sampled waveform We ZEROPLUS LAP 32128U A Standard 3 11 CHO1 S H 000000 0000 HDQ_SET ae E 2 01234ms XM exeMms Ss 3 348s MB 13 442ms DMD 15 528m5 167 695ns et 605m 167 695ns 167 695ns o ef 695s ot 898ns 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms g 80 60 B2 E B3 B3 Bt B4 BS BS mgao oot A L4 A o C m B li aj iat fi l j ooo fadt MM 7 Fig4 114 HDQ Waveform 153 FMO7IAA 2 BETIS BR 0 ARAN The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Arrange the signal channels into Bus We ZEROPLUS LAP 32128U A Standard 3 11 CHO1 S H 000000 0000 HDQ SET ry P 1 13 348ms 13 442ms 13 528ms d Cha 167 695ms jore 167 695ms 167 695ms 167 695ms 167 695ms 167 695ms 16
148. etween 0 and 9 Tip The number shortcut is set in the Add Bar dialog box Every new bar can be filled in one number which is used to find the required bar faster the default number of the new bar is O It is noticed that once the number key is set it can t be modified and each new bar can named with the same number that is to say one number can name many bars For example users can set the number 3 as the shortcut key When users press the number 3 key the C Bar will be displayed in the centre position of the screen 48 The Zeroplus Logic Analyzer User s Manual V3 11 center of the waveform area ad Select an 4nalytic Range un Noise Filter EE Bus Width Filter Data Contrast B Find Data Value Ctrl F EA Find Pulse width l To the Previous Edge Fil f To the Next Edge Fi2 Ie GoToTBa T Fi Add Bar Alt 4 Ae GoTo A Bar aF Bar i Delete Bar Alt B E Go Ta B Bar B i Foom B Go To Mare em Hand H k Normal ESCAPE NU zoom In F3 if Zoom Qut F8 sss Show all Data Fig we Previous Zoom Chrl F Data Format waveform Mode k List Data Mode Fig 3 54 The selected bar will be shifted to the center of the waveform area x Setting O Bar Mame 8 cu Bar Color NENNEN Bar Pos Bar key T Fig3 55 Add Bar en omet adal nj ae 7 Ie I N 22i Dea ed i ee ee en 9m Come fi D BEE amp 7 52 B omn rx ZzhbLkbLA s p rage frs s
149. evice has SCL at logic high will gain access priority Furthermore since I2C is a synchronous communication protocol and data transmission must be in bytes a complete I2C signal packet must consist of Start Address Read Write Data ACK NACK and Stop segments They are as following Start This is the initiation of SCL and SDA 1 bit only Address This identifies the device address 7 bits Read Write This is a data direction bit O Write 1 Read ACK NACK This is a confirmation bit following every data transmission segment Data The actual signal data transmitted by byte Stop This appears when SCL High and SDA Low bit only 124 FMO7IAA 125 Phe AR AR 2 BPR Zeroplus Technology Co Ltd 4 5 2 1 Step1 Set up RAM Size Frequency Trigger Level Step2 Set up the Falling Edge as the trigger condition on the signal which connects to the tested I2C data pin SDA Step3 Group the analytic channels into Bus1 Bus Signal wag an s IL Sampling Setup The Zeroplus Logic Analyzer User s Manual V3 11 Software Basic Setup of Protocol Analyzer I2C and Trigger Position as described in Section 4 1 El wA Mw Channels Setup 3 BUS Bus Property az Snalog Waveform Bus Signal Trigger S a4 Reverse y Group into Bus 40 a0 g 55 Ungroup From Bus Ctrl I Al al F AS r amp dd channel C A3 A3 BD Copy Channel az a g Bl Delete Channel I
150. f 2pPBETEHSBS iS BPR al The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 High Quality Professional Instruments ZEROPLUS FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Features of Zeroplus LOGIC AnalyZGr uos catch id rene Sani pi ape eo RR a ao han tud dax ria ndis Ue ER RR DEO d ne 5 1 1 FC ACSC OMS I NRI REOR 6 1 2 PETES GTN OU sic abcde 8 1 3 Hardware Specifications ccccccssccccesceccececceececeeeecseeeseeeseaeeeseaeeeseacessaueessaeeessaeeesaeeesages 11 1 4 System Rice UE RIS PINE TET 14 1 4 1 Operating System Requirements cccccccsssceccesseeeceenseecceseeseageeessagseeeseseeessageeessagess 14 1 4 2 Hardware System Requirements ccccceccceceeeceeeeeeeeeeeeeeeeeseeeeeseeeeesseeeeeseeeeeesseeeesnaaes 14 1 5 Device Maintenance and Safety ssssssssssssssssssssssssesee enne nnn nennen nns 15 IS CAN AN OOM ETE t RET 17 2 1 SOMWale IMStAN AVON MT rE 18 2 2 Frardware InstallallOFiies euren ni het arida sa odi tesa ave Xa AUR RID dat TRE tte unu c UR D RI 20 2a To 6 2 1 O MR E m m R 22 8 dijzg e 23 3 1 Menus ere INNER TT T 26 3 2 FDO Data AMS c 76 3 3 SAUS CS
151. g device Users must carefully read instructions and procedures pertaining to installation and operation Any instrument connected to the unit should be properly grounded A pair of anti static gloves is strongly recommended when performing a task with the device To ensure accuracy and consistency of output data use of the bundled components is strongly recommended Users opinions are very important to Zeroplus Please contact our engineering team by telephone fax or email with your questions or feedback Thank you for choosing the Zeroplus Logic Analyzer Notice We will not have additional notice for you when there is any modification of the User Manual If there is some unconformity caused by the software version upgrade users should take the software as the standard 4 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 1 Features of Zeroplus Logic Analyzer 1 1 1 2 1 3 1 4 1 5 Package Contents Introduction Hardware Specifications oystem Requirements Device Maintenance and Safety FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Objective In this chapter users will learn about the package contents description hardware specifications system requirements and safety issues of the Zeroplus Logic Analyzer Although this chapter is purely informative we highly recommend reading this carefully to ensur
152. ge Video Pulse STEP 12 Select DSO_CH1 and DSO CH2 channels to analyzer AO A1 channels of LA Below is the waveform it captured We ZEROPLUS LAP C 321000 Standard 3 11 CHO1 S H 00000000001 LaDoci E P BE x File Bus Signal Trigger Run Stop Data Tools Window Help m gj x Dc amp me e SS bb 2K x i 1OMHz m om we 5096 Te S Page fi Count i E R Ri e i 2 4us R nt Ax B Te tle gt i ill Height 28 Trigger De 100ns Font Siz 12 Scale 418 BETKHz Display Pos Ons A Pos 16 8us v A T 59 524KHz v A B 25 62KHz v Total 204 Bus Display Range 60us 60 2us B Pos 22 2315T9us v B T 44 981Khz v Compr Rate Ho Bus Signal Trigger Filter a 48us 36us 24us n 12us H 12us E 36us 48us t 1 t i t 1 t 1 1 Li t i t 1 1 t 1 t t t t 1 t 1 1 Li t i t 1 1 t 1 t t i t 1 i 8v 4V DSO_CH1 oy DSO_CH2 ov gaoa i E Unknown g Al v Pe Unknown v as re a Unknown e M Unknown gas Unknown e a Unknown Pa Unknown g 5 Unknown v ei Unknown PIE Unknown e B3 Unknown e 5 Unknown 194 FM0714A 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 9 Troubleshooting 9 1 Installation Troubleshooting 5 2 Software Troubleshooting 5 3 Hardware Trouble
153. ght v Trigger Delay l ms Scale 100Hz Display Pos ns A Pos ETE A 6 667Hz v A B 3 333Hz v Total 20 48s Display Range 250ms 270ms B Pos 150m B T 6 667Hz v Compr Rate No a a v200ms fms 100ms 50ms Uns 50ms 100ms f5Ums 200ms 250ms V Bu S LAANAAAAAAAAAAAAAAAAAAAAAAARAAAAAAAAAAAAAAAAAAAAAAAAXAA PLL UU VEDLTEELTTU LEFEPETEFLTHEEUBHEEEETE ULET Lj l Packet Name Timestamp Data Data Data Data Data Data Data Data Data Data Length o 1 2 3 4 5 6 7 0 1 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length 2 3 4 s I6 7 Io 1 92 3 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length La s 6 j 7 j o r 1 292 3 4 5 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length 6 7 0 p p 41 3 4 5 p 56 7 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data Length Ady End DEMO Fig4 39 Bus Packet List Packet List has a setup window users can set up the Packet List according to their requirements Setting 113 FMO7IAA Phe PAR 0 BPRS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Bus Packet Length in dialog box is only used for doing Bus Statistic Users can define how long the time is as a data packet to add the export function See the following figure Sett
154. has to convert Data line from the high logic to the low 3 Data line must be kept as low as us 4 The Output Data of Slave must be 14us at most 5 To read from 15us where Read slot starts Master must stop driving I O Read data Time Slot VPULLUP VPULLUP MIN VH MIN MASTER SAMPLING WINDOW m RDV gt RESISTOR ASTER DS2432 VIL MAX 0V Fig4 98 Read data Time Slot 6 When Read Time Slot ends I O Pin will be pulled back to the high count through the external resistor 7 During a write cycle all Write time slots must have duration of at least 60us and a recovery period of 1us 4 Typical 1 WIRE Conversation model can be summarized as below A typical 1 Wire conversation Reset CUN Presence Puks Nut Meit Pulsa N READ OF WRITE DATA EE Paat Sequence LET ROS PUR VOR B Huts o MEMORY Command Code Unique FUNCTION device ix selected Command Code Diagram 1 trpical 1e coena sequence Fig4 99 A Typical 1 WIRE Conversion 1 Master keeps Protocol Analyzer at low signal standard speed 480us high speed 48us as the Reset Pulse 2 Then Master releases Protocol Analyzer and locates a Presence Pulse responded by any online Slave 3 The above two points are Reset Pulse and Presence Pulse which can be put together as a Reset Sequence 4 If Presence Pulse is detected the slave location will enable Master to access Slave using the
155. he Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 STEP 4 After filtering the waveforms that are not bigger than 5 clocks are deleted Bus Signal Trigger a E 10 5 a 5 10 15 20 pups pt CEETOE GNE Ei on TEUER a a n mee i 2048 2048 Fig4 151 Waveforms after Filtering STEP 5 Reserve the original waveform open the Noise Filter window and then select None the waveform will be restored Noise Filter x Moise Filter None Fig4 152 Restore the Waveform 175 FM0714A 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 9 Data Contrast In order to make users analyze the Data and contrast the difference of Data easily there are adding the function of Data Contrast The function of Data Contrast is used to compare the difference of two signal files of the same type One is the Basic File and the other is the Contrast File It can line out the different waveform segments of the basic file in the contrast file Meanwhile it can count the number of the difference 4 9 4 Basic Software Setup of Data Contrast STEP 1 Click Data on the Menu Bar then select Xi to open the Data Contrast Settings dialog box 176 Data Tools Window Help 4 4 99S Data Contrast Settings X W Active Data Contrast Contrast Files Basic File 2 alc Contrast File 1 alc m Error Tolerance None C Beginning of Data Cont
156. igger mi Range the dialog box will appear as shown in Fig4 16 Tip This function is mainly for the range control for the saved files after triggering According to the procedures of the range control users can start the save of data according to the requirement of its time and times to get the standard of data statistic status Trigger Property AXI Trigger Content Trigger Delay Trigger Ranae Range Setting Time Sample i minute Cancel Default Help Fig 4 16 Trigger Range 1 Trigger Range The default is not activated 2 There are Time Sample and Frequency Sample in the part of Range Setting the default is Time 102 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 sample The units of Time Sample are second minute hour and day The unit of Frequency Sample is times Users can set the value by themselves in the editor box Task 3 Bus Trigger and Trigger Mark Setup Step1 Click icon or click Bus Trigger Setup and Trigger Mark from the Trigger on the Menu Bar The menu is shown as Fig 4 17 6 Bus Trigger Setup Channel Trigger Setup Trigger Property Trigger Mark 4 Pulse Width Trigger Module ption Ser Don t Gare H High Eier LOY a Rising Edge FAS Falling Edge 3 Either Edge Reset Fig 4 17 Trigger Menu Step2 Bus Trigger Setup 1 Bus Trigger Setup Bus Trigger a
157. ilter is to use an alterable judgment circuit which can filter undesired signals in order to capture and store valuable data in the memory When the combination of input signals from each channel meets the filter conditions the section of acquired data will be gathered by the Logic Analyzer and stored in the memory After storing the data it will return to the Logic Analyzer s system and be displayed as a waveform If the combination does not meet the filter conditions it won t gather and store data 1 s Don t Care means that the Logic Analyzer captures all signals from sampling Filter Condition delay time stam edge Ld Filter Condition delay time ius m start edge Fig 3 23 High and Low Levels It is the system default and displays the input signals satisfying the high level 3 Low Level means that the Logic Analyzer captures and displays the input signals satisfying the low level FMO7IAA P BE AIR Be 2 ARAE Zeroplus Technology Co Ltd iy Channels Setup Tip iy Channels Setup Tip Add Bus Signal Delete Bus Signal Delete All Restore Defaults Group into Bus Cri Reserve waveform data and show them Ungroup From Bus Ctrl U Expand 36 The Zeroplus Logic Analyzer User s Manual V3 11 Filter Condition delay time Filter Condition end edge delay time Fig 3 24 High and Low Levels Signal Filter Delay Setup Filter Delay According t
158. in the Plugins as the Fig4 35 111 a SsSSss rmm E Ee six File Ech wea Fae cc9r Halo JARE d fkgcAaWb Pug Fugit Pagel d PupusTdi Sai an ter bo sie its description mnc py meie Bor Mab mn fy Lapa er Fig4 35 PluginsA FMO7IAA PRET RAR 3 ER 23 8l The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 STEP 2 Select CAN 2 0B in the Protocol Analyzer list Bus Property 2 color Config e Activate the Latch Function e Q ZEROPLLIS L CAN 2 068 MODULE Vv1 32 00 CMO1 ZEROPLUS LA I2C EEPROM 24LC561 24LC562 MODULE V1 00 00 CN01 ZEROPLUS LA I2C MODULE 2 01 03 ZEROPLUS LA LG4572 MODULE V1 00 00 CN03 ZEROPLUS LA PECI MODULE V1 11 00 CN01 ZEROPLUS LA PT2262 PT2272 MODULE V1 00 00 CM01 ZEROPLUS LA S2Cwire AS2Cwire MODULE v1 00 00 CNO1 ZEROPLUS LA SPI MODULE V1 11 03 ZEROPLUS LA UART MODULE V2 13 00 CN01 Fig4 36 Bus Property STEP 3 Click Parameters Configuration button select Register and enter the Serial Key PROTOCOL ANALYZER CAN 2 06 eraut Fig4 37 Protocol Analyzer CAN 2 0B Register dialog box 112 FMO7IAA 2P BETIS AR ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 4 Bus Packet List Bus Packet List is a graphics list which is used for doing Statistics and showing Bus Packet List It is visual and direct especially for I2C USB 1 1 and CAN 2 0B When
159. ine and Clerk Triggar Dalay Tima LU inci arri Min Ons Wax 188 SSi p Trigger Position Trigger Delay Clock i ac CH z Win 1 Wan 158582511 m T Fas ns Ztort Fos 131 08us End Fos 1 1T388es xal Wate Ehin mora than ena trigger pager ora z l ctad the triggpar bar diszuppearz from the view Fig 4 10 Trigger Page and Screen 1 100 FMO7IAA 101 2P BETIS HE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 a ZEROTLUS LAP TEED Standard 3 11 CMU1 S N ETT 418i xj sl Trigger Eun p Bata Tools Find alaj x ro araw S p pp Tea ae ol ft xx 5 Count fs m a e R Rl gt d B 2 151904u eR E A p OM le Height 30 v Trigger Delay 1005 Scala 454 TOSKH Display Pos 5 2428881 A Pos S 1219at Ae B T X A B 3 330MM v _Teted 1 9107205 Display Range S 12002ex 5 B Pos S i122Z2ms T gt Compre Rate Be Bus 53 gal Filter L 1gsbizas 5 5 21060ims 5 221361as 5 232izms 24 M DM 23364es s 26439 as S 27SiStas 5 28 5 2esoitas S 3 ine Km all IUUUUUUUUUUUUUUUUUL MUL UT sf K ILILILILTI Az A Trigger Content Trigger Delay Tri ecer Rance 1 z da J Trizzer Pues C Delay Time and Clock OM SZ rTrigge Pese Trigger Delay Tine nds Bg Mint Wax 2 Mia 10as Man 188 St2Sins r z Trigger Pos
160. ing x Bus Select Data Format C Binary Decimal C ASCII C Gray Code Complement Bus Packet Length Mint 1 ms l00ms Max 20 485 Packet Item M Packet W Name W TimeStamp Length Data Text G a Text Color Auto Cancel Default Help Fig4 40 Packet List Setting i Refresh Export Synch Parameter Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Data ml LO 1j 2 j 3 j 4 5 j 6 7 O0 1 Length Data Data Data Data Data Data Data Data Data Data L2 3 4 s 6 7 o 1 2 J 3 Packet Name TimeStamp Bus1 Bus 10 13s Packet Name Timestamp Data Data Data Data Data Data Data Data Data Data Length 4 5 6 7 o 1 2 3 4 5 Packet ETE TimeStamp Data Data Data Data Data Data Data Data Data Data Length L6 7 o 1 2 3 4 5 6 7 Data Data Data Data Data Data Data Packet Name TimeStamp Data Data Data Fig4 41 Bus Packet List 1 View Specifications Packet Name and TimeStamp can be selected to display from the Packet List Setting dialog box Packet List the order of Packet Name Display the name of Packet or the Filter Display Bar TimeStamp It is the starting point of the Packet Tip The rest name and content are supplied by Plug 114 FMO7IAA 2P BE HS BR 0 3 ER 23 S The Zeroplus Logic Analyzer Zeroplus Technology Co
161. ion or higher Display Device At least 100MB available space At least 100MB available space USB USB1 1 supported USB2 0 recommended 14 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 1 5 Device Maintenance and Safety Follow these instructions for proper operation and storage of the Logic Analyzer 15 Table1 7 General Advice Cautions Do not place heavy objects on the Zeroplus Logic Analyzer Avoid hard impacts and rough handling Protect the Logic Analyzer from static discharge Do not disassemble the Zeroplus Logic Analyzer this will void the warranty and could affect its operation Cleaning Use a soft damp cloth with a mild detergent to clean Do not spray any liquid on the Zeroplus Logic Analyzer or immerse it in any liquid Do not use harsh chemicals or cleaners containing substances such as benzene toluene xylene or acetone Table1 8 Electrical Specifications LAP A Series amp LAP C Series items Minimum Typical Maximum Current at Rest CurentatWok PoweratRet o PowratWok J A DC 30V Error in Phase Off DC 30V Input Resistance 500KO l0pF Working Temperature S C Storage Temperature 40 C Refer to the User Manual for error analysis calculation FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zerop
162. ip Left click on Trigger column of the Bus as shown in Fig 4 31 Bus Signal Trigger Single Click on the Left Key YV Bus ean 40 eA i ea2 42 iG A3 A3 Fig 4 31 Trigger Column 109 FMO7IAA BE 32S BPR 8l The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 2 Set Binary Hexadecimal Decimal Decimal signed ASCII Gray Code or Complement as the Data Format of the Bus to represent the value see Fig 4 30 3 Set and Don t Care and type the value of the Bus into Value column to set the trigger condition of the Bus 4 Click OK to confirm the settings Step4 Click Run and activate the signal from the tested board to the system to get the result as shown in Fig 4 32 Tip Click icon to view all data and then select the waveform analysis tools to analyze the waveforms Set Value is 2 as Hexadecimal and set Operator equals to then click OK Click Run and activate the signal from the tested board to the system to get the result as the trigger happens on 0X2 File Bus Sig rigger fax j o 00MH z o mu 509 v 4 Page fi j Count fi Dc E amp mA TRI JP l Ej EB OR Gh ios fe Rae BB De B 0 ES o Been 30 z Trigger Dey 1 Scale 27 5301532 Display Pos 343 p 64527 A T 64527 7 A B 30 7 Total 131072 Display Range 345 1034 B Pos
163. is the presen ispla wey ZOOM OU 8 p pray EE Show all Data itn mode x Previous Zoom Ghr z nee ST ES ET eens ETE een Data Format gt Tapia ET ER ET ERI T Sampling Changed Dot MGR MSIE Se ist Data Mode Compression Take the sampling BEN Sampling Changed Dot Compression changed dot as the compression dates DE Dt hanoed Dot icompression reference dot Fig 3 70 List Data Mode All Data Sampling Data Changed Dot Compression Changed Dot Compression and Data Changed Dot Take the present data change dot as Compression the compression data reference dot FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 6 Tools lace eT x Color Setting BUS Bus Property Common Setup Toolbars Shortcut Kep Auto Save ae Refresh Protocol amp nalyzer mg Multi stacked Logic Analyzer Settings Analog Waveform gt Waveform Display Mode Sampling Site Display Frequency Display DSO stacked Settings Hide time of waveform Ruler Mode Regular Ruler Waveform Setting wW avelarm Height TimesSampling Site Ruler Font Size Correlated Setting Auto Close pen Close Compression Warning Show Gridline Iw Show the T Bar in the middle area 4 Show Tooltip Open Close Double warning Ie When the roller iz moved toward back the Time xis in the waveform area will mowe toward right Data Proces
164. istics icon i and an interface like Fig 3 131 or Fig 3 132 will appear x Column Selection Condition Parameter Warning Parameter Refresh Statistics Filter CHANNEL Full Period Positive Per Negative P Conditional Conditional Conditional StartPos EndPos sSelectedData l AD 211 212 211 0 0 0 Ds Dp Al 52 53 52 0 0 0 Ds Dp A2 0 0 1 0 0 0 Ds Dp A3 0 0 1 0 0 0 Ds Dp A4 0 0 1 0 0 0 Ds Dp A5 0 0 1 0 0 0 Ds Dp A6 0 0 1 0 0 0 Ds Dp A 0 0 1 0 0 0 Ds Dp BO 0 0 1 0 0 0 Ds Dp B1 0 0 1 0 0 0 Ds Dp Fig 3 131 Statistics table TT ATETEUETEXEZDTTPEITTNMUTTTTTTSBBE 19 xj Ded RA wre BD DD lex ven sMHz ow so Page 1 Count fi Sil BB Gk 8 Ole MB 1450216 t R aa EI n Bee m Heow 22 TrggerDelay 2005s Scale 609 552KHr Display Pos 145 021634us A Pos 52 0884ens gt A T 19 190K gt A B 16666710 gt Totai78 6034ms Display Range 108 76622505 BPos 520024m B T 192r Coenpr Rate 1 91 903 ws Tape fan 123 2663650s 130 51 132 22055204 145 001654 152 22271604 155 562329708 166 774875 174 0655104 181 27708 YV asne em X PLL LL LLL LLL Ln m m 1 m LN f 1 en ai si a3 I ob M P Chaneed Selection Column Selectxel Condibon Foros Warrang Parameter CHANEL rdiPenos Postave Per Negative P Condition 21 2 9 9 12 21 To occ oo cfr ae SARKIS ARES A
165. ition q p Trigger Delay Clock ei E pe o X Wis Max 16699751 en X T Por One Start Por 5 11182as End Pos 6 42254as ES X Wote Then more than one trigger pages are selected the trigger B8 a bar disappears from the view T Caneel Default Help Fig 4 11 Trigger Page and Screen 2 2 Delay Time and Clock Click the Delay Time and Clock then type the numbers into the column of the Trigger Delay Time or type numbers into the Trigger Delay Clock at the Trigger Delay page of the Trigger Property dialog box as shown in Fig 4 11 Or type the numbers into the column of Trigger Delay Trigger Delay on the Tool Bar The system will display the Start of the waveform Tip The formula of Delay Time and Clock is Trigger Delay Time Trigger Delay Clock 1 Frequency To use the compression mode the lt Delay Time and Clock gt will be unavailable Step5 Trigger Position Setup Type the percentages or select the percentages from the pull down menu of the 50 9 on the Tool Bar or click the pull down menu of the Trigger Position on the Trigger Delay page of the Trigger Property dialog box as shown in Figs 4 12 4 13 4 14 and 4 15 The selected Trigger Position percentages will be displayed on the right side of the screen of the system X Trigger Content Trigger Delay Trigger Range C Trigger Page Delay Time and Clock Trigger Page Trigger Del
166. itions of the Signal Filter or the Filter Delay Setup if there aren t any results Tip Click icon to view all the data and then select the waveform analysis tools to analyze the waveforms Filter es Setup Select Filter Delay Mode Select Delay Stark Point Delay Time According to Filter Condition f Start Edge 100ns C End Edge Min 100ns Opposite of Filter Condition Period Delay Max amp 553ms Fig 4 141 Filter Delay Setup 170 FMO7IAA 2P BETIS RR 2 BPR uj The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Tip Definitions of the Start Edge and the End Edge and the Period Delay are listed as Figs 4 142 4 143 4 144 and 4 145 time o Filter Condition delay time stait edge Fig 4 142 Start Edge Filter Condition Filter Condition delay time end edge j Filter Condition end edge delay time Fig 4 143 End Edge Filter Condition period delay time Ll Filter Condition period delay time Ld L Fig 4 144 Period Delay 171 FM0714A 2P BETIS RR 20 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 oid Fue 20 395us hs 46us _ MAL 355 ET f Filter Condition Trigger Condition Pi Porta REESE Tm m E Z mW g EK B pude Trigger Condition 5 p Pont poe Filter Delay Setup v Activate Filter Delay Select Filter Delay
167. its parity is Even Parity 133 FMO7IAA 7P BE TFS AR 00 BBR ul The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Packet4 It is commonly normal Data which includes 1 Data and 1 Parity its parity is Even Parity Packet Length When judging to the start of UART it is the packet TimeStamp State 1 Having Stop The data start is regarded az The Unknow Register is Unknow_End Flag Packet Timestamp Packet Lenath Fig4 80 Packet Length State 2 No Stop This linknow Register is general Bus Unknow EDEN hiz Unknow Register The data start is regarded as iz Unknow End Flag Tinestanp Packet f Eom JEN RX TX d Facket Length ty s Data Length 1 1 5 2b3 1 Fig4 81 Packet Length If the STOP falls short of condition it isn t noted down in UART Packet Length From START Starts TimeStamp to STOP Unknow End Flag TimeStamp Packet Idling Length Unknow End Flag TimeStamp to START TimeStamp 134 FMO7IAA BB tt Ae 2 f3 ER 2S 8l Zeroplus Technology Co Ltd 4 5 4 SPI Analysis SPI Introduction The Zeroplus Logic Analyzer User s Manual V3 11 SPI Synchronous Peripheral Interface is a parallel synchronous full duplex protocol with a Bus like physical interface This protocol was first developed by Motorola and was generally used for EEPROM ADC FRAM and display device drivers which are equipped with
168. j qe Dee 509 Port i we 1 1271410128 pia Foy 13 berots APus t10 E A faighinns ms Tote JD obm Conger Marge 132 107949 a fea Sire BETren Commer 0 gt ha b tee s A M an caved re a S a a a E N en E C p r mows Ome Oe 2 f a too tur cove Fig3 56 Add a Bar with the number between 0 and 9 FMO7IAA O PPB A 5 AS OS BRA 8j Zeroplus Technology Co Ltd mh Delete Bar Alt B ar Delete a user defined bar 1 Click the above menu item from Data menu or click Delete Bar icon from Tool Bar 2 Select a user defined bar and click on Delete 3 Delete the selected Bar with the Delete key on the Keyboard Use the mouse to select the added bar and press the Delete key on the keyboard to delete the bar ts Zoom E hi Tip A Zoom In or a Zoom Out view will be centered in the Waveform Display Area and the new zoomed view will be sized according to the available space on the display 49 The Zeroplus Logic Analyzer User s Manual V3 11 Delete Bar x Clase Fig3 57 Delete Bar Dialog Box Fig 3 58 Delete a selected Bar 40 35 5 20 Lil des LX dL Fig 3 59 To Zoom In left click and drag FMO7IAA BE HS Ae 2 f3 ER 2S S Zeroplus Technology Co Ltd The Zeroplus Logic Analyzer User s Manual V3 11 the mouse point from left to right When users activate the Zoom to zoom in zoom out the selected area the Tooltip on the
169. ket List BUS Packet List x Setting Refresh Export Synch Parameter Packet Name TimeStamp Data Data Data Data Data Data Data Data 1 Busi 67 Packet Name TimeStamp Data Data Data Data Data Data Data Data Data Bus SPI 12 23 34 45 56 67 78 89 9A Packet Name Timestamp Data Data Data Data Data Data Bus SPD amp Fig4 87 Protocol Analyzer SPI Packet List Packet Length and Packet Idling Length 1 SS channel is activated 55 Rising Edze iz the 55 Falling Edea iz start of the packet start of the packet Unknow Start r lay E Unknow_End Falg SPI SCK ERI DATA Packet Lensth Fig4 88 Packet Length Packet Length From Unknow Start Flag TimeStamp to Unknow End Flag TimeStamp Packet Idling Length From Unknow End Flag TimeStamp to Unknow Start Flag TimeStamp 2 SS channel is not activated 138 FMO7IAA BE 32S BPR 8l The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Virtual SS is activated 1 Data needs 8 bit the Idling Time is set as 3us 2 355us is less than Unknow registers c m iu the packet Idling time so the Unknow End Flag informati ion after 2 355us isn t data 1605s 3 Sut ste i v N P 3i Packet T eneth If the time length of SCK low fs S7Sus is Mamer than Level is bigger than idling time Idling Time
170. lement Cancel Default Help T Before Registering Register Dialog Box x The Function is an optional purchased item Welcome to purchase its serial key to activate this Function For your necessary Enter serial key IF vou ordered software or have questions about ordering software please Follow Ehe appropriate instructions below Our sales team will respond to your enquiry as soon as possible gt gt By phone B56 2 66202225 gt gt Applications through Email service _2i zeroplus com tw gt gt Website http www zeraplus cem Ew Copyright C 1997 2011 ZEROPLUS TECHNOLOGY CO LTD cna Bus Trigger X Bus Trigger Protocol Analyzer Trigger r MT Analyzer Protocol Sedi Value ge Busl IzL fo ic ADDRESS i Read Data Format i White Binary im AACE Decimal i ANALE C pecimal Signed iC DATA Heszadecimal C D ACK m SSE D NACK Gray Code Stop ic REG ADDR Cancel Default Help Fig 4 19 2 After Registering f Complement Allow Protocol Analyzer Trigger When it is selected the Protocol Analyzer Trigger function is activated And then users can set Protocol Analyzer Protocol Packet Value and Data Format 104 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Protocol Analyzer It only displays the name of Protocol Analyzer and only one name can be selected Protocol Packet It is displayed according to
171. level Compression Mode Signal Filter RAM Size ok W Data Compression Signal Filter Setup Channel number will be limited bo 24 Apply iL Cancel Restore Defaults Help Fig 3 20 Sampling Setup See Section 4 1 for detailed instructions Tip m 728 OF 4 Icon Description ek ae ba 5 0MHz A reri ha Decrease tll4 RAM Size Fig3 21 RAM Size a Increase Choose the RAM Size and the internal clock frequency from RAM Size the pull down menus Decrease Mes Internal Clock Frequency Increase A Internal Clock Frequency RAM Size The amount of the acquired data that can be stored by the Logic Analyzer depends on the amount of the allocated RAM The total depth of the memory for the LAP A C is 128K Bits in each probe If the Logic Analyzer starts gathering data with a 128K memory range it will take a long time to find the required information In order to avoid spending a lot of time gathering data select a smaller RAM Size The RAM Size options are 2K 16K 32K 64K 128K and 256K So if gathering data with 128K takes a long time why does 256K make sense The reason for this extra RAM Size is to cope with the fact that a few of the 1 16 channels may have a large data input Tip Use the pull down menu to choose the speed of the clock on Clock Source the board being tested Asynchronous Clock The sampling frequency should be more than 4 times higher than the signal to be measured so that the waveform duty cycle depic
172. low data transmission speed The SPI data transmission is synchronous in both receiving and transmitting directions Although Motorola initially did not define the clocking impulse it is commonly seen that the clocking impulse is according to the master processor In practice there are two clocking impulses CPOL Clock Polarity and CPHA Clock Phase The configuration of both CPOL and CPHA decides the sampling rate When the SPI must transmit serial data it initiates the highest bit 135 Since SPI is a synchronous communication protocol and data transmission may not be in bytes a complete SPI signal Packet must consist of SCK MOSI MISO and SS segments with CPHA and CPOL They are as following SCK Serial Clock Line SCL MOSI Master data output Slave data input MOSI stands for Master Out Slave In MISO Master data input Slave data output MISO stands for Master In Slave Out SS SS stands for Signal Selector of the master device which is to select signals for the Slave devices CPHA The clock phase CPHA control bit selects one of the two fundamentally different transfer formats CPOL The clock polarity is specified by the CPOL control bit which selects an active high or active low clock Dor albsadan saris ellos va amid eg ema Fhe ht Faba D deo DB hang ve colo hop pee Chak Pine Oe ee vence gne ect fhe daria mo num urbe sme ed ag WI te Giggi Folarity 1 where Hng edgen ha ey Clink PRraee Q where w
173. lt is 1s and the unit can be selected from s second m minute and hr hour Every Renewal When the repetitive run is activated the waveform image or the state image will renew again and again Open the first file after stopping the Run When the repetitive run function is activated the waveform only displays the first file and it isn t renewed when the repetitive run is stopped the waveform still displays the first file 89 BA Dua HSEEEEEEEEEEESSEEEELEEELLLE LLLLLLLLLLO OO p ICEAEATDZZZLLZZ ZDZ 2 D ZZiLL S xi t D Fig3 152 Auto Save FMO7IAA 90 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 3 6 Color Setting To modify Color click Tools gt Color Setting x Workaround Waveform F Relating aveform Background List Backaraund 1 List Background 2 Cursor Grd ENMENEEENENNENEENH After the background i altered corresponding color dE es automatically changes according ta the contrast ratio When being printed the I background iz white Cancel Default Help Fig 3 153 Workaround and Waveform Color Setting Workaround Set the workaround color of the Logic Analyzer and the text Color Setting X workaround waveform avehorm Background List Background 1 List Background 2 Cursor r r M r M r M r M M M r Fig 3 154 Workaround Color Interface Waveform Background
174. lus Technology Co Ltd User s Manual V3 11 Table1 9 Operating Environment WARNING Avoid direct sunlight Use in a dust free non conductive environment see Note Relative Humidity 8096 Altitude 2000m Temperature 0 40 Degrees C This is a Class A product which may cause radio interference in a domestic environment Note EN 61010 1 2001 specify degrees of pollution and their requirements Logic Analyzer falls under Level 2 Pollution refers to addition of foreign matter solid liquid or gaseous ionized gases which may produce a reduction of dielectric strength or surface resistivity Pollution Degree 1 No pollution or only dry non conductive pollution occurs This pollution has no effect Pollution Degree 2 Normally only non conductive pollution occurs Occasionally however temporary conductivity caused by the condensation must be expected Pollution Degree 3 Conductive pollution occurs or dry non conductive pollution which becomes conductive due to the condensation occurs In such conditions the equipment is normally protected against exposure to direct sunlight precipitation and wind but neither temperature nor humidity is controlled Storage Relative Humidity 80 Environment Temperature 0 50 Degrees C Conclusion After reading this section users should have a basic grasp of the Logic Analyzer A complete understanding of the section Device Maintenance and Safety is a critical prerequi
175. lution can be adjusted to 1 Baud Rate The Baud Rate can be set to Integer or selected from the pull down menu 10000 20000 40000 50000 80000 100000 125000 200000 250000 400000 500000 660000 800000 and 1000000 manually and the default is 125000 If the Auto is selected the Baud Rate can be calculated by the main program automatically and displayed on the CAN 2 0B dialog box Data Reverse Decoding If it is selected the data can be decoded in reverse After End Packet happens just begin to analyze If it is selected the signal will be decoded when the End Packet appears When CAN Data for expansion combine Basic ID and ID If the option is selected the Basic ID and ID will be combined FMO7IAA 2P BE HS BR 03 ER 23 8j The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 The Del is displayed in CRC Field If it is selected the Del will be displayed in the CRC Field Protocol Analyzer Color The protocol analyzer colors can be varied by users Operating Instructions Turn on the user interface of the Logic Analyzer Y ZEROPLUS LAP C 32128 Standard V3 11 CN01 S N 000000 0000 LaDoc1 o File Bus Signal Trigger UE Data Tools Window Help 25 ja Ir IEJ Ey Bpo gT ge B D gt DD 2K vy iei 10MHz v an mw ud E Page fi Count fi Tu E oms a Rn OBS IE Boe re sey enn Egtatgtatgay EglgERRHRNRE REgERESERES gans Iq 1 11 eaga I LI Fig4 128
176. m Display Area even with an old black and white laser printer FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 5 3 Hardware Troubleshooting Q1 Why are no lights on when I hook the USB cable to the Logic Analyzer A Double check whether the other end is properly connected to your PC There may also be a defect in your USB cable Try another cable Q2 Why can t I read any signals from my Logic Analyzer A Check whether you have correctly connected the signal cables to the activated pin on your test board and check the power supply of your test board The Logic Analyzer does not supply any electricity to a test board via signal lines Q3 I get a signal from only one Logic Analyzer when I have two connected what is wrong A Currently only the LAP 32128U A LAP 321000U A LAP 322000U A LAP C 32128 LAP C 321000 and LAP C 322000 support many Logic Analyzers working in series Also make sure that the signal lines power lines and ground line are properly connected Refer to Fig 1 11 Table 1 2 Table 1 3 Table 1 4 and Table 1 5 Q4 Why should bother grounding Where can ground A Grounding will protect the Logic Analyzer and the test board A proper ground may improve the quality and accuracy of your data Since it is impossible to avoid unwanted interference you may ground the Logic Analyzer with the test board to ensure that unwanted interference will equally distu
177. me of waveform 84 FMO7IAA Zeroplus Technology Co Ltd User s Manual V3 11 O 2P BETIS AR 2 ARAS The Zeroplus Logic Analyzer 3 4 2 Modify Ruler Mode Use the menu to modify the Ruler Mode Go to Tools and click Customize See Fig 3 142 x Common Setup Toolbars Shortcut Key Auto Save Waveform Display Mode Sampling Site Display Frequency Display Time Display Waveform Setting Waveform Height 22 C Regular Ruler Time 5 ampling Site Ruler Font Size 12 Fig 3 142 Ruler Mode Regular Ruler Fig 3 143 Scales in Regular Ruler Time Sampling Site Ruler Oris hs ang uns H Zong ans n l l l l l l l l l l l l l l l l l l l l l l l l l l Fig 3 144 Scales in Time Sampling Site Ruler Ruler Mode There are two styles of Ruler Regular Ruler Time Sampling Site Ruler Regular Ruler Presented in increments of 5 Time Sampling Site Ruler default Presented in increments of 25ns 85 FMO7IAA 86 Zeroplus Technology Co Ltd User s Manual V3 11 O 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer 3 4 3 Modify Waveform Height amp Correlated Setting To modify Waveform Height click Tools gt Customize Waveform Height Set the height of waveform 18 100 in chosen items at toolbar that will show the amplitude of the waveform x Common Setup Toolbars Shortcut Key Auto Save Waveform Display Mode C Sampling Site Display C Fre
178. mg 8 Cascade Horizontal Vertical Screen Display k w 1 LaDac5 Fig 3 84 Window Menu Fig 3 85 Window Tool Box Menu Bar Windows Menu Item Detail Menu amp Dialog Box File Bus Signal Trigger Run Stop Data Tools window Help Dc amp fey us gi an gill P A Waveform Display yr 200K TAM i au Listing Display Eg k I amp did B ons Ln Scale 200MHz Display Pos Hot News Window gt Frons Total 10 24us Display Ran _ Real time Monitoring Preng m Navigator Bus Signal Trigger Filte sm Memory Analyzer 5 ns Waveform Display L L iru D g 0 n Se SZ fij Bus Packet List d ua gt fi Statistics window A2 2 Cascade Q A3 A3 Horizontal A4 4 Vertical Screen Display gt 45 A5 e 6 56 wv llaDocs P 7 A7 B0 B0 E Fig 3 86 Display Signals in Waveform 64 FMO7IAA O 7P BE T SE AR 0 BBR 23 ul The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Bus Signal Trigger Run Step Data Tools Window Help 2 00MHz Display Pos Hot News Window 10 2408 Real time Monitoring ee havigater AU AT AZ A3 A4 gm Memory Analyzer FF ag nus Packet List il Statistics Window i 1E MEE E TEE m m Listing Display Cascade Horizontal i vertical Henke hekwl Screen Display i ones El lLaDacs 1 EEEEEEDEE w 2La
179. mine when the trigger point starts to record the information Tigaen hack Open the Trigger Mark function I See Section 4 1 for detailed instructions Pulse Width Trigger Module Set a trigger condition for a TA Pulse width Trigger ModuleiOption single channel and the signal in this channel can be triggered in the predetermined range However this function is required to use with the hardware of the Pulse It is not necessary to register as it Width Trigger Module If you want to learn the detail can be used for free please refer to the Specification of the Pulse Width Trigger Module Tip Set the trigger condition as Don t Care See Section 4 1 for detailed instructions High Set the trigger condition as High See Section 4 1 for detailed instructions Set the trigger condition as Low mm See Section 4 1 for detailed instructions Set the trigger condition as Rising Edge See Section 4 1 for detailed instructions Set the trigger condition as Falling Edge See Section 4 1 for detailed instructions os Don t Care f Rising Edge Falling Edge 39 FMO7IAA Phe AIR AR 2 ARAE Zeroplus Technology Co Ltd Reset i Trigger Property Tip Trigger Content Setup Icon Description b Decrease its trigger position Fa Increase trigger position N A Trigger Page N A Trigger Count Tip Trigger Delay Icon Description N A Trigger Delay
180. mn then type the given name of the Bus and then press Enter to confirm it 2 Go to the relative channels as shown in the example and go to numbers O 1 2 3 which are located on column A and row Bus1 Click them to become purple then set these segments of channels 3 Click OK to get the result as shown in area 1 108 FMO7IAA 2P BE HS BR 03 ER 23 S The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Channels Setup Fig 4 29 Channels Setup Window Tip Channels Setup In the dialog box of Channels Setup there isn t only Add Bus Signal but also Delete Bus Signal Delete All Restore Defaults provided 1 Delete Bus Signal Firstly highlight the Bus or channels on area 6 of Fig 4 29 then click Delete Bus Signal to delete them 2 Delete All Click Delete All to delete all Bus signals on area 6 of Fig 4 29 3 Restore Defaults Click Restore Defaults to restore the dialog box of Channels Setup as shown in Fig 4 27 Step3 Trigger Condition Setup 1 Highlight the Bus which will be triggered then click icon or select Bus Trigger Setup from the Trigger of the Menu Bar the dialog box as shown in Fig 4 30 will appear Bus Trigger Bus Trigger Protocol Analyzer Trigger Bus Mame Operator Bust Data Format C Binary C Decimal Decimal Signed Hexadecimal C ASCII C Gray Code C Complement Cancel Default Help Fig 4 30 Bus Trigger Setup T
181. n it will go to the corresponding position which is highlighted by the Blue frame STEP 3 Display the Memory Analyzer function in the waveform window Tip The Packet is read the Address is 0X50 the Data are 0X00 0X79 in sequence 184 Y ZEROPLUS LAP C 32128 Standard 3 11 CNO1 S N 000000 0000 12C Oj xl oe File Bus Signal Trigger RunjStop Data Tools Window Help amp 8 x Dc aS d E 0 gb et of Iba bb e 2k ae MM 5MHz mu b50 6 v ke J Page fi Count fi al RP co fh BD 1 450216 6 Rz 86 Be De Be Mi le 9 BS a Height 22 Trigger Delay Scale 1 450216us Display Pos 35 5303us APo0s 52 0884ms M A T 52 0884ms A B 6us v Total 78 6034ms Display Range 725 108169ns B Pos 52 0824md Y B T 52 0824ms v Compr Rate 191 903 Bus Signal Trigger Fite BM 20 tg Ee V Busi I2C Qi eao ao amp _ 2 2f1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 t 2ugt 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2uft 2 2f1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 eal Al x e L 3 2ug 3 2u 3 2u 50 8us 88us 32u e 2 az ex amp e i 78 603ms A3 A3 e 78 603ms d 4 4 e l 78 603ms gas as 78 603ms 6 6 e l 78 603ms a7 47 RI l 78 603ms g 80 50 amp e i 78 603ms g Bl B e i 78 603ms B2 B2 e 78 603ms B3 B3 amp J 78 603ms B4 B4 2s e i 78 603ms f 55
182. n Stop gt Stop Data gt Zoom Out Data gt Zoom In Data gt To the Previous Edge Data gt To the Next Edge Statement Logic Analyzer Help Decrease the sampling rate Increase sampling rate Execute the acquirement once Execute the acquirement continuously Stop acquiring data Zoom out the waveform Zoom in the waveform Move forward to the prior variation waveform and center that location Move forward to the next variation waveform and center that location FM0714A 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 7 2 Contact Us Table 7 5 Contact Us Contact Us Copyright 1997 2011 ZEROPLUS TECHNOLOGY CO LTD Headquarter Taiwan New Taipei City Instrument Division Business Department Taiwan Hsinchu City Taiwan New Taipei City Other Service Departments China Shenzhen China Shanghai ZEROPLUS TECHNOLOGY CO LTD 3F No 121 Jian Ba Rd Zhonghe Dist New Taipei City Taiwan Tel 886 2 6620 2225 Fax 886 2 6620 2226 ZIP Code 23585 ZEROPLUS TECHNOLOGY CO LTD 2F No 242 1 Nanya St North Dist Hsinchu City 30052 Taiwan R O C Tel 886 3 542 6637 Ext 87 Fax 886 3 542 4917 ZIP Code 30052 E Mail Service 2 zeroplus com tw ZEROPLUS TECHNOLOGY CO LTD Address 2F NO 123 Jian Ba Rd Zhonghe Dist New Taipei City Taiwan Tel 886 2 6620 2225 Ext 200 Fax 886 2 6620 2226 Website www z
183. nd Data Value IEEE TEETH FA Find Pulse Width l To the Previous Edge Fli To the Next Edge F12 fro To d Add Bar ALttA i Delete Bar AlttB Fe Zoom E em Hand H ke Hormal ESCAPE vm Zoom In Fd E Zoom Out Fa show all Data F1 x Previous Zoom trit lata Format k Waveform Mode k wo Square Waveform einen F Sawtooth Waveform Fig 6 7 Waveform Mode The second alternative is to right click any place in the Waveform Display Area Then a menu will pop up Click Waveform Mode and choose a waveform See Fig 6 8 204 FMO7IAA Phe AIR Be 2 ARAE Zeroplus Technology Co Ltd B Find Data Value LE Find Pulse wW idtkh Gn Ta Place t Add Bar bee Zoom e Hand k Normal 558 Show all Data x Previous soom Data Format Waveform Mode Color Bus Data olor Bus Single Gate calar The Zeroplus Logic Analyzer User s Manual V3 11 Ctrl F E H ESCAPE F10 Gtr Hz iv Square waveform Sawtooth Wawveform Fig 6 8 Waveform Mode SW15 Can I change the Signal Display Mode into the Timing Mode A Yes you Can SW16 Why does not Filter Delay work when the Double Mode is enabled To optimize signal output quality and maximize memory efficiency the Signal Filter Setup function may work under the Double Mode However the Filter Delay function doesn t work under the Double Mode at A 205 this stage FMO7IAA RGO1 RGO2 RGO3
184. nd other node have the chance to retransmit themselves information 160 FMO7IAA Set 161 2P BETIS AR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 7 1 Software Basic Setup of Protocol Analyzer CAN 2 0B PROTOCOL SNALYZER CAN 2 06 Configuration Packet Data Format Register Pin Assignment Start Packet Format Protocol Analyzer Name Bus 111Bit Start henne ais OBit Start Protocol Analyzer Property Data Reverse Decoding Percentage 5 ample BU After End Packet happens just begin to analyze Baud Fate 125000 Auto When CAN Data for expansion combine Basic ID and ID Min bps Man 7 OME rte Min bps Max ps Iw The Del is displayd in the CAC Field Error CRC ID Data Overload Control Fig4 127 Protocol Analyzer CAN 2 0B Configuration dialog box the CAN 2 0B Configuration dialog box Pin Assignment Protocol Analyzer CAN 2 0B only needs one channel to decoding signals the default channel is AO Start Packet Format The Start Position can be divided into two formats 111 Bit Start the Start Position is that three bits are High and O Bit Start the Start Position is that one bit is Low Protocol Analyzer Property Percentage Sample The Percentage Sample should be entered in the position of the Baud Rate which is selected from the range between 25 and 75 and the default of the Baud Rate is 60 The reso
185. ne VLUU means low patent Ti VR meam Rising Edge CEU prevents Falling Edge E stands Tor Either Hi The dipli and trigger sebup of Bis According the character of thi original file bo present The deuplu of message Total 20 dBem Sooke Ln Keeping The sert mgs mn eventa t reproduce channels amd fines r Chamel haer AUD Al As A3 4 A Ab AP EX E1 Bi B ui n Et By L Cl tz ca C4 ch Lh Ci oo Dl nz n3 Ui D3 Di n E Fig 3 8 Export File FMO7IAA Phe AR AR 0 BPR Zeroplus Technology Co Ltd C Export Packet List 29 The Zeroplus Logic Analyzer User s Manual V3 11 Export Packet List 2 xl C3 signal D E3 Save in Y Fe My Recent Documents Desktop TA My Documents pE My Computer S My Network File name laces Text Files txt m Export Format Report Form Cancel Save as type Data Format Hexadecimal r Bus Output Parameter Yes C No r Output Range From First Packet 1 IV Pop up an export file automatically To Final Packet Fig 3 9 Export Packet List Dialog Box Users can use paperwork register and analyze packet list data Pop up an export file automatically The function of popping up an export file automatically in the Export Packet List dialog box is the same with that of the Export Waveform dialog box Export Format The Export Format is convenient for users to use the captured d
186. o the filter condition Start Edge Show the waveform from the start edge to the delay time interval See details in Section 4 1 E m m mn A mum men in or DOS l a2 8 ocoacoco of hs ee Cah a iaa i ak ae a E E avem ma oem EXE qeu m mem o emm Om aedem de dm dm dee dm Sd el ted d i mS quam mom Ie a KES PPAR COTES eae omg ed Sd orenean cn en BR on an Pees cn cn cn om an Le ee ey ESSEN Oem en m an OS E FER Ri mmr sd Ba E eters wonton data and sheer thon T a Fig 3 25 Channels Setup See details in Section 4 2 Click the Add Bus Signal button to add a channel This will appear as New0 Click the Bus or channel you want to delete and press the Delete Bus Signal button Press the Delete All button to delete all the Buses and channels Press Restore Defaults to return all channels and Buses to the system defaults Select this function when adding and deleting channels the software reserves the original waveform not select this function the waveforms in channel are cleaned up Signals can be grouped into Buses by pressing Ctrl G Signals can be added deleted copied and grouped into Bus using the mouse or the keyboard or right click and select the desired operations from the pull down menu The movement of a signal channel are Auto Size not available in waveform
187. ogic 1 the waveform is as An unknown signal waveform is displayed in gray between the high and low levels as There are sixteen channels in LAP 16032U LAP 16064U LAP 16128U LAP C 16032 LAP C 16064 LAP C 16128 and LAP C 162000 and thirty two channels in LAP 32128U A LAP 321000U A LAP 322000U A LAP C 32128 LAP C 321000 and LAP C 322000 Listing Display This interface shows the digital signals as 1 and 0 Logic 1 is displayed as 1 and logic O is displayed as 0 Status Area Display Logic Analyzer status The function name is also indicated here FMO7IAA 2P BETIS HE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 3 1 Menu amp Tool Bars Section 3 1 presents detailed information on the eight menu and thirteen tool items shown in the menu bar The eight menu items are File Bus Signal Trigger Run Stop Data Tools Window and Help The thirteen tool items are Standard Trigger Run Stop Sampling Trigger Content Set Display Mode Windows Mouse Pattern Zoom Data Show Time Height Trigger Delay and Font Size 1 File New Ctrl h ta Open Chrl o Close Close the file being worked on Close Ctrl F4 Save CEr 5 Save As Auto Save Save the required file automatically See ML Section 3 5 for detailed instructions Export Waveform Export files into Text txt and CSV fan Export Waveform Ctrl Shifk E Files csv 5 Export Packet List
188. ogic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 ISO Settings Oscilloscope Brand Tektronix Online Made TCPJIP Stack Parameters Current Online Model E Sampling Frequency Hz stacking Delay E Trigger Position Trigger channel Trigger Type Activate C Trigger Edge C video C Pulse STEP 10 It will display the currently connected DSO Model after pressing the Online button Oscilloscope Brand rektronis Online Mode USB C TCPJIP m fo ack Faramece Current Online Model tes 10026 56 Sampling Frequency jioooo0 00 Hz stacking Delay mM Ps Trigger Position o fo Trigger Channel External 7 1 00 v Trigger Type Activate Trigger Edge Rising Edge video All Lines x Pulse ioo 193 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 STEP 11 Set the relevant parameter and press the OK button DSO Settings X Tektronix Oscilloscope Brand Online Mode USB C TCP IP C AUTO IP n Stack Parameters Current Online Model THs 10026 52 v Sampling Frequency 1 00000 00 Hz vw Stacking Delay ln Ps v Trigger Position so E v Trigger Channel External 1 00 E m Trigger Type Trigger Edge Rising Ed
189. on Parameter Condition Parameter X Conditional Full Period 400ns lt Time lt Conditional Positive Period g ns lt Jime lt Conditional Negative Period 700ns z Time c Fig 3 135 Condition Parameter Allow the setting of time intervals for Conditional Full Period Conditional Positive Period and Conditional Negative Period Channel Selection Column Selection Condition Parameter Warning Parameter Refresh J Statistics Filter CHANNEL Full Period Positive Per Negative P Conditional Conditional Conditional StartPos EndPos SelectedData l A0 211 212 211 0 0 0 Ds Dp Al 52 53 52 0 0 Ds Dp A2 0 0 1 0 0 0 Ds Dp A3 0 0 1 0 0 Ds Dp A4 0 0 1 0 0 0 Ds Dp AS 0 0 1 0 0 0 Ds Dp A6 0 0 1 0 0 0 Ds Dp A7 0 0 1 0 0 0 Ds Dp B 0 0 1 0 0 0 Ds Dp B1 0 0 1 0 0 0 Ds Dp Fig 3 136 The Numbers of Data Qualified by Condition Parameter 81 FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Warning Parameter Warning Parameter xj Conditions Min Max Period Iv 10us m 100us Frequency 10k iz 100KHz Fig 3 137 Warning Parameter Set the conditions which will be marked to call users attention Channel Selection Column Selection Condition Parameter Warning Parameter Refresh statistics Filter CHANNEL Full Period Conditional Conditional Con
190. orm Find XI LR LU xi Activate the Function of Chain Data Find Activate the Function of Chain Data Find ver i lame Mext Previous Close Next Previous Close niini ame Min Value Max Value Bus Item Max Value 00000000000 F J z when Found Statistics Start At nd Statistics 0 Fig 3 126 Waveform Find Dialog Box of the SPI Signal E FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Waveform Find JX ENS x Activate the function of Chain Data Find Activate the function of Chain Data Find Bus Signal Name ional Name fs Next Previous Close Next Previous Close Bus Item Find Min Value Max Value Bus Item Find Min Value Max Value CIEE j 00000000000 fF inRange v o0000000000 F s a When Found Statistics en Found Statistics A Statistics SEN Statistics o o Fig 3 127 Waveform Find Dialog Box of the Bus Item of the SPI Signal Step4 Choose the position to start the search by selecting one of the following Start At Ds T A B C etc End At Dp A B C etc Then click Next or Previous to search it When Found Choose a Bar to mark the result A B C etc Step5 Click Statistics to show the number of instances of the search results Note It is available only when searching through a Bus Scale 3 04128ns Display Pos 10 15us Pos 10
191. orm area is the middle packet segment which is displayed by waveform Activate Packet and Waveform Synch select Top and Left Synch Parameter Setting X v Activate Packet and Waveform Synch Synch Point of Packet List Synch Point of Waveform Area C Middle Fig 4 52 Synch Parameter Setting Dialog Box 118 FM0714A 2P BE HS BR 03 ER 23 8j The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Display the corresponding waveform and packet as below image P ZEROPLUS LAP C 32128 Standard 3 11 CNO1 5 N 000000 0000 12C a File Bus Signal Trigger Run Stop Data Tools Window Help Dc E S Bo oe ee IDB gt p gt me fx Be Te ho Bb le s A Pos 52 0884ms x A T 19 198Hz na A B 166 667 KHz v B P0s 52 0824ms v B T 19 2Hz M Compr Rate 191 903 Scale 689 552KHz Total 78 6034ms Display Pos 32 654543us Display Range 3 600865us MILI LLL LLL LILI LI n VW Busi I2C esc 50 SDA P A2 22 A3 A3 P A4 n4 g 45 55 A6 d 47 g 50 B Bi B2 5 B3 P B4 w 55 B6 B m n ra o Setting Refresh Export Packet Name TimeStamp Bus1 2C Synch Parameter ADDRESS Write A ACK DATA aa DATA a DATA a DATA a DATA LB ACK Packet Name TimeStamp ADDRESS write A ACK DATA DACKE DATA DCK Busi 2C 10 2064ms SO Write A ACK OO D ACK D ACK
192. os 120 68us v B T 8 266KHz M Compr Rate Ho Bus Signal Trigger Filter E 2s 054313us14 2947 92us 3 335 lus T 22425us 17 Qe3rTus 28 T43231us 33 50281 2us 50 262333us 61 021853us n Testum E ae eT ET x e Coote T p FiTTITTTT P 2 22 L CRT ee oe A3 A P 4 n4 Unknown L4 TEN pou m BES Bo 50 Bi bi B2 B2 NEU Fig 4 14 Trigger Position 10 We ZEROPLUS LAP C 32128 Standard 3 11 CHO1 S H 00000000001 LaDoci b File Bus Signal Trigger Run Stop Data Tools Window Help 8 x ja 2 S wy Us gt IB bb e 128K site i 100MHz an Fox s 3 Page fi Count E gigi gi ev iid E 2 151904u E amp zz f Ax Be Te P le um Height 30 v Trigger Delay 10ns Ani xl Scale 464 TOSKHz Display Pos Ons A Pos 907 41us v A T 1 102KHz IY A B 3 333MHz v Total 1 310T2ms Display Range 53 T9TBO4us B Pos 907 11us v B T 1 102KHz v Compr Rate No Bus Signal Trigger Filter ME uc 038083us 32 2r8562us 21 513041u7 10 F59521us g 10 759521us 2a 513041us 32 278562us 43 038083us 53 em zs moet TTL UU UL a2 22 St 1 A3 A3 5d Ad Ad a5 55 SE 6 A 5d P 7 7 5d g 80 50 5 g Bi Bi BZ B2 B Fig 4 15 Trigger Position 70 Step6 Trigger Range Setup Click if icon or click Trigger Property from the Trigger on the Menu Bar Then Click the Tr
193. oscillator from the tested board to the signal connector of the Logic Analyzer to measure it by using the internal clock of the Logic Analyzer 96 FMO7IAA BB tt Ae 2 f3 ER 2S 8l Zeroplus Technology Co Ltd Sampling Setup m Clock Source Asynchronous Clock Internal Clock Frequency Atlas SOOHz m Synchronous Cloc 1KHz 25KHz Rising E ISO ney 100KHz Min 0 001Hz Max 100MHz evel is the same as the port A trigger level Sampling MRAM Size ession Mode RAM Size gt ee Medan a Compression Channel number limited to 32 Signal Filter Signal Filter Setup The Zeroplus Logic Analyzer User s Manual V3 11 M IDE 50 4 B I 100Hz H 105 7505 A T 13 333h ns 75ns B T213 333k I I alr 3 I I I aang LI L Ll Fig 4 2 Clock Source Pull down Menu External Clock Synchronous Clock Click on External Clock and then select Rising Edge or Falling Edge as the trigger condition of the DUT In the Frequency column type the frequency of the oscillator on the DUT Tip The External Clock is applied when the frequency of the oscillator on the tested board is exceeds the range of the internal clock of the Logic Analyzer Connect the output pin of the oscillator on the tested board to the CLK pin of the Logic Analyzer Step 3 RAM Size Setup Click the RA
194. play Bar of Signal Filter are not available under the compression mode B The Filter Delay and Display Bar of Signal Filter are not available under the double mode C The final two data are NULL D Logic Analyzer supports the Signal Filter Time Interval function on condition that the time interval between signal filter must be more than two clocks 173 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 8 Noise Filter The Noise Filter function enables the system to filter the waveform that doesn t meet users requirements 4 8 1 Basic Software Setup of Noise Filter STEP1 Click Data on the Menu Bar then select Noise Filter to activate the noise filter function as the figure below Data Tools Window Help Select an Analytic Range M d 8 Noise Filter x Noise Filter Fee Bus Width Filter Noise Filter Data Contrast E None z B Find Data value Ctrl F FA Find Pulse width Cancel Fig4 148 Noise Filter STEP 2 Transmit the tested signal to the Logic Analyzer as the figure below Bus Signal Trigger Filter a0 40 wal l 42 42 as A3 Fig4 149 Tested Signal STEP 3 Filter waveforms that are not bigger than 5 clocks Noise Filter E xl Noise Filter None Noise Filter Noise Filter Fig4 150 The condition of Noise Filter is 5clock 174 FMO7IAA 2P BETIS HE 2 ARAS T
195. puter after installing it The shortcut is removing the software interface and then reinstalling it By default the program is available for all users My HDD is modest which software components are absolutely necessary Choose Custom as your setup type Next unselect items such as examples and tutorials You must install at least the Main App application My MS Windows system will not accept the driver what should I do Double check that you run the correct Setup exe from the folder that corresponds to your hardware and MS Windows version Visit our website for the latest updated or debugged software If you are running this program on a virtual machine the virtual machine may not support the amount of hardware addressing In this case try it with a machine that is physically running a Windows system FMO7IAA Q1 Q2 Q3 QA 197 PRE HE DARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 5 2 Software Troubleshooting Can I run the program even if don t have the Logic Analyzer hardware Yes you can You can run the program under the demo mode See Fig5 1 T gt ZEROPLUS Logic Analyzer xj Hardware Searching Failed y C Fig 5 1 Select Run Demo if you do not have the actual hardware I am running a graphing program and software at the same time Whenever try to make a screenshot of my work it keeps telling me that I have insufficient memory space what is wrong
196. quency Display Time Display Huler Made Waveform Setting C Regular Ruler Waveform Height 22 Time Sampling Site Ruler Font Size 12 Fig 3 145 Waveform Height Waveform Height 18 Waveform Height 40 Rut Signal grim tn m tee E BEEN ET uiSignal ne Re wal Lis 4 war g ig wo Fig 3 146 1 Fig 3 146 2 Fig 3 146 Examples of Waveform Height FMO7IAA O SPREE HSA Aa PRA Sd Zeroplus Technology Co Ltd Correlated Setting Select Auto Close in the following figure W Auto Close Show Gridline fi Show Tooltip v When the roller i moved toward back the Time Asis in the waveform area will move toward right Data Process The Zeroplus Logic Analyzer User s Manual V3 11 Open Close Compression Warning Iw Show the T Bar in the middle area i Open Close Double Warning What do vou want to show when you press the Stop during the running Keepthe Present Data Read the Captured Data Restore Defaults Check for Update Bus 5 g a0 g Ai g az a A3 ad 5 was g A6 w a7 60 g Bi 40 g Ai P a y A3 g 44 45 g 6 ar g Bo g B Cancel Help Fig 3 147 Correlated Setting ignal al AL Ai Ae Trigger Fig 3 148 An Example for Auto Close Auto Close With the cursor in the channel when users try to drag a Bar the Bar will stop at the approaching edge of the channel Rising Edge or Falling E
197. r My Computer ic a My Network Places File name j Save as type Logic Analyzer LAP C File alc h File Note Project LaProject Author SUNSHINE Tle easelemma Note Fig 3 6 Save As Dialog Box Save Save the current file Save As Specify the name of the file to be saved Auto Save Save the required file automatically FMO7IAA 2P BETIS HR 0 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 A4 xl Save in B11004 LAP BDM Jj ce Fe B11004 LAP BDM M CHM SI v1 00 20110520 J E BDM Module Introduction My Recent Documents Desktop 9 My Documents Pr My Computer Ka 3 wmm Filename um v Places Save as type Text Files t t Y Cancel Bus Output Parameter q Data Information Bus Item f Yes C No Data Style a m Perform Model Data Model All Data ise nz Export Waveform Ctrl Shift E sd Data Format i m C iBortzontal Hexadecimal r Output Range From a Bar To user Defined 150us 10 25ms V Pop up an export file automatically Fig 3 7 Export Waveform Dialog Box Export Waveform Export a file into text txt or CSV csv formats Bus Output Parameter Decide whether or not to display the parameters of the file to be exported Perform Model Choose whether to export the data either vertical or horizontal Data Style In
198. r to change the color Highlight a signal or Bus and click Rename to rename the Bus or signal FMO7IAA 3 P RE PIR ER 40 BPR 8l The Zeroplus Logic Analyzer J Zeroplus Technology Co Ltd User s Manual V3 11 Bus Trigger mo mJ m ae TAS Fig 3 30 Trigger Tool Box 38 FMO7IAA 2P BET AR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Menu Bar Trigger Menu Item Detail Menu amp Dialog Box Bus Trigger x Bus Trigger Protocol Analyzer Trigger Bus Marne Operator Bust E Data Format E Bus Trigger Setup Binary C Decimal C Decimal Signed Hexadecimal 6 ASCII C Gray Code C Complement Cancel Default Help Fig 3 31 Set Bus Trigger See Section 4 1 for detailed instructions Channel Trigger Setup x B 5 4 3 2 1 0 Fiter Condition X X X X X X X R ort Trigger Condition gt lt Pat Juuw y Channel Trigger Setup a Enercon X A A X EN EN EN N id Trigger Condition lt eS eS eS eS eS eS eS Filter Condition X X X X X X R R ortC Trigger Condition gt lt DX Y x DX D DG po FiterCondton X X X X X X R R ontD EE Trigger Condition 26 2c 2c os os ES bs es B Cancel Restore Defaults Help Fig 3 32 The trigger action tells the Logic Analyzer when to send data to the PC The trigger conditions deter
199. rast Result Error Stat gt Contrast Beginning Point 7 Bar Select an Analytic Range d rue t E Noise Filter v Rall the contrast waveforms synchronization Pin Assignment S82 Bus Width Filter 2 v Display Files the contrast differences x Data Contrast v Display Files horizontal Perform Contrast b Find Data value Ctrl F v Do contrast automatically when being run Fol Find Pulse Width Apply Close Help Fig4 153 Data Contrast Interface Activate Data Contrast Click the checkbox to activate the function of Data Contrast Basic File It is the standard contrast file Contrast File It is used to compare with the Basic File Contrast Beginning Point It can set the beginning point of the contrast at Trigger Bar or Beginning of Data Error Tolerance It is the allowable time error when setting data contrast Contrast Result It displays the same contrasted result and the different contrasted result with PASS and FAIL respectively Error Stat It displays the number of discrepant parts Pin Assignment Users can select the contrastive channel Perform Contrast It can activate the Contrast at once Display files horizontal The waveform window of the two contrast files are displayed in horizontal Users can select it as their requirements and the default is non activated Roll the contrast waveforms synchronization The two contrast files roll synchronously Users can sel
200. ration dialog box Pin Assignment SCLK It is the Clock channel and the default is AO DATA It is the Data channel and the default is A2 Protocol Analyzer Property Mode There are six modes for selecting which are CPHA 0 CPOL 0 CPHA 1 CPOL 1 CPHA 1 CPOL 0 CPHA 0 CPOL 1 Rising and Falling Transmission Direction Set the Transmission Direction to MSB gt LSB or LSB gt MSB Data Length Set the Data Length in the range from 1 to 56 and the default is 8 Fill 0 at the LSB when the bit count is not enough For example the value of Data is 1001111 there is only 7 Bits When the value of Data is set to 8 Bits the displayed value should be 10011110 SS Pin Assignment SS Channel Select the channel for the SS the default is A1 SS Setting Set the Judgment Level of the SS Channel to Low or High Virtual SS When the SS Channel is not activated the Virtual SS will be activated The Idling Time of the Virtual SS should be set as an auxiliary condition to decode Type the idling time of the SCLK signal on the tested SPI circuit The idling time is defined as the idling time as shown in Fig 4 86 136 FMO7IAA 137 2P BETIS HE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 begin en HN 8 IIA sce coum SLU HTL eel jdling time idling time yea e ic Ee ea Fig 4 84 Idling Time Protocol Analyzer Color Users can vary the colors of the de
201. rb both the testing and tested devices ensuring a set of data that is still accurate Conclusion Every user of a product is a potential writer for Chapters 5 7 in this User Manual In fact this chapter is a composition of many unnamed electronic professionals especially experts 198 FMO7IAA 199 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 6 FAQ 6 1 6 2 6 3 6 4 6 5 Hardware ooftware Registration Technical Information Others FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Objective In this chapter common problems and questions are roughly classified into five categories Hardware Software Registration Technical Information and Others This is a backup resource for users especially those without Internet access Most references refer to English web links 6 1 Hardware H01 Is it ok to substitute stock items for bundled cables and connectors A Yes users may use any compatible connectors and cables However to ensure consistency and accuracy in measurements and data we strongly recommend using the bundled connectors and cables Each of the Logic Analyzer s is calibrated with the bundled cables and connectors before packing H02 Does Zeroplus manufacture grippers How may purchase grippers A Yes we have a production line dedicated to grippers Contact our sales department and a
202. rcuits is a serial synchronous half duplex communication protocol The I2C was first proposed by Philips Semiconductor Netherlands This I2C protocol consists of a very simple physical interface which has only two signal channels SDA Serial Data and SCL Serial Clock Most I2C devices consist of an independently sealed I2C chip and this I2C chip has direct connection to both SDA and SCL The data transmission is a byte base 8 bit base for every segment Since many oscilloscopes do not allow engineers to observe timing sequence information directly from the screens of oscilloscopes this Logic Analyzer was created to help engineers resolve timing sequence issues during their circuit development I2C has a multi control Bus as its physical and firmware interfaces This protocol analyzer is basically a signal network that may connect to one or several control units The intention of inventing this protocol was in the application of designing television sets which allowed the central processing unit to quicken data communications with peripheral chips and devices The I2C interface is initiated with a SDA triggered High and SCL triggered Falling Edge Following the initiation there will be a set of 7 bits or 10 bits address space Beyond this point there will be Read Write ACK Acknowledgement and STOP or HALT HLT The signal information packet is transmitted in bytes If there are two or more devices trying to access the I2C protocol whichever d
203. rigger Fiter m Doy su ig qu alu ms BE vu 2 30 525us 20 4us iid af 309 055us m LOLLL e A 655 36us c A3 AS o 655 36us d At n i x 655 36us g as 2c sa B 655 36us gas A6 a S2 655 36us BusSgnd T gger Fier mu E es eet I ass I E CELL gaa mp 388 33us d i2 EN 388 33us e A3 AS R 388 33us d 4 As s 388 33us 7 as AS E 388 33us Fig 4 140 Without With Signal Filter Setup The first picture shows the result without any signal filter setup The second picture shows the result which has set the high level on the Filter Condition of the signal A1 Only the waveform with the high status of A1 is displayed Step5 Filter Delay Setup 1 Click on the Activate Filter Delay as shown in Fig 4 141 2 Click on the According to Filter Condition or the Opposite of Filter Condition to select the waveforms to be kept 3 Click on the Start Edge End Edge or Period Delay to set the Start Point of Filter Delay 4 Type the value of the Delay Time into the column of the Delay Time 5 Click OK then click Run to activate the signal from the tested circuit to the Logic Analyzer 6 The result will be displayed in the waveform display area as shown in Fig 4 140 Step6 Stop Signal Filter Filter Delay Click Stop then click Signal Filter Setup and select Cancel from the Signal Filter Setup dialog box to stop the Signal Filter or the Filter Delay Setup Tip Click Stop to check the cond
204. rocal of horizontal scale the range is 1 5ns 1 50s Stacking Delay It is used to align the T Bar and the T Bar of LA when users use the main program to show the oscilloscope s waveform The range is 1000000ps 1000000ps Trigger Position It matches the horizontal spin button of oscilloscope the range is 0 100 Trigger Channel It matches the trigger level spin button of oscilloscope the lever range is 16V 16V Trigger Type The other options is available only after the active option is selected A Trigger Edge Users can select Rising Edge or Falling Edge B Pulse Users can select lt gt the range is 33ns 10s C Video Users can select Line All Lines Odd Field Even Field and All Field Online Click the Online to link with the oscilloscope and the Online button will change into Disconnect button Users can set the oscilloscope by selecting the options and inputting values then pressing OK Note the Stacking Delay is set into the main program If no oscilloscope is connected or the oscilloscope disconnects the whole options under the Stack Parameters are unable For the above details please refer to the 4 13 FMO7IAA Zeroplus Technology Co Ltd User s Manual V3 11 O 2P BETIS AR 2 ARAS The Zeroplus Logic Analyzer 7 Window waveform Display Listing Display Hot Wews Window Real time Monitoring Navigator Memory Analyzer Bus Packet List Statistics Window a
205. rotocol analyzer CAN 2 0B and select OK to confirm Ye ZEROPLUS LAP C 32128 Standard 3 11 CHO1 S H 000000 0000 CAN2 0B _ inl xl Gp File Bus Signal Trigger Run Stop Data Tools Window Help 2181 x De S a sm fizek z se o f200MHz v fe z ie s Page fl con fl l gx Ri e iid X 9 736541u 7 AIE Ax B Tx te B 16 gt l JE i Height 30 Trigger Delay 55s Scale 9 T36541us Display Pos 194 T30814us A Pos 87 851299us v A T 87 851299us v B 16 182424us v Total 167 69579ms Display Range 48 682703us B Pos 104 033724us v B T 104 033724us hd Compr Rate 255 883 Bus Signal Trigger Filter Hi 32 096221u 340 778324u 383 461628u 438 a Bus Property xE peapa n TEES n mem nm ree oY Ff OKO A A AMA AA 8r r Bus Setting U _ OKO HUUU e o a0 C Bus Golor Config g Al Al e Activate the Latch Function Register A2 22 9 A3 A3 r Protocol Analyzer Setting A4 A4 amp Protocol Analyzer Parameters Config PA 9 ZEROPLUS LA 1 WIRE MODULE V1 10 00 CNO01 E ZEROPLUS LA 3 WIRE MODULE V1 04 00 CNO1 g ac ab amp ZEROPLUS LA AC97 MODULE V1 02 00 CNO1 ZEROPLUS LA ARITHMETICAL LOGIC MODULE V1 51 00 CN01 PIE ZEROPLUS LA BDM MODULE V1 00 00 CNO1 ZEROPLUS LA BUS MODULE V1 00 00 CNO1 r BO BO Q ZEROPLUS LA CAN 2 0B MODULE 1 32 00 CN01
206. s Protocol Analyzer Format Break This is the initial bit for the Protocol Analyzer HDQ after Low signal lasting a period of t B it is then converted to a High signal lasting a period of t BR The length of Low signal is no less than 190us whereas the High signal is no less than 40us kea _ tem Fig4 110 Pulse from Low to High Address The Address comprises 7 bits The initial Low signal lasts a period of t HW1 and if the write O status continues through the end of the t HWO period the signal will convert to High and last throughout the period of t CYCH as shown by the dotted line in the following figure Conversely if it is the write 1 status after t HW1 period of time the signal will convert to High and last throughout the period of t CYCH which is of 1 bit and no less than 190 us The t HW1 range is from 0 5us to 17us and no more than 50us The t HWO range is from 86us to 100us and no more than 145us Read Write Read Write is 1 bit O and 1 are displayed in the same way as the above description T RSPS The High signal lasts a period of 190us 320us The following 8 bit data is Send Host to BQ HDQ or Receive from BQ HDQ Data Data Made up by 8 bits and it is Send Host to BQ HDQ or Receive from BQ HDQ Data It operates in the same way as in 2 2 and the data is from LSB to MSB BQ HDQ To Host If the data transmission is read by BQ HDQ To Host the initial Low signal lasts a period of t DW1 and if the
207. s What da you want to show when you press the Stop during the running Keepthe Present Data Read the Captured Data he Check for Update Restore Defaults Fig 3 71 Tools Menu pS ae Height 30 Fig 3 72 Show Time Height Tool Box 55 FM0714A 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Menu Bar Tools Menu Item Detail Menu amp Dialog Box x Common Setup Toolbars Shortcut Key Auto Save Waveform Display Mode a Customize C Sampling Site Display Frequency Display C Time Display Ruler Made C Regular Ruler Waveform Setting Wavetorm Height 22 hl Time Sampling Site Ruler FaontSize je 7 Correlated Setting M Auto Close Open Close Compression arming Show Gridline W Show the T Bar in the middle area Show Tooltip Iw Open Close Double Warning lw When the roller is moved toward back the Time Axis in the waveform area will move toward right Data Process What do you want ta show when vou press the Stop during the running C Kesepthe Present Data F Fiead the Captured Data I Check for Update Restore Defaults Cancel Help Fig 3 73 Customize Dialog box See Section 3 4 for detailed instructions Customize O x Common Setup Toolbars Shortcut Key Auto Save Data Contrast Screen Display Cancel Help Fig 3 74 Toolbars Setting FM0714A 57 Phe PER
208. se Width 0000 Signal Name It can select the single channel for Find Find It can select the Find conditions which are In FMO7IAA zBERHSE ROO BER ZS SI Zeroplus Technology Co Ltd Tip This function is mainly used for finding the pulse width in a single channel and the single channel of a Bus It improves the efficiency of finding the Pulse Width for engineers and strengthens the Find function of the Logic Analyzer l To the Previous Edge F11 d To the Mexk Edge Fi The Zeroplus Logic Analyzer User s Manual V3 11 Range Min Value gt lt and When users select the option of In Range they can input the value of the Min Pulse Width and Max Pulse Width between 1 and 65535 and find the Pulse Width in range When users select the Min Value they can find the Min Pulse Width for the present single channel When users select the options gt lt and they can input the value of the Pulse Width between 1 and 65535 and find the Pulse Width in range Start At Select the Start point of Find The selectable items are all Bars the default is the Ds Bar End At Select the End point of Find The selectable items are all Bars the default is the Dp Bar When Found Select a Bar to mark the found Pulse Width The selectable items are all Bars the default is A Bar Statistics It can count the number of Pulse Width in the present range Next It can find the next Puls
209. shooting 195 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Objective In this chapter troubleshooting is divided into installation software and hardware issues These troubleshooting questions and answers depend not only on our engineers but also on end users such as students engineers technical manual writers and others Q1 Q2 Q3 Q4 Q5 196 5 1 Installation Troubleshooting Why it is not prompt when insert the driver CD into my CD ROM At this stage the driver CD is not auto executable The primary issue here is a chipset problem Though these six Logic Analyzer models seem only different in model number they are quite different in firmware and chipsets Due to installation procedures see Chapter 2 we are unable to compile a driver program that auto detects the chipset at the beginning of the installation Why does the installation software keep giving an error message saying that don t have enough memory This kind of problem happens in many hardware installations Turn off multimedia programs such as Media Player media decoders media encoders and so on If there are any multimedia icons in the system tray see the far right end of the START menu taskbar remove them The Logic Analyzer software will run better in memory locations from 64 to 512 MB What should do if want to share this software interface with all users of my com
210. site of any further operation as presented in the User Manual 16 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 2 Installation 2 1 Software Installation 2 2 Hardware Installation 2 3 Tips and Advice 17 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Objective This chapter describes the installation of the Logic Analyzer hardware and software Software installation steps must be followed precisely to ensure successful installation 2 1 Software Installation In this section users will learn how to install the software interface and drivers As with proper installation of many USB devices the Logic Analyzer application and driver software must be installed prior to the connection of the hardware The following steps illustrate an installation of a Zeroplus LAP C V3 11 Logic Analyzer The other twelve models mentioned in Chapter 1 would follow identical procedures Step 1 Insert the driver CD ROM in the PC CD drive Step 2 Execute the installation program Go to the START menu click START Run Browse in sequence select Setup exe file in the appropriate model folder and then click OK It is recommended that all other programs are closed while the installation proceeds Step 3 Choose the Application Setup Step 4 Click Next to proceed with the Install Wizard Step 5 Select I accept the terms of
211. t Data Mode The Zeroplus Logic Analyzer User s Manual V3 11 tl Y 200MHz Bo Te Bar Bar Bar 08 178 Ctrl F Fil Fle k Alt A Alt B TRU HU UU UT PULL LI pagpa ESCAPE F3 Fa Emu h Ctrl 2 d v Square Waveform Sawtooth WawveForm B Te t Fale i Bar Bar Bar Ctrl F Fil Fl Alt A Alt B E H ESCAPE FQ Fa F10 Ctrl z Square Waveform piv Sawtooth Waveform Fig 3 69 Sawtooth Waveform FMO7IAA 2P BETIS HR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 List Data Made gt Tip Select an Analytic Range M 1 Il200MHz wu 502 gt Noise Filter BT no B fg The data for list mode are so Bus Width Filter n el 09 178 v A T Data Contrast E ele many to be convenient for users that B Find Data value Ctrl F EX Find Pulse Width there is adding a List Data Mode Te TO TRE reo Ee EM gt To the Next Edge Fiz function The formats for the List Data Go To te Add Bar Alt 4 Mode are All Data Sampling Changed _ Delete Bar AUR mINBIDIENEENBSEDEERBEENBNTI Zoom E Dot Compression and Data Changed B i i EN INN RN RN RN RN RN GR M an en E n pep Tents mx pm g Norma ESCAPE Dot Compression R a ee ERE TR ER ER E 1 All Dat It is th t displ ceo A ie EM EmA ESTER EE ER ET ES ET ER TRU ata
212. ted the background color is white Waveform Change the color of the Buses or signals on the waveform area Color Setting 1 x Workaround Waveform Mame Relating Color Linewidth BE mimm T F T r F F F r r T r T r F r Cancel Default Help Fig 3 155 Waveform Color Interface Waveform The channel color can be varied by users Linewidth The linewidth can be adjusted by the users requirements there are three options which are 1pixel 2 pixel and 3 pixel 91 FMO7IAA 2P BETIS HE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 3 6 1 Modify Workaround Color To modify the workaround color click the color block shown in Fig 3 154 A Color panel shown in Fig 3 156 will appear Select a color shown on the panel or click on Define Custom Colors to create the desired color Color Basic colors EI Cel eee BI Ce mmm EI Hm NN E ioe Ef RI E EH NN NN D DI EENENINMNI Custom colors LB UN UN NN Hue feo Red o Bee eee mE Sat 0 Greer 0 Defne Custom Colors gt Color alid Lum E Blue lo OF Cancel Add to Custom Colors Fig 3 156 Color Panel with Its Advanced View 92 FMO7IAA O 2P BETIS HE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 3 6 2 Modify Waveform Color Foreground color refers to the color of the output signal lines in the Waveform Display
213. ter recognizing bit stuffing wrong the Error Frame called Error Corresponding Error Flag Field includes sequence bits from 6 to 12 which produces by 1 or more nodes Error Frame ends in Error Delimiter field After Error Flag sends out Bus actively to get the right state and the interrupted node tries its best to send abeyant message Error Delimiter Error Delimiter consists of eight recessive bits and allows Bus node to restart Bus transmission after Error happens Fig4 125 Error Frame Overload Frame There are two kinds of Overload conditions which both lead to the transmission of an Overload Flag The internal conditions of a node which require a delay of the next Data Frame start during the first bit of Intermission Overload Flag can send six 0 which may damage Intermission format so that it makes the other nodes know node sending Overload Flag at this time When Overload Flag is sent out Overload Delimiter can send eight 1 others send seven 1 after finishing either Fig4 126 Overload Frame Interframe Space Interframe Space is divided into Intermission and Bus Idle Intermission is three 1 It is impossible to send any message during this time except Overload Frame The Bus is recognized to be free the period of BUS IDLE may be of arbitrary length And any station having something to transmit can access the Bus When a node is at the state of error passive the node will send eight 0 after INTERMISSION a
214. the packet in every protocol analyzer Value The value needs to be entered in the frame and the data mode can be selected by users according to their requirements the default is Hexadecimal When a value can be input in the selected protocol analyzer data the frame can be enabled Or the frame will be disabled For example Protocol Analyzer I2C when the protocol packet is DATA the frame can be used to the contrary when the protocol packet is START the frame is disabled Data Format The displayed value mode can be selected There are five options Binary Decimal Decimal signed Hexadecimal ASCII Gray Code and Complement 105 Step3 Trigger Mark Setup To find the item in the Bus better users can activate the Trigger Mark function after starting Bus Trigger the trigger mark is shown with T bar According to the number of the trigger position the T bar is displayed in order TO T1 T2 T3 T4 and the color is red as the image below 1 Bus The trigger condition is 0 the red T bar displays the trigger condition in order Bus Signal Trigger Filter 1 833 B esr 88 i 5687 F Qo 16667 13167 Fis cer B v Bus1 Hj now b ot oxo d 0X4 0X5 J0X4 0X0 loxifoxo oxa Yoxp oxc 0X4 0X0 eao l A1 l z eA2 J Hl __ _ w A3 Aj Fig 4 20 Bus Trigger Mark 2 Protocol Analyzer I2C The trigger condition is Data 0 the
215. there is a packet list it gets twice the result with half the effort to check the data Packet List has its startup button in Toolbar After starting it it will show a small window under the waveform window Users can alter its size to find more data Notice If you want to learn more about the Bus Packet List please refer to the Specification of the Protocol Analyzer ZEROPLUS LAP C 32128 Standard 3 11 CNO1 S N 000000 0000 LaDoc1 2 f d a File Bus Signal Trigger Run Stop Data Tools Window Help 81 x D E NR m gy BY 48 ey P TE gt DD e 2k en D 100Hz mw 50 3 Page fi gt Count fi v UR oe Aw Be Te ie Mi ie d Bar Bar Bar Bar E5 o gt Height TriggerDelay 10ms Display Pos ns APos 150ms v A T B 6B7Hz 7 A B 3 333Hz v Display Range 250ms 270ms BPos i50m v B T 6 667Hz v Compr Rate No 200ms 5Ums 00ms 5 0ms Uns ms 100ms fSUms 200ms AAAA AAAA AAAA AAA AAA AAA AA AAA AULA LA ALLA US gogege Pe Lae LET Bigegagigagaghgagigh gaging gamm ne T L3 13 LI LI Ll Ll Lk 1 1 an Fig 4 38 Packet Icon E ZEROPLUS LAP C 32128 Standard 3 11 CNO1 5 N 000000 0000 LaDoc1 o File Bus Signal Trigger Run Stop Data Tools Window Help e x Deh S ux SS PE bb m 2k Jes 141 oore 1 d ifs ie Page fi Count fi Em Ir n Riu B 10ms at kee Oe Be le ie e 3 y Hei
216. tion Pre Trigger Y Trigger Count 1765535 Threshold Working 6V 46V Voltage 11 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 T LED Operating Interface Chinese Si Chinese Tr English Language Time Base 5ps 10M Sizing Bus Pod M Pod mo Mave Nile Waveform Width Yes y Trigger Page ds 1 8192Page erem Function ear Mode LT Data Multi stacked Logic Analyzer Settings Protocol Trigger Safety Certification FCC CE WEEE RoHS Table 1 6B Hardware Specifications of LAP C Series LAP C LA C apcl LApc LAP C LAP C LAP C HeMeNt Rr o 16064 16128 162000 32128 321000 322000 USB 2 0 u System Windows 2000 Windows XP Windows Vista Windows 7 Power Supply USB 1 1 USB 2 0 Recommended Sampling Internal Clock Rate 100Hz 100MHz 100Hz 200MHz Rate asynchronous 12 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Max EM Max 75MHz Max 100MHz Clock 5 ERE Bandwidth TM Memory 512K Bits 1M Bits 4M Bits 64M Bits 4M Bits 32M Bits 64M Bits Bits Memory Memory Depth Per 32K Bits 64K Bits 128K Bits 2M Bits 128K Bits 1M Bits 2M Bits Channel Trigger 16 Channels 32 Channels Channel Trigger Pattern Edge Condition Trigger Pre Trigger Post pg Trigger Level Level a a Trigger Count 1 655
217. tion will be accurate 33 FMO7IAA Phe AIR Be 2 ARAE Zeroplus Technology Co Ltd Sampling Setup Clock Source Asynchronous Clock Internal Clack Frequency S00H Synchronous Clor onis f Rising Edi C Falling Ed Sampling RAM Size RAM Size 16K Synchronous Clock of LAP A C UV f ry VETTE EET j j At V A TANNA ANNALAN iy f Tip T Compression 34 The Zeroplus Logic Analyzer User s Manual V3 11 Choose the frequency of the clock on the board of the Logic Analyzer Select External Clock to acquire data through external sampling Choose either Rising Edge or Falling Edge to execute the analysis process According to the users input the value of external frequency in software the software can count the relevant value about signal mode and frequency For example the value of the message the time scale and the zoom in and out will be the value of time mode Connecting the Synchronous Clock Use one of the single connecting cables to put one end on the testing board and the other in the LA as shown in the diagram opposite Check the box to compress all the data Compression is used to compress acquired data through a lossless compressor The purpose of this compression is to place more data in a limited memory than in an actual memory The compression rate of the Logic Analyzer can be up to 255 times This means that the maximum acquisition can be 32M
218. tomer Individual or Registered Company Whereas ZEROPLUS owns a software product including computer LAP C Standard InstallShield Wizard Customer Information Please enter your information Installshield 19 LAP C Standard InstallShield Wizard Setup Type Select the setup type to install installshield FMO7IAA 7P BE TFS AR 00 BBR ul The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 2 2 Hardware Installation Hardware installation simply involves in connecting the Logic Analyzer to your computer with the included USB Cable as shown in Figures 2 4 and 2 5 1 Plug the fixed end of the cables into the LA Fig 2 1 2 Plug the loose ends into the connectors on the circuit board to be analyzed Fig 2 2 Note The following sequence must be observed when connecting the connectors into the circuit board AO 4 Brown A1 Red A2 Orange A3 Yellow A4 Green A5 Blue A6 Purple and A7 Gray Fig 2 2 3 The circuit board must be grounded to the Logic Analyzer with the black Ground Cable Fig 2 3 4 Plug the square end of the USB cable into the Logic Analyzer Fig 2 4 5 Plug the thin end into the computer Fig 2 5 Fig 2 5 20 FMO7IAA 2P BE HS BR 0 3 ER 23 S The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 At this point the computer should be able to detect the Logic Analyzer and fin
219. unning Text Ads Interface FMO7IAA P BE AIR AR 2 ARAE Zeroplus Technology Co Ltd Real time Monitoring m Navigator Tip The Navigator Window is displayed under the waveform display area when activating the 66 The Zeroplus Logic Analyzer User s Manual V3 11 Real time Monitoring The Level and the Frequency of all the channels can be monitored according to the Real time Monitoring function of software which is convenient for users to know the current data status of each channel There are two display mode see as below Logic Hode Display x Port 4 Ay Low Level High Level Logic Mode Display x Port 4 Port B Port C Port D AQ 3 431KHz B 5 36KHz co 5 37 1KHz D0 5 968KHz Al 4 356KHz B1 20 64KHz Ci 5 097MHz D1 23 28KHz A2 18 153KHz B2 352Hz CZ 23 82KHz D2 17 031KHz A3 19 155KHz B3 2 764KHz C3 30 408KHz D3 25 641KHz A4 22 043KHz B4 14 88KHz C4 13 411KHz D4 11 597KHz 45 19 165KHz BS 5 497KHz cs 2 867KHz D5 29 7KHz A6 2 307MHz B6 3 253KHz C6 578KHz D6 17 121KHz A 25 852MHz B7 5 023KHz C 5 158KHz D7 15 689KHz Fig 3 91 Navigator Window FM0714A Frequency Mode Display P BE IZA 3 ER 23 8 Zeroplus Technology Co Ltd Logic Analyzer The Navigator displays the waveform length of all the captured data it only can display the waveform of the data of four channels In the
220. us Analysis function enables the system to analyze the Bus Basic Software Setup for the Bus STEP 1 Click Bus Property the following dialog box will appear Bus Property xj Bus Setting Activate the Latch Function A Rising Edge Protocol Analyzer Setting Protocol Analyzer Parameters Canfig ZEROPLUS LA 1 WIRE MODULE v1 10 000 MOT ZEROPLUS LA 3 WIRE MODULE V1 04 00r CMO1 7 ZEROPLUS L Aco MODULE v1 02 006 CNOT ZEROPLUS L ARITHMETICAL LOGIC MODULE v1 51 006CNO1 ZEROPLUS L BUS MODULE 1 00 000CNO1 4 ZEROPLUS L CAN 2 05 MODULE 1 32 000CM014 ZEROPLUS L CCIR656 MODULE v1 31 000 C NOT ZEROPLUS L Compact Flash 4 1 MODULE v1 01 DUC NOT ZEROPLUS L CMOS IMAGE MODULE v1 00 O00 NOT gt SIC nod A AALT Te bee ee RAAMI N A d ad omen vw Use the spp More Protocol Analyzer Fig4 57 Bus Setting STEP 2 Click Color Configuration to set Bus Data Color Bus Property E x Bus Setting Bus Activate the Latch Function rising Edge Protocol Analyzer Setting Protocol Analyzer Parameters Coni C ZEROPLUS L 1 WIRE MODULE 1 10 00 CN01 ZEROPLUS L 3 WIRE MODULE 1 04 000CNO1 ZEROPLUS L ACS MODULE 1 02 000CNO1 C ZEROPLUS L ARITHMETICAL LOGIC MODULE v1 51 0000 M01 ZEROPLUS LA BUS MODULE v1 00 0007 NOT ZEROPLUS L CAN 2 06 MODULE v1 32 006C NOT C ZEROPLUS L
221. usly when the NACK appears Add the Read Write Bit for Slave Address When the option is selected the decoding will be displayed by way of the added Read Write Bit for Slave Address Protocol Analyzer Color Users can vary the colors of the decoded packet Step7 Press OK to exit the dialog box of Protocol Analyzer I2C Steps Click Run to acquire I2C signal from the tested I2C circuit Refer to Fig 4 68 Tip Click icon to view all data and then select the waveform analysis tools to analyze the waveforms V ZERO US LAP CPS 128 SEandard V3 1 100901 58 060 Gon EAC amp l xj m Bie Bapa Trigger Punia Deka Too Window pep 18 x D B ee S oe gg m b bb NE m EMH uL om pase de 45 Pags fi Ceun i E og E rs tomre R Be Be Te LEAL EIE r2 Trigg y _200ns Sealed 378MHr Display Pns 17 40758BuE APOE UERAms T A Tz1RTWEHz T A HpzT6B5B5KHr T Totat 0 60 4a Display Ftange 725 10BTEBng 6 Posed 08s B Tei1523Hz Comgr Ralg 131 333 m 45 Ao 05 5 10 15 m s SJ ri fi li i FL FL FL LL eiu j l j l Fig 4 68 Waveform Analysis FMO7IAA 2P BETIS RR 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 4 5 2 2 Protocol Analyzer I2C Timing Analysis protocor anaivzer ec OOO x Configuration Timing Facket Data Format Register Waveform Image E C RE c 3i j tsu par i Usu sTto gt ie gt of
222. utomatically changed to ns When zooming out it will be changed to ms s or ks 2 Pull down Menu There are thirty scales The maximum zoom in and out is the cycle of each grid 0 0001piece The minimum zoom in and out is the cycle of each grid 1 000 000 000 Zoom in and out the proportion with each grid being the cycle the zoom in and out 96 is 100 The time of Zoom In and Out counts by the clock of each grid sample frequency For example 1 Each grid is being a cycle the zoom in and out is 100 The time of Zoom In and Out wil be presented by the clock of each grid X 1 sample frequency 2 Each grid stands for the clock of 100 pieces the zoom in and out is 1 and the time of Zoom In and Out will be displayed by the cycle of each grid X 1 sample frequency 10 Display Pos 0 Display Range 250 200 150 RR TOUT AMnnninnnnnr Display Pos 0 Display Range 25 25 uale E OUUU L d fl SRN ERN Fig 3 64 Result from Normal to Zoom In d ise T isplay Fos 1000 isplay Range 1023 102 AA Fig 3 65 Result from Normal to Zoom Out FM0714A 52 O SPE A HSA A SER A Sl Zeroplus Technology Co Ltd Shaw all Data x Previous zoom Data Format Fill The Zeroplus Logic Analyzer User s Manual V3 11 ARDAS LAP CUOSTT79 9 amdeed V3 1 DIL 8 nt uu ue fupe Des Deb wee oe Ot GS BAN FH Bows ix Anz alix jan je v ree a coe
223. vice site or our headquarters The in store warranty may vary and many require extra charges for various extended warranty policies The company is not being responsible for an in store warranty that exceeds our factory warranty Why should I register this product If you do not register this product the warranty will be counted from the manufacturing date indicated by the serial number of your product Thus we strongly recommend registering your product for your own benefit What should I do if the hardware serial number is previously registered In this case take a picture of the decal on the rear side of the product and fill in the registration form Call us and mail both picture and registration to us A customer representative will be happy to assist you How do register the protocol analyzer and buy protocols Every product is assigned and engraved with a unique serial number please print your S N number window as an example attachment and send it to our distributor or ZEROPLUS head office According to your S N we will provide passwords for your protocol registration FMO7IAA TIO1 TIO2 TIO3 TIOA TIO5 TI06 TIO7 TIOS TIO9 TI10 TI11 207 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 6 4 Technical Information What is the Logic Analyzer The Logic Analyzer is a tool that sieves out and shows the digital signal from test equipment
224. vide the packet format in the Protocol Analyzer and display the Address and Data in an independent list It is better for understanding the relative relationship and status of the Address and Data in the operating process of the Protocol Analyzer Users will know the operation when they use this function It improves the efficiency of knowing the conditions 4 11 1 Basic Software Setup of Memory Analyzer STEP 1 Click Tools on the Menu Bar then select m to activate the Memory Analyzer function Waveform Display Listing Display Hot Mews Window k Real time Monitoring Navigator mm Memory Analyzer 4 Bus Packet List Statistics Window Cascade Horizontal Vertical Screen Display k w 1 LaDoci Fig4 161 Memory Analyzer Interface STEP 2 Open the Memory Analyzer dialog box lt lt lt gt gt gt option Import Export Merge Refresh Reset Display Alteration Ba Bus1 I2C Address write data Read data ross ee R 1 L L 8 T 3 TL T 9 L L 7 3 Unused 0X00 0X4F ox50 0x00 oxcn NXFF Lo o o Lo o LL LLL LE LLL LY v Compact Mode Unused 0X60 0X7F Complete Mode v 4 b Fig4 162 Memory Analyzer Dialog Box 1 Compact Mode and Complete Mode Click the Right Key in the memory analyzer dialog box there are two modes for selecting which are the Compact Mode and the Complete Mode See the two
225. xternal sampling signal Select Waveform Display from the Window list What is an External Trigger An external trigger is a signal outside the Logic Analyzer It is used for the simultaneous test of 2 test tools For example one Logic Analyzer can be started by one signal from another test tool Or when it is triggered it can output one signal to another test tool The Logic Analyzer is often used for triggering an oscilloscope Why does Double Mode not coincide with Filter Delay In order to set out the perfect waveform from the Logic Analyzer and achieve optimal memory efficiency you can use the Signal Filter when using Double Mode the system doesn t support the function of Filter Delay How do update software The software will automatically check for and download updates This function deletes old software first and then downloads and installs the latest version FMO7IAA 2P BETIS RR 2 BPR uj The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 6 5 Others OTO01 How was the Logic Analyzer developed A It took us more than two years to develop this product We envision Everyone carrying the Logic Analyzer and we would like to make some contributions to the electronics industry in return We also wish to transform the stereotypical OEM factory into a world class R amp D center OT02 Why is there a rich information database for game chips rather than the Logic Analyzer A First of all
226. yzer HDQ Signal Frequency Not fixed around 12MHz 13MHz and 19 2MHz Appropriate Sampling Rate 100MHz Same Data Time Per Bit Yes aNo Name of Syn Signals HDQ Data Verification Point Low signals gt 190us converts to High signals gt 40us 3 Protocol Analyzer IO Description me The sole I O transmits Host and BQ HDQ status and data 4 Protocol Analyzer Electrical Specifications Parameter min Type Max Unit Note Protocol Analyzer HDQ Format Description The format changes according to the pulse width so the display must refer to the defined pulse width Protocol Analyzer HDQ is made up of 16 bits signals Firstly after the period of status signals a device will be installed for the 7 bits address through the Host so that 1 bit signals can be read or written After a response time of high signals data will be exported in 8 bits format with the data and location content from LSB to MSB The following is the Host to BQ HDQ analysis 150 FMO7IAA 2P BETIS RE 2 ARAS The Zeroplus Logic Analyzer Zeroplus Technology Co Ltd User s Manual V3 11 Send Host to BO HDQ Send Host to BO HDQ or Receive from BQ HDQ i i CDMR Data gt 4 tRR O LP LE LLL Lo EETECELLETLET Le Lo Lee ue al Address ee Aw LSB MSE Break i Bito Bit7 ET eye ee ET eee 1 er i EFT URN K tRSPS Start bit AddresmBi Stop Bit 77 j p Fig4 109 Host to BQ HDQ Analysi

User`s Manual - Cru Power Oy

Contents

Download Pdf Manuals

Related Search

Related Contents