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VIPower® M0-7 standard high-side drivers hardware design guide

1. A vbat ZD1 Vaar 18v 4I p channe MOSFET Vo o1 R2 1k Vise Vreg GND uC Vpop 100nF Vi ro qn s GND END VND7xxx Vec GND V 15k SEREN GPio RC VER FaultRST T5K GPIO m Vino ino F 15k GPIo NiLuC Vit ina OUTO SUID 22nF V 15k GPio SEnuc Vsen SEn cpio VSELo uc 19k VsELO seto ay GND 15k Gio VsELt wc VsEL1 egi 4 OUT4 gS OUT Vcs uc 15k Ves SCHEME 69 ADC e Multisense e ND L 470pF Rsense GND GND GND GND GND GND GND GAPG1121140941CFT As soon as the battery voltage is applied and for the first start up the body diode of the MOSFET will conduct until the channel is switched on in parallel The Zener diode will clamp the Gate of the MOSFET to its Zener voltage in case of over voltage on the battery track In normal operation only the leakage current of ZD1 Zener Diode is flowing through R2 to GND In order to minimize this current even at higher supply voltages a diode with higher Zener voltage i e 18 V might be chosen however it shall be dimensioned to ensure the Zener voltage is always safely below the maximum rated gate source voltage Ves of the P channel MOSFET The resistor R2 limits the current through the Zener diode at supply voltages higher than the Zener Voltage and limits the charging discharging
2. Multisense Multisense M 15k t 15k t GND 470pF 470pF GND Rsense Rsenst Row y Doo Roo y Dow A r3 uC I O GAPG1128131011MS Ly DoclD028098 Rev 1 153 196 Paralleling of devices UM1922 154 196 Direct connection of SE pins is not safe in following cases e Negative voltage surge either on Vpgar or Vgaro e Positive voltage surge either on Vgat or Vpgaro while Device GND pin disconnected Dgwp not used resistor protection only Positive pulse energy higher than HSD or Dawp capability all paralleled devices could be damaged A negative voltage surge ISO7637 2 pulse 1 3a either on Vgat or Vgaro could cause unlimited current flow between both supply lines via the SE pins of connected devices This current could lead to malfunction or even failure of one or both of the HSDs The mechanism current path is shown graphically on example on Figure 123 The negative transient i e 100 V on Vpgar4 device U1 is transferred to the GND pin via the Vcc GND clamp 70 7 V voltage drop 99 3 V and consequently to the SE pin via the SE GND clamp 6 3 V voltage drop 93 V Since the SE pin of second device U2 is pulled negative a parasitic NPN bipolar structure on SE pin is activated emitter pulled negative versus base and pulls the SE pin high towards the Vcc pin Vgato Since this parasitic NPN structure doesn t allow
3. UM1922 MultiSense analogue current sense 7 MultiSense analogue current sense 7 1 Introduction For diagnostic of MO 7 devices an analog monitoring output called MultiSense is used It is multiplexing several analogue signals controlled by SELx and SE pins Depending on the device family these types of signals are provided e Current monitor current mirror of channel output current e Vcc voltage scaled monitor of Vcc e Case temperature scaled chip temperature On top of these signals it is possible to apply high Z state on MultiSense pin output when SE is set to low Figure 88 MO 7 driver with analogue current sense block diagram x FaultRST m Y SEL r SELo SEn Reror cese IET aenn o o _ es To uc ADC m Opemioadmorr K factor VsenseH GND 54 GAPG1127131801MS ky DoclD028098 Rev 1 117 196 MultiSense analogue current sense UM1922 7 2 Principle of MultiSense signal generation Figure 89 Structure of MultiSense signal generation Vec Ps bd hd Sense MOS Main MOS j gt Ke 1 e H Current sense x OUT y y y Vbat Monitor Dp Temperature monitor il Multisense Switch Block Fault J e MULTISENSE To uC ADC m 9 Rerot Rsense GAPG1127131802MS In General the MultiSense output signal operates for Voc lt 24 V Current moni
4. VSENSE 4 DoclD028098 Rev 1 177 196 Inverse output current behavior UM1922 9 2 2 178 196 Device driven in PWM Effects of linverse are evaluated for devices driven in PWM as well Based on channels dynamic status four major cases can be identified as below reported 1 Device state ChUT in PWM Test execution Increasing Inverse Current is injected in a channel the ChUT up to the lINVERSE th while the ChUT is driven OFF In that case if the INPUT goes from low to high during inverse current injection the output stage is kept OFF and cannot be switched back ON until lwygnsg disappears As soon as I NveRSE th S reached the ChUT sense signal is set to high impedance or VsENseH depending if it is in ON or OFF state respectively The MultiSense current monitor behavior can be identified as an open load indication see Figure 151 Figure 151 Waveforms related to the inverse injection on a channel driven in PMW Tek Run Hi Res e T T m tton J e i Vbatt oe 8v I i NO i INJECTION INSH IN i OE S H p Min C1 203 4mVv inject e a 3 B q 1 Max C3 500 9rV Vsense a i sh i Max C4 1 656A e y T lout II Chit 5SO00rnv Cn2 1 2ms chs 20v Chas 10A hs Tek Run Hi Res om T YT I es Dun o s IN H IN L vos Vbatt OL in OFF state 8v ch0 3 47A EE j INJECTION b diode P 795 Ma C2
5. GAPG1127130958MS Assuming Tpemac gt gt Tpww orr the switching losses can be estimated as follows Vpar 16 V Temperature 23 C Turn on energy loss J Won 3x higher versus equivalent resistive load Turn off energy loss J Worr 3x higher versus equivalent resistive load Note The factor 3 is the result of experiment see Table 21 and Table 22 Measurement example 1 high inductance with external freewheeling single event Conditions e Vepat 16V e Temperature 23 C e Load 20 mH at 13 5 O e External freewheeling diode STPS2H100 e Device VND7040AJ 86 196 DoclD028098 Rev 1 Ly UM1922 Load compatibility Figure 64 High inductance Tpemac gt tworr measurement example 1 LeCroy I LeCroy x VND7040AJ at 20mH 13 50 V i external fre wheeling GAPG1127130959MS Measured losses 20 mH at 13 5 Q Won 11 uJ Wore 533 pJ Measured losses pure resistive 13 5 Q Woy 139 uJ Wore 157 uJ Won ratio 20 mH versus pure resistive 11 139 0 08x Woprr ratio 20 mH versus pure resistive 533 157 3 39x The measured values confirm that the turn on switching loss is negligible zero starting current while the turn off switching loss is 3x higher in comparison with pure resistive load Measurement example 2 High inductance with external freewheeling single event Conditions e Vpar 16 V e Temperature 23 C e Load 1m
6. GND GAPG2111140810CFT Besides since the device input may be driven independently of the microcontroller by a separate HW which is supplied directly from battery it s mandatory to decouple the signal coming from the microcontroller to the one coming from the limp home circuitry in order to avoid any backward supply of one circuit versus the other one The decoupling is ensured by a signal diode placed in series to the Limp Home path connected to the device input Dimensioning of the series resistors on I O line The resistor value should be calculated according to the maximum injected current to I O pin of the used microcontroller That value can be assumed about 10 mA so that the resistors value should be at least 15 kO 150 V 10 mA R 2 15kQ Ly DoclD028098 Rev 1 39 196 Protection against battery transients UM1922 40 196 The basic application schematic has been validated in order to be reliable with the following stress test based the ISO7637 2 standard edition 2004 and 2011 in different operative conditions e ISO n1 2 msec 10 Q 5 K pulses Class C must be complied full operational after each pulse e ISO n2a 50 usec 2 Q 5 K pulses Class C must be complied full operational after each pulse e ISO na 0 1 usec 50 Q 1h Class B must be complied full operational even during pulses exposure e ISO n3b 0 1 usec 50 Q 1h A Class B must be complied full operational even
7. Resistor Rpy connected to Vgar supply results to Vgar VoL MAX Rpu ha vc cUm GND LEAKAGE L off2 MIN Where l off2 is a value present in the datasheet Considering Vgar 7 V ground leakage current lawp LEAKAGE 9 and lj oo 100 HA IN 4V PU 400A For Vgart 7 V Rpy should be applied less than 30 KQ to identify open load in off state 30kQ Minimum Rpy calculation while load is connected In order to ensure that no OL in off state failure flag set if the load is connected minimum Rpy must be evaluated Minimum Rpy can be calculated as follows a 136 196 DoclD028098 Rev 1 UM1922 MultiSense analogue current sense Figure 104 Rpy calculation with load connected Ven Z Voc FauttRST Peu i IND lotta E gt sen CUTO UE NNUS z 2 o S Multisense e Rop 5 ee t Considering lLoAD our ot IL oft2 Pu LOAD n BAr Vour VBAT Vout pg 2 PU PU then Vour _ BAT Vout B t2 g Roan O3 Rey with Vout lt Voi MIN results to R V V LOAD BAT OL MIN OL MIN LOAD L off2 MAX Example 6 Let us consider a VND7020AJ driving a load with Rj oAp 4 and following parameters VoL min 2 V and Vegar 18 V as worst case battery IL oft2 MAX 19 HA Applying below formula the pull up resistance in order not to generate a false OL diagnostic is 4Q 18V 2V PPU 2V 4Q
8. DocID028098 Rev 1 Ly UM1922 Usage and handling of MultiSense SEL pin 5 Usage and handling of MultiSense SEL pin For diagnostic of MO 7 devices one analog monitoring output signal is used It is capable to provide current sense signal reflecting channel output current or digital failure flag in off state signaling open load provided by the presence of an external pull up resistor or short to Voc diagnostic Information about device temperature or Voc voltage can be also selected Signal output is controlled by SE pin enable disable MultiSense output signal and a set of SEL pins used for diagnostic signal selection The number of control pins depends on implementation and number of channels applied on device 5 1 Classification of M0 7 HSDs As preamble of this chapter we can consider the MO 7 high side drivers as belonging to two main groups e Monolithic HSDs one chip is present inside the package e Hybrid HSDs two chips are present inside the package one acting as power stage and the other one acting as drive control and protection stage The main difference between the two categories from an application standpoint is that the Hybrid HSDs have an additional integrated protection against the reverse battery event please refer to Chapter 2 Reverse battery protection In Table 13 the current MO 7 set of high side drivers according to the above classification is presented The assembly package to which the final
9. ST7 Motherboard Power AN ipo Supply 0 5m 1 5mm MO 7 Daughterboard GND 0 5m 1 5mm 1m 1 5mm VFR_uc e VND7xxx Vec Ver FaultRST Vino_uc Vino Vin1_uc INO IN1 Vint Vsen_uc Vsen VstL0 uc Vseto VstL1 uc Vseu1 Vcs uc 15k Vcs 470pF GND Voc l Multisense GND Rsense GND GAPG1121131240MS 22 196 Figure 6 Measurement example tpemac gt tp stpy Without GND resistor 2a VGND DoclD028098 Rev 1 Mode D Couplin Noise Rej gt Holdoff Era 4 UM1922 Reverse battery protection Figure 7 Measurement example tpemac gt tp stay With 4 7 KQ GND resistor B 275v a MIVIN wVOUT i 29 VGND aj TOUT Mode lt D Couplin Noise Rej D Holdoff Kred The experimental trials have shown e The operation with high inductivity load Tpemac gt tp srpv is correct even without the GND resistor only the diode knowing that the device GND pin oscillation with period of tp sty may be present see Figure 6 e Inallcases the 10 kQ resistor was enough to reduce the GND shift below the logic input activation level so eliminate the oscillations e The 4 7 KQ appea
10. Configuration Failure type detection 2x21W Failure of one 21 W detectable without calibration 2x27W Failure of one 27 W detectable without calibration 21W 5W Failure of 21 W detectable without calibration failure of 5 W cannot be detected Failure of one 21 W bulb can be detected without calibration only above 10 V 2x21W 5W battery voltage assuming that a missing 5 W bulb must not trigger the failure diagnostic Ly 130 196 DoclD028098 Rev 1 UM1922 MultiSense analogue current sense 7 2 10 Table 24 Paralleling bulbs overview on the example of VND7020AJ continued Configuration Failure type detection 2x27 W 5 W Failure of one 27 W detectable without calibration failure of 5 W cannot be detected Failure of one 21 W bulb can be detected with calibration assuming that a missing 5 ERES W bulb must not trigger the failure diagnostic The Table 24 shows a set of cases where bulbs in parallel driven by the suitable M0 7 HSD see as reference Table 20 in Section 6 1 Bulbs channel are used The MO 7 HSD family allows the detection of individual bulb failures when in a parallel arrangement However if we consider the bulb wattage spread the HSD K factor tolerance the variation of bulb currents vs Vgar and the resolution of the ADC it is clear that accurate failure determination can be difficult in some cases For example if there are bigger and smaller bulbs paralleled the d
11. General items UM1922 14 196 voltage feedback reading is required For dimensioning the same recommendations apply as for R5 C2 C4 it is recommended to place a ceramic capacitor on each output to dissipate energy of high frequency high voltage transients in particular ESD transient pulses A 100 V ceramic capacitor generally has sufficient voltage capability The device ESD robustness of each pin is rated in Absolute Maximum Rating chapter of the datasheet for details refer to Chapter 11 Usage in H Bridge configurations C5 C5 capacitor helps to suppress voltage transients that originate from other actuators connected in parallel and sharing the same battery line This capacitor will be capable to suppress only low energetic short transient pulses The device itself is rated to sustain ISO 7637 2 2004 E transient test pulses 1 4 up to test level IV according to class C Other methods are needed to protect the module from higher energy transients such as load dump Moreover C5 capacitor helps to suppress HF noise at the Vcc pin that is generated by the high side driver device itself The noise can originate from the charge pump circuitry or from the switching slopes of PWMed outputs Using a 100 nF low ESR ceramic capacitor mounted close to device Veg and GND terminals the devices meet CISPR25 Class 5 requirements measured in conducted emission voltage method in DC as well as in PWM operation Finally during a loss
12. DEMAG DEMAG 0 Eusp EP EN L R ly Voenael y Roya on Equation 7 2 Veat VpEMAGI V simplified for R gt 0 DEMAG 1 limg gEjsp 5 LI Calculation example This example shows how to use above equations to calculate the demagnetization time and energy dissipated in the HSD e Battery voltage Veat 13 5 V e HSD VND7040AJ e Clamping voltage VcLAMP 46 V typical for MO 7 e Load resistance R 810 e Load inductance L 260 mH e Load current at turn off event lo Vpgar R 167 mA Step 1 Demagnetization voltage calculation using Equation 1 VpEMAG VBAT VcLAMP 135 46 32 5V Step 2 Demagnetization time calculation using Equation 2 t Vpemacl lo R _ 0 260 32 5 0 167 81 _ TDEMAG R p Poges ta t ET Sete 1 12ms DocID028098 Rev 1 Ly UM1922 Load compatibility Step 3 Calculation of energy dissipated in the HSD using Equation 6 V V BAT DEMAG DEMAG 0 E __ _ L R I V Ini e HSD R2 0 DEMAG IVbEMAc 13 5 32 5 81 Step 4 Measurement comparison with theory 32 5 0 167 81 0 260 81 0 167 32 5 n ae J 404mJ Figure 74 Inductive load turn off example VND7040AJ L 260 mH R 81 O T Vibat LeCro Vaar 1 n t l LE 36mJ Smm Vout lout Voemag 29V Pioss Vaar Vour lour i E Measure P1 rise C3 P2fall C3 P3 max C1 P4 P5 PB value 251
13. 3 4784 iMax C4 1 808A 4 lout r ILL Ch SO0mV Ch2 204 Q oms Ch3 20v Ch4 104 Q Ch2 GAPG1129131037MS DocID028098 Rev 1 Ly UM1922 Inverse output current behavior 9 3 2 Device state ChUT in PWM Test execution Increasing Inverse Current is injected in a channel the ChUT up to the linverse while the ChUT is driven ON The linveRSE th in this case is much higher than case a The ChUT is turned OFF and there is no possibility to switch it back ON 3 Device state ChUT in PWM Test execution Increasing Inverse Current is injected in a channel the ChUT up to the lINVERSE th While all others are permanently ON Regardless of the ChUT dynamic state either ON or OFF no influence on the other channels behavior is reported In such condition the diagnosis of channels not under test is correct and reflects real output current 4 Device state ChUT in PWM Test execution Increasing Inverse Current is injected in a channel the ChUT up to the lijveRse thy While all others are permanently OFF As soon as the linverse is applied all other channels show increased l or position dependent The closer is the channel to the ChUT the higher is the l off During injection any variation of Vcc signal due to the influence of current injected into the output can be well monitored by the multi sense functionality set in Voc mode Conclusions In case of inverse current disturbance inject
14. On the other hand a decreased number of analogue channels increases the number of control signals separate SE Pins control In total pin count is the same as in Example f The same strategy as GND offset measurement is used in this example Improper configuration on SEn 1 2 outputs causes no valid Vsgwsg result multiple MultiSense outputs can be activated applied into common Rsgwsg Figure 38 Monolithic devices common power supply rails common MultiSense gt GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO A p a Vi aian GPIO AD1 AD2 2 F4 o Ave t 100 nF 50V 100nF 50V ele 100nF 50V s Common bus for SELO 2 Ut U2 us eee A c V NL FauRST x ram x ram SEn_3 at ES x INO X no X ino SEn_2 KJ int XJ nt 15k SEn 1 SEn ouTo OUTO x IN2 OUTO 15k SELO SELO SEn R ina 15k SEL SEL1 SELO 15k SEL2 SEL1 outi ouTt FaulRST Multisense 15k control GND Iu Mulisense c p 100 470pF SEn OUT2 E ale 100 470pF SELO i 5 Dx L SEL1 TE 15k SEL2 outs LX 15k Multisense 15k GND offset measurement GND 100 470pF PE 470pF SNSE 470pF a Resor Ak y Truth table shows signals mapping Table 17
15. VsENSE GAPG1512141604CFT MultiSense diagnostic evaluation with SPC560Bxx Considering analogue monitoring for several outputs appropriate microcontroller must be used Choosing SPC560Bxx dedicated HW blocks can be used with advantage to monitor multiple Csenge signals together with automated MultiSense channel switching SPC560Bxx is capable to generate independent PWM signals for multiple outputs by dedicated hardware block called eMIOS It includes capability to specify trigger position within PWM period for signal A D conversion without any SW intervention 0 96 CPU load in software task used for MUX switching and A D conversion triggering Figure 113 shows specific eMIOS mode applicable for PWM generation and A D conversion triggering OPWMT mode a DoclD028098 Rev 1 UM1922 MultiSense analogue current sense Figure 113 eMIOS PWM generation mode principle Falling edge reconfigured Rising csl Falling Rising sd Falling On rising Trigger Falling edge point edge edgeY point edge edge point edgen i i i 1 i new falling i i dge applied i eMIOS Selected counter bus uC output flip flop T 1 i i i 1 1 i i i i i i 1 i i i i i i i 1 i i 1 i i i i 1 1 1 i 1 i 1 i i i 1 i i 1 i i i i i D i D Corresponds to J device output signal FLAG pin t t 1 Trigger for ADC GAPG1128131001MS eMIOS block is able to control many c
16. eee 167 2 MH 2 8 Q VND7040AJ Ch 0 Chit 0 eee 168 2mH 2 80 with external freewheeling VND7040AJ Ch 0 Ch 1 168 Test setup inductive short circuit test with paralleled outputs 169 Inductive short 5 uH 50 mQ VND7020AJ Ch0 and Ch1 in parallel Latch mode 170 Inverse current injected by a capacitive load llle 172 Inverse Current injected by an inductive load in the high side driver of an H Bridge 173 Inverse current Injected by a short circuit to battery llle 173 Current Injection test set up and concerning a double channel HSD 177 Waveforms related to the inverse injection on a channel driven in PMW 178 ESD current pulses according to different standards 0000 eee e eee 180 ESD test application scheme for HSD placed on a powered module 182 ESD charge device model test scheme 000 cece tte ee 183 Equivalent circuit for ESD protection dimensioning illie esses 184 H Bridge scheme 0 cece cee mr 185 Example of automobile multi motor driving connection 00002 e eee eae 186 VND7040AJ cross conduction with different OMNIFET delay times 187 VND7140AJ cross conduction with different OMNIFET delay times 188 VND7012AY cross conduction with different OMNIFET delay times 189 PowerMOS capacitance effect duri
17. gt lt Loss of Vec ee 150 7V T pre gs Voc Y Ld I GND FR e I 143V M 143V Vos from 0V to 46V x A depending on actual gate SEn charge The lowest 143V voltage potential SEL 196 7V 143V Lv S A Multisense e 4 P Bi F sms 150V GND 1 450V i i P l Vout Diode is conducting in avalanche mode i Venp Reno W Deno Ri Breakdown voltage i j e g 150V mE MI GND GND GAPG2111141443CFT The Vec pin is pulled down by the output via the device power MOSFET If the gate of this MOSFET is still charged immediately after the Vcc disconnection the Vcc pin voltage follows the OUT pin voltage while the voltage levels on both pins are the same neglecting the voltage drop on Rpsoy As the gate is being discharged the voltage drop can rise up to the Vc_amp 746 V as indicated on the figure Since the Vcc pin is floating neglecting the Vcc capacitor the negative voltage is theoretically unlimited no external freewheeling considered no discharge path for the demagnetization available Practically the Vcc pin voltage is limited by the breakdown voltage of the GND network diode through which the demagnetization paths is closed the GND pin is also pulled down via an internal Vcc GND clamp structure with o
18. 153 8 1 2 Hybrid HSDs supplied from different supply lines 155 8 1 3 Mix of monolithic and hybrid HSDs lesen 155 8 2 Paralleling of MultiSense 0 00 c eee eee 158 8 2 1 Monolithic HSDs supplied from different supply lines 158 8 2 2 Hybrid HSDs supplied from different supply lines 159 8 2 3 Mix of monolithic and hybrid HSDs supplied from different supply lines rr cT 160 8 3 Paralleling of GND protection network 0000 0c cence 162 8 4 Paralleling of outputs cuc sam UR RAI RR A CR RR RO Y RO CAR wed 163 8 4 1 Current balancing with resistive load llle 163 8 4 2 Overload behavior with resistive loads 200ee eae 165 8 4 3 Driving inductive loads 0 0 cece tees 166 9 Inverse output current behavior 2000 cece eee eee eee 172 9 1 WMIOOUCHON iior a Garon ses os tore E Rea Se els a eRe 172 9 2 Device capability versus inverse current 2 2200055 173 9 2 1 Device in steady state 0 eee 174 9 2 2 Device driven in PWM sssseeeeeeee eh 178 9 3 Conelusions 2 125 ew ura ue ace dd aire Send es veces Res EVE x 179 10 ESD protection ssins nura au kx amd 4E RR RR 180 10 1 EMC requirements for ESD at module level 005 180 10 2 EMC Requirements for ESD at device level 000 183 10 3 Design and layout basic suggestions to increase ESD failure po
19. 90 C 2 Condition 3 applied to VNQ7140Ad is fulfilled with TcAsg 95 C Simulation example VN7016AJ with H4 bulb 60 W A simulation is performed in order to verify if the driver is able to turn on the bulb and matches the requirements under the defined conditions see 1 Normal condition 2 Cold condition and 3 Hot condition below The tool used for this simulation is based on Matlab Simulink Figure 42 Principle of the setup used for the simulation Line in NIN 1mQ i Vbatt TN Vin Sense VN7UTBAJ Resistance 2cn PSO16 3kQ GAPG1122131140MS 1 Normal condition VBAT 13 5 V TCASE 25 C TBuLB 25 C Requirement 66 196 none of the protection functions must be triggered DocID028098 Rev 1 Ly UM1922 Load compatibility 4 Figure 43 Simulation result normal condition 80 Vbatt 13 5V Tamb 25 C ILimH 77A RdsOn 14mQ Rin 1mQ Rout 10mQ VN7016AJ Device 2cm PSO16 Tj C lout A a Vout V 0 01 0 02 0 03 0 04 0 05 Time s GAPG1122131141MS Cold condition VBAT 16V Tease 25 C TBULB 25 C Requirement power limitation allowed for durations of less than 20 ms autorestart mode considered DoclD028098 Rev 1 67 196 Load compatibility UM1922 68 196 Figure 44 Simulation result cold condition Vbatt 16V Tamb 25
20. DoclD028098 Rev 1 131 196 MultiSense analogue current sense UM1922 Vsense 17 6 mV measured value lout _ lour 30mA K mp SSS E 3750 CALIBRATED laENSE VsENSE 17 6mV BZ 2 2kQ PsENSE Maximum Vsense level for open load detection is then OUT 10mA KsENSE OL RSENSE Kory 2200 Soe 8 4mV And following minimum Vsgwsg for low current load at 50 mA OUT 50mA KsENsE LOAD RSENSE Kay 2200 5 519 22 6mvV Considering 12 bit A D converter for Vsenge monitoring with error of 2LSB bits and measurement range 0 5 V gives precision 5V IE uer 4dgog cem 2 LSB Considering a maximum leakage of 0 3 pA of the ADC this causes on the 15 KO ADC series resistor an error on ADC voltage of 4 5 mV Even applying these errors result is a non overlapping thresholds for detection of e Open load lour lt 10 mA where Vcense lt 8 4 mV 2 mV 4 5 mV Max 14 9 mV e Minimum load lour gt 50 mA where Vsense gt 22 6 mV 2 mV 4 5 mV Min 16 1 mV Figure 101 gives a graphical explanation of the Example 4 132 196 DoclD028098 Rev 1 Ly UM1922 MultiSense analogue current sense Figure 101 Example of single point calibration at low current for VND7020AJ Low current detection with single point calibration Low current Load 40 w a Vseuse m V w N un K_MAX 30 VSENSE_MIN mV Low curre
21. Emp ERES VND7140A DE d 200 Vcc 14V lout 0 3A D A Rds on mOhm m e uo 40 20 0 20 40 60 80 100 120 140 160 Tj C GAPG1127130944MS Figure 49 Ron dependency on Vcc measured on a VND7140AJ sample nes 350 300 NB amm EE rm 2 1 __ __ ote e device in Na P T T3 connected directly to module 100 GND batt Bb Fem pem Dn EE ERES ER UR DR ea o a ee ee ee E 0 2 4 6 8 10 12 14 16 Vcc V Rds on mOhm GAPG1127130945MS DoclD028098 Rev 1 71 196 Load compatibility UM1922 72 196 Figure 50 Roy dependency on lour measured on a VND7140AJ sample 300 noaoo 140 VND7140AJ E400 ae 100 o gt eie i r E z 40 Rds on 20 Eesti O 100 200 300 400 500 600 700 800 900 1000 lout mA GAPG1127130946MS The calculation of conduction losses in PWM mode is based on similar consideration as in case of steady state losses focusing on Ron lout ton however it is important to consider right PWM on time corrected with the turn on off switching delays and switching times and right current in on state for instance in case of bulb it depends on actual duty cycle Corrected duty cycle laoN laorr iwoN Door D 2s period where UN high D eH period Duty cycle applied on input pin t dON CM s dOFF Turn on off delay time won s Turn on switching time ON state power dissipation W 2 Pon Ron
22. OUT ON DocID028098 Rev 1 Ly UM1922 Load compatibility Note 6 2 2 In case of bulb the load current in on state depends on actual duty cycle Average power dissipation W Pava Pon Dcon Switching losses The switching losses are important especially in PWM operation Compared to conduction losses the calculation depends on many factors like the load characteristic resistive capacitive or inductive device characteristics switching times and environmental conditions ambient temperature battery voltage The switching shapes of MO 7 devices are optimized to fulfill the EMC requirements with minimum switching losses Moreover the turn on and turn off shapes are symmetrical to ensure minimum duty cycle error Switching losses resistive loads bulbs This sub chapter deals with all kind of loads with resistive character such as bulbs heating elements etc The inductivity of wire harness is neglected lt 5 uH considered The next calculations are simplified assuming constant resistance of the load However it is applicable also for non linear resistive loads bulbs driven in PWM mode The PWM frequency is usually high enough gt 50 Hz to minimize the filament temperature resistance variation over the PWM period so it behaves like constant resistor The instantaneous power dissipation in the switch during the switching phase is equal to drain to source voltage Vps multiplied by the output
23. Ter UM1922 y life qugmented User manual VIPower MO0 7 standard high side drivers hardware design guide July 2015 Introduction VIPower parallel high side drivers have reached the 7 generation of smart power drivers internally called MO 7 In this latest set of drivers all the experience and know how from existing features of the previous generations as well as new features have been implemented The continuous increasing demanding requirements from automotive customers in terms of quality reliability flexibility and cost effective system solutions represent the basic factor of new protection feature concept latch off in overload condition beside the already known auto restart feature and new diagnostic features like real time device case temperature and battery terminal voltage sensing beside the already existing output current sensing available to the microcontroller in a unique MultiSense pin Purpose of this user manual is to give a comprehensive tool kit for a better understanding of the behavior of the MO 7 parallel High Side Drivers abbreviation HSDs in their application usage context and thus allowing the design engineer an easier design in DoclD028098 Rev 1 1 196 www st com Contents UM1922 Contents 1 General ECU SS oe een ki cc irae be lad i it a 11 1 1 Overview about MO 7 standard high side drivers 55 11 1 2 Application schematics monolithic devices
24. pn uo ogsouBeip 352 99A ou 17 2713S Old alum vn 1 PAM pariod 147 96 DoclD028098 Rev 1 MultiSense analogue current sense UM1922 7 2 13 7 3 148 196 MultiSense low pass filtering Figure 118 Low pass filter connection Vbat Voc C uC ADC Rerotection Multisense M Isense a E Rsense V fis T 470pF SE 4k7 GND GND GND GND The current sense voltage is usually connected through a 15 kO protection resistor to the ADC input of the microcontroller In case of Vsengeq level the voltage is limited by the microcontroller internal ESD protection 75 6 V while the ADC shows maximum value OxFF in case of 8 bit resolution The capacitor CF is used to improve the accuracy of the Vsense Measurement refer to Figure 118 This capacitor acts as a low impedance voltage source for the ADC input during the sampling phase Together with 15 kQ serial resistor it creates a low pass filter with cutoff frequency of 22 kHz against potential HF noise on the MultiSense line especially if a long wire is routed to the microcontroller This capacitor should be connected close to the microcontroller Chosen value of filtering capacitor 470 pF together with Rerotection 15 KQ results in a time constant lower than settling times between multiplexer selection control of SEL pins so with a minimized delay between SEL
25. value 10v status op Porin asav ELI Measured losses 20 mH at 13 5 Q Won 307 wd lour 1 A Worr 463 wd lour 1 2 A Measured losses resistive 13 5 Q Won 139 Wd lour 1 2 A Worr 157 wd lour 1 2 A Won ratio 20 mH versus resistive equivalent 307 139 12 1 2 3 18x Worp ratio 20 mH versus resistive equivalent 463 157 2 95x GAPG1127131000MS 4 DoclD028098 Rev 1 UM1922 Load compatibility The measured values confirm that the turn on and turn off losses are 3x higher in comparison with equivalent resistive load Measurement example 4 High inductance with external freewheeling PWM Operation Conditions e Vpar 16V e Temperature 23 C e Load 1mHat20 e External freewheeling diode STPS2H100 e Device VN7004AH E e PWM 80 at 500 Hz Figure 67 High inductance TpgyAc gt Tpwm orff measurement example 4 Voet LeCroy VN7004AH at 1mH 20 external freewheelin PLoss Vaar Vour lour i pasir Plrise C1 P2rise2080 C1 P3fallC1 P4fallB020 C1 P5 PE al 6 84233 us 19 75917 us 8 37900 us sais rA v P4 10 0 Vidiv 5 00 A div 10 0 Vidiv 5 00 Aldiv 50 0 Widiv 500 usidiv Stop 3 35 A 10 000 v 0 mA offset 20 000 V 5 000 A ofst 500 usidi UE EP ULES IEEE EL LeCroy Won 2 foes 0 dani Pin d P2 nse3080 Cf E Mc P niEmUCO PSareaFt Measure Pansat Prnsezos0 ct Pane mag P alin20 c3 P5areaF
26. 25 5 25 5 25 5 4 4k Y Y Y Y 4 e 2 GAPG1127130950MS The first example shows a simple LED cluster with serial parallel combination of LEDs and resistors In the second example there is a schematic and V A characteristic measured on a real LED lamp VW Passat B6 As seen on schematic on top of the serial parallel LED resistor strings there is a reverse battery protection diode ESD capacitor on input terminal and dummy load circuitry with bipolar transistors This circuitry is used to adapt the LED string behavior V A characteristic according to diagnostic requirements open load in on state open load in off state Example 1 Switching losses measurement The following example shows the switching losses measurement on VND7140AJ with LED cluster example 1 LED test board 6 x 3 LEDs OSRAM LA E67 4 using an oscilloscope with mathematical functions The first function F1 shows the actual power dissipation on the HSD Vegart Vout lout the second function F4 shows the HSD energy integral of F1 Conditions e Vpar 16V e Temperature 23 C e PWM 200 Hz 70 e load test board with 6 x 3 LED OSRAM LA E67 4 see Figure 54 e Device VND7140AJ DocID028098 Rev 1 Ly UM1922 Load compatibility Figure 56 Slew rate and switching losses VND7140AJ LED test board LN Ud 2 9 A ba value 1721428
27. C 93 Paralleling bulbs overview on the example of VND7020AJU 20 0005 130 VsEgNse measurement sies ee 133 MultiSense pin levels in off state llli eee 139 Diagnostics overview lille teas 140 SPC560Bxx example signals mapping 000 c eects 146 Example of channels configuration on a dual channels HSD 004 174 Inverse current threshold experimental values according to channels status ChO is the channel under test ChO ON llieesseeseeee eens 175 Inverse current threshold experimental values according to channels status ChO is the channel under test ChO OFF 0 0 cee eens 176 MO 7 HSDs ESD results osne crara nrerin ee eee n eens 183 Maximum switching slopes which do not cause cross current due to MOSFETs capacitances measurements on a sample on each component 000 eee ee eee 191 Document revision history 1 0 00 eee eae 195 4 DoclD028098 Rev 1 UM1922 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37
28. TT I m Binan AvourT M R i HVT EYE wIVSENSE 3 VSENSE m 1f RH H Tue NN li TOUT TOUT emp Sd dd th Cursors Menu GAPG1122131113MS Even more the FaultRST pin can be managed as a global system pin connecting this pin of several high side drivers in parallel to a specific microcontroller I O port refer to example in Figure 32 and Section 8 1 Paralleling of logic input pins for advice on how to parallel pins This signal is always kept high means all connected devices are configured in latch off mode except e Fora periodical unlatch pulse for duration longer than t_atcy pst Max once per diagnostic period This unlatch pulse aims at restarting all latched channels which are supposed to be restarted i e when the debouncing strategy for short circuit detection is not yet elapsed e Forablanking pulse FaultRST low for i e 10 ms generated at every activation of any channel Figure 33 illustrates the described FaultRST pin handling concept DoclD028098 Rev 1 53 196 Usage handling of fault reset and standby UM1922 54 196 Figure 32 Common FaultRST pin handling example basic schematic without decoupling components HSD 1 quad channel HSD 2 quad channel HSD 3 dual channel HSD 4 dual channel HSD 5 dual channel HSD 6 dual channel HSD 7 dual channel HSD 8 dual channel GAPG1122131114MS Figure 33 FaultRST pin handli
29. The resistive one is made by the RC content of the standard used see Figure 152 Figure 152 ESD current pulses according to different standards IEC ISO 150pF ISO 330pF 18 4 16 14 z 12 10 T S 8 aj 2 0 T T a a 20 0 20 40 60 80 100 Time ns GAPG0912141016CFT Typical car makers ESD requirements at module level are the following 3 DocID028098 Rev 1 UM1922 ESD protection Module not powered during the test This test simulates any possible handling of the module before being assembled in the Car Connector pins to test are normally the ones that go out of the module Supply pins protected and or filtered as per datasheet Output pins protected and or filtered as per typical design practice e g ceramic capacitor Standard applied is the ESD HBM Automotive acc IEC61000 4 2 150 pF 330 Q0 Required acceptance limits are in 4 KV 8 KV range contact discharge Test execution requires a sequence of 3 to 5 ESD pulses applied with fixed delay time 1s typically Pulses are applied either by touching the pin under test with the ESD gun contact discharge or without touching it air discharge Test is passed if no pin to pin IV characteristic degradation is reported after pulses exposure This test simulates any possible handling of the module before being assembled in the car In some c
30. a 9 e 41400 Voc VrE Vec VSENSEH 0 44300 VoctVe Vor VSENSEH 0 E ky DoclD028098 Rev 1 175 196 Inverse output current behavior UM1922 Table 30 Inverse current threshold experimental values according to channels status Ch0 is the channel under test ChO ON continued Channel configuration MultiSense enabled in current monitor mode 5 Ch0 ON Ch1 ON Ch0 ON Ch1 OFF a 5 RL ch0 10 k RL ch 10k RL ch0 10 k RL ch1 10k c 5 V V G SENSE SENSE a Ed Vout V configuration didus Vout V configuration Cho mA cho cht cso csi CPOIMA cho chi cso cst uj 201800 Voc d 0 mm lt 3 nrg S 2 212800 VcsV V X 1r ccotVF SENSEH ES z gt aan LE Table 31 Inverse current threshold experimental values according to channels status ChO is the channel under test ChO OFF Channel configuration MultiSense enabled in current monitor mode 5 Ch0 OFF Ch1 ON Ch0 OFF Ch1 OFF a 5 RL ch0 10 k RL chi 10k ChO floating RL ch 10k c P V V G SENSE SENSE a pios Ten Vout V configuration ais Ton Vout V configuration CholmA cho chi cso csi CIA cho cni cso Csi 2 0 7 Vectd Vcc VsenseH 0 0 7 Vcc d 0 VSENSEH 0 a S 2 s Vv Veo V 0 30 VceVe 29 v 0 5 i CC tVF Vcc VSENSEH CC F zyg SENSEH 2 2
31. channel ON no fault SE active While device is operating in normal conditions no fault intervention Vsense calculation can be done using the following simple equations Current provided by MultiSense output Isense lout K while the Voltage on Voltage on RseENSE VsSENSE RsENSE ISENSE RsENSE louT K Where e Vgense is the voltage measurable on Rgense resistor e lsENsre is the current provided from MultiSense pin in current output mode e lour is the current flowing through output e K factor represents the ratio between Power MOS cells and Sense MOS cells Its spread includes geometric factor spread current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between lout and Isense Current monitoring range of linear operation During the current monitoring the voltage on MultiSense pin will have a certain voltage depending on load conditions and Rgense value as default value it can be assumed for example that MultiSense voltage at nominal load current is 2 V Particular care must be taken for the correct dimensioning of the Rgengg in order to ensure linearity in the whole load current range to be monitored for different the full dimensioning rules on Rgense please seeSection 7 2 5 Failure flag indication In fact the current monitoring via MultiSense is guaranteed until a maximum MultiSense voltage of 5 V defined as minimum value of Vsense sat in MO 7 datasheets Example 1 Mu
32. control signals and ANXO ANX1 signals is shown DoclD028098 Rev 1 145 196 MultiSense analogue current sense UM1922 Table 28 SPC560Bxx example signals mapping GPIO mai mao maz Negative ANXO ANX1 MA2 SEn SEn A SEL3 SEL SELg U1 U2 U3 U4 MultiSense MultiSense X L L H L CurrentSense ChO CurrentSense Cho a g lt X L H H L CurrentSense Ch1 S CurrentSense Ch1 S 2 25 25 X H L H L Tcuip Sense E B Tcuip Sense 3 5 S X H H H L Vcc Sense 7 Voc Sense L L L L H CurrentSense ChO NET CurrentSense ChO lt L L H L H CurrentSense Ch1 v amp CurrentSense Ch1 o eo L H L L H Tcuip Sense gt B CurrentSense Ch2 o 2 5 lt L H H L H Voc Sense gt CurrentSense Ch3 at amp Oz H L L L H CurrentSense Cho Tcuip Sense B S a X 2 H L H L H CurrentSense Chi 5 S Vcc Sense zu 0 H H L L H Tcuip Sense E 2 5 Tcuip Sense H H H L H Voc Sense z Voc Sense 1 SEL not applicable output according SEL SELo and SEn 146 196 Time diagram shows A D trigger points of MultiSense diagnostic DoclD028098 Rev 1 4 MultiSense analogue current sense UM1922 Figure 117 SPC560Bxx example MultiSense trigger points H Grap 1 active MA2 1 H H i 9 64us 64us Mux settling time Grap 2active MA2
33. e Vat 16V e Temperature 23 C e PWM 200 Hz 70 96 e Load 13 5 Q 60 uH at 13 5 Q calculated Tpemag 1 9 us e Device VND7040AJ DoclD028098 Rev 1 81 196 Load compatibility UM1922 82 196 Figure 59 Low inductance TpgyAg lt lt tworr measurement example VND7040AJ at 13 50 x P2AaIK C3 Pinse c3 3519113308 GAPG1127130954MS Measured losses pure resistive 13 5 Q Won 139 uJ Worr 157 uJ Measured losses 60 uH at 13 5 Q Won 116 uJ Worr 204 uJ Won ratio 60 uH versus pure resistive 116 139 0 83x Worp ratio 60 uH versus pure resistive 204 157 1 30x High inductance TpEMAG gt tworr If the load inductance is relatively high so the time needed for the load demagnetization is much higher than the HSD turn off time tworr the output voltage at turn off phase is forced negative so the load current continues via the HSD output clamp see Figure 60 4 DoclD028098 Rev 1 UM1922 Load compatibility Figure 60 Switching losses with high inductance Tpemac gt tworr Vout N lour Veat VNoM Inom MO 7 HSD 0 Vbemac Pioss Pmax f Reno y Denn Vout twon ton tworr GAPG1127130955MS The above example explains a single turn on turn off event This means that zero load current is considered at the beginning of turn on phase and nominal load curren
34. i channels GAPG1112141518CFT A second solution with an additional branch in parallel R2 low drop diode D depends on specific considerations The Table 8 gives a suggestion according to the Hybrid device type and to the logic level of Input pin adopted The given suggestion based on some experimental measures take into account a minimum high state input voltage on Regulator s side and the maximum voltage drop on 15 kQ I O series resistance This yields a maximum allowed GND voltage on the device s GND network for 5 V and 3 3 V system Table 8 GND network proposals for Hybrids HSDs Single double channels VN7007AH VN7004AH E VND7012AY Device Vpeg supply voltage Quad channels VNQ7040AY R1 270 Q low drop D 5V Assumption max allowed GND Shift 1 67 V 3 3 V Assumption max allowed GND Shift 0 33 V Only R1 150 Q value for each driver Only R1 33 Q value for each driver series resistor R2 47 Q value for each driver Vz D gt 150 V Only R1 18 Q value for each driver e Hi must be chosen taking into account the two following limits Minimum value is chosen according to the signal clamp structure energy capability and maximum power dissipation allowed inside the component the lower is the resistance value the higher is the Power dissipated during the pulses Maximum value is chosen to guarantee PowerMOS operation in full Roy during reverse battery a
35. several cases can occur depending on the combination of channels operating conditions ON or OFF state A single channel HSD can be intended as a subset of a generic multichannel high side driver The inverse current linverse could modify the behavior of the channel under test ChUT and of the others close by The analysis is performed both while the channels operate in DoclD028098 Rev 1 173 196 Inverse output current behavior UM1922 static way permanent operation and while they are dynamically controlled PWM operation The first Inverse value that modifies the expected channels behavior is called lINVERSE th Inverse current threshold In case of static operation channel permanently ON or OFF the linverse th changes either the ChUT and the others previous state In case of dynamic operation the liNveRse th inhibits the effect of the input command used to change the channel state for instance the linverse n inhibits the turn ON of the ChUT and the others while are in OFF state at the time the inverse current is applied Moreover the effects of the linverse are reported looking at the behavior of the diagnostic that could be modified by this current injection Effects of linyverse are reported in the two following operating conditions 1 Device in steady operation DC operation 2 Device in PWM operation 9 2 1 Device in steady state Based on channels permanent status three major cases can be
36. 0 7 Vectd Vcc VsenseH 0 0 7 Vcc d O0 VSENSEH 0 JE S2 30 Vec Ve Vec IV 0 30 Vesa 2 gt Jv 0 i CCtVF CC VSENSEH CC F lt Vo VSENSEH za m 0 7 Vectd VsENsEH lt o wg 5 g 30 VectVe VsenseH 713 176 196 DoclD028098 Rev 1 4 UM1922 Inverse output current behavior Table 31 Inverse current threshold experimental values according to channels status ChO is the channel under test ChO OFF continued Channel configuration MultiSense enabled in current monitor mode 5 Ch0 OFF Chi ON ChO OFF Ch1 OFF a 5 RL ch0 10 k RL ch1 z 10k ChO floating RL ch1 10k c 5 V V S SENSE SENSE a xi Vout V configuration didus Vour IV configuration ChO ImA cho cht cso csi CPOIMA cho cm cso Csi 2 0 7 Vectd Vcc VsenseH 0 0 7 Vcc d O0 VSENSEH 0 S 2 Ww gt 0 9g 30 Vcc Vr Voc VsENsEH 0 30 Vcc Vr cy VSENSEH 0 gt Z gt 0 4 Vectd Vcc VsenseH 0 0 4 Vcc d 0 VSENSEH 0 ES 5 2 10 VoctVe Voc IV 0 10 Vee 2 gt ly 0 2 6 cc tVr Voc VseNseH co Vr Vo VSENSEH B ul 0 4 Vectd VsENsEH t ee zl 3H RIS 10 Voc Vr VsENsEH Z gt gt 2 Figure 150 Current Injection test set up and concerning a double channel HSD 12V uc
37. 12 1 3 Application schematics hybrid devices 2000000 ee 13 1 4 Application schematics description of external components 13 2 Reverse battery protection 0000 c eee eee eee 16 2 1 IntroduGtlOn us ose sra Seem Rb bed rudem AAG ade d AUR 16 2 2 Reverse battery protection of monolithic HSDs 16 2 2 1 Schottky diode iio eringni teei ee ede em eua Y hide d ed 17 2 2 2 Diode resistor in GND line llle 18 2 2 8 N channel MOSFET in GND line 000 cece eee 24 2 2 4 P channel MOSFET in the Voc line 62 ee eee 28 2 2 5 Dedicated ST Reverse FET solution llle 31 3 Protection against battery transients Le 34 3 1 Introduction on automotive electrical hazards 34 3 2 Source of hazard on automotive 0 ee 34 3 2 1 Conducted hazards 0 0 ccc tenes 34 3 3 Propagation of electrical hazards on the supply rail 35 3 4 Standard for the protection of automotive electronics 36 3 5 Basic application schematic to protect a MO 7 standard monolithic high side ond Pc EPI TTD 37 3 5 1 Components dimensioning sse 38 3 6 Component dimensioning for hybrid devices llus 41 3 6 1 Dimensioning of the series resistors on O line 43 3 6 2 Dimensioning of the GND network to pass the ISO n 1 and 2a level IV 2011 edition suse ciotatta
38. 14 V e Temperature 25 C e Device VND7040AJ e Load 2 mH 5 5 Q a Limited by safe operating area according to Tpemac single pulse Limited by max junction temperature repetitive pulses DocID028098 Rev 1 Ly UM1922 Load compatibility Figure 78 Test setup verification of new external clamp proposal Power My Oscilloscope Supply a a E E E E Ol g Ch 1 Ch 2 Ch 3 Ch 4 e oF 9 E E Ww Ww eo eo 2 1m 1 5mm ST7 Motherboard L MO 7 Daughterboard GND Vreg id T a cc ST7 100nF Vi d GND VNX7xxx GND 15k Voc GPIO FaultRST T5k GPIO INO y EEF 15k nductive GPIO IN1 OUTO OUTO af 2 ee L 22nF louro 15k een GPIO SEn 5i 15k L GPIO SELO GND CLAMP oi 15k Vourt GPIO SEL1 OUT1 Li A Ext freewheeling Vikis 1N4007 15k 22nF ADC Multisense cus Rsense GND 470pF peti ZDi 15V GND GND R2 ADC A vec 15k y ks GND y al Qi 1 FDT86113LZ GND GND GAPG2111141212CFT Repetitive operation PWM 50 96 at 100 Hz the demagnetization time is shorter than the PWM off state time see Figure 79 4 DoclD028098 Rev 1 105 196 Load compatibility UM1922 106 196 Figure 79 PWM 50
39. 3 6 2 Dimensioning of the GND network to pass the ISO n 1 and 2a level IV 2011 edition DoclD028098 Rev 1 15 196 Reverse battery protection UM1922 2 2 1 2 2 16 196 Reverse battery protection Introduction A universal problem in automotive environment is the threat of damage when an end user inverts the battery polarity Users of battery powered equipment expect safeguards to prevent damage to the internal electronics in the event of reverse battery installation These safeguards can be either mechanical use of special connectors or electronic In that case battery powered equipment designers and manufacturers must ensure that any reverse current flow and reverse bias voltage is low enough to prevent damage to the equipment s internal electronics To provide these electronic safeguards different concepts applying passive or active reverse polarity protection are possible and described in this chapter Depending on the type of device monolithic or hybrid for classification please refer to Section 5 1 Classification of MO 7 HSDs a specific protection must be implemented in order not to exceed the device s reverse capability e Monolithic HSDs the reverse battery protection needs to be inserted according to the instructions suggested in this chapter In particular if the reverse polarity protection is installed on device GND connection the device will conduct through the body diode of the power MOSFET with t
40. A special care must be taken in case of inductive Vgar connection long wire harness Even a few pH of inductance of the supply line can generate a positive over voltage pulse on Voc pin at turn off latch off of the outputs in case of short circuit conditions This positive pulse could activate the Vcc GND signal clamp and cause damage of the device Therefore it is recommended in case of long battery cables to add gt 100 uF low ESR electrolytic capacitor between the Vcc pin and GND in order to keep the Vcc peak voltage safely below the minimum clamping voltage Vc_amp It is always recommended to run an experimental verification on module level to confirm the correct dimensioning and placement of the DoclD028098 Rev 1 Ly UM1922 UM1922 Paralleling of devices capacitor Practical experiments on MO 7 HSDs show that this capacitor is not needed in case of paralleling of two channels of high ohmic devices VND714044J Ly DoclD028098 Rev 1 171 196 Inverse output current behavior UM1922 9 9 1 172 196 Inverse output current behavior Introduction The objective of this chapter is to describe the robustness of MO 7 monolithic devices submitted to disturbances injected on output in a typical application scheme Sometimes devices operate in condition where the Output voltage can be higher than the supply voltage Vs for instance because the device is driving a Capacitive see Figure 148 or Inductive Load for
41. F4 shows the HSD energy integral of F1 Figure 76 Inductive load turn off VND7020AJ L 2 2 mH RZ 40 Vi Vbat LeCroy Vout E 49 1mJ 1 Note Parallel resonance between 2 2mH and ESD capacitor 22nF Pioss Vagar Vour lour Measure Pt rise C3 P2 A P3 max C1 value 14 593004S 95 anaes status 10 0 Vidiv 10 0 Vidiv 2 00 A div 50 0 Widiv 5 00 mJidiv LEUTE SEL Stop 5 5 VI 20 000 10 000 V 2 000 A ofst 100 psidiv 100 psidi 1 00MS 1 0GS s Edge Negative X1 395 694 us LIES Ed 35 mvi Eu bd 90 mv 19 103 GAPG1127131009MS As seen from the oscillogram measured values are close to the theoretical calculation Eusp 19 1 mJ 20 1 mJ calculated Tpemac 220 us 235 us calculated Conclusion The device can safely drive the load without additional protection The worst case demagnetization energy is clearly below the device limit External clamping protection The main function of an external clamping circuitry is to clamp the demagnetization voltage and dissipate the demagnetization energy in order to protect the HSD It can be used as a cost effective alternative in case the demagnetization energy is exceeding the energy capability of a given HSD A typical example is driving DC motors high currents in combination with high inductance During the selection of a suitable HSD for such kind of application we usually end up in the situation that a given HSD is fitting in terms of current profi
42. Figure 38 Figure 39 Figure 40 Figure 41 Ly Typical application schematics monolithic devices 00000 2 eee eee 12 Typical application schematics hybrid devices 0000 0c eee eee eee 13 Voltage levels during reverse battery diode resistor protection 18 Negative GND shift TDEMAG gt tD_STBY 0 00000 cece eee eren 21 GND resistor requirements inductive load test setup 0 0002 e eee eee 22 Measurement example tpemac gt tp stpy without GND resistor 22 Measurement example tDEMAG gt tD_STBY with 4 7 KQ GND resistor 23 Generic schematic and test setup with N channel MOSFET in GND line 26 MOSFET solution in GND experiment VND7020AJ ISOpulse 1 150V 90 Q 27 Reverse battery test VN7016AJ 13 5 V 4 V 82 mQ R2 15 KQ as per LV 124 2009 10 standard ick ste xem yeh X PURO GRADA DR AUR sd 28 Generic schematic and test setup with P channel MOSFET in Vcc line 29 MOSFET solution in Vcc experiment VND7020AJ ISOpulse 1 100 V 90 Q 30 Reverse battery test according to LV 124 2009 10 VN7016AJ 13 5 V at 4 V 82 mO pela ale eee ee el edd eae ie Eee eee 31 Reverse polarity protection reverse FET protection 0000 eee eee 32 Maximum current versus duration time of VNBROOSH E 0200 eee 33 Conducted hazards sc wade ego salts dares ww d
43. LeCroy Vout Vsense Saturation Thermal Protection Vsense_H latch off Current limitation reached Current sense is in high impedance when Vou lt 5V a 5 00 Vidiv 100 mVvidiv 2 00 Vidiv 5 00 Vidiv 50 0 psidiv Stop 8 40 V 0 mY offset 300 00 mV 4 000 V ofst 5 000 V ofst 250kS5 SOOMS sfEdge Negative Considerations on MultiSense resistor choice for current monitor In normal operating conditions the following equation describes relation between lour and VSENSE Equation 8 OUT Vsense Rsense sense PseNusE K lV Design value of Sense Resistor can be calculated from the above equation given the intended voltage at the ADC with the nominal load current and the typical K factor of the device The calculated sense resistor implies the following considerations that the Hardware Designer has to take into account 1 In normal operating conditions in order not to reach MultiSense voltage saturation VsENsE sar With the maximum load current that can be read lout max the Rsense has to fulfill the following equation Equation 9 VsENSE SAT MIN V OUT MAN RsENsE lt Kin DoclD028098 Rev 1 Ly UM1922 MultiSense analogue current sense Within this maximum current linearity of MultiSense is guaranteed If a lower maximum load current needs to be read like for example LED string the Rsense value must be increased 2 In normal operating conditions the maximum sense voltage that can be r
44. S e SEn Rpull up mu 10k OUT R3 SEL LJ L m l OUT i ADC in Multisense RS hd La e GND Cext Rsense OUT C4 4 1 10nF GND GAPG1121131237MS 1 4 Application schematics description of external components Pull up this resistor is optional and is needed when open load in off state diagnostic is required It has to be dimensioned to pull up the output above the maximum open load in off state detection voltage VoL max and make sure that the output voltage stays below the minimum open load in off state detection voltage Vo min in case the load is connected for details refer to Section 7 2 11 Open load detection in off state R5 Cgy a low pass filter as an RC filter can be placed across the Rsense resistor to suppress HF noise The time constant of this filter t RC should be long enough to effectively suppress the noise and short enough to allow MultiSense signal stabilization taking into account multiplexer delay and settling times C2 should be placed close to the MCU s A D input Also the ground connection for C2 should be at the same potential as the ground of the A D reference The filter resistor R5 is also used to limit the A D s input pin current for details refer to Section 7 2 13 MultiSense low pass filtering R6 Cgy1 this low pass filter and ADC input connection is optional and is recommended for monolithic devices when a precise chip temperature or supply DoclD028098 Rev 1 13 196
45. Usage handling of fault reset and standby Table 11 Truth table Mode Conditions INx FR SE SEL OUTx MultiSense Comments Standby All logic inputs L L L L L Hi Z Low quiescent low current consumption Nominal load L X L connected Outputs configured Normal Tj lt Trsp p L Refer to Table 12 1 pe for auto restart Table 12 ang Outputs configured AT lt ATj_sp M j H for latch off Overload or L X L short to GND pian Refer to Table 12 Referto Output cycles with Overload H L H Table 12 temperature Tj Trsp i j hysteresis and AT gt ATj sp Outputs latch off Re start when L Hi Z Undervoltage em X X X x i Lig Voc gt Vusp Vusp hyst rising OFF state Short to Voc L diagnostics i Open load L X Refer to Table 12 H da NA External pull up Negative output Inductive loads L X lt 0 V voltage turn off Table 12 MultiSense multiplexer addressing for a dual channel device MultiSense output SE SEL SEL MUXchannel Normal mode Overload OFF state diag Negative output L x x Hi Z Channel 0 P H L L diagnostic Isense 1 K louto Vsense VsenseH VsENsE VSENSEH 0 Channel 1 P H L H diagnostic Isense 1 K loyri Vsense VseNseH Vsense VSENSEH 0 Tcuip sense VsENsE VsENsE TC H Vcc sense VsENsE VSENSE_VCC As indicated in Table 12 the Vsense_un failure flag is present on
46. Vouro I i l GPO i INI OUTO t B E ER I l i l ik Pama j wDiaNvo I Ge as sh I Boo 1 vsaNvo4 MEM T gd ng i 1 1 Ice GPO m Ssmo 1 ploy N lam u H I 1 cPo Lo sau out 4 O I f Pag Var wDiavvos M E po Museo Cap i i Ek onsen Fd Posse Fg i I i I Fg I l Fg ty I Fg i 1 I I Test set up contemplates driving through a microcontroller of HSDs and LSDs The latter can be set with adjustable switching times via different input series resistors OMNIFET II In this way it is possible to measure the sensitivity to shoot through of the HSD according to decreasing LSD input resistances this means increasing switching slopes A 4 5 O resistance is supplied by turning HS 0 and LS 1 on and LS 1 is submitted to a 100Hz PWM So the shoot through relevant critical element is HS 1 driven OFF Result is that in this case the shoot through is eliminated with slopes below 5 V us The shoot through mechanism is a limitation factor of PWM frequency of H Bridge with Standard MO 7 HSDs frequently used in case of speed control of DC Motors can be up to 30 kHz because at each period an extra power dissipation due to the cross current is summed up to the existing continuous and switching losses of each element Therefore the frequency of MO 7 HSD should be carefully evaluated In Table 33 a summary of the Ly DoclD028098 Rev 1 UM1922 Usage in H Bridge configurations maximum switching slopes measure
47. Vsen SEn RIO venae 19k Vago SELO a GND 15k apio L SELL uC Vse REN OUT1 out Vos n 45k Vos 22nF x ADC Multisense GND GND 470pF Rsense P Venn GND GND Dgnd Y Rgnd 4 7k GND GND GND GAPG1121131238MS Out 5 W bulb Out 0 1 5 W bulb DoclD028098 Rev 1 4 UM1922 Reverse battery protection Table 2 Reverse battery voltages on pins VND7040AJ Pin voltages V VND7xxxAJ Pin voltages V microcontroller Voc 16 Vpp 0 4 VER 9 7 VER uc 0 7 Vino 10 ViINo_uC 0 7 Vint 10 ViN1 uc 0 7 VsEn 10 VsEn uc 0 7 VSELo 10 VSELo_uc 0 7 VSEL1 10 VSEL1_uC 0 7 Ves 15 3 Vos uc 0 7 Vouro 15 3 Vouri 15 3 VaND 15 4 GND voltage on device is dropping to the reverse battery voltage plus the forward voltage of the integrated Vcc to GND clamping circuit Voltage on MultiSense pin is dropping to the reverse battery voltage plus the forward voltage across the internal ESD protection diode The maximum allowed DC output current on MultiSense pin Isense in reverse battery conditions is limited to 20 mA Therefore the Sense Resistor Rsense must be chosen accordingly For generic Rgense dimensioning rules please refer to Chapter 7 MultiSense analogue current sense Due to the clamping voltage of the integrated ESD protection diodes on logic pins FaultRST IN SEL SE the voltage on those pins is dropping to 10 V about Therefore a serial r
48. analogue current sense 4 Table 27 Diagnostics overview continued Fault condition Power limitation or over temperature Latch mode Signal Value ViN L H FR H H VSENSE 0v VSENSEH Current sense delay response time from rising edge of IN pin must be considered tDSENSE2H trip time to PowerLimitation Overtemperature Notes shutdown whatever is longer Output latched off after the first intervention of power limitation or thermal shutdown Can be unlatched by a low level pulse on the FR pin rPULsE gt TLATCH_RST MAVENS See Figure 112 sampling Figure 108 Open load without pull up timings Vin Vsense ov K tpsENsE2H GAPG1512141628CFT Figure 109 Open load with pull up timings VSENSEH VsENsE 3 tpsTKON tpsENsE2H GAPG1512141643CFT DoclD028098 Rev 1 141 196 MultiSense analogue current sense UM1922 7 2 12 142 196 Figure 110 Short circuit to Vgarr timings Vin Vout gt Vor VSENSEH Nominal psENSE2H psTKON GAPG1512141644CFT Figure 111 Power limitation or overtemperature waveforms in autorestart mode lLimH lout L LI LSA VSENSEH GAPG1512141625CFT Figure 112 Power limitation or overtemperature waveforms in lacth mode vw fC lLimH lout Latched off VSENSEH
49. and behaves like a power diode between source and drain pins The power losses of an N channel MOSFET for a reverse battery protection are determined by the Rps on of the device and the load current The device is able to withstand an abrupt high load current value typical of an application where several HSDs are activated simultaneously and loads like motors or bulbs can have a transient current above the devices DC Current maximum rating The diagram reported in Figure 15 gives information about the safe operating area as well as the maximum pulsed drain current the device is able to manage during normal operation The usage of VN5ROOSH E for reverse polarity protection is not recommended when the system must be compliant to ISO 7637 2 2011 E pulse 1 test level IV In this case in fact it is needed that the pulse does not discharge through the HSD and the conducting VN5R003H E device as this might be destructive for the HSD The VNROO3H E is robust against ISO 7637 2 2004 rev E pulses in the configuration with IN pin grounded through a resistance R gt 5 Q DocID028098 Rev 1 Ly UM1922 Reverse battery protection Figure 15 Maximum current versus duration time of VN5RO03H E 350 Tj start 25 C 300 44 250 200 Imax A 150 100 50 0 Let a ae a mm 0 00 0 25 0 50 0 75 1 00 1 25 1 50 1 75 2 00 2 25 2 50 2 75 3 00 t pulse s Note PCB FRA area 58 mm x 58 mm PCB thickness 2 m
50. at 100 Hz 2 mH 5 5 Q VND7040AJ Average power Measure value status 5 00 Vidiv 0 00 V offset a P1 rise C3 P2 fall C3 P3 duty C1 P4 fall C2 P5 P6 4 6977637 ms 6 4002246 ms RE Ed 100 mVidiv 5 00 Vidiv 1 00 A div 301 00 mV 5 00 offset 3 000 A ofst top 20 MS s Edge 1 00 MS ZOOM Energy dissipated in the diode 1 3mJ Measure value status 5 00 Vidiv 0 00 offset E P1 rise C3 4 6928906 ms ES 100 mVidiv 5 00 Vidiv 301 0 mV 5 00 V offset P2fall C3 2 2000860 ms P3 duty C1 base 3 00 ms dg 1 00 ms div Stop 1 00MS 100 MSisfEdge GAPG1127131702MS P4fall C2 P5 P6 Repetitive operation PWM 80 96 at 400 Hz the demagnetization time is longer than the PWM off state time see Figure 80 DoclD028098 Rev 1 4 UM1922 Load compatibility Figure 80 PWM 80 at 400 Hz 2 mH 5 5 VND7040AJ Measure P1 rise C3 P2fall C3 P3 duty C1 P4 fall C2 P5 P6 value 1 9026405 ms 598 6943 us status R FR 5 00 Vidiv 100 mV div 5 00 Vidiv 1 00 A div 0 00 offset 301 0 mV 5 00 offset 3 000 A ofst r A E a n n a n a Energy dissipated in ithe diode 0 6mJ 1 Measure P1 rise C3 P2fall C3 P3 duty C1 P4fall C2 P5 P6 value 241 8388 us 630 6237 us status m 5 00 Vidiv 1
51. consider is test pulse 2a at level IV 50 V during 50 us This voltage is considered on top of the nominal supply voltage of 13 5 V so the total voltage is 63 5 V The MO 7 HSDs have a clamping voltage VcLAMP 7 46 V typical In case of a typical device the remaining voltage is 63 5 V 46V 0 7 V 16 8 V The ISO pulse generator output impedance is 2 O With this the resulting peak current through the diode is 8 4 A for duration of 50 us The most severe negative ISO 7637 2 2004 E pulse we have to consider is test pulse 1 at level IV 100 V at 1 ms This pulse is directly transferred to the GND pin via the internal clamping So the maximum peak reverse voltage of the diode should be at least 100 V In case ISO 7637 2 2011 E pulse 1 test level IV compliance is required the maximum peak reverse voltage of the diode should be at least 150 V The Diode will work in avalanche mode if the pulse level is above the rated reverse voltage Conclusion The dimensioning the GND diode must fulfill the following e Maximum peak forward current 8 4 A for 50 us for ISO 7637 2 2004 E e Maximum reverse voltage 100 V for ISO 7637 2 2004 E resp 150 V for ISO 7637 2 2011 E As seen from above explanation the HSD with a diode protection at the GND pin doesn t clamp negative ISO pulses on the supply line Therefore an appropriate serial protection resistor should be used between microcontroller and HSD typically 15 kQ The resistor value s
52. current of the gate In addition the resistor R2 together with the gate capacitance of the P channel MOSFET determines the turn off time when exposed to fast negative transients or abrupt reverse polarity according to LV 124 2009 10 standard 1 kO as demonstrated by the experiment reported below appears to be a good compromise between minimizing the charging discharging current and ensuring a fast turn off time Due to the fact that the P channel MOSFET will carry also the load current it needs to be a lower ohmic component compared to an N channel reverse polarity protection MOSFET in the GND line In consequence it will have a higher gate capacitance hence longer turn off times for identical gate resistance R2 Ly DoclD028098 Rev 1 29 196 Reverse battery protection UM1922 Vegar V Measured values VND7020AJ Table 4 Static reverse battery voltages on pins Reverse battery Vgar 16 V 16 02 Normal operation standby mode 14 02 Normal operation outO on out1 off 14 00 Normal operation outO on outi on 13 98 Vcc IV Va o1 V 0 0 14 02 0 13 99 0 13 97 0 Ine HA 0 0 0 0 30 196 Table 4 reports the measurement results on VND70204AJ test vehicle according to the schematic in Figure 11 Vcc voltage on device is completely decoupled from the reverse battery voltage No negative voltage is present on MultiSense and on logi
53. cycle limitations for diagnostic in ON state can arise Considering the spread of time delay between Input switched and current sense output signal specified in datasheet by TpEseNseEon there is a minimum required ON time for which diagnostic is possible 4 DoclD028098 Rev 1 UM1922 MultiSense analogue current sense Minimum duty cycle calculation Figure 99 Minimum ON time for correct Vsense sampling Minimum ON time Vsense il Sampling Input control C_i L 4 Vsense rel TpsENsEH MIN TbsENsEH MAX psENSEL MIN iIpsENsELL MAX tpSENSE2H 250 us maximum datasheet value tON MINIMUM tpsENSE2H 250 us Considering PWM frequency 200 Hz Tpgniop 1 200 Hz 5 ms Duty cycle corresponding to ton minimum 100 250 5000 5 Result At PWM frequency 200 Hz minimum duty cycle is 5 for valid Vsense diagnostic Minimum operating current Distinguishing between open load and minimum load is possible without calibration Taking reference values of VND7020AJ datasheet minimum Ko 1020 at specified current of 10 mA considered as maximum failure current gives maximum 0 01A loL SENSE MAX 1020 9 8uA For output current of 0 1 A considered as detectable load Isense the minimum and maximum sense current can be calculated as follows l OUT 0 1 i 19uA SENSE_MIN KLED MAX 5100 l OUT 0 1A l gt 55uA SENSE_MAX KLED MIN 1800 Results
54. dE 3 939 2 196 3 30 Ly DoclD028098 Rev 1 149 196 MultiSense analogue current sense UM1922 7 3 2 150 196 Figure 120 Vcc monitor transfer function 4 5 4 3 5 3 gt 25 E 5 Vsense min 2 15 Vsense_typ 1 Vsense_max 0 5 0 0 5 10 15 20 VeclV GAPG0912141718CFT Applying limit cases of transfer coefficients show possible inaccuracy of Vcc monitoring The precision of MultiSense Vcc monitor can be improved with a calibration this means measuring an operating point of one device Vsense vcc for example calibration at 13 V and 25 C and by knowing the dependency of the Vsense vec With the device temperature to be able to read the Vcc value with maximum precision Experimental results show an average dVsegNse vcc DTcuip 70 uV K and an average relative error dVsENsE VCC VSENSE vcc DT cHip 4 5 uV V K in the range 40 C to 85 C i i Moreover the MultiSense signal in Vcc mode depends on the state of the channels experimental results show an increase for each channel turned on of about 8 mV Case temperature monitor Case temperature monitor is capable of providing information about actual device temperature Since diodes are used for temperature sensing the following equation describes the link between temperature and output Vsense level VseusE rc D Vseuse vc T 9 T TQ dVsENsE TC dT where dVsense Tc dT is the temperature c
55. driven complementary with a PWM signal and with different delay times between switching off of the HSD 0 and switching on of the LSD O0 in order to see the effect of the cross conduction and how it can be attenuated or eliminated a delay has to be introduced Let us quantify in this example the delay Current in HSD_0 is plotted Figure 158 VND7040AJ cross conduction with different OMNIFET delay times VND7040AJ r VND14NV04 VND14NV04 GAPG1128131044MS In the left side plot of Figure 159 a delay of 20 us only is given on the right side a delay of 100 us is given and still it is possible to see a residual cross current Ly DoclD028098 Rev 1 187 196 Usage in H Bridge configurations UM1922 Figure 159 VND7140AJ cross conduction with different OMNIFET delay times g 9 D D H VBAT TEL T WI IT yjvouro na VOUTO a IOUTO_H LS 1 VND7140AJ f s M 4 Veat N HS 0 iL HS 1 HAYBAT PWM Ioaea ON f ee 2A VOUTL louro Hy iloi 1j VOU T O sivit aPIOUTO H alts 1 a is 1 LS 0 Bk L ig 4 S52 PW orr We ELM VNS3NV04 I VNS3NV04 o 5 s Stetisti J ara 5S ANION PEREN ee E T ee E D ae i PP Pp P 20us lt as 5mm gt GAPG1129131045MS 188 196 In Figure 159 same conditions are applied to one VND7140AJ in combination with two VNS3NVO0AP E and driving a 13 Q resistan
56. example in case of a DC motor driven in H Bridge configuration see Figure 149 or because accidentally the Outputs are wired to the battery see Figure 149 or moreover in case of ripples induced by a disturbance sources for instance ISO pulses on battery which could create transient voltages on Output Power Stage Figure 147 Inverse current injected by a capacitive load INVERSE Multisense Rsense Rgnd A Pon Capacitor 4 DoclD028098 Rev 1 UM1922 Inverse output current behavior Figure 148 Inverse Current injected by an inductive load in the high side driver of an H Bridge e A HSA ON HSB OFF L p lt INVERSE dt BN lforward Vbatt P N LSA OFR LSB ON OFF ZN lt oo T Figure 149 Inverse current Injected by a short circuit to battery A N N EN EJ T Vbatt EE Vbatt INVERSE m x OUT We define linverse the current that flows into the device from the output Generally the conditions above described could become permanent in case of output short circuit to battery creating an extra stress on the solid switch 9 2 Device capability versus inverse current Considering a generic multichannel high side driver in case of inverse current disturbance injected into output
57. identified as reported below 1 Device sensitivity of channels permanently ON for dynamic inverse output current Device state all channels in ON state Inputs high and loaded Test execution Increasing Inverse Current is injected in a channel the ChUT up to the linvERSE th 2 Device sensitivity of channels permanently OFF for dynamic inverse output current Device state all channels in OFF state with all channels loaded inputs low Test execution Increasing Inverse Current is injected in a channel up to the linveRse th 3 Device sensitivity of channels either permanently ON or OFF for dynamic inverse output current while ChUT state is opposite to the one of the adjacent channel i Channel ch i set in OFF state while other Channel ch j is in ON state and loaded ii Channel ch i set in ON state while other Channel ch j is in OFF state and loaded Table 29 Example of channels configuration on a dual channels HSD Channels mcs Test ID canngurayen ChUT status Signals monitored Chi Chj 1 ON ON 3 i OFF ON Enable 3 ii ON OFF 2 OFF OFF CurrentSense Chi Vout anddiagnostic Vcc TcAsE 1 ON ON flag feedback feedback 3 i OFF ON Disable 3 ii ON OFF 2 OFF OFF 174 196 4 DoclD028098 Rev 1 UM1922 Inverse output current behavior This analysis results are reported in Table 33 Test conditions Vgar 12 V and room temperature values in the table are representative of
58. increase and if the gate voltage reaches the PowerMOS threshold a consequent turn on of the HS 1 takes place As this event occurs the HS 1 and LS 1 conduct for a limited time simultaneously creating a cross conduction event in this case called also shoot through DoclD028098 Rev 1 189 196 Usage in H Bridge configurations UM1922 190 196 Figure 161 PowerMOS capacitance effect during high dVps dt e e l l jCgd h nm f NC Y Cds F7 r 1 JCC vs Ore 7X LL Se ow I T L I l Cgs Rgl gt I __ I I 14 n e e A practical example follows in which see Figure 162 a test set up with two VND14NV04 OMNIFET II family and one VND7020AJ connected in H Bridge configuration is aimed to reproduce the shoot through Figure 162 Test set up for H Bridge cross current 3 eed ui Oscilloscope t t Cha Ch2 Cha Cha oio as STZ Motherboard x quee m MACH P eie m eim m cm m c m m de e im atm m m m Pa sj f MOZ Daunhterboard J 35 L I Vreg 14 l nd Ge i i Iva 100rF l l I Ye GND I xL I l I l VNDZox S Fg ceo l FaWRST l l l I GPO LS INO I i s ton Sie bod nce I I E
59. inductor will have little impedance a shunt At faster rise times higher frequency bandwidth an inductor will have greater impedance a block As a result transient suppression components must be carefully selected for the optimal operating conditions The actual performance of the component in the application will depend on the frequency based characteristics of the component and the board layout DoclD028098 Rev 1 37 196 Protection against battery transients UM1922 3 5 1 38 196 Resistors Series resistance between two nodes can provide inexpensive and effective transient protection blocking or limiting transients with frequency independent resistance Resistance can be used to create low pass filters and to decouple power domains Series resistance is primarily suited to protecting digital or analog signals that carry low currents and can accept a modest voltage drop across the series resistance Capacitors Capacitors are used in a variety of transient protection roles They can be used to filter the high frequency pulses produced by an ESD event They also provide switching current to ICs and serve as energy storage bins that limit voltage variation In either role the capacitor can be used to effectively shunt fast transients of limited energy such as ESD Important characteristics to consider when selecting capacitors are the maximum DC voltage rating parasitic inductance parasitic resistance and over voltage
60. is protected disconnected during reverse battery condition or negative ISO pulse In normal operation conditions it behaves like a standard freewheeling diode connected in parallel with load By using a standard silicon diode the demagnetization voltage is reduced from 32 V a typical VpemaG Of MO 7 device at Vgar 14 V to approximately 1 V depending on forward voltage of the diode and the voltage drop on the MOSFET This has an influence to the DoclD028098 Rev 1 103 196 Load compatibility UM1922 104 196 demagnetization time lowering Vpemacl increasing Tpemac as can be derived from the TpgyAg equation Component selection e MOSFET Q1 According to ISO pulse requirements see reverse battery protection chapter Drain current pulsed lpp Ioy gt Load current e Diode Dr Peak repetitive reverse voltage Var Varm gt 52 V must not conduct during positive transient on the output limited by the Vcc cNp Clamp Vcr AMP max 52 V Noncrepetitive peak forward surge current lesy Iggy gt Load current This parameter must be aligned with TpgwAG Average rectified forward current IF ay Igy gt Average clamp current in repetitive operation Limited by max junction temperature Experimental verification of described clamping circuitry Check the freewheeling operation at different conditions different duty cycle in repetitive operation negative ISO pulse loss of Vcc e Vpgar
61. load Vesar Y LeCroy Won Ross a Measure P1 risegotv C1 value 38 28400 us status v i P2fall h C1 P3 duty C1 5 00 Virdiv 20 0 psidiv Pa fall C2 P PB LUT econ lout C3 Turn OFFf 4 15W i eu C4 i Pout ag i id Poe Loss VV BAT our OUT Wout F4 Woy Foss d t Measure value status E Pt rise lwitl i P2fall h C1 41 72500 us P3 duty C1 5 00 Virdiv 20 0 psidiv Pafall C2 p5re PB GAPG1129131048MS As seen from the measurement in this case the switching shapes are not absolutely symmetrical so the turn off loss is slightly higher 531 uJ turn off versus 417 uJ turn on Measured values are slightly below the calculated value 569 uJ Another measurement example shows switching shapes and losses of VNQ7040AY on channel 0 configured in bulb mode Vpat 16 V Temperature 25 C resistive load 5 20 DoclD028098 Rev 1 Ly UM1922 Load compatibility Figure 53 Example of switching losses on VNQ7040AY with 5 2 O resistive load P3 ICT F4fall020 c m Pies 28450167 ya 12410400 us Woy l Fross zd E value 252413338 et 00 x 30892 ps GAPG1212140915CFT Switching losses LED clusters The switching losses evaluation in combination with LED loads is a much more complex task compared with resist
62. of turn on phase and nominal load current is considered at the beginning of turn off phase Assuming Tpemac gt gt tworp the switching losses can be estimated as follows Turn on energy loss J Won 0 Turn off energy loss J Wogr 3x higher versus pure resistive load The factor 3 is the result of experiment see Table 21 and Table 22 In PWM operation or at turn on with a small delay after the last turn off there is a possibility that the turn on event comes before the end of the demagnetization phase if the PWM off state time is shorter that the load demagnetization time TpgyAG gt Tpwm opp This means that turn on phase is starting while the current is still forced via the freewheeling diode This makes the turn on switching loss significant if compared with the case of zero starting current As a rough estimation a 3x higher value can be considered versus equivalent resistive load This way of the operation is frequently used on purpose i e for the load current regulation by PWM duty cycle see Figure 63 DoclD028098 Rev 1 85 196 Load compatibility UM1922 Figure 63 Switching losses high inductance ext freewheeling PWM operation Tpemac gt tworr ext clamp Tpemac gt Teww orF Vear V Teww orr IN MO 7 HSD Load current continues AN via external freewheeling V Vnom j i 0 Pioss 7 CLAMP 2 L Freewheeling P MAX diode A Renp V Deno
63. on Vaar L 100nF S0V 100nF 50V i Ji 15k Multisense Multisense 15k bL 470pF ATOpF A uc I O GAPG1128131013MS Direct connection of SE pins is not safe in the following cases e Loss of GND connection If the GND connection of one device is lost positive as well as negative ISO pulses on the associated supply line are not clamped anymore considering no other devices connected to this supply line If the transient voltage is big enough to activate a parasitic NPN bipolar structure of one SE pin and the clamp structure of second SE pin there could be unlimited current flow between both supply lines through SE pins same mechanism as already described in case of monolithic devices This current could lead to malfunction or even failure of one or both of the HSDs The parasitic current path is shown graphically on Figure 125 In order to avoid such failures it is recommended to add a 15 KO resistor in series to each SE pin in the same way as already described in case of monolithic devices see previous chapter In principle the same applies to all other logic input pins as well since the clamp structure is
64. periods Figure 35 provides the detail of one diagnostic period CurrentSense on channel 0 rises to Vsenseu failure flag as soon as the channel enters in power limitation Thanks to the blanking pulse the channel is able to turn on the bulb correctly in autorestart mode CurrentSense on channel 1 and channel 3 report open load failures CurrentSense on channel 2 indicates the channel is latched off due to a power limitation or overtemperature event Figure 36 shows the effect of the regular unlatch pulse on the shorted channel 2 as long as its input is kept high After elapse of thatcy rst the channel is turning on into the short circuit and latching off again as soon as AT sp dynamic temperature threshold power limitation is reached This fast device intervention protects the device and the system including connectors and wire harness from short circuit stress induced degradation For details regarding device endurance in short circuit conditions refer to the relevant AEC Q100 012 characterization reports DoclD028098 Rev 1 55 196 Usage handling of fault reset and standby UM1922 56 196 Figure 35 FaultRST pin handling example detail of diagnostic period a m 49 Coupling BW Limit Invert Probe GAPG1122131130MS Figure 36 FaultRST pin handling example detail of unlatch pulse Ch 2 a J a D SEN 0 rae qe GAPG1122131131MS
65. settings and sampling at the ADC TcasE Vcc device dependent Devices containing full logic implementation have the possibility to monitor device case temperature and battery voltage please for knowing the list of devices containing or not the full logic consult Table 14 In this case MultiSense output operates in voltage mode and output level is referred to device GND For monolithic devices where reverse battery protection circuitry is used on device GND pin voltage offset is created relative to real GND potential This offset must be considered during measurement on microcontroller side Following picture shows the link between VygAsungp and real Vsense signal a DoclD028098 Rev 1 UM1922 MultiSense analogue current sense Figure 119 GND voltage shift Multisense voltage mode VsENsEH Vcc monitor Tease monitor SELO SEL1 Multisense GND TouC ADC SENSE V MEASURED 7 3 1 Vcc monitor Battery monitoring channel provides Vsense Voc 4 Without calibration of voltage analogue feedback accuracy limited precision of Voc monitoring can be applied Considering limit values of VND7020AJ datasheet and in case all channels are deactivated IN 0 V 3 16 S OB SENSE_VCC_MIN TRANSFER COEFFICIENT MAX TRANSFER COEFFICIENT MAX 358 4 114 4 2 1 and similar V 3 30 B O O SENSE VCC MIN TRANSFER COEFFICIENT MIX TRANSFER COEFFICIENT MIX
66. show that differentiation between open load of 10 mA and minimum load current of 100 mA is possible without calibration Ly DoclD028098 Rev 1 129 196 MultiSense analogue current sense UM1922 Diagnostics with different load options In some cases the requirement profile asks for alternative loads driven with one and the same high side driver This could be a bulb lamp with the alternative of an LED cluster In this case the driver e Has to handle the high inrush current of the bulb load e Has to provide a power dissipation low enough during continuous operation e Must not indicate an open load in case of an LED cluster is applied instead of a bulb In case of different load options Bulb LED there is the possibility to use two different switch able sense resistors in order to have the current sense band in the appropriate range matching the different load currents An example of a current sense resistor switching circuit can be seen in the Figure 100 The measured scale can be extended by Rsgysg switched in parallel to Rgenses by MOSFET Q1 Figure 100 Switched current sense resistor example 100nF 50V Multisense Rsense1 Rsense 2 Q1 GND GND GND 10nF 100 V 7 A4 GND GND GND GND 7 2 9 Diagnostic with paralleled loads partial load detection Table 24 Paralleling bulbs overview on the example of VND7020AJ
67. torr us DEMAG z calculated freewheeling freewheeling Ratio vs Ratio vs 10 90 of 90 10 of LIHA Rio py res load py res load Vout Vout at 0 6V ps 300 13 5 65 0 47 315 2 01 34 37 74 1 000 13 5 162 1 17 450 2 87 33 38 246 3 500 13 5 302 2 17 490 3 12 32 37 861 5 400 13 5 360 2 59 505 3 22 31 36 1328 20 000 13 5 398 2 86 490 3 12 31 35 4919 Note Used inductors 1 5 uH 5 4 mH Air coil 1 5 mm cable 20 mH Iron powder core inductor Isar 3 A The coil resistance compensated by adding a serial resistor to reach 13 5 Q in total Switching losses capacitive loads This chapter deals with the switching losses in combination with capacitive loads A typical application example is the usage of the HSD as a supply voltage switch for other modules see Figure 68 Figure 68 A typical example of HSD combined with capacitive load Veat MO 7 HSD Supplied module s Clamp Vos lout Switchable supply line OUT V Reno OUT Dann A capacitive character of the load creates an inrush current during turn on phase depending mainly on the load capacitance switching time and the load resistance i e capacitor ESR A typical requirement for the HSD in such applications is ability to handle the worst case inrush current without activation of the protection mechanisms power limitation or thermal shutdown to ensure cor
68. us 209 mired 10 0 peak t 1 i HW F ed tj i i Measure ONinseamd LOSE luct P4T2NC2 e PB Measure P1nsaghwCT PIINE P3dutct P4TaNC2 E Pee vatue 16 758a0ckis zw n A GAPG1127130951MS Measured losses Won 6 9 uJ Wore 8 5 uJ Contribution to total average power dissipation Won Worr 69uJ 858J _ 34 w 9L CRUST EOS 2 Bite SW Tow 200Hz Example 2 Switching losses measurement This example shows the switching losses measurement on VND7140AJ with LED cluster example 2 VW Passat B6 tail amp brake light using an oscilloscope with mathematical functions The first function F1 shows the actual power dissipation on the HSD VBar Vout lout the second function F4 shows the HSD energy integral of F1 Conditions e Vpar 16V e Temperature 23 C e PWM 200 Hz 70 e load VW Passat B6 Tail amp Brake see Figure 55 e Device VND7140AJ Ly DoclD028098 Rev 1 79 196 Load compatibility UM1922 80 196 Figure 57 Slew rate and switching losses VND7140AJ VW Passat B6 tail amp brake LeCroy Vour lour Fass a t Prg Pact GAPG1127130952MS Measured losses Won 26 uJ Wore 17 uJ Contribution to total average power dissipation Won W ON OFF _ OuJ 7 fut 8 6mW Pa id TPwM 200Hz Switching losses inductive loads A typical characteristic of inductive loads is the tendency to maintain the direction and value of
69. when driving bulbs is the inrush current generated when starting up a cold filament A properly selected driver should allow the safe turn on of the bulb without any restrictions under normal conditions Under worst case conditions the driver should still be able to turn on the bulb even if some protection of the driver may be triggered temporarily However the drivers long term integrity should not be jeopardized Typical combinations of bulbs and MO 7 devices Roy classes are shown in the following Table 20 Table 20 Typical bulb loads for given MO 7 Roy class Device Rpson class mO Suggested bulb types and combinations in the given 1 2 and 3 conditions 2 x H1 2 x 55 W 2 x H4 2 x 55 W 60 W 2 x H7 2 x 55 W 2 x H9 2 x 65 W 1 55 W H4 55 W 60 W 7 55 W H9 65 W H1 55 W H4 55 W 60 W 7 55 W H9 65 W x P27 W R5 W 1 55 W 4 55 W 60 W 7 55 W 9 65W b5 W 4 55 W 60 W 7 55 W ei 65 W 20 2xP21W 2x P27 W 2x P21W R5W 2x P27 W RSW 30 2x P21 W R5W 2 x P27 W 40 P21 W R5 W P27 W R5 W DoclD028098 Rev 1 65 196 Load compatibility UM1922 Table 20 Typical bulb loads for given MO 7 Roy class continued Device Rpsoy class mQ Suggested bulb types and combinations in the given 7 2 and 3 conditions P21W s P27 W 2xR5W me R10 Ww 1 Condition 3 applied to VNQ7050Av is fulfilled with TcAsg
70. 0 0 mv 60 00 ofst 4 000 A ofst 500kS 1 0GSisfEdge Negative GAPG1127131705MS Conclusion The circuitry behavior is the expected one After loss of Vcc or negative ISO transient most of the demagnetization energy is submitted to the reverse battery protection MOSFET and supply line capacitor The energy dissipated in the device is relatively low since the channels are most of the time turned on the device GND pin pulled negative via freewheeling diode below the logic pins 6 3 6 Loss of Vcc The loss of supply voltage e g due to blown fuse intermittent contact on ECU connector etc in combination with inductive load on HSD output can lead to huge negative voltage peak on all device pins assuming the load without external freewheeling The aim of this paragraph is to complement the theoretical explanations of different cases of loss of Vcc with experimental verifications The device used is the VND7020AJ Monolithic device with GND network When the Vcc disconnection occurs during the on state the load inductance tends to continue to drive the current via any available path by reversing its voltage acts as a source until the stored energy E Pn 12 is dissipated Therefore the lowest voltage potential is seen on the OUT pin which is forced in negative by the inductance see Figure 83 Ly DoclD028098 Rev 1 109 196 Load compatibility UM1922 Figure 83 Loss of Vcc with inductive load monolithic Vear
71. 0 14 Q 1000 uF 35V ESR 0 03 Q 2200 pF 25 V ESR 0 035 Q 4700 uF 35 V ESR 0 020 Q Electrolytic aluminum Experimental results done on a sample of each mentioned device have highlighted that no protection is triggered for value of capacitance below the ones indicated in Table 23 Figure 69 Measurement example VND7040AJ on 320uF c4 Pout 153 13600 us status alue a 5 00 Vidiv 5 00 Vidiv 10 0 Adiy 100 Widiv 10 0 muidi 2 500 V ofst 0 mV offset 10 100A 100 psidiv 100 psid 15 952 V 16 038 VI 106 bd O OWl gt s 19910m Table 23 Maximum capacitance on the HSD output no power limitation triggered Tistart 25 C Measure P1 risegnlv C3 P2fall lv C3 P3 duty C1 P4fall C2 y a P5 P6 imebase 200 s Trigger 100 us div Stop 1 84 250kKS 250 MS s Edge Positive X1 601 052 ps GAPG1127131002MS Experimentally F Slew rate Part number determined maximum ii dVou1 dt ee Rois i ed capacitance pF V us y gin app VND7140AJ 76 22422422410 6 05 0 11 47 VND7040AJ 320 1004 220 19 9 0 084 220 VND7020AJ 1220 1000 220 44 7 0 039 820 VN7016AJ 2200 80 0 031 1500 VN7004AH E 4700 357 0 008 3300 Ly DoclD028098 Rev 1 93 196 Load compatibility UM1922 94 196 Switching losses Xenon Since there are several different types of the Xenon modules Lamps there is probably no general way for the switching
72. 0 Hz 2 mH 5 5 O VND7040AJ 0 0002 0 107 ISO pulse 1 100 V 10 Q 2 mH at 5 5 Q VND7040AJ 0 00000 0000 108 Loss of Vcc 2 mH 5 5 Q VND7040AJ 2 I 109 Loss of Vcc with inductive load monolithic llle 110 Test setup loss of Voc monolithic llle 113 Loss of Vcc VCND7020AJ 1 mH 3 5 Q 100 nF 22 eee 114 Loss of Vcc VND7020AJ 1 mH 3 5 Q 100 nF 222 pF 115 Loss of Vcc VND7020AJ 1 mH 3 5 Q 100 nF 100 uF iis 116 MO 7 driver with analogue current sense block diagram 200 eae 117 Structure of MultiSense signal generation liliis 118 Vsense Saturation example sssssseee en 120 Plotted VSENSE with increasing IOUT versus time with RSENSE 220 O left and RSENSE 470 Q right for VND7040AJ and corresponding XY plot Voc 14 V 121 DoclD028098 Rev 1 Ly UM1922 List of figures Figure 92 Figure 93 Figure 94 Figure 95 Figure 96 Figure 97 Figure 98 Figure 99 Figure 100 Figure 101 Figure 102 Figure 103 Figure 104 Figure 105 Figure 106 Figure 107 Figure 108 Figure 109 Figure 110 Figure 111 Figure 112 Figure 113 Figure 114 Figure 115 Figure 116 Figure 117 Figure 118 Figure 119 Figure 120 Figure 121 Figure 122 Figure 123 Figure 124 Figure 125 Figure 126 Figure 127 Figure 128 Figure 129 Figure 130 Figure 131 Figure 132 Figure 133 Figu
73. 00 mV by the increased supply current Ison so that the standby mode will be activated again after tp stpy As a result we could see short negative peaks on the GND pin with period of tp srgy during the whole demagnetization phase These peaks are not long enough to activate the HSD output which means the device works safely even without the GND resistor However this resistor is still needed in order to suppress the described parasitic oscillations if TpEMAG gt tp STBY The ground network can be safely shared amongst several different high side drivers provided they are supplied from the same supply rail Sharing the ground network is even possible among different HSDs when they are supplied from different supply rails In this case however special precautionary measures must be applied for details refer to Section 8 3 Paralleling of GND protection network The presence of the ground network will produce a shift 600 mV in the input threshold This shift will not vary if more than one HSD share the same diode resistor The diode at the GND terminal allows the high side driver to clamp positive ISO pulses above 46 V the typical clamping voltage of the HSD Negative ISO pulses still pass GND and logic terminals The diode should withstand clamped ISO currents in case of positive ISO pulses and reverse voltages in case of negative ISO pulses Dimensioning of the GND diode The most severe positive ISO 7637 2 2004 E pulse we have to
74. 00 mV div 5 00 Vidiv 1 00 A div 0 00 offset 301 0 mV 5 00 offset 3 000 A ofst GAPG1127131703MS Negative ISO pulse exposure on Vgc line DoclD028098 Rev 1 107 196 Load compatibility UM1922 Figure 81 ISO pulse 1 100 V 10 O 2 mH at 5 5 O VND7040AJ 9056 100V Measure P1 rise C3 P2fall C3 P3 duty C1 P4fall C2 P5 P6 value 934 29 ns status A v 20 0 Vidiv 200 20 0 Vidiv 2 00 A div 40 00 V ofst 60 00 V ofst 2 000 A ofst Vbat I ZOOM c3 i i j i Load demagnetizatio completed gt I gt Reverse current forced via the output Discharging of the gate oHhe MOSFET Delay time t3 elapsed negative i pulse generated ry Measure P1 rise C3 P2fall C3 P3 duty C1 P4ffall C2 P5 P6 value 49 31371 us status E 0 0 p 1 00MS 5 Edge Ne 20 0 Vidiv puni 20 0 Vidiv 40 00 V ofst 200 0 mv 60 00 V ofst GAPG1127131704MS 108 196 DoclD028098 Rev 1 4 UM1922 Load compatibility Figure 82 Loss of Vcc 2 MH 5 5 Q VND7040AJ Discharging of the Am gate of the MOSFET Output turned on GND pin pulled below the logic input MOSFET in avalanche 120V Measure P1 rise C3 P2 fall C3 P3 duty C1 P4fall C2 P5 P6 value 24 0756 us 5 0490 us status v v imebase 200us 20 0 V div 200 mV div 20 0 Vidiv ERUUEIRII ERATES Stop 48V 40 00 V ofst 40
75. 13 kO 130 V 10 mA an input series resistor R 15 kO can be considered a reasonable value DoclD028098 Rev 1 43 196 Protection against battery transients UM1922 3 6 2 44 196 The recommended application schematic guarantees device operation according to the below classes standard ISO7637 2 edition 2004 and 2011 as shown in the table below e SOnt1 2 ms 10 Q 5K pulses Class C must be complied full operational after each pulse e ISO n2a 50 us 2 Q 5K pulses Class C must be complied full operational after each pulse e ISO n3a 0 1 us 50 Q 1h Class B must be complied full operational even during pulses exposure e ISO n3b 0 1 us 50 Q 1h Class B must be complied full operational even during pulses exposure Figure 23 Basic test setup for ISO 7637 2 2004 pulses applied to VN7004AH E ISO generator 10nF TF 130 To simulate 2 65W bulbs No network is needed on GND pin GAPG1112141434CFT Dimensioning of the GND network to pass the ISO n 1 and 2a level IV 2011 edition As already mentioned to pass the ISO n 1 150 V and 2a 112 V pulses a dedicated GND network must be used The suggested basic solution is represented by a resistance R1 between device GND and module GND 4 DoclD028098 Rev 1 UM1922 Protection against battery transients Figure 24 Recommended GND network for ISO 7637 2 2011 level IV Device GND Needed for quad
76. 14000 us 64 65682 us status ks v 10 0 Vidiv 10 0 Vidiv 100 mA div 2 00 Widiv 1 00 mJ div 500 usidiv Stop 5 6V 20 000 Y 10 000 v 0 00 mA ofst 500 usidi 500 us div 1 00MS 200 MS s Edge Negative X1 1 576485 ms 13 327 Vit 11 050 Ed EET 4 17 majt 3 5712 mJ GAPG1127131007MS The demagnetization energy dissipated in the HSD was measured by an oscilloscope with mathematical functions The first function F1 shows the actual power dissipation on the HSD Vegar Vout lout the second function F4 shows the HSD energy integral of F1 As seen from the oscillogram measured values are close to the theoretical calculation Eusp 3 6 mJ 4 04 mJ calculated Tpemag 1 2 ms 1 12 ms calculated 6 3 4 Selection criterion with reference to l L plot Even if the device is internally protected against break down during the demagnetization phase the energy capability has to be taken into account during the design of the application Ly DoclD028098 Rev 1 99 196 Load compatibility UM1922 100 196 It is possible to identify two main mechanisms that can lead to the device failure e The temperature during the demagnetization rises quickly depending on the inductance and the uneven energy distribution on the power surface can cause the presence of a hot spot causing the device failure with a single shot e Like in a normal operation the life time of the device is affected by the fast thermal variation as described by the Coffin Man
77. 154A 49 DoclD028098 Rev 1 137 196 MultiSense analogue current sense UM1922 Figure 105 Analogue HSD open load detection in off state nw Vbat A Vbat 100nF 50V SE 100nF 10k GND GND Microcontroller Voo Voc 7 External 1 Pull Up e us r OUT OUTPUT gt V Multisense Rsense2 1OnF 100V a In the following plots delay times for the OL detection in off state vs settings of INx and SE are shown The relevant delay times tpstkon and tp yo are given in the datasheets Figure 106 Open load short to Vcc detection in OFF state delay after IN is set from low to high Vin l1 T Pull up connected Vsense Pullup OPEN LOAD ull up disconne V SENSE 0 VSENSE tbsTKON SHORT TO Vcc GAPG1128130909MS 4 138 196 DoclD028098 Rev 1 UM1922 MultiSense analogue current sense Figure 107 Open load short to Vcc detection in OFF state delay after SE is set from low to high Vsen Pull up conne ted B VsENsEH OPEN LOAD Pull up discorjnefted 3 VsENSE V SENSE xU VsENSE SHORT TO Vcc GAPG1128131000MS Table 26 MultiSense pin levels in off state Condition Pull up MultiSense SE 0 L Yes 7 F ENSEH Open load 0 L No 0 H 0 L Yes 7 B ENSEH Short t
78. 2 64 196 Figure 41 Hybrid devices separate power supply rails common MultiSense v 1 GND SELO 2 SEn 2 SEn 1 SELO SEL1 15k NC SEL2 GPIO Lx control cpio 7 FaultRST Gio A control Gpo 7 INx control cpio 7 15k _ V FaNRST INO SEn Multisense GND 100nF 50V OUTO Il 100nF 50V e 6 FaultRST INO INT NC Ne 15k m Ins NC po 15k NUT up OUTO OUT1 SEn OUT2 SELO SEL1 SEL2 OUT3 Multisense AID 1 T 3 gs Reuse Truth table shows signals mapping rl Table 19 Truth table hybrid devices separate supply rails common MultiSense SEn U1 SEn U2 A D MultiSense L L Hi Z MultiSense N A H L Current Sense U1 VN7004AH E L L L L H Current Sense ChO L L H L H Current Sense Ch1 L H L L H Current Sense Ch2 gt Lg der L H H L H Current Sense Ch3 az o eo H L L L H Tcu Sense 27g S Zz H L H L H Voc Sense gt H H L L H TCHIP Sense H H H L H Voc Sense X X X H H Hazard states DoclD028098 Rev 1 a UM1922 Load compatibility 6 Load compatibility 6 1 Bulbs This chapter is intended to suggest drivers that can be used for typical automotive bulb loads or typical combinations of bulbs A major consideration
79. 37 2 2011 E pulse 1 transients In order to limit the current in this experiment a 90 O generator resistor was chosen As long as the N channel MOSFET is still conducting during the negative pulse the voltage on Vcc pin Vpar is clamped to minus one diode voltage due to the forward biased substrate diode of the HSD The N channel MOSFET is turned off once the GND voltage begins to drop This happens within a few microseconds The first current spike is due to the recharging of the Voc DoclD028098 Rev 1 27 196 Reverse battery protection UM1922 2 2 4 28 196 capacitor As soon as the GND voltage drops to 100 V the N channel MOSFET starts to conduct in avalanche until the pulse amplitude drops below its breakdown voltage BVpss 100 V The breakdown voltage BVpss of the N channel MOSFET either should be higher than the maximum negative transient peak voltage of ISO 7637 2 2011 E or the energy capability of the N channel MOSFET in avalanche must be high enough to sustain the transient pulse energy Figure 10 Reverse battery test VN7016AJ 13 5 V 4 V 82 mO R2 15 kO as per LV 124 2009 10 standard Vat LeCroy 1 R2 15k VCC GND stress 0 1mJ a Measure P1ffall C2 P2fall C2 P3 duty C1 P4fall C2 P5 P amp value 7 40935 us status v 5 00 Vidiv 5 00 Vidiv 5 00 Vidiv 5 00 Adiy 10 0 us div Stop 55V D mV offset 0 mV offset 5 100 V EJ 5 000 A ofst 500kS 5 0GS sfEdge Negative Figur
80. 5 0 0 68 0 82 1 12 15 18 22 27 33 3 9 Rsense kOhm GAPG2111141459CFT Figure 97 MultiSense in Vcc mode behavior versus Rsense for VND7140AJ at Vcc 14 V and Tc 25 C 3 Isense_Vcc mA Vsense_Vcc V 0 68 082 1 12 15 18 22 27 33 39 Rsense kOhm GAPG2111141503CFT An example about Rsense value definition is shown Example 3 Let s consider the VN7016AJ 16 mQ HSD with a nominal load current ly 5 A which corresponds to an intended Vsense 2 V and typical Ko 3750 from datasheet Let us apply above Equation 8 V SENSE 3750 2 1 5kQ OUT Let us suppose that the maximum load current the ADC has to monitor in linearity is 2 times the nominal current so to say 10 A at Vgensemax 4 V So this means that neither VsENsE sat Nor Isense sat must be reached and in fault conditions a voltage above 5 V must be issued Let us verify that Rgense value chosen is the correct one by applying above Rsense K DoclD028098 Rev 1 Ly UM1922 MultiSense analogue current sense Equation 9 and Equation 10 V SENSE SAT MIN 5 loUT MAN VSENSEMAN 4V HSENSECq o E ma T e SENSE sar MN 4mA B VsENSE H min 5V _ zii SENSE 7ma ISENSE H min MA So the chosen sense resistor of 1 5 kQ is correct 7 2 7 Usage when multiplexing several devices If several devices are supposed to sh
81. 5 10 15 20 25 30 VeclV GAPG1128131805MS Ly DoclD028098 Rev 1 121 196 MultiSense analogue current sense UM1922 Note 7 2 4 7 2 5 122 196 Figure 93 Behavior of Isense sat VS Voc Isense_sar function 12 4 11 4 10 9 4 z 8 E 7 6 8 5 84 3 2 1 0 T T 1 0 5 10 15 20 Vcc V GAPG1128131806MS The Isense sat decreases significantly for Vcc below about 10 V Above this battery level we can consider as minimum value of Isense sar 5 2 V instead of the minimum of Isense sat 4 MA given in the datasheets at Voc 7 V This increases the upper load current range that can be monitored by the current sensing avoiding any saturation The MultiSense current monitoring linear behavior is featured down to a Voc 4 5 V and for Vsense lt Vcc 1 5 V even though relevant specification limits reported in datasheets are not guaranteed anymore Impact of the output voltage to the MultiSense output The current sense operation for load current approaching the current limitation is not guaranteed and predictable Indeed because of the intervention of the current limiter the output voltage can drop significantly up to approximately 0 V in the extreme case of a hard short circuit Being the whole circuit referred to Vout ambiguous and unreliable current values could be sourced by the MultiSense under such conditions In order to bring the MultiS
82. 6 ESD protection EMC requirements for ESD at module level An Electrostatic Discharge ESD pulse on any ECU connector pin is an expected event during the life of a car A transfer of discharge when a person approaches the ECU for example during maintenance reparation or installation is a typical event that could damage the ECU and in particular an IC whose pins are connected to the outside environment Standards and limits are applied in order to simulate those events but they strongly depend on the car maker specification and on the application Some international standards for testing schemes and requirements have been introduced for the electrical systems such as car modules They include IEC 61000 4 2 and the automotive standard ISO 10605 The two standards use different values for the C R components IEC 61000 4 2 uses a 330 O resistor and a 150 pF capacitor ISO 10605 uses a 2000 O resistor but different capacitances depending on condition A 150 pF capacitor is used to simulate a person reaching into an automobile for example a module loads repair or change can be reproduced by this standard A 330 pF capacitor is used to simulate ESD events for a person sitting in the passenger compartment in a vehicle Such ESD pulses are made by two components a capacitive and a resistive one the first one made by a pure peak current in the first nanoseconds of the pulse strongly depends on the distributed capacitance of the ESD simulator body
83. 66 Simulation result normal condition 0 00 eee eens 67 Simulation result cold Condition 0 tenes 68 Simulation result hot condition 0 0 0 00 68 Control stage current consumption in ON state all channels on driving nominal load datasheet value lasse ke We ee ee ee ee le Ra dor For RU ee 69 Steady state condition datasheet values lour 3 A Ron at 150 C 2 44 MQ 70 RON dependency on temperature measured on a VND7140AJ sample 71 RON dependency on VCC measured on a VND7140AJ sample 04 71 RON dependency on IOUT measured on a VND7140AJ sample 72 Switching and conduction losses resistive loads 00 000 cece eee eee 74 Example of switching losses on VND7040AJ with 4 50 resistive load 76 Example of switching losses on VNQ7040AY with 5 2 Q resistive load 77 LED cluster example 1 LED test board 6 x 3 LEDs OSRAM LA E67 4 77 LED cluster example 2 tail amp brake light VW Passat B6 0 004 78 Slew rate and switching losses VND7140AJ LED test board 02 4 79 Slew rate and switching losses VND7140AJ VW Passat B6 tail amp brake 80 Switching losses with low inductance 0 cece ete eens 81 Low inductance TDEMAG lt lt tworr measurement example 82 Switching losses with high inductance 00 c cence eee ees 83 High in
84. 8 1 9 300 13 5 69 0 50 x 382 2 43 x 321 2 04 x 34 35 9 5 1 000 13 5 54 0 39 x 785 5 00 x 438 2 79 X 33 36 32 3 500 13 5 52 0 37 x 2 370 15 1 x 492 3 13 x 31 36 111 5 400 13 5 50 0 36 x 3 470 22 1 x 487 3 10 x 31 36 171 20000 13 5 11 0 08 x 13630 86 82x 533 3 39 x 30 36 633 The Table 22 describes the PWM operation with high duty cycle shortest possible PWM off time adjusted to have complete turn off on phase The measurement was done with external freewheeling only Schottky diode In the last column there is a calculation of demagnetization time considering Vpemac 0 6 V Vpar 16 V PWM 94 at 500 Hz 120 us off time shortest possible for complete turn off on phase Table 22 VND7040AJ measurement of switching losses versus L in PWM mode with external freewheeling Won Worr T Load with external with external ton us torr us calculate d freewheeling freewheeling Ratio vs Ratio vs 10 90 of 90 10 of L uH RIO pJ res load uJ res load Vout Vout at 0 6V us 1 5 13 5 139 1 00 157 1 00 35 39 0 0 15 13 5 130 0 94 173 1 10 35 38 4 60 13 5 118 0 85 205 1 31 35 38 15 90 196 DoclD028098 Rev 1 Ly UM1922 Load compatibility Table 22 VND7040AJ measurement of switching losses versus L in PWM mode with external freewheeling continued Won Worr T Load with external with external ton us
85. 922 Load compatibility 114 196 Figure 85 Loss of Vcc VND7020AJ 1 mH 3 5 100 nF I LeCroy i Cvcc 100nF lout Veonp 150V GND diode in avala 12 FI Vec Vgnd x I Measure P1 rise2080 C1 P2 freq C1 P3 P4 value 17 67533 us status P5 PB Timebase 101 us ESTIS ETHER 500kS 1 0GS s Edge Negative GAPG1127131708MS R 50 0 Vidiv 50 0 Vidiv 50 0 Vidiv 2 00 A div 10 0 Vidiv 150 00 V 150 00 V 100 00 V 4 000 A ofst 50 0 psidi Most of the demagnetization energy Figure 85 is absorbed by the GND network diode in avalanche mode The voltage peak on the Vcc and GND pin is 150 V equal to break down voltage of the diode The device channel stays on for whole demagnetization phase 30 us A positive overshoot on Vcc is seen at the end of demagnetization phase due to the resonance between the Vcc capacitor and load inductance DoclD028098 Rev 1 UM1922 Load compatibility Figure 86 Loss of Vcc VND7020AJ 1 mH 3 5 100 nF 2 2 pF LeCroy Cyce 100nF 2 2uF Vbat F F F 1 ca par Vand C3 Vol lout C4 i V CC Q UV i Lf Vcc Vgrd Eu i bas FA i i i i i i Measure P1 rise2080 C1 P2 freq C1 P3 P4 P5 PB value 76 77250 us status R Trigger m 20 0 Vidiv 20 0 Vidiv 20 0 Vidiv 2 00 Adiy 10 0 Vidiv 200 ps div Normal 1 8 Y 40 00 V ofst 40 00 V ofst 20 00 V ofst 4 000 A ofst 200 us di LAEE EP E Nega
86. Above the Jump Start requirement 27 V for 60 s Above the Load Dump requirement 36 V for 400 ms e Energy capability Must be compatible with standard ISO pulses 1 2a 3a 3b Must be able to withstand the demagnetization energy Peak power dissipation see calculation below Discharge time see calculation below Peak power dissipation on suppressor Pp Vc lo Discharge demagnetization time Tpremag E nf Me where x lo Load current at Vcc disconnection VoL Clamping voltage of the suppressor device R Load resistance Example of suppressor selection for given application conditions e Load inductance L 2 1 mH e Load current Ilp 4A e Load resistance R 3 50 e Negative clamping voltage requirement Vc lt 60 V Peak power dissipation Pp Voy l 60 4 240W Discharge demagnetization time L Your R lg 0 001 60 3 5 4 gin Merlo zi 9 33 4 TpEMAG R Vou 50 J 60us Bidirectional automotive TRANSIL SM4T39CAY E SMA package selected e Peak pulse power rating 400 W 10 1000 us OK 240 W at 60 us required e Max clamping voltage 53 3 V at 7 5 A OK Vcul lt l 60 V required e Min breakdown voltage 36 7 V at 1 mA OK compatible with load dump e Compatibility with ISO pulses OK ISO pulse 1 2a 3a 3b specified in datasheet DoclD028098 Rev 1 Ly UM1922 Load compatibility Mea al a E E E E O 5 Ch1 Ch 2 Ch3 Ch4 9 9 9 9 g g Q
87. Ake R 75 N LP M Y lload NS LSA LSB gt F 5 m i Using the nomenclature above the switches HSA and LSA or HSB and LSB should never be closed at the same time as this would cause a short circuit on the input voltage source This condition creates the so called cross current A simpler configuration called Half Bridge consists of a single high side driver which opens or closes the load towards the battery the loads itself which is directly grounded and a low side driver in parallel to the load normally inductive which is activated only to connect the load to ground The low side driver in this way absorbs the inductive energy which otherwise would be completely discharged through the high side driver with a consequent possible damage in case the energy exceeds its capability In case of a DC motor the low side driver when turned on after having turned the high side driver off brakes the motor safely to ground and stops it Finally more than two Half Bridges can be connected together in order to drive at least two different loads in cascaded configurations see in Figure 157 an example of an automobile front door system with a total of five motors The independent activation and diagnostic reading of each switch gives large flexibility in those configurations DoclD028098 Rev 1 185 196 Usage in H Bridge configurations UM1922 Figure 157 Example of automob
88. C ILimH 77A RdsOn 14mQ Rin 1mQ Rout 10mQ VN7016AJ Device 2cm PSO16 120 4 d lou A Vout V TIC 100 80 60 40 20 0 i i 0 00 0 01 0 02 0 03 0 04 0 05 Time s GAPG1122131142MS Hot condition Vepat 16V xz TCASE 105 C TBULB 25 C A Requirement thermal shutdown is allowed for a duration below 20 ms autorestart mode considered Figure 45 Simulation result hot condition Vbattz16V Tamb 105 C ILimH 77A RdsOn 14mQ Rin 1mQ Rout 10mQ VN7016AJ Device 2cm PSO16 T T lout A TICC Vout V 0 01 0 02 0 03 Time s DoclD028098 Rev 1 GAPG1122131143MS 4 UM1922 Load compatibility Note 6 2 Conclusion The device is able to turn on a H4 bulb 60 W under specified conditions 7 Normal condition 2 Cold condition and 3 Hot condition without triggering the device protection functions Power Limitation Thermal shutdown The mentioned simulation example only refers to the inrush current at turn on of a cold bulb Still the steady state power dissipation and in case of PWM is applied the additional switching losses of the driver have to be considered in order not to exceed the maximum possible power dissipation This obviously becomes more important with a larger number of channels per package i e dual or quad channel drivers and high power loads applied to mor
89. Ds or hybrid HSDs and supply line configuration either the same or separate supply lines for each HSD Direct paralleling of logic pins is generally an allowed operation in case of devices designed in the same technology monolithic or hybrid supplied from one supply line In all other cases like combination of monolithic with hybrid technology different supply lines we should use additional components to ensure a safe operation under conditions in automotive environment ISO pulses reverse battery The clamp structure of all logic input is similar except for a slight difference on FaultRST pin therefore all the explanations related to the paralleling of SE pins are applicable also to paralleling of other logic input pins including the FaultRST pin Monolithic HSDs supplied from different supply lines Paralleling of SE pins of monolithic HSDs is possible however some precautions in schematic should be applied if the HSDs are supplied from different supply lines In this case the direct connection of SE pins as shown in Figure 123 is not safe Figure 123 Direct connection of SE pins not recommended L 100nF 50V Negative ISO pulse on Vaari 100nF 50V
90. Hat20 e External freewheeling diode STPS2H100 e Device VN7004AH E Figure 65 Figure 62 High inductance TpgyAg gt tworr measurement example 2 2 i giicay 7 i piroy VBAT i T Mm trit Pt i a eS Vout P VN7004AH at 1mH 20 A 130W eterni freewheeling Ay M M Pross Vaar Vour lour i de Xie 2 9080 we ct P CLS Thay Measured losses 1 mH at 2 Q Woy 0 04 mJ Worp 1 75 mJ GAPG1212141202CFT Ly DoclD028098 Rev 1 87 196 Load compatibility UM1922 88 196 Measurement example 3 High inductance with external freewheeling PWM operation Conditions e Vpar 16 V e Temperature 23 C e Load 20 mH at 13 5 Q e External freewheeling diode STPS2H100 e Device VND7040AJ e PWM 80 at 500 Hz Figure 66 High inductance Tpemac gt Tpwm orr measurement example Ybat LeCroy re rn er e a VND7040AJ at 20mH 13 50 o oo RM external freewheeling a ad M 16 13W i i i i Pioss Vat Vout lout x I i i Measure P1 rise C3 P2fall C3 P3 max C1 P4 P5 PB5 value 162V status Trigger 89 100Vidw 50 0 mVidiv 10 0 Vidiv 500 m div 10 0 Widi Eme E 20000v 1 00 mv ofst 14 600 V EXT 500 usidi 4 00MS 200 MSis Ec E Taray E Tu Eswon Press t gt j y 463uJ j S Y Xie 58484015 B p5ee Ph Measure Pinse c3 P253 P3masict
91. I V curve check e previous points are repeated till failure if any Devices performances are guaranteed by margin to failure reported during characterization The test is performed on specific ESD test boards where general ESD layout rules are applied Ly DoclD028098 Rev 1 UM1922 ESD protection The ESD characterization has demonstrated the capability of MO 7 HSDs to pass the ESD levels normally required Following results are reported Table 32 M0 7 HSDs ESD results ESD at module level powered ESD at module level unpowered Sustained ESD pulse level gt 8 KV gt 8 KV 10 2 EMC Requirements for ESD at device level ESD tests for electrical components such as integrated circuits include e Human Body Model HBM e Charged Device Model CDM Those ESD test methods for integrated circuits are intended to insure that the circuits can be safely handled in an ESD controlled environment during manufacture HBM It is intended to simulate a charged person touching an integrated circuit A person has approximately 100 pF of capacitance and skin and body resistance limit the current during a discharge HBM tests results according to JEDEC 22A 114F and CDM AEC Q100 011 are reported in MO 7 datasheets Absolute Maximum Ratings CDM This test CDM AEC Q100 011 emulates an integrated circuit which becomes charged and discharges when it touches a grounded metal surface There is no fixed va
92. MultiSense pin of a latched channel x if the following conditions are met e MultiSense is enabled SE High e The channel x is driven on through its input INx High e The multiplexed MultiSense is mapped to channel x through appropriate SELx pin settings Note Off state diagnostic is provided on the MultiSense if INx Low 4 DoclD028098 Rev 1 49 196 Usage handling of fault reset and standby UM1922 All latched channels can be restarted by setting the FaultRST pin low for a duration corresponding to the maximum t_atcH_rst this parameter is given in the datasheet A graphical explanation of the latch off functionality can be seen in Figure 26 Figure 27 and Figure 28 Figure 26 Latch functionality behavior in hard short circuit condition Tjunction lt lt Trsp High Logic Sense Enable Logic High High Input Logic Fault Reset t limy Output Current 60 e in rus Junction Temperature lt lt Trsp Logic Internal High 8 Fault Detection Ed Output Circuit Vout lt 5V Vout lt 5V Voltage Vsense Multisense Voltage Figure 27 Latch functionality behavior in hard short circuit condition Tr lt Tjunction lt Trsp Logic a High 2 Sense Enable Logic ae High Input Logic High s a t gt tlatchpsy Fault Reset e V t
93. NSE SAT MIN 4MA In Figure 91 a measurement of MultiSense of VND7040AJ is given Two different low Rsense values are connected to the MultiSense pin and relevant linearity range of Vsense versus louT is highlighted In the measured sample the ISENSE SAT VsENSE RsENSE is about 5 4 mA corresponding to a maximum monitorable current of about 13 A DoclD028098 Rev 1 Ly UM1922 MultiSense analogue current sense Figure 91 Plotted Vsense with increasing Ioyz versus time with Rsense 220 Q left and Rsense 470 Q right for VND7040AJ and corresponding XY plot Vcc 14 V PLIM starts 7ms Vsense 500mV div Vsense 500mV div 0 gt n GAPG1127131804MS Note VsENsE sat and Isense sar minimum values are guaranteed for the minimum Vcc voltage in which all K factor limits are guaranteed in datasheets this is 7 V and maximum operating junction temperature in datasheets this is 150 C which represent worst case conditions in the assessment of the maximum load current to be monitored Experimental Measurements on samples have In Figure 92 and Figure 93 plots extracted from experimental data at 25 C are shown for VsENsE sar and lsgwse sar respectively The Voltages in the plots refer to module GND so they include the voltage drop on GND network of about 300 mV Figure 92 Behavior of Vsense sat VS Vcc Vsewse sAr function BR VsewsE satlV 0
94. Powe vatue 173020001 6 0404GQ us astes en value 1332 MUN T550800us 10055220587 mJ 9 stans B 1 Er MET ws Xie 308100 ws BASRA w 1 69mJ GAPG1212141509CFT Measured losses 1 mH at 2 Q Won 0 44 mJ Wore 1 69 mJ DoclD028098 Rev 1 89 196 Load compatibility UM1922 Measurement example switching losses versus L VND7040Av In order to get a better idea about the switching losses dependency on the value of the inductance a comparative measurement with different load inductances was performed on VND7040AJ The summary of this measurement is shown in the tables below The Table 21 describes the steady state operation single turn on off event with or without an external freewheeling diode For each load inductance there is a measurement of switching losses and switching times time between 10 90 of nominal Voyy considered All switching losses are compared versus the resistive load In the last column there is a calculation of demagnetization time considering Vpemac 28 V Vpat 16 V Single turn on lj gAp 0 single turn off lj oap nominal 1 2 A Table 21 VND7040AJ measurement of switching losses versus L in steady state OFF t T Load Won Worr with external ton ps Inl caleulate d freewheeling aaa a a 1 5 13 5 139 1 00 x 157 1 00 x 157 1 00 x 35 39 0 0 15 13 5 130 0 94 x 173 1 10 x 173 1 10 x 35 38 0 5 60 13 5 116 0 83 x 204 1 30 x 204 1 30 x 35 3
95. Truth table for monolithic devices common MultiSense N A Hi Z A D MultiSense Current Sense Tcuip Sense N A I ES Fe a r DoclD028098 Rev 1 Voc Sense MultiSense U1 VN7020AJ Current Sense ChO Current Sense Ch1 TcuiP Sense Voc Sense MultiSense U2 VND7020AJ 61 196 Usage and handling of MultiSense SEL pin UM1922 62 196 Table 17 Truth table for monolithic devices common MultiSense continued SEL SEL SEL SEn_U1 SEn U2 SEn_U3 A D MultiSense L L L L L Current Sense ChO L L H L L Current Sense Ch1 L H L L L H Current Sense Ch2 ELM T L H H L L Current Sense Ch3 3 o 3 7 AAR H L L L L Hi Z E 9 H L H L L Hi Z gt H H L L L Tcuip Sense H H H L iL Voc Sense x X X Other combinations of SE Hazard states Example 3 e VN7020AJ VND7020AJ VNQ7140AJ e Separate power supply lines common GND network e Common MultiSense Separate SE control Topology of control part SEn SEL 5 is similar to Example 2 The main difference consists of using separate power supply lines on HSDs Due to this fact recommendations of paralleling SEL signals are implemented as well as MultiSense input described in Chapter 8 Paralleling of devices e MultiSense monitor is using diode in series to on MultiSense outputs e Each HSD c
96. V Ving 5 V Be dnA active louTo 3 A louTi 3A The next description is divided into 2 sub chapters e Conduction losses steady state losses during the ON state e Switching losses losses during switching phases DoclD028098 Rev 1 69 196 Load compatibility UM1922 6 2 1 70 196 Conduction losses The conduction losses are given by the power dissipation of the MOSFET switch due to the ON state resistance Ron ON state power dissipation W 2 Pon Ron OUT ON state energy loss J Wron Pon ton where ton ON state duration Example 2 For VND7020AJ Figure 47 Steady state condition datasheet values lour 3 A Ron at 150 C 44 mQ lout 3 A Tj225 C lout 3 A T 150 C lout 3 A Voc 24V Tj 25 C ON state resistance Pon Roy our 44mQ 3A 396mW The Roy parameter depends mainly on temperature see measurement on Figure 48 This should be taken into account during the calculations In most cases it is not necessary to consider the dependency on Vcc or lour The Ron is almost independent of Vcc down to 4 V see Figure 49 and almost independent of louT for a Drain Source voltage range above the output voltage drop limitation given in the datasheet as Von 20 mV typical see Figure 49 3 DoclD028098 Rev 1 UM1922 Load compatibility Figure 48 Roy dependency on temperature measured on a VND7140AJ sample 250
97. after PCB production by SW modification inside microcontroller Ly DoclD028098 Rev 1 127 196 MultiSense analogue current sense UM1922 Figure 98 Bulb LED diagnostic example Vee Outputs ON OFF control 15k Veo 15k iu Load type Bulb LED not known during layout N1 15k OUTO mL 10nF 100V 10nF 100V Analogue diagnostic control 15k SEn 15k SELO outs 15k t3 SEL1 15k SEL2 t3 IN2 15k Analogue feedback signal GPIO GPIO GPIO GPIO OUT1 Outputs BULB LED mode Ch 0 1 15k GPIO GPIO LEDO 15k E OUT2 GPIO GPIO GPIO GPIO Multisense GND Only one load type connected after production 4K7 128 196 Diagnostic in OFF state Considering diagnostic of LED loads it can appear specific situation during diagnostic in OFF state While pull up resistor is applied during OFF state diagnostic allowing distinguish between output short to Vcc and open load current flowing through pull up resistor can create unintended LED light emission To prevent such a situation external circuitry inside the LED load or a pull down structure on device level is needed to create sufficient load for detection without side effect of LED lightning Without external circuitry on LED loads diagnostic in off state is not recommended Diagnostic in ON state Since LED loads are usually driven by PWM signal at low duty
98. after exposure to disturbance and cannot be returned to proper operation without replacing the device 1 The results on pulse ISO7637 2 2011 2a level IV depend mainly on load status and condition open load nominal load shorted load resistive load inductive load capacitive load Lower ohmic loads with low inductive contribution help to increase the sustainable peak voltage for the device reaching Class C compliance Tests performed on VND7020AJ for example give as result class C in the condition ON state with a resistive load equivalent to the nominal one on each output see Figure 20 instead they give class E with Outputs in open load 3 6 Moreover MO 7 Monolithic HSDs pass the load dump clamped pulse test class C according to Table 7 criteria relevant to the standard ISO 7637 2 2004 E bb pulse with 40 V centralized load dump suppressor as well as the standard ISO 16750 2 2010 E pulse with 35 V centralized load dump suppressor Component dimensioning for hybrid devices Differently from monolithic devices the Hybrids do not need the external reverse battery protection network since they have an embedded protection formed by an anti parallel Zener diode which prevents the signal clamp activation refer to Figure 5 Moreover the reverse battery event enables the self turn on of output channels For this reason during the ISO transients the parasitic structures of I O pins are softly triggered with no high current flowing thr
99. age a MultiSense diagnostic bus DoclD028098 Rev 1 11 196 General items UM1922 1 2 Application schematics monolithic devices Figure 1 Typical application schematics monolithic devices 5V 3 3V Vbat Vbat switched 21 Vbo cs d 100nF OUT i Vcc e G OUT FR e e R1 15k IN j R2 15k OUT pre P gt I H e SEn e Rpull_up E 10k lt eur R3 15k SEL R4 15k OUT eo e A ADC in Multisense A lr L4 e GND Cig Rsense 4 ADC in Ld ins R6 15k Dgnd w Rgnd Es e ext GND GAPG1121131236MS 12 196 DoclD028098 Rev 1 4 UM1922 General items 1 3 Application schematics hybrid devices Figure 2 Typical application schematics hybrid devices 5V13 3V Vbat Vbat switched fo C1 Von T 100nF C5 L T 100nF OUT OUT FR R1 IN e R2 OUT
100. ages higher than the Zener voltage and limits the charging discharging current of the gate In addition the resistor R2 together with the gate capacitance of the N channel MOSFET determines the turn off time when exposed to fast negative transients or abrupt reverse polarity according to the LV 124 2009 10 standard 15 kO as demonstrated by the experiment reported below appears to be a good compromise between minimizing the charging discharging current and ensuring a fast turn off time A capacitor might be placed between Gate and Source of the N channel MOSFET The RC filter composed by R2 and C can be dimensioned to be transparent against the fast negative pulses ISO 7637 2 2004 E pulse 1 test level IV keeping the reverse polarity protection circuitry switched on The usage of such capacitor C is not recommended when the system must be compliant to ISO 7637 2 2011 E pulse 1 test level IV In this case in fact it is needed that the pulse does not discharge through the HSD and the conducting N channel MOSFET as this might be destructive for the HSD Figure 9 MOSFET solution in GND experiment VND7020AJ ISOpulse 1 150V 90 Q 50007 B sov 1 y VBAT k za VGND l VG slbat N MOSFET in avalanche i ji Vcc capacitor recharging LIII Mode gt Couplin Noise Rej gt Holdoff ers icai Figure 9 shows the example of a 100 V 100 mQ N channel MOSFET in the schematics as for Figure 8 submitted to ISO 76
101. al and to protect devices in all previously described cases we can add a diode in series to each MultiSense pin in the same way as already described in case of monolithic devices see previous chapter Mix of monolithic and hybrid HSDs supplied from different supply lines Paralleling of MultiSense pins of monolithic and hybrid HSDs is possible however some precautions in schematic should be applied if the HSDs are supplied from different supply lines Direct connection of MultiSense pins as shown in the next picture is not safe DoclD028098 Rev 1 Ly UM1922 Paralleling of devices Figure 132 Direct connection of MultiSense pins not recommended Var ata jo a 100nF 50V 100nF 50V Voc U1 U2 Vee FR IN gt H L al e HA SEn p SEL OUT SENSE Multisense GND lt 15k L VsENsE Roo D 470pF 4k7 A om Resi influenced GAPG1128131019MS Direct connection of MultiSense pins is not safe in the following cases e Negative ISO pulse on Vgar2 e Loss of Vgat Or Vgaro e Loss of GND connection A negative voltage surge ISO7637 2 pulse 1 3a on Vento is directly coupled to the MultiSense pin through the internal Vcc MultiSense clamp structure If the negative
102. alues 10 uH or with external freewheeling Nevertheless this behavior does not impact the total power dissipation in the device or functionality in steady state conditions The load current sharing during the demagnetization phase is unstable see measurement with 2 mH 2 8 Q This leads to the conclusion that in the worst case total demagnetization energy could be dissipated in one channel only Therefore the energy capability of a single channel must be sufficient to sustain the whole demagnetization energy If this is not the case an external protection must be added refer to Section 6 3 Inductive loads The following measurement demonstrates the overload condition turn on into the short circuit on VND7020AJ device with paralleled outputs configured in latch mode e VBAT 14V e Temperature 25 C e Device VND7020AJ OUTO OUT1 paralleled e Short circuit parameters 5ygH 50 mQ coil from 1 5 mm cable 168 196 DoclD028098 Rev 1 Ly UM1922 Paralleling of devices Figure 145 Test setup inductive short circuit test with paralleled outputs Ch1 Ch 2 Ch3 Ch4 Q qj 4 DoclD028098 Rev 1 169 196 Paralleling of devices Figure 146 Inductive short 5 WH 50 mQ VND7020AJ ChO and Ch1 in parallel Latch mode As seen from the measureme
103. an ESD pulse has frequency content in the range of hundreds of MHz the capacitive value of a real capacitor is lower than the theoretical one The ESD pulse destruction value strongly depends on the module layout In order to make the module pass the required stress level it is recommended to add a ceramic capacitor to the output close to the connector whose value could be in the range of tens of nF This capacitor decreases both the applied voltage gradient and the maximum output voltage seen by the HSD 4 DoclD028098 Rev 1 UM1922 Usage in H Bridge configurations 11 Usage in H Bridge configurations 11 1 Introduction The term H Bridge refers to the typical graphical representation of such a circuit An H bridge is built with four switches solid state or mechanical Two of them are connected between the battery and the load high side switches the other two between the load and the ground low side switches When the switches HSA and LSB according to the Figure 156 where a basic circuit with tour MOSFETS driving a bidirectional DC motor is shown are closed and HSB and LSA are open a positive voltage will be applied across the motor By opening HSA and LSB switches and closing HSB and LSA switches this voltage is reversed allowing reverse operation of the load in most cases a DC Motor Figure 156 H Bridge scheme e A HSA HSB E UNE a Vload 4 Vde
104. are one Rgense resistor for proper diagnostic only one MultiSense of each device at a time should be activated All other devices sharing the Rsgwsg should apply the High Z state on MultiSense output SE L In this case Rgenge is supplied from one device at a time If by mistake more than one MultiSense is activated the MultiSense output in current mode will draw a current in the shunt resistor Rgense defined as Isense J sENSEIN where N is number of devices with enabled current output There must be considered the possibility of Vsenge saturation range of linear operation since current delivered from multiple devices increase voltage drops on Rgense In case one device is switched to voltage output due to fault condition diagnostic for other devices cannot be applied since Vsgwsgg is applied to Rsense 7 2 8 LED diagnostic VNQ7040AY device Quad channels contains a feature consisting in a switch able output mode selected through dedicated control pin LEDx according to the connected load Bulb LED Several output parameters are influenced according to the selected mode Bulb LED e K factor for current sense monitoring lii MH li ML as well as e QV dt slopes for rising and falling edges For applications where output type is not known in advance it is possible drive LED pin by microcontroller pin applying appropriate protection see relevant chapter Then output mode parameters can be adjusted even
105. ases extra test with a modified HBM network for example 150 pF 2 KO contact discharge are required Module powered during the test This test normally simulates any possible stress that could be applied to the connector pins with module already assembled in car The standard typically applied is the ISO10605 330 pF 2 KO Acceptance limits are in the 8 KV range contact discharge and 15 KV air discharge In some cases if higher pulse level is required the applied network changes in 150 pF 2 KQ Test execution requires a sequence of 3 5 ESD pulses applied with fixed delay time Real car battery must be used Module must be inserted in a test environment that simulates a car It is normally ESD tested in real configuration loads on load off driver in PWM Pulses are applied to the pins that go out of the module such as outputs transceivers pins Test is passed if no pin to pin I V characteristic degradation is reported after pulses exposure ESD pulses are applied between the pin under test and module ground connected to the ESD GND plane by a minimum wire It has been demonstrated some variability of the ESD Main causes of such variability are in general the environmental conditions humidity mainly the ESD simulator pulse spread specifically of the initial current pulse and the test execution as well The M07 HSDs are characterized with powered and unpowered module ESD tests In Figure 153the applica
106. asure capability of MO 7 Hybrid device in this case the VN7004AH E to sustain ISO7637 2 2011 pulses Figure 25 Basic Test setup for ISO 7637 2 2011 pulses applied to VN7004AH E ISO generator 13 5V m 9 xp 100nF r s i SV 15K D m 10nF TF sv L L 130 1K To simulate 2 65W bulbs GAPG1112141521CFT DocID028098 Rev 1 Ly UM1922 Protection against battery transients Operative conditions given for VN7004AH E are reported below e Device in OFF state and output in open load e Device in OFF state with OUTs in short circuit to GND e Device in ON state INO IN1 high and output in open load e Device in ON state INO IN1 high driving 1 3 Q resistive load on each OUT e Device in Limp Home state INO IN1 pulled up by 2 7 K Diode to Vcc and output in OL Results are reported in Table 9 Table 9 ISO 7637 2 levels and results for Hybrid HSDs ISO 7637 2 Test pulse 1 Level Ill 1 Level IV 2a Level Ill 2a Level IV 3a Level III 3a Level IV 3b Level Ill 3b Level IV 2004 Class C Class C Class C Class C Class B Class B Class B Class B 2011 Class C e Class C ue d 9i Class B Class B Class B Class B Class C full operational after each pulse Class B full operational even during pulses exposure Class E One or more functions of the device do not perform as designed after exposure to disturbance and cannot be r
107. battery supposing a static condition of Vcc 16 V is Vcc Vg 16V 07V z 7650 ISENSE_rev_max 20mA HsENSE 5 The above given Rgense 765 Q is suitable as well to protect the current sense circuit against pulse 1 up to level IV ISO 7637 2 E 2004 and 2011 In conclusion the Rgense value must fulfill two opposite conditions for having linearity in normal operating condition one is avoiding MultiSense pin current saturation increase Rsense and the other is avoiding MultiSense pin voltage saturation decrease of RsEwsE Moreover the Rgense value has to be dimensioned in order to distinguish a normal operating condition linear mode Vsgwsg proportional to load current from a Fault condition Constant Voltage Generator developing Vsense p across the Rsense In Chip Temperature and Vcc monitor mode the MultiSense is a voltage source with limited current but in this case the current saturation is higher than the Isense sar So linearity in Tcuip and Voc reading is respected with the minimum Rsense which fulfills the recommendation of point b In Figure 96 and Figure 97 experimental plots on a VND7140AJ are shown in typical conditions for the Tepp and Vcc monitor versus Rsense respectively DoclD028098 Rev 1 125 196 MultiSense analogue current sense UM1922 126 196 Figure 96 MultiSense in Tc jp mode behavior versus Rsense for VND7140AJ at 3 5 2 5 Vsense TC V 1 5 sense TC mA 0
108. body diode of Ve max 0 7 V the resulting power dissipation in the high side driver per output channel is Pp 0 7 V lj gAp Zthj a diagrams reported in HSD datasheets support the user to calculate the maximum affordable load current for a given PCB layout Note that the intrinsic diode between MultiSense pin and Vcc pin will be forward biased in reverse battery condition The current is limited by the external sense resistor A 1 kO sense resistor will dissipate 250 mW about For what concerns the GND path of the device the integrated Voc GND clamping protection which circuit behaves like a Zener diode will be forward biased in reverse battery condition The power dissipation in the GND resistor therefore is determined by Pp VBat rev 0 3 V Renp A 1 KQ GND resistor will dissipate 250 mW about The following figure provides an overview about the resulting voltage levels on pins ina typical application schematic during reverse battery condition Figure 3 Voltage levels during reverse battery diode resistor protection Vbat Vreg a uC Vpp 100nF M PEN REM DD GND ETUR VND7xxx Voc GND V 15k SENE GPIO nex Ver EagiRST 15k Gili ve Vino INO m 15k GPIO N1 uC Vit ina OUTO y OUTO 22nF V 15k amp cpio VSEn uc
109. c pins By reverse polarity the MOSFET will be switched off because the gate source voltage for this case will be positive Vas gt 0 voltage drop over the Zener diode and protects the HSD The same reverse polarity protection network can be shared among several HSD connected to the battery A capacitor might be placed between gate and source of the P channel MOSFET The RC filter composed by R2 and C can be dimensioned to be transparent against the fast negative pulses ISO 7637 2 2004 E pulse 1 test level IV keeping the reverse polarity protection circuitry switched ON The usage of such capacitor C is not recommended when the system must be compliant to ISO 7637 2 2011 E pulse 1 test level IV In this case in fact it is needed that the pulse does not discharge through the HSD and the conducting P channel MOSFET as this might be destructive for the HSD Figure 12 MOSFET solution in Vcc experiment VND7020AJ ISOpulse 1 100 V 90 Q 30 VG ay IBAT MOSFET in avalanche Gate capacitance discharging 11nF Normal DC Ed mi 60ns Figure 12 shows the example of a 55 V 16 mQ P channel MOSFET in the schematics as per Figure 11 submitted to ISO 7637 2 2004 E pulse 1 transients In order to limit the current in this experiment a 90 O generator resistor was chosen As long as the P channel Ly DoclD028098 Rev 1 UM1922 Reverse battery protection 2 2 5 MOSFET is still conducting durin
110. c terminal Conduction through protection concept Chapter Active passive GND terminal output stage p channel MOSFET 2 2 4 Active Voc No Reverse FET 22 9 Active Voc No 2 2 1 Schottky diode When the battery is installed backwards the Schottky diode is reverse biased and only the rated leakage current Ip flows With respect to a standard diode the Schottky diode has the advantage of a very low voltage drop in forward direction hence power dissipation is reduced However the disadvantage of using a Schottky diode is that it is typically more expensive than a standard diode Below reported there is the suggested procedure to choose properly the right device The following parameters will constitute the selection criteria e The average current used by the device electronic module load to be reverse battery protected Failure scenarios such as an output shorted to GND load short circuit have to be considered as well e The maximum repetitive peak reverses voltage Varn e The maximum ambient temperature Tamb The following inequality must apply in all cases Tamb Pi P lt Timax where 2 lF av maximum average forward current le RMs RMS forward current Rin thermal resistance Junction to ambient for the device and mounting in use rd small signal diode resistance V o are depending on the special characteristics of the diode One important thing to take into account is the peak reverse volta
111. ce At 20 us in this case the cross current spike is eliminated Similar considerations can be applied when the HSD must be switched on after the LSD is switched off but in this case the switching off times of the OMNIFET Il are much shorter than the switching times of the HSD so in this case the cross conduction shall not take place In order to avoid the cross conduction due to the mechanism explained before the low side drivers have to be driven with delay times named also dead times when for example in case of a DC motor it is requested to change direction in the rotation As general rule for Monolithic M0 7 HSD minimum dead time to be introduced in the low side driver is about 250 us In Figure 160 the same measurement is shown for one dual channel HSD VND7012AY and two LSD VNB35NV04 E driving a 1 84 Q resistance In this case a significant cross current spike is visible when the delay time between HSD deactivation and LSD activation is below 2 ms However the minimum required delay time to avoid any cross condition may be much longer depending on slew rate of the LSD can be adjusted by the input pin serial resistor value Experimental verification shows that with increased slew rate of LSD from 0 6 V us to 1 2 V us the cross conduction spike is visible up to the 5 ms delay time Therefore the minimum dead time must be determined case by case As general rule for hybrid MO 7 HSD minimum dead time to be introduced in the Low Si
112. cs of ISO 7637 2 editions 2004 and 2011 Table 5 ISO 7637 2 2004 E ISO Test levels Burst cycle pulse repetition time 7637 2 Number of Delay and 2004 E pulses or test im Sans Test I IV times Min Max P pulse 1 75 V 100 V 5000 pulses 0 5s 5s 2 ms 10 O 2a 37 V 50 V 5000 pulses 0 25 5s 50 us 20 3a 100 V 150 V 1h 90 ms 100 ms 0 1 us 50 Q 3b 75 V 100 V 1h 90 ms 100 ms 0 1 us 50 O 4 6 V 7 V 1 pulses 100 ms 0 01 Q 5b 65 V 87 V 1 pulses 400 ms 2 Q 36 196 DoclD028098 Rev 1 Ly UM1922 Protection against battery transients Table 6 ISO 7637 2 2011 E Test pulse severity level Burst cycle pulse repetition Test Selected U 3 4 Min number time puise i u of pulses or level IV Tm vil TEST UMES Min Max 1 150 V 112 V 75 500 pulses 0 5s 5 2a 112 V 55 V 37 500 pulses 0 2 s 5s 2b 10 V 10 V 10 10 pulses 0 5s 5s 3a 220 V 165 V 112 1h 90 ms 100 ms 3b 150 112 V 75 1h 90 ms 100 ms 1 Test pulse as in 5 6 paragraph of ISO 7637 2 2011 E see Appendix A References 2 Values agreed between vehicle manufacturer and equipment supplier 3 The amplitudes are the values of Us as defined for each test pulse in 5 6 paragraph of ISO 7637 2 2011 E see Appendix A References 4 The former levels and II are revised because they did ensure sufficient immunity in subsequent road vehicles design 5 The maximum pulse repetition time shall be chosen so tha
113. d on a typical sample which cause no shoot through in the given test set up for VND7020AJ VND7040AJ VND7140AJ and VND7012AY is shown Table 33 Maximum switching slopes which do not cause cross current due to MOSFETs capacitances measurements on a sample on each component Device Max slew rate of the low side switch no parasitic activation of the HSD VND7020AJ 5 V us 4 5 O load resistance VND7040AJ 8 V us 4 5 O load resistance VND7140AJ 14 V us 13 O load resistance VND7012AY 13 V us 1 84 O load resistance 11 2 3 Usage of MultiSense Tcp p in H Bridges The MultiSense chip temperature monitor can be used to aid the thermal management in case critical conditions are forecasted in the application This features of MO 7 HSDs can be applied to cyclic loads loads which are statically activated for a certain time and then switched off again for a certain number of times During prototyping of the application board in order to monitor the temperature of the package for a certain operating cycling profile for example 20 consecutive activations of a DC motor driving the opening closure of the car trunk the application engineer can evaluate if with given activation cycles the HSD does not reach a too high temperature 11 2 4 Freewheeling current of inductive loads The driving in PWM of inductive loads is a common technique to control the average load power according to application requirement acting as speed contr
114. de Driver is typically 2 ms DoclD028098 Rev 1 Ly UM1922 Usage in H Bridge configurations Figure 160 VND7012AY cross conduction with different OMNIFET delay times VBAT VOUT 1 VOUTO LS 1 3 BAT 2fVOUTL y VOUTO UA AY 0 0A Vo File Explorer Options Lang eT 3p VBAT 20 VOUTI yVoUTO LS 0 Tl Ne 49 Mein ORI NIS PRINS UNI SENE nnm ARARARAARARARA A o E nHS 1 g D HS 0 Fall 1 24 5u s D Source Measure Settings Clear Meas Statistics VOUTO Fall lt v wa v 200us 5 i 2 Source 4D Select Measure Settings Clear Meas Statistics VOUTO Fall Fall ba GAPG1612141159CFT Cross conduction due to MOSFETs capacitances Another event causing cross conduction is related to dynamical effects inside HSD and LSD and precisely to high voltage gradient which can occur across them Let us consider an H Bridge in which one of the two MOSFETs of one leg e g HS 1 is completely off and the LSD 1 is switched on Due to this the drain source voltage of HS 1 is submitted to a fast increase high dV dt and considering the simplified equivalent model of the MOSFET of the HS 1 represented in Figure 162 this gradient injects a current in the gate drain capacitance and the gate source capacitance The current component flowing on the Cos causes the gate voltage to
115. devices could be damaged e Loss of VBATI or VBAT2 A negative voltage surge ISO 7637 2 pulse 1 3a either on Vgat or Vpgaro is directly coupled to the MultiSense pin through the internal Vcc MultiSense clamp structure If the negative voltage on MultiSense line is big enough to activate the Vec MultiSense clamp DoclD028098 Rev 1 Ly UM1922 Paralleling of devices structure there could be an unlimited current flow through both MultiSense pins This current could lead to malfunction or even failure of one or both of the HSDs A positive voltage surge ISO7637 2 pulse 2a 3b either on Vgat or Vgaro together with missing Denp Denp not used Denp failure or GND pin disconnected can activate the Voc MultiSense clamp structure clamp voltage similar to Voc GND clamp As soon as this occurs there could be an unlimited current flow through both MultiSense pins This current could lead to malfunction or even failure of one or both of the HSDs Loss of either Vgart or Vgaro is leading to a wrong current sense signal If Varo is lost U2 and other components connected to Vgar2 is supplied by U1 current sense signal through the internal Vcc MultiSense clamp structure Therefore the voltage on MultiSense bus will drop to almost OV and we ll have no valid Vsense reading anymore In order to protect the devices during ISO pulses and to ensure valid current sense signal as well we can add a diode in series to each MultiSense
116. ductance TDEMAG gt gt tworr measurement example Ls 84 Switching losses with high inductance and external freewheeling single event 85 Switching losses high inductance ext freewheeling PWM operation 86 High inductance TDEMAG gt tworr measurement example 1 5 87 Figure 62 High inductance Tpemac gt tworr measurement example 2 87 High inductance Tpemac gt Tpwm off measurement example 0 88 High inductance Tpemac gt Tpwm orp measurement example 4 89 A typical example of HSD combined with capacitive load 0 0 0 c eee eee 91 Measurement example VND7040AJ on 320UF 1 eee 93 Xenon load slew rate switching losses VN7016AJ 00 00 cece eee 94 HSD turn on phase with inductiveload llle 95 Turn on example VND7140AJ with inductive load L 260 mH R 81Q 96 Inductive load HSD turn off phase 0 000 ees 97 Inductive load turn off example VND7040AJ L 260 mH R 810 99 Maximum turn off current versus inductance VND7020AJ datasheet 101 Inductive load turn off VND7020AJ L 2 2mH R 40 24 102 Example of external clamping Circuitry 2 0 0 eae 103 Test setup verification of new external clamp proposal 00 0 eee eae 105 PWM 50 at 100 Hz 2 mH 5 5 Q VND7040AJ 0 0 eee 106 PWM 80 at 40
117. during pulses exposure Figure 20 Basic test setup for ISO 7637 2 pulses applied to VND7020AJ signal Generator L T Hz s 9c used only for 3a 3b pulses ISO generator M to simulate 2 21W 5W bulbs min ESD capacitor GAPG1122131107MS Below reported the operative conditions given for VND7020AJ e Device in OFF state and output in open load e Device in OFF state with OUTS in short circuit to GND e Device in ON state INO IN1 high and output in open load e Device in ON state INO IN1 high driving 3 Q resistive load on each OUT e Device in Limp Home state INO IN1 pulled up by 2 7 KQ Diode to Vcc and output in OL After test exposure device results are given in the Table 7 here the most severe pulses are reported DocID028098 Rev 1 Ly UM1922 Protection against battery transients Table 7 ISO 7637 2 2004 and 2011 tests and results on monolithic HSDs TEST PULSE ISO 7637 2 1 1 2a 2a 3a 3a 3b 3b Level Ill Level IV Level Ill Level IV Level Ill Level lV Level Ill Level IV 2004 Class C Class C Class C Class C ClassB Class B Class B Class B 2011 Class C Class C Class C ClassCor E ClassB Class B Class B Class B Class C full operational after each pulse Class B full operational even during pulses exposure Class E One or more functions of the device do not perform as designed
118. e 10 shows an example of an abrupt reverse battery test changing the polarity of the battery supply from 13 5 V to 4 V within a few us The test setup used a 100 V 100 mQ N channel MOSFET with a gate resistor R2 15 kQ The total line impedance is measured with 82 mQ in line with the requirements of LV 124 2009 10 The N channel MOSFET is able to turn off within 10 us about During this time a relatively high current will flow through the HSD substrate diode The total energy dissipated in the HSD is around 100 uJ which is withstood by the MO 7 high side driver family P channel MOSFET in the Vcc line The P channel MOSFET is connected in such a way that its Gate is connected to GND viaa resistor R2 and its drain to Vcc pin while the source acts as the reverse polarity protected supply In Figure 11 is reported a generic schematic with P channel MOSFET configuration Compared to an N channel MOSFET the device will be turned on by applying a negative gate source voltage It is important to insert the transistor in the right direction because the P channel MOSFET has as well an intrinsic anti parallel body diode which is in forward direction from drain to Source By referring the gate signal to the ground line the device is fully turned on when the battery is applied in the right polarity DocID028098 Rev 1 Ly UM1922 Reverse battery protection Figure 11 Generic schematic and test setup with P channel MOSFET in Vcc line
119. e ACE Dee a ce ORE 34 Radiated hazards 00 0 ccc tenet E E 35 Various surges occurring in the supply rail 2 2 eee 36 Internal structures involved during application of ISO 7637 2 pulse 1 in a monolithic HSD and indication of pin voltages 0 2 ce tees 39 Basic test setup for ISO 7637 2 pulses applied to VND7020AJU 000005 40 Internal structures involved during application of ISO 7637 2 2004 pulse 1 in Hybrid HSD and indication of pin voltages 1 2 0 ee RII 42 Internal structures involved during application of ISO 7637 2 2011 pulse 1 in Hybrid HSD and indication of pin voltages llle III 43 Basic test setup for ISO 7637 2 2004 pulses applied to VN7004AH E 44 Recommended GND network for ISO 7637 2 2011 level IV llli 45 Basic Test setup for ISO 7637 2 2011 pulses applied to VN7004AH E 46 Latch functionality behavior in hard short circuit condition Tjunction TTSD 50 Latch functionality behavior in hard short circuit condition TR lt Tjunction lt TTSD 50 Latch functionality behavior in hard short circuit condition autorestart mode and latch off E 51 Standby mode activation 0 ene e 52 Standby state diagram 1 0 aeaaee tenes 52 FR handling example bulb inrush blanking VNQ7140AJ 000000 e ee 53 Common FaultRST pin handling example basic schematic without decoupling COMPONENIS T m 54 Faul
120. e load Vaar Vin gt t Vour Vepat tr gt t L lour Veat A vo 7 Reno W Deno Vour R re L lr E i i ji LU a t o t GAPG1127131004MS DoclD028098 Rev 1 95 196 Load compatibility UM1922 Figure 72 Turn on example VND7140AJ with inductive load L 260 mH R 81 Q Lo iB i i zu i Measure P1 freq C1 P2 period C1 P3 duty C1 P4 fall C2 P5 P6 value I m status E E 4 base 10 0 ma Trigger C1 0 00 V offset 10 00 V ofst 150 00 mA 1 00MS 20MS s Edge Positive GAPG1127131005MS 6 3 2 Turn off The HSD turn off phase with inductive load is explained in Figure 73 The inductance reverses the output voltage in order to be able to continue driving the current in the same direction This voltage so called demagnetization voltage is limited to the value given by the clamping voltage of the HSD and the battery voltage Equation 3 VbpEgMaG Vgar VcLAMP 13V 46V typical 96 196 DoclD028098 Rev 1 Ly UM1922 Load compatibility Figure 73 Inductive load HSD turn off phase Vear MO 7 HSD Ear V yes 46V typ Eusp Egar Etoap lour l l z Eroan E Er OUT i 1 Vbemac Reno V Deno 33V Voemac eis i a R KS 1 Tpemac GAPG2111141204CFT T
121. e of the integrated Voc to GND clamping circuit substrate diode Voltage on MultiSense pin is dropping to the reverse battery voltage plus the forward voltage across the internal ESD protection diode The maximum allowed DC output current on MultiSense pin Isense in reverse battery conditions is limited to 20 mA Therefore the sense resistor Rgeyge must be chosen accordingly 26 196 DoclD028098 Rev 1 Ky UM1922 Reverse battery protection Rsense gt IVBAr reverse 0 7 VI 0 02 A 765 Q For generic Rgense dimensioning rules please refer to Chapter 7 MultiSense analogue current sense Due to the clamping voltage of the integrated ESD protection diodes on logic pins FaultRST IN SEL SE the voltage on those pins is dropping to 10 V about Therefore a serial resistor is needed to limit the current and protect the I O structure on microcontroller port pins and the high side driver s logic pins The gate voltage of the N channel MOSFET is pulled down to the reverse battery voltage ensuring the MOSFET is fully off In normal operation only the leakage current of ZD1 Zener diode is flowing through R2 to GND In order to minimize this current even at higher supply voltages a diode with higher Zener voltage i e 18 V might be chosen The Zener voltage should be anyway always lower than the maximum rated Gate Source Voltage Vas of the N channel MOSFET The resistor R2 limits the current through the Zener diode at supply volt
122. e than one channel In case the application requires latch mode configuration of the HSD in order to avoid unwanted turning off of the bulb during the inrush phase it is suggested to implement a proper software strategy in order to set up a blanking time whenever the inrush of the bulb occurs Blanking time length depends on environmental conditions bulb type and device type Power loss calculations The power loss calculation is an important step during the application design as it is a basis for further thermal considerations and PCB design This chapter is intended to provide guidelines for calculation and estimation of power dissipation in the device in combination with different kind of loads resistive inductive capacitive etc and with different modes of operation steady state PWM All next evaluations are focused on power losses in the power MOSFET of the device The power dissipation of other parts control logic charge pump is in most cases negligible If needed it can be calculated from the device supply current Is and supply voltage value Vcc Device control part power dissipation W Porn Voc anpcon Example 1 For VND7020AJ Figure 46 Control stage current consumption in ON state all channels on driving nominal load datasheet value Control stage current Voc 13 V Vsen 5 Vj consumption in ON Ver Vsgi o1 0 V IGND ON state All channels Vino 5
123. ead with the given Rgense must be higher than a certain ADC threshold This can be expressed by the following equation VSENSEMAX ISENSE SAT MIN Where Vsensemax is the maximum voltage that the ADC has to read at the maximum monitored load current This value can be below or equal to 5 V which normally is the maximum operating range of the ADC 3 In fault conditions overload short circuit to GND that cause Power Limitation or Thermal Shutdown and in Open Load Short to Battery in OFF state in order to be able to differentiate a normal operating condition from a Fault condition the MultiSense pin must be capable of developing a voltage above the Vsensey Value given in the datasheet Vsensen 6 V typically Therefore the following condition must be fulfilled HsENSE Equation 10 VSENSE H min R gt ENSE SENS ISENSE_H_min 4 Finally the current sense resistor is necessary to protect the MulitSense pin in case of reverse battery During this event for monolithic devices an intrinsic diode between MultiSense and Vcc pins is forward biased and the resulting current must be limited in the datasheet the maximum MultiSense current that can flow in reverse battery condition is indicated in the absolute maximum ratings table This value is given in the Absolute Maximum Ratings section of MO 7 datasheets Isense value in case of VND7020AJ this is 20 mA therefore the minimum Rsense to protect the MultiSense pin in case of reverse
124. ed into output device works properly and the output stage follows the state of the IN pin as long as the injected current does not exceed a certain threshold The inverse current threshold value which modifies the device functionality depends on channels Status ON or OFF state In particular the inverse current which inhibits device operation with channels in ON state is proportional to the ratio between Vp and Ron IINVERSE th Bo where e Ve is the body diode forward voltage at room temperature typical value is 0 7 V e Ron is the value of ON state resistance of PowerMOS at room temperature Instead in case of channels OFF the threshold current is almost constant and does not depend on Roy value Its value is about 0 6 mA for monolithic devices and 0 4 mA for hybrid devices The reason behind this different behavior between the ON and OFF channel state can be explained by the device structure itself The triggering event that modifies the channel under test behavior when in OFF state and during inverse current injection is the Vour Vcc value As soon as this value approaches the threshold of the intrinsic anti parallel diode or in other words as soon as some current flows through this diode NPN bipolar parasitic components between PowerMOS gate and battery pin Vcc are triggered This does not allow to switch the channel under test back on DoclD028098 Rev 1 179 196 ESD protection UM1922 10 10 1 180 19
125. ense into a defined state a dedicated circuit section shuts down the current sense circuitry when Voyrt drops below the threshold Vout men typically 5 V In conclusion in normal operation the current sense works properly within the described border conditions For a given device the Isense is a single value monotonic function of the lout as long as the maximum Vgense 15t example or the current sense saturation 209 example are reached i e there s no chance to have the same Isense for different lout within the given range Failure flag indication In case of Power Limitation or overtemperature or open load short to Vcc in OFF state the fault is indicated by the MultiSense pin which is switched to a current limited voltage Source DoclD028098 Rev 1 Ly UM1922 MultiSense analogue current sense Indeed with reference to Figure 89 whenever a Power Limitation overtemperature condition is reached The MultiSense output is internally pulled up to Vsensen The MultiSense output in those events is controlled in such a way to develop at least a voltage of Vsensen given in the datasheet across the external sense resistor In any case the current sourced by the MultiSense in this condition is limited to the Isensey given in the datasheet In order to allow the current sense pin to develop at least VsenseH 5 V a minimum sense resistor value must be set for details see Section 7 2 6 Considerations on MultiSense resistor c
126. es e Common control pins SEQ separate MultiSense Depicted is a combination of hybrid and monolithic HSDs In order to use common control signals for both HSDs protection resistor is used for each device separately see Chapter 8 Paralleling of devices paralleling monolithic and hybrid HSDs Additional A D is used for GND shift offset compensation of Tepp and Vpar signals Figure 40 Monolithic and hybrid device separate power supply rails separate MultiSense 100 nF 50V L Vas FaultRST GPIO INO GPIO GPIO SEn FaultRST GPIO A control GPIO Multisense Multisense GND GPIO INx 4d E w AID 1 15k AID2 Apa 15k GND offset measurement GND Eo el 4TOpF lil Truth table shows signals mapping Table 18 Truth table monolithic hybrid separate MultiSense A D 1 A D 2 SEL SEL SEn MultiSense U1 MultiSense U2 VN7004AH E VND7020AJ X X L Hi Z Hi Z L L H Current Sense ChO L H H Current Sense Ch1 Current Sense H L H TcuIP Sense H H H Voc Sense Example 5 e VN7004AH E VNQ7040AY e Separate power supply lines e Separate SE control pins common MultiSense Because of both hybrid HSDs share common MultiSense and different power supply lines are used on each HSD serial protection diode is used on each device MultiSense output DoclD028098 Rev 1 63 196 Usage and handling of MultiSense SEL pin UM192
127. esistor is needed to limit the current and protect the I O structure on microcontroller port pins and the high side driver s logic pins Furthermore the ground network shall ensure the device will work properly when driving inductive loads and or is not being damaged when submitted to ISO 7637 2 2011 E pulse 1 test level IV pulses The diode at the GND terminal blocks the current through the forward biased internal substrate diode of the HSD during reverse battery condition A resistor connected in parallel to the diode is recommended in case the device drives a high inductive load with a demagnetization time longer than tp stpy delay time for the device to reach standby mode after the last logic pin IN FaultRST SE and SEL is set low The purpose of this resistor is to suppress a negative voltage on the GND pin during the standby mode if the demagnetization phase is still ongoing Without this resistor the low supply current in standby mode Igo 0 5 pA max at 85 C allows the GND pin to be pulled negative by the demagnetization voltage on the output Vcc Vei AMpP 13 5 V 46 V 32 5 V via an internal pull down resistor 790 KQ on the output see Figure 4 lf the negative ground shift exceeds the input high level threshold the device leaves the standby mode and tends to turn on The GND pin is immediately pulled high DoclD028098 Rev 1 19 196 Reverse battery protection UM1922 Note Note 20 196 6
128. etection limit for the lowest power bulb is lost in the tolerances In order to achieve better current sense accuracy the current sense calibration K factor measurement of each HSD can be adopted K factor calibration method In order to reduce the Vsense spread it is possible to reduce the K spread and eliminate the Rsense Variation by adding a simple test calibration test at the end of the module production line Single point calibration on low current K factor can be calibrated in single point by measurement of Isense for specified lor K is then calculated as lout ISENSE For low currents diagnostic using single point calibration method it is possible distinguish between open load 10 mA and low current limit depending on device Rpsow for example VND7020Au datasheet specifies low current level gt 50 mA KCALIBRATED For calibration of K factor at lor 30 mA T 25 C and Vcc 13 V in the datasheet of VND7020Au there is specified a maximum drift of K factor 80 96 in range lout 10 to 50 mA temperature range of T 40 C to 150 C and battery range Vcc 7 V to 18 V All these parameters allow clear distinguishing between minimum and maximum lour within specified range Following example shows detection thresholds with no overlapping zone between maximum VseENSE Corresponding to open load threshold at 10 mA and minimum Vsense corresponding to minimum load at 50 mA Example 4 louT 30 mA
129. eters Woy and Wo considering Voc 13 V 40 lt Tj 150 The switching losses vary with battery voltage If we suppose constant switching times at varying the battery voltage this yields DocID028098 Rev 1 Ly UM1922 Load compatibility Ww W PLoA DatVBAT2 ONatVBAT2 ONatVBAT p LOADatVBAT1 w NT PLOADatVBAT2 FFatVBAT2 WorFawBATI B uid a PLOADatVBAT Experimental measurements on MO 7 HSDs have highlighted that switching times are slightly decreasing with increasing Vcc so the above formulas are approximated Calculation example VND7040AJ e Load 4 5 O resistor e V BAT 16V e twon tworr 60 us this parameter is not explicitly specified in the datasheet The value can be obtained by the measurement this case or estimated from dVoyr7 dt datasheet parameter e Requirement driver must not run into thermal shutdown Peak power dissipation W 2 p 2 BAT _ 16v MAX 4 R 4 450 Turn on Turn off energy loss J 2 1 16V Switching losses measurement comparison with calculation The switching losses in the HSD are measured by an oscilloscope with mathematical functions The first function F1 shows the actual power dissipation on the HSD VBar Vout lout the second function F4 shows the HSD energy integral of F1 DoclD028098 Rev 1 75 196 Load compatibility UM1922 76 196 Figure 52 Example of switching losses on VND7040AJ with 4 50 resistive
130. eturned to proper operation without replacing the device 1 By adding a series resistance 47 Q on GND pin the device is able to pass level IV of ISO 7637 2 2011 N 1 edition 2011 2 Device is not able to pass the level IV of ISO 7637 2 2011 in off state with open load condition In off state condition with a minimum series resistance on the GND pin the device is able to pass level ISO 1 and 2a level IV of ISO 7637 2 2011 Moreover M0 7 Hybrid HSDs pass the load dump clamped pulse test class C according to Table 7 criteria relevant to the standard ISO 7637 2 2004 E 5b pulse with 40 V centralized load dump suppressor as well as the standard ISO 16750 2 2010 E pulse with 35 V centralized load dump suppressor DoclD028098 Rev 1 47 196 Usage handling of fault reset and standby UM1922 4 4 1 48 196 Usage handling of fault reset and standby On top of M0 5 Enhanced HSDs functions and protections in the new MO 7 devices additional features have been implemented e Latch off functionality FaultRST pin high The drivers will latch off in case of power limitation or thermal shutdown In order to unlatch the channel s a low level pulse on FaultRST pin is required for minimum duration of tj Arcu nsr This time ensure the device clears the latch only if required and not accidentally FaultRST pin low or left open The drivers will behave like MO 5Enhanced devices autorestart in case of powe
131. experimental results on a limited sample base In the Table 33 following symbols are given e Vr is the body diode forward voltage at room temperature e d isa delta voltage between Voc and Vourn with a value lower than Vr e VsENSEHI is the fault MultiSense voltage e Vo is the OFF state open load detection threshold Table 30 Inverse current threshold experimental values according to channels status Ch0 is the channel under test ChO ON Channel configuration MultiSense enabled in current monitor mode 5 Ch0 ON Ch1 ON Ch0 ON Chi OFF a E RL ch0 10 k RL chi 10k RL ch0 10 k RL chi 10k c NE V M V S SENSE SENSE UT Vour IV configuration Ri di Vout V configuration Cho mAl cho chi cso csi CPOIMA cho ch cso cst 2 26800 Voctd Voc 0 0 27600 Voectd 0 0 0 NES REIS OQ g 29200 VcctVe Voc Vsensen 28400 Voc Vr gt VoL VsenseH VSENSEH es 2 3500 Vectd Voc 0 0 3500 Vectd 0 0 0 x LLI N o e 3700 Vcc VF Vcc VsenseH 9 3700 Vcc Vr gt VoL VsENsEH VSENSEH gt Z 45000 Voctd 0 d S S 50000 Vcc Ve VsENsEH gt gt 2 13700 Voectd Voc 0 0 13000 Vectd 0 0 0 REIS OQ g 14500 VcctVe Vcc Vsensen 14100 Vcc VE gt VoL VsenseH VsENsEH zd 41000 Vocsd Vec 0 0 42900 Vcesd 0 0 0 a se S
132. failure mechanism Components dimensioning Because the Reverse Battery event the device needs to be protected by an external diode plus a resistor network in case of inductive loads connected in series to the ground pin In this chapter the ground network is dimensioned referring to the SO7637 2 edition 2011 test pulse 1 and 2 Due to the presence of such protection network the Negative ISO pulse 1 level IV 150 V at 1 ms is directly transferred to the GND pin via the internal clamping Then the HSD with a diode protection at the GND pin does not clamp negative ISO pulses on the supply line Moreover the internal parasitic structures of I O pins link these pins directly to Vgar and then to 150 V see Figure 19 Therefore an appropriate serial protection resistor should be used between microcontroller and HSD in order to limit the current injected into these pins DocID028098 Rev 1 Ly UM1922 Protection against battery transients Figure 19 Internal structures involved during application of ISO 7637 2 pulse 1 in a monolithic HSD and indication of pin voltages 5V r j ov gt RN ov Limp Home circuitry 1 1 1 1 1 1 Rprot X Did Rprot OUTPUT Rprot l X 149V Rsense Renp y Deno
133. g the negative pulse the voltage on Vcc pin Vgar is clamped to minus one diode voltage due to the forward biased substrate diode of the HSD The P channel MOSFET is turned off once the Vgar voltage begins to drop This happens within few tens of microseconds about As soon as the Vgar voltage drops to 55 V the P channel MOSFET starts to conduct in avalanche until the pulse amplitude drops below its breakdown voltage BVpss 55 V The breakdown voltage BVpss of the P channel MOSFET either should be higher than the maximum negative transient peak voltage of ISO 7637 2 2011 E or the energy capability of the P channel MOSFET in avalanche must be high enough to sustain the transient pulse energy Figure 13 Reverse battery test according to LV 124 2009 10 VN7016AJ 13 5 V at 4 V 82 mO R2 1kQ LeCroy VCC GND stress 0 6mJ a Measure P1fall C2 P2fall C2 P3 duty C1 P4fall C2 P5 P6i value 2 188883 ps status x imebase 20 0 u 5 00 Vidi 5 00 e 5 00 Vidiv 5 00 Aidiv 20 0 usidiv Stop 55V 0 mV offset 10 000 V 6 100 V ofst 5 000 A IG 1 00MS 5 0GS sfEdge Negative Figure 13 shows the example of an abrupt reverse battery test changing the polarity of the battery supply from 13 5 V to 4 V within a few us The test setup used a 55 V 16 mQ P channel MOSFET with a gate resistor R2 1 kQ The total line impedance is measured with 82 mQ in line with the requirements of LV 124 2009 10 The P channel MOSFET is able to t
134. ge limit of the Schottky diode Vary 100 V seems a good compromise with respect to the ISO 7637 2 2004 E pulse 1 Test levels IV In case compliance with ISO 7637 2 2011 E pulse 1 Test level IV is required Varn must be 2 150 V The main drawback of this method is the power dissipation in the Schottky diode in forward direction Depending on the type of package the Ry and the ambient temperature the maximum affordable power dissipation in the Schottky diode is typically in the range of 1 W In consequence the maximum average forward current is limited to the range of 1 A 2 A The direct diode reverse battery protection can also be replaced with a simple fuse However upon battery inversion this fuse will blow and the module will need to be replaced or repaired Ly DoclD028098 Rev 1 17 196 Reverse battery protection UM1922 2 2 2 18 196 Diode resistor in GND line The reverse battery protection is applied to the GND terminal of the driver This kind of protection leaves the output power stage in reverse battery condition conductive through its body diode The current is limited by the external load Since no thermal protection works in reverse condition special attention must be paid to the total power dissipation in the device During the reverse battery event the peak junction temperature shall remain safely below the maximum allowed junction temperature Trsp max Considering a voltage drop on the internal
135. gh SE pins This current could lead to malfunction or even failure of one or both of the HSDs In order to avoid such failure it is recommended to add a 15 KO resistor in series to each SE pin in the same way as already described in case of paralleling of monolithic devices See previous chapter In principle the same applies to all other logic input pins as well since the clamp structure is similar The following table is summarizing possible combinations of HSDs with paralleled inputs relative to the used power supply networks Figure 128 Paralleling of inputs summary Different supply networks Texchnology WAS IIT poner SIDE REST different VBAT VBAT GND network z or different GND protection network Singleresistor on uC side HSD inputs in parallel Monolithic Monolithic NI uCVO 15k Each HSD use separate protection resistor Hsp 15k HSD INx INx Hybrid Hybrid uC I O m p 15k HSD INx Monolithic Hybrid ky DoclD028098 Rev 1 157 196 Paralleling of devices UM1922 8 2 8 2 1 Paralleling of MultiSense The following chapters describe the paralleling of MultiSense pins of HSDs taking into account device technology monolithic HSDs or hybrid HSDs and supply line configuration either the same or separate supply line for each HSD Direct connection of MultiSense pins is an allowed operation without any restriction when the devices are supplied from one supply line
136. gy is derived from the I L diagram in the datasheet see Figure 75 DoclD028098 Rev 1 Ly UM1922 Load compatibility Figure 75 Maximum turn off current versus inductance VND7020AJ datasheet 100 0 1mH 18A Emax 22 9mJ Min 10 ee Se p 1mH 7 7A CEREREM m o EE Em m EA Da qee EE aae 4a ld lo T A ee Ge E D G u VND7020AJ Single Pulse Repetitive pulse Tjstart 100 C 2 2mH 5 5A Emax 747 1mJ Repetitive pulse Tjstart 125 C Toemac 7372ys TT 0 01 L mH 0 1 1 22 10 GAPG1127131008MS The maximum turn off current for 2 2 mH inductance is 5 5 A for the repetitive pulse Tjstart 125 C which is above the load current in this example ly 4 A However this current limit is specified for R 0 Q and Vpaz 13 5 V Since these conditions are different from conditions considered in this example R 4 Q Vgar 16 V it is recommended to find the energy limit in the I L diagram with same demagnetization time as calculated in the example 235 us Then it is possible to directly compare this limit with calculated energy in the application regardless the different condition As a first step the 2 2 mH 5 5 A limit is selected from the I L diagram and related energy limit and demagnetization time is calculated Demagnetization energy related to selected point 2 2 mH 5 5 A using Equation 7 V V BAT Ypemag _ E Gnas ig P 185 8238 maed EMAX 7 5 L
137. hannels applying independent configuration of rising falling edge position duty cycle together with trigger specifying sampling point for MultiSense signal For example SPC560B64 up to 2x31channels are available for this purpose other models can contain different number of eMIOS channels These channels can be mapped directly to control INx signals of multiple HSDs Additional block aligned with MO 7 devices MultiSense control is ADC external Multiplexer This peripheral use MA 2 0 control pins capable to control external analogue Multiplexer in this case MO7 devices are in role of external multiplexer SELo SE pins are controlled by MA 2 0 outputs Four analogue input channels ANX 3 0 linked with MA 2 0 selector outputs create possibility to monitor 4 A D inputs x 8 possible combination of MA 2 0 32 analogue signals driven by MA 2 0 outputs Depending on the system complexity multiple devices can be diagnosed using extended ADC channels without need of SW control on the microcontroller side eMIOS block create trigger measurement points pass them to the ADC external multiplexer It drives MA 2 0 outputs applied to MO 7 HSDs SELx pins selecting relevant monitored channel Selected MultiSense feedback passed to one of the A D inputs is automatically measured by microcontroller A D converter at preconfigured time This operation applies to all channels using MA 2 0 external multiplexer For simple med
138. he current limited by the external load Since no device intrinsic protection schemes are active in reverse condition special care must be taken on total Power Dissipation e Hybrid HSDs in contrast to monolithic devices all hybrids VIPower HSD do not need any external components to protect the internal logic in case of a reverse battery condition The protection is provided by internal structure Moreover due to the fact that the output MOSFET turns on even in reverse battery mode and thus providing the same low ohmic path as in regular operation condition no additional power dissipation has to be considered Even more if e g a diode without any parallel resistor is connected to GND of a hybrid HSD the output MOSFET is unable to turn on and thus the unique feature of the driver is disabled Reverse battery protection of monolithic HSDs Reverse battery protection schemes basically can be grouped in the following categories e Active or passive reverse polarity protection e Reverse polarity protection on supply line Vcc terminal or on GND line GND terminal Table 1 Reverse battery protection concepts eter chapter Activetpassivo iem Conduction trough Schottky Diode 28 Passive Vcc No Diode Resistor d Passive GND Yes N channel MOSEFT 223 Active GND Yes a DoclD028098 Rev 1 UM1922 Reverse battery protection Table 1 Reverse battery protection concepts continued Reverse battery i Vc
139. he load current decays exponentially linearly if R 0 and reaches zero when all energy stored in the inductor is dissipated in the HSD and the load resistance Since the HSD output clamp is related to the Vgar pin the energy absorbed by the HSD grows with increasing battery voltage the battery is in series with the high side switch and load so the energy contribution of the battery is increasing with the battery voltage 6 3 3 Calculation of dissipated energy The energy dissipated in the high side driver is given by the integral of the actual power on the MOSFET through the demagnetization time ees EHsp VcLAMP lour D8t To integrate the above formula we need to know the current response igur t and the demagnetization time TpgyAg The loyt t can be obtained from the well known formula of R L circuit current response using the initial current lg and the final current VpgyAG R considering iour 2 0 condition see Figure 73 f V aoe DEMAG L Putting i t 0 we can calculate the demagnetization time Equation 4 _ Lpf pevac lo P ee a IVbEMaG Ly DoclD028098 Rev 1 97 196 Load compatibility UM1922 98 196 Equation 5 lo simplified for R gt 0 VDEMAG lima oTpemaG L Substituting the Tpemac and igur t by the formulas above we can calculate the energy dissipated in the HSD TDEMAG TDEMAG Eusp VciAMP lour 0dt J Vgar VbeuAgp tour tat then Equation 6 V HV IV 1 R BAT
140. he protection of on board receivers 2 ISO 7637 2 2004 E Road Vehicles Electrical disturbances from conduction and coupling second edition 3 ISO 7637 2 2011 E Road Vehicles Electrical disturbances from conduction and coupling third edition 4 LV 124 2009 10 Electrical and Electronic components in motor vehicles up to 3 5t General requirements test conditions and tests 5 ISO 16750 2 2010 E Road Vehicles Environmental conditions and testing for electrical and electronic equipment 6 ISO 10605 Road Vehicles Test methods for electrical disturbances from electrostatic discharge 7 IEC 61000 4 2 Electromagnetic compatibility EMC 8 Double channel high side driver with MultiSense analog feedback for automotive applications VND7020AJ DoclD027393 194 196 DoclD028098 Rev 1 3 UM1922 Revision history Revision history Table 34 Document revision history Date 29 Jul 2015 Revision 1 Initial release Changes DoclD028098 Rev 1 195 196 UM1922 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditio
141. hoice for current monitor The typical behavior of a MO 7 high side driver in case of overload or hard short circuit is shown in the following figures FaultRST set low so to indicate autorestart mode Figure 94 Failure flag indication example 4 Short to GND INo 3 5B ms 10 0 V Vour 5B ms 20A div lout 50 ms BWL GAPG1129131807MS An example of a condition with a progressive increase of the output current single shot ramp by an electronic load supplied by VND7040AJ is shown in Figure 95 Sense resistor is 2 2 KQ Device is set in latch off mode The saturation voltage Vsense satis reached and then the current limitation lj jy p afterwards the Thermal protection acts As soon as the output voltage falls down below about 5 V parameter Voyt msp in the datasheet the MultiSense pin goes in high impedance as previously explained until the first power limitation peak is reached At this point the MultiSense pin is reactivated again and the Vsense n Voltage is issued and latched Since in this case the FaultRST pin is set high latch off the PowerMOS remains off DoclD028098 Rev 1 123 196 MultiSense analogue current sense UM1922 Figure 95 MultiSense operation of VND7040AJ in current monitoring with increasing overload and consequent device s latch off due to thermal protection intervention 7 2 6 124 196 Vhat Veat 14V
142. hould be calculated according to the maximum injected current to I O pin of the used microcontroller and to the maximum Input sink current of the HSD Diode parameters can be lower if an external clamping circuitry is used e g HSD module is supplied from a protected power supply line DocID028098 Rev 1 Ly UM1922 Reverse battery protection Dimensioning of the GND resistor The GND resistor is recommended in case of a high inductive load To determine if the resistor is needed or not we need to know the demagnetization time Tpemac The resistor is recommended if Tpemaa is higher than the standby delay time tp srgy A typical tp stpy value of 350 Us is considered in this comparison TpEMaAa Can be determined by either measurement Figure 6 Rawp 4 7 KQ Load Relay 270 mH 90 Q alternatively Bulb on a typical wire harness with 6 uH stray inductance or calculation using Equation 1 and Equation 2 Figure 4 Negative GND shift TpEMAG 2 lp STBY 13 5V 32 5V Multisense 4 7k GND Tp sTBY GAPG1121131239MS Equation 1 VbpEMAG VBAT VCLAMP Equation 2 n _ La peEmacl lo R a IVpEMAcG Ly DoclD028098 Rev 1 21 196 Reverse battery protection UM1922 Figure 5 GND resistor requirements inductive load test setup
143. iSense result The measurement setup is similar to previous evaluation extended with 2 additional AD channels for GND shift monitoring two reverse battery protection groups These AD channels are HW triggered with dedicated eMIOS channels Analogue signals mapping is the same as shown in Table 28 Figure 121 Example MultiSense reading on multiple HSDs with GND shift compensation Goup2 Mer Vo ac 10rF 50V 10nF50V re i L le Voo FautRST 15k cc 15k Vec GPO zi FadtRST p FauitRST l Mio HE cm No 15k es l mar EH XX INI XT INI l Sn oUm M2 P OUTO p a2 l GPO Sn SEn 15 18k sao Ssmo l 15k 15k i ivenGPIo seu oun E su oum 9 l s 8 M isense Multiserse l Ei GND 26 l Z JL 100 470 i eMIOSdrivengPIO 10 40 EE 18k JL Roe ANXO b y Do Ld l Ex Ras JE l 4p l I Vow 7 7 15k ae 100nF S0V 100nF 50V 5 Sy ANPO ie SS L 15 18k Voc Peg m FaitRST sal FajtRST zi INO mm INO l m N E INI d5i I outo mm m2 OUT0 1 151 l Sn me INS 15 sao 15 i sai ou
144. ile multi motor driving connection e o e e A F A so Ze TPA uU O A mE CL uS Mirror Vertical Mirror Horizontal x ES P dans Jt X PA Mirror Folder Safe Lock Lock E N A N A N s M a M a M NC Pi A P 11 2 11 2 1 11 2 2 186 196 MO 7 high side drivers in H Bridges specific considerations The MO 7 high side drivers single and multichannel can be used to drive various bidirectional loads in H Bridges configurations Some general guidelines should by the way be applied in order to avoid issues An overview of some potential issues is given in the following paragraphs Short circuit event to ground and to battery In case of short of one output of the H Bridge to GND the MO 7 high side driver protects the H Bridge with its well know protections circuitry Current Limitation Power Limitation Thermal Shutdown with autorestart or latch off MultiSense pin will signalize Vsenseq like already explained in Section 7 2 4 Impact of the output voltage to the MultiSense output In case of short circuit of one output of the H Bridge to Vcc the H Bridge needs an external protection during ON state because in this case the low side of the fa
145. immy Output li 2 eurei Current im P S Tso TR d Junction Them ut Dow ig Temperature in AutoRestart mode Tame 4 M Logic ER Mew __ Internal High Fault Detection hara Output Circuit Vout lt 5V Vout lt 5V diio pedit po Vsense Multisense Voltage 50 196 Ly DoclD028098 Rev 1 UM1922 Usage handling of fault reset and standby Figure 28 Latch functionality behavior in hard short circuit condition autorestart mode and latch off Logic High Sense Enable Logic High Input Logic llim l lim High Fault Reset TIN MOM uar Cp wmm uy eee Trsp 60 Tame Junction Temperature j_ Chip 4 Temperature Logic Internal High Fault Detection Hard Short Circuit Vout lt 5V Vout lt 5V eee V Sense Multisense Voltage 4 2 Standby mode The standby mode is available when the FaultRST pin SE pin SEL pin and all IN pins are set low or open and kept in this condition for a duration corresponding to the maximum tp stpy This time tp stpy has been introduced in order to avoid entering the standby condition in case all generic input pins are low during a commutation so no accidental standby can occur see Figure 29 In standby condition the supply current drops down to 0 5 uA max at 85 C As soon as the device enters the standb
146. int level 184 11 Usage in H Bridge configurations Lees 185 Tet InuoduguOlt siocs sane RAO RE RAE XR ERE PER EEEN A AE KR RE 185 11 2 MO 7 high side drivers in H Bridges specific considerations 186 11 2 1 Short circuit event to ground and to battery 186 11 2 2 Cross current events llle 186 4 196 DoclD028098 Rev 1 Ly UM1922 Contents 11 2 3 Usage of MultiSense TCHIP in H Bridges 191 11 2 4 Freewheeling current of inductive loads lessen 191 Appendix A References lseeeeeeeeeeeeee nnne 194 REVISION NISIO Y oua iex i ck d Eod Wok VR CARO RR RUE rac oa C e CR 195 Ly DoclD028098 Rev 1 5 196 List of tables UM1922 List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 6 196 Reverse battery protection concepts 0 cece eee eee 16 Reverse battery voltages on pins VND7040AJ 0 0 00 eee 19 Static reverse battery voltages on pins llli illie eee 26 Static reverse battery voltages on pins lille lessen 30 I8Q 7637 2 2004 E r e clo xem ere ee D
147. ium complex systems up to 32 analogue monitored channels analogue monitoring of all channels can be applied without impact on CPU load using extended ADC attached to eMIOS channels in OPWMT mode On more complex system analogue monitoring more than 32 channels additional logic must be involved DoclD028098 Rev 1 143 196 MultiSense analogue current sense UM1922 144 196 Figure 114 SPC extended ADC channels block diagram Up to 32 extended channels through external MUX CTU eMIOSO 0 H ChO trig ieMIOSO 23 L ADC system ADC control Ch 6471 Ch23 trig eMIOS ieMIOS1 0 ADC trigger I M Ch298 trig Digital Interface Analog switch ANP 15 Ch 15 16 channels INTC 5 s 2 single ended interrupts F TANP O Ch 0 high accuracy EOC Watchdog eMIOS1_23 Up to 20 channels Ch52 trig ADC done 15 Ch 47 medium accuracy S p Ch28 trig PIT2 PIT 0 Ch 32 While ADC external MUX control is used on SPC it is important to preconfigure maximum delay 64 us between MUX switching and A D conversion This delay covers time necessary to switch MO 7 internal Multiplexer to newly selected channel signal together with time needed for signal stabilization caused by low pass filter used on A D input Additionally must be ensured valid curre
148. ive loads Since there are many different types of the LED string it is almost impossible to cover all cases with one general calculation formula like in case of resistive loads Exact calculation is problematic even for specific LED load with known behavior due to its non linear V A characteristic see examples in the next figures Therefore it is usually more efficient to do the estimation only or switching losses measurement as shown in this chapter Figure 54 LED cluster example 1 LED test board 6 x 3 LEDs OSRAM LA E67 4 27 400100 100 100 100 100 250 4 O Ld e Ld e e E 200 H 150 4 VVVV VV s 100 TAS SETS E id VVVV VV F SNNSNNNSNIRS 0 Ft Ht 0 2 4 6 8 10 12 14 16 yy AAAA Vled v O Ld e e Ld e GAPG1127130949MS ky DoclD028098 Rev 1 77 196 Load compatibility UM1922 78 196 Figure 55 LED cluster example 2 tail amp brake light VW Passat B6 x E Uv S 0 2 4 6 8 10 12 14 16 Vled V BZX84 3 3V 3 3 16 x RED LED rt t et a SO8S Lr 25 5 59 59 59 59 x TAK o H Upcaadabasnas Y y v aa SO To J O e 1k Y X Y Ys T4mr 4 x BC846B eee e 0 59 59 59 59 ASJ4A T cl i Y v vov m S RY R 2 2k 25 5
149. le but the worst case demagnetization energy is too high turn off from stall condition at DoclD028098 Rev 1 Ly UM1922 Load compatibility 16 V 40 C Rather than selecting a bigger HSD the use of an external clamp can be the most convenient choice External clamping circuitry requirements summary e Negative clamping voltage below the HSD clamping voltage e No conduction at Normal operation 0 16 V Jump start 27 V for 60 s Load Dump 36 V for 400 ms Reverse battery condition 16 V for 60 s e Proper energy capability Single demagnetization pulse Repetitive demagnetization pulse An example of external clamping circuitry compatible with all above listed requirements is shown on Figure 77 Figure 77 Example of external clamping circuitry J Vear Vcc FR e Ld e IN Pre Vos x Akal SEn eo SEL e lour ILoap OUT A Multisense mum mmm 15V t Avec y e Q1 W n channel MOSFET j I j j j j j Vout GND GND GAPG2111141208CFT It is a combination of standard freewheeling diode and active reverse battery protection with N channel MOSFET introduced in previous reverse battery protection chapter Since the anode of the diode is connected to the source of the MOSFET it
150. les The load dump is caused by the discharged battery being disconnected from the alternator while the alternator is generating charging current This transient can last 400 ms and the equivalent generator internal resistance is specified as 0 5 O minimum to 4 O maximum According to the ISO 7637 2 standard the 100 spikes are due to supply sudden interruption of currents in a device connected in parallel with the DUT due to the inductance of the wiring harness while the 150 V spikes are due to a supply disconnection from inductive loads This chapter deals with voltage transient pulses detailed on the ISO 7637 2 standard DoclD028098 Rev 1 35 196 Protection against battery transients UM1922 Figure 18 Various surges occurring in the supply rail 25 kV ESD spikes 87V Load dump 100 150V Spikes 24 V Jump start Nominal 14V 6V Crank 0v Reverse battery GAPG1122131105MS 3 4 Standard for the protection of automotive electronics All the hazards indicated above are described by several standards bodies such as the Society of Automobile Engineers SAE the Automotive Electronic Council AEC and the International Standard Organization ISO Since the 1807637 are the most important automotive standards regarding electrical hazards transient this document mainly concerns the cases considering such standard Below the electrical characteristi
151. load current lour With given switching shapes and resistive load the instantaneous power dissipation can be approximated by triangular waveform see yellow area on Figure 51 DoclD028098 Rev 1 73 196 Load compatibility UM1922 Note Note 74 196 Figure 51 Switching and conduction losses resistive loads Vin gt lt Ta on lt gt Tatort Vout lour Vaar Vps N 100 l Vout lout MOo 7 HSD 8096 50 20 0 Pioss N Puax A R Vour Reno v twon ton tworrF GAPG1127130947MS Considering resistive load the maximum instantaneous power dissipation occurs at half of the nominal output voltage and half of the nominal load current It is the point where the switch resistance matches the load resistance maximum power transfer theorem impedance matching Peak power dissipation W Pmax 72 72 2 DR 4 R Turn on Turn off energy loss J 2 1 VBAT Won Wore g 7g twon twon lworP Linear shape of the switching phase and symmetrical turn on off shapes considered Same calculations are applicable also on the bulb in PWM mode If the PWM frequency is high enough gt 50 Hz the filament temperature resistance variation over the PWM period is negligible so it behaves like constant resistor Typical and maximum switching losses on nominal resistive loads are specified in the datasheet with param
152. losses calculation or estimation Aim of this chapter is to show one example related to a measurement with specific Xenon module and Xenon lamp In most cases there are two inrush currents phases The first peak comes during the HSD activation charging of the input capacitor of the module and the second peak after the ignition of the Xenon bulb Therefore in terms of switching losses the xenon module behaves like a capacitive load the first inrush current peak When the input capacitor is charged Vout reaches nominal current the input current falls down usually almost zero until the ignition starts usually after a few ms delay This second inrush phase is not contributing to the turn on switching loss since the HSD is already turned on The losses during HSD deactivation are usually negligible due to the capacitive character of the load Switching losses measurement example e Veat 16V e Temperature 23 C e Load Xenon lamp Phillips D2S 35 W Ballast Hella 5DV 008 290 00 e Device VN7016AJ Figure 70 Xenon load slew rate switching losses VN7016AJ LeCroy LeCroy GAPG1127131003MS Measured values Won 3 1 mJ dVoyt dt on 0 8 16 V 44 us 0 29 V us DocID028098 Rev 1 Ly UM1922 Load compatibility 6 3 6 3 1 Wore OmJ dVout dt orr 0 8 16 V 251 uS 0 051 V us During the HSD channel activation the xenon module behaves like capacitive load waveforms losses eq
153. low to high 139 Open load without pull up timings llsssleele I 141 Open load with pull up timings liliis III 141 Short circuit to Vgarr timings 00 IRR 142 Power limitation or overtemperature waveforms in autorestart mode 142 Power limitation or overtemperature waveforms in lacth mode 142 eMIOS PWM generation mode principle 0 0 00 eee tee eee 143 SPC extended ADC channels block diagram llli illie 144 Cgense diagnostic approach principle s s s saanunna ee eee 144 Example of connection of multiple HSDs to SPC using external ADC MUX control 145 SPC560Bxx example MultiSense trigger points 000 eee eee eee 147 Low pass filter connection 0 0 0 0 cee eee 148 GND voltage shift 22 llis 149 Voc monitor transfer function 6 eee 150 Example MultiSense reading on multiple HSDs with GND shift compensation 151 GND shift measurement position example 0 0 000 cee eee 152 Direct connection of SE pins not recommended 0 eee eee 153 Proper connection of SE pinS 1 2 e 154 Direct connection of SE pins not recommended 00 eee eee ee 155 Direct connection of SE pins not recommended 00 0 cee eee eee 156 Direct connection of SE pins not recommended during loss of GND 157 Paralleling of inputs summary 0 0 000 eae 157 Direct connection of Mu
154. ltiSense pins not recommended 0 00000 158 Safe solution for paralleling MultiSense pins 0 000 c cece eee eee 159 Direct connection of MultiSense pins not recommended 00000e00 160 Direct connection of MultiSense pins not recommended 2 00 00 161 Paralleling of MultiSense summary 0 000 cece eens 162 Common GND network with different supply lines not recommended 162 Test setup paralleling of outputs load current sharing 0 2 200 eae 163 Sharing of load current Voy regulation VND7020AJ 2 0 2 0 0 000 eene 164 Current sense behavior at low current VND7020AJ 0 0000 e eee eee 164 Sharing of load current Voy regulation VND7140AJ sleseseeeeeense 164 Current sense behavior at low current VND7140AJ isses eee eee 165 Behavior during overload condition VND7040AJ Ch 0 Ch 1 00005 166 DoclD028098 Rev 1 9 196 List of figures UM1922 Figure 141 Figure 142 Figure 143 Figure 144 Figure 145 Figure 146 Figure 147 Figure 148 Figure 149 Figure 150 Figure 151 Figure 152 Figure 153 Figure 154 Figure 155 Figure 156 Figure 157 Figure 158 Figure 159 Figure 160 Figure 161 Figure 162 Figure 163 Figure 164 Figure 165 10 196 Test setup paralleling of outputs inductive loads 0002020e eee aes 167 Bulb with 10 uH VND7040AJ Ch 0 Ch 1 2
155. ltiSense voltage saturation VND7020AJ Rsgwse selected in order to have Vsense 2 V at lout 2 3A Considering for sake of simplicity Ko at 3 A 2755 typical value gt Isense 1 089 mA Rsense 1 84 KQ Given a Vsense_sat minimum given in the datasheets of 5 V the maximum Isense 5 V 1 84 KQ 2 72 mA so to have still linearity and assuming that Ko remains constant the maximum lour 7 5 A DoclD028098 Rev 1 119 196 MultiSense analogue current sense UM1922 120 196 In other words with the selected Rgense any load current greater than 7 5 A will produce the same Vsgwsr see Figure 90 Figure 90 Vsense saturation example Veense Saturation 6 4 F VSENSE SAT 5 RS a mmm ap a aoa VsenselV w loul A GAPG1127131803MS Moreover care must be taken to prevent the current mirror output from saturation then causing again the Isense no longer to be proportional to loyrt This normally happens when the maximum current from the current mirror is reached and corresponds to the minimum value of the parameter Isense sat IsENSE sar Minimum reported in the datasheets Example 2 MultiSense current saturation VND7020AJ Rsgwse selected in order to have Vsense 2 V at lour 3A Considering an overload current of 6 A at 4 V of MultiSense pin Analog Voltage and ISENSE_SAT 4 mA minimum Rgense has to fulfill the following formula V SENSE _ 4V 1kQ R gt SENSE SE
156. lue of a capacitor to discharge the capacitance to be charged is the capacitance of the integrated circuit to its surroundings The discharge path consisting only of the circuit s pin and the arc formed between pin and the metal surface has very little impedance to limit current In the Field Induced CDM the most popular implementation the integrated circuit is placed pins up on top of a field plate with only a thin insulator between the circuit and the field plate The thin space between the circuit and the field plate creates a capacitance whose value depends on the size of the integrated circuit and the package geometry A ground plane is positioned by a pogo pin over the field plate as shown in Figure 154 Figure 154 ESD charge device model test scheme 509 ea Coax 19 Ground Circular Plate oom E 4 P gt zu HV Pogo Pin E ES 7 Supply Insular 100MO Pd Field Plate lt To perform the CDM test an uncharged circuit is placed on the field plate The field plate is charged to a high voltage and the circuit s potential tracks the field plate The ground plane is then moved so that the pogo pin touches the integrated circuit grounding it The result is DoclD028098 Rev 1 183 196 ESD protection UM1922 10 3 184 196 a very fast redistribution of charge between the field plate to ground plate capacitance and the integ
157. m Cu thickness 35 mm Copper areas minimum pad lay out and 2 cm Ly DoclD028098 Rev 1 33 196 Protection against battery transients UM1922 3 3 1 3 2 3 2 1 34 196 Protection against battery transients Introduction on automotive electrical hazards The automotive environment is the source of many electrical hazards These hazards such as electromagnetic interference electrostatic discharges and other electrical disturbances are generated by various accessories like ignition relay contacts alternator injectors SMPS i e HID front lights and other accessories Because electronic modules are sensitive to electromagnetic disturbances EMI electrostatic discharges ESD and other electrical disturbances caution must be taken wherever electronic modules are used in the automotive environment These hazards can occur directly in the wiring harness in case of conducted hazards or be applied indirectly to the electronic modules by radiation These generated hazards can impact the electronics in two ways either on the data lines or on the supply rail wires depending on the environment Several standards have been produced to model the electrical hazards that are currently found in automobiles As a result manufacturers and suppliers have to consider these standards and have to add protection devices to their modules to fulfill the major obligations imposed by these standards The chapter deals with the robustne
158. ment for reading of both current sense values at low current levels only the sum of these values will ensure correct diagnostic Overload behavior with resistive loads This experiment shows the behavior during the overload conditions on a VND7040AJ sample with paralleled outputs same test setup as for the load current sharing test e Vpar 14V e Temperature 25 C e Device VND7040AJ OUTO OUT1 paralleled e To be checked Behavior during overload condition cold bulb startup DoclD028098 Rev 1 165 196 Paralleling of devices UM1922 8 4 3 166 196 Figure 140 Behavior during overload condition VND7040AJ Ch 0 Ch 1 LeCroy Veense D s a es WT P1 Thase B0 0ms Trigger 5 00 Vidiv 2 00 Vidiv 100 mV div 100 mV div 20 0 msidiv Stop 88 mV 5 00 V offset 2 000 ofst 300 0 mV 200 0 my 1 00MS 5 0 MSisfEdge Positive Conclusion S After turn on of both channels in overload condition both channels are in current limitation and contribute equally to the total load current The current regulation is stable on both channels The first intervention of power limitation turn off comes almost synchronously on both channels However the next power limitation or thermal shutdown cycling is asynchronous The cycling frequency is the same but the phase shift is varying Driving inductive loads The following part checks the load current sharing during the demagne
159. n E oun i 15k ANXI 4 Mutiserse l GND 15k SEn our E Renee 100 470 pF 15 0 l 4mp 18K a L ale 18K l C4 2 outs l l 15k ANPI fH Misese ap l GND i 100 470pF L 4r Reor AKT y B Ly DoclD028098 Rev 1 151 196 MultiSense analogue current sense UM1922 To eliminate the effect of the GND shift variation it is important to measure the GND voltage and Vcc Temp signal in the same time ideally or with a few us delay Possible solutions are shown in the Figure 122 Figure 122 GND shift measurement position example U1 U2 U3 E ase diagnostic on U4 U4 While GPIO SEL2 no Vcc To The best trigger position for the Vcc Temp and the GND voltage measurement is usually after the rising edge of channel with highest phase shift when all PWM channels are already activated At that point the GND signal is stable note that this statement is not valid during power limitation or thermal shutdown a 152 196 DoclD028098 Rev 1 UM1922 Paralleling of devices 8 8 1 a Vear ISO pulse Vear2 Paralleling of devices Paralleling of logic input pins The following chapters describe the paralleling of Logic input pins SE INx SELx LEDx and FaultRST of different HSDs taking into account device technology monolithic HS
160. nal freewheeling diode Steady state operation single turn on turn off PWM operation DocID028098 Rev 1 Ly UM1922 Load compatibility Low inductance TDEMAG lt tworr If the load inductance is relatively low so the stored energy is dissipated within the HSD turn off time tworr the output voltage decays down to 0 or slightly in negative without the activation of the output clamp see Figure 58 Figure 58 Switching losses with low inductance Vin Tpoemac lt tworr I 4 Vour 7 Taon Taon bas lour 7 M0 7 HSD ee t Renn 80 L ET ene eee y Denn Ig c twon ton twoFF GAPG1127130953MS In this case the switching losses can be roughly estimated from equivalent losses with pure resistive load see calculation in previous chapter Since the output current is delayed from the output voltage the losses at turn on phase Won will be lower while the losses at turn off phase Worp will be higher up to factor of 5 in comparison with pure resistive load This factor was found experimentally in condition when the demagnetization time TpgwAG is matching with turn off switching time tworr Measurement example Low inductance Tpemac lt tworr This measurement example compares the switching losses in the VND7040AJ with two different loads pure resistive 13 5 Q and 60 uH at 13 5 Q Conditions
161. nd a GND shift that guarantees device properly driven ON even in the worst case device limits relevant parameters to be taken into account at DoclD028098 Rev 1 45 196 Protection against battery transients UM1922 46 196 device level are minimum Vj and maximum lenp on values are both available in datasheets Experimental trials have led to fix the below range 47 Q lt R1 lt 300 Q in case of 5 V Input logic level and single or double channel Hybrid HSD 18 Q lt R1 lt 300 Q in case of 3 3 V Input logic level and quad channel Hybrid HSD e The simple reverse battery network R1 is not always enough In case of four channels Hybrid HSD a further D R2 network is required in order to keep the GND pin voltage drop as little as possible and avoid usage of big space demanding low ohmic R1 component R2 must be chosen according to the following limits Minimum value must limit the current flowing from Vcc to GND through the internal signal clamp structure during the ISO 2a pulse Maximum value according to maximum GND shift that guarantees device properly driven ON even in the worst case device limits relevant parameters to be taken into account at device level are minimum Vj and maximum lanp on both values are available in datasheets Experimental trials have led to suggest the below range assuming R1 270 Q and drop Voltage on diode of 0 4 V 180 R2 910 In Figure 25 a test setup is used in order to me
162. ne diode voltage drop versus Vcc pin The MultiSense and all logic pins are pulled down as well see clamp structure on Figure 83 The fact that all device pins are pulled so deeply in negative can have the following drawbacks e The GND network diode must have a proper avalanche capability limiting factor during the choice higher cost e A relatively high current injected to the microcontroller 10 mA per pin in case of above example assuming 15 k serial resistors e Negative peak on Vcc pin can influence other devices sharing same supply line or same ground protection network e The level of the negative pulse on Vcg is not exactly known depends on break down voltage of Dawp which is usually not exactly specified 110 196 DoclD028098 Rev 1 Ly UM1922 Load compatibility The above mentioned issues can be eliminated by a proper Capacitor selection or Bidirectional suppressor selection connected between the Vcc pin and module ground This external device provides the demagnetization path and absorbs the demagnetization energy Capacitor selection A minimum capacitor value can be roughly estimated from the energy content stored in the inductor and required suppression level voltage change on the capacitor after the demagnetization phase Energy stored in the inductor E 5 L NI Energy absorbed by the Vcc capacitor E i Cyce Vec Vcc riNAU Where lo Load current at Vcc disconnection V
163. ng concept Periodical unlatch pulse every diagnostic period i e 60ms _ lt _____ Power limitation blanking inrush current of a bulb GAPG1122131128MS A practical example shall further clarify the concept A quad channel device is used in the following conditions e OUTO bulb start up e OUT floating e OUT2 short to GND permanent on e OUTS floating Channel 0 is switched on Channel 1 3 are permanently on The MultiSense multiplexer is switched every 10 ms in order to monitor sequentially the current sense information on channels 0 3 the Tcase temperature information and the Vcc local supply voltage information Consequently it takes 60ms to sample once each diagnostic source On the FaultRST pin a 20 us unlatch pulse is forced once per diagnostic period and 10 ms DoclD028098 Rev 1 Ly UM1922 Usage handling of fault reset and standby blanking pulse is imposed synchronously with the rising edge on INO During bulb inrush Channel 0 operates in power limitation for a few ms Figure 34 FaultRST pin handling example overview 2 a ae met unlatch pulse 20ps every diag cycle 60ms Inrus h current PN LU blanking 10ms Ch d activation seo UJ U UJ UNJ UJ UJ UJ UJ L SEN GAPG1122131129MS While Figure 34 shows an overview about the sequence of periodical unlatch pulses and the blanking pulse on FaultRST pin over several diagnostic
164. ng high dVDS dt 00000 0a eee 190 Test set up for H Bridge cross current lille 190 H Bridge formed by one VND7140AJ and two OMNIFETs II showing the high side freewheeling phase 0 0 0 lh 192 H Bridge formed by one VND7140AJ and two OMNIFETS II showing the high side freewheeling phase 6 cece ee hr 192 H Bridge formed by one VND7012AY and two OMNIFETs II showing the freewheeling via HSD body diode e dae a eke wee ae actos eiat des anaes ob wes 193 4 DoclD028098 Rev 1 UM1922 General items 1 1 General items Overview about MO 7 standard high side drivers The MO 7 standard high side drivers are manufactured using STMicroelectronics proprietary VIPower technology The devices are designed to drive 12 V automotive resistive as well as inductive and capacitive loads connected to ground A 3 3 V and 5 V CMOS compatible interface to a microcontroller unit is provided The products feature a very low quiescent current to preserve battery charge during standby mode Undervoltage shutdown acts below 4 V in order to ensure the loads are driven when charge pump can deliver sufficient power Overvoltage clamp structure protects the devices effectively from ISO 7637 2 2004 E pulses with the exception of load dump pulses unclamped or clamped above 40 V At loss of ground the outputs are safely turned off current injected into the outputs is less than 2 mA At loss of Vcc the outputs a
165. nhecubaswesentharcovunmbrareoncen 44 4 Usage handling of fault reset and standby 48 4 1 Latch off functionality axo au RE RER ERRRRREGOER RE XE 48 4 2 Standby mode 2 22 sigs e REX E RR WEGRRAORR ERR ACHSE RE E EARS E 51 4 3 Flexible blanking time fault reset management 52 2 196 DoclD028098 Rev 1 Ly UM1922 Contents 5 Usage and handling of MultiSense SEL pin 57 5 1 Classification of M0 7 HSDs 0 000 ce ee 57 5 2 X SEL pins truth table device dependant 0000 5 58 5 3 Connection of SEL pins with control logic Microcontroller 59 6 Load compatibility scu saco ear P ad o I RR e HC mh E D 65 6 1 olg LITT 65 6 2 Power loss calculations xs xus a ey eR REA KA E REA RE FEE RR EE 69 6 2 1 Conduction losses ssssssseseeee eee 70 6 2 2 Switching losses sssssslseeee es 73 6 3 Inductive logds ae xiva xs e XAR RAP re ee ee 95 6 3 1 Uni a cT 95 6 3 2 TUEBEOf aus o epe etg deret e epe baal ae teo eden 96 6 3 3 Calculation of dissipated energy 0 cee eee eee eee 97 6 3 4 Selection criterion with reference to I L plot 99 6 3 5 External clamping protection 0 ee eee 102 6 3 6 LOSS Of fh Rr m 109 7 MultiSense analogue current sense 117 7 1 puse o e amp 117 7 2 Principle of MultiSen
166. ns and influence to a hardware connection scheme Example 1 e VN7020AJ VND7020AJ VNQ7140AJ e Common power supply common GND network e Common SE SEL separate MultiSense All three devices are designed in monolithic technology Devices have different number of SEL pins In order to use only one protection resistor on the side of microcontroller there must be used common Vgar power supply as well as the same ground protection network fulfilling conditions for paralleling SELn on monolithic devices Each HSD s MultiSense output is mapped to separate A D input Additional A D channel is used for measurement of GND protection network offset While MultiSense is switched to voltage mode Vgar or TcAsg output level is referred to device ground not to global GND To adjust measured MultiSense value of Vgar or Tease GND offset measured value can be used accordingly DoclD028098 Rev 1 59 196 Usage and handling of MultiSense SEL pin UM1922 VBaT or Tcuip corrected value VsENSE VGND Figure 37 Monolithic devices common power supply rails separate MultiSense IS Vexr 100nF 50V M Common bus for SEn SELO 2 ob Ut u2 U3 as v Von m XL Faust y XY ams x ramsr C i ero Sen K mo sa NW mo X no 1 GPIO 1585 rR m RK nt 15k SEL1 x eo L3 SEn OUTO ouTo IN2 OUTO GPIO n SELO SEn KK ms FaulRST SEL SELO 15k control I GPlO g
167. ns of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved 4 196 196 DoclD028098 Rev 1
168. nt A D imprecision 20 L m a a a u a u a E eee Open Load A D imprecision H K MEASURED y VSENSE_TYP mV t K_MIN 30 VSENSE_MAX mV Calibration point 10 Open Load lourlmA GAPG2101151029CFT Two points calibration How the calibration works To calibrate means to measure on a specific device soldered in a module the K ratio ata given output current by a Vsense reading Since the relation of loyt Isense K is known it is then easy to calculate the K ratio However even if the K ratio measured in a single point eliminates the parametric spread it doesn t eliminate the Vsense variation due to the K dependency on output current This variation can be eliminated doing the following considerations Table 26 and Figure 102 show a Vsense measurement on a sample of VND7020AJ with Table 25 Vsense measurement lour A Vsense IV 1 0 823 2 1 647 3 2 465 4 3 283 5 4 090 Ly DoclD028098 Rev 1 133 196 MultiSense analogue current sense UM1922 134 196 Figure 102 VsENSE vs lout measurement Vsense VS lout lout A The trend is almost linear in the application range and then we can approximate the Vsense trend with the following equation Equation 11 Vsense m louyr a Where m Q is the rectangular coefficient and a V is a constant By inverting this equation it is easy to get a relation where the out
169. nt sense signal during A D conversion It means there must be delay between HSD channel switch ON and ADC sampling at least tpsenseox time After ADC is sampled MUX can be changed to following channel signal Via MA 2 0 Figure 115 Csense diagnostic approach principle gger A D conversion done eMIOSN 1 trigger MUX switching time min 64us tdsense 2H ecMIOSN tri HSD In l E cT l l c Ux o so HSDIn a LL E 2 E Mux 5 AD N MUX ch0 chi Example configuration applying 0 CPU load MUX switching done by microcontroller HW peripherals In the following example two groups of drivers are given Each group consists of two devices maximum can be 4 given by microcontroller A D peripheral number of analogue input channels linked to external multiplexer ANXO 3 see Figure 114 where SEL pins are connected in parallel selecting the same MUX channel on all devices During diagnostic DoclD028098 Rev 1 Ly UM1922 MultiSense analogue current sense groups 1 and 2 are alternated by SE signal every time only one group is active for diagnostic group 2 use inverter on SE signal SPC560Bxx diagnostic Interface is using externally multiplexed A D channels ANXO and ANX1 linked with control SE and SELO 1 pins automatically without any microcontroller load Since quad channel device U4 in Group 2 is used SEL2 pin must be controlled by SW no additional MA pin i
170. nt the device latches off after the first power limitation pulse 170 196 Vbat LeCroy SSE gg SSS loutO lout 10mvs4 a Measure P1 rise C3 P2 fall C3 P3 max C1 P4 P5 P5 value 10 9 V status 10 00 ofst 20 00 V ofst 1 000 V ofst BEES LC 1 00MS 500MS s Edge Positive while the current among the channels is distributed almost equally Conclusion Paralleling of output channels should be restricted to exceptional cases Due to the significant stray inductance of the wire harness a paralleling of output channels implies the exposure to a critical high demagnetization energy in case of short circuit conditions impacting the component lifetime Even a small difference between the channels turn off shapes actual clamping voltage could lead to almost 100 96 current imbalance during the demagnetization phase In worst case all inductive energy is dissipated by only one channel Since the inductive energy is proportional to the square of the load current the stress in the channel could be four times higher in comparison with non parallel operation at half of the current with same inductance Therefore there is a potential risk of damage even at relatively low inductance values in range of standard wire harness In case the paralleling of outputs is required the devices must be configured in latch mode to avoid the repetitive demagnetization stress during the power limitation or thermal shutdown cycling
171. o Voc SENS 0 L No VSENSEH H 0 L Yes 0 H Nominal 0 L No 0 H Diagnostic summary The table below summarizes all failure conditions the Vsense signal behavior and recommendations for diagnostics sampling DoclD028098 Rev 1 139 196 MultiSense analogue current sense UM1922 Table 27 Diagnostics overview Fault condition Signal Value Vin L H Open load Current sense delay response time from rising thout pull Notes without pull up edge of IN pin must be considered tpsENsE2H Waveforms sampling See Figure 108 Vin L H VsENSE VsENSEH ov Delay time from falli Open load rene ane of IN current sense delay response time from rising with pull up considered edge of IN pin must be considered tpsense2H tpsrkoN ANa Velorms See Figure 109 sampling ViN L H VSENSE VSENSEH lt Nominal Delay time from Short circuit to Notes edd of IN Current sense delay response time from rising VBAT ee edge of IN pin must be considered tpsenseon tpsrkoN Mavelenns See Figure 110 sampling Vin L H FR L Power limitation VsENSE OV VSENSEH or over temperature Current sense delay response time from rising Autorestart Notes edge of IN pin must be considered tDSENSE2H mode trip time to PowerLimitation Overtemperature shutdown whatever is longer wvavelorms See Figure 111 sampling DoclD028098 Rev 1 a UM1922 MultiSense
172. oU e e a ST AMONIA a 4 GND l l Vreg l Loss of VCC location I i p Pavaberboard E E E 1 I GND i Y l ST7 I 100 nF I I I I p qp Ow I Fd VND7020AJ 15k NEN i i GPIO i ct FaWRST i I l I GPIO I D INO I l I l apo cch i OUTO d dcc I GPIO SE und d lt a n ae d lec epio 1_ _ seo ud l GPIO t SEL1 OUT LL 24 l VsENsE I I i tha mma I I ADC T 1 L1 Multisense T EN I I ATOpF Rsense GND I I i T p l 2 2k I l l GND l GND i l I l l I l GND l l I I I l I p l surement example VND7020AJ VBAT 14V Temperature 25 C Load Ch0 1mH 3 50 Ch t No load connected Capacitor on device Voc pin Option 1 100 nF Option 2 100 nF 2 2 uF ceramic Option 3 100 nF 100 uF electrolytic GND network Diode STPS2H100 Resistor 4 7 k To be checked Make a Loss of Vcc during normal operation mechanical disconnection of power supply while the channel is active see test setup schematic Monitor following signals Vout Ch 1 Yellow Voc Ch 2 Red VGND Ch 3 Blue louT Ch 4 Green Voc Vawp F1 Yellow Calculated by math function Figure 84 Test setup loss of Vcc monolithic Power Supply Oscilloscope we we m m ee ee ee ee 9 z Sl DoclD028098 Rev 1 113 196 UM1
173. oc Supply voltage VcC FINAL Final voltage on Vcc capacitor after the demagnetization phase If we assume that the whole inductive energy is transferred to the capacitor Ej Ec this yields 12 0 C bb vcc 2 Voc Voc riNAD Calculation example Battery voltage Voc 2 14V e Final voltage on Vcc capacitor Option 1 Vcc riNaAL7 0 V negative voltage fully suppressed Option 2 Vcc riNAL 90 V still safe value in order to avoid the breakdown of Denp with maximum reverse voltage 100 V e Loadinductance L 1 mH e Load current Ilp 4A Option 1 2 Cuec L lo 0 001 4 81 63 uF vec e 0 001 81 Vcc Vcc FINAL gr Option 2 2 lo 42 Cygg L9 3 0001 go 1 48 HF Voc Vcc Fna The minimum capacitor value needed to completely suppress the negative voltage peak on Vcc pin after the loss of Vcc is 81 6 uF If the Vcc drop down to 90 V is accepted still safe level in case of 100 V Denp used the capacitor value can be reduced to 1 48 uF DoclD028098 Rev 1 111 196 Load compatibility UM1922 112 196 Bidirectional suppressor selection A bidirectional suppressor can be used as an alternative to the capacitor Following requirements must be fulfilled e Negative clamping voltage absolute value considered Below the maximum reverse voltage of the GND network diode Above the reverse battery requirement 16 V e Positive clamping voltage Above normal Vgar range 0 16 V
174. oefficient Typical Vsense rc at 25 C and 13 V and with all channels off with Rsense 1 KQ is 2 06 V The temperature coefficient is dVsense rc dT 5 5 mV C The total spread of Vsense Tc at a given temperature between 40 C and 150 C is constant and equal to 85 mV This corresponds to a precision in temperature reading of about 16 C without calibration The precision of MultiSense Tepp monitor can be improved with a calibration this means measuring an operating point of one device Vsense tc for example calibration at 1 V and 25 C and by knowing the dependency of the Vsenge vec With the battery voltage to read the Tcp p value during the real operation i Experimental results show an average dVsEwsge 1c dVcc 0 4 mV V this means dTc dVcc 0 1 ON in the range from 7 V to 18 V DoclD028098 Rev 1 Ly UM1922 MultiSense analogue current sense Moreover the MultiSense signal in Vcc mode depends on the state of the channels experimental results show an increase for each channel turned on of 10 mV this means a positive offset of about 1 8 C 7 3 3 Example on evaluation of Vcc Tease and diagnostic with SPC560Bxx Similar concept shown in the example for Current Sense monitoring can be applied The major difference is consideration of GND offset on monolithic devices Since voltage drop on GND protection depends on varying operating conditions device ground voltage should be monitored for accurate Mult
175. of Vcc condition the C5 capacitor supplies load current for the demagnetization of inductive loads Rsense Rsense resistor will convert the MultiSense output current which is a copy proportional to the load current into a voltage which can be read by the A D Converter of the Microcontroller The Rsgysg should be dimensioned to ensure proper resolution range and granularity to monitor nominal current as well as detecting open load or overload events Typical values of Rgenge are in the range from 1 KQ to 2 7 KO in order to generate typically 1 V 2 V sense voltage at nominal load current Rgense selection must also take into account maximum power dissipation and maximum current injection during reverse battery conditions and ISO 7637 2 2004 E and ISO 7637 2 2011 E pulse 1 transients Refer to Section 7 2 6 Considerations on MultiSense resistor choice for current monitorfor details on Rsgysg dimensioning rules R1 R5 R1 R5 serial resistors are needed on digital inputs in order to limit the current in the input structures as well as in the microcontroller output structures to a safe value during transient and reverse battery conditions A proper value for such resistors is 15 kQ No low ohmic impedance paths to GND such as pull down transistors or capacitors shall be connected directly to the digital inputs In such conditions device ground shift may trigger intrinsic parasitic structures and an unlimited destructive current path from Vcc
176. off functionality might interfere with the load in case it has an inrush characteristic as for example an incandescent bulb a DC motor or a capacitive load The transient current which typically has the highest peak at low ambient DocID028098 Rev 1 Ly UM1922 Usage handling of fault reset and standby temperature and high battery voltage may trigger the power limitation leading to latch off of the HSD In consequence the load will not be turned on Even though the device could be restarted again by toggling FaultRST pin low for a time longer than tj Arcu rsr So that all latches are reset the latch will occur again as long as the device is maintained in latch off mode A possible way to overcome this issue is managing the FaultRST pin in such a way that the latch off functionality is blanked out for a time longer than the time of the inrush of the bulb The following figure is giving an example on how the correct turn on of an incandescent bulb is ensured by means of a 20 ms blanking pulse on FaultRST pin Despite the device toggles in Power Limitation for approximately 10 ms the load is correctly activated with negligible delay Figure 31 FR handling example bulb inrush blanking VNQ7140AJ iX Agilent Technologies THU MAY 171615242012 X Agilent Technologies THU MAY 17 161538 2012 B 225V B sov g 5 00v M 200V B 500A 3 4500r 1009 Stop t B 225V Delay 450 00000us Locmtusns Dent Cd ceed TI RULEHN
177. ol for example in case of DC motors If the PWM signal is applied to the LSD during its off state the inductive load current re circulates in the body diode of theMO 7 HSD If during this phase the HSD input is driven ON the current will keep on flowing through the body diode whilst the HSD remains turned off therefore no active freewheeling is possible In Figure 163 an example with VND7140AJ combined with two OMNIFET II LSDs driving an inductance explains this behavior the current in HS 0 output is plotted as well Ly DoclD028098 Rev 1 191 196 Usage in H Bridge configurations UM1922 Figure Figure 163 H Bridge formed by one VND7140AJ and two OMNIFETS II showing the high side freewheeling phase VND14NV04 VNS3NV04 VND14NV04 VNSSNVO4 WNDIANVOA VNS3NV04 VND14NV04 GND VNS3NV04 164 H Bridge formed by one VND7140AJ and two OMNIFETS II showing the high side freewheeling phase s VOUTO 4pIOUTO H ls 1 B E p rN 3pVBAT 28 VOUT1 Ep VOUTL 100mV A HS 1 LS 0 HS 0 D G3 D D 3B VBAT 20 VOUT1 4D Source 43 Slope LS 0 E ip VOU T O mam 3p VBAT 2p VOUT1 43 Source 5 Slope LS 0 E IM VOU T O Ta rmn miii mmiai imm is The HSD is not able to turn on during inverse current e
178. on in Vcc line while the monolithic device needs an external diode resistor in series with GND pin refer to Chapter 2 Reverse battery protection of this document The different potential on each GND pin hybrid 0 V monolithic Vgar 0 7 V is leading to the activation of both SE clamp structures when Vpgar is below 7 5 V Vsenc_amp two diode voltage drop The resulting current can lead to malfunction or even failure of one or both of the HSDs 4 DoclD028098 Rev 1 UM1922 Paralleling of devices Figure 127 Direct connection of SE pins not recommended during loss of GND A Vaari Veat2 On L 100nF 50V 100nF 50V Multisense 15k 15k 470pF 470pF Rsense Rsense Lossof GND 3 Devo A uc I O GAPG1128131015MS In configuration of separate supply lines where the GND connection of one device is lost positive as well as negative ISO pulses on the associated supply line are not clamped anymore considering no other devices connected to this supply line If the transient voltage is big enough to activate involved structures there could be unlimited current flow between both supply lines throu
179. ontrol signal is using own protection resistor Figure 39 Monolithic devices separate power supply rails common MultiSense Dass I i H 100 nF 50 V LL 100nF 50V VEL Common bus for SELO 2 A vs Ua V 15k Vi l Voo FauiRST FammSr X FaNRST l GPIO INO K L mo l 15k GPIO X INI I SEn 1 X 15k l GPIO SEn ar outo i GPIO SELO SELO X N3 SEL1 I GPIO SEL1 SELO I GPIO sle SEL1 outi L l Multisense cub ln GPIO LC contrat de Multisense L GND 15k i GPlo A SAE SEn ouT2 B 15k i 8 d 100 470 pF erty 15k l ox we Se z l a SEL2 outs I cpio cA l 15k I ND 1 A 5 Multisense 15k GND l AD2 d a GND offset measurement l GND WD3 L3 i 100 470pF l 15k L ra L iE A 470pF 470pF 470 pF R R L we o maf Dono Signals mapping truth table is the same as in Example 2 4 DoclD028098 Rev 1 UM1922 Usage and handling of MultiSense SEL pin Example 4 e VN7004AH E VND7020AJ e Separate power supply lin
180. ough them Nevertheless as precaution a serial protection resistance is suggested between microcontroller and logic pins to limit the current flowing Hybrid devices are fully compliant with the tests level specified in the ISO 7637 2 2004 see the relevant table for more details DoclD028098 Rev 1 41 196 Protection against battery transients UM1922 Figure 21 Internal structures involved during application of ISO 7637 2 2004 pulse 1 in Hybrid HSD and indication of pin voltages g cU ov w Limp Home circuitry i 1 i 100V 5V 2 qc SY 1 id 1 Rprot 4 0V MCU Rprot OUTPUT Rprot Multisense T 1 Rsense av LA a GND GAPG1112141143CFT Anyway to be compliant with the ISO 7637 2 edition 2011 test pulse 1 level IV and 2a level IV it is recommended to adopt a GND network in order to limit the current flowing through the internal clamp structure Due to the presence of such protection network the Negative ISO pulse 1 level IV 150 V for 2 ms is transferred to the GND pin via the 20 V typical clamp voltage Then logic pins could go down to about 130 V see Figure 22 and this would lead to a triggering of parasitic structures on Signal pins Therefore a suitable serial protection resistor between microcontroller and HSD is mandator
181. out is then Equation 15 An easy algorithm can give the M and b values During the EOL the pairs Vsense1 IREF1 and VsENsE Ingro or alternatively only M and b can be stored in the microcontroller relevant EEPROM After the calibration the current sense variation is still influenced by the device temperature Equation 15is still affected by an error proportional to the sense current thermal drift This drift is reported in the datasheet as dK K The drift decreases when increasing the output current e g in the VND7020AJ datasheet the drift is 25 at 0 1 A and it decreases down to 5 when the output current is 9 A 7 2 11 Open load detection in off state e Available if SE pin is set high e Indicated by Vgengen on MultiSense pin e External pull up on the output needed e Possibility to distinguish between open load in off state and short to Vgar using switchable pull up resistor Ly DoclD028098 Rev 1 135 196 MultiSense analogue current sense UM1922 Maximum Rpy calculation during open load condition Switchable resistor Rpy must be selected in order to ensure Voyt gt Voi wax value given in the datasheet considering maximum leakage current for Vo max as well as additional leakage current flowing to GND i e due to humidity Figure 103 Rpy calculation with no load connected Veat MET le FautRST Feu INO lotta E ie gt sen oam on b Miltisense i XK 8 M
182. p OUT OUT m k a Multisen Multi ultisense ultisense Ee es A N A GND GND Reno 4k7 Doo 162 196 DoclD028098 Rev 1 Ly UM1922 Paralleling of devices 8 4 Paralleling of outputs Paralleling of outputs within one device is usually considered when higher current capability is needed In this section is showed the device behavior with paralleled outputs and highlight potential issues especially in combination with inductive loads Considerations and conclusions concerning this chapter are based on experimental measurements on a limited sample size for each indicated part number 8 4 1 Current balancing with resistive load Following experimental measurements show the current sharing between the channel and behavior of current sense with different load current Two MO 7 devices one high and one low ohmic are considered e VBAT 14V e Temperature 25 C e Device VND7020AJ OUTO OUT1 paralleled VND7140AJ OUTO OUT1 paralleled e Tobe checked Sharing of load current amp current sense Behavior at low current Voy regulation Figure 135 Test setup paralleling of outputs load current sharing 3 E Ch1 Ch 2 Ch3 Ch4 9 9 9 o a4 Ly DoclD028098 Rev 1 163 196 Paralleling of devices UM1922 164 196 Figu
183. p of Rps on x Ison is seen in the ground return path when using the N MOS FET A voltage drop of Rps on x ILoap is seen in the power path when using the PMOS FET In the past the primary disadvantage of these circuits has been the high cost of low Rpscon low threshold voltage FETs However advances in semiconductor processing have resulted in FETs that provide minimal drops in small packages The N channel MOSFET is connected in such a way that its gate is driven directly by the battery voltage and its drain is connected to ground In normal condition it is ON whilst a reverse battery event switches it OFF because Ves s 0 and protects the HSD In Figure 8 is reported a generic schematic with N channel MOSFET configuration In this case like for the solution with Diode Resistor network in the GND line the HSD s output stage body diode is forward biased and therefore is conducting during the reverse battery The current is limited by the external load Since no thermal protection works in reverse condition special care must be taken on the total power dissipation in the device During the reverse battery event the peak junction temperature shall remain safely below the maximum allowed junction temperature Ttsp max Considering a voltage drop on the internal body diode of Ve max 0 7 V the resulting power dissipation in the HSD per output channel is Pp 0 7 V li oAp Zij a diagrams reported in HSD datasheets help the user to calculate
184. pin as shown in the following schematics In order to suppress the rectification of noise injected to the sense line it is recommended to add a ceramic filter capacitor between each CS pin and ground However the voltage drop on diodes in series with MultiSense pin can have an influence on the dynamic range of current sense temperature and current sense accuracy There must be also taken in account voltage drop over protection diode while MultiSense output is switched in voltage mode Vgar Temperature signal output or Vsensen fault flag Figure 130 Safe solution for paralleling MultiSense pins A Vas A Vas 4 100nF 50V 100 imul Ut u2 Vcc FR FR ee a Oi 1 1 L H ii 1 JIET Logic H i BRESIL l4 idi g ha sa 9 H OUT OUT a Multi Multi Currontmirror T e X GND 100 470pF 100 470pF GND ads aw Y w ve lt ADC in 15k I 470pF Reuse 8 2 2 Hybrid HSDs supplied from different supply lines Paralleling of MultiSense pins of hybrid HSDs is possible however some precautions in schematic should be applied if the HSDs are supplied from different supply lines Direct connection of MultiSense pins as shown in the next picture is not safe DoclD028098 Rev 1 159 196 Paralleling of devices UM1922 Figure 131 Direct connection of MultiSense pins not recommended Negative or Po
185. put current can be calculated as Equation 12 lout M Vsguse P Instead of loyt Isense K once M S and b are known it is possible to evaluate the lout with a high accuracy leaving only the spread due to the temperature variation The current sense ratio maximum fluctuation is expressed in the datasheet with the parameter dK K maximum relative error in the full MultiSense Vcc and T specification range versus K at Vcc 13 V and T 25 C How to calculate M and b To calculate M and b two simple measurements done at the end of the production line are needed Chosen two reference output currents Inge and Iggpo the relevant Vsense1 and VsENse have to be measured Then these 4 values can be stored in an EEPROM in order to let the microcontroller use this information to calculate M and b using the simple formulas reported below Since we defined loy M Vsense b it is also true that DoclD028098 Rev 1 Ly UM1922 MultiSense analogue current sense Equation 13 Ingp1 M Vgense1 b and Ingp2 M Voenses b Solving these two equations we get the following relations Equation 14 lout M Vsgyse D InEr1 REF2 M pee EL SENSE1 VSENSE2 lREF2 VsENsE1 Ingr1 VSENSE2 b VsENsE1 VSENSE2 Example 5 M b calculation for the chosen device Fixing Inge 2 A and lper2 4 A according to Table 25 we get Vsense1 1 647 V and VsENSE2 3 283 V then M 1 222 S b 0 013 A l
186. r limitation or thermal shutdown e Standby mode all generic input pins IN SE SEL FaultRST low or open A permanent low level on FaultRST pin SE pin SEL pin and all IN pins disables all outputs and sets the devices in standby mode after elapse of standby mode blanking time tp stpy open load diagnostic in off state is disabled Current consumption in this state is Istpy The device reverts to active mode normal operation as soon as at least one of the generic inputs is set high FaultRST pin and Latch off functionality are not present on specific device classes of the MO 7 standard HSD family Table 10 M0 7 HSD devices not featuring latch off functionality and FaultRST pin Octapak SO 8 VN7004AH E VN7040AS VN7007AH VN7050AS VN7140AS Devices listed in Table 10 operate in auto restart mode in case of power limitation or thermal shutdown Latch off functionality The latch off functionality is available when the FaultRST pin logic input is set high This pin is common for all device channels In case an overload occurs the related channel is automatically latched off at the first intervention of either power limitation or thermal shutdown The latch condition is indicated by Vsenseu level on the related multi sense pin Please refer to the truth tables to identify the conditions to detect a latched channel through the Vsensen level on the related multi sense pin 3 DoclD028098 Rev 1 UM1922
187. rated circuit to field plate capacitances 500V is the commonly used value Results relevant to CDM AEC Q100 011 are reported in MO 7 datasheet s Absolute maximum Values Devices performances are guaranteed by margin to failure reported during characterization Design and layout basic suggestions to increase ESD failure point level When the ESD pulse level required to be passed exceeds the standalone device capability the HSD needs an external protection The easiest and less expensive design practice is the use of a ceramic capacitor on the output The capacitor goal is to limit the voltage and then the energy discharged into the device This external capacitor builds a capacitive divider with the internal ESD pulse one see Figure 155 Figure 155 Equivalent circuit for ESD protection dimensioning ESD discharge resistance ESD discharge ap ESD capacitor on HSD ERE output A preliminary estimation of the capacitor value can be obtained applying the following formula Vo V fg Final ESD Cesp Ceyt Where Vesp is the ESD pulse level required Cgsp is the ESD simulator capacitor value and V inal is the maximum allowed voltage across the HSD typically around 45 V It is in any case necessary to verify the choice of the external capacitor given by the above formula with the real test The main reason of that is the behaviour of the capacitor impedance over the frequency More specifically since
188. re 134 Figure 135 Figure 136 Figure 137 Figure 138 Figure 139 Figure 140 Ly Behavior of VSENSE_SAT vs M iiec ewcana ica ean Cita cat Qaid sani oca ar d ul esDa dir Out 121 Behavior of SENSE SAT vs Verona acau Ia pO CIR ade Ex oaa edi ORG doen ova 122 Failure flag indication example 4 sslseleleeee ne 123 MultiSense operation of VND7040AJ in current monitoring with increasing overload and consequent device s latch off due to thermal protection intervention 124 MultiSense in TCHIP mode behavior versus RSENSE for VND7140AJ at Voc 14 V and TG 25 9 Ls essi emu aue Led xe Iber ad Ged eer atl dane dum Laon ted ia 126 MultiSense in Voc mode behavior versus RSENSE for VND7140AJ at Voc 14 V and Me om LT 126 Bulb LED diagnostic example 0 000 cece I 128 Minimum ON time for correct Vsense sampling llle 129 Switched current sense resistor example 0000 cece eee eee eee 130 Example of single point calibration at low current for VND7020AJ 24 133 Vsense VS IOUT measurement 0 0 eee 134 Rpy calculation with no load connected n asnasa ee eee 136 Rpy calculation with load connected n nasaan annann ee 137 Analogue HSD open load detection in off state 1 2 0 2 00 02 eee 138 Open load short to Vcc detection in OFF state delay after IN is set from low to high 138 Open load short to Vcc detection in OFF state delay after SE is set from
189. re 136 Sharing of load current Voy regulation VND7020AJ Load current sharing 96 100 80 60 40 20 0 1 2 3 Load current A 4 1 2 3 Load current A GAPG1128131022MS 4 5 Figure 137 Current sense behavior at low current VND7020AJ 2 Vsense0 Vsensel Vsense V Re 1 2 Load current A 3 4 Figure 138 Sharing of load current Voy regulation VND7140AJ Load current sharing 96 0 2 0 4 0 6 Load current A 0 8 100 0 2 04 06 08 1 Load current A GAPG1128131024MS DoclD028098 Rev 1 UM1922 Paralleling of devices 8 4 2 Figure 139 Current sense behavior at low current VND7140AJ 1 VsenseO 0 8 x Vsense1 0 6 a z 90 4 2 0 2 0 0 01 02 03 04 05 0 6 Load current A Conclusion The current balancing is very good at high current levels when the Drain Source voltage is above 30 mV approximately half of the nominal output current Reducing the load current increases the current unbalance up to 100 at very low current levels since the outputs operates in voltage regulation mode 20 mV typically The current sense values well correspond to actual output currents This leads to the require
190. re also safely turned off but special care must be taken when inductive loads are driven since additional external protection is required to absorb the demagnetization energy refer to Chapter 6 Load compatibility Reverse battery protection is provided in conjunction with external components for monolithic standard high side drivers whilst hybrid high side drivers are reverse battery protected by self turn on of output channels without the need of external components refer to Chapter 2 Reverse battery protection Note that no protection features are operating under reverse battery conditions MO 7 standard high side drivers integrate advanced protective functions such as load current limitation overload active management by power limitation and overtemperature shutdown with configurable latch off A FaultRST pin unlatches the output in case of fault or disables the latch off functionality A dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including e Proportional load current sense e Supply voltage feedback e Chip temperature sense e Detection of overload e Short circuit to ground e Shortto Vcc and e Off state open load A SenseEnable pin allows off state diagnosis to be disabled when it is needed to send the module in low power mode Moreover thanks to the sense enable functionality it is possible to share one common external sense resistor among several devices and so to man
191. rect operation of connected load module Since there are several variables and conditions depending on application there is no calculation provided in this chapter DoclD028098 Rev 1 91 196 Load compatibility UM1922 The following measurement was performed on several different parts Rpson classes in order to determine the turn on switching loss slew rate and maximum possible capacitance which don t trigger the device protection The devices were loaded by an electrolytic capacitor or parallel combination of capacitors and 10 kQ resistor for the discharge Conditions e VBAT 16V e Temperature 23 C e Device Load 10 kO pull down resistor connected in parallel for discharge VND7140AJ Ch 0 10 uF 22 UF 32 uF 10 22 44 uF 22 22 76 UF 22422422410 88 UF 22422422422 VND7040Au Ch 0 100 uF 220 UF 320 uF 1004220 440 uF 220220 660 uF 22042204220 VND7020Au Ch 0 220 UF 440 uF 220220 1220 uF 1000 220 1440 uF 1000 220 220 2200 uF 3200 uF 2200 1000 VN7016AJ 220 UF 440 uF 220 220 1000 uF 2200 uF 2640 uF 2200 220 220 3200 uF 2200 1000 VN7004AH E 220 uF 440 uF 220 220 2200 uF 3200 uF 2200 1000 4700 uF 5700 pF 4700 1000 92 196 DoclD028098 Rev 1 Ly UM1922 Load compatibility Used capacitors 1 uF 50V ESR 1 70 10 uF 25V ESR 1Q 22 uF 25V ESR 0 7 Q 100 uF 50V ESR 0 17 Q 220 uF 35V ESR
192. res supposing following conditions Load resistance Rioap 9 Q Wiring inductances L 5yH in case of very long cabling Initial current lg 2 7 A Applying Equation 2 yields a Tpemac 0 4 us lt lt tb STBY min Example with short circuit with long wire harness In case of a resistive load connected via long wires supposing following conditions Load resistance Rioap 100 Q Wiring inductances L 5 uH in case of very long cabling Initial current lo 130 A liiuQ max lowest ohmic monolithic HSD VN7010AJ Applying Equation 2 yields a Tpemag 180s lt lt lp STBY min This demagnetization phase lasts very short time in comparison to the standby delay time SO in case of not highly inductive loads no GND resistor is needed in parallel to the GND diode N channel MOSFET in GND line In comparison to the solutions described in the previous chapters reverse polarity protection with MOSFETS offer two main advantages lower power losses and minimal voltage drop Generally the MOSFET s body diode is oriented in the direction of normal current flow When the battery is installed incorrectly the N MOS P MOS FET s gate voltage is low high preventing it from turning ON When the battery is properly installed and the portable equipment is powered the N MOS P MOS FET s gate voltage is taken high low and its channel shorts out the diode DocID028098 Rev 1 Ly UM1922 Reverse battery protection A voltage dro
193. rrent Sense Ch2 L H H H Voc Sense Voc Sense Current Sense Ch3 H L L H Tcouip Sense H L H H Voc Sense H H L H Tcuip Sense H H H H Vcc Sense Devices list 9 d VND7004AY E p VN7010AJ VND7012AY VNQ7040AY E VN7016AJ VND7020AJ i 8 VN7020AJ VND7030AJ 68 VN7040AJ VND7040AJ VNQ7040AY VN7050AJ VND7050AJ VN7140AJ VND7140AJ VNQ7140AJ DoclD028098 Rev 1 a UM1922 Usage and handling of MultiSense SEL pin 5 3 Table 15 Reduced logic implementation only current sense signal no TcHip NO Vcc SEL SEL SE MultiSense output signal Quad channel control signals Single channel control signal X X L High Z High Z L L H Current Sense Current Sense ChO L H H Current Sense Ch1 H L H Current Sense Ch2 H H H Current Sense Ch3 Devices list VN7004AH E VNQ7050AJ Only n d has VN7007AH VN7040AS VN7050AS VN7140AS Connection of SEL pins with control logic Microcontroller SEL pins are usually driven by microcontroller in order to select MultiSense output signal for diagnostic purposes In order to save microcontroller pins multiple devices SEL pins can be driven in parallel sharing the same Microcontroller pins To protect devices and Microcontroller from disturbances or possible damage there are valid recommendations for paralleling of SEL pins for details see Chapter 11 Usage in H Bridge configurations The following examples show possible combinatio
194. rs to be the best compromise between the GND shift safety and power dissipation during static reverse battery condition 50 mW The value of the resistor should be low enough to be sure that the negative voltage at the GND pin is suppressed as much as necessary to keep the device off This means the Venp should be kept above 1 3 V The minimum resistor value is determined by the maximum DC reverse ground pin current of the HSD in reverse battery condition VBAT reverse _ 16V 809 2 200mA Rend 2 GND reverse max In order to keep the power dissipation on the resistor during reverse battery condition as low as possible it is recommended to select the resistor value close to the maximum value 4 7 k Ly DoclD028098 Rev 1 23 196 Reverse battery protection UM1922 2 2 3 24 196 Summary dimensioning of the resistor Resistor recommended if TpEMaG gt fp srBY Resistance 4 7 KQ or lower Voltage capability min 150 V ISO 7637 2 2011 E pulse 1 at level IV min 100 V ISO 7637 2 2004 E pulse 1 at level IV Power dissipation reverse battery min 50 mW 4 7 KQ Example with relay coil In case of a relay coil connected supposing following conditions Load resistance Rioap 90 Q Wiring inductances L 270 mH Initial current lg 0 14 A Applying Equation 2 yields a Tpemac 1 0 ms gt tp stay Example with resistive load with long wire harness In case of a resistive load connected via long wi
195. s available In this example SW controls alternation between current sense signals and Vcc Tc signals on quad channel HSD U4 Figure 116 Example of connection of multiple HSDs to SPC using external ADC MUX Group Goup2 Verri Voo ag 10rF 50V 10nF50V uw w Voo FaitRST 15k loc 15k I eno v FaliRST L E nm l mo INO x INO l sau 15k p MAI X Hm X m S amp m om oUm I a2 15k E cAO S S amp 15k p l sao seo 15k 15k MOsdtven PIO LL E oun E sau am o l E l 8 Mutisense M s l oS ac Seo RUE 100 470pF i MOSdivencro 100 470 pF ER i 15k JL ANXC AKT y o A Ras i amp l K Vero d ac e ey RERUM 100nF50v N A t3 UA 15k 15k I m FaJiRST FAREET ro B 15k l eo m N 15 l outro X m or B 15k NEN l Sn INS l 15k T sa oun E Qum 15k ANX 4 Mulisense GND 15k Sen our nz E 15 Pau 100 470 pF sib 4o 15k sau m 2 15k sa2 ours l T Milserse GND LE 100 470pF Prot AKT y Dx In Table 28 the mapping between SEL SE
196. se signal generation 0 00 ee eee 118 7 2 1 Current monitor 0 000 cee 119 7 2 2 Normal operation channel ON no fault SE active 119 7 2 3 Current monitoring range of linear operation 119 7 2 4 Impact of the output voltage to the MultiSense output 122 7 2 5 Failure flag indication llle 122 7 2 6 Considerations on MultiSense resistor choice for current monitor 124 7 2 7 Usage when multiplexing several devices 2 0000 127 7 2 8 LED diagQnostiG nra ee Paine a bee ea e eA RR ap EES ad 127 7 2 9 Diagnostic with paralleled loads partial load detection 130 7 2 10 K factor calibration method 0 cee ee 131 7 2 11 Open load detection in off state 0 000 eee eee 135 7 2 12 MultiSense diagnostic evaluation with SPC560Bxx 142 7 2 13 MultiSense low pass filtering 0 00 cece eee ee 148 73 Tease Vcc device dependent 2 02 222 ccc es eios 148 7 3 1 oen 149 Ly DoclD028098 Rev 1 3 196 Contents UM1922 7 3 2 Case temperature monitor llli 150 7 3 8 Example on evaluation of Voc Tease and diagnostic with SPC560Bxx DTI 15 8 Paralleling of devices eesseleeeeeesree 153 8 1 Paralleling of logic input pins llllslllsesseenlesssrse 153 8 1 1 Monolithic HSDs supplied from different supply lines
197. sharing the same GND network In case of separated supply lines or separated GND protection networks we should use additional components to ensure a safe operation under conditions in automotive environment ISO pulses reverse battery Monolithic HSDs supplied from different supply lines Paralleling of MultiSense pins of monolithic HSDs is possible however some precautions in schematic should be applied if the HSDs are supplied from different supply lines Direct connection of MultiSense pins as shown in the next picture is not safe Figure 129 Direct connection of MultiSense pins not recommended Vee u1 100nF 50V Loss of Vbat2 OE Ei SENSE Multisense 4 L 1 ADC in i 15k Rus Vsense influenced AKT y Dono 470pF Rsense GAPG1128131016MS 158 196 Direct connection of MultiSense pins is not safe in the following cases e Negative voltage surge on either on Vgar or VBAT2 e Positive voltage surge either on Vgat or Vpgaro while Device GND pin disconnected Dgwp not used resistor protection only Positive pulse energy higher than the HSD or Denp capability all paralleled
198. similar Mix of monolithic and hybrid HSDs Paralleling of SE pins of monolithic and hybrid HSD is possible however some precautions in schematic must be applied The direct connection of SE Pins as shown in Figure 126 is not safe even if we consider the same power supply for both devices DoclD028098 Rev 1 155 196 Paralleling of devices UM1922 Figure 126 Direct connection of SE pins not recommended Ts ISO pulse L 100nF 50V 100nF 50V Reverse battery condition or negative ISO pulse Multisense Multisense 15k 15k 470pF 470pF Rsense Rsense e A uc I O GAPG1128131014MS 156 196 Direct connection of SE pins is not safe in the following cases e Reverse battery single supply line considered e Negative ISO pulse single supply line considered e Loss of GND connection separate supply lines considered ISO pulse Due to the different concepts of reverse battery protection of hybrid and monolithic devices there is a way for unlimited current flow between both devices in case of reverse battery condition The hybrid device has an integrated reverse battery protecti
199. sitive ISO pulse Van ISO pulse L 100nF 50V 100nF 50V a Multisense Multisense 470pF GAPG1129131018MS 8 2 3 160 196 Direct connection of MultiSense pins is not safe in the following case Loss of GND connection If the GND connection of one device is lost positive as well as negative ISO pulses on the associated supply line are not clamped anymore considering no other devices connected on this supply line If the transient voltage is big enough to activate involved clamp structures there could be an unlimited current flow between both supply lines through the MultiSense pins This current could lead to malfunction or even failure of one or both of the HSDs The mechanism current path is graphically explained on Figure 131 The ISO transient is applied on supply line of device U2 In case of negative ISO pulse the current flows via negative clamp of internal reverse battery protection and MultiSense structure of device U2 17 V drop and MultiSense GND clamp of device U1 15 V clamp In case of positive ISO pulse the current flows via Vcc MultiSense clamp of device U2 50 V clamp and MultiSense GND clamp of device U1 7 V clamp In order to ensure a valid current sense sign
200. son law A repetitive demagnetization energy causing a temperature variation above 60 K will cause a shorter life time These considerations lead to two simple design rules e The energy has to be below the energy the device can withstand at a given inductance e Incase of a repetitive pulse the average temperature variation of the device should not exceed 60 K at turn off To fulfill these rules the designer has to calculate the energy dissipated in the HSD at turn off and then to compare this number with the datasheet values as shown in the following example Example Check if the VND7020AJ device can safely drive the inductive load 2 2 mH at 4 O under following conditions e Battery voltage Vegart 16 V e HSD VND7020AJ e Load resistance R 40 e Load inductance L 2 2 mH e Load current at turn off event lo Vgar R 16 V 4O 4A e Power clamping voltage VcLAMP 46 V typical value considered Step 1 Demagnetization voltage calculation using Equation 1 VpEMaG VBar VcLAMP 16 46 30V Step 2 Demagnetization time calculation using Equation 2 L Poeuact tto F E 089 jp ates TpEMAG g I vacua 1 EN NN 235us Step 3 Calculation of energy dissipated in the HSD using Equation 6 Vaar VpEMAG VpEMaqa lo R Eusp wear EPEMAO L 1 voe In IVpEuag lo P z R IVpEMAG 16 30 4 Step 4 HSD datasheet analysis 0 0022 4 4 80 in 20 1mJ The maximum demagnetization ener
201. ss of MO L7 monolithic devices submitted to ISO7637 2 2004 and ISO7637 2 2011 disturbances on the battery line and mounted in the typical application scheme Source of hazard on automotive Conducted hazards These hazards occur directly in the cable harness They are generated by inductive loads like electro valves solenoids alternators etc The schematic in Figure 16 is a typical configuration Figure 16 Conducted hazards Source of Eaui quipment distrubances mm n protection GAPG1122131103MS DoclD028098 Rev 1 Ly UM1922 Protection against battery transients 3 3 These hazards are generated by high current switching like relay contact high current MOS or IGBT switches ignition systems etc The electromagnetic field generated by these circuits directly affects lines or modules near the source of the electromagnetic radiation The schematic diagram in Figure 17 indicates how electromagnetic radiation creates such hazards as electromagnetic interference in electronic modules Figure 17 Radiated hazards Equipment needing protection GAPG1122131104MS Propagation of electrical hazards on the supply rail Transients that are generated on the supply rail range mainly concern ISO7637 2 and 8010605 standards The most energetic transients are those resulting from load dump and jump start But all other hazards may affect the normal operation of electronic modu
202. suffix in the part number is referring to is indicated as well Table 13 Classification of MO 7 HSDs Typical Ron 1 channel 2 channels 4 channels 4mQ VN7004AH E VND7004AY 7 mO VN7007AH 10 mo VN7010AJ 12mO VND7012AY 16 mQ VN7016AJ 20 mQ VN7020AJ 2 VND7020AJ 2 30 mQ VND7030AJ 2 40 mQ PCS VND7040AJ VNQ7040AY 50 mQ eee VND7050AJ VNQ7050AJ2 140 mQ Mor VND70140AJ VNQ7140AN 1 Hybrid HSD 2 Monolithic HSD Note Final suffix J PowerSS0 16 H OctaPAK S SO 8 Y PowerSSO 36 Ly DoclD028098 Rev 1 57 196 Usage and handling of MultiSense SEL pin UM1922 5 2 58 196 SEL pins truth table device dependant There are defined two main categories e Full logic implementation provide output current sense Vcc and Tepp sensing e Reduced logic implementation only current sense of output s Complete encoding and its mapping to devices can be found in the following tables different colors show mapping between device and SEL pins used Table 14 Full logic implementation SEL SEL SELo SE MultiSense output signal Quad channel control signals Double channel control signals Single channel control signals X X X L Hi Z Hi Z Hi Z L L L H Current Sense ChO Current Sense ChO L L H H ISTE Current Sense Ch1 Current Sense Ch1 L H L H Tcuip Sense Tcuip Sense Cu
203. t is considered at the beginning of turn off phase Assuming Tpemag gt gt tworp the switching losses can be calculated as follows Turn on energy loss J Turn off energy loss J VpEMaaG VBAT V 1 R Worr Moemaal Year R lo Vpemacl in DEMAG BENAGI 0 R IVbEMaG Losses during transition phases twon and tworr neglected Calculation example single turn on off event e Load 20 mH at 13 5 Q e Veat 16V e VpEMAG 30 V Vgar 46 e Io 1 185 A Vgaz 13 5 Q L in DEMAG lo R T RE In 30 1 185 13 5 DEMAG R IVpEMAG _ 0 02 18 5 30 633us Won 0 TpEMAG gt gt Twon 633 us gt gt 60 us condition fulfilled Ly DoclD028098 Rev 1 83 196 Load compatibility UM1922 84 196 IV V IV lg R DEMAG VBAT DEMAG lo Wore Moemaal aT n lo Voemacl invoewac t7 R IVbEMAG E3011 16 02 135 1 185 30 in C30L 1 185 138 _ 16my 13 5 301 Measurement example comparison with calculation high inductance Tpemac gt tworr Conditions e Vpar 16V e Temperature 23 C e load 20 mH at 13 5 O Device VND7040AJ Figure 61 High inductance TpgyAg gt gt tworr measurement example LeCroy F LeCroy GAPG1127130956MS Measured Tpemaa 6500 us 633 us calculated Measured Won 11 uJ 0 estimated Measured Worr 13 63 mJ 16 mJ calculated Measured losses pure resistive 13 5 Q Woy 139 uJ Wore 157
204. t it is the minimum time for the DUT to be correctly initialized before the application of the next pulse and shall be 2 0 5 s 3 5 Basic application schematic to protect a MO 7 standard monolithic high side driver The hardware design techniques used for an application will establish the baseline immunity performance The purpose of hardware techniques is to protect the device from performance degradation or long term reliability problems Below reported the STM application proposal for protecting monolithic HSDs under the common stress event mentioned in the ISO 7637 2 editions 2004 and 2011 To provide these electronic safeguards manufacturers typically chose either a diode or resistor or capacitor for protecting both data line and supply rails Components used to suppress or control transients as well as their implementation details are described in the next paragraph providing a basic description of how the most typically used components are employed in low cost designs for achieving the desired level of transient immunity Components used to suppress or control transients can be grouped into two main categories e Components that shunt transient currents voltage limiters e Components that block transient currents current limiters Note that depending on the rise time frequency bandwidth of the transient a component may function as either a shunt or a block For instance at a slow rise time low frequency bandwidth an
205. t r SEL1 out L outi L 15k GPIO a e Multisense GND T p Multisense p 1 DOOR iius SEn ouT2 P 1 cpio L9 p I Fires SELO SEL1 I 15k i AD 1 tC SEL2 outs AD2 jJ 15k I AD3 Multisense l NDA 15k GND offset measurement GND I Reese GND 470pH prop Ros i re Truth table shows signals mapping Table 16 Truth table for monolithic devices separate MultiSense A D 1 A D 2 A D 3 SEL SEL SEL SE MultiSense U1 MultiSense U2 MultiSense U3 VN7020AJ VND7020AJ VNQ7140AJ X X X L Hi Z Hi Z Hi Z L L L H Current Sense ChO Current Sense ChO Current Sense L L H H Current Sense Chi Current Sense Ch1 L H L H Tcuip Sense Tcuip Sense Current Sense Ch2 L H H H Voc Sense Voc Sense Current Sense Ch3 H L L H Current Sense Chol Tcuip Sense Current Sense H L H H Current Sense Ch1 Voc Sense H H L H TcuIP Sense TcuiP Sense TcuiP Sense H H H H Voc Sense Voc Sense Voc Sense 1 SEL not applicable output according SEL SEL and SE Example 2 e VN7020AJ VND7020AJ VNQ7140AJ e Common power supply common GND network e Common MultiSense separate SE control The same HSDs are used like in Example 1 but different topology is used separate SE common MultiSense signal This option uses only one A D channel for all HSDs 60 196 DoclD028098 Rev 1 Ly UM1922 Usage and handling of MultiSense SEL pin 4
206. tRST pin handling concept 0 00 cee eh 54 FaultRST pin handling example overview 00000 eee eese 55 FaultRST pin handling example detail of diagnostic period 0 005 56 FaultRST pin handling example detail of unlatch pulse Ch 2 200 56 Monolithic devices common power supply rails separate MultiSense 60 Monolithic devices common power supply rails common MultiSense 61 Monolithic devices separate power supply rails common MultiSense 62 Monolithic and hybrid device separate power supply rails separate MultiSense 63 Hybrid devices separate power supply rails common MultiSense 64 DoclD028098 Rev 1 7 196 List of figures UM1922 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82 Figure 83 Figure 84 Figure 85 Figure 86 Figure 87 Figure 88 Figure 89 Figure 90 Figure 91 8 196 Principle of the setup used for the simulation 0000 cece eee eee eee
207. the SE pin to be pulled negative to 93 V an unlimited current can flow between the devices A positive voltage surge I807637 2 pulse 2a 3b either on Vent or Vgara could lead to the increase of the GND pin voltage in case of missing Dawp Denp failure or GND pin disconnected As soon as this occurs the voltage on SE pin is rising also since a parasitic NPN bipolar structure is activated base positive versus emitter Since the second device with properly connected GND pin doesn t allow the voltage on SE pin to rise above the clamp voltage 76 3 V an unlimited current can flow between the devices This could lead to malfunction or even failure of one or both of the HSDs In order to avoid such failures it is recommended to add a 15 K resistor in series to each SE pin see Figure 124 In principle the same applies to all other logic input pins as well since the clamp structure is similar Figure 124 Proper connection of SE pins 4 DoclD028098 Rev 1 UM1922 Paralleling of devices 8 1 2 Hybrid HSDs supplied from different supply lines Paralleling of SE pins of hybrid HSDs is possible however some precautions in schematic should be applied if the HSDs are supplied from different supply lines Direct connection of SE pins as shown in Figure 125 is not safe Figure 125 Direct connection of SE pins not recommended 2 Vant ISO pulse A vanz 4 Positive ISO pulse
208. the actual current flow Applying nominal voltage on inactive load turn on it takes a certain time depending on time constant t L R to reach nominal current Removing the voltage source from the active load turn off the load inductance tends to continue to drive the current via any available path i e clamp of the HSD by reversing its voltage acts as a source until the stored energy E 21 2 L l0 is dissipated Time needed to dissipate this energy is called demagnetization time Tpemac This time is strongly dependent on the voltage across the load VpgyAg at which the demagnetization is performed higher IVpemacl shorter TpEMAG A typical VDEMAG for MO 7 devices is equal to Vec 46 V Corresponding Tpemac can be calculated as TpgwAG E i DEMAG lo P R VpEMAG neglecting the turn off switching time of the HSD where L load inductance R load resistance and l load current at the beginning of turn off event From these considerations it is obvious that instant power dissipation and switching losses in the HSD are usually higher at turn off phase Since the HSD output behavior voltage current waveforms depends on several factors mainly on the ratio between the demagnetization time and turn off switching time tworr the next analysis of switching losses is divided into the following parts e Low inductance TpgMAg lt tworr e High inductance Tpemac gt tworr e High inductance Tpemac gt tworr with exter
209. the maximum affordable load current for a given PCB layout DoclD028098 Rev 1 25 196 Reverse battery protection UM1922 Figure 8 Generic schematic and test setup with N channel MOSFET in GND line vbat Vreg a uC Vpp 100nF Vi A i SND VND7 GND XXX Vec GND V 15k aie cpio RC VrR FauiRST apio VINO uc 19k Vino ino 15k V cpio INT uc Vii N4 OUTO OUTO 22nF G9 cpio Sen uc 19k VsEn sen ET k ndl d p gpjo sELo uc 19K VsELO selo GND GND 15k V Gpio VSELt uc VseL1 sey OUT1 SUIT TR 15k Ves L 22nF G9 ADC x Multisense ae 470pF Rsense Wino GND GND GND GND ZD1 GND Vbat 15V Inoy R2 1 15k T de GND e y V Gat n channel F MOSFET GND GAPG1121140937CFT Measured values VND7020AJ Table 3 Static reverse battery voltages on pins Reverse battery Normal operation Normal operation Normal operation Voc 16 V standby mode outOzon out1 off out0 on outi on Vcc V 15 99 14 13 97 13 95 Venp V 15 37 0 0 000028 0 000042 Ve ai V 15 92 13 97 13 95 13 94 Ig HA 4 1 0 2 0 2 0 2 Table 3 reports the measurement results on VND7020AJ test vehicle GND voltage on device is dropping to the reverse battery voltage plus the forward voltag
210. tion schematic for a powered test performed on a dual channel device which is the Device Under Test DUT is shown DoclD028098 Rev 1 181 196 ESD protection UM1922 182 196 Figure 153 ESD test application scheme for HSD placed on a powered module Vbat t00nF S SEL1 Yee i OUTO S SELO BIS 10nF T SEn 7 c INO 4 IN1 T FRST 10nF dl LT os M S OUT1 GND 1K 150V Test set up e The wire length between Vgar and DUT Vcc and between board GND and ESD ground plane is minimized ESD Simulator ground is identical to battery ground Both are connected on GND plane e DUT Board is placed above GND plane by means 50 mm thick insulating support e Filtering ceramic X7R series capacitors are placed on Vcc and on outputs e DUT outputs not loaded e n case of unpowered module test the supply voltage is not present and the device signal pins are connected to GND via the commonly used protection resistances Test conditions e Vgaz from real car battery 12 6 V in case of powered module test only Room temperature Test execution e Tests are performed on two typical device configurations in case of powered module test e ESD discharges are applied on output board trace Test procedure e Incremental discharge voltage levels from 1 KV up to 30 KV are applied with 1 KV voltage step e bdischarges on discharge pad OUTx with delay time of 1sec are applied e failure test by
211. tive GAPG1127131709MS Most of the demagnetization energy Figure 85 is absorbed by the Vcc capacitor The voltage peak on the Vcc pin is 80 V The device channel stays on for the whole demagnetization phase 80 us A positive overshoot on Vcg is seen at the end of demagnetization phase due to the resonance between the Vcc capacitor and load inductance DoclD028098 Rev 1 115 196 Load compatibility 116 196 Figure 87 Loss of Vcc VND7020AJ 1 mH 3 5 Q 100 nF 100 pF I LeCroy 1 Cycc 100nF 100pF Vba T A l hs Vout c2 T la i Voc z1Ve xt rm a Vind C3 a Yeoo Vignd A j i Measure P1 rise2080 C1 P2 freq C1 P3 P4 P5 P6 value status amp 5 00 Vidiv 5 00 Vidiv 5 00 Vidiv ERUIT 5 00 Vidiv 500 usidiv Stop 700 mV 5 000 V ofst 5 000 V ofst OmV offset 4 000 A ofst 500 usidi 1 00MS 200 MSis Edge Negative GAPG1127131800MS The demagnetization energy Figure 87 is distributed between the device and Vec capacitor The turn off phase is seen when the Vcc capacitor is discharged below undervoltage Final voltage on Vcg is 1 V DoclD028098 Rev 1 Ly UM1922
212. tization phase at various load conditions standard load with long wire harness high inductance load with or without external freewheeling on VND7040AJ device with paralleled outputs e Vpar 14V e Temperature 25 C e Device amp Load VND7040AJ OUTO OUT1 paralleled Bulb 10 uH wire harness 2 mH 2 8 Q with or without external freewheeling e _ To be checked Demagnetization phase sharing of load current amp current sense With or without external freewheeling DoclD028098 Rev 1 Ly UM1922 Paralleling of devices Figure 141 Test setup paralleling of outputs inductive loads gQ e e Figure 142 Bulb with 10 uH VND7040AJ Ch 0 Ch 1 LeCroy LeCroy Lau et PWM 50 100Hz 4 ead utl COR VIA Fi Vtt Homi GAPG1128131028MS 4 DoclD028098 Rev 1 167 196 Paralleling of devices UM1922 Figure 143 2 mH 2 8 O VND7040AJ Ch 0 Ch 1 WAO edt LOMA mauan E s el 2 eum n pl Q i LIT 700 20 0 mid PILAM IT TT 0 0 midi 200 7 omy 1 00 mean 10 Vote mV 100 pen 100MS 1008 Figure 144 2mH 2 80 with external freewheeling VND7040AJ Ch 0 Ch 1 i led CYOnviA GAPG1128131030MS Significant current imbalance is observed during the turn off phase even at relatively low inductance v
213. to the digital input will be formed Raeup Dawp a reverse polarity protection network between device ground and module ground is needed for monolithic devices The diode prevents unlimited destructive current flow through the Vcc GND clamping structure in case of reverse polarity connection Renp paralleled to Denp avoids device ground dropping to negative voltage during turn off of inductive loads Typical values range from 1 kO to 4 7 kQ higher values reduce power dissipation under reverse battery condition for details refer to Chapter 2 Reverse battery protection Hybrid devices for classification of Hybrid and Monolithic HSDs please refer to Section 5 1 Classification of M0 7 HSDs do not need GND network please refer to Figure 2 in case pulses belonging to ISO 7637 2 2004 E standard are requested to be passed A resistive path in the GND connection of Hybrid devices with Renp gt 300 DoclD028098 Rev 1 Ly UM1922 General items would not properly activate the self turn on of the Power MOS in case of reverse battery the load current would circulate into the Body Diode instead RON in reverse battery conditions with self turn on is indicated in the Hybrid devices datasheets In case ISO 7637 2 2011 E is requested to be fulfilled the same schematic applies except in case ISO pulses 1 level IV and 2a level IV are requested to be passed In this case a GND network must be implemented for details please refer to Section
214. tor During no fault conditions Vout gt Vout msn see datasheet value the current flowing through Main MOS is mirrored through Sense MOS Sense MOS is scaled down as a copy of the Main MOS according to a defined geometric ratio Current is passed through MultiSense Switch Block fully decoupling MultiSense signal from output current In fault conditions internal logic switches to MultiSense mode and delivers constant voltage on the output named Vsensen Temperature Vgar monitor Internal logic is switched to voltage output mode applying output voltage corresponding to temperature or Vcc sensor according to the selected signal 118 196 DoclD028098 Rev 1 ky UM1922 MultiSense analogue current sense 7 2 1 7 2 2 7 2 3 Current monitor When current mode is selected in the MultiSense this output is capable of providing e Current mirror proportional to the load current in normal operation delivering current proportional to the load according to known ratio named K e Diagnostics flag in fault conditions delivering fixed voltage with a certain current capability in case of Power Limitation Overtemperature in on state Short to Vgar Open load in off state with external pull up resistor condition The current delivered by the current sense circuit can be easily converted to a voltage by using an external sense resistor allowing continuous load monitoring and abnormal condition detection Normal operation
215. uJ Won ratio 20 mH versus pure resistive 11 139 0 08x Worp ratio 20 mH versus pure resistive 13630 157 86 8x The measured values correspond to theoretical assumptions and calculations High inductance Tpemac gt tworr With external freewheeling diode An external clamping circuitry i e freewheeling diode is usually used to protect the HSD in case the demagnetization energy is exceeding the energy capability of a given HSD By using a standard freewheeling diode the demagnetization voltage is reduced from 32 V a typical Vpemac Of MO 7 device at Vgar 14 V to approximately 1 V depending on forward voltage of the diode see Figure 62 This has an influence to the demagnetization time lowering Vpemacl increasing TpgyAg as can be derived from the TpgwAG equation DocID028098 Rev 1 Ly UM1922 Load compatibility Figure 62 Switching losses with high inductance and external freewheeling single event MO 7 Reno Vin Tpemac gt tworr ext clamp Vour Load current continues lour via external freewheeling V Vat VNOM ej OUT Inom HSD OUT p p IcLamp 2L bi Freewheeling diode Vour v Denn n t twoN ton tworr GAPG1127130957MS Note The above example explains a single turn on turn off event This means that zero load current is considered at the beginning
216. uivalent to 47 uF capacitor When the input capacitor is charged Vout nominal the input current falls to O until the convertor starts 71 5 ms delay The losses during HSD deactivation are below the measurement resolution capacitive character of the load Inductive loads Switching inductive loads such as relays solenoids motors etc can generate transient voltages of many times the steady state value For example turning off a 12 volt relay coil can easily create a negative spike of several hundred volts The MO 7 high side drivers are well designed to drive such kind of loads in most cases without any external protection Nevertheless there are physical limits for each component that have to be respected in order to decide if an external protection is necessary or not As a feature of the MO 7 drivers it can be highlighted that a relatively high output voltage clamping leads to a fast demagnetization of the inductive load The aim of this chapter is to have a simple guide on how to check the conditions during demagnetization how to select a proper HSD and the external clamping if necessary according to the given load Turn on When a HSD turns on an inductive load the current is increasing with a time constant given by L R values so the nominal load current is not reached immediately This fact should be considered in diagnostics software i e to avoid false open load detection Figure 71 HSD turn on phase with inductiv
217. ulty leg will be submitted to the total battery voltage in case of hard short circuit or to a part of it in case of a weak short circuit with its possible damage A possibility to guarantee the protection in this conditions would be to implement a drain source monitoring of the low side drivers directly via the microcontroller I Os or to use fully protected low side drivers for example LSD belonging to ST s OMNIFET families Cross current events Cross conduction due to MOSFETs delay times A common issue which can affect one leg of a H Bridge occurs when both HSD and LSD are on at the same time This condition called cross current can happen even if it is not intended to drive the HSD and LSD simultaneously and can cause significant extra power dissipation which can become critical especially during PWM driving For instance when the HSD is turned off and the LSD is turned on in order for example to change a motor DoclD028098 Rev 1 Ly UM1922 Usage in H Bridge configurations direction logic propagation delay and the time required to discharge and charge respectively the HSD and LSD gate capacitances can cause the HSD still to be half on when the LSD is turned on Let us consider a practical example where a VND7040AJ is used in combination with two VND14NV04 belonging to the OMNIFET II family to build an H Bridge For the sake of simplicity a resistive load of 4 5 Q is driven The HSD 0 and LSD O0 on the left leg are
218. urn off within 20 us about During this time a relatively high current will flow through the HSD substrate diode The total energy dissipated in the HSD is around 600 uJ which is withstood by the MO 7 HSD family Dedicated ST Reverse FET solution The VN5RO003H E is a device made using STMicroelectronics VIPower technology It is intended to provide reverse battery protection to an electronic module This device which consists of an N channel MOSFET and its driver circuit has two power pins drain and source and a control pin IN see Figure 14 DoclD028098 Rev 1 31 196 Reverse battery protection UM1922 32 196 Figure 14 Reverse polarity protection reverse FET protection VN5R003H E Vbat To system supply GND GAPG2111140944CFT Note that a MOSFET has always an intrinsic anti parallel body diode If the IN voltage versus drain is negative the device is turned ON The MOSFET is fully turned on when applying the battery voltage and the IN pin goes negative versus drain Due to the fact that the Source is at high potential the MOSFET is a high side switch not referring to ground a charge pump circuit is needed to boost the gate voltage over the source voltage to turn the MOSFET on During reverse polarity of the battery no voltage will supply the gate of the MOSFET which will automatically switch off When IN is left open device is in OFF state
219. v 1 161 196 Paralleling of devices UM1922 Figure 133 Paralleling of MultiSense summary Different supply networks Texchnology uis ccm FEO Sp JG SS different VBAT uero RID RE Gier or different GND protection network Multisense in parallel Monolithic Monolithic HSD Multisense Each HSD use diode in series HSD Hybrid Hybrid Multisense Multisense Monolithic Hybrid 100 470 pF 8 3 Paralleling of GND protection network Sharing common ground protection network of monolithic HSDs is safe in case of using the same power supply line If different supply lines are required an external clamp must be present on both supply lines to clamp the negative transients to a voltage lower than the minimum Vc Ap So that Vaart VnNEG peakl lt 40 V During the negative voltage exposure the outputs of all paralleled devices linked to stable battery line turns on since the logic input thresholds are exceeded by pulling the GND pins negative Applying different supply lines without an external clamp protection is not safe in case of e Negative ISO pulse on Vpgar4 or Vgaro Figure 134 Common GND network with different supply lines not recommended Vus A Vama 100nF 50V 100 nF 50V L Voi Ut U2 Vd g N e R O IN IN 1 40 TE Logic Logic Ca a Ca i CQ sen SEn H O SEL SEL
220. voltage on MultiSense line is big enough to activate the MultiSense GND clamp structure there could be an unlimited current flow through both MultiSense pins This current could lead to malfunction or even failure of one or both of the HSDs Loss of either VgAr4 or Vpgaro is leading to wrong current sense signal If Vaato is lost U2 logic part is supplied by U1 current sense signal through the internal Vcc MultiSense clamp structure Therefore the voltage on MultiSense bus will drop and we ll have no accurate Vcense reading anymore If the GND connection of one device is lost Dgnp not used Denp failure or GND pin disconnected positive as well as negative ISO pulses on the associated supply line are not clamped anymore considering no other devices connected to this supply line If the transient voltage is big enough to activate the involved clamp structures there could be an unlimited current flow between both supply lines through the MultiSense pins This current could lead to malfunction or even failure of one or both of the HSDs In order to ensure a valid current sense signal and to protect devices in all previously described cases we can add a diode in series to each MultiSense pin in the same way as already described in case of monolithic devices see previous chapter The following table is summarizing possible combinations of HSDs with paralleled MultiSense outputs relative to the used power supply networks Ly DoclD028098 Re
221. wax V SET IVpEMAG Demagnetization time related to selected point 2 2 mH 5 5 A using Equation 5 0 5 5 T L 0 0022 372us DEMAG VDEMAG 32 5 Note Same calculation as Emax and Tpemag Is performed at 1 mH and 0 1 mH just to see the dependency on inductance see Figure 75 As seen from the calculation the maximum energy related to selected point is 47 1 mJ at 372 us In order to find the energy limit at 235 us either an iterative process can be performed in graphical way repeat the same calculation with different I L point choices until the Tpemac is matching or the following empiric formula can be used where E is the sustainable energy for time t and E2 is sustainable energy corresponding to different application condition time t Ly DoclD028098 Rev 1 101 196 Load compatibility UM1922 6 3 5 102 196 ty 235us E E d 47 1mJ 372us 37 4mJ Conclusion The device is able to safely drive the selected load since the calculated demagnetization energy 20 1 mJ at 235 us is clearly below the maximum allowed demagnetization energy derived from the I L diagram for the repetitive operation Tistart 125 C 37 4 mJ at 235 ps Step 5 Measurement comparison with theory The demagnetization energy dissipated in the HSD was measured by an oscilloscope with mathematical functions The first function F1 shows the actual power dissipation on the HSD Vegar Vout lout the second function
222. x er ENG QU aree e 36 ISO 7637 2 2011 B tee uer Ric or oe tee scc Pawan attendees Re d 37 ISO 7637 2 2004 and 2011 tests and results on monolithic HSDs 41 GND network proposals for Hybrids HSDs 000000 ce ee 45 ISO 7637 2 levels and results for Hybrid HSDs 200 000 c eee eee 47 MO 7 HSD devices not featuring latch off functionality and FaultRST pin 48 Tr thi table use eere teh ew ten e Raia e oe e a GE NUR Ree REA RR RR arn 49 MultiSense multiplexer addressing for a dual channel device 00005 49 Classification of MO 7 HSDs 2 1 0 nent n eee 57 Full logic implementation isss 0 0 0 0 teas 58 Reduced logic implementation only current sense signal no TCHIP no VCC 59 Truth table for monolithic devices separate MultiSense 00000005 60 Truth table for monolithic devices common MultiSense 000000 eens 61 Truth table monolithic hybrid separate MultiSense 0000 0 cea eee 63 Truth table hybrid devices separate supply rails common MultiSense 64 Typical bulb loads for given MO 7 RON class llle 65 VND7040AJ measurement of switching losses versus L in steady state 90 VND7040AJ measurement of switching losses versus L in PWM mode with external freewheeling ido eres urere RP e ene ce ROI p SUPR Se 90 Maximum capacitance on the HSD output no power limitation triggered Tjistart 25
223. xposure 4p IOUTO i MNRMMRHNURURNANNAERANLAR AGAR 4 TCL T CIH iia pLS_1 f p LS_1 y DHS 1 DHS 1 DnL5 0 nis 0 D HS 0 D HS 0 gt Source 42 Slope LS 0 E Active freewheeling turn on the HS 43 Source D Slope LS 0 Y 192 196 DoclD028098 Rev 1 4 UM1922 Usage in H Bridge configurations Another example with one VND7012AY and two VNB35NV04 E is shown in Figure 165 As seen from the measurement the HSD is not able to turn on during the freewheeling phase when the demagnetization current flows to the battery line via the body diode same behavior as in case on monolithic device in previous example Therefore no active freewheeling is possible Figure 165 H Bridge formed by one VND7012AY and two OMNIFETS II showing the freewheeling via HSD body diode Source LS 0 C exposure 49 TOUT _H u ars t zi b lH als Q HS 0 VND7012AY ee p m v t 380VBAT 20 VOUT1 WYOUTOm oe LS 1 DHS n Ls 0 ojis o VNB35NV04 VNB35NV04 3 Source fed sa JUL 30 15 11 57 2013 The HSD is not able to turn on during inverse current GAPG1612141343CFT DoclD028098 Rev 1 193 196 References UM1922 Appendix A References 1 CISPR 25 Vehicles boats and internal combustion engines radio disturbance characteristics limits and methods of measurement for t
224. y mode all diagnostic latches are reset This is also caused by the fact that the FaultRST pin is set low for a time t5 srgy gt ti ATCH RsT The device exits the standby condition as soon as anyone of FaultRST pin SE pin SEL pin or one of the INx pins is set high DoclD028098 Rev 1 51 196 Usage handling of fault reset and standby UM1922 4 3 52 196 Figure 29 Standby mode activation INPUTO jo i oe INPUTL SEn SELO SELL FaultRST IS ON Standby mm t lt t stay mmm t gt tp stay GAPG0810141003CFT The device leaves the Standby mode when any of the above mentioned pins is set high see Figure 30 Figure 30 Standby state diagram Normal Operation INx Low INx High AND OR FaultRST Low FaultRST High t gt tp srBv AND OR SEn Low SEn High AND OR SELx Low SELx High gt Stand by Mode Flexible blanking time fault reset management On one hand the use of the latch off functionality provides significant benefits to the application in terms of safety and reliability due to the very fast reaction and protection against hazardous conditions induced by heavy overload or short circuit events On the other hand it requires from the user a proper selection of the suitable high side driver for a given load in example through load compatibility studies refer to Chapter 6 Load compatibility Concretely the latch
225. y to limit the current flowing through these pins a 42 196 DoclD028098 Rev 1 UM1922 Protection against battery transients Figure 22 Internal structures involved during application of ISO 7637 2 2011 pulse 1 in Hybrid HSD and indication of pin voltages p ov Md Limp Home circuitry i 1 5V i 150V 150V i Rprot 130V MCU Rprot 130V OUTPUT Rprot Vt Multisense X 7 lt 4 Needed for Rsense ry quad li 130V 1 channels device GND GAPG1112141154CFT 3 6 1 Besides since the device inputs may be driven independently from the microcontroller by a separate HW limp home feature which is supplied directly from battery it is mandatory to decouple the signal coming from the microcontroller to the one coming from the Limp home Circuitry in order to avoid any backward supply of one circuit versus the other one The decoupling is ensured by a signal diode placed in series to the Limp Home path connected to the device input as shown in Figure 22 Dimensioning of the series resistors on I O line The resistor value should be calculated according to the maximum injected current to I O pins of the used microcontroller That value can be assumed equal to 10 mA so that the resistors value should be at least

VIPower® M0-7 standard high-side drivers hardware design guide

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VIPower&reg; M0-7 standard high-side drivers hardware design guide

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VIPower® M0-7 standard high-side drivers hardware design guide