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GPIB-1014 User Manual - National Instruments

1. A brief description of the GPIB 1014 interface is given in Chapter 2 along with a functional block diagram see Figure 2 4 The major elements of the GPIB 1014 are discussed in more detail in this chapter with references to signals and circuits shown in the schematic diagram in Appendix A Signal names in the following discussion are referenced in terms of logic value true or false and asserted or not asserted and also in terms of logic level TTL high or low Both positive and negative logic symbols are used in the schematic diagram The terms clear negate unassert reset and set false are synonymous as are set assert and set true Since in the circuit implementation some positive true signals are derived from the inverted output of flip flops these terms are not synonymous with the device signals CLR clear and PR preset VMEbus Interface Address data control and status signals to or from the VMEbus are buffered with LSTTL ASTTL or FTTL logic devices All drivers drive the proper amount of current as required by the VMEbus specification and all receivers present the required bus load as called out by the VMEbus specification Data Lines Two F245 octal bus transceivers connect the VMEbus data lines D15 through DOO to the circuitry on the GPIB 1014 All 16 of these data lines are routed directly to the DMAC while only the lower eight data lines D07 through D00 are connected to the 8 bit data bus of the TLC Slave R
2. Base address 0C Base address 1C Base address 14 Base address 0A Base address 1A Base address 29 Base address 39 Base address 31 Base address 04 Base address 05 Base address 06 Base address 07 Base address 00 Base address 01 Base address 2D Base address FF Base address 25 Base address 27 Base address 101 Base address 105 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Only Read Write Read Write Read Write Read Write Write Only Write Only Chapter 4 VMEbus computers support three transfer sizes for read and write operations 8 16 or 32 bit Table 4 1 shows the size of each GPIB 1014 register For example reading the Memory Transfer Counter Register requires a 16 bit read operation at the indicated address whereas writing to the End Of String Register requires an 8 bit write operation at the indicated address Register Description Table 4 1 divides the GPIB 1014 registers into three different register groups A detailed bit description of each of the registers making up these groups is included later in this chapter The GPIB Interface Register Group consists of 21 registers located in the NEC uPD7210 TLC chip The DMA Register Group consists of 18 registers located in the 68450 DMAC chip The Configuration Register Group contains two registers use
3. Contents Figure 6 3 Figure E 1 Figure E 2 Figure E 3 Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 3 Table 3 Table 3 Table 3 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 6 1 Table Table A 1 Table A 2 A 3 Array Format for Linked Chaining Modes eee 6 21 The GPIB Connector and Signal Assignments eene E 4 Iidem E 5 Sar C ODDISUPAUOD ola ae prende Du pa laid ie eo E 6 Tables GPIB 1014 Signals oic hn ena re T aa Urania bb Eee en Ra na aee oe TRU EN ERE 2 1 uPD7210 Internal GPIB Interface Registers i 2 3 68450 Internal DMA Registers c 2 4 GPIB 1014 Configuration Registers eese 2 5 GPIB 1014 IEEE 488 Interface Capabilities eere 2 13 GPIB 1014 IEEE 1014 Interrupter Compliance Levels 2 15 Programming Values for Default Settings of W3 W4 and WS 3 6 Setting the Address Modifier Code Bits AMS5 AMO see 3 6 GPIB 1014 Pin Assignment on VMEbus Connector P1 3 8 GPIB 1014 Pin Assignment on VMEbus Connector P2 3 9 GPIB 1014 Register MAD sas cscs ceive oe r e opacis to aas ai 4 Clues to Understanding Mnemonics eese nennen 4 3 Multiline GPIB Commands Recognize
4. Register Descriptions Chapter 4 Channel Error Register VMEbus Address Base Address 01 hex Attributes Read Only Internal to DMAC 7 4 3 2 1 0 R 6 5 The Channel Error Register CER is an error condition register The ERR bit of the CSR indicates if there is an error Bits 0 through 4 of the CER indicate what type of error occurred Bit Mnemonic Description 7 51 0 Reserved Bits 4 0r ERROR CODE Error Code 00000 No error 00001 Configuration Error 00010 Operation Timing Error 00011 undefined reserved OOlrr Address error Ollrr Count error 010rr Bus Error 10000 External Abort 10001 Software Abort where rr register or counter code 01 Memory address or memory counter 10 Device address 1 Base address of base counter GPIB 1014 User Manual 4 60 National Instruments Corporation Chapter 4 Register Descriptions Channel Priority Register VMEbus Address Base Address 2D hex Attributes Read Write Internal to DMAC 7 6 5 4 3 2 0 Ae eee SE The Channel Priority Register CPR is used to define the priority level for each channel The priority of a channel is a number from 0 through 3 with 3 being the highest priority level When multiple requests for DMA service are pending at the DMAC the channel with the highest priority receives first service Channel priority is also used to determine which channel is serviced first when multiple channels have interrupts pending If there ar
5. Second ccary address points to last data byte Set CFG2 for carry cycle Start channel 1 o Configure CFG2 without ECC N Channel 0 transfers all bytes Start channel 0 E nable DMA to the CDOR Loop waiting for GPIB error or DMA done Set count to 1 if error occurred GPIB 1014 User Manual Sample Programs DSEND4 btst bne movw subw btst beq subw bra DSEND5 btst bne movw subw addw DSEND6 movb movb movb rts COC CSRO DSEND5 MTCO d1 d1 dO ECC CFG1 DSEND6 1 d0 DSEND6 ECC CFG1 DSEND6 MTC1 d1 d1 d0 1 d0 0 IMR2 STOP CCR1 STOP CCRO GPIB 1014 User Manual Appendix C Calculate number of bytes transferred D S isable DMAs top DMA channels National Instruments Corporation Appendix C National Instruments Corporation Sample Programs KR KKK KKK WRITE ockok ok ok KKK Summary Called to send device dependent data messages when the GPIB 1014 is Controller In Charge DSEND is called when the interface is Idle Controller Assumptions on entry GPIB 1014 is CIC One Listener is addressed and its address is placed in the variable ola The data to be sent is placed in datbuf The variable datct contains the number of bytes to send Actions Set up cmdbuf and cmdct and call CMD to address the GPIB 1014 as Talker to address the Li
6. 094 DAR2 daddr 0A 101 CFG1 00 GPIB 1014 User Manual Set LMR and turn LED green Clear LMR Reset Channel 2 status register Burst mode 16 bit transfer with 68000 dev Mem to dev word xtfr no chain internal req MAC and DAC both count up 5 words 10 bytes transfer 4 byte data address Ex 00200000 4 byte data address Ex 0020000A no interrupt BRO amp BGO no carry cycle enable ROR feature 7 4 National Instruments Corporation Chapter 7 087 080 daddr FF daddr 1 FE daddr 9 F6 CCR2 80 CSR2 81 daddr 0A FF daddr 0B FE daddr 13 hex F6 Diagnostic and Troubleshooting Test Procedures Set data values at source locations Start DMA on Channel 2 DMA completed without error Bit 4 1 if error Verify data values at destination locations 11 Test DMA transfer flyby to GPIB one byte memory read 105 105 00A 004 005 006 000 040 045 029 00C 101 11B 119 007 115 11B 000 040 113 111 101 040 040 CFG2 0A CFG2 08 MTCO 0001 DCRO AO OCRO 02 SCRO 0 CSRO FF CSRI FF OCR1 0 MFCO 06 MARO daddr daddr data CFGI 18 AUXMR 2 ADMR CO CCRO 80 IMR2 20 AUXMR 0 CSRO 81 CSRI 02 ISR1 03 CDOR data CFGI 18 CSRI 02 CSRI 01 Set LMR and turn LED green Clear LMR one byte 4 byte data address any free data area put data byte in memory BRG3 OUT enable ROR feature TLC Reset ton lon Start channel 0 DMA ou
7. 140 141 142 143 144 145 146 147 150 151 152 153 154 155 156 157 160 161 162 163 164 165 166 167 170 171 172 173 174 175 176 177 SPE TCT UNL UNT Dec ASCII kel ON i 104 OB BTATT SDS mmeo aAa 112 CA z 4m mc o n o0 59 119 120 121 122 123 124 125 Me TON lt x 127 Serial Poll Enable Take Control Unlisten Untalk DEL Msg MSAO PPE MSA1 PPE MSA2 PPE MSA3 PPE MSA4 PPE MSAS PPE MSA6 PPE MSA7 PPE MSA8 PPE MSA9 PPE MSA10 PPE MSA11 PPE MSA12 PPE MSA13 PPE MSA14 PPE MSA15 PPE MSA16 PPD MSA17 PPD MSA18 PPD MSA19 PPD MSA20 PPD MSA21 PPD MSA22 PPD MSA23 PPD MSA24 PPD MSA25 PPD MSA26 PPD MSA27 PPD MSA28 PPD MSA29 PPD MSA30 PPD GPIB 1014 User Manual Appendix E Operation of the GPIB This chapter describes the operation of the GPIB Communication among interconnected GPIB devices is achieved by passing messages through the interface system Types of Messages The GPIB carries device dependent messages and interface messages e Device dependent messages often called data or data messages contain device specific information such as programming instructions measurement results machine status and data files e Interface messages manage the bus itself They are usually called commands or command messages Interface messages perform such tasks as initializing the bus addressing and unaddressing devices and setting devic
8. 2 6 master direct memory access 2 5 to 2 6 uPD7210 interface registers 2 3 signals chart 2 1 to 2 2 slave addressing 2 2 to 2 3 slave data 2 3 slave read and write transfers 6 1 W WRITE sample program C 17 to C 18 GPIB 1014 User Manual Index 21 Index National Instruments Corporation Index X X Don t Care Bit 4 42 4 50 XEOS Transmit END with EOS Bit 4 37 XRM External Request Mode Bits 7 through 6 4 51 GPIB 1014 User Manual Index 23 National Instruments Corporation
9. 6 17 operating environment A 1 Operation Control Register OCR 4 53 to 4 54 optional equipment for GPIB 1014 1 3 P P 3 1 Parallel Poll Response Bits 3 through 1 4 36 Parallel Poll Register PPR 4 35 to 4 36 parallel polls conducting 5 23 overview 5 22 responding to 5 24 parts list and schematic diagrams B 1 to B 9 PASS CONTROL PASSC sample program C 21 PCL Peripheral Control Line Bits 1 through 0 4 52 PCS Peripheral Control Status Bit 4 59 PCT Peripheral Control Transition Bit 4 59 4 62 PEND Pending Bit 4 19 physical and electrical characteristics description of 2 1 to 2 2 E 4 GPIB connector and signal assignments illustration E 4 linear configuration illustration E 5 specifications A 1 star configuration illustration E 6 pin assignments See signals power requirement A 1 PPC Parallel Poll Configure command 4 25 PPR See Parallel Poll Register PPR PPU Parallel Poll Unconfigure command 4 26 programmed I O transfers overview 2 8 sending and receiving data 5 19 to 5 20 sending END or EOS 5 20 terminating on END or EOS 5 20 programming Controller function becoming controller in charge CIC and active controller 5 3 going from active to idle 5 5 going from active to standby 5 4 going from standby to active 5 4 sending remote multiline messages commands 5 4 initialization 5 1 to 5 3 interrupts 5 20 to 5 21 parallel polls 5 22 to 5 24 sample programs COMMAND CMD C 2
10. 80 20X CER AX 33 29 715079 01 1 0000 AVX SA105E473ZAA CAP 047UF 50V 80 20 CER AX 34 C30 715079 01 4 0000 AVX SA105E473ZAA CAP 047UF 50V 80 20 CER AX 35 C31 715079 01 1 0000 AVX SA105E473ZAA CAP O47UF 50V 80 20 CER AX 36 C32 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V B0 20X CER AX 37 C33 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX C34 T15079 01 1 0000 AVX SA105E4752AA CAP LOATUE SOV 89 209 CER AX 39 C35 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 40 C36 715079 01 1 0000 AVX SA105E473ZAA CAP O47UF 50V 80 20 CER AX 41 C37 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20X CER AX 42 C38 715079 01 1 0000 AVX SA105E4752AA CAP 047UF 50V 80 20X CER AX 43 C39 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 44 c4O 715079 01 1 0000 AVX SA105E4732AA CAP 0470F 50V 80 20 CER AX 45 C41 715079 01 1 0000 AVX SA105E4722AA CAP O47UF 50V 80 20 CER AK 46 t42 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20X CER AX 47 National Instruments Corporation B 3 GPIB 1014 User Manual Parts List and Schematic Diagrams Appendix B AREER ARATE E ESE ERISA RARE RISA ERAS ob eee Ife eee dede IAI ARIA NIRS AT IAEA III AA III ie SOT AINA IORI SONIA ICA ITEM NO NI PART NO QTY REQD MFR MFR PART PRODUCT DESCRIPTION c43 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 48 Chh 715079 01 1 0000 AVX
11. A bus error that occurs when Channel 0 is active only sets the PCT bit in the CSR of Channel 1 and the ERR bit in the CSR of Channel 0 After an interrupt is generated the VMEbus interrupt handler asks the interrupting source for a status ID byte so that it can branch to the appropriate interrupt service routine Depending upon the value of the ERR bit Channel 1 sends out the Normal Interrupt Vector NIV or Error Interrupt Vector EIV Since all errors are logged it is possible and convenient to use the same vector for NIV and EIV The source of the interrupt must be determined by the interrupt service routine The status of the TLC interrupt can be found by reading the appropriate TLC status registers The status bits in ISRI or ISR2 are all automatically cleared when the register is read even if the conditions are still true If two conditions are true at the same time that is more than one bit in ISRI or ISR2 is set a software copy of the register must be maintained if the program is going to analyze the conditions one at a time Since reading ISRI can clear the INT bit in ISR2 ISR2 must always be read before ISRI The PCL of Channels 0 and 2 are also connected to two GPIB signals so you can directly detect them The PCL of Channel 0 is connected to the GPIB Service Request signal active low This can be used to read the status of the SRQ line at any time or to generate an interrupt when the SRQ line is asserted and the TLC is Contro
12. Address Mode Register ADMR are cleared All other TLC register contents should be considered as undefined while the LMR bit is set and after LMR has been cleared While the TLC internal signal pon is set all Auxiliary Mode Register AUXMR commands are cleared and cannot be executed All other TLC registers can be programmed while pon is set When pon is released or cleared by issuing an Immediate Execute pon auxiliary command to the TLC the interface functions are released from the pon state and the auxiliary commands can be executed The 68450 DMAC is initialized as follows 1 All bits of the General Control Register GCR Device Control Register DCR Operation Control Register OCR Sequence Control Register SCR Channel Control Register CCR Channel Status Register CSR Channel Priority Register CPR and Channel Error Register CER are cleared for all channels This resets the Start STR Continue CNT Channel Active ACT and interrupt generation bits and clears the status and error bits 2 The interrupt vector registers Normal Interrupt Vector Register NIVR and Error Interrupt Vector Register EIVR for all channels are set to OxOF hex A typical programmed initialization sequence for the GPIB 1014 might include the following steps 1 Set and then clear the Local Master Reset LMR bit in Configuration Register 2 CFG2 to place the GPIB 1014 in a known quiescent state 2 Load the two GPIB 1014 Configurat
13. DTB master Unless programmed the GPIB 1014 is a Release When Done RWD master VMEbus Modules Not Provided Because the GPIB 1014 is not designed to be VMEbus System Controller it does not have the following modules e Bus Timer e Arbiter e Interrupt Handler e JACK Daisy Chain Driver e System Clock Driver Serial Clock Driver e Power Monitor Diagnostic Aids The GPIB 1014 is designed to allow stand alone verification of I O and DMA functions See Chapter 7 Diagnostic and Troubleshooting Test Procedures for details Data Transfer Features The GPIB 1014 can be used to transfer data to and from the GPIB using Direct Memory Access DMA and programmed I O The overall throughput is dependent upon the following parameters e The number of GPIB commands sent e The amount of time spent setting up the GPIB 1014 DMA transfers e The size of the DMA data buffers number of bytes transferred in one DMA operation Operating system overhead Interrupt service time e VMEbus memory response time DS low to DTACK low National Instruments Corporation 2 7 GPIB 1014 User Manual General Description Chapter 2 e GPIB Listener response time DAV low to NDAC high e GPIB Talker response time NRFD high to DAV low e GPIB 1014 transfer mode Cycle Steal with hold programmable timeout TI timing high speed Transfer rates of 250 to 350 kbytes sec can be expected in typical systems and rates up to 500 kbytes sec can
14. GTM ACHN OCR1 movl ccary BAR1 movw 2 BTC1 movl HLDA ccary d0 d1 1 d1 d1 MTCO movw subw movw a0 d2 d2 d1 d1 ccary 6 movl addl movl movb BRG ECC IN CFG2 movb AUXRA 022 AUXMR GO CCR1 RCV2 movb bra RCV1 BRG IN CFG2 AUXRA AUXMR do MTC0 movb movb movw RCV2 movb movb movb GO CCRO DMAI IMR2 FH AUXMR RCV3 btst bne btst beq ENDRX ISR1 RCV4 PCT CSRI1 RCV3 GPIB 1014 User Manual Appendix C Comments Set DMA transfer mode Set control registers Clear status registers Point channel 0 to buffer Is GPIB 1014 Controller In Charge Yes set up carry cycle feature Enable chaining on channel 1 Point channel 1 to ccary 2 elements in ccary First ccary address points to HLDA Set channel 0 transfer count to transfer all but the last byte Second ccary address points to last data byte configure CFG2 for carry cycle Set HLDE and BIN in AUXRA Start channel 1 No no carry cycle Clear any HLDE or HLDA in effect Channel 0 transfers all bytes Start channel 0 Enable DMAs from the DIR Release any handshake holdoff in progress Loop waiting for ENDRX or PCT DMA done National Instruments Corporation Appendix C RCV4 btst bne movw subw btst beq subw bra RCV5 btst bne movw subw addw RCV6 movb movb movb rts National Instruments Corporation COC CSRO RCV5 MTCO d1 di d0 ECC
15. National Instruments Corporation Base address 111 Base address 111 Base address 113 Base address 113 Base address 115 Base address 115 Base address 117 Base address 117 Base address 119 Base address 119 Base address 11B Base address 11B Base address 11B Base address 11B Base address 11B Base address 11B Base address 11B Base address 11D Base address 11D Base address 11F Base address 11F 4 1 Read only Write only Read only Write only Read only Write only Read only Write only Read only Write only Read only Write only Write only Write only Write only Write only Write only Read only Write only Read only Write only continues GPIB 1014 User Manual Register Bit Descriptions Table 4 1 GPIB 1014 Register Map continued DMA Register Group Address Registers Memory Address Register Base Address Register Device Address Register Transfer Count Registers Memory Transfer Counter Base Transfer Counter Function Code Registers Memory Function Code Base Function Code Device Function Code Device Control Register Operation Control Register Sequence Control Register Channel Control Register Channel Status Register Channel Error Register Channel Priority Register General Control Register Interrupt Vector Registers Normal Interrupt Vector Error Interrupt Vector Configuration Register Group Configuration Register 1 Configuration Register 2 Register Sizes
16. New Byte Available Not Data Accepted Negative Poll Response State Not Ready for Data Null byte F 7 GPIB 1014 User Manual Mnemonics Key O OSA OTA P 3 1 PACS PCG PEND pof pon PP PPAS PPC PPD PPE PPIS PPR PPSS PPU PUCS RD rdy REM REMC REMC IE REMS REN REOS RESET RFD RL RMW ROAK ROR RORA rpp RQS rsc ISV RM RM ST RM LM LM ST RM RM RM ST RM ST RM ST VBO VBO VBO VBO LM RM GPIB 1014 User Manual Appendix F Other Secondary Address Other Talk Address Parallel Poll Response Bits 3 through 1 Parallel Poll Addressed to Configure State Primary Command Group Pull up Enable Pending Bit Power Off Power On Parallel Poll scan all status flags Parallel Poll Active State Parallel Poll Configure Parallel Poll Disable Parallel Poll Enable Parallel Poll Idle State Parallel Poll Response Parallel Poll Standby Active Parallel Poll Unconfigure Parallel Poll Unaddressed to Configure State TLC Read Signal Ready for next message Remote Bit Remote Change Bit Enable Interrupt on Remote Change Bit Remote State Remote Enable End on End Of String Received Bit Local Reset Signal Ready For Data Remote Local Read Modify Write Release on Register Access Release on Request Release on Register Access Request Parallel Poll Request Service Request System Control Request Service Bit F 8 National Instruments Corporation Appendix F
17. Transfer from memory to GPIB Array Chaining SCR Bits Memory address counts up CCR Bits Start DMA channel Stop DMA channel National Instruments Corporation C 3 GPIB 1014 User Manual Sample Programs CLRS 0377 COC 0200 CERR 020 ACT 010 PCT 002 ECC 004 IN 001 OUT 000 SLMR 012 CLMR 010 TCT 011 UNL 077 UNT 0137 SELO 0 SEL1 0200 MA 0 SC 011 ROR 002 TMODE 0240 BRG 030 ADMC 06 even cmdbuf 100 cmdct word 0 datbuf 100 count word 0 datct word 0 ccary word 0 0 1 0 0 2 ola byte 0 sre byte 0 tctadr byte 0 vecc byte 0 vseoi byte 0 Cic byte 0 HLDA byte 0x81 SEOI byte 0x06 GPIB 1014 User Manual Appendix C CSR Bits Clear all status bits Channel operation complete Error in channel operation Channel active PCL transition occurred CFG1 Bits Enable Carry Cycle feature Accepting data from GPIB Sending data to GPIB CFG2 Bits Set Local Master Reset bit Clear Local Master Reset bit GPIB Commands Take control Universal unlisten Universal untalk User Specified Constants Select ADRO Select ADR1 GPIB address of GPIB 1014 System Controller set to 010 if not Sys Con Release on Request feature set to 0 if not used Cycle Steal DMA transfer mode set to 340 if Cycle Steal with Hold is desired Bus Request BR3 selected other options are BR2 020 BR1 010 BR0
18. jumpers W3 W4 and W5 National Instruments Corporation 3 1 GPIB 1014 User Manual Chapter 3 Configuration and Installation Figure 3 1 shows the locations of the GPIB 1014 configuration jumpers and switches TEA al aste e aes use d Pass dj sese q see i EE UNE WA O NBN CSEIOHTASSH FI0T BIdU 6B6T LHOISAdO aren I D res rae li dYOI SINSH HISNI dia Cera q d sese d YNOT LYN gon fan pan Me ann ach Leos dR ra RUE BZ RC ue sisi i o tg nn E een ean sen MEE aos RIETI Br ern orn n orse gle ess que sess3 Ce os 2n Ten nen z83 e Cass OC WE oes zwak g D d c DEN sin ven ren E arn MEZZI RC ees d pence e 3ss1 4 Cas an san UM TREL IMG sen can NI O sen osa em x as a eed ssi tee eas a Figure 3 1 Parts Locator Diagram National Instruments Corporation 3 2 GPIB 1014 User Manual Chapter 3 Configuration and Installation Access Mode The GPIB 1014 can be configured to respond to Supervisor privileged or User non privileged access Hardware jumper W2 is used to select the access mode that is automatically in effect upon a power up or a system reset The access mode then can be changed by software via a bit in Configuration Register 2 Figure 3 2 shows the placement of the jumper for the desired mode after a power up or a system reset Move the jumper to the side labeled S for Supervisor mode or to the side labeled U for User mode Supervisor mode
19. 0 Address Mode Register Address Only Cycle Address Register Address Register 0 Address Register 1 Address Status Change Address Status Change Interrupt Enable Bit Address Status Register Acceptor Handshake Acceptor Idle State Address Modifier Lines Acceptor Not Ready State Affirmative Poll Response State Address Pass Through Bit Enable Interrupt on Address Pass Through Bit Address Register Select Bit Address Strobe Attention Attention Bit Auxiliary Mode Register Auxiliary Register A Auxiliary Register B Auxiliary Register E Acceptor Wait for New Cycle State Bus Busy Bus Clear Bus Error Bus Grant In Lines F 2 National Instruments Corporation Appendix F Mnemonics Key BG 0 3 OUT VBS Bus Grant Out Lines BIN B Binary Bit BLT VBO Block Transfer BR 0 3 VBS Bus Request Lines National Instruments Corporation F 3 GPIB 1014 User Manual Mnemonics Key C C CACS CADS CAWS CDOR CDO 7 0 CIC CIDS CLK 3 0 CNT CNT 2 0 CO COC CO IE COM 4 0 CPPS CPT CPT ENABLE CPT IE CPTR CPT 7 0 CPWS CS CSBS CSHS CSNS CSRS CSWS CTRS D D 00 15 D08 O D 16 31 DAB DAC dacr DAV DC DCAS DCIS DCL DEC DEC IE DEC RX EOM MASS UV SECUS MM MOM DAD GPIB 1014 User Manual Appendix F Controller Controller Active State C function Controller Addressed State Controller Active Wait State Control Data Out Register Control Data Out Bits 7 through 0 Controll
20. 000 Address Modifiers set to 24 bit supervisor access of data area Program Variables Buffers Command buffer for interface messages Number of commands to be sent Data buffer for device dependent messages Current number of commands transferred Number of data bytes to be sent Carry Cycle Array Listen address passed to WRITE REN flag zero to not set REN non zero to set REN TCT address of new Active Controller ECC flag set appropriately by RCV SEOI flag zero to not send non zero to send END message with last DSEND byte Controller In Charge flag non zero if CIC Holdoff on all command AUXMR Send END command to AUXMR C4 National Instruments Corporation Appendix C National Instruments Corporation Sample Programs KR RK KKK k k k k k kk INITIALIZE INIT okok ok ko ko ko ko ko k KKK KKK Summary nitialize the GPIB 1014 hardware Assumptions on entry User specified constants MA ADMC and SC have been initialized Mode 1 primary addressing is used Low speed timing is used Interrupts are not used Status byte will be set elsewhere Remote Parallel Poll configuration will be used Actions Pulse LMR to put hardware in known reset state Disable interrupts and clear status Set hardware registers to desired values Status on return
21. 023 19 DC3 33 063 51 3 MLA19 14 024 20 DC4 DCL 34 064 52 4 MLA20 15 025 21 NAK PPU 35 065 53 5 MLA2I 16 026 22 SYN 36 066 54 6 MLA22 17 027 23 ETB 37 067 55 7 MLA23 18 030 24 CAN SPE 38 070 56 8 MLA24 19 031 25 EM SPD 39 071 57 9 MLA25 1A 032 26 SUB 3A 072 58 MLA26 1B 033 27 ESC 3B 073 59 MLA27 1C 034 28 FS 3c 074 60 MLA28 1D 035 29 GS 3D 075 61 MLA29 1E 036 30 RS 3E 076 62 gt MLA30 1F 037 31 US 3F 077 63 UNL Message Definitions DCL Device Clear MSA My Secondary Address GET Group Execute Trigger MTA My Talk Address GTL Go To Local PPC Parallel Poll Configure LLO Local Lockout PPD Parallel Poll Disable MLA My Listen Address GPIB 1014 User Manual D 2 National Instruments Corporation Appendix D PPE PPU SDC SPD Multiline Interface Messages Multiline Interface Messages Oct Dec ASCH Msg 100 64 MTAO 101 65 A MTAI 102 66 B MTA2 103 67 C MTA3 104 68 D MTA4 105 69 E MTAS5 106 70 F MTA6 107 71 G MTA7 110 72 H MTA8 111 73 I MTA9 112 74 J MTA10 113 75 K MTAII 114 76 L MTA12 115 TI M MTA13 116 78 N MTA14 117 79 O MTA15 120 80 P MTA16 121 81 Q MTA17 122 82 R MTA18 123 83 S MTA19 124 84 T MTA20 125 85 U MTA21 126 86 V MTA22 127 87 W MTA23 130 88 X MTA24 131 89 Y MTA25 132 90 Z MTA26 133 91 MTA27 134 92 MTA28 135 93 MTA29 136 94 A MTA30 137 95 _ UNT Parallel Poll Enable Parallel Poll Unconfigure Selected Device Clear Serial Poll Disable National Instruments Corporation Oct
22. 1014 1 776059 01 GPIB 1014 2 776060 01 GPIB 1014 EH EH Ejector Handles 776059 51 GPIB 1014 1S no P2 signals 776059 21 GPIB 1014 1S EH no P2 signals EH Ejector Handles 776059 61 One GPIB 1014 User Manual 320030 01 Optional Equipment Single Connector Scrambler Interface Card 180170 01 Dual Connector Scrambler Interface Card 180170 02 Scrambler Card to P2 Cable Assembly 180173 01 Single Shielded Cables GPIB Type X1 Cable 1 m 763001 01 GPIB Type XI Cable 2 m 763001 02 GPIB Type X1 Cable 4m 763001 03 GPIB Monitor Analyzer GPIB 400 776074 01 GPIB 410 776104 01 National Instruments Corporation 1 3 GPIB 1014 User Manual Introduction Chapter 1 Unpacking Follow these steps when unpacking your GPIB 1014 1 Verify that the pieces contained in the package you received match the kit parts list given earlier in this chapter Do not remove the board from its plastic bag at this point 2 Your GPIB 1014 board is shipped packaged in an antistatic plastic bag to prevent electrostatic damage to the board Several components on the board can be damaged by electrostatic discharge To avoid such damage in handling the board touch the plastic bag to a metal part of your VMEbus computer chassis before removing the board from the bag 3 Remove the board from the bag and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not insta
23. 4 32 LOK Lockout Bit 4 16 LOKC Lockout Change Bit 4 17 LOKC IE Lockout Change Interrupt Enable Bit 4 17 lon Listen Only Bit 4 22 LPAS Listener Primary Addressed State Bit 4 20 M MO Program Data Access Bit 4 50 M1 Standard Short Addressing Bit 4 50 M2 Supervisor User Access Bit 4 50 MAC Memory Address Count Bits 3 through 2 4 55 MAR See Memory Address Register MAR master direct memory access VMEbus 2 5 to 2 6 Memory Address Register MAR 4 48 Memory Transfer Counter Register MTCR 4 48 messages multiline interface command messages D 1 to D 2 types of E 1 MJMN Major Minor Bit 4 21 MLA My Listen Address command 4 26 mnemonics for registers alphabetical list with definitions F 1 to F 9 clues to understanding 4 3 MSA PPD My Secondary Address or Parallel Poll Disable command 4 26 MSA PPE My Secondary Address or Parallel Poll Enable command 4 26 MTA My Talk Address command 4 26 MTCR See Memory Transfer Counter Register MTCR multiline GPIB commands table 4 25 to 4 26 D 2 to D 3 uPD7210 interface registers 2 3 N NDAC not data accepted signal E 3 NDT Normal Device Termination Bit 4 58 Non Valid Secondary Command or Address command codes for 4 28 description 4 30 NRED not ready for data signal E 2 O National Instruments Corporation Index 12 GPIB 1014 User Manual Index OCR See Operation Control Register operands and addressing DMAC channel operation
24. 6 14 interrupter 6 9 test and troubleshooting 6 24 timing state machine 6 6 to 6 7 VMEbus interface 6 1 to 6 3 with VMEbus computer illustration 2 9 GPIB Controller See Controller function GPIB Synchronization and Interrupt Control definition of 2 12 theory of operation 6 12 to 6 14 GPIB TLC See Talker Listener Controller TLC GTL Go To Local command 4 25 H handshake lines DAV data valid E 3 NDAC not data accepted E 3 NRED not ready for data E 2 overview E 2 hidden registers Auxiliary Register A AUXRA 4 37 to 4 38 Auxiliary Register B AUXRB 4 39 to 4 40 Auxiliary Register E AUXRE 4 41 Internal Counter Register ICR 4 34 overview 4 33 Parallel Poll Register PPR 4 35 to 4 36 HLDA Holdoff on All Bit 4 38 HLDE Holdoff on END Bit 4 38 HLT Halt Bit 4 56 6 18 I ICR See Internal Counter Register ICR IEEE 488 standard GPIB 1014 capabilities 2 13 to 2 15 GPIB 1014 compatibility 1 1 IEEE 1014 standard GPIB 1014 User Manual Index 9 National Instruments Corporation Index GPIB 1014 compatibility 1 1 GPIB 1014 compliance levels 2 15 IFC interface clear line E 3 Immediate Execute Pon command codes for 4 28 description 4 29 IMRI See Interrupt Mask Register 1 UMR1 initialization of GPIB 1014 5 1 to 5 3 INITIALIZE INIT sample program C 5 to C 6 installation cabling 3 10 hardware installation tests 7 2 to 7 8 prerequisites for 3 1 unpacking the GPIB 1014 1
25. 68 C6 715079 01 1 0000 AVX SATOSE473ZAA CAP DA7UF 50V 80 20X CER AX C65 715079 01 1 0000 AVX SAT05E4722AA CAP 047UF 50V 80 20X CER AX c66 715079 01 1 0000 AVX SA105E473ZAA CAP 047UF 50V 80 20 CER AX 7i C67 715079 01 1 0000 AVX SA105E473ZAA CAP 047UF SOV 80 20 CER AX 72 GPIB 1014 User Manual B 4 National Instruments Corporation Appendix B Parts List and Schematic Diagrams TE EAE AE HEE e E EERE RRR EER EERE REE EER RII IO eco e edere edo eee ee eI I CR eei et carcerarie ITEM NO NI PART NO QTY REQD c68 715079 01 1 0000 69 715079 01 1 0000 C70 715079 01 1 0000 cz 715010 01 1 0000 c72 715010 01 1 0000 C73 715079 01 1 0000 D01 730001 01 1 0000 poz 730001 01 1 0000 DS01 735016 01 1 0000 P01 760208 96 1 0000 P02 760208 96 1 0000 R01 711146 01 1 0000 Roz 711146 01 1 0000 R03 711009 01 1 0000 ROA 711009 01 1 0000 ROS 711040 01 1 0000 R06 711009 01 1 0000 u01 700739 01 1 0000 u02 700902 01 4 0000 U03 700743 01 1 0000 UO amp 700173 01 1 0000 U05 700004 01 1 0000 v6 700106 01 1 0000 UO7 700107 01 1 0000 vos 700741 01 1 0000 National Instruments Corporation MFR AVX AVX AVX KMT KMT AVX NSC NSC BIA PAN PAN TI SIG NSC Ti NS TI MFR PART SA105E4732AA SA105E4732AA SA105E4732AA T322D0476M010AS T3220476M010AS SA105E47324A 184148 1N4148 550 3606 100 096 033 100 096 033 29AB250 150 29AB250 150 29AB250 1K 29AB250 1K 29AB250 3 3K 29AB250 1K S
26. 8 Tw 5 0r S 6 1 Serial Poll Status Bits 6 through 1 5 0w Cleared by Power On Reset pon and by issuing the Chip Reset auxiliary command These bits are used for sending device or system dependent status information to the GPIB when the TLC is serial polled When the TLC is addressed as the GPIB Talker and receives the GPIB multiline Serial Poll Enable SPE command message the TLC transmits a byte of status information SPMR 7 0 to the Controller In Charge after the Controller goes to standby and becomes an Active Listener 6r PEND Pending Bit PEND is set when rsv 1 and cleared when the Negative Poll Response State NPRS amp Request Service rsv 1 Reading the PEND status bit can confirm that a request was accepted and that the Status Byte STB was transmitted PEND 0 6w rsv Request Service Bit The rsv bit is used for generating the GPIB local rsv message When rsv is set and the GPIB Active Controller is not serial polling the TLC the TLC enters the Service Request State SRQS and asserts the GPIB SRQ signal When the Active Controller reads the STB during the poll the TLC clears rsv at the Affirmative Poll Response State APRS The rsv bit is also cleared by pon and by issuing the Chip Reset auxiliary command Register Bit Descriptions Chapter 4 Address Status Register ADSR VMEbus Address Attributes Base Address 119 hex Read Only Internal to TLC The Address Status Register ADSR
27. Appendix G Customer Communication sotto ere eoo ted fisse te aor lei G 1 Glossa esce etd Waele Bane paia dai sri Glossary 1 Indexia nem hatants Index 1 Figures Figure 1 1 GPIB 1 014 Interlace Board zs tnnc elaine ares tend 1 2 Figure 2 1 GPIB 1014 with a VMEbus Computer eene 2 0 Figure 2 2 GPIB 1014 in a Multiprocessor Application 2 10 Figure 2 3 GPIB 1014 Block DIAgram csse aiio tette eionded eic tod d eget eee 2 11 Figure 3 1 Parts Locator Diagram 3uiscenensR d ntu bte de ed siiiad ege edd 3 2 Figure 3 2 Access Mode After RESET 5 idees ttes lidi 3 3 Figure 3 3 Configuration for GPIB 1014 Base Address 2000 hex 3 4 Figure 3 4 Default Settings of AM Code Jumpers W3 W4 and WS sess 3 5 Pigured L Interface REpisters oce d ed aiid eae tee et De bate ede 4 4 Figure 4 2 Writing to the Hidden Registers iae be Tii euadelieacaaue 4 5 Figure 4 3 DMA Register Memory Map sseessseseessssrsssesressessresressessresresseeseeseesressesrreseesee 4 47 Figure 5 1 DMA Transfer without Carry Cycle ui atea lol ali 5 10 Figure 5 2 DMA Transfer with Carry C vele saliera 5 13 Figure 6 1 DTB Requester and Controller Flip Flop Operations sss 6 10 Figure 6 2 Array Format for Array Chaining Modes eee 6 20 National Instruments Corporation xi GPIB 1014 User Manual
28. Attention Bit 4 20 ATN attention line E 3 auxiliary commands detailed description 4 29 to 4 32 summary table 4 28 Auxiliary Mode Register AUXMR command summary table 4 28 detailed description table 4 29 to 4 32 overview 4 27 Auxiliary Register A AUXRA 4 37 to 4 38 Auxiliary Register B AUXRB 4 39 to 4 40 Auxiliary Register E AUXRE 4 41 B BAR See Base Address Register BAR base address configuration selecting base address 3 3 setting with compare address lines 3 4 setting with jumper block W1 3 4 Base Address Register BAR 4 48 Base Transfer Counter Register BTCR 4 48 BIN Binary Bit 4 37 BR Bandwidth Available to DMAC Bits 1 through 0 4 63 BRG Bus Request Grant Bits 4 65 BT Burst Transfer Time Bits 3 through 2 4 63 BTC Block Termination Complete Bit 4 58 4 62 6 19 BTCR See Base Transfer Counter Register BTCR bus signals See VMEbus National Instruments Corporation Index 2 GPIB 1014 User Manual Index C cabling 3 10 capability codes for GPIB 1014 2 13 to 2 15 CC Carry Cycle Bit 4 65 CCR See Channel Control Register CCR CDO 7 0 Command Data Out Bits 7 through 0 4 7 CDOR See Command Data Out Register CDOR CER See Channel Error Register CER chaining operations array chaining operations 6 19 to 6 20 linked chaining operations 6 20 to 6 21 Channel Control Register CCR 4 56 to 4 57 Channel Error Register CER 4 60 Channel Priority Register
29. CFG1 RCV6 1 d0 RCV6 ECC CFG1 RCV6 MTC1 d1 d1 dO 1 d0 0 IMR2 STOP CCR1 STOP CCRO Sample Programs Calculate number of bytes transferred If carry cycle MTCO was initialized to dO 1 If no carry cyle leave d0 as is Disable DMAs and stop DMA channels C 11 GPIB 1014 User Manual Sample Programs GPIB 1014 User Manual Appendix C kkk k ko READ Summary Called to read device dependent data messages when the GPIB 1014 is Controller In Charge RCV is called when the GPIB 1014 is Idle Controller Assumptions on entry GPIB 1014 is Controller In Charge The Talker address is placed in first location of cmdbuf The variable cmdct is set to 1 The buffer datbuf is free to place incoming data The number of bytes to read is placed in datct Actions Set up cmdbuf and cmdct and call CMD to address the Talker and unaddress all other devices Program the GPIB 1014 to listen Go to standby and unassert ATN Transfer the contents of datct to the dO register Load the a0 register with the address of datbuf Call RCV to receive the data Call CMD to unaddress all devices Program the GPIB 1014 to unlisten Status on return GPIB 1014 is Active Controller Acceptor handshake is held off at NRFD All GPIB devices are unaddressed C 12 National Instruments Corporation Appendix C 68000 Code Sample Pr
30. Code Channel 1 Status Register Channel 1 Device Control Register Channel 1 Operation Control Register Channel 1 Sequence Control Register Channel 1 Channel Control Register Configuration Register 1 Configuration Register 2 C 2 National Instruments Corporation Appendix C DI DO ERR ENDRX CO NATN MODE1 TRM DT1 DL1 ICR PPR AUXRA AUXRB AUXRE IEPON FH GTS TCA TCS TCSE LTN LTNC LUN SIFC CIFC SREN CREN CRST GTM MTG ACHN MCU GO STOP 001 octal 002 004 020 010 0100 001 060 0100 0 40 040 0140 0200 0240 0300 000 003 020 021 022 032 023 033 034 036 026 037 027 002 202 002 010 004 0200 020 Sample Programs ISR1 Bits Data in Data out Error END received ISR2 Bits Command out ADSR Bits Not ATN ADMR Bits Address Mode 1 GPIB 1014 functions for T R2 and T R3 ADR Bits Disable Talker Disable Listener AUXMR Hidden Registers Internal Counter Register Parallel Poll Register Auxiliary Register A Auxiliary Register B Auxiliary Register E AUXMR Commands Immediate execute power on Finish release handshake Go to standby Take control asynchronously Take control synchronously Take control synchronously on END Listen Listen continuously Unlisten Set IFC Clear IFC Set REN Clear REN Chip Reset OCR Bits Transfer from GPIB to memory
31. DCR OCR SCR GCR MAR DAR or MTCR with STR or ACT asserted if an attempt to assert CNT is made when CHN is 10 or 11 or if an attempt to assert CNT is made when BTC and ACT are asserted This is signaled if a word or longword operation is attempted to an odd address This indicates a bus error occurred during the last bus cycle generated by the channel This is signaled if the MTCR or BTCR are initialized with terminal count A count error is signaled if a terminal count is encountered during continue or chain processing This is signaled if the PCL was configured as an abort input and made an active transition or if the channel operation was aborted by the SAB bit of the OCR If the PCL is used as an abort input the PCT bit must be cleared prior to starting the channel The DMAC allows access to internal registers to implement error recovery procedures If an error occurs during a DMA transfer appropriate information is available to the operating system for a soft failure operation The operating system must be able to determine how much data was transferred where the data was transferred to and what type of error occurred The information available to the operating system consists of the present values of the Memory Address Device Address and Base Address Registers the Memory Transfer and Base Transfer Counters and the Control Status and Error Registers After the successful completion of any National Instruments Corpora
32. I O Compare Address lines Can be used to set base address of GPIB 1014 GPIB signals used for GPIB I O via P2 Reserved pin Defined by the VMEbus specification For models GPIB 1014 1S and GPIB 1014 1S EH These signals are not connected to the P2 connector National Instruments Corporation 3 9 GPIB 1014 User Manual Configuration and Installation Chapter 3 Cabling Two options are available for GPIB I O from the GPIB 1014 A Front Panel Plug In Connector A VMEbus P2 Connector The Model GPIB 1014 1 interface board has a standard 24 pin IEEE 488 connector on the front panel of the board A standard GPIB cable can plug in directly to this connector Two GPIB cables cannot be connected side by side in this configuration that is if more than one Model GPIB 1014 1 is installed in the system they cannot be placed side by side due to the width of the GPIB cable connector housing another board must be placed between any two GPIB 1014 1 interface boards The Model GPIB 1014 2 interface board has no connector on the front panel therefore GPIB I O is performed through the VMEbus P2 connector A scrambler card and interface cable assembly are available from National Instruments for this configuration The interface cable assembly is a 96 wire flat ribbon cable used to connect the GPIB I O signals from the backplane P2 connector to the scrambler card where they are routed to the IEEE 488 connector A standard GPIB cable enters the
33. Interrupt on Device Execute Trigger Bit DAC Holdoff on DCAS Data Accepted Holdoff on Device Trigger Active State Bit Data In Bit Data In Bits 7 through 0 Enable Interrupt on Data In Bit GPIB Data Lines 1 through 8 Data In Register Disable Listener Bit Disable Listener 0 Bit Disable Listener 1 Bit Direct Memory Access DMA Input Enable Bit DMA Out Enable Bit Data Out Bit Enable Interrupt on Data Out Bit Data Strobe Zero Data Strobe One Device Trigger Disable Talker Bit Disable Talker 0 Bit Disable Talker 1 Bit Data Transfer Acknowledge Device Trigger Active State Device Trigger Idle State End Enable Interrupt on End Received Bit End Received Bit End or Identify Bit End or Identify GPIB EOI Signal Output Enable End of String End of String Bits 7 through 0 End of String Register Error Bit Error Enable Interrupt on Error Bit Enable Vector F 5 GPIB 1014 User Manual Mnemonics Key FH FIN GET GND GTL gts HLDA HLDE I IA 1 3 IACK IACKIN IACKOUT IB 1 3 ICR IDTACK IDY IFC IMRI IMR2 INT INTA INTB INV IR IRQ 1 7 ISRI ISR2 ISS ist LM LS VBS LM GPIB 1014 User Manual Appendix F Finish Handshake GPIB DMA Transfer Finished Group Execute Trigger Ground Go To Local Go to Standby Holdoff on All Bit Holdoff on End Bit Interrupt Priority Code Bits Interrupt Acknowledge Signal Interrupt Acknowledge In Interrupt Acknowledge Out Interrupt Pr
34. LBROUT and BR are high The DTB Requester then releases the VMEbus BBSY immediately if the Release On Request feature is not enabled ROR 1 amp BUS_REL 0 If the DMAC operates in cycle steal mode it releases OWN immediately after it has finished the DMA transfer In contrast if the DMAC operates cycle steal with hold mode it keeps asserting OWN during the hold period and releases OWN if the onboard TLC does not request DMA within the hold time If the Release On Request feature is enabled in CFG1 ROR 0 however the DTB Requester circuitry monitors the four VMEbus bus request lines BR3 BRO If none of these lines is logic zero indicating that no other device is requesting the bus BRIN 0 the DTB Requester simply holds the bus by continuing to drive the BBS Y line low even when the OWN signal of the DMAC is unasserted If any of the VMEbus Bus Request lines are driven low BRIN 1 before the DMAC indicates that it needs the bus again BUS_REL is asserted and the circuitry relinquishes the system bus by releasing the BBSY line The DTB Requester performs the entire bus arbitration protocol the next time the DMAC requests the bus If however the DMAC requests the bus while the DTB Requester still has control of the bus the DMAC is immediately granted the bus and the bus arbitration overhead is avoided GPIB Synchronization and Interrupt Control This circuitry is designed to allow the GPIB 1014 to detect GPIB synchronization
35. SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks NI 488M is a trademark of National Instruments Corporation Product and company names listed are trad
36. The following registers are cleared SR1 2 IMR1 2 SPMR SPSR BCR ACR PPR AUXRA AUXRB AUXRE Other registers are configured as described The GPIB 1014 interface functions are reset to idle and are enabled C 5 GPIB 1014 User Manual Sample Programs 68000 Code Appendix C Comments INIT movb movb movb movb movb tstb tstb movb movb movb movb movb movb movb movb movb rts SLMR CFG2 CLMR CFG2 CRST AUXMR 0 IMR1 0 IMR2 ISR1 ISR2 MODE1 TRM ADMR MA SEL0 ADR DT1 DL1 SEL1 ADR ICR 8 AUXMR ADMC MFCO ADMC MFC1 ADMC BFC1 SC CFG2 IEPON AUXMR GPIB 1014 User Manual Pulse Local Master Reset Chip Reset Disable TLC interrupts Clear status bits by reading registers Set address mode Talker Listener inactive and proper T R signal mode Set GPIB address mode 1 primary only with Talker Listener enabled Disable secondary address recognition Set clock divider for 8 MHz low speed Set DMA address modifier codes By default be System Controller Execute pon to bring TLC online C 6 National Instruments Corporation Appendix C 68000 Code IFC movb SIFC AUXMR movb 50 d1 IFC1 subb 1 d1 bne IFC1 movb CIFC AUXMR rts National Instruments Corporation Sample Programs ok ck ck ck ck ck ck ko Ck Ck Ck Ck k KK KKK kk INTERFACE CLEAR IFC ok ck ck ck ck ck ck ko ck Ck Ck Ck KK
37. This byte must be transferred by the DMAC to the TLC auxiliary register Since the TLC does not allow DMA transfers to the auxiliary register discrete circuitry must make this cycle appear as a normal write cycle to the TLC Furthermore the circuitry must ensure that this byte is always transferred from memory to the TLC even though the DMAC may be configured to transfer the data from the GPIB to VMEbus memory The circuitry knows that the first byte to be transferred from Channel 1 is always the carry cycle byte so when ACKI is driven low at the start of the DMA cycle the onboard signal CCBYTE becomes active This signal is ORed with the DMAC WR signal to ensure that the onboard circuitry performs a read from VMEbus memory and a write to the TLC Signal CCBYTE is also used to gate the TLC register select lines RS2 through RSO to drive them as needed to address the TLC auxiliary register and to drive the TLC CS line instead of the DMAACK line As mentioned earlier DACKEN is kept high during the carry cycle byte to prevent DMAACK from asserting The Timing State Machine circuitry and the TLC interpret the cycle as a normal write to the TLC while the VMEbus memory interprets the cycle as a DMA read from memory The DMAC signal ACK1 goes high at the end of the transfer This low to high transition is used to set a flip flop which gates further DMA requests from the TLC to DMAC Channel 1 and disables generation of the CCBYTE signal When the TLC
38. User Manual Chapter 4 Description Reserved Bit Write a zero to this bit Peripheral Control Line Bits 1 through 0 Each of the four DMAC channels has a Peripheral Control Line called PCLO through PCL3 The two PCL bits define the function of each line The GPIB 1014 uses the four lines as status inputs On PCLO GPIB signal SRQ is connected On PCL2 signal REN is connected If programmed as status inputs you can determine the state high or low of these two GPIB signals by reading the PCS bit in the appropriate CSR PCL1 is designed to detect an interrupt from the TLC synchronization of the GPIB handshake or a bus error during a DMA transfer PCL1 must be set to 01 status input with interrupt if interrupts are used or 00 status input if polling is used This is described in more detail in the nterrupts section of Chapter 5 PCL3 is left unconnected 00 Status Input can be read by reading CSR 01 Status Input with Interrupt 10 Start Output Pulse Negative 1 8 CLK 11 Abort Input 4 52 National Instruments Corporation Chapter 4 Register Descriptions Operation Control Register VMEbus Address Base Address 05 hex Attributes Read Write Internal to DMAC 7 6 5 4 3 2 1 0 DIR EA SIZE CHN REQG R W The Operation Control Register OCR is an operation oriented register Bit Mnemonic Description Tr w DIR Direction Bit The Direction bit specifies the direction of the transfer to or from VM
39. User Manual Memory Transfer Counter Memory Address Register Memory Function Code Device Address Register Device Function Code Base Transfer Counter Base Address Register Base Function Code Channel Status Channel Error Device Control Operation Control Sequence Control Channel Control Channel Priority Normal Interrupt Vector Error Interrupt Vector Memory Transfer Counter Memory Address Register Memory Function Code Device Address Register Device Function Code Base Transfer Counter Base Address Register Base Function Code Channel Status Channel Error Device Control Operation Control Sequence Control Channel Control Channel Priority Normal Interrupt Vector Error Interrupt Vector Memory Transfer Counter Memory Address Register Memory Function Code Device Address Register Device Function Code Base Transfer Counter Base Address Register Base Function Code Channel Status Channel Error Device Control 2 4 MTCRO MARO MFCRO DARO DFCRO BTCRO BARO BFCRO CSRO CERO DCRO OCRO SCRO CCRO CPRO NIVRO EIVRO o SPOSO SP SP _ _S SP _ _ _ _ _ _D _ DS I MTCR1 MARI MFCR1 DARI DFCR1 BTCR1 BARI BFCR1 CSR1 CER1 DCR1 OCR1 SCR1 CCR1 CPR1 NIVR1 EIVR1 I LR p xn Ln xxn pb pd pd i L ra Ka Wu MTCR2 MAR2 MFCR2 DAR2 DFCR2 BTCR2 BAR2 BFCR2 CSR2 CER2 DCR2 NNNNNNNNNNN continues Nat
40. assigning the response line and sense to devices on the GPIB This is accomplished using the Parallel Poll Enable PPE and Parallel Poll Disable PPD commands which are issued by the Active Controller The sequence for remotely configuring devices on the GPIB is as follows 1 Become Active Controller GPIB 1014 User Manual 5 24 National Instruments Corporation Chapter 5 Programming Considerations 2 Send the GPIB UNL message to unaddress all GPIB Listeners 3 Send the listen address of the first device to be configured 4 Send the GPIB PPC message to all devices followed by the PPE message for that device 5 Repeat from the second step UNL for each additional device Follow the same procedure to disable polling with PPD for example when changing responses during reconfiguration Responding to a Parallel Poll Before the GPIB 1014 can be polled by the CIC the TLC must be configured either locally by your program at initialization time or remotely by the CIC Configuration involves the following e Enabling the TLC to participate in polls e Selecting the sense or polarity of the response Selecting the GPIB data line on which the response will be asserted when the CIC issues the IDY message With remote configuration PP1 the TLC interprets the configuration commands received from the CIC without any software assistance or interpretation from your program With local configuration PP2 the three actions listed
41. base address of the board VMEbus Slave Data The GPIB 1014 can function as a VMEbus slave decoding short I O addresses and commands from a VMEbus master The uPD7210 and the two Configuration Registers function as 8 bit slaves allowing data to be transferred to and from the VMEbus Master on data lines D07 through DOO The 68450 can function as an 8 or 16 bit slave allowing transfers on data lines D15 through DOO The board is designed to accommodate Address Only ADO cycles In VMEbus terminology the slave module of the board is designated as D16 amp DO08 EO The GPIB Interface Registers associated with the uPD7210 are addressed relative to the base address of the board as shown in Table 2 2 The DMA registers internal to the 68450 are shown in Table 2 3 The two Configuration Registers of the GPIB 1014 are shown in Table 2 4 Table 2 2 uPD7210 Internal GPIB Interface Registers Address Base Hex Offset Mode Register Size Data In Command Data Out Interrupt Status 1 Interrupt Mask 1 Interrupt Status 2 Interrupt Mask 2 Serial Poll Status Serial Poll Mode Address Status Address Mode Command Pass Through Auxiliary Mode Address 0 Address Address 1 End of String R W R W R W R W R W R W R W R W National Instruments Corporation 2 3 GPIB 1014 User Manual General Description Chapter 2 Table 2 3 68450 Internal DMA Registers Address Base Hex Offset Mode Register hannel Size GPIB 1014
42. check the COC and ERR bit in the CSR of Channel 0 to determine the status of the DMA transfer This is described further in Terminating the Transfer and Checking the Result later in this chapter A detailed programming sequence for DMA transfers without a carry cycle is as follows 1 In CFGI the CC bit must be cleared to 0 The DIR bit should be set to reflect the direction of the DMA transfer 12GPIB to Memory 0 Memory to GPIB The ROR bit must also be set if the Release On Request feature is to be enabled If interrupts are used the INTRQ bits are set to select the interrupt level BRG bits must be set to choose one of four VMEbus request lines 2 Channel 0 must be configured to provide a flyby transfer for the n data bytes between the GPIB and the VME system memory The sequence is as follows a The CCR of Channel 0 must be written with the SAB bit set to abort the channel operation in case it is still active GPIB 1014 User Manual 5 10 National Instruments Corporation Chapter 5 Programming Considerations b A OxFF hex must be written to the CSR of Channel 0 to clear any leftover error or status bits c The DCR of Channel 0 is loaded with the proper value to select the DMA transfer mode cycle steal without hold or cycle steal with hold The DTYP bits should be set to binary 10 device with ACK implicitly addressed the DPS bit must be set to 0 8 bit port size and the PCL bits should be set to binary 000 status inp
43. cleared TADS LIDS 1 if TPAS was set The GPIB DAC message to be sent true and the GPIB handshake to be finished 7 When the Non Valid auxiliary command is issued the TLC assumes that the Other Secondary Address OSA message has been received which causes the following events to occur The TLC Talker or Listener function to go to its idle state TIDS 1 or LIDS 1 if the either the TPAS or LPAS bit was set The GPIB DAC message to be sent true and the handshake to be finished Until a GPIB Primary Command Group PCG message is received that is as long as the subsequent messages are secondary addresses the APT bit is set and a DAC holdoff is in effect each time a GPIB secondary address is received In this way the GPIB CIC can address several devices having the same primary address without repeating the primary address each time If a PCG message is received before a secondary address is received the TPAS and LPAS bits are cleared Sending Receiving Messages When the TLC is a GPIB Talker or Listener data device dependent messages can be sent or received using either DMA or programmed I O When the TLC is Active Controller commands remote multiline messages can be sent using programmed I O only The default configuration is programmed I O DMA mode is activated only by issuing a specific sequence of commands to the GPIB 1014 In either programmed I O or DMA modes the GPIB interface functions are programmed or addres
44. cleared by pon read ISR1 Notes DCAS GPIB Device Clear Active State pon Power On Reset read ISR1 Bit is cleared immediately after it is read The DEC bit indicates that the GPIB Device Clear DCL command has been received or that the GPIB Selected Device Clear SDC command has been received while the TLC was a GPIB Listener the TLC is in DCAS Error Bit Error Interrupt Enable Bit ERR is set by TACS amp SDYS amp DAC amp RFD SIDS amp write CDOR SDYS to SIDS ERR is cleared by pon read ISR1 Notes TACS GPIB Talker Active State SDYS GPIB Source Delay State DAC GPIB Data Accepted message RED GPIB Ready For Data message SIDS GPIB Source Idle State 4 12 National Instruments Corporation Chapter 4 Bit lr lw Or Ow Mnemonic DO DO IE DI DI IE Register Bit Descriptions Description write CDOR Bitis set immediately after writing to the Command Data Out Register SDYS to SIDS Transition from GPIB Source Delay State to Source Idle State pon Power On Reset read ISRI Bit is cleared immediately after it is read The ERR bit indicates that the contents of the CDOR have been lost ERR is set when data is sent to the GPIB without a specified Listener or when a byte is written to the CDOR during SIDS or during the SDYS to SIDS transition Data Out Bit Data Out Interrupt Enable Bit DO is set as TACS amp SGNS becomes true DO is cleared by read ISR1 TACS S
45. corresponding Mask bit for INT INT is set by CPT amp CPT IE APT amp APT IE DET amp DET IE ERR amp ERR IE END RX amp END IE DEC amp DEC IE DO amp DO IE DI amp DI IE SRQI amp SRQI IE REMC amp REMC IE CO amp CO IE LOKC amp LOKC IE ADSC amp ADSC IE Notes CPT Command Pass Through Bit CPT IE Enable Interrupt on Command Pass Through Bit APT Address Pass Through Bit APT IE Enable Interrupt on Address Pass Through Bit DET Device Execute Trigger Bit DET IE Enable Interrupt on Device Execute Trigger Bit ERR Error Bit GPIB 1014 User Manual 4 14 National Instruments Corporation Bit Tw 6r 6w Mnemonic SRQI SRQIIE Description ERR IE Enable Interrupt on Error Bit END RX End Received Bit END IE Enable Interrupt on End Received Bit DEC Device Clear Bit DEC IE Enable Interrupt on Device Clear Bit DO Data Out Bit DO IE Enable Interrupt on Data Out Bit DI Data In Bit DIIE Enable Interrupt on Data In Bit SRQI Service Request Input Bit SRQI IE Enable Interrupt on Service Request Input Bit REMC Remote Change Bit REMC IE Enable Interrupt on Remote Change Bit CO Command Output Bit CO IE Enable Interrupt on Command Output Bit LOKC Lockout Change Bit LOKC IE Enable Interrupt on Lockout Change Bit ADSC Address Status Change Bit ADSC IE Enable Interrupt on Address Status Change Bit Reserved Bit Write zero to this bit Service Request I
46. documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS
47. fe idet V e orci Geant 5 22 Conducting a Parallel Poll eoo ha Prose oiran 5 23 Responding to a Parallel Poll 4 3 7 rei ott detenti eats 5 24 Chapter 6 Theory of Operation pullula RN des 6 1 VIM bus Infertage car eb i Rei 6 1 Data TINE Sear T 6 1 Slave Read and Write Transfers aie i cedi tete ret eene 6 1 DMA Transfers db die nek d lalla 6 1 Control Signals s siseecsnt oiran ni desde i 6 2 uc M 6 2 Control Equations of Transceivers eee e eee entere eene entente nee en aae en ae 6 3 Address D coding uil e I D d RS RE TAA RT Fo gh RE e E seus Po e uude 6 3 Clock and R eset Circuitry s pesca epa boc e tar lino ella 6 4 Confeuradonm Reglsiers c aiio oe ace odds a irae A Ris TI PRU Mere s ee 6 5 Configuration Register T i udo ete op het ieee date e AG seria 6 5 Confir rati n Ree ster 2 i licia ca dida 6 6 Timing State Machine iade podes ies tdeo die Deoa det uude Bae eee dud 6 6 Save ECS or descent i tA bru RAI o dfe T 6 6 DMA dar p 6 7 DNPEA Crating and Control uei eoe ero Gated aks Hoan pe Ubi 6 7 seq MET 6 9 DIB Requester and Controller is ie toe rg arte siai e Eia 6 9 GPIB Synchronization and Interrupt Control esee 6 12 National Instruments Corporation ix GPIB 1014 User Manual Contents 68450 DMA Cia 6 14 DMAC Channel Operation ceto cies dass iu ei 6 15 Initialization and Transfer Pha
48. is the default setting configured at the factory If the board is configured for Supervisor mode it will initially respond to a 16 bit address and an AM code of 2D If the board is configured for User mode the board will initially respond to a 16 bit address and AM codes of 29 and 2D Refer to the ANSI IEEE Std 1014 1987 IEEE Standard for a Versatile Backplane Bus VMEbus for more information on Supervisor and User modes Figure 3 2 Access Mode After RESET Base Address The GPIB 1014 occupies a total of 512 bytes of 16 bit I O space The base address is selected with either hardware jumper block W1 on the interface board or compare address lines located on the P2 connector The 1S and 1S EH versions of the GPIB 1014 do not have compare address lines located on the P2 connector Note If the base address is configured using the onboard jumpers the lines must not be strapped on the P2 connector Likewise if the base address is configured on the P2 connector the jumpers provided on the interface board must be removed National Instruments Corporation 3 3 GPIB 1014 User Manual Configuration and Installation Chapter 3 Set Base Address Using Jumper Block W1 Move the jumper to the side labeled to select a logical one for the corresponding address bit or to the side labeled 0 to select a logical zero Figure 3 3 shows the configuration for a base address 2000 hex which is the default address configu
49. issues another DMA request Channel 1 responds by transferring the last byte of data with a normal DMA transfer cycle The low to high transition of ACK1 at the end of this cycle clears the flip flop which masks any further DMA requests from the TLC Again the flip flop state determines if a carry byte cycle has been completed It is cleared Q 0 at all time before and during the carry cycle byte and set Q 1 at the end of the carry cycle byte The output of the flip flop is also used to generate signal ALLDONE which is used in the GPIB synchronization circuitry discussed later in this chapter National Instruments Corporation 6 9 GPIB 1014 User Manual Theory of Operation Chapter 6 If the carry cycle feature is not used in a DMA transfer the CC bit in CFGI is 0 and DMA Gating and Control circuitry directs all DMA requests from the TLC to DMAC Channel 0 DMAC Channel is not used and must not be started Interrupter The GPIB 1014 requests service by using the Interrupter circuitry The circuitry consists of the following A74145 open collector 4 bit decoder Two 74F74 flip flops e A 7TAF85 4 bit magnitude comparator e A 2 tap digital delay line Miscellaneous gates The interrupt priority of the GPIB 1014 is software selectable via three bits in CFG1 These bits are connected to the 74145 and 74F85 Since all interrupts from the GPIB 1014 are routed through the DMAC the IREQ pin of the DMAC is connected to the 74145
50. just before writing the last data byte to the CDOR To send the GPIB EOS message make the last byte the EOS code Terminating on END or EOS The END status bit or interrupt is used to inform the program of the occurrence of an END message or an EOS message GPIB 1014 User Manual 5 20 National Instruments Corporation Chapter 5 Programming Considerations Interrupts If the GPIB 1014 is enabled for interrupts there are three events that can cause an interrupt on the VMEbus The first event is an interrupt from the TLC The second event is a GPIB handshake synchronization that occurs when a DMA transfer is finished and the GPIB is synchronized The last event is a bus error that occurs during a DMA transfer Interrupts must be enabled in software to be recognized as described in the following paragraphs The Interrupter circuitry of the GPIB 1014 enables the board to interrupt the CPU to request service The hardware offers programmable selection of the interrupt priority level level 1 to level 7 via Configuration Register 1 Interrupts can be generated on numerous conditions These conditions can also be detected by polling if desired If interrupts are enabled the GPIB 1014 generates an interrupt on any of the following conditions e An interrupt request is received from the GPIB TLC A bus error occurs during a DMA transfer ADMA transfer from memory to the GPIB is complete and the GPIB is synchronized that is all devices have
51. k KK OK RECEIVE ROV okok KKK k k k k k k kk OK Summary Called by READ to receive data if GPIB 1014 is Controller In Charge Called directly from main program to receive data if GPIB 1014 is Idle Controller Assumptions on entry GPIB 1014 is Standby or Idle Controller GPIB 1014 is or will be addressed to listen The GPIB Talker has been or will be addressed The Talker will send END with last byte if the number of bytes sent is less than the byte count The dO register contains the byte count The a0 register contains the address of the data buffer The user specified variable cic is set properly Actions Clear DMAC channel 0 and 1 status registers Configure channel 0 to transfer all but the last byte Configure channel 1 for carry cycle to implement handshake holdoff after last byte Start the DMA channels Release any holdoff in progress Set IMR2 to enable DMAs Wait for DMA done or GPIB END message Disable DMA Set dO register to number of bytes received Status on return a NRFD handshake holdoff is in effect The number of bytes transferred is in dO C 9 GPIB 1014 User Manual Sample Programs 68000 Code TMODE DCRO TMODE DCR1 movb movb GTM OCRO MCU SCRO movb movb FF CSRO FF CSR1 movb movb movl a0 MARO 0 cic RCV1 cmpb beq movb
52. rsv rtl RWD RWLS S8 S 6 1 SACS SCG SDC SDYS SEOI SERCLK SERDAT SGNS SIAS sic SIDS SIIS SINS SIWS SNAS SPAS SPD SPE SPEOI SPIS SPMR SPMS SPMS SPSR SRAS Sre SRIS SRNS SRQ SRQI SRQIIE SRQS STB STRS STRT SWNS National Instruments Corporation LM LM ST Mnemonics Key Request Service Return To Local Release When Done Bit Remote With Lockout State Status Bit Polarity Sense Bit Serial Poll Status Bits 8 and 6 through 1 System Control Active State Secondary Command Group Selected Device Clear Source Delay State Send EOI Serial Clock Serial Data Source Generate State Source Handshake System Control Interface Clear Active State Send Interface Clear Source Idle State System Control Interface Clear Idle State System Control Interface Clear Not Active State Source Idle Wait State System Control Not Active State Serial Poll scanning flags Serial Poll Active State T function Serial Poll Disable Serial Poll Enable Send Serial Poll End Or Indentify Bit Serial Poll Idle State Serial Poll Mode Register Serial Poll Mode State Bit Serial Poll Mode State Serial Poll Status Register Service Request System Control Remote Enable Active State Send Remote Enable System Control Remote Enable Idle State System Control Remote Enable Not Active State Service Request Service Request Input Bit Enable Interrupt on Service Request Input Bit Service Request State St
53. that the PCT bit is set Sending END or EOS To send the GPIB END message with the last data byte use the carry cycle feature as described in the DMA Transfers With A Carry Cycle section earlier in this chapter Terminating the Transfer and Checking the Result If either Channel 0 or 1 is improperly programmed the ERR bit in the CSR of the active channel is set by the DMAC and the CER of the channel indicates a configuration error The following paragraphs assume the channels are properly programmed to allow normal termination of a GPIB DMA transfer They describe how to check the CSR of the channel to determine the success of the GPIB DMA transfers The termination of the GPIB DMA transfer causes an interrupt if interrupts have been enabled in Channel 1 If interrupts are not used this condition can be detected by polling Regardless of whether or not the carry cycle feature is used when the DMA transfer is complete that is all data blocks have been transferred and the GPIB is synchronized that is all Listeners have accepted the last byte a transition occurs on the Channel 1 PCL line of the DMAC The PCT bit in the CSR of Channel is set by this transition This generates an interrupt if Channel 1 is configured to interrupt on a PCL transition This transition can also be detected by polling the CSR of Channel 1 and waiting for the PCT bit to set Once detected the software must service the interrupt condition The first action in
54. the COC to detect if the nth byte has been transferred and GPIB 1014 User Manual 5 18 National Instruments Corporation Chapter 5 Programming Considerations accepted by all Listeners on the GPIB indicating a GPIB synchronization For this reason Channel is programmed to transfer two bytes to avoid a premature COC interrupt After the last data byte the nth byte is transferred the MTCR of Channel 1 contains a 1 and the next DMA request from the TLC is not allowed to reach the DMAC through onboard hardware Channel 1 is still active waiting for another request but never detects one The PCL transition is generated when the GPIB becomes synchronized Note After a DMA transfer in which the carry cycle was used Channel 1 must be stopped by issuing a software abort command before another DMA transfer takes place This is done by writing to the CCR of Channel 1 with the SAB bit set In general after a DMA transfer has completed with or without an error the following actions should be taken Read ISR2 to clear any interrupt bit set 2 Read ISRI 3 Clear IMRI 4 Clear IMR2 5 Write a value to CFGI to unassert the PCL line of Channel 1 A write to CFGI clears the circuitry on the board which generates the GPIB handshake synchronization status signal 6 If a GPIB error occurred during the transfer ERR bit set in the TLC s ISR1 poll the BTAC and MTCR of the DMAC until you are satisfied that no DMA transfers are taking
55. the standard manner Send EOI SEOI The Send EOI command causes the GPIB End Or Identify EOI line to go true with the next byte transmitted The EOI line is then cleared upon completion of the Handshake for that byte The TLC recognizes the Send EOI command only if TA 1 that is the TLC is addressed as the GPIB Talker Non Valid Secondary Command or Address The Non Valid command releases the GPIB DAC message held by the Address Pass Through APT The TLC is permitted to operate as if an Other Secondary Address OSA message has been received Valid Secondary Command or Address The Valid command releases the GPIB DAC message held off by APT and allows the TLC to function as if a My Secondary Address MSA message had been received The DAC message is released at the time of Command Pass Through CPT DAC is also released if DCAS or DTAS is in Holdoff state continues GPIB 1014 User Manual 4 30 National Instruments Corporation Table 4 5 Auxiliary Commands Detail Description continued Command Code COM4 COM0 43210 Description Clear Parallel Poll Flag Set Parallel Poll Flag These commands set the Parallel Poll Flag to the value of COM3 The value of the Parallel Poll Flag is used as the local message ist when bit four of Auxiliary Register B is zero The value of SRQS is used as the ist when ISS 1 Go To Standby The Go To Standby command sets the local message gts if the TLC is in Controller Active S
56. the state machine The timing control begins when one of the signals TLCCS CS1 or CS2 is low indicating that the TLC CFG1 or CFG2 is selected During a read cycle to the TLC the TLC RD signal is immediately driven low The circuitry then counts a minimum delay of 250 nsec which National Instruments Corporation 6 7 GPIB 1014 User Manual Theory of Operation Chapter 6 corresponds to the read access time of the TLC Local signal SACK is asserted to drive VMEbus signal DTACK active to indicate that the data is valid on the VMEbus data lines D07 through DOO The data remains valid and the DTACK signal remains asserted until DSO is released by the bus master When DSO is released the board first disables the data transceiver and then releases DTACK At the same time the circuitry delays for a recovery time of 250 nsec Signal END_RECOVERY is asserted at the end of the 250 nsec period to reset the Timing State Machine At this point the TLC can perform another read write cycle During a write cycle to the TLC CFG1 or CFG2 the timing is similar Once DSO is asserted the TLC signal WR is driven low immediately The WR signal is ANDed with both CS1 and CS2 to drive the clock inputs of the two Configuration Registers Once WR is driven low the circuitry counts a data setup time of 250 nsec SACK then is asserted to drive the VMEbus signal DTACK low At the same time the WR signal is immediately driven high to latch the da
57. to SRQ Send interface messages Receive control Pass control Parallel Poll Take control synchronously or asynchronously El E2 Tri state bus drivers with automatic switch to open Collector drivers during Parallel Poll The GPIB 1014 has complete Source and Acceptor Handshake capability e The GPIB 1014 can operate as a basic Talker or Extended Talker and can respond to a Serial Poll It can be placed in a Talk Only mode and is unaddressed to talk when it receives its listen address The interface can operate as a basic Listener or Extended Listener It can be placed in a Listen Only mode and is unaddressed to listen when it receives its talk address The GPIB 1014 has full capabilities for requesting service from another Controller The ability to place the GPIB 1014 in local mode is included but the interpretation of remote versus local mode is software dependent Full Parallel Poll capability is included in the interface although local configuration requires software assistance Device Clear and Trigger capability is included in the interface but the interpretation is software dependent All Controller functions as indicated by the IEEE 488 standard are included in the GPIB 1014 These include the capability to do the following functions e Be System Controller Initialize the interface Send Remote Enable e Respond to Service Request Send multiline command messages GPIB 1014 User Manual 2 14 National Instrume
58. to clear the ERR flag set by the software abort Using Programmed I O Programming considerations for using programmed I O data transfers are explained in the following paragraphs Sending and Receiving Data When using programmed I O to send or receive a GPIB data byte the DMAO and DMAI bits in IMR2 must be cleared The contents of other GPIB 1014 DMA registers are irrelevant To send data wait until the TLC has been programmed or addressed to talk and the CDOR is empty When this occurs the DO bit in the ISRI is set indicating that it is safe to write a byte to the CDOR The DO bit is set again once that byte has been received by all Listeners To receive data wait until the TLC has been programmed or addressed to listen and the DIR is full When this occurs the DI bit in ISRI is set indicating that the GPIB Talker has written a byte to the DIR Once that byte has been read the DI bit is set again when a new byte is received from the Talker To determine if the CDOR is empty or if the DIR is full either poll ISR1 until the DO or DI status first appears or allow a program interrupt to occur on the respective event Remember however that the status bits and the interrupt signals are cleared when the ISRI is read so the absence of a true DO or DI status does not unambiguously indicate that the CDOR is still full or that the DIR is still empty Sending END or EOS Send the GPIB END message by issuing the Send EOI auxiliary command
59. to send and the DO bit is set Caution Some instruments are very sensitive to assertions of ATN at what they may consider the wrong time and can lose data abort operations being performed or in some severe cases become completely nonresponsive Consult your instrument s manual carefully to make sure any such situations can be avoided GPIB 1014 User Manual 5 4 National Instruments Corporation Chapter 5 Programming Considerations Case 2 The TLC as a Listener takes control upon receipt of the Take Control Synchronously auxiliary command If programmed I O is used the Take Control Synchronously auxiliary command should be issued between seeing a DI status bit and reading the last byte from the DIR If DMA is used a handshake holdoff must be in effect after the last data byte is read in order for the Take Control Synchronously auxiliary command to work properly This is accomplished by first writing 100XX110 binary to the AUXMR Writing this byte to the AUXMR issues the RFD holdoff on End mode auxiliary command to the TLC and also causes the END bit in ISR1 to be set at reception of the EOS message Next the carry cycle feature of the GPIB 1014 should be used to cause the RFD holdoff on all data mode auxiliary command to be written to AUXRA before the DMAC reads the last data byte from the TLC Finally set the CC bit in CFGI and then start the DMA transfer When the DMA transfer has finished either from an END interrupt o
60. w EINT Interrupt Enable Bit The Interrupt Enable bit in used to enable or disable interrupts from the channel GPIB 1014 interrupts are discussed in more detail in Chapter 5 O No interrupts enabled 1 Interrupts enabled 2 0r w 0 Reserved Bits Write zeros to these bits National Instruments Corporation 4 57 GPIB 1014 User Manual Register Descriptions Chapter 4 Channel Status Register VMEbus Address Base Address 00 hex Attributes Read Write Internal to DMAC 7 6 5 4 3 2 1 0 The Channel Status Register CSR bits are set automatically by DMAC Bits are cleared by writing a one 1 to each register bit or by resetting the DMAC Bit Mnemonic Description Tr w COC Channel Operation Complete bit The Channel Operation Complete bit is set if the DMA transfer has completed This bit is set following the termination whether successful or not of any DMA operation This bit must be cleared to start another channel operation O Channel operation incomplete 1 Channel operation complete 6r w BTC Block Termination Complete Bit The Block Termination Complete bit is set when the memory transfer count is exhausted the operation is unchained and the continue bit is set This bit must be cleared before another continuation is attempted otherwise an operation timing error is signaled See The Continue Mode of Operation in Chapter 6 for more information O Block transfer incomplete 1 Block transfer complete Sr
61. 0 GPIB 1014 User Manual Index 13 National Instruments Corporation Index COMMAND SEND CSEND C 19 DATA SEND DSEND C 14 to C 16 GPIB 1014 Sample Functions for Driver C 2 to C 4 INITIALIZE INIT C 5 to C 6 INTERFACE CLEAR IFC C 7 overview C 1 PASS CONTROL PASSC C 21 READ C 12 to C 13 RECEIVE RCV C 11 REMOTE ENABLE REN C 8 WRITE C 17 to C 18 sending receiving messages DMA transfers with carry cycle 5 13 to 5 17 DMA transfers without carry cycle 5 10 to 5 12 overview 5 8 polling during DMAs 5 17 sending and receiving data 5 19 to 5 20 sending END or EOS 5 17 5 20 terminating on END or EOS 5 19 5 20 terminating transfer and checking results 5 17 to 5 19 using direct memory access 5 8 to 5 9 using programmed I O 5 19 to 5 20 serial polls 5 22 Talker and Listener addressed implementation 5 6 to 5 8 National Instruments Corporation Index 14 GPIB 1014 User Manual Index overview 5 6 programmed implementation 5 6 R READ sample program C 12 to C 13 RECEIVE RCV sample program C 11 receiving messages See sending receiving messages registers Configuration registers definition of 2 12 DMA Configuration registers 4 64 to 4 67 GPIB 1014 Configuration registers chart 2 5 DMA registers 68450 internal DMA registers chart 2 5 address registers 4 48 Base Address Register BAR 4 48 Base Transfer Counter Register MTCR 4 48 Channel Control Register 4 56 to 4 57 Channel Er
62. 014 has all the necessary signals needed by the system and vice versa Note For models GPIB 1014 1S and GPIB 1014 1S EH there are no signals connected to the P2 connector except for power 5 V and ground signals National Instruments Corporation 3 7 GPIB 1014 User Manual Configuration and Installation Chapter 3 Table 3 3 GPIB 1014 Pin Assignment on VMEbus Connector P1 Signal Used Signal Not Used Signal Used Signal Not Used Al DOO GND D01 AS D02 GND D03 IACK D04 IACKIN D05 IACKOUT D06 AMA D07 A07 GND A06 SYSCLK A05 GND A04 DS1 A03 DSO A02 WRITE A01 GND DTACK 5V BBSY BCLR ACFAIL BGOIN BGOOUT SERCLK BGIIN SERDAT BGIOUT BG2IN BG20UT BG3IN BG30UT BRO BRI BR2 BR3 5V STDBY AMO D08 D09 D10 D11 D12 D13 D14 D15 GND SYSFAIL BERR SYSRESET LWORD AMS A23 A22 GPIB 1014 User Manual 3 8 National Instruments Corporation Chapter 3 Configuration and Installation Table 3 4 GPIB 1014 Pin Assignment on VMEbus Connector P2 Signal Signal Signal Signal Used Not Used Notes Pin No Used Not Used 1 4 User I O 1 4 User I O 1 4 User I O 1 4 User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User I O User
63. 1014 User Manual Register Descriptions Chapter 4 The following paragraphs describe the channel configuration and status registers More information on the 68450 can be found in the Motorola Semiconductor Technical Data MC68450 Advance Information Direct Memory Access Controller DMAC or the Hitachi Microcomputer System HD68450 DMAC Direct Memory Access Controller Each channel contains the same status and configuration registers Address Registers The Memory Address Register MAR Base Address Register BAR and Device Address Register DAR are 32 bit registers Due to packaging limitations only the least significant 24 bits are connected to the address output pins The Memory Address Register MAR is used to hold the address of the VMEbus memory location which is where the data is transferred This register is used in all DMA operations memory to memory or memory to device The Base Address Register BAR is used in continue array chained and link chained operations In continue mode of operation the BAR holds the address of the next block of data to be transferred At the end of the last block transfer the content of the BAR is automatically transferred to the MAR and a next block transfer is started In array chained and link chained modes of operation the BAR is used as a pointer to a table in memory which holds the address es of the data block s to be transferred Using the BAR in the chained modes of operation the DMAC
64. 14 as GPIB Controller The GPIB 1014 Controller function is generally in one of two modes idle or in charge When in charge the Controller function is either active asserting ATN or standby not asserting ATN The following section discusses the various transitions between these two modes Becoming Controller In Charge CIC and Active Controller The TLC can become CIC either by being the System Controller and taking control by issuing the Set IFC auxiliary command or by being passed control of the GPIB from the current Active Controller The GPIB 1014 is only capable of driving the GPIB IFC and REN lines which allows the TLC to function as GPIB System Controller when the SC bit in CFG2 is set To take control issue the Set IFC auxiliary command wait for a minimum of 100 usec and then issue the Clear IFC auxiliary command The ensuing GPIB IFC message initializes the GPIB interface functions of all devices on the bus As soon as any existing CIC goes to idle dropping ATN if it was active the TLC becomes CIC and Active Controller and asserts the GPIB ATN line Another Active Controller passes control to the GPIB 1014 by sending the TLC GPIB talk address MTA followed by the GPIB Take Control TCT message The TLC upon receiving these two messages MTA and TCT automatically becomes CIC when ATN is dropped The exact sequence of events is as follows 1 The TLC receives the My Talk Address MTA The TLC then enters into Talker Ad
65. 160AN Control Transceivers DS75162AN Note The GPIB 1014 requires regulated 5 VDC power from the VMEbus Current load is typically 1 6 A 2 0 A maximum VMEbus Characteristics The following paragraphs describe each of the VMEbus modules on the GPIB 1014 slave master interrupter and requester Table 2 5 at the end of this chapter summarizes the capabilities of these modules VMEbus Slave Addressing The GPIB 1014 occupies 512 bytes 256 words in the A16 short I O space As a VMEbus slave it only responds when the address modifier AM lines specify a short supervisory access AM code 2D or a short nonprivileged access AM code 29 The board responds to short 16 bit addresses The GPIB 1014 compares address lines A15 through A9 with its base address GPIB 1014 User Manual 2 2 National Instruments Corporation Chapter 2 General Description to generate its board select signal It then decodes the lowest eight lines A8 through A1 to address the following items e The 68450 DMA Controller DMAC The uPD7210 GPIB Talker Listener Controller TLC Two 8 bit write only Configuration Registers You can configure the base address of the board through the hardware jumper set W1 located on the interface board Except for the models GPIB 1014 1S and GPIB 1014 1S EH the base address can also be set using strapped address lines located on the VMEbus P2 connector See Chapter 3 Configuration and Installation on how to set the
66. 4 verification of system compatibility 3 7 to 3 9 verification testing 3 10 INT Interrupt Bit 4 14 to 4 15 INTERFACE CLEAR IFC sample program C 7 interface management lines ATN attention E 3 EOI end or identify E 3 IFC interface clear E 3 overview E 3 REN remote enable E 3 SRQ service request E 3 interface registers Address Mode Register ADMR 4 22 to 4 24 Address Register ADR 4 43 Address Register 0 ADRO 4 42 Address Register 1 ADR1 4 44 Address Status Register ADSR 4 20 to 4 21 Auxiliary Mode Register AUXMR 4 27 to 4 33 Command Data Out Register CDOR 4 7 Command Pass Through Register CPTR 4 25 to 4 26 Data In Register DIR 4 6 End of String Register EOSR 4 45 hidden registers Auxiliary Register A AUXRA 4 37 to 4 38 Auxiliary Register B AUXRB 4 39 to 4 40 Auxiliary Register E AUXRE 4 41 Internal Counter Register ICR 4 34 overview 4 33 Parallel Poll Register PPR 4 35 to 4 36 illustration 4 4 Interrupt Mask Register 1 IMR1 4 8 to 4 13 Interrupt Mask Register 2 IMR2 4 14 to 4 18 Interrupt Status Register 1 ISR1 4 8 to 4 13 Interrupt Status Register 2 ISR2 4 14 to 4 18 overview 4 3 National Instruments Corporation Index 10 GPIB 1014 User Manual Index register map 4 1 Serial Poll Mode Register SPMR 4 19 Serial Poll Status Register SPSR 4 19 writing to hidden registers 4 4 Internal Counter Register ICR 4 34 interrupt control See GPIB Synch
67. 4 43 GPIB 1014 User Manual Register Descriptions Chapter 4 Address Register 1 ADR1 VMEbus Address Base Address 11F hex Attributes Read Only Internal to TLC 7 6 5 4 3 2 1 0 R Address Register 1 ADR1 indicates the status of the GPIB address and enable bits for the secondary address of the TLC if mode 2 addressing is used or the minor primary address of the TLC if dual primary addressing is used modes 1 and 3 If mode 1 addressing is used and only a single primary address is needed both the talk and listen addresses disable in this register If mode 2 addressing is used the talk and listen disable bits in this register must match those in ADRO Bit Mnemonic Description Tr EOI End Or Identify Bit EOI indicates the value of the GPIB EOI line latched when a data byte is received by the TLC GPIB Acceptor Handshake AH function If EOI 1 the EOI line was asserted with the received byte EOI is cleared by pon or by using the Chip Reset auxiliary command EOI is updated after each byte is received 6r DTI Disable Talker 1 Bit If DTI is set the mode 2 secondary or mode 1 and 3 minor Talker function is not enabled that is the TLC does not respond to a secondary address or minor primary talk address formed from bits AD 5 1 1 1 If DTI is cleared the secondary address is checked only if the TLC received its primary talk address that is is in TPAS 5r DLI Disable Listener 1 Bit If DL1 1 the mode 2 secondar
68. 40 11B CPTR 0 cleared OFF GCR 0 007 CCRO 0 047 CCRI 2 0 000 CSRO 01 040 CSRI 01 065 NIV1 OF 067 EIV1 OF 3 Test DMAC Channel Address Registers 105 CFG2 0A Set LMR and turn LED green 105 CFG2 08 Clear LMR 00C MARO 5533 00C MARO 5533 04C MARI 5533 04C MARI 5533 01C BARI 5533 01C BARI 5533 4 Test Local Master Reset GPIB 1014 User Manual 7 2 National Instruments Corporation Chapter 7 105 065 065 067 067 105 105 065 067 5 Test ton DO ERR CPTR TA 105 105 11B 119 11B 119 113 111 11B 113 113 11B 119 11B 119 CFG2 08 NIVI 55 NIVI 55 EIVI 55 EIVI 55 CFG2 0A CFG2 08 NIV1 OF EIV1 0F CFG2 0A CFG2 08 AUXMR 2 ADMR 80 AUXMR 0 ADSR 42 ISR1 2 CDOR 51 CPTR 51 ISR1 6 ISR1 0 AUXMR 2 ADMR 0 AUXMR 0 ADSR 40 6 Check lon LA 105 105 11B 113 115 119 11B 119 11B 119 105 105 11B 119 11B CFG2 0A CFG2 08 AUXMR 2 IMRI 0 IMR2 0 ADMR 40 AUXMR 0 ADSR 44 AUXMR 2 ADSR 40 Test ATN CIC CO CFG2 0B CFG2 09 AUXMR 2 ADMR 31 AUXMR 0 National Instruments Corporation Diagnostic and Troubleshooting Test Procedures Clear LMR Set LMR and turn LED green Clear LMR Set LMR and turn LED green Clear LMR TLC Reset ton Immediate execute pon TA DO write data byte verify DO ERR bits cleared when read TL
69. 5 X BMM RSD CSKHD ZPS 12 16 745176 01 2 0000 SCHR 21100 662 SLEEVE 5 9 X 3 3 DIA SS 13 17 742412 01 2 0000 SCHR 21100 379 SCREW 2 5 X 11MM CAPTIVE NPS 16 18 745096 01 2 0000 SCHR 20809 295 HANDLE HP GRAY 15 19 180149 01 1 0000 MI 180149 01 LABEL GPIB 1014 GPIB VME 16 20 180189 01 1 0000 NC 180189 01 LABEL GPIB 1014 NATL INST 17 21 180158 12 1 0000 PANEL GP18 1014 CHAMP 18 24 753025 01 1 0000 NI 753025 01 LABEL FCC WARNING CLASS A 19 A01 180155 00G 1 0000 CCA GP18 1014 BASELINE 20 ia 180168 01 1 0000 NI 180168 01 CONN CHAMP 24 PIN DISASSEMBLED 21 National Instruments Corporation B 9 GPIB 1014 User Manual Appendix C Sample Programs This appendix contains listings of routines in 68000 assembly language code that implement the essential elements of these major utility functions Initialize the GPIB 1014 interface INIT Initialize the interface functions of the GPIB devices IFC e Set or clear the GPIB REN line REN e Accept data bytes from a Talker RCV e Address Talker and read device dependent messages READ Send data bytes to Listeners DSEND e Address Listener and write device dependent messages WRITE Send command bytes to Listeners CSEND Write interface messages CMD e Pass GPIB control to another device PASSC Assumptions regarding the state of the GPIB 1014 appear at the beginning of each routine and must be adhered to for proper error free operation The foll
70. 68450 DMAC Da o 2 2 3 o 2 Iz dd n 3 ea n d n Ss S E e o e Priority Interrupt DTB Arbitration Configuration Registers D SIOAIOOSUEJT vq IYW IPIS guru SIQAIOOSUEI SIOATOOSURIL 10u00 q d Jonuoz sso1ppy SIOAIOOSUPIT eq SuIposaq SIOAIQOSUPIT SSoIPpV ssoppy SOQHINA 2 11 GPIB 1014 User Manual Figure 2 3 GPIB 1014 Block Diagram National Instruments Corporation General Description Chapter 2 The interface consists of these major components which are discussed in greater detail in Chapter 6 VMEbus Interface Address Decoder Clock and Reset Circuitry Configuration Registers Timing State Machine DMA Gating and Control Interrupter DTB Control Transceivers GPIB Synchronization and Interrupt Control DMAC 68450 GPIB TLC NEC uPD7210 GPIB 1014 User Manual Consists of the buffers drivers and transceivers for the address data status and control lines used on the VMEbus plus other logic circuitry that converts internal signals to bus compatible signals Recognizes when the VMEbus master addresses one of the GPIB 1014 registers and generates the appropriate strobe to begin the data transfer Monitors the VMEbus utility signals to generate the 8 MHz clock used by the TLC and DMAC and to detect System Reset Power Failure and Bus Error conditions Programmably configures some of the operating parameters of the GPIB 1014 Controls the timin
71. 737 4644 U K 01635 523545 01635 523154 National Instruments Corporation G 1 GPIB 1014 User Manual Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax Phone Computer brand Model Processor Operating system Speed MHz RAM MB Display adapter Mouse yes no Other adapters installed Hard disk capacity MB Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps will reproduce the problem GPIB 1014 Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Update this form each time you revise your software or hardware configuration and use this f
72. 743 01 1 0000 U26 700171 01 1 0000 U27 700310 01 1 0000 u28 700740 01 1 0000 U29 700706 01 1 0000 u30 700013 01 1 0000 U31 700012 01 1 0000 U32 700562 01 1 0000 U33 700418 01 1 0000 GPIB 1014 User Manual MFR TI TI TI TI TI TI SIG MEC TI TI Ti TI TI TI NSC TE TI Ti TI TI TI TI TI MFR PART SN74LS240N SN74F245N SN74LS240N SH74LSO2N SN74LS241N SN74F241N SN74145N N74F85N UPD7210 SN74F245N AM25LS2521PC SN74LS273N SN74LS32K SN74LS32N SN74LS20N SN74F245N DM74AS573 SN74LS38N SN745139AN SN74F20N SN74F74N SN74LS74AN SN74LS74AN SN74F245M SN74F32M B 6 PRODUCT DESCRIPTION 1C LS240 BUFFER DREVER 1C F245 TRANSCEIVER IC LS240 BUFFER DRIVER IC LS02 2 INP NOR IC LS241 BUFFER DRIVER IC F241 0CTAL BUFFER 3 STATE 1C 74145 8CD TO DECIMAL DECODE IC F85 4 BIT MAGNITUDE COMP IC 7210 GP B INTFC CNTRLR IC F245 TRANSCEIVER IC LS2521 8 B1T EQUAL TO CMPTR IC LS273 FLIP FLOP IC LS32 2 INP OR IC LS32 2 INP OR IC LS20 4 IMP NAND IC F245 TRANSCEIVER IC AS573 0CTAL D LATCHES 3STAT IC LS38 2 INP NAND BUFFER 1C 139 DCDR DMUX IC F20 DUAL 4INPUT NAND IC F74 FLIP FLOP IC LS74 FLIP FLOP 1C LS74 FLIP FLOP IC F245 TRANSCEIVER 1C F32 QUAD 2 INPUT OR National Instruments Corporation 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 Appendi
73. ASE 0x101 BASE 0x105 GPIB 1014 User Manual Appendix C GPIB 1014 Sample Functions for Driver INIT Initialize the GPIB 1014 IFC Send Interface Clear REN Set Clear Remote Enable RCV Receive READ Read Data DSEND Data Send WRITE Write Data CSEND Command Send CMD Write Commands i PASSC Pass Control Base address of GPIB 1014 interface Data In Register read Control Data Out Register write Interrupt Status Register 1 read Interrupt Mask Register 1 write Interrupt Status Register 2 read Interrupt Mask Register 2 write Serial Poll Status Register read Serial Poll Mask Register write Address Status Register read Address Mode Register write Command Pass Thru Register read Auxiliary Mode Register write Address Register 0 read Address Register write Address Register 1 read End Of String Register write Channel 0 Memory Transfer Count Channel 0 Memory Address Register Channel 0 Memory Function Code Channel 0 Status Register Channel 0 Device Control Register Channel 0 Operation Control Register Channel 0 Sequence Control Register Channel 0 Channel Control Register Channel 1 Memory Transfer Count Channel 1 Memory Address Register Channel 1 Memory Function Code Channel 1 Base Transfer Count Channel 1 Base Address Register Channel 1 Base Function
74. ATN the TLC unasserts SRQ and transfers the STB message onto the GPIB data bus with DIO7 the RQS signal asserted While the Serial Poll is in progress SPAS 1 the CIC normally reads the STB only once however it can read STB any number of times RQS rsv and PEND are cleared when the CIC asserts ATN to terminate the poll The GPIB EOI line is asserted along with the status byte that is the END message is sent during the Serial Poll if bit Bl of the AUXRB is set Parallel Polls Parallel Polls are used by the GPIB Active Controller to check the status of several devices simultaneously The meaning of the status returned by the devices being polled is device dependent Two general ways in which Parallel Polls are useful are as follows e When the GPIB Controller sees SRQ asserted in a system with several devices it can quickly determine which one needs to be serial polled usually using only one Parallel Poll nsystems in which the Controller response time requirement to service a device is low and the number of devices is small Parallel Polls can replace Serial Polls entirely provided that the Controller polls frequently National Instruments Corporation 5 23 GPIB 1014 User Manual Programming Considerations Chapter 5 Although the Controller can obtain a Parallel Poll response quickly and at any time there can be considerable front end overhead during initialization to configure the devices to respond appropriately Thi
75. B RELEAEAEAEREE MW IAIRIHA IR IERE SETE FERESE RARI IRR EIR III III REE III SISSIES EARNER ERIN AER eee END PRODUCT PRODUCT DESCRIPTION REVISION LEVEL 180155 00G CCA GPIB 1014 BASELINE G ITEM NO WI PART HO QTY REQD MFR MFR PART PRODUCT DESCRIPTION 01 180157 01 1 0000 NI 180157 01 PWB GPIB 1014 1 02 742410 01 4 0000 SCHR 21100 138 SCREW 2 5 X 10MM FLSTRHD 2PS 2 E 745067 01 0 0000 LOCTITE 242 LOCTITE 3 0 740009 01 4 0000 SCHR 21100 144 NUT 2 5MM HEX ZPS 4 14 760014 02 11 0000 AMP 531220 3 CONN MINI JUMP 2 POS SHORT 5 C01 715079 01 1 0000 AVX SA105 473ZAA CAP 047UF 50V 80 20 CER AX 6 C02 715079 01 1 0000 AVX SA1 PEREBA CAP 047UF 50V 80 20 CER AX 7 COS 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 8 C04 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 9 C05 715079 01 1 0000 AVX SA105E4732AA ns 047UF 50V 80 20 CER AX 10 C06 715079 01 1 0000 AVX SATOSE473ZAA CAP 047UF 50V 80 20 CER AX 11 C07 715079 01 1 0000 AVX SA105E4732AA CAP 047UF SOV 80 20 CER AX 12 C08 715079 01 1 0000 AVX SA105E473ZAA CAP 047UF 50V 80 20 CER AX 13 C09 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20X CER AX 14 C10 715079 01 1 0000 AVX SA105E4732AK CAP 047UF 50V 80 20X CER AX 15 CM 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 16 c12 715079 01 1 0000 AVX SATOSEG73ZAA CAP O47UF 50V 80 20 CER AX 17 Ci3 715079 01 1 0000 AVX SA105
76. B message 3 letters lowercase Local GPIB message Ends in R RO R1 R2 GPIB Program Register Appendix F contains an alphabetical list of mnemonics National Instruments Corporation 4 3 GPIB 1014 User Manual Register Bit Descriptions Chapter 4 Interface Registers Twenty one GPIB Interface registers eight of which are readable and 13 of which are writable are located within the NEC uPD7210 Talker Listener Controller TLC integrated circuit Each of the 21 interface registers is addressed relative to the GPIB 1014 VMEbus base address Figures 4 1 and 4 2 show the register and bit mnemonics of each TLC internal register its read write accessibility and its relative address Figure 4 1 shows the regular GPIB 1014 GPIB Interface registers Figure 4 2 shows the hidden GPIB interface registers and illustrates the method of writing to those registers via the Auxiliary Mode Register Following Figures 4 1 and 4 2 are detailed function descriptions of all 21 interface registers GPIB 1014 User Manual 4 4 National Instruments Corporation Chapter 4 Register Bit Descriptions Contents of Read Register Bit Bit Bit Bit Bit Bit slash Contents of Write Register Fem aer oer poof pec em o pr co Co sor pwao war co roe jew apse KNIE Ds 9 Le e pron mw v T s S6 S6 EO S4 S4 X Note X indicates bit is not used SV on T1 Figure 4 1 Interface Registers National Instrumen
77. C DS1013M DDL 40NS 3 IN 1 162 w01 760013 07 3 0000 DUPO 65500 107 CONN BRGSTK HDR SGL ROM 7 POSN 163 w02 760013 03 1 0000 BERG 65500 103 HEADER SGL ROW STR 1 CTR SPOS 164 W03 760015 03 1 0000 BERG 65500 103 HEADER SGL ROW STR 1 CTR 3POS 165 w04 760013 03 1 0000 BERG 65500 103 HEADER SGL ROW STR 1 CTR 3POS 166 w05 760013 03 1 0000 BERG 65500 103 HEADER SGL ROW STR 1 CTR 3POS 167 GPIB 1014 User Manual BS National Instruments Corporation Appendix B i Parts List and Schematic Diagrams EREA KEREDE RIE AEAEE ARE EDE AEEA AEAEE RIVA III IIIA IIE HA AEEA AE k III IIIIAIAIIN ERI LIZ IICI ARIA III END PRODUCT PRODUCT DESCRIPTION REVISION LEVEL 180155 01G CCA GPIB 1014 1 REVG1 6 ITEM NO NI PART HO QTY REQD MFR MFR PART PRODUCT DESCRIPTION 02 742510 01 2 0000 SCHR 21100 138 SCREM 2 5 X 104M FLSTRHD 2PS 1 03 755047 01 0 0000 LOCTITE 242 LOCTITE 2 05 180188 01 1 0000 NI 180188 01 EMI SHIELD CONN CHAMP 3 06 180187 01 2 0000 NI 180187 01 JACKSOCKET CHAMP METRIC LONG 4 07 740406 01 2 0000 740406 01 WASHER 10 LOCK SPLIT ZPS 5 745100 01 2 0000 ZIER 741 ANGLE BKT 4 40 THD HOLE 6 09 740912 01 2 0000 740912 01 SCREW 4 40x5 16 PNH SS 7 40 740401 01 4 0000 740401 01 WASHER 4 LOCK INT TH ZPS 8 11 740001 01 2 0000 740001 01 NUT 4 40 HEX ZPS 9 12 745108 01 3 0000 SCHR 60807 181 PWB HOLDER DIE CAST 10 15 742413 01 3 0000 SCHR 21100 140 SCREW CHEESE HD M2 5x8 ZPS 1 15 740705 01 1 0000 SCHR 21100 429 SCREM 2
78. C Reset disable ton Immediate execute pon not TA Set LMR and turn LED green Clear LMR TLC Reset no interrupts no interrupts lon Immediate execute pon LA TLC Reset not LA Set LMR and turn LED green Clear LMR and become System Controller TLC Reset Address Mode 1 Immediate execute pon 7 3 GPIB 1014 User Manual Diagnostic and Troubleshooting Test Procedures 11B AUXMR 1E 11B AUXMR 16 119 ADSR 80 115 ISR2 9 11B AUXMR 10 119 ADSR C0 8 Test DMA Error 105 CFG2 0A 105 CFG2 08 007 CCRO 80 007 CCRO 10 000 CSRO 91 000 CSRO 90 000 CSRO 01 9 Test DMAC Interrupt Detection 105 CFG2 0A 105 CFG2 08 044 DCRI 00 040 CSRI FF 11B AUXMR 2 11B AUXMR AO 119 ADMR 80 113 IMRI 2 11B AUXMR 0 040 CSRI 2 113 ISR1 2 040 CSRI 3 040 CSRI FF 040 CSRI 01 Chapter 7 set IFC clear IFC CIC CO ADSC go to standby CIC ATN Set LMR and turn LED green Clear LMR start channel 0 abort channel 0 COC amp Error clear bits bits cleared Set LMR and turn LED green Clear LMR PCL Status Input channel 1 Clear bits channel 1 TLC Reset Clear INV ton DO IE Immediate execute pon PCL transition occurred DO TLC interrupt cleared bit reset 10 Test memory to memory flowthrough DMA transfer 105 CFG2 0A 105 CFG2 08 080 CSR2 FF 084 DCR2 08 085 OCR2 11 086 SCR2 05 08A MTC2 0005 0A9 MFC2 06 OBI DFC2 06 08C MAR2 daddr
79. CPR 4 61 Channel Status Register CSR 4 58 to 4 59 Chip Reset command codes for 4 28 description 4 29 CHN Chain Bits 3 through 2 4 53 CIC Controller In Charge Bit 4 20 Clear IFC command codes for 4 28 description 4 32 Clear Parallel Poll Flag command codes for 4 28 description 4 31 Clear REN command codes for 4 28 description 4 32 CLK 3 0 Clock Bits 3 through 0 4 34 clock and reset circuitry definition 2 12 theory of operation 6 4 to 6 5 CNT Continue Bit 4 56 6 18 CNT 2 0 Control Code Bits 2 through 0 4 27 CO Command Out Bit 4 16 CO IE Command Out Interrupt Enable Bit 4 16 COC Channel Operation Complete Bit 4 58 4 62 COM 4 0 Command Code Bits 4 through 0 4 27 COMMAND CMD sample program C 20 Command Data Out Register CDOR 4 7 Command Pass Through Register CPTR 4 25 to 4 26 COMMAND SEND CSEND sample program C 19 commands auxiliary commands detailed description 4 29 to 4 32 summary table 4 28 GPIB 1014 User Manual Index 3 National Instruments Corporation Index commands or command messages E 1 multiline GPIB commands table 4 25 to 4 26 D 2 to D 3 compare address lines location of 3 3 setting base address 3 4 compliance levels for GPIB 1014 IEEE 1014 interrupter 2 15 configuration access mode 3 3 base address 3 3 to 3 4 DMA address modifier code output 3 5 to 3 7 hardware jumpers 3 1 jumpers and switches illustration 3 2 other configuration pa
80. Descriptions een eee 4 1 Register Mapa iaia 4 1 RESISICE SIZES al ilari e aio 4 2 National Instruments Corporation vii GPIB 1014 User Manual Contents Register Description oes treat iinis i oare E E Rin as dinies 4 2 Register Description Format ira 4 3 Interface Registers i acne e eras EO RESI UU IRE CI MEER a eH AREA E a 4 3 Data Resiste DIR 4 6 Command Data Out Register CDOR eee 4 7 Interrupt Status Register IISRI colera palio 4 8 Interrupt Mask Register 1 IMR1 acilia lar 4 8 Interrupt Status Register 2 ISR2 Sirion 4 14 Interrupt Mask Register 2UIMR2 lele 4 14 Serial Poll Status Register SPSR scsisisasssessvassavasesveasasesracddscacecenspsvaavetoesabeesnnece 4 19 Serial Poll Mode Register SPMR eese nennen 4 19 Address Status Register ADSR arietes earn 4 20 Address Mode Register ADMR i ceteseecia tss oeo aaa 4 22 Command Pass Through Register CPTR eene 4 25 Auxiliary Mode Register AUXMR eese nennen 4 27 Hidden RESisters P 4 33 Internal Counter Register ICR ace eoe eee eed 4 34 Parallel Poll Register PPR zoe eboli 4 35 Auxiliary Register A AUXRA loi alii liiarazi 4 37 Auxiliary Register B CAUXRDB y aiar 4 39 Auxiliary Register E AUXRE Messe aula sicae x Qe redet oed dee NUR UR 4 4 Address Register O ADRO Sac e a iaoi aenieiai 4 42 Address Register ADR ansore ae eae io ici rai 4 43 Address R
81. E 488 standard codes Table 2 5 GPIB 1014 IEEE 488 Interface Capabilities Complete Source Handshake capability Complete Acceptor Handshake capability DAC and RFD Holdoff on certain events Complete Talker capability Basic Talker Serial Poll Talk Only mode Unaddressed on MLA Send END or EOS Dual primary addressing Complete Extended Talker capability Basic Extended Talker Serial Poll Complete Extended Talker capability continued Talk Only mode Unaddressed on MSA LPAS Send END or EOS Dual primary addressing Complete Listener capability Basic Listener Listen Only mode Unaddressed on MTA Detect END or EOS Dual extended addressing with software assist Complete Extended Listener capability Basic Listener Listen Only mode Unaddressed on MSA TPAS Detect END or EOS Dual extended addressing with software assist Complete Service Request capability Complete Remote Local capability with software interpretation Remote Parallel Poll configuration Local Parallel Poll configuration with software assist continues National Instruments Corporation 2 13 GPIB 1014 User Manual General Description Chapter 2 Table 2 5 GPIB 1014 IEEE 488 Interface Capabilities continued DCI Complete Device Clear capability with software interpretation DTI Complete Device Trigger capability with software interpretation C1 C2 C3 C4 C5 Complete Controller capability System Controller Send IFC and take charge Send REN Respond
82. E4732AA CAP 047UF 50V 80 20X CER AX 18 14 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 19 c15 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 20 ci 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 21 c17 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 22 GPIB 1014 User Manual B 2 National Instruments Corporation Appendix B Parts List and Schematic Diagrams Ee e e e e Ve e PE IRR EE r Ae Se e Ae Ae e e e e EE EERERR AIRE de e e e Ae Se AE AE e e de Ae EEA ITT IOI AS ie fe Ae Fe de de OSTA a iri bene ER eee dede eee ITEM NO NE PART NO QTY REQD MFR MFR PART PRODUCT DESCRIPTION C18 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 23 C19 715079 01 1 0000 AVX SA105E473ZAA CAP 047UF 50V 80 20 CER AX 24 C20 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX c21 715079 01 1 0000 AVX SAT05E4732AA CAP O47UF 50V 80 20x CER AX 26 c22 715079 01 1 0000 AVX SATOSE473ZAA CAP O47UF 50V 80 20 CER AX 27 23 715079 01 1 0000 AVX SA105E473ZAA CAP 047UF 50V 80 20 CER AX 28 C24 715079 01 1 0000 AV SA105E4732AA CAP mo CER AX c25 715079 01 1 0000 AVX SAT05EA732AA CAP O47UF 50V 80 20 CER AX C26 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 31 C27 715079 01 1 0000 AVX SA105E473ZAA CAP O47UF 50V 80 20 CER AX 32 C28 715079 01 1 0000 AVX SA105E473ZAA CAP 047UF 50V
83. EE 488 specification The most familiar of these delay times T1 is the minimum delay between placing the data or command bytes on the GPIB DIO lines and asserting DAV These delay times vary depending on the type of transfer in progress and the value of the AUXRB bit TRI For proper operation ICR should be set to eight because the TLC is clocked at 8 MHz GPIB 1014 User Manual 4 54 National Instruments Corporation Chapter 4 Register Descriptions Parallel Poll Register PPR VMEbus Address Base Address 11B hex AUXMR Control Code 011 Binary Bits 7 5 Attributes Write Only Internal to TLC Accessed through AUXMR 4 3 2 1 0 W This 5 bit command code determines the manner in which the TLC responds to a Parallel Poll When using the remote Parallel Poll Configure IEEE 488 capability code PP1 do not write to the PPR The TLC implements remote configuration fully and automatically without software assistance The hardware recognizes interprets and responds to Parallel Poll Configure PPC Parallel Poll Enable PPE Parallel Poll Disable PPD and Identify IDY messages It is only necessary to set or clear the individual status ist message using Set Clear Parallel Poll Flag auxiliary commands according to pre established system protocol convention Writing to the PPR after it is remotely configured will corrupt the configuration When using the local PPC capability code PP2 a valid PPE or PPD message must be w
84. ELS Remote Change Bit Remote Change Interrupt Enable Bit REMC is set by any change in REM REMC is cleared by pon read ISR2 Notes REM ISR2 4 r pon Power On Reset read ISR2 Bit is cleared immediately after it is read REMC is set when there is a change in the REM bit ISR2 4 r REMS RELS Addressed Status Change Bit Addressed Status Change Interrupt Enable Bit ADSC is set by any change in TA any change in LA any change in CIC any change in MJMN amp lon ton ADSC is cleared by pon read ISR2 Register Bit Descriptions Chapter 4 Bit Mnemonic Description Notes TA Talker Active bit ADSR 1 r LA Listener Active bit ADSR 2 r CIC Controller In Charge bit ADSR 7 r MJMN Major Minor bit ADSR O r lon Listen Only bit ADMR 6 w ton Talk Only bit ADMR 7 w pon Power On Reset read ISR2 Bit is cleared immediately after it is read ADSR Address Status Register ADMR Address Mode Register ADSC is set when there is a change in one of the four bits TA LA CIC or MIMN of the Address Status Register ADSR GPIB 1014 User Manual 4 18 National Instruments Corporation Serial Poll Status Register SPSR VMEbus Address Base Address 117 hex Attributes Read Only Internal to TLC Serial Poll Mode Register SPMR VMEbus Address Base Address 117 hex Attributes Write Only Internal to TLC 7 6 5 4 3 2 1 0 R W Bit Mnemonic Description Tr S8 Serial Poll Status Bit
85. Ebus memory 0 Transfer from memory to device 1 Transfer from device to memory In GPIB applications 0 indicates transfers from memory to GPIB and 1 indicates transfers from GPIB to memory 6r w 0 Reserved Bit Write zero to this bit 5 Ar w SIZE Size Bits 5 through 4 The Size bits indicate the size of the data transfer For the GPIB 1014 GPIB transfers the size is always byte 00 For memory to memory transfers the size can be byte word or long word 00 Byte 8 bits 01 Word 16 bits 10 Long word 32 bits 11 undefined reserved 3 2r w CHN Chain Bits 3 through 2 The Chain bits are used to indicate what type of chaining if any is used 00 Chain operation is disabled 01 undefined reserved National Instruments Corporation 4 53 GPIB 1014 User Manual Register Descriptions Chapter 4 10 Array Chaining 11 Linked Chaining Bit Mnemonic Description In most GPIB applications either no chaining or array chaining is used See Chapter 5 for details 1 0r w REQG DMA Request Generation Bits 1 through 0 The DMA Request Generation method bits define how requests for transfers are generated For the GPIB to memory DMA transfers the request mode is always 10 the REQ line initiates an operand transfer For memory to memory transfers automatic request mode must be used 00 Automatic request at a rate limited by the General Control Register GCR 01 Automatic request at maximum rate 10 REQ lin
86. GNS Notes TACS GPIB Talker Active State SGNS GPIB Source Generate State read ISR1 Bit is cleared immediately after it is read The DO bit indicates that the TLC is ready to accept another data byte from the VMEbus for transmission on to the GPIB when the TLC is the GPIB Talker The DO bit is cleared when a byte is written to the CDOR and also when the TLC ceases to be the Active Talker When performing a DMA operation DO IE must be clear so that an interrupt request does not occur Instead the DMAO bit in the Interrupt Mask Register 2 IMR2 5 w must be set to enable a DMA cycle request when DO is asserted Data In Bit Data In Interrupt Enable Bit Bit DI is set by LACS amp ACDS amp continuous mode DI is cleared by pon read ISR1 Finish Handshake amp Holdoff mode read DIR National Instruments Corporation 4 13 GPIB 1014 User Manual Register Bit Descriptions Bit Mnemonic GPIB 1014 User Manual Description Notes LACS ACDS continuous mode pon read ISR1 finish Handshake Holdoff mode read DIR Chapter 4 GPIB Listener Active State GPIB Accept Data State Listen in continuous mode auxiliary command in effect Power On Reset Bit is cleared immediately after it is read Finish Handshake auxiliary command issued RFD Holdoff state Read Data In Register The DI bit indicates that the TLC as a GPIB Listener has accepted a data byte from the GPIB Talker When performing
87. GPIB 1014 User Manual March 1997 Edition Part Number 3 70945A 01 Copyright 1985 1997 National Instruments Corporation All Rights Reserved National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin TX 78730 5039 512 794 0100 Technical support phone 512 795 8248 Technical support fax 512 794 5678 Branch Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 5734815 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico5 520 2635 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 20 51 51 Taiwan 02 377 1200 U K 01635 523545 Limited Warranty The GPIB 1014 is warranted against defects in materials and workmanship for a period of two years from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other
88. Group SCG messages following an undefined GPIB PCG message are also treated as undefined When an undefined GPIB message is encountered it is held in the CPTR and the TLC Acceptor Handshake function is held off in ACDS until the Valid auxiliary command is written to the AUXMR The CPTR is also used to inspect secondary addresses when mode 3 addressing is used The TLC Acceptor Handshake function is held off in ACDS until the Valid or Non Valid auxiliary command is written to the AUXMR Table 4 3 Multiline GPIB Commands Recognized by the uPD7210 nee I TCT Take Control 11 LLO Local Lockout 14 DCL Device Clear continues Register Bit Descriptions GPIB 1014 User Manual Chapter 4 Table 4 3 Multiline GPIB Commands Recognized by the uPD7210 continued MSA PPE My Secondary Address or Parallel Poll Enable MSA PPD My Secondary Address or Parallel Poll Disable The CPTR is read during a TLC initiated Parallel Poll operation to retrieve the Parallel Poll response The PPR message is latched into the CPTR when CPPS is set until CIDS is set or until a command byte is sent over the GPIB 4 26 National Instruments Corporation Auxiliary Mode Register AUXMR VMEbus Address Attributes Base Address 11B hex Write Only Internal to TLC Permits Access to Hidden Registers 7 6 5 4 3 2 1 0 CNT2 CNTI CNTO COM4 COM3 COM2 COM1 COMO W The Auxiliary Mode Register AUXMR is used to issue auxiliary
89. H74F241H W74F1241N DM74A5573 AM25LS2521PC SN74LSOSN DS75160AN DS75162AN T4ASTSEN B 5 PRODUCT DESCRIPTION CAP 047UF 50V 80 20 CER AX CAP 047UF 50V 80 20X CER AX CAP 047UF 50V 80 20 CER AX CAP 47UF 10V 20 TANT AXL CAP 47UF 10V 20 TANT AXL CAP 047UF 50V 80 20 CER AX DIODE 1N4148 SWITCHING DIODE 184148 SWITCHING LED RED GRN RTANG PWB MOUNT CONN DIN 3X32POS RTANG CLASS11 CONN DIN 3X32POS RTANG CLASSI I RES 150 1 4W 5 CF RES 150 1 44 5X CF RES 1K 1 49 5X CF RES 1k 1 49 5X CF RES 5 3K 1 44 5 CF RES 1K 1 49 5X CF IC F241 0CTAL BUFFER 3 STATE IC F1241 0CTAL BUFFER 3STATE 1C ASS7S 0CTAL D LATCHES 3STAT IC LS2521 8 BIT EQUAL TO CMPTR IC LS08 2 1NP AND IC 75160 GPIB DATA BUS XCVR 1C 75162 GPIB CNTRL BUS XCVR IC AS756 0CTAL DRVR OC OUTPUT GPIB 1014 User Manual 74 76 8 3 A R S Parts List and Schematic Diagrams Appendix B FATTA RIE EAI RRERREEEREEARRRIEE ER HER II II ICI REI TAI eee erede ACI ICI ATTIC RI einn ITEM NO NI PART NO QTY REQD UO9 700176 01 1 0000 U10 700562 01 1 0000 Ul 700176 01 1 0000 U12 700002 01 1 0000 U13 700236 01 1 0000 U14 700739 01 1 0000 UIS 700029 01 1 0000 uit 700540 01 1 0000 U17 700200 01 1 0000 UiB 700562 01 1 0000 UI9 700173 01 1 0000 U20 700237 01 4 0000 U21 700011 01 1 0000 u22 700011 01 1 0000 u23 700008 01 1 0000 u24 700562 01 1 0000 u25 700
90. I and IMR2 are Interrupt Mask Registers for enabling and disabling the interrupt from the TLC on the occurrence of 13 key GPIB conditions or events The status of these conditions can be read from the ISR1 and ISR2 The status bits in these registers function independently of the corresponding mask bits that is they are set and cleared regardless of whether an interrupt GPIB 1014 User Manual 6 26 National Instruments Corporation Chapter 6 Theory of Operation request is enabled for the condition An important fact to remember is that ISR1 and ISR2 are always cleared when read even if the condition that caused the bit to be initially set remains true Data to and from the GPIB is pipelined through the CDOR and DIR respectively An 8 MHz clock is used as the CLOCK input to the TLC For proper GPIB timing the internal counter must be programmed to eight The TLC RESET pin is driven by the GPIB 1014 RESET signal Connecting the TLC to the GPIB itself are two multi function transceivers one handling the data lines a 75160A and the other handling the handshake and management lines a 75162A The 75160A and 75162A transceivers are specifically designed to meet the IEEE 488 driver and receiver specifications In particular they do not affect bus operations when the GPIB 1014 power is removed or during power up or down transitions The TLC controls the direction of the 16 GPIB signals depending on whether the chip is functioning as a GPIB Talke
91. IB 1014 User Manual Register Descriptions Chapter 4 Bit Mnemonic Description 1 Ow HLDE Holdoff on End Bit HLDA Holdoff on All Bit HLDE and HLDA together determine the GPIB data receiving mode The four possible modes are as follows HLDE HLDA Data Receiving Mode 0 0 Normal Handshake 0 1 RFD Holdoff on All Data 1 0 RFD Holdoff on END 1 1 Continuous In Normal Handshake mode the local message rdy is generated when data is received from the GPIB When the received data is read from the DIR rdy is generated in Acceptor Not Ready State ANRS the RFD message is transmitted and the GPIB Handshake continues In RFD Holdoff on All Data HLDA mode RFD is not sent true after data is received until the Finish Handshake FH auxiliary command is issued Unlike Normal Handshake mode the RFD HLDA mode does not generate the rdy message even if the received data is read through the DIR that is the GPIB RFD message is not generated In RFD Holdoff on End mode operation is the same as the RFD HLDA mode but only when the end of the data block EOS or END message is detected that is the END message is received or if REOS is set the EOS character is received Handshake Holdoff is released by the FH auxiliary command In continuous mode the rdy message is generated when in ANRS until the end of the data block is detected A Holdoff is generated at the end of a data block The FH auxiliary command must be issued to release the Hold
92. IB 1014 hardware provides automatic GPIB synchronization after the data transfer is complete This allows an interrupt or a set status bit for polling when the last data byte has been transferred and the GPIB is synchronized that is all devices on the GPIB have accepted the last byte When the DMA transfer is complete and the GPIB is synchronized a negative transition is generated on the PCL of Channel 1 Because the PCL detects a high to low transition on its input the input once pulled low to generate an interrupt must be pulled back to high by your program for the PCL to work properly on the next transition For example if the interrupt of the TLC pulls PCL1 low your program must read ISRI or ISR2 of the TLC to clear the interrupt and pull PCL1 high If GPIB synchronization occurs you must write any value to CFGI to pull PCL1 high If a VMEbus error occurs during a DMA transfer the PCL is pulled high automatically when the VMEbus memory releases signal BERR high Your program cannot pull PCL high in the last case but can only clear the PCT bit in the CSR Interrupts from the PCL of DMA Channel 1 are enabled by setting the EINT bit in the CCR of Channel 1 An interrupt is generally not enabled on Channel 0 If triggered all three interrupt events mentioned earlier will cause the set PCT bit to indicate a PCL transition and an interrupt A bus error that occurs when Channel 1 is active sets both the ERR and PCT bits in the CSR of Channel 1
93. K k ok KKK Summary nitialize the interface function of other GPIB devices Assumptions on entry GPIB 1014 has been initialized GPIB 1014 is System Controller SC is true Actions Assert GPIB IFC Wait at least 100 microseconds Unassert IFC Status on return GPIB 1014 is Active Controller Interface functions of other GPIB devices are reset to their idle states Comments ie et the IFC signal Wait at least 100 microseconds Clear IFC C 7 GPIB 1014 User Manual Sample Programs 68000 Code REN tstb sre beq RENI movb SREN AUXMR bra REN2 REN1 movb CREN AUXMR REN2 rts GPIB 1014 User Manual Appendix C oko RE E ck ck ck ck ko ko Ck ko ko k KK k kk REMOTE ENABLE REN ok RK ck ck ck ck ko ko ko ko ko KK KK kk Summary Set or clear GPIB Remote Enable signal Assumptions on entry User specified sre is non zero if REN is to be asserted and is zero if REN is to be unasserted GPIB 1014 is System Controller and Active Controller Actions Check sre flag if non zero true send REN else send clear REN Status on return REN is asserted or unasserted Comments Turn on the REN signal if sre is non zero Else turn off REN if sre is zero C 6 National Instruments Corporation Appendix C National Instruments Corporation Sample Programs okok KKK k k k k
94. LC except when the carry cycle byte is written to the Auxiliary Register by the DMAC Instead the chip is enabled and selected by the DMAACK DMA Acknowledge signal and the TLC internal registers CDOR and DIR are automatically accessed Data is strobed into the CDOR at the rising edge of the TLC WR signal If RD is asserted data from the DIR is placed on the internal 3 state data bus a minimum access time after DMAACK is asserted low Most of the TLC GPIB interface functions can be implemented or activated from either side that is the TLC can be programmed to do these functions by the VMEbus master or it can be addressed to do them by the GPIB Controller In terms of the IEEE 488 standard the distinction between these two modes of operation is generally the same as that between local and remote interface messages respectively as defined in the standard The ADSR is the primary register for monitoring the current status of the TLC that is to determine if it is a GPIB Talker GPIB Listener GPIB Active Controller or in GPIB remote or local mode The CPTR provides a means to read the GPIB data bus directly and is used to recognize interface messages that are not automatically decoded and implemented by the TLC The ADR is used to program the primary and secondary GPIB addresses of the TLC and is also used to disable talking or listening and to enable dual primary addressing The SPMR is used to program the serial poll status byte IMR
95. Manual 6 12 National Instruments Corporation Chapter 6 Theory of Operation 4 The outputs of the 748139 are connected to four 74L S02 gates along with the LBROUT signal to assert one of the four VMEbus bus request lines BR3 through BRO 5 The DTB Requester waits for the appropriate Bus Grant In line BG3IN through BGOIN to become active at which time BGIN becomes high 6 The 748139 outputs are used to direct the others to the corresponding Bus Grant Out line BG30UT through BGOOUT If BGIN is high and the DMAC has no bus request pending BGMATCH is not asserted BUS REL is asserted to prevent flip flop Q2 to change state and the appropriate Bus Grant Out line is driven low This line is released when the Bus Grant In line is released If however the DMAC has a bus request pending flip flop Q2 changes state and BG is asserted to inform the DMAC that it has been granted the bus BGMATCH is also asserted to maintain the BGXOUT high As soon as the VMEbus signal BBSY is detected high the DMAC asserts its signal OWN to start the DMA cycle BBSY and OWNBUS are both asserted Notice that BGIN is delayed 25 nsec by a digital delay line before its output is used to create onboard signals BGMATCH and BG This delay prevents fluctuation on Q2 output from momentarily asserting BGMATCH or BG When the DMAC finishes the DMA transfer and wishes to relinquish the bus it first unasserts its OWN signal at this time both
96. PIB Talker Active State TACS It is also necessary to execute the Chip Reset or Immediate Execute pon auxiliary command 6w lon Listen Only Bit By setting lon programs the TLC becomes a GPIB Listener If lon is set ton ADMI and ADMO must be cleared Note Clearing lon does not by itself take the TLC out of GPIB Listener Active State LACS It is also necessary to execute the Chip Reset or Immediate Execute pon auxiliary command 5 4w TRMI 1 0 Transmit Receive Mode Bits 1 through 0 TRMI and TRMO control the function of the TLC T R2 and T R3 output pins For proper operation set both TRM1 and TRMO to 1 These are set to configure the uPD7210 to match the transceivers chosen for hardware implementation of the GPIB interface 3 2w 0 Reserved Bits Write zeros to these bits GPIB 1014 User Manual 4 22 National Instruments Corporation Bit 1 Ow Mnemonic ADM 1 0 Description Address Mode Bits 1 through 0 These bits state the addressing mode currently in effect that is the manner in which the information in ADRO and ADRI is interpreted see Address Register 0 and Address Register 1 later in this chapter If both bits are zero then the TLC does not respond to GPIB address commands Instead the ton and lon bits are used to program the Talker and Listener functions respectively The ton and lon bits must be cleared if mode 1 2 or 3 addressing is selected and the ADMI through 0 bits must be cleared if eithe
97. PIB command messages After the TLC has become the GPIB Active Controller it must complete the following procedures to pass control 1 Write the GPIB Talk address of the device being passed control to the CDOR 2 In response to the next CO status write the GPIB TCT message to the CDOR 3 As soon as the TCT command message is accepted by all devices on the GPIB the TLC automatically unasserts ATN and the new Controller asserts ATN National Instruments Corporation 5 5 GPIB 1014 User Manual Programming Considerations Chapter 5 The GPIB 1014 as GPIB Talker and Listener The TLC may be either GPIB Talker or Listener but not both simultaneously Either function is deactivated automatically if the other is activated The TA LA and ATN bits in the ADSR together indicate the specific state of the TLC ATN TA LA 0 1 0 Addressed Talker cannot send data 1 1 0 Active Talker can send data 0 0 1 Addressed Listener cannot receive data 1 0 1 Active Listener can receive data The Address Status Change ADSC Command Output CO Address Pass Through APT Data Out DO and Data In DI status bits are used to prompt the program possibly with an interrupt request when a change of state occurs The following sections discuss several aspects of data transfers Programmed Implementation of Talker and Listener When there is no Controller in the GPIB system the ton and lon address modes refer to the description of the ADMR are use
98. RO 00003000 MTCO 0002 MFCI 06 BFC1 06 BARI 00003004 BTC1 0002 CSRO FF CSR1 FF AUXMR 2 ADMR CO IMR2 20 CCRI 80 CCRO 80 AUXMR 0 ISR1 1 CDOR 1 ISR1 1 DIR 2 CSRO 81 MTCI 0001 ISR1 13 DIR 3 CSRI 0A CCRI 10 CSRI FF Diagnostic and Troubleshooting Test Procedures 4 byte address 00003000 of the first two data bytes 2 byte transfer count 0002 4 byte address 00003004 of the carry cycle array carry cycle array has two entries two small memory blocks to be transferred TLC Reset ton lon DMA out enable start channel 1 start channel 0 Immediate execute pon TLC immediately sets DO in ISRI requests a DMA transfer for a byte from memory DO is cleared here because a byte has been transferred from memory to TLC s CDOR TLC does not currently request for DMA transfer check the first data byte that was transferred from memory to TLC after this read the TLC will request for another DMA transfer DO is cleared here because a byte has been transferred from memory to TLC s CDOR second data byte that was transferred from memory to TLC after this read the TLC will request for another DMA transfer channel 0 finished COC last data byte transferred will make count 1 END DO and DI carry cycle byte will set END bit last data byte GPIB synchronized software abort clear status bits 14 Test DMA transfer flyby from GPIB to memory one byte
99. RTER 143 u56 700004 01 1 0060 TI SN74LSO8N 1C LS08 2 INP AND 144 u58 700545 01 1 0000 TI SN74F240N IC F240 0CT INVERTER SUFFER 145 u59 700004 01 1 0000 Ti SN74LS08N IC LS08 2 1HP AND 146 U60 700013 01 1 0000 TI SN74LS74AN IC LS74 FLIP FLOP 147 National Instruments Corporation B 7 GPIB 1014 User Manual Parts List and Schematic Diagrams l Appendix B ER EEA E E k ESE AEEA AE FE E AE AE A ede SESE e k E A EE AE BE AAE AEE E e A e OO AE e De EAE AE E RE AE E cR e Se AE dn eei RR EER A ITEM NO NI PART NO QTY REOD MFR MFR PART PRODUCT DESCRIPTION u61 700001 01 1 0000 TI SN74LSOON IC LS00 2 INP NAND i 148 u62 700008 01 1 0000 TI SN76LS20N IC LS20 4 INP_NAND 149 u63 700013 01 1 0000 TI SN74LS74AN IC LS74 FLIP FLOP 150 PA 700309 01 1 0000 KITA HD68450 8 1C 68450 8 DMA CHTRLR 151 u65 700013 01 1 0000 TI SN74LS740N IC LS74 FLIP FLOP 152 u66 700418 01 1 0000 TI SN74F32N IC F32 QUAD 2 INPUT OR 153 u67 700418 01 1 0000 HH SN74F32N IC F32 QUAD 2 INPUT OR 154 u68 700706 01 1 0000 TI SN74F74N IC 74 FLIP FLOP 155 w9 700431 01 1 0000 TI SN74FOBN IC F08 QUAD 2INPUT AND 156 u70 700743 01 1 0000 NSC DM74AS573 IC AS573 0CTAL D LATCHES 3STAT 157 471 700739 01 1 6000 TE SNTAF241N IC F241 0CTAL BUFFER 3 STATE 158 u72 700431 01 1 0000 TI SN74FO8N IC F08 QUAD 2INPUT AND 159 U73 700025 01 1 0000 Ti SN74S74N IC S74 FLIP FLOP 160 U74 700986 01 1 0000 TI SHN74F02N IC F02 QUAD 2 INPUT NOR GATE 161 u75 701028 01 1 0000 DAL SEMI DS1013M 40 1
100. Reset auxiliary command 4 20 National Instruments Corporation Bit 3r 2r lr Or Mnemonic TPAS LA TA MJMN Description Talker Primary Addressed State Bit TPAS is used when the TLC is configured for extended GPIB addressing and when set indicates that the TLC has received its primary GPIB talk address In extended mode addressing mode 3 addressing TPAS 1 indicates that the secondary address being received as the next GPIB command message can represent the TLC extended secondary GPIB talk address Listener Active Bit LA is set when the TLC has been addressed or programmed as a GPIB Listener that is the TLC is in the Listener Active State LACS or the Listener Addressed State LADS The TLC can be addressed to listen either by sending its own listen or extended listen address while it is Controller In Charge or by receiving its listen address from another Controller In Charge It can also be programmed to listen using the Listen Only lon bit in the Address Mode Register ADMR If the TLC is addressed to listen it is automatically unaddressed to talk LA is cleared by pon or by issuing the Chip Reset auxiliary command Talker Active Bit TA is set when the TLC has been addressed or programmed as the GPIB Talker that is the TLC is in the Talker Active State TACS the Talker Addressed State TADS or the Serial Poll Active State SPAS The TLC can be addressed to talk either by sending its o
101. SA105E4732AA CAP O47UF SOV 80 20 CER AX 49 c45 715079 01 1 0000 AVX SA105E473ZAA CAP 047UF 50V 80 20 CER AX 50 C46 715079 01 1 0000 AVX SA105E4722AA CAP 047UF 50V 80 20 CER AX 51 C47 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 52 c48 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 53 C49 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 480 20 CER AX 54 c50 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 55 c51 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 56 c52 715079 01 4 0000 AVX SA105E4732ZAA CAP 047UF 50V 80 20 CER AX 57 C55 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 58 054 715079 01 1 0000 AVX SA105EA73ZAA CAP 047UF SOV 80 20 CER AX 59 c55 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 60 c56 715079 01 1 0000 AVX SA105E473ZAA CAP 047UF 50V 80 20 CER AX 61 c57 715079 01 1 0000 AVX SATOSE473ZAA CAP O47UF 50V 80 20 CER AX 62 c58 715079 01 1 0000 AVX SA105EA732AA CAP 047UF 50V 80 202 CER AX 63 c59 715079 01 1 0000 AVX SA105E473ZAA CAP 047UF 50V 80 20 CER AX C60 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 65 c61 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 66 c62 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 67 c63 715079 01 1 0000 AVX SA105E4732AA CAP BA7UF 50V 80 20 CER AX
102. Seven of the 74145 outputs are connected directly to the seven VMEbus interrupt request lines IRQ1 through IRQ7 When the DMAC drives its IREQ pin low the VMEbus interrupt request line corresponding to the interrupt priority code in CFGI is driven low When the GPIB 1014 detects an interrupt acknowledge cycle AS DS and IACK all low the 74F85 compares VMEbus address lines A3 through A1 against the 3 bit interrupt priority code in CFG1 If IACKIN is asserted and the indicated priority does not match the GPIB 1014 priority the daisy chain signal IACKOUT is asserted This signal remains asserted until AS is released However if the priority indicated matches the GPIB 1014 priority the IACK pin of the DMAC is driven low The DMAC then finishes the acknowledge cycle by placing the contents of Channel 1 NIVR EIVR if a DMA error was encountered on VMEbus data lines D07 through D00 and driving the DTACK line An F74 flip flop keeps the IACK line of the DMAC continuously asserted until the interrupt handler releases DS When IACK is released the DMAC then releases the data transceiver and DTACK Notice the use of a 2 tap digital delay line in the circuitry The first delay is used to give the flip flop enough data to clock setup time and the second is used to prevent fluctuation in the flip flop output from momentarily asserting signals DIACK or IACKOUT DTB Requester and Controller The DTB Requester and Controller circuitry is des
103. X e GPIB Handshake Error ERR Command Pass Through CPT e Lockout Change LOKC e Bus Error BERR e GPIB DMA Transfer Finished and GPIB Synchronized FIN You can select one of seven VMEbus interrupt request lines IRQ1 through IRQ7 through software using three bits located in Configuration Register 1 The onboard hardware implements the VMEbus interrupt acknowledge protocol Interrupt Vector Registers located in the 68450 let you select through software the 8 bit Interrupt Status ID byte supplied by the GPIB 1014 during an interrupt acknowledge cycle of the correct priority The GPIB 1014 is a D08 O interrupter because it responds to an interrupt acknowledge cycle by providing an 8 bit status ID byte on data lines DOO through D07 In addition the board is a Release On Register Access RORA interrupter because it releases its interrupt line when the Channel Status Register is written with the proper value In VMEbus terminology the GPIB 1014 has D08 O RORA Interrupter capability GPIB 1014 User Manual 2 6 National Instruments Corporation Chapter 2 General Description Data Transfer Bus DTB Requester The GPIB 1014 arbitrates for the DTB before each DMA transfer The board is designed for you to select through software one of four VMEbus request lines BRO through BR3 using two bits in Configuration Register 1 To maximize the capabilities of the DTB the board can be programmed to become a Release On Request ROR
104. XRA is set the END message GPIB EOI line asserted low is sent along with the data byte whenever the contents of the CDOR match the EOSR Bit Mnemonic Description 7 0w EOS T7 0 End of String Bits 7 through 0 National Instruments Corporation 4 45 GPIB 1014 User Manual Register Descriptions Chapter 4 DMA Registers The onboard DMA Controller is a 68450 DMAC This chip is extremely flexible and uses four independent DMA channels The DMAC can support single address flyby transfers or dual address flowthrough transfers The GPIB 1014 uses two channels Channel 0 and 1 for 8 bit flyby DMA transfers between VMEbus memory and the GPIB All four channels are available for 8 or 16 bit flowthrough memory to memory DMA transfers The DMAC supports unchained continue array chained or link chained operations between memory and memory or between memory and device GPIB The TLC to DMAC interface includes lines for requesting acknowledging and providing incidental control of the TLC The DMAC contains a large number of internal configuration and status registers These registers define and control the activity of the DMAC in processing a channel operation The registers are addressed relative to the base address of the board Locations not used in the board address space are reserved The registers set associated with each DMA channel is shown in Table 4 7 Table 4 7 DMAC DMA Channel Register Set Memory Address Register Memory Tra
105. a DMA operation DI IE must be clear so that an interrupt request does not occur Instead the DMAI bit in the Interrupt Mask Register 2 IMR1 4 w must be set to enable a DMA cycle request when DI is asserted 4 14 National Instruments Corporation Register Bit Descriptions Chapter 4 Interrupt Status Register 2 ISR2 VMEbus Address Base Address 115 hex Attributes Read Only Internal to TLC Bits are cleared when read Interrupt Mask Register 2 IMR2 VMEbus Address Base Address 115 hex Attributes Write Only Internal to TLC 7 6 5 4 3 2 1 0 R 0 skom DMAO DMAT COIE LOKC IE REMC IE ADSCIE W The Interrupt Status Register 2 ISR2 consists of six Interrupt Status bits and two TLC Internal Status bits The Interrupt Mask Register 2 IMR2 consists of five Interrupt Enable bits and two TLC Internal Control bits If the Interrupt Enable bit is true when the corresponding status condition or event occurs an interrupt request is generated Bits in ISR2 are set and cleared regardless of the status of the bits in IMR2 If a condition occurs that requires the TLC to set or clear a bit or bits in ISR2 at the same time ISR2 is being read the TLC holds off setting or clearing the bit or bits until the read is finished Bit Mnemonic Description Tr INT Interrupt Bit This bit is the logical OR of all the Enabled Interrupt Status bits in both ISRI and ISR2 each one ANDed with its Interrupt Enable bit There is no
106. able interrupts Load the NIVR and EIVR of Channel 1 with the proper status ID byte to return to the VMEbus interrupt handler b If VMEbus interrupts are not used complete the following event e Set the PCL bits in the DCR of Channel 1 to binary 00 for status input You can check the PCT and PCS bits in the CSR of Channel 1 to see if the TLC has requested an interrupt BERR has occurred or if GPIB synchronization has occurred It is not necessary to configure any other Channel 1 registers 4 Once Channels 0 and 1 have been configured the DMAC must be started by setting the STR bit in the CCR of Channel 0 Channel 1 is not used 5 Finally configure the TLC for DMA operation by completing the following steps a Set the END IE bit in IMRI if the TLC is a GPIB Listener Set the ERR IE bit in IMRI if the TLC is a GPIB Talker In all cases clear all other IE bits b Setthe DMAO bit in IMR2 if the TLC is a GPIB Talker Otherwise clear DMAO c Setthe DMAI bit in IMR2 if the TLC is a GPIB Listener Otherwise clear DMAI GPIB 1014 User Manual 5 12 National Instruments Corporation Chapter 5 Programming Considerations DMA Transfers with the Carry Cycle Data Block A VMEbus Block A interrupt carry cycle byte i yte 4 TLC interrupt Bus Error Count 1 GPIB Sync Block B Data last data Block C byte Count 2 Total N 1 bytes Total N 1 bytes Carry Cycle byte Nth data byte NO CHAINING CHAINING CHAINING arra
107. above must be explicitly handled in the software by writing the appropriate values to the U S and P3 to PI bits of the PPR Refer to the PPR description in Chapter 4 for more information Once the PPR is configured all that remains for your program is to determine the source and value of the local individual status ist message If the ISS bit in the AUXRB is 0 ist is set and cleared via the Set and Clear Parallel Poll auxiliary commands If ISS is 1 ist is set if the Service Request function of the TLC is in the Service Request State SRQS and the TLC is asserting the GPIB SRQ signal line and cleared otherwise Consequently setting ISS ties the Parallel Poll function to the Service Request function and also to the Serial Poll process As explained under the Conducting a Serial Poll section earlier in this chapter which of the 16 possible responses that is transmitted by the TLC during a Parallel Poll is a function of the value of ist and the configuration of the TLC The GPIB system integrator must decide what ist indicates and what configuration is used The response can be changed dynamically during program execution by changing the value of ist and when remote configuration is used by reconfiguration National Instruments Corporation 5 25 GPIB 1014 User Manual Chapter 6 Theory of Operation This chapter contains a functional overview of the GPIB 1014 board and explains the operation of each functional block making up the GPIB 1014
108. accepted the last byte or A DMA transfer from the GPIB to memory is complete and the GPIB is synchronized All interrupt sources from the GPIB 1014 are routed to the onboard DMAC which actually generates the interrupt request on the VMEbus The Peripheral Control Line PCL1 of Channel 1 is used as a status input for the interrupt sources listed earlier These events are ORed together so that a transition on the PCL1 occurs when any of these events occur If programmed as a status input the status level of the PCL can be determined by reading the PCS bit in the CSR If a negative transition occurs on this input the PCT bit of the CSR is automatically set Any of the four DMAC channels can be programmed to generate an interrupt on a negative transition high to low on its PCL This enables an interrupt which is requested when the PCT bit of the CSR is set indicating that a transition has occurred National Instruments Corporation 5 21 GPIB 1014 User Manual Programming Considerations Chapter 5 The TLC contains its own internal registers which are used to control and enable interrupts The interrupt output from the TLC however is sensed by the PCL of DMA Channel 1 If an interrupt operation is used the DMAC Channel 1 must be configured to interrupt on a high to low transition of the PCL 1 If the DMAC encounters a bus error during operation a negative transition is caused on the PCL of Channel 1 thus causing an interrupt The GP
109. an reload the BFCR BAR and BTCR with information describing the next data block if necessary clear the BTC bit and set the CNT to repeat the operation In all cases if the MTCR is loaded with a terminal count the count error is signaled The GPIB 1014 usually does not use continue operations for its GPIB DMA transfers Array Chaining Operations Chaining is not necessary when transferring a single small block of data When data to be transferred is fragmented or is larger than 64K array chaining is used to transfer these blocks of data This type of chaining uses an array in memory that holds the addresses and transfer counts of the data blocks The address amp transfer count array must occupy continuous memory locations Each entry in the array is six bytes long four bytes to hold the starting address of a data block and two bytes to hold the length of the data blocks The beginning address of this array is in the Base Address Register BAR and the number of entries in the array is in the Base Transfer Counter BTCR that is the BAR points to the address amp transfer count array Before starting any block transfers the DMAC fetches the entry a total of six bytes in three DMA cycles currently pointed to by the BAR The address information is placed in the MAR and the count information is placed in the MTCR After each chaining entry is fetched the BTCR is decremented by one and the BAR is incremented by six to point to the next entry W
110. and control interrupts routed to the PCL input line of DMAC Channel 1 Using the GPIB synchronization circuitry the GPIB 1014 can detect when the last byte of data in a data transfer has been accepted by all devices on the GPIB In this manner the host CPU can be notified that the DMA transfer is complete and does not have to timeout to ensure that the GPIB is synchronized The interrupt control circuitry consists of three inputs from the NOR gate and several other miscellaneous gates The output of the NOR gate is tied to the PCL input line of Channel 1 National Instruments Corporation 6 13 GPIB 1014 User Manual Theory of Operation Chapter 6 This PCL is used to detect interrupts from the GPIB 1014 that are not internal to the DMAC A negative transition on the PCL sets the PCT bit in the CSR of DMAC Channel 1 If interrupts are enabled in the CCR of Channel 1 EINT 1 the setting of the PCT bit causes the DMAC to drive its IREQ line requesting an interrupt The three inputs of the NOR gate enable the negative transition to occur if the TLC requests an interrupt if a bus error occurs while the DMAC is the bus master or when the GPIB becomes synchronized after the last DMA transfer has finished The INT pin of the TLC is connected to one of the inputs of the NOR gate Each of the TLC interrupt request events or conditions are controlled by mask bits located within the TLC Each of the 13 events is individually enabled by bits in the mask
111. and the chain is exhausted last block in the chain has been transferred When the last transfer of the last data block has been completed the ACT bit of the CSR is cleared and the COC bit is set indicating the channel operation is complete A bus exception during a bus cycle being run for a channel or an error in the channel terminates the block transfer and the channel operation The bit of the CER corresponding to the error is set The ACT of the CSR is cleared and the COC and ERR bits are set Multiple Block Operations When the MTCR is exhausted there are additional blocks to be transferred if the channel is chained and the chain is not exhausted The DMAC provides the re initialization of the MAR and the MTCR Continued Operations When the MTCR is exhausted and the continue bit of the CCR is set the DMAC performs a continuation of the channel operation 1 First the Base Address Register the Base Function Code Register and the Base Transfer Count Registers are automatically copied into the Memory Address Registers the Function Code Registers and Memory Transfer Count Registers 2 The Block Transfer Complete BTC bit of the CSR is set 3 The Continue bit is cleared 4 The channel begins a new block transfer National Instruments Corporation 6 21 GPIB 1014 User Manual Theory of Operation Chapter 6 If the interrupt bit in the CCR is set when the BTC bit is set an interrupt is generated The interrupt handler c
112. ansfer the last data byte indicated by ACK1 asserted make signal ALLDONE high After this last data transfer DMAREQ from TLC is masked see DMA Gating and Control earlier in this chapter and Channel 1 is still active see Chapter 5 Programming Considerations thus Channel 1 cannot reach its terminal count In both cases the positive transition 0 to 1 in ALLDONE causes the GPIB synchronization circuitry to begin monitoring the GPIB DAV line The GPIB synchronization is detected differently depending upon the direction of the DMA transfer The direction of the transfer is specified in the DIR bit in CFGI If the transfer is from the VMEbus memory to the GPIB DIR 0 the ALLDONE signal indicates that the last byte has just been transferred to the TLC The DAV line at this time is high The TLC drives DAV low as it places the data on the GPIB As soon as all Listeners have accepted the byte the TLC releases DAV to high again It is this positive transition of the DAV line that is of interest A D type flip flop with the DAV line as the clock input is set by the DAV low to high transition This generates a negative transition on the PCL of DMAC Channel 1 If the direction of the DMA transfer is from the GPIB to the VMEbus system memory DIR 1 the GPIB synchronization is detected by watching the level of the DAV line rather than looking for a transition The ALLDONE signal indicates that the last byte in the DMA transfer has just be
113. ard 1014 1987 EEE Standard for a Versatile Backplane Bus VMEbus uPD7210 GPIB IFC User Manual NEC Electronics U S A Inc One Natick Executive Park Natick MA 01760 uPD7210 Intelligent GPIB Interface Controller Engineering Data Sheet NEC Electronics U S A Inc Microcomputer Division How to Interface a Microcomputer System to a GPIB amp The NEC uPD7210 TLC NEC Electronics U S A Inc GPIB 1014 User Manual xiv National Instruments Corporation About This Manual e Motorola Semiconductor Technical Data MC68450 Advance Information Direct Memory Access Controller DMAC Hitachi Microcomputer System HD68450 DMAC Direct Memory Access Controller Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix G Customer Communication at the end of this manual National Instruments Corporation Xv GPIB 1014 User Manual Chapter 1 Introduction This chapter describes the GPIB 1014 lists the contents and oiptional equipment for your GPIB 1014 kit and explains how to unpack the GPIB 1014 kit The GPIB 1014 is a high performance IEEE 488 interface for the VMEbus This interface permits IEEE 488 compatible engineerin
114. ata is separately latched by this register and is not destroyed by a read from the DIR When a byte is written to the CDOR the TLC GPIB Source Handshake SH function is initiated and the byte is transferred to the GPIB Bit Mnemonic Description 7 Ow CDO 7 0 Command Data Out Bits 7 through 0 GPIB 1014 User Manual 4 6 National Instruments Corporation Chapter 4 Register Bit Descriptions Interrupt Status Register 1 ISR1 VMEbus Address Base Address 113 hex Attributes Read Only Internal to TLC Bits are cleared when read Interrupt Mask Register 1 IMR1 VMEbus Address Base Address 113 hex Attributes Write Only Internal to TLC 7 6 5 4 3 2 1 0 R cr ar Der ENDRX DEC ERR o m W The Interrupt Status Register 1 ISR1 is composed of eight Interrupt Status bits The Interrupt Mask Register 1 IMR1 is composed of eight Interrupt Enable bits that directly correspond to the Interrupt Status bits in ISRI Asa result ISR1 and IMRI service eight possible interrupt conditions where each condition has an Interrupt Status bit and an Interrupt Enable bit associated with it If the Interrupt Enable bit is true when the corresponding status condition or event occurs a hardware interrupt request is generated Bits in ISR1 are set and cleared by the TLC regardless of the status of the Interrupt bits in IMRI If an interrupt condition occurs at the same time ISRI is being read the TLC holds off setting the correspon
115. atus Byte Source Transfer State Start Cycle Signal Source Wait for New Cycle State F 9 GPIB 1014 User Manual Mnemonics Key SYSCLK SYSFAIL SYSRESET T T TA TACS TADS TAG tca tcs tcse TCT TDMA TIDS TLC TLC CS TLC WR ton ton TPAS TPAS TPIS TRI TRIG TRM 1 0 VBS VBS VBS GPIB 1014 User Manual Appendix F System Clock System Fail System Reset Talker Talker Active Bit Talker Active State T function Talker Addressed State Talk Address Group Take Control Asynchronously Take Control Synchronously Take Control Synchronously on End Take Control Terminate DMA Extended Talk Talker Idle State Talker Listener Controller GPIB Adapter TLC Chip Reset TLC Write Talker Only Bit Talker Only Talker Primary Addressed State Bit Talker Primary Addressed State Talker Primary Idle State Three State Timing Bit Trigger Transmit Receive Mode Bits 1 through 0 F 10 National Instruments Corporation Appendix F U U UAT UCG UDPCF UNL UNT VIO 7 WR WRITE XEOS National Instruments Corporation LS LS VBS Mnemonics Key Unconfigure Bit Unaligned Transfer Universal Command Group Undefined Primary Command Function Unlisten command Untalk command Interrupt Vector Bits TLC Write Signal Read Write Line Transmit End with End Of String Bit F II GPIB 1014 User Manual Appendix G Customer Communication For your convenience this appen
116. ay in memory The array must begin at an even address and all addresses in the array must be even The contents of the array are as follows First four bytes physical address of carry cycle byte Next two bytes 0001 hex Next four bytes physical address of last data byte in the data buffer to be transferred Last two bytes 0002 hex See Terminating the Transfer and Checking the Result or Theory of Operation on why two bytes are required j For linked chaining mode the carry cycle array is similar to the previous carry cycle array except that you need the link address to the next array entry Figures 6 1 and 6 2 describe how to set up the array for both chaining modes The carry cycle byte is the command that is to be written to the AUXMR of the TLC send EOI RFD Holdoff on ALL and so on This byte must be located somewhere in memory where it can be accessed by the DMAC The address of this byte is the first element in the carry cycle array four bytes The DMAC uses this carry cycle array and the chaining mode with Channel 1 to insert the TLC auxiliary command in the data string The MAR and MTCR are initialized and the carry cycle byte is transferred The MAR and MTCR are then reloaded and the last byte of the data buffer is transferred k Program Channel 1 in the following manner before starting the transfer If VMEbus interrupts are used 1 Set the PCL bits in the DCR of Channel 1 to 01 for status input with inte
117. be achieved under optimum conditions Programmed I O Transfers The GPIB 1014 is able to transfer data to and from the GPIB using programmed I O Transfer rates using programmed I O depend on many factors including how fast the program code executes how fast the microprocessor services interrupts and the operating system overhead Typically the GPIB 1014 transfers data at rates ranging from 10 to 80 kbytes sec using programmed I O GPIB 1014 Functional Description In the simplest terms the GPIB 1014 can be thought of as a bus translator converting messages and signals present on the VMEbus into appropriate GPIB messages and signals Expressed in GPIB terminology the GPIB 1014 implements GPIB interface functions for communicating with other GPIB devices and device functions for communicating with the central processor and memory Expressed in VMEbus terminology the GPIB 1014 is an interface to the outside world Figures 2 1 and 2 2 show typical applications for the GPIB 1014 In Figure 2 1 the GPIB 1014 is used to interface an assortment of test instruments to a VMEbus computer system which then functions as an intelligent System Controller This is the traditional role of the GPIB In Figure 2 2 the GPIB 1014 is used along with other National Instruments interface boards to connect a VMEbus computer to other processors to transfer files electrically rather than manually via a removable storage medium or to perform other interprocess
118. bled by the CPT ENABLE bit AUXRB 0 w Any GPIB command message not decoded by the TLC is treated as an undefined command however any addressed command is automatically ignored when the TLC is not addressed Undefined commands are read using the Command Pass Through Register CPTR The TLC holds off the GPIB Acceptor Handshake in the Accept Data State ACDS until the Valid auxiliary command function code OF hex is written to the AUXMR If the CPT feature is not enabled undefined commands are simply ignored Address Pass Through Address Pass Through Interrupt Enable APT is set by ADMI amp ADMO amp TPAS LPAS amp SCG amp ACDS APT is cleared by pon read ISR1 Notes ADMI Address Mode Register Bit 1 ADMR 1 w ADMO Address Mode Register Bit 0 ADMR 0 w TPAS GPIB Talker Primary Addressed State LPAS GPIB Listener Primary Addressed State 4 10 National Instruments Corporation Chapter 4 Bit 5r 5w 4r 4w Mnemonic DET DET IE END RX END IE Register Bit Descriptions Description SCG GPIB Secondary Command Group ACDS GPIB Accept Data State pon Power On Reset Read ISR1 Bitis cleared immediately after it is read The APT bit indicates that a secondary GPIB address has been received and is available in the CPTR for inspection Note The application program must check this bit when using TLC address mode 3 When APT is set the Data Accepted DAC message is held and the GPIB Handsha
119. bus DMA Controller but also enables comprehensive stand alone diagnostics to be performed on the DMA circuitry without using the GPIB GPIB 1014 User Manual 4 48 National Instruments Corporation Chapter 4 Register Descriptions Transfer Count Registers The Memory Transfer Counter Register MTCR and the Base Transfer Counter Register BTCR are 16 bit registers The MTCR is used to specify how many operands will be transferred An operand can be either a byte 8 bits or a word 16 bits This register is loaded prior to starting the channel and will be decremented with each operand transfer When the contents of this register are zero and the operation is unchained or the chain is exhausted the channel has reached terminal count and the COC bit of the CSR is set In continue mode of operation the BTCR holds the size of the next block to be transferred which is then transferred into the MTCR when the last block is finished In array chaining mode of operation the BTCR holds the number of memory blocks to be transferred Linked chaining mode of operation does not use the BTCR National Instruments Corporation 4 49 GPIB 1014 User Manual Register Descriptions Chapter 4 Function Code Registers VMEbus Address Base Address 29 hex for Memory Function Code Base Address 31 hex for Device Function Code Base Address 39 hex for Base Function Code Attributes Read Write Internal to DMAC 7 6 5 4 3 2 1 0 w On each of th
120. called a three wire interlocked handshake and it guarantees that message bytes on the data lines are sent and received without transmission error GPIB 1014 User Manual E 2 National Instruments Corporation Appendix E Operation of the GPIB NRFD not ready for data NRED indicates when a device is ready or not ready to receive a message byte The line is driven by all devices when receiving commands and by Listeners when receiving data messages NDAC not data accepted NDAC indicates when a device has or has not accepted a message byte The line is driven by all devices when receiving commands and by Listeners when receiving data messages DAV data valid DAV tells when the signals on the data lines are stable valid and can be accepted safely by devices The Controller drives DAV when sending commands and the Talker drives it when sending data messages Interface Management Lines Five lines are used to manage the flow of information across the interface ATN attention The Controller drives ATN true when it uses the data lines to send commands and false when it allows a Talker to send data messages IFC interface clear The System Controller drives the IFC line to initialize the bus and become CIC REN remote enable The System Controller drives the REN line which is used to place devices in remote or local program mode SRQ service request Any device can drive the SRQ line to asynchronously request serv
121. cations ec eee ez A 1 Appendix B Parts List and Schematic Diagrams 1 17 1 sese B 1 Appendix C Sampli amp Prosrans capelli cala C 1 Appendix D Multiline Interface Messages eee cei D 1 Appendix E Operation of the GPIB i e cc cc ee E 1 Types of MESBHHES i essi Monell cag pa de tation ate tint afta etiaai et tears E 1 Talkers Listeners and Controllers eee E 1 The Controller In Charge and System Controller eene E 2 GPIB Signals and Lines E M E 2 GPIB 1014 User Manual x National Instruments Corporation Contents Data Lines c E 2 Handshake dames sicci coe ae utet ae ina pri DSL ade ile iena i E 2 NRED not ready for data e oic e ete ica soia E 2 NDAC not data accepted ueste olo E 3 DAV Cdatary ald eene SERE at veu E 3 Interface Management Lines zogen reta petisti paar E 3 ATN attention tail nau E 3 TRE interface elear arcana E 3 REN remote enable i E 3 SRO service request oen rta to tae ian E 3 EOL end Ot identify ola ii a De TRA Toe Se Mane E 3 Physical and Electrical Characteristics purea nare sd cas er eed rose pude E 4 CONN SUPA ON Requirements deed tetti he toos eaae ooo E 6 Related Documents ue e tea e edat ua ut Dot iet tae tute eeu uec a riale E 7 Appendix F Mnemonics K y on ce aa oh aon Alora F 1
122. channel cannot be started if any of the ACT COC BTC NDT or ERR bits is set in the CSR In this case the channel signals an operation timing error If the operation is unchained as to transfer a single block of data the MAR and the MTCR should have been previously initialized If the operation is chained as to transfer multiple blocks of data the BAR and or the BTCR should have been previously initialized For array chained operation both the BAR and BTCR should have been previously initialized For linked chained operation only the BAR is to be initialized The Continue Mode of Operation The continue bit CNT can transfer multiple blocks in unchained operations The CNT bit is set to continue the current channel operation If an attempt is made to continue a chained operation a configuration error is signaled The BAR and BTCR should have been previously initialized The continue bit can be set at the same time as the STR bit is set to start a channel or it can be set while the channel is still active The operation timing error bit is signaled if a continuation is otherwise attempted GPIB 1014 applications generally do not use the continue mode of operation Halt The CCR has a halt bit that can suspend the operation of the channel If this bit is set a request can still be generated and recognized but the DMAC does not attempt to acquire the bus GPIB 1014 User Manual 6 20 National Instruments Corporation Chapter 6 Theor
123. chassis through the rear to plug into the IEEE 488 connector on the scrambler card The scrambler card is equipped with a 96 pin DIN connector and a 24 pin IEEE 488 connector A dual connector version of the scrambler card is also available for use with two GPIB 1014 2 Interface Cards The Models GPIB 1014 EH GPIB 1014 1S and GPIB 1014 1S EH interface boards use the same cable as the Model GPIB 1014 1 Verification Testing A performance verification test can be run to ensure the board has not been damaged during shipment and also to ensure that the board has been configured correctly To do this you need an interactive control program or an equivalent mechanism such as front panel control jumper or a front panel emulator that can load and read memory and I O addresses The tests presented in Chapter 7 of this manual consist of a series of steps written in a pseudo processor independent language with instructions The steps generally involve writing data to specific GPIB 1014 device registers followed by reading other GPIB 1014 registers to verify that the programming is correct These tests exercise virtually all of the major functions of the GPIB 1014 including I O communications DMA operation and GPIB communications AII functions except GPIB communications can be performed as stand alone operations that is without another GPIB device To completely check the GPIB functions you must use a bus tester or analyzer such as a National Ins
124. commands It is also used to program the five hidden registers e Auxiliary Register A AUXRA e Auxiliary Register B AUXRB e Parallel Poll Register PPR e Auxiliary Register E AUXRE Internal Counter Register ICR Table 4 4 shows the control and command codes used Bit Mnemonic 7 5w CNT 2 0 4 0w COM 4 0 Description Control Code Bits 2 through 0 These bits indicate the control code that is the manner in which the information in bits COM 4 0 is to be used If CNT 2 0 are all zero the special command selected by COM 4 0 is executed Otherwise the hidden register selected by CNT 2 0 is loaded with the data from COM 4 0 Command Code Bits 4 through 0 These bits indicate the command code of the special function if the control code is 000 Table 4 4 is a summary of the implemented special functions Table 4 5 explains the details of each special function If the control code is not 000 these bits are written to one of the hidden registers indicated by the control code in CNT 2 0 Register Bit Descriptions Chapter 4 Table 4 4 Auxiliary Command Summary Function Code COM4 COM0 Hex 43210 Code Auxiliary Command 1 Set Parallel Poll Flag Take Control Asynchronously Pulsed Take Control Synchronously Take Control Synchronously on End Go To Standby Listen Listen in Continuous Mode Local Unlisten Execute Parallel Poll Set IFC Clear IFC Set REN Clear REN Disable System C
125. contains information that can be used to monitor the TLC GPIB address status Bit Mnemonic Tr CIC 6r ATN 5r SPMS 4r LPAS GPIB 1014 User Manual Description Controller In Charge Bit CIC CIDS CADS CIC indicates that the TLC GPIB Controller function is in an active or standby state with ATN on or off respectively If CIC 0 the Controller function is in an idle state with ATN off Attention Bit ATN is a Status bit that indicates the current level of the GPIB ATN signal If ATN 0 the GPIB ATN signal is asserted Serial Poll Mode State Bit If SPMS 1 the TLC GPIB Talker T or Talker Extended TE function is able to participate in a Serial Poll SPMS is set when the TLC has been addressed as a GPIB Talker and the GPIB Active Controller has issued the GPIB Serial Poll Enable SPE command message SPMS is cleared when the GPIB Serial Poll Disable SPD command is received by pon by LMR CRO 2 w or by issuing the Chip Reset auxiliary command Listener Primary Addressed State Bit The LPAS bit is used when the TLC is configured for extended GPIB addressing and when set indicates that the TLC has received its primary listen address In mode 3 addressing see Address Mode Register in this chapter LPAS 1 indicates that the secondary address being received on the next GPIB command represents the TLC extended secondary GPIB listen address LPAS is cleared by pon by LMR CRO 2 w or by issuing the Chip
126. d 4 26 SPE Serial Poll Enable command 4 26 specifications electrical characteristics 2 1 to 2 2 IEEE 488 bus transfer rate A 1 operating environment A 1 physical characteristics A 1 power requirement A 1 storage environment A 1 SPEOI Send Serial Poll EOI Bit 4 40 SPMR See Serial Poll Mode Register SPMR SPMS Serial Poll Mode State Bit 4 20 SPSR See Serial Poll Status Register SPSR SRQ service request line E 3 SRQI Service Request Input Bit 4 15 SRQI IE Service Request Input Interrupt Enable Bit 4 15 standards for GPIB 1 1 storage environment A 1 STR Start Bit 4 56 SUP Supervisor Bit 4 66 Supervisor or Non privileged access configuration 3 3 switches See jumpers and switches Synchronization and Interrupt Control GPIB See GPIB Synchronization and Interrupt Control system reset clock and reset circuitry 6 4 during initialization 5 1 T TA Talker Active Bit 4 21 Take Control Asynchronously Pulsed command codes for 4 28 description 4 31 Take Control Synchronously command codes for 4 28 description 4 31 Take Control Synchronously on END command National Instruments Corporation Index 18 GPIB 1014 User Manual Index codes for 4 28 description 4 31 Talker Listener Controller TLC See also Controller function DMAC channel operation addressed implementation Address Mode 1 5 6 Address Mode 2 5 6 to 5 7 Address Mode 3 5 7 to 5 8 definition 2 12 GPIB interface 6 23 t
127. d by the uPD7210 4 25 Auxiliary Command Summary eese nennen ener 4 28 Auxiliary Commands Detail Description eese 4 29 Examples for Configuring the PPR icut i feci 4 36 DMAC DMA Channel Register Set ite oe irme eive ilari 4 46 Control EgquauensofTranscenerts oriali 6 3 Electrical Charaeteristies criniera iride A 1 Environmental Characteristics uda cod oett etatis ecu etu c eon A 1 Physical Ch racteristiQs eiie eie einn a E E ai A 2 GPIB 1014 User Manual xii National Instruments Corporation About This Manual The GPIB 1014 User Manual describes the mechanical and electrical aspects of the GPIB 1014 the data transfer features and contains information concerning its operation and programming Organization of This Manual The GPIB 1014 User Manual is organized as follows Chapter 1 Introduction describes the GPIB 1014 lists the contents and optional equipment for your GPIB 1014 kit and explains how to unpack the GPIB 1014 kit e Chapter 2 General Description contains the electrical specifications for the GPIB 1014 the data transfer features and describes the characteristics of key interface board components Chapter 3 Configuration and Installation describes the steps needed to configure and install the GPIB 1014 hardware e Chapter 4 Register Bit Descriptions contains a description of the register map a list of interface registers and a description of th
128. d to activate the TLC GPIB Talker and Listener functions If used ton or lon should be set during TLC initialization When the TLC is GPIB Active Controller the Listen and Local Unlisten programmed auxiliary commands are used to activate and deactivate the TLC GPIB Listener function Addressed Implementation of the Talker and Listener The TLC when GPIB Active Controller can address itself by sending its own GPIB Talk or Listen address using the CO bit and the CDOR When another device on the GPIB is acting as Controller the TLC is addressed with GPIB command messages to become a Talker or Listener Address Mode 1 If the TLC ADMR has been configured for Address Mode 1 the TLC responds to the reception of two primary GPIB addresses major and minor Upon receipt of its major or minor MTA or its major or minor MLA from the GPIB Active Controller the TLC is addressed as Talker or Listener If the TLC has received its GPIB Talk Address the TA bit in the ADSR is set the ADSC bit in ISR2 is set and the DO bit in ISR1 is set If the TLC has received its GPIB Listen address the LA bit in the ADSR is set the ADSC bit in ISR2 is set and the DI bit in ISRI is set when the first GPIB data byte is received GPIB 1014 User Manual 5 6 National Instruments Corporation Chapter 5 Programming Considerations Address Mode 2 Address Mode 2 is used when Talker Extended TE or Listener Extended LE functions are to be used TE and LE functions r
129. d to configure some of the board operating parameters GPIB 1014 User Manual 4 2 National Instruments Corporation Chapter 4 Register Bit Descriptions Register Description Format The remainder of this chapter discusses each of the GPIB 1014 registers in the order shown in Table 4 1 Each register group is introduced followed by a detailed bit description of each register The register bit map shows a diagram of the register with the most significant bit bit 15 for a 16 bit register bit 7 for an 8 bit register shown on the left and the least significant bit bit 0 shown on the right A square is used to represent each bit Each bit is labeled with a name inside its square An asterisk after the bit name indicates that the signal is active low An asterisk is equivalent to an overbar In many of the registers several bits are labeled with an X indicating don t care bits When a register is read these bits may appear set or cleared and should be ignored If the register is written to these bit locations should be cleared Mnemonics are assigned to messages states registers and bits Most mnemonics contain a clue to their meaning Table 4 2 contains a list of clues to look for Table 4 2 Clues to Understanding Mnemonics Clue Mnemonic Probably Stands For Ends in IE Interrupt Enable bit Ends in EN Enable bit 4 letters Interface function as defined in the ends in S IEEE 488 standard 3 letters uppercase Remote GPI
130. dicates that if the board has been granted the bus BGIN asserted BGACK is released as soon as BBSY is released by another master on the VMEbus While the GPIB 1014 is holding the bus BGACK will be released at all times If a pending DMAC bus request is acknowledged with a BGIN BGMATCH is asserted to maintain the appropriate BGXOUT high When the GPIB 1014 does not request for the bus BGMATCH is unasserted to pass BGXIN directly to BGXOUT through the daisy chain OWNBUS and BBSY are both asserted when the GPIB 1014 is using control or is holding control of the bus If the Release On Request feature is not enabled ROR 1 BUS REL is asserted to release the bus right after the DMAC has finished with its cycle and released OWN If the ROR feature is enabled ROR 0 and the board is simply holding the bus OWN BR and LBROUT all released the board releases the bus as soon as there is an external bus request BRIN asserted Finally BUS REL is asserted to release the VMEbus after the board has released the data bus and the arbiter has released its BGx A typical bus arbitration process is described as follows 1 The DMAC indicates that it needs the bus for a DMA transfer by driving its BR pin low 2 Two bits in CFGI are used to select one of four VMEbus Bus Request Grant lines A 7748139 decoder is used to decode these two bits 3 Because the board does not have control of the bus LBROUT is driven low GPIB 1014 User
131. ding Status bit until the read has finished Bit Mnemonic Description Tr CPT Command Pass Through Bit TW CPT IE Command Pass Through Interrupt Enable Bit CPT is set on UCG ACG amp TADS LADS amp undefined amp ACDS amp CPT ENABLE UDPCF amp SCG amp ACDS amp CPT ENABLE CPT is cleared by pon read ISR1 Notes UCG GPIB Universal Command Group message ACG GPIB Addressed Command Group message TADS GPIB Talker Addressed State LADS GPIB Listener Addressed State defined GPIB command automatically recognized and executed by TLC National Instruments Corporation 4 9 GPIB 1014 User Manual Register Bit Descriptions Bit Mnemonic 6r APT 6w APT IE GPIB 1014 User Manual Chapter 4 Description undefined GPIB command not automatically recognized and executed by TLC ACDS GPIB Accept Data State CPT ENABLE AUXRB 0 w UDPCF Undefined Primary Command Function SCG GPIB Secondary Command Group message pon Power On Reset TAG GPIB Talk Address Group message LAG GPIB Listen Address Group message read ISRI Bit is cleared immediately after it is read UDPCF is set on UCG ACG amp TADS LADS amp undefined amp ACDS amp CPT ENABLE UDPCF is cleared on UCG ACG amp defined TAG LAG amp ACDS CPT ENABLE pon The CPT bit flags the occurrence of a GPIB command not recognized by the TLC and all following GPIB secondary commands when the Command Pass Through feature is ena
132. dix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation Filling out a copy of the Technical Support Form before contacting National Instruments helps us help you better and faster National Instruments provides comprehensive technical assistance around the world In the U S and Canada applications engineers are available Monday through Friday from 8 00 a m to 6 00 p m central time In other countries contact the nearest branch office You may fax questions to us at any time Technical Support Phone 512 795 8248 Technical Support Fax 512 794 5678 Branch Offices Phone Number Fax Number Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 79 90 19 Belgium 02 757 00 20 02 757 03 11 Canada Ontario 905 785 0085 905 785 0086 Canada Quebec 514 694 8521 514 694 4399 Denmark 45 76 26 00 45 76 26 02 Finland 90 527 2321 90 502 2930 France 1 48 14 24 24 1 48 14 24 14 Germany 089 741 31 30 089 714 60 35 Hong Kong 2645 3186 2686 8505 Israel 03 5734815 03 5734816 Italy 02 413091 02 41309215 Japan 03 5472 2970 03 5472 2977 Korea 02 596 7456 02 596 7455 Mexico 5 520 2635 5 520 3282 Netherlands 0348 433466 0348 430673 Norway 32 84 84 00 32 84 86 00 Singapore 2265886 2265887 Spain 91 640 0085 91 640 0533 Sweden 08 730 49 70 08 730 43 70 Switzerland 056 200 51 51 056 200 51 55 Taiwan 02 377 1200 02
133. dressed State TADS This operation can be transparent to a program The Talker Active TA bit in the Address Status Register ADSR is set when the TLC receives its GPIB talk address 2 The TLC receives the GPIB TCT message 3 The current Active Controller sees the completed handshake goes to idle and unasserts ATN 4 As soon as the ATN line on the GPIB is unasserted the TLC automatically becomes CIC and asserts ATN As soon as the TLC becomes CIC the CIC bit in the ADSR and the Command Output CO bit in Interrupt Status Register 2 ISR2 are set Using these two bits the program can clearly determine that the TLC is the GPIB Active Controller and can send remote messages National Instruments Corporation 5 3 GPIB 1014 User Manual Programming Considerations Chapter 5 Sending Remote Multiline Messages Commands The GPIB 1014 sends commands as Active Controller simply by writing to the Command Data Out Register CDOR in response to the CO status bit in ISR2 DMA transfers are not supported when the TLC is GPIB Active Controller and should not be attempted The TLC recognizes any commands applicable to itself such as its own talk or listen address Thus to make the TLC a Listener write its listen address to the CDOR Going from Active to Standby Controller If the TLC is GPIB Active Controller the Controller Standby State CSBS is entered upon reception of the Go To Standby auxiliary command The ATN line is una
134. ds to be sent which must be less than 256 Interruption of any data transfer in progress is acceptable Actions ssue TCA command to assert ATN in case the GPIB 1014 is at standby Load the dO register with the address of cmdbuf Load a0 with the number of commands Call CSEND to transmit the bytes Status on return GPIB 1014 is Active Controller GPIB devices are programmed as implied by command bytes Take control in case at standby Set up registers for CSEND call Call CSEND to send commands C 20 National Instruments Corporation Appendix C 68000 Code PASSC movb TCA AUXMR movb UNT cmdbuf movb UNL cmdbuf 1 movb tctadr cmdbuf 2 movb TCT cmdbuf 3 movw 4 cmdct bsr CMD rts National Instruments Corporation Sample Programs ok ck ck ck ck ck ck ko KR Ck Ck Ck k KK KKK KK PASS CONTROL PASSC ok ck ck ck ck ck ck ko Ck Ck Ck Ck KK KK KK kk Summary Passes GPIB Controller In Charge status to another device Assumptions on entry The GPIB 1014 is Controller In Charge The primary GPIB address of the new controller is placed in tctadr Actions Send TCA command to take control in case the GPIB 1014 is at standby Set up the command buffer and command count Call CMD to send the command bytes Status on return The GPIB 1014 is Idle Controller Comments Take control in case at standby Set up the command buffer The GPIB 1014 automatically
135. e The carry cycle byte 81 HLDA was transferred to the TLC automatically by the GPIB 1014 after it transferred the first two bytes and before the last data byte 7 9 GPIB 1014 User Manual Appendix A Hardware Specifications This appendix specifies the electrical environmental and physical characteristics of the GPIB 1014 board and the conditions under which it should be operated Table A 1 Electrical Characteristics Transfer Rates DMA Over 500 kbytes sec Programmed I O Over 80 kbytes sec Power Requirement 5 VDC 1 6 A typical 2 0 A maximum Actual speed may vary considerably from those shown due to instrumentation capabilities Table A 2 Environmental Characteristics Operating Environment Component Temperature 0 to 70 C Relative Humidity 10 to 90 noncondensing Storage Environment Temperature 55 to 71 C Relative Humidity 10 to 90 noncondensing National Instruments Corporation A I GPIB 1014 User Manual Hardware Specifications Appendix A Table A 3 Physical Characteristics di ni gt a d I O Connector GPIB 1014 1S IEEE 488 Standard 24 pin GPIB 1014 2 VMEbus P2 connector GPIB 1014 User Manual A 2 National Instruments Corporation Appendix B Parts List and Schematic Diagrams This appendix contains the parts list and schematic diagrams for the GPIB 1014 National Instruments Corporation B 1 GPIB 1014 User Manual Parts List and Schematic Diagrams Appendix
136. e 3 4 Default Settings of AM Code Jumpers W3 W4 and W5 Rev D and earlier versions of the GPIB 1014 do not have jumpers W3 W4 and W5 If all of the jumpers on later versions of the board remain in their factory default settings the address modifier codes generated are equivalent to those generated by the earlier versions The GPIB 1014 can produce eight AM codes from the default settings of W3 W4 and W5 These eight codes are the most commonly used Table 3 1 lists these AM codes next to the corresponding DMAC Function Code Register FCR values needed to produce the codes See Chapter 4 for a description of the DMAC FCR National Instruments Corporation 3 5 GPIB 1014 User Manual Configuration and Installation Chapter 3 Table 3 1 Programming Values for Default Settings of W3 W4 and W5 FCR Bits AM Codes M2 through M0 o m se If it is necessary to produce a code other than those listed in Table 3 1 you can produce any arbitrary AM code by changing jumpers W3 W4 and W5 along with programming the DMAC Table 3 2 shows how each of the six AM code bits is affected by the jumpers and the values of the DMAC s FCR bits Table 3 2 Setting the Address Modifier Code Bits AM5 AMO Jumper W4 AM 0 Jumper W5 AM 1 or AM 1 AM 1 GPIB 1014 User Manual 3 6 National Instruments Corporation Chapter 3 Configuration and Installation For example to produce an AM code of 17 hex a binary value of 010111 comp
137. e Address 04 hex Attributes Read Write Internal to DMAC XRM DTYP DPS ECKE PCL R W The Device Control Register DCR is a device soriented control register Bit Mnemonic Description 7 6r w XRM External Request Mode Bits 7 through 6 The External Request Mode bits indicate whether the channel is in cycle steal or cycle steal with hold transfer mode These two modes are used in all GPIB applications Burst mode is not used in GPIB 1014 GPIB data transfers but may be used in memory to memory transfers 00 Burst Transfer Mode 10 Cycle Steal Mode 01 Undefined Reserved 11 Cycle Steal with Hold Mode 5 Ar w DTYP Device Type Bits 5 through 4 The Device Type bits indicate what type of device is on the channel For the GPIB 1014 GPIB application set the device type to 10 device with ACK For memory to memory transfers set the device type to 00 68000 compatible 00 68000 compatible explicitly addressed 01 6800 compatible explicitly addressed 10 Device with ACK implicitly addressed 11 Device with ACK and READY 3r w DPS Device Port Size Bit The Device Port Size bit indicates the size of the device port For GPIB 1014 GPIB transfers the device port size is 8 bits For memory to memory transfers the device port size can be 8 or 16 bits 0 1 8 bit port 16 bit port National Instruments Corporation 4 51 GPIB 1014 User Manual Register Descriptions Bit Mnemonic 2r w 0 1 0Or w PCL GPIB 1014
138. e DMA registers e Chapter 5 Programming Considerations explains the initialization process sending receiving messages and the serial parallel poll process e Chapter 6 Theory of Operation contains a functional overview of the GPIB 1014 board and explains the operation of each functional block making up the GPIB 1014 e Chapter 7 Diagnostic and Troubleshooting Test Procedures contains test procedures for determining if the GPIB 1014 is installed and operating correctly e Appendix A Hardware Specifications specifies the electrical environmental and physical characteristics of the GPIB 1014 board and the condition under which it should be operated e Appendix B Parts List and Schematic Diagrams contains the parts list and schematic diagrams for the GPIB 1014 e Appendix C Sample Programs contains listings of routines in 68000 assembly language code that implement the essential elements of the major utility functions e Appendix D Multiline Interface Messages lists the multiline interface messages and describes the mnemonics and messages that correspond to the interface functions These functions include initializing the bus addressing and unaddressing devices and setting device modes for local or remote programming The multiline interface messages are IEEE 488 defined commands that are sent and received with ATN TRUE e Appendix E Operation of the GPIB describes the operation of the GPIB National Instruments Corpo
139. e address register is counting up or down the DMAC accesses the parts of the operand in a linear increasing sequence The step between the addresses of the parts is two The size of the parts is of course the size of the device port or memory width The number of parts is the operand size divided by the port size or memory width The address increment is added or subtracted after the operand is transferred Address Register Operation The DMAC has three 32 bit address registers per channel the Memory Address Register MAR Device Address Register DAR and the Base Address Register BAR The MAR is used in all operations since all operations are between memory and a device This register is either initialized before the channel operation is started or is loaded during chaining or continue operations which are discussed later The DAR is used to National Instruments Corporation 6 19 GPIB 1014 User Manual Theory of Operation Chapter 6 address the device VMEbus memory in dual address transfers It is initiated before starting the channel operation The BAR is used only in chaining or continue operations Transfer Count Register Operation The DMAC has two 16 bit transfer counter registers per channel the Memory Transfer Counter MTCR and the Base Transfer Counter BTCR The MTCR is used in all operations to count the number of operands transferred in a block It is decremented by one after each operand is transferred This regis
140. e and non carry cycle DMA transfers Since non carry cycle DMA transfers do not use Channel 1 synchronization detecting on Channel 1 causes no conflict Since carry cycle DMA transfers briefly employ Channel 1 their operations require special considerations If the carry cycle feature is not enabled Channel 0 transfers everything It is desirable to disable interrupts on Channel 0 but enable interrupts on Channel 1 A negative transition on the PCL of Channel 1 occurs if the GPIB is synchronized requesting an interrupt at this point Channel 0 is already complete Since Channel 0 can terminate its operation normally you can simply check the COC and ERR bits in the CSR of Channel 0 to determine the success of the data transfer on Channel 0 If you do use the carry cycle feature however Channel 1 must not terminate its operation and set the COC bit as this termination will cause an interrupt immediately rather than waiting for the GPIB to become synchronized This is why Channel 1 is configured to operate in chained mode with the length of the second and also last block in the chain set to two one more byte than needed This value is loaded in the DMAC Channel 1 transfer count register After one byte is transferred the last byte in the data buffer DMA requests are automatically masked Channel 1 is still active expecting to transfer one more byte but never sees another request so the COC bit is never set The interrupt is disabled on Cha
141. e board The factory default setting of jumper W2 will set this bit to 1 after power up or reset GPIB 1014 User Manual 4 66 National Instruments Corporation Chapter 4 Register Descriptions Bit Mnemonic Description lw LMR Local Master Reset Bit The Local Master Reset bit is used to reset the GPIB 1014 to a known state Setting this bit to a 1 drives the local reset line active while clearing this bit releases the local reset line The local reset line must be left in the active state for at least 10 msec to ensure that the onboard circuitry is reset properly 0 1 Local reset line inactive Local reset line active VMEbus signal SYSRESET if asserted will automatically force a Local Master Reset Ow SC System Controller Bit The System Controller bit is used to control whether the GPIB 1014 is in the System Controller mode or not 0 1 GPIB 1014 is not System Controller GPIB 1014 is System Controller This bit is cleared not System Controller upon reset or power up National Instruments Corporation 4 67 GPIB 1014 User Manual Chapter 5 Programming Considerations This chapter explains the initialization process sending receiving messages and the serial parallel poll process Additional information on programming the uPD7210 GPIB interface chip can be obtained from the uPD7210 GPIB IFC User Manual by NEC Electronics U S A Inc More specific information on programming the 68450 DMAC chip can be obtained fro
142. e entire operand through the device port if the operand is larger than the device port size For single addressing operations like GPIB DMA operations the device port size and the operand size must be equal The transfer counter counts the number of operands transferred For GPIB DMA data transfers the operand size is eight bits and the transfer counter indicates the number of bytes to be transferred For memory to memory transfers the operand size can be byte word or longword Address Sequencing The sequence of addresses generated to address the memory and device depends on the port size operand size whether the addresses are to count up down or not change and whether the transfer is explicitly or implicitly addressed The Sequence Control Register SCR is used to program the memory address count method and the device address count method For single address transfers such as GPIB DMA transfers the device port size and operand size must be equal If the operand size is a byte the address increment decrement is one 1 If the operand size is a word the address increment is two 2 The Memory Address Register and the transfer counter are updated after the operand is transferred For dual address transfers memory to memory the device port size or the memory width need not equal the operand size The DMAC will run multiple bus cycles to transfer operand parts until the entire operand has been transferred Regardless of the way th
143. e four DMAC channels there are three Function Code Registers FCRs associated with the three address registers MAR DAR and BAR The three FCRs are MFCR DFCR and BFCR During a DMA cycle when the DMAC outputs the contents of one of the three address registers the DMAC also outputs the associated FCR The 3 bit value of an FCR along with jumpers W3 W4 and W5 determine the 6 bit Address Modifier AM code on the VMEbus The AM codes are used to identify the type of cycle specified by the DMAC when the GPIB 1014 is the bus master Table 3 1 shows how to program bits M2 through MO to produce AM codes supported by the default settings of W3 W4 and W5 Tables 3 2 shows how to program bits M2 through MO to produce any arbitrary AM code Bit Mnemonic Description 1 3r w X Don t Care Bits Read as zeros or ones 2r w M2 Supervisor User Access Bit If this bit is a one the GPIB 1014 will specify Supervisor access If it is a zero the GPIB 1014 will specify User access lr w MI Standard Short Addressing Bit If this bit is a one the GPIB 1014 will specify a standard 24 bit cycle If it is a zero the GPIB 1014 will specify a 16 bit short I O cycle Or w MO Program Data Access Bit If this bit is a one the GPIB 1014 will access program area If it is a zero the GPIB 1014 will access data area GPIB 1014 User Manual 4 50 National Instruments Corporation Chapter 4 Register Descriptions Device Control Register VMEbus Address Bas
144. e initiates an operand transfer 11 Automatic request the first operand external request the remaining operands GPIB 1014 User Manual 4 54 National Instruments Corporation Chapter 4 Register Descriptions Sequence Control Register VMEbus Address Base Address 06 hex Attributes Read Write Internal to DMAC 7 2 1 0 6 2 4 3 The Sequence Control Register SCR is used to define the sequencing of memory and device addresses Bit Mnemonic Description T 4rlw 0 Reserved Bits Write zeros to these bits 3 2r w MAC Memory Address Count Bits 3 through 2 The Memory Address Count bits indicate the count sequence of the Memory Address Register 00 Memory address does not count 01 Memory address register counts up 10 Memory address register counts down 11 undefined reserved 1 0r w DAC Device Address Count Bits 1 through 0 The Device Address Count bits indicate the address sequence of the Device Address Register This is only used in flowthrough memory to memory DMA transfers 00 Device address does not count 01 Device address register counts up 10 Device address register counts down 11 undefined reserved National Instruments Corporation 4 55 GPIB 1014 User Manual Register Descriptions Chapter 4 Channel Control Register VMEbus Address Base Address 07 hex Attributes Read Write Internal to DMAC 7 6 5 4 3 2 1 0 This register is used to control the operation of the channel By wr
145. e modes for remote or local programming The term command as used here should not be confused with some device instructions that can also be called commands Such device specific instructions are actually data messages Talkers Listeners and Controllers A Talker sends data messages to one or more Listeners The Controller manages the flow of information on the GPIB by sending commands to all devices Devices can be Listeners Talkers and or Controllers A digital voltmeter for example is a Talker and may be a Listener as well The GPIB is a bus like an ordinary computer bus except that the computer has its circuit cards interconnected via a backplane bus whereas the GPIB has standalone devices interconnected via a cable bus The role of the GPIB Controller can also be compared to the role of the CPU of a computer but a better analogy is to the switching center of a city telephone system The switching center Controller monitors the communications network GPIB When the center Controller notices that a party device wants to make a call send a data message it connects the caller Talker to the receiver Listener The Controller addresses a Talker and a Listener before the Talker can send its message to the Listener After the message is transmitted the Controller may unaddress both devices National Instruments Corporation E 1 GPIB 1014 User Manual Operation of the GPIB Appendix E Some bus configurations do not
146. e several requesting channels at the highest priority level a round robin resolution is used For the GPIB 1014 application channel 0 and channel 1 priority are the same Bit Mnemonic Description 7 2r w 0 Reserved Bits Write zeros to these bits 1 0r w CP Channel Priority Bits 1 through 0 The Channel Priority bits indicate the channel priority 00 Priority level 0 01 Priority level 1 10 Priority level 2 11 Priority level 3 National Instruments Corporation 4 61 GPIB 1014 User Manual Register Descriptions Chapter 4 Interrupt Vector Registers Each channel has a Normal Interrupt Vector Register NIVR and an Error Interrupt Vector Register EIVR each consisting of eight bits The CPU responds to an interrupt request from the DMAC by executing an Interrupt Acknowledge Cycle The GPIB 1014 hardware detects this cycle and checks to see if the indicated priority matches its own programmable priority level for the VMEbus this can be level 1 through 7 If it does the GPIB 1014 hardware acknowledges the interrupt service to the DMAC and the DMAC completes the cycle by placing the appropriate programmable interrupt vector on the lower eight bits of the data bus for the channel requesting an interrupt The EINT bit of the Channel Control Register CCR determines if an interrupt can be generated by the channel The interrupt request is generated if EINT is set and any of the three following conditions is met e The COC bit is
147. ead and Write Transfers During the slave read and write to the DMAC both transceivers are enabled In contrast only the lower 8 bit transceivers are enabled during accesses to the TLC or to the two onboard 8 bit Configuration Registers The GPIB 1014 drives the VMEbus data lines during onboard register reads and receives is driven by the data on the VMEbus during onboard register writes DMA Transfers During DMA transfers the 8 bit data bus of the TLC can be directed to either the lower eight bits D7 through DO or the upper eight bits D15 through D08 of the VMEbus data bus This is National Instruments Corporation 6 1 GPIB 1014 User Manual Theory of Operation Chapter 6 accomplished using an F245 8 bit data transceiver which gates the upper data byte to the TLC This data transceiver is automatically controlled by the DMAC signal HIBYTE When the data transfer is on VMEbus data lines D07 through D00 the HIBYTE is not active and the TLC data bus is connected to the lower eight bits of the VMEbus data bus When the data transfer is on VMEbus data lines D1 through D09 HIBYTE is active and the TLC data bus is connected to the upper eight bits of the VMEbus data bus This feature allows the 8 bit GPIB data to be packed in the 16 bit VMEbus memory When the GPIB 1014 is acting as a VMEbus master it drives the VMEbus data lines on VMEbus memory writes and receives from is driven by the VMEbus data lines on VMEbus memory reads Cont
148. eared so that both the STR and CNT bits of the CCR are cleared GPIB 1014 User Manual 6 24 National Instruments Corporation Chapter 6 Theory of Operation Sources of errors are as follows Configuration Error Operation Timing Error Address Error Bus Error Count Error Abort This occurs when any undefined or reserved bit pattern or illegal device operand size combination is programmed into a channel and an attempt is made to set the STR bit This error occurs for example when chaining is programmed and the continue bit is also set if the DT YP bit specifies a single address transfer and the device port size is not the same as the operand size or if DT YP is 68000 or 6800 DPS is 16 bits SIZE is eight bits and REQG is 10 bits or 11 bits request pin Setting an undefined configuration signals a configuration error The undefined configurations are XPM 01 MAC 11 DAC 11 CHN 01 SIZE 11 In any case the channel will not start If a write access is attempted to certain registers or bits within registers while a channel is active or if certain status bits are set an operation timing error occurs and the channel operation aborts if the channel is active This error will occur for example if an attempt is made to continue an operation without STR being simultaneously set if the channel is not active if an attempt to set STR is made with ACT COC BTC NPT or ERR asserted if an attempt is made to write to the
149. ed in CFG1 During a DMA transfer from the VMEbus memory to the GPIB the carry cycle feature is used to make the TLC send the EOI bit active with the last byte of data During a DMA transfer from the GPIB to the VMEbus memory the carry cycle feature is used to make the TLC hold off the GPIB handshake sequence after the last byte has been accepted by all GPIB Listeners Channel 0 is used to control the transfer of the entire block n bytes of data when the carry cycle feature is not selected If the carry cycle feature is used Channel 0 is used to control the transfer of the first n 1 bytes of data Then Channel 1 is used to transfer one byte of data the carry cycle byte from the VME system memory to the TLC Auxiliary Register and to transfer the last nth byte of data The carry cycle byte must be written to the TLC just prior to the last data byte in order to instruct the TLC to handle the last byte as needed to send EOI or holdoff handshake The carry cycle byte is just a TLC auxiliary command that is inserted in the n byte transfer There is a slight preparation process you need to do if you use the carry cycle See DMA Transfers with a Carry Cycle later in this chapter After the GPIB 1014 has transferred n bytes of data it then automatically detects for GPIB handshake synchronization that is if all Listeners have accepted the data This synchronization signal along with interrupt signals from the TLC and VMEbus signal BERR are all r
150. ed to 4 3 REM Remote Bit 4 16 REMC Remote Change Bit 4 17 REMC IE Remote Change Interrupt Enable Bit 4 17 REMOTE ENABLE REN sample program C 8 REN remote enable line E 3 REOS END on EOS Received Bit 4 37 REQG DMA Request Generation Bits 1 through 0 4 54 reset See system reset Return to Local rtl command codes for 4 28 description 4 30 RFD Holdoff mode 4 38 RFD Ready for Data message 4 6 ROR Release On Request Bit 4 65 rsv Request Service Bit 4 19 S S Status Bit Polarity Bit 4 36 S 6 1 Serial Poll Status Bits 6 through 1 4 19 S8 Serial Poll Status Bit 8 4 19 SAB Software Abort Bit 4 56 6 18 sample programs COMMAND CMD C 20 COMMAND SEND CSEND C 19 DATA SEND DSEND C 14 to C 16 GPIB 1014 Sample Functions for Driver C 2 to C 4 INITIALIZE INIT C 5 to C 6 INTERFACE CLEAR IFC C 7 overview C 1 PASS CONTROL PASSC C 21 READ C 12 to C 13 RECEIVE RCV C 11 REMOTE ENABLE REN C 8 WRITE C 17 to C 18 SC System Controller Bit 4 67 schematic diagrams B 1 to B 9 National Instruments Corporation Index 16 GPIB 1014 User Manual SCR See Sequence Control Register SDC Selected Device Clear command 4 25 Send EOI SEOI command codes for 4 28 description 4 30 sending receiving messages using direct memory access DMA transfers with carry cycle 5 13 to 5 17 DMA transfers without carry cycle 5 10 to 5 12 polling during DMAs 5 17 sending END or EOS 5 17 terminating on END o
151. egister d CADR LI orli aio 4 44 End of String Register EOSR nece teet eet tee Ra rnb laine 4 45 DMA ReUISIOES irlanda ooo 4 46 Address Reglslets 2 e aL o rina 4 48 Transfer Count Resistere eie eost e pi ud a pibe tu io uideret idi Ede dha 4 48 Function Code R6glsters eee eI rS SH parita rea 4 50 Device Control Resistere Bunce ear s E ease ae eee Coe Rd eode 4 5 Operation Control Resistere dun o eii eit tossed be eae a Ra qe 4 53 Sequence Control Remstet ioco delis dioe das qu ttasetub M b basse 4 55 Chantel Control Register uses aee eG Ica epe RI I EUM aes 4 56 Channel Status Restelli 4 58 Channel Brror Re GIS Ler aces teles alien 4 60 Channel Priority Register o lie en 4 61 Interrupt Vector RE SISTSIS sos toe ecd la li 4 62 General Control Register Liana 4 63 Conlieuration REBISCETS s aureae voe pottea ola irc 4 64 Configuration Register 1 CFG1 seen 4 64 Configuration Register 2 CEGD J cott ii ied ety ath ier ee dn SENE gh 4 66 Chapter 5 Programming Considerations 1 essere 5 1 uie libet Ea aaisa 5 1 The GPIB 1014 as GPIB Controller priori qo spreto soc bit uti cedes 5 3 Becoming Controller In Charge CIC and Active Controller 5 3 Sending Remote Multiline Messages Commands sess 5 4 Going from Active to Standby Controller eee 5 4 GPIB 1014 User Manual viii National Ins
152. emarks or trade names of their respective companies Warming Regarding Medical and Clinical Use of National Instruments Products National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment FCC DOC Radio Frequency Interference Compliance This equipment generates and uses radio frequency energy and if not installed and used in strict accordance with the instructions in this manual may cause interference to radio and television reception This equipment has been tested and found to comply with the following two regula
153. en transferred from the TLC This means that the TLC has already accepted the byte from the GPIB By the time the DMA transfer is complete all devices on the GPIB may have already GPIB 1014 User Manual 6 14 National Instruments Corporation Chapter 6 Theory of Operation accepted the byte and the Talker may have already released DAV For this reason the synchronization circuitry looks at the level of the DAV line rather than for a transition When the DAV line is detected high all devices have accepted the byte and a negative transition is generated on the PCL of Channel 1 requesting an interrupt For the GPIB 1014 to wait until the GPIB is synchronized to signal that the DMA transfer is complete it must be configured to wait until the PCL transition occurs to notify the host CPU Each DMA channel of the DMAC has one interrupt enable which generates an interrupt not only for the PCL transition but also if the COC bit is set in the channel CSR The COC bit Channel Operation Complete is set when the channel has finished its DMA transfer If the channel was operated in the chained mode array or linked chained COC will be set after the DMAC has transferred the last data byte in the last data block of the chain The condition of interest is not just when the DMAC is finished but when the DMAC is finished and the GPIB is synchronized that is two conditions must be satisfied Channel 1 is used to detect synchronization for both carry cycl
154. eneration of the rdy message In continuous mode the DI bit is not set when a data byte is received The continuous mode caused by the Listen in Continuous Mode command is released when the Listen auxiliary command is issued or the TLC enters the Listener Idle State LIDS Local Unlisten The Local Unlisten command generates the local message lun in the form of a pulse Execute Parallel Poll The Execute Parallel Poll command sets the local message Request Parallel Poll rpp The rpp message is cleared when the TLC enters either Controller Parallel Poll State CPPS or Controller Idle State CIDS The transition of the TLC interface function is not guaranteed if the local messages rpp and Go To Standby gts are issued simultaneously when the TLC is in Controller Active State CACS and Source Transfer State STRS or Source Delay State SDYS Set IFC Clear IFC These commands generate the local message request system control rsc and set Interface Clear IFC to the value of COM3 These commands should only be issued if the System Controller SC bit in CFG2 is set that is the GPIB 1014 is SC In order to meet the IEEE 488 requirements you must not issue the Clear IFC command until IFC has been held true for at least 100 usec Set REN Clear REN These commands generate the local message rsc and set REN to the value in COM3 These commands should only be issued if the SC bit in CFG2 is set that is the GPIB 1014 is SC In orde
155. equire receipt of two addresses primary and secondary before setting TA or LA The TLC GPIB primary address is indicated by the byte written to ADRO The secondary address is indicated by the byte written to ADR1 Upon receipt of both the primary and secondary GPIB addresses the TLC becomes an addressed Talker or Listener If the TLC has received its primary GPIB Talk address the Talker Primary Addressed State TPAS bit in the ADSR is set If the TLC has received its primary GPIB Talk address immediately followed by its secondary GPIB Talk address the TA bit in the ADSR is set the ADSC bit in ISR2 is set and the DO bit in ISR1 is set If the TLC has received its Primary GPIB Listen address the LPAS bit in the ADSR is set If the TLC has received its primary GPIB Listen address immediately followed by its secondary GPIB Listen address the LA bit in the ADSR is set the ADSC bit in ISR2 is set and the DI bit in ISR1 is set when the first GPIB data byte is received The MJMN bit in the ADSR indicates whether the address status refers to the major or minor address Address Mode 3 Address Mode 3 like Address Mode 2 is used to implement Extended GPIB Talk and Listen address recognition However unlike Address Mode 2 Address Mode 3 provides for both major and minor primary addresses and your program must identify the secondary address by reading the CPTR Proper operation using Address Mode 3 is listed as follows 1 During initialization of t
156. er In Charge Bit Controller Idle State Clock Bits 3 through 0 Continue Bit Control Code Bits 2 through 0 Command Out Channel Operation Complete Bit Enable Interrupt on Command Output Bit Command Code Bits 4 through 0 Controller Parallel Poll State Command Pass Through Bit Command Pass Through Enable Bit Enable Interrupt on Command Pass Through Bit Command Pass Through Register Command Pass Through Bits 7 through 0 Controller Parallel Poll Wait State Chip Select Signal Controller Standby State Controller Standby Hold State Controller Service Not Requested State Controller Service Requested State Controller Synchronous Wait State Controller Transfer State C function Data Lines 0 through 15 Single Odd Byte Transfers Data Lines 16 through 31 Data Byte Data Accepted DAC holdoff release Data Valid Device Clear Device Clear Active State Device Clear Idle State Device Clear Device Clear Bit Enable Interrupt on Device Clear Bit Device Clear Received F 4 National Instruments Corporation Appendix F DEN DET DET IE DHDC DHDT DI DI 7 0 DI IE DIO 1 8 DIR DL DLO DLI DMA DMAI DMAO DO DO IE DSO DS1 DT DT DTO DTI DTACK DTAS DTIS E END END IE END RX EOI EOI EOI OE EOS EOS 7 0 EOSR ERR ERR ERR IE EV National Instruments Corporation GS n gal aa MM i ML nn RM RM LM RM RM LS Mnemonics Key Data Enable Device Execute Trigger Bit Enable
157. ery similar to array chaining The difference is that it uses a list in memory consisting of memory address transfer counts and linked addresses While array chaining requires a continuous address amp transfer count array the linked address in each entry allows a non continuous address amp transfer count array Each entry in the chain list is 10 bytes long four bytes to hold the address of the data block two bytes to hold the transfer count and the last four bytes to hold the linked address of the next array entry The link address of the last array entry must be set to zero Similar to array chaining the BAR points to the first array entry but the BTCR is unused Before starting any block transfers the DMAC fetches the entry currently pointed to by the BAR The address information is placed in the MAR the count information is placed in the MTCR and the link address replaces the current contents of the BAR The channel then begins a new block transfer As each chaining entry is fetched the updated BAR is examined for the terminal link which has all 32 bits equal to zero When the new base address is the terminal address the chain is exhausted and the entry just fetched determines the last block of the channel operation Linked chaining allows entries to be easily removed or inserted without having to reorganize data within the chain Since the end of the chain is indicated by a terminal link the number of entries in the chain need not be s
158. ess register operation 6 17 address sequencing 6 17 data transfers 6 16 device port size 6 17 device TLC DMAC communication 6 15 DMA requests 6 16 operand size 6 17 operands and addressing 6 17 transfer count register operation 6 17 to 6 18 initiation and control of channel operations National Instruments Corporation Index 6 GPIB 1014 User Manual continue mode of operation 6 18 halt 6 18 initiating the operation 6 18 interrupt enable 6 19 software abort 6 18 overview 6 15 DMAI DMA Input Enable Bit 4 16 DMAO DMA Out Enable Bit 4 16 DO Data Out Bit 4 12 DO IE Data Out Interrupt Enable Bit 4 12 documentation abbreviations used in the manual vi related documents vi to vii E 7 don t care bits 4 3 See also X Don t Care Bit DPS Device Port Size Bit 4 51 DT Disable Talker Bit 4 43 DTO Disable Talker 0 Bit 4 42 DT1 Disable Talker 1 Bit 4 44 DTB control transceivers 2 12 DTB Requester and Controller flip flop operations illustration 6 10 theory of operation 6 9 to 6 12 typical bus arbitration process 6 11 DTYP Device Type Bits 5 through 4 4 51 GPIB 1014 User Manual Index 7 Index National Instruments Corporation Index E EINT Interrupt Enable Bit 4 57 4 62 6 19 electrical characteristics See physical and electrical characteristics END IE End Received Interrupt Enable Bit 4 10 to 4 11 End of String Register EOSR 4 45 END or EOS sending receiv
159. est line IRQ6 selected 111 Interrupt request line IRQ7 selected No interrupt request line is selected after power up or after the board is reset GPIB 1014 User Manual 4 64 National Instruments Corporation Chapter 4 Register Descriptions Bit Mnemonic Description 4 3w BRG Bus Request Grant Bits The Bus Request Grant bits are used to select which pair of the VMEbus request grant lines are used by the GPIB 1014 to request and obtain control of the system bus 00 BRO BGOIN BGOOUT selected 01 BRI BGIIN BGIOUT selected 10 BR2 BG2IN BG2OUT selected 11 BR3 BG3IN BG30OUT selected BRO BGOIN BGOOUT is selected automatically after power up or after the board is reset 2w CC Carry Cycle Bit The Carry Cycle bit is used to enable or disable the automatic carry cycle feature of the GPIB 1014 1 0 Carry Cycle feature enabled Carry Cycle feature disabled The feature is not enabled after power up or after the board is reset lw ROR Release On Request Bit The Release On Request bit is used to indicate the status of the Release On Request feature for the GPIB 1014 1 0 Release On Request feature disabled Release On Request feature enabled The feature is automatically disabled ROR 1 after power up or after the board is reset Ow DIR Direction Bit This bit is used to indicate the direction of the GPIB DMA data transfer 0 1 Transfer from system memory to GPIB Transfer from GPIB to system me
160. ew buffer can be compared against expected results The DMAC must be configured to provide flowthrough transfers using the automatic request mode GPIB Interface Testing The NDAC and DIO1 bits can be used to determine if the output signals of the TLC the 75160A and the 751624 are functioning properly Since most failures including problems with shorts or open on the printed wire board prevent the TLC from working at all this test gives National Instruments Corporation 6 27 GPIB 1014 User Manual Theory of Operation Chapter 6 limited assurance that the TLC and its associated circuitry are working and that the output signals can be manipulated properly NDAC is the GPIB Not Data Accepted signal By programming the TLC to Listen or not Listen via the AUXMR NDAC can be asserted or not asserted respectively DIO1 is the GPIB Data Input Output bit 1 LSB By programming the TLC as active GPIB Controller and sending command bytes using the CO bit the CDOR DIO1 can be asserted and unasserted for testing GPIB 1014 User Manual 6 28 National Instruments Corporation Chapter 7 Diagnostic and Troubleshooting Test Procedures This chapter contains test procedures for determining if the GPIB 1014 is installed and operating correctly The tests are similar to those used by National Instruments to verify correct hardware functioning The method used is to program specific internal functions by writing to one or more registers the
161. fects the polarity of the TLC INT pin Setting INV causes the polarity of the Interrupt INT pin on the TLC to be active low As implemented on the GPIB 1014 configuring the INT pin to active low results in interrupt request errors Consequently INV must always be cleared and must never be set except for diagnostic purposes INV 0 INT pin is active high INV 1 INT pin is active low National Instruments Corporation 4 39 GPIB 1014 User Manual Register Descriptions Bit Mnemonic 2w TRI lw SPEOI Ow CPT ENABLE GPIB 1014 User Manual Chapter 4 Description Three State Timing Bit The TRI bit determines the TLC GPIB Source Handshake Timing T1 TRI can be set to enable high speed data transfers T1 2 500 nsec when tri state GPIB drivers are used The GPIB 1014D uses tri state GPIB drivers except during Parallel Poll responses in which case the GPIB drivers automatically switch to Open Collector Setting TRI enables high speed timing as T1 of the GPIB Source Handshake after transmission of the first byte Clearing TRI sets the low speed timing T1 2 2 usec Send Serial Poll EOI Bit The SPEOI bit permits or prohibits the transmission of the END message in Serial Poll Active State SPAS If SPEOI is set EOI is sent true when the TLC is in SPAS otherwise EOI is sent false in SPAS Command Pass Through Enable Bit The CPT ENABLE bit permits or prohibits the detection of undefined GPIB commands and permits or p
162. first reads using DMA the address of the next block to be transferred into the MAR then starts the actual data transfer In most GPIB to memory transfers the array chained mode of operation is used For more information on this mode see Sending Receiving Messages in Chapter 5 and Block Termination in Chapter 6 The Device Address Register DAR is used to hold the device address when the DMA transfer is in dual address flowthrough mode This mode is used for devices that cannot be implicitly addressed with an acknowledge ACK signal but must be addressed via the address bus Flowthrough transfers address both the memory and the device by executing two bus cycles and storing the data temporarily in an internal register In single address flyby transfers the device is implicitly addressed with an acknowledge signal so that the data transfer takes one cycle and the data is transferred directly between the device and memory DMA transfers between the GPIB and VMEbus memory use only flyby mode so the device address register is not used General purpose memory to memory flowthrough transfers use both the MAR and DAR to hold the source and destination VMEbus memory addresses While data transfers between the GPIB and VMEbus memory must use flyby mode memory to memory DMA transfers can be accomplished using any of the four available full function DMA channels channels 0 to 3 This not only makes the GPIB 1014 available as a general purpose VME
163. g scientific or medical instruments to be controlled from a VMEbus based computer The GPIB 1014 has the following features Complete IEEE 488 Talker Listener Controller TLC capability using the NEC uPD7210 GPIB TLC chip DMA transfers Data rates up to 500 kbytes sec Unlimited data block lengths Full 24 bit addressing GPIB synchronization detection General purpose DMA capability Complete software control through programmable configuration parameters One out of four Bus Request Grant lines One out of seven Interrupt Request lines Supervisor or User access Red Green SYSFAIL LED indicator Local Master Reset VME laboratories certified TEEE 1014 VMEbus standard compliance Comprehensive software support National Instruments Corporation 1 1 GPIB 1014 User Manual Chapter 1 Introduction Figure 1 1 shows the GPIB 1014 interface board HS ra j APRORTTO NATIONAL INSTRUMENTS CORP COPYRIGHT 1989 Ian CPIO 1014 1458YIB0155 0 REU G s 1014 Interface Board GPIB 1 1 igure F National Instruments Corporation 1 2 GPIB 1014 User Manual Chapter 1 Introduction The GPIB 1014 interface kit includes hardware and programming examples to implement the GPIB functions Optional cables are supplied for interconnection with other devices on the GPIB What Your Kit Should Contain Your GPIB 1014 kit should contain the following components One of these GPIB 1014 boards e GPIB
164. g of DMA transfers and accesses to the GPIB 1014 from the VMEbus Controls the DMA request acknowledge interface between the DMAC and the TLC Implements the VMEbus priority interrupt protocol allowing the GPIB 1014 to request and respond to an interrupt acknowledge cycle All interrupt conditions are also detectable by polling Performs the necessary VMEbus protocol to request obtain and release control of the VME system bus Once configured for a DMA transfer the GPIB 1014 automatically performs data transfers between the GPIB and VMEbus memory Detects the synchronization of the GPIB after the last byte in a DMA transfer all devices on the GPIB have accepted the last byte and detects interrupting conditions from the TLC TLC interrupt requests are routed through the DMAC which notifies the Interrupter when either a TLC interrupt or one of its own internal interrupt conditions is detected Controls DMA transfers between the GPIB and the VMEbus The DMA Gating and Control circuitry controls the DMA request acknowledge interface between the TLC and the DMAC Implements many of the GPIB interface functions either independently or with assistance of or interpretation by the controlling program Together with special transceivers the TLC forms the GPIB interface side of the GPIB 1014 2 12 National Instruments Corporation Chapter 2 General Description Table 2 5 lists the capabilities of the GPIB 1014 in terms of the IEE
165. g sections discuss these three phases of the channel operation Initialization and Transfer Phases The following paragraphs describe the communication between the TLC the device and the DMAC as well as specific details on how the DMAC controls the data transfer during DMA operations GPIB 1014 User Manual 6 16 National Instruments Corporation Chapter 6 Theory of Operation Device TLC DMAC Communication Communication between the TLC and the DMAC is accomplished mainly by two signals Each of the four DMA channels has a DMA request input REQO through REQ 3 and a DMA acknowledge output ACKO through ACK3 The TLC requests service by first asserting its DMAREQ line waits for its DMAACK pin to assert and finally waits for its RD or WR pins to assert before sending or receiving data The DMA Gating and Control circuitry gates the DMAREQ of the TLC to REQO or REQI depending on if carry cycle function is used Depending on which channel is being serviced either the ACK0 or the ACK1 line is activated during transfers to or from the TLC This line is used to tell the TLC its current DMA request is being serviced the DMAACK of the TLC is asserted Flowthrough memory to memory transfers must use the automatic request mode The ACK line is not activated Each channel also has a peripheral control line PCLO through PCL3 The function of this line is quite flexible and is programmable via the Device Control Register DCR T
166. h strapped lines routed to the P2 connector The base address of the GPIB 1014 is recognized whenever the VMEbus signal AS is active IACK is inactive the Address Modifier lines indicate a short I O operation and VMEbus address lines A15 through A9 match the jumper selected base National Instruments Corporation 6 3 GPIB 1014 User Manual Theory of Operation Chapter 6 address If DS from the master is also asserted local signal BRDEN is asserted Further decoding is necessary to determine which register is being addressed Eight data lines A8 through A1 are latched by an AS573 8 bit register at the start of every slave cycle that is when AS is low and DTACK from the last cycle is high to provide the address decoder with constant address information When the GPIB 1014 has been addressed signal BRDEN is active and VMEbus address line A is a logic zero the DMAC select signal DMACS is driven active indicating that the DMAC has been addressed Address lines A7 through Al DS0 and DS1 are then used to select one of the internal registers of the DMAC The DMAC can function as an 8 or 16 bit slave AII registers within the chip can be accessed with 8 or 16 bit transfers A 16 bit access to an 8 bit register will return arbitrary data in the unused bits Reading from unused locations within the address range occupied by the DMAC results in a normal bus cycle but returns all ones Also DMAC asserts the DTACK to prevent a bus err
167. he DTYP bits of the DCR define what type of device is on the channel If the DTYP bits are programmed to be a HMCS6800 device the PCL definition is ignored and the PCL is an Enable Clock input If the DTYP bits are programmed to be a device with READY the PCL definition is ignored and the PCL is used as a READY input The PCL is active at all times when it is programmed as a Status input Interrupt input Ready input or Enable input When programmed as an Abort input it is only active after the channel has been started When programmed as a Status input like in most GPIB 1014 applications the status level of the PCL can be determined by reading the PCS bit in the CSR TTL high or low If a negative transition occurs and remains stable for two DMAC clock cycles 8 MHz the PCT bit of the CSR is set The setting of the PCT bit causes an interrupt if interrupts were previously enabled by setting the EINT bit in CCR The GPIB 1014 uses the PCL of Channel 1 PCL1 to detect interrupts from the TLC bus error and GPIB synchronization conditions In addition the board uses the PCLs of Channel 0 PCL0 and Channel 2 PCL2 to detect the status of two GPIB signals SRQ and REN If they are used in a GPIB 1014 application these two PCLs must be programmed as Status input or Interrupt input National Instruments Corporation 6 17 GPIB 1014 User Manual Theory of Operation Chapter 6 DMA Requests Internal or external requests activate the DMAC
168. he GPIB 1014 is Active Controller The Q0 register contains the number of bytes to send The a0 register contains the address oc cmdbuf Initialize a count variable Wait until the CDOR is empty Write a byte and increment the counter Check for a GPIB error Loop until all bytes are transferred On an error set dO to 1 Status on return dO register contains number of bytes sent or 1 if an error occurred Actions CSEND clrw CSEND1 btst beq cmpw beq addw movb btst bne bra CSEND2 movw CSENDS rts count CO ISR2 CSEND1 count d0 CSEND3 1 count a0 CDOR ERR ISR1 CSEND2 CSEND1 1 d0 National Instruments Corporation Initialize count variable Wait till CDOR is empty Have all commands been sent Yes No Increment counter and write the next command If there are no Listeners return 1 in dO register C 19 GPIB 1014 User Manual Sample Programs 68000 Code CMD movb TCA AUXMR movl cmdbuf a0 movw cmdct d0 bsr CSEND rts GPIB 1014 User Manual Appendix C KR RK ok ok ok ok k k k k kc COMMAND CMD oko ko kok ok ok k k k k k kc Summary Send GPIB interface or command messages Assumptions on entry The GPIB 1014 is Controller In Charge The commands to be sent are in cmdbuf The variable cmdct contains the number of comman
169. he TLC enable Address Mode 3 and optionally set the APT IE bit in IMRI to enable an interrupt request on receipt of a secondary GPIB address Write the TLC major GPIB primary address to ADRO and the TLC minor GPIB primary address to ADRI 2 Receipt of the TLC major or minor primary GPIB Talk Address MTA or major or minor primary GPIB Listen Address MLA sets TPAS or LPAS indicating that the primary address has been received 3 If the next GPIB command following the primary address is a secondary address the APT bit is set and a DAC handshake holdoff is activated the GPIB DAC message is held false 4 Inresponse to APT the program must complete the following events Determine whether the command just received is a listen talk major or minor address by reading the LPAS TPAS and MJMN bits of the ADSR e Read the secondary address in the CPTR and determine whether or not it is the address of the TLC 5 If it is not the TLC address issue the Non Valid auxiliary command If it is the TLC address issue the Valid auxiliary command National Instruments Corporation 5 7 GPIB 1014 User Manual Programming Considerations Chapter 5 6 When the Valid auxiliary command is issued the TLC assumes that the My Secondary Address MSA message has been received which causes the following events to occur e The LA bit to be set and the TA bit to be cleared LADS TIDS 1 if LPAS was set or the TA bit to be set and the LA bit to be
170. he cycle and sets the COC and ERR bits in the CSR of the active channel Whether or not a carry cycle was used a bus error also causes a transition on the PCL of Channel 1 requesting an interrupt on Channel 1 The host CPU can detect the error condition by examining the CSR of Channels 0 and 1 68450 DMAC The DMAC is a high performance device and is very flexible It provides four independent DMA channels but the GPIB 1014 uses only Channels 0 and 1 to provide GPIB to memory DMA flyby transfers All four channels are available for general use such as memory to memory DMA transfers The DMAC provides 24 bit addressing a 16 bit data path and programmable selection of the address modifier lines During DMA operations the GPIB 1014 functions as a full VMEbus master The DMAC controls the direction of the GPIB 1014 data bus transceivers as needed to effect the transfer Details of the DMAC operation with emphasis on GPIB 1014 applications are given in the following section DMAC Channel Operation A DMAC channel operation proceeds in three principal phases During the initialization phase the CPU configures the channel control registers sets initial addresses and starts the channel During the transfer phase the DMAC accepts requests for data operand transfers and provides addressing and bus controls for the transfers The termination phase occurs after the operation is completed when the DMAC reports the status of the operation The followin
171. he following conditions e The local pon message is set and the interface functions are placed in their idle states All bits of the SPMR are cleared The EOI bit is cleared All bits of the AUXRA AUXRB and AUXRE are cleared The Parallel Poll Flag and RSC local message are cleared The contents of the ICR is set to eight F3 set to 1 F2 F1 and FO set to 0 The TRMO bit and the TRMI bit are cleared The interface functions are held in their idle states until released by an Immediate Execute pon command Between these commands the TLC unitable bits may be programmed to their desired states continues Register Bit Descriptions Chapter 4 Table 4 5 Auxiliary Commands Detail Description continued Command Code COM4 COM0 43210 Description Finish Handshake FH The Finish Handshake command finishes a GPIB Handshake that was stopped because of a Holdoff on RFD or DAC Trigger Note Trigger cannot be used with the GPIB 1014 The Trigger command generates a high pulse on the TRIG pin T R3 pin when TRM1 0 of the TLC The Trigger command performs the same function as if the DET Device Trigger bit ISR1 5 r were set The DET bit is not set by issuing the Trigger command Return to Local rtl Return to Local rtl The two Return to Local commands implement the rtl message as defined by IEEE 488 When COM3 is zero the message is generated in the form of a pulse When COM3 is one the rtl command is set in
172. hen mode 3 is used When the TLC is in Talker Primary Addressed State TPAS or Listener Primary Addressed State LPAS and a secondary address byte is on the GPIB DIO lines the APT bit of ISR2 is set and the secondary GPIB address may be inspected in the CPTR The TLC Acceptor Handshake is held up in the Accept Data State ACDS until the Valid or Non Valid auxiliary command is written to the AUXMR signaling a valid or invalid secondary address respectively to the TLC Register Bit Descriptions Chapter 4 Bit Mnemonic Description ADMO and ADMI must be cleared when either of the two programmable bits ton or lon is set For more information on the different addressing modes supported by the GPIB 1014 refer to the Addressed Implementation of Talker and Listener section in Chapter 5 GPIB 1014 User Manual 4 24 National Instruments Corporation Command Pass Through Register CPTR VMEbus Address Base Address 11B hex Attributes Read Only Internal to TLC 7 6 5 4 3 2 1 0 R Bit Mnemonic Description 7 Or CPT 7 0 Command Pass Through Bits 7 through 0 These bits are used to transfer undefined multiline GPIB command messages from the GPIB DIO lines to the computer When the CPT feature is enabled CPT ENABLE 1 AUXRB 0 w any GPIB Primary Command Group PCG message not decoded by the TLC is treated as an undefined command The multiline GPIB commands recognized by the uPD7210 are listed in Table 4 3 All GPIB Secondary Command
173. hen the BTCR reaches a terminal count the chain is exhausted and the entry just fetched determines the last block of the the channel operation After this data block is transferred the channel operation is completed and the COC bit will be set As described in Chapter 5 Programming Considerations the array chaining mode is used for Channel 1 in the GPIB 1014 applications to implement the carry cycle feature It is also used to transfer multiple blocks of data on Channel 0 The address amp transfer count array must start at an even address or the entry fetch results in an address error The transfer count the last two bytes of each array entry must be non zero The starting address the first four bytes of each array entry can be even or odd Since the base registers can be read by the CPU appropriate error recovery information is available should the DMAC encounter an error anywhere in the chain An example of the array format for array chaining is shown in Figure 6 2 GPIB 1014 User Manual 6 22 National Instruments Corporation Chapter 6 Theory of Operation Address and Transfer Count Array Data Blocks Start of array Memory Address A E Data Block A of entries 3 Transfer Count A Memory Address B Transfer Count B E Data Block Memory Address C B Transfer Count C Data Block C Figure 6 2 Array Format for Array Chaining Modes Linked Chaining Operations This type of chaining is v
174. ice from the Controller EOI end or identify The EOI line has two purposes The Talker uses the EOI line to mark the end of a message string The Controller uses the EOI line to tell devices to identify their response in a parallel poll National Instruments Corporation E 3 GPIB 1014 User Manual Operation of the GPIB Appendix E Physical and Electrical Characteristics Devices are usually connected with a cable assembly consisting of a shielded 24 conductor cable with both a plug and receptacle connector at each end This design allows devices to be linked in either a linear or a star configuration or a combination of the two See Figures E 1 E 2 and E 3 The standard connector is the Amphenol or Cinch Series 57 Microribbon or Amp Champ type An adapter cable using a non standard cable and or connector is used for special interconnection applications The GPIB uses negative logic with standard TTL logic level When DAV is true for example it is a TTL low level 0 8V and when DAV is false it is a TTL high level 2 2 0V DIO5 DIO6 DIO7 DIO8 REN GND TW PAIR W DAV GND TW PAIR W NRFD GND TW PAIR W NDAC GND TW PAIR W IFC GND TW PAIR W SRQ GND TW PAIR W ATN SIGNAL GROUND DIO1 DIO2 DIO3 DIO4 EOI DAV NRFD NDAC IFC SRQ ATN SHIELD l no lo N a A WIM no Ino no no 2 a Ja Ja ho O 0 OO N o O1 A Figure E 1 The GPIB Connector and Signa
175. iew 6 6 slave cycles 6 6 to 6 7 TLC See Talker Listener Controller TLC ton Talk Only Bit 4 22 TPAS Talker Primary Addressed State Bit 4 21 transceivers for GPIB 1014 component designations 2 2 control equations of transceivers 6 3 Transfer Count Registers Base Transfer Counter Register BTCR 4 48 Memory Transfer Counter Register MTCR 4 48 theory of operation 6 17 to 6 18 TRI Three State Timing Bit 4 40 Trigger command codes for 4 28 description 4 30 TRM 1 0 Transmit Receive Mode Bits 1 through 0 4 22 National Instruments Corporation Index 20 GPIB 1014 User Manual troubleshooting test procedures DMA stand alone testing 6 24 GPIB interface testing 6 24 hardware installation tests 7 2 to 7 8 interpreting test procedures 7 1 overview 7 1 verification of GPIB 1014 before installation 3 10 U U Parallel Poll Unconfigure Bit 4 35 UNL Unlisten command 4 26 unpacking the GPIB 1014 1 4 UNT Untalk command 4 26 V Valid Secondary Command or Address command codes for 4 28 description 4 30 verification of system compatibility 3 7 to 3 9 testing 3 10 VMEbus 68450 internal DMA registers chart 2 4 to 2 5 address 6 2 control equations of transceivers 6 3 control signals 6 2 data lines 6 1 data transfer bus DTB requester description of 2 7 VMEbus modules not provided 2 7 definition 2 12 DMA transfers 6 1 GPIB 1014 Configuration registers chart 2 5 interrupt events
176. igned to translate the bus request BR from the DMAC into the appropriate VMEbus arbitration protocol This circuitry is responsible for informing the DMAC that it has been granted the bus and for implementing the programmable Release On Request feature If the feature is enabled the GPIB 1014 interface board once received and finished using the bus simply holds control and releases the bus only when there GPIB 1014 User Manual 6 10 National Instruments Corporation Chapter 6 Theory of Operation are some external requests for the bus While the board is holding the bus and the DMAC requests the bus the DMAC is immediately granted the bus thus avoiding bus arbitration time The circuitry consists of various components to drive and receive VMEbus signals BBSY BRO through BR3 BGOIN through BG3IN and BGOOUT through BG3OUT An 139 2 to 4 bit decoder is used to select one of the four VMEbus Request Grant lines In addition the circuitry uses three flip flops to keep status of the bus arbitration process that is bus request pending bus grant received and bus release and uses miscellaneous logic to generate various combinational outputs The operation and output of each flip flop Q1 Q2 and Q3 is shown in Figure 6 1 Q2 RESET 0 or BUS_REL 0 BUS_REL 0 BGIN 1 and BR 0 Q3 RESET 0 or BUS_REL 0 BUS_REL 0 OWN 0 and BR 0 Figure 6 1 DTB Requester and Controller Flip Flop Operati
177. ing 5 17 5 20 END RX End Received Bit 4 10 to 4 11 EOI End or Identify Bit 4 44 EOI End or Identify line E 3 EOS 7 0 End of String Bits 7 through 0 4 45 EOSR See End of String Register EOSR ERR Error Bit 4 11 to 4 12 4 59 ERR IE Error Interrupt Enable Bit 4 11 to 4 12 ERROR CODE Channel Error Register 4 60 error conditions DMAC channel operation 6 21 to 6 22 Execute Parallel Poll command codes for 4 28 description 4 32 F features of GPIB 1014 1 1 Finish Handshake FH command codes for 4 28 description 4 30 Function Code Registers 4 50 G General Control Register GCR 4 63 GET Group Execute Trigger command 4 25 Go To Standby command codes for 4 28 description 4 31 GPIB 1014 block diagram 2 11 capabilities 2 13 to 2 15 contents of kit 1 3 definition 1 1 features of 1 1 functional description 2 8 to 2 15 IEEE 1014 compliance levels 2 15 illustration 1 2 major components of 2 12 in multiprocessor application illustration 2 10 optional equipment 1 3 National Instruments Corporation Index 8 GPIB 1014 User Manual Index parts list and schematic diagrams B 1 to B 9 theory of operation 68450 DMAC 6 14 to 6 23 address decoding 6 3 to 6 4 clock and reset circuitry 6 4 to 6 5 Configuration registers 6 5 to 6 6 DMA gating and control 6 7 to 6 8 DTB requester and controller 6 9 to 6 12 GPIB interface 6 23 to 6 24 GPIB synchronization and interrupt control 6 12 to
178. ion Registers CFG1 and CFG2 with the appropriate values to configure the desired operation 3 Set or clear the desired interrupt enable bits in Interrupt Mask Register 1 IMR1 and Interrupt Mask Register 2 IMR2 of the TLC 4 Ifa VMEbus interrupt is used the PCL bits in Channel 1 DCR must be set to 01 for status input with interrupt In addition bit EINT in Channel 1 CCR must be set for Channel 1 to generate an interrupt If polling no interrupt is used set PCL bits to 00 for status input without interrupts Bit EINT should be cleared 5 Ifthe VMEbus interrupt is used load the DMAC Channel 1 NIVR and EIVR with the desired GPIB 1014 Status ID byte 6 Load the TLC primary GPIB address in Address Register 0 ADRO and Address Register 1 ADRI 7 Enable or disable the GPIB Talker and Listener functions and addressing mode using the ADMR 8 Load the Serial Poll response in the SPMR GPIB 1014 User Manual 5 2 National Instruments Corporation Chapter 5 Programming Considerations 9 Load the Parallel Poll response in the Parallel Poll Register PPR if local configuration is used If using remote configuration clear the PPR 10 Clear power on pon by issuing the Immediate Execute pon auxiliary command to the TLC to bring the TLC online 11 Execute the desired TLC auxiliary commands The registers associated with the 68450 DMAC do not need to be configured further until just prior to a DMA operation The GPIB 10
179. ional Instruments Corporation Chapter 2 General Description Table 2 3 68450 Internal DMA Registers continued Address Base Hex Offset Mode Register R W Operation Control OCR2 Sequence Control SCR2 R W Channel Control CCR2 R W Channel Priority CPR2 R W Normal Interrupt Vector NIVR2 R W Error Interrupt Vector EIVR2 R W Memory Transfer Counter MTCR3 R W Memory Address Register MAR3 R W Memory Function Code MFCR3 R W Device Address Register DAR3 R W Device Function Code DFCR3 Base Transfer Counter BTCR3 Base Address Register BAR3 Base Function Code BFCR3 CSR3 Channel Error CER3 R W Device Control DCR3 R W Operation Control OCR3 Sequence Control SCR3 R W Channel Control CCR3 R W Channel Priority CPR3 M Normal Interrupt Vector NIVR3 Error Interrupt Vector EIVR3 Table 2 4 GPIB 1014 Configuration Registers Address Base Hex Offset Mode Register Size WWW LI WW WW WW W Li LI LI LI W O2 101 W Configuration Register 1 8 bits 105 W Configuration Register 2 8 bits VMEbus Master Direct Memory Access The GPIB 1014 can function as a VMEbus master performing data transfers to and from VMEbus memory In most applications the 68450 controls the data transfer to and from the GPIB during DMA and can transfer the 8 bit data on data lines D07 through D00 or D15 through D08 allowing the packing of data in VMEbus memory In addition to GPIB to VMEbu
180. ions Configure DMA channel 0 Clear DMAC status registers Configure channel 1 for carry cycle if END is to be sent with last byte Start DMA channels Set IMR2 to enable DMAs Wait for DMA done or a GPIB error Place in the dO register the number of bytes transferred or 1 on an error Disable further DMAs Status on return The dO register contains the number of bytes transferred or a 1 to indicate an error C 14 National Instruments Corporation Appendix C 68000 Code TMODE DCRO TMODE DCR1 movb movb MTG OCRO MCU SCRO movb movb FF CSRO FF CSR1 movb movb a0 MARO vseoi DSEND1 movl tstb beq movb MTG ACHN OCR1 do d1 1 d1 d1 MTCO movw subw movw movl ccary BAR1 movw 2 BTC1 movl SEOl ccary a0 d2 d2 d1 d1 ccary 6 movi addi movi BRG ECC OUT CFG1 G0 CCRI1 DSEND2 movb movb bra DSEND1 movb BRG OUT CFG2 movw d0 MTCO DSEND2 movb GO CCRO movb DMAO IMR2 DSENDS btst bne btst beq movw bra PCT CSR1 DSEND4 ERR ISR1 DSEND3 1 d0 DSEND6 National Instruments Corporation Sample Programs Comments Set DMA transfer mode Set control registers Clear status registers Point channel 0 to buffer Send END with last byte Yes enable carry cycle feature Enable chaining on channel 1 Channel 0 transfer all but the last data byte Point channel 1 to ccary 2 elements in ccary First ccary address points to SEOI
181. iority Code Bits Internal Counter Register Interrupt DTACK Identify Interface Clear Interrupt Mask Register 1 Interrupt Mask Register 2 Interrupt Bit TLC Interrupt Request Line A TLC Interrupt Request Line B Invert Bit Interrupt Request Interrupt Request Lines 1 through 7 Interrupt Status Register 1 Interrupt Status Register 2 Individual Status Select Bit Individual Status F 6 National Instruments Corporation Appendix F L L LA LACS LADS LAG LD 0 7 LDTACK LE LIDS LLO LMR LOCS LOK LOKC LOKC IE lon lon LPAS LPAS Ipe Ipe LPIS Itn lun LWLS LWORD M MAKOUT MCYC MDTACK MJMN MLA MSA MTA N nba NDAC NPRS NRFD NUL National Instruments Corporation VBS Mnemonics Key Listener Listener Active Bit Listener Active State L function Listener Addressed State L function Listener Address Group Local Data Bus Local DTACK Listener Extended Listener Idle State Local Lockout Local Master Reset Bit Local State Lockout Bit Lockout Change Bit Enable Interrupt on Lockout Change Bit Listen Only Bit Listen Only Listener Primary Addressed State Bit Listener Primary Addressed State Local Poll Enabled Local Poll Enabled Active Low Listener Primary Idle State Listen Local Unlisten Local With Lockout State Low Word Internal IACKOUT From A to B My Cycle DMA Acknowledge Major Minor Bit My Listen Address My Secondary Address My Talk Address
182. iting to this register a channel operation can be started and set to be continued halted and aborted Also the channel can be enabled to issue interrupts when an operation is terminated normal or error termination Setting the STR bit causes immediate activation of the channel the channel will be ready to accept requests immediately The STR and CNT bits of the register cannot be reset by a write to the register The software abort bit SAB can be used to terminate the operation Setting the SAB resets the STR and CNT Setting the HLT bit halts the channel and resetting the HLT bit resumes the operation Bit Mnemonic Description Tr w STR Start Bit The Start bit is used to start the operation of the channel 0 No operation is pending 1 Start operation 6r w CNT Continue Bit The Continue bit is used to select the continue option This bit must be set when the channel is active or at the same time you set the STR bit Generally this is not used for GPIB 1014 GPIB transfers 0 Nocontinuation is pending Continue operation Sr w HLT Halt Bit The Halt bit is used to temporarily halt channel operation O Operation not halted 1 Operation halted Ar w SAB Software Abort Bit The Software Abort bit is used to abort channel operation GPIB 1014 User Manual 4 56 National Instruments Corporation Chapter 4 Register Descriptions O Channel operation not aborted 1 Abort channel operation Bit Mnemonic Description 3r
183. ke stops until either the Valid or Non Valid auxiliary command is issued The secondary address can be read from the CPTR Device Execute Trigger Bit Device Execute Trigger Interrupt Enable Bit DET is set by DTAS DET is cleared by pon read ISR1 Notes DTAS GPIB Device Trigger Active State pon Power On Reset read ISR1 Bit is cleared immediately after it is read The DET bit indicates that the GPIB Device Execute Trigger DET command has been received while the TLC was a GPIB Listener the TLC has been in DTAS End Received Bit End Received Interrupt Enable Bit END RX is set by LACS amp EOI EOS amp REOS amp ACDS END RX is cleared by pon read ISR1 Notes LACS GPIB Listener Active State EOI GPIB End Of Identify Signal National Instruments Corporation 4 11 GPIB 1014 User Manual Register Bit Descriptions Bit Mnemonic 3r DEC 3w DEC IE 2r ERR 2w ERR IE GPIB 1014 User Manual Chapter 4 Description EOS GPIB END Of String message REOS Reception of GPIB EOS allowed AUXRA 2 w ACDS GPIB Accept Data State pon Power On Reset read ISR1 Bit is cleared immediately after it is read The END RX bit is set when the TLC is a Listener and the GPIB uniline message END is received with a data byte from the GPIB Talker or the data byte in the DIR matches the contents of the End Of String Register EOSR Device Clear Bit Device Clear Interrupt Enable Bit DEC is set by DCAS DEC is
184. l Assignments GPIB 1014 User Manual E 4 National Instruments Corporation Appendix E Operation of the GPIB Figure E 2 Linear Configuration National Instruments Corporation E 5 GPIB 1014 User Manual Operation of the GPIB Appendix E Figure E 3 Star Configuration Configuration Requirements To achieve the high data transfer rate that the GPIB was designed for the physical distance between devices and the number of devices on the bus are limited The following restrictions are typical e A maximum separation of 4 m between any two devices and an average separation of 2 m over the entire bus Amaximum total cable length of 20 m No more than 15 devices connected to each bus with at least two thirds powered on GPIB 1014 User Manual E 6 National Instruments Corporation Appendix E Operation of the GPIB Bus extenders are available from National Instruments and other manufacturers for use when these limits must be exceeded Related Documents For more information on topics covered in this section consult the following manuals e ANSI IEEE Std 488 1978 IEEE Standard Digital Interface for Programmable Instrumentation e ANSI IEEE Std 488 1 1987 IEEE Standard Digital Interface for Programmable Instrumentation e ANSI IEEE Std 488 2 1987 IEEE Standard Codes Formats Protocols and Common Commands e MC66450 Direct Memory Access Controller DMAC Motorola Inc National Instruments Corporatio
185. l to TLC Accessed through AUXMR 4 3 2 1 0 XEOS REOS HLDE HLDA W Writing to Auxiliary Register A AUXRA is done via the AUXMR Writing the binary value 100 into the Control Code CNT 2 0 and a bit pattern into the Command Code COM 4 0 portion of the AUXMR causes the Command Code to be written to AUXRA When the data is written to AUXRA the bits are denoted by the mnemonics shown in the register bit map above This 5 bit code controls the data transfer messages Holdoff and EOS END Bit Mnemonic Description 4w BIN Binary Bit The BIN bit selects the length of the EOS message Setting BIN causes the End Of String Register EOSR to be treated as a full 8 bit byte When BIN 0 the EOSR is treated as a 7 bit register for ASCII characters and only a 7 bit comparison is done with the data on the GPIB 3w XEOS Transmit END with EOS Bit The XEOS bit permits or prohibits automatic transmission of the GPIB END message at the same time as the EOS message when the TLC is in Talker Active State TACS If XEOS is set and the byte in the CDOR matches the contents of the EOSR the EOI line is sent true along with the data 2w REOS END on EOS Received Bit The REOS bit permits or prohibits setting the END bit ISR1 4 r at reception of the EOS message when the TLC is in Listener Active State LACS If REOS is set and the byte in the DIR matches the byte in the EOSR the END bit ISR 1 4 r is set National Instruments Corporation 4 37 GP
186. lete the following steps 1 Set jumper W3 to 0 2 Set jumper W4 to 0 3 Set jumper W5 to AM 1 4 Write the pattern 00000111 to the FCR of the DMAC Other Configuration Parameters All other configuration parameters for the GPIB 1014 are software selectable including the following e Selecting one of seven interrupt request lines IRQ1 through IRQ7 e Selecting one of four Bus Request lines BRO through BR3 e Enabling the Release On Request ROR feature e Selecting the automatic carry cycle feature Enabling the GPIB 1014 to be the GPIB System Controller e Selecting the color of front panel SYSFAIL LED indicator Red Green Selecting the DMA transfer mode Software control of these parameters gives you the flexibility to tailor operation and performance to meet the specific requirements of separate tasks within your system Installation The GPIB 1014 is a dual height board that interfaces to the VMEbus P1 and P2 connectors There are two options for the GPIB I O from the GPIB 1014 interface board The following paragraphs describe the GPIB 1014 interface to the VMEbus backplane and to the IEEE 488 bus Verification of System Compatibility The GPIB 1014 does not use all of the signals included in the VMEbus specification Compare signals listed in Tables 3 3 and 3 4 to those signals used by the VMEbus system in which the GPIB 1014 will be installed This is to ensure that the two are compatible that is the GPIB 1
187. ll a damaged board into your computer GPIB 1014 User Manual 1 4 National Instruments Corporation Chapter 2 General Descnption This chapter contains the electrical specifications for the GPIB 1014 the data transfer features and describes the characteristics of key interface board components Electrical Characteristics All integrated circuit drivers and receivers used on the GPIB 1014 meet the requirements of the VMEbus specification and the IEEE 1014 standard Table 2 1 contains a list of the VMEbus signals used by the GPIB 1014 and the electrical loading presented by the circuitry on the interface board in terms of device types and their part numbers Note The asterisk after the bus signal indicates that the signal is active low Table 2 1 GPIB 1014 Signals Bus Signals Part Number Part Number D00 D15 F245 A15 A09 LS2521 Z A07 A01 F245 AMS AM3 AMO LS2521 AMD 5200 DSO DS1 AS WRITE F1241 WORDS Lr I m SYSCLK o a BGOIN BG3IN LS241 BGOOUT BG30UT DTACK continues National Instruments Corporation 2 1 GPIB 1014 User Manual General Description Chapter 2 Table 2 1 GPIB 1014 Signals continued Bus Signals Part Number Part Number BRO BR in I 20 IACKIN 02 asm IRQI IRQ7 BERR SYSFAIL SYSRESET All GPIB transceivers meet the requirements of the IEEE 488 standard The components used are as follows Transceivers Component Designation Data Transceivers DS75
188. ller in Charge The PCL of Channel 2 is connected to the GPIB Remote Enable signal active low This can be used to read the status of the REN line at any time or to generate an interrupt when the REN line is asserted GPIB 1014 User Manual 5 22 National Instruments Corporation Chapter 5 Programming Considerations Serial Polls Conducting a Serial Poll The TLC as CIC can serial poll other devices as described in the IEEE 488 specification From the programming point of view the TLC must first become Active Controller to send the addressing and enabling commands to the device being polled make itself a GPIB Listener by issuing the Listen auxiliary command and then go to standby with the Go To Standby auxiliary command to read the status byte Responding to a Serial Poll The CIC can conduct Serial Polls to determine which device is asserting the GPIB SRQ signal to request service Before requesting the service the recommended practice is to wait until the PEND bit in the SPSR is zero indicating that the TLC is not presently in the middle of a Serial Poll SPAS 0 If PEND 0 write the desired Status Byte STB into the SPMR with the rsv bit set At that time PEND sets and remains set until the Serial Poll completes Once rsv is set the TLC waits until any current Serial Poll is complete before asserting the GPIB SRQ signal In response to that signal the CIC starts the poll addressing the TLC to talk When the CIC unasserts
189. m Controller This bit is used by the 75162 GPIB control transceiver to determine whether the GPIB 1014 drives or receives the GPIB signal IFC e Selecting Supervisor only or User access to the GPIB 1014 A jumper on the GPIB 1014 is used to automatically determine the state of this bit SUP after a system or local reset After reset you can write a to this bit to select Supervisor only access or a 0 to select User access e Controlling the GPIB 1014 LED SYSFAIL indicator If this bit SFL is a 0 the VMEbus SYSFAIL line is driven low with an AS756 open collector driver and the LED on the GPIB 1014 turns red Writing a 1 to this bit releases the VMEbus SYSFAIL line and turns the LED green This bit is set to 0 on SYSRESET and is unaffected by a local master reset LMR Timing State Machine The Timing State Machine circuitry is designed to control the timing of local signal LOCAL DTACK in slave cycles and the RD and WR signals which control the TLC in slave and DMA cycles A 74LS74A flip flop two 74LS393 4 bit counters a 748139 decoder and some miscellaneous logic gates are used to implement a state machine to control this timing Slave Cycles If the GPIB 1014 is functioning as a VMEbus slave and the DMAC has been addressed the VMEbus signal DTACK is driven by the DMAC and the timing is controlled entirely by the DMAC If the TLC or one of the Configuration Registers has been addressed however the timing is controlled by
190. m Hitachi and Motorola technical data Initialization On power up the VMEbus system typically issues a system reset SYSRESET that drives the GPIB 1014 RESET signal active This action clears both Configuration Registers and initializes the following circuitry e Timing State Machine DMA Gating and Control e GPIB Synchronization and Interrupt Control e Interrupter e DTB Requester e uPD7210 TLC 68450 DMAC The GPIB 1014 also has another method for initializing the circuitry on the card If the Local Master Reset LMR bit in Configuration Register 2 is set the RESET signal is driven and the GPIB 1014 is initialized in the same manner The NEC uPD7210 Talker Listener Controller TLC integrated circuit is initialized as follows e The local message pon is set and the interface functions are placed in their idle states SIDS AIDS TIDS SPIS TPIS LIDS LPIS NPRS LOCS PPIS PUCS CIDS SRIS SIIS e All bits of the Serial Poll Mode Register SPMR are cleared e The End Or Identify EOI bit is cleared e All bits of the Auxiliary Registers A B and E AUXRA AUXRB and AUXRE are cleared e The Parallel Poll Flag and Request System Control RSC local message are cleared The Internal Clock Register ICR is set to a count of eight National Instruments Corporation 5 1 GPIB 1014 User Manual Programming Considerations Chapter 5 e The Transit Receive Mode 0 TRMO and Transit Receive Mode 1 TRM1 bits in the
191. mation refer to Auxiliary Register B and the Clear Parallel Poll Flags Set Parallel Poll Flags later in this section 2 Ow P 3 1 Parallel Poll Response Bits 3 through 1 PPR bits 3 through 1 designated P 3 1 contain an encoded version of the Parallel Poll response P 3 1 indicate which of the eight DIO lines is asserted during a Parallel Poll equal to N 1 The GPIB 1014 normally drives the GPIB DIO lines using three state drivers During Parallel Poll responses however the drivers automatically convert to Open Collector mode as required by IEEE 488 For example if P 3 1 010 binary GPIB DIO line DIO3 is driven low asserted if the GPIB 1014 is parallel polled and S ist Table 4 6 contains some examples of configuring the Parallel Poll Register Table 4 6 Examples for Configuring the PPR Written to the AUXMR 7 6 54 3 2 1 Of Result O 0 0 0 Unconfigures PPR 00000 is written to the PPR The GPIB 1014D participates in a Parallel Poll asserting the DIOI line if ist 0 Otherwise the GPIB 1014D does not participate 01001 is written to the PPR The GPIB 1014D participates in a Parallel Poll asserting the DIO2 line if ist 1 Otherwise the GPIB 1014D does not participate GPIB 1014 User Manual 4 56 National Instruments Corporation Chapter 4 Register Descriptions Auxiliary Register A AUXRA VMEbus Address Base Address 11B hex AUXMR Control Code 100 Binary Bits 7 5 Attributes Write Only Interna
192. memory write use the Carry Cycle feature Addresses 3000 to 300E are used for this test other locations may be used if required National Instruments Corporation 7 7 GPIB 1014 User Manual Diagnostic and Troubleshooting Test Procedures 3000 3002 3004 3006 3008 300A 300C 300E 105 105 101 004 044 005 045 006 046 029 00C 00A 069 079 05C 05A 000 040 11B 119 115 047 007 11B 113 111 113 111 000 data 0000 data 0081 data 0000 data 3003 data 0001 data 0000 data 3002 data 0002 CFG2 0A CFG2 08 CFG1 1D DCRO AO DCRI AO OCRO 82 OCR1 8A SCRO 04 SCR1 04 MFCO 06 MARO 00003000 MTCO 0002 MFC1 06 BFC1 06 BARI 00003004 BTC1 0002 CSRO FF CSR1 FF AUXMR 2 ADMR CO IMR2 10 CCRI 80 CCRO 80 AUXMR 0 ISR1 2 DIR 1 ISR1 2 DIR 22 CSRO 81 GPIB 1014 User Manual Chapter 7 clear two memory locations these will be written over by data from GPIB clear memory location 3002 as it will be written over and put carry cycle byte 81 2 HLDA in location 3003 define carry cycle array s first entry 4 byte address of carry cycle byte 00003003 first entry s transfer count 0001 define carry cycle array s second entry 4 byte address of last data byte 00003002 second entry s transfer count 0002 Set LMR and turn LED green Clear LMR BRG3 IN CC enable ROR feature Configure DMAC 4 byte address
193. ment eere re riali reina 1 3 y Sure eU DR TEN 1 4 Chapter 2 General Description rsa alalslalease tale 2 1 Electrical Cliaracteristies 2 oin eee er ail 2 1 VMEbus Characteristic Sesoni ei OR eet ees et ii uuum ut uci Rete 2 2 VMEbus Slave Addressmg i ara 2 2 VMBbus SlavesD dbi sn eoe oie ade dealer 2 3 VMEbus Master Direct Memory Access ii 2 5 js sstrersteet RM TR 2 6 Data Transfer Bus DTB Requester irritati 2 7 VMEbus Modules Not Provided uiae ensi ette oec nene ua eeu te 2 7 Diagnostic AGS sacs oM UT ered voa I ct isse eatis e satu E sue 2 7 Data Lransfer Eeablutes save em bite raro lieta ne 2 7 Programmed VO Trans ters 2 eoe eto plain 2 8 GPIB 1014 Functional DesctiptiOn usi eus eerte meae cenare dent tp d radica 2 8 Chapter 3 Configuration and Installation sees 3 1 Conf SULA OM m 3 1 YRC COSS IM OU PED rs 3 3 Base Ad tess edere dee dique aid oa conte ocd 3 3 Set Base Address Using Jumper Block W1 sess 3 4 Set Base Address Using Compare Address Lines 3 4 DMA Address Modifier Code Output eese nee 3 5 Other Configuration Parameters ol est resecnd te adds d desc gelo iuoda 3 7 installano dalai iaia 3 7 Verification of System Compatibility essere 3 7 Cablinig scuola 3 10 Verification TSG zar m 3 10 Chapter 4 Register Bit
194. ments written to the right of each test step briefly describe the action taken and sometimes suggest the purpose The test procedures are designed to check the most elemental levels of functioning first and then progress to tests of higher complexity For this reason users are advised to perform the tests in the order given If the GPIB 1014 does not perform as described in the test procedures users are advised to carefully perform the following steps 1 Verify that the test instructions have been followed correctly National Instruments Corporation 7 1 GPIB 1014 User Manual Diagnostic and Troubleshooting Test Procedures 2 Examine any read and write routines being used in connection with the checkout procedure for errors 3 Recheck the jumper settings described in Chapter 3 After these items have been carefully checked if the interface is still not functioning properly gather together the information concerning what the GPIB 1014 is and is not doing with regard to the expected results and contact National Instruments GPIB 1014 Hardware Installation Tests 1 Initialize TLC 105 CFG2 0A Set LMR and turn the LED green 105 CFG2 08 Clear LMR 11B AUXMR 2 TLC Reset 11B AUXMR 0 Immediate execute pon 2 Send LMR then read registers and compare to reset values 105 CFG2 0A Set LMR and turn LED green 105 CFG2 08 Clear LMR 111 DIR 0 cleared 113 ISR1 0 115 ISR2 0 117 SPSR 0 119 ADSR
195. modules not provided 2 7 data transfer features See also DMA data transfers programmed I O transfers 2 8 throughput 2 7 to 2 8 DAV data valid signal E 3 DCL Device Clear command 4 25 DCR See Device Control Register DCR DEC Device Clear Bit 4 11 DEC IE Device Clear Interrupt Enable Bit 4 11 DET Device Execute Trigger Bit 4 10 DET IE Device Execute Trigger Interrupt Enable Bit 4 10 Device Address Register DAR 4 48 Device Control Register DCR 4 51 to 4 52 DHDC DAC Holdoff on DCAS Bit 4 41 DHDT DAC Holdoff on DTAS Bit 4 41 DI 7 0 Data In Bits 7 through 0 4 6 DI Data In Bit 4 12 to 4 13 DI IE Data In Interrupt Enable Bit 4 12 to 4 13 DIR See Data In Register DIR DIR Direction Bit 4 53 4 65 Disable System Control command codes for 4 28 description 4 32 DL Disable Listener Bit 4 43 DLO Disable Listener 0 Bit 4 42 DLI Disable Listener 1 Bit 4 44 DMA address modifier code output configuration 3 5 to 3 7 default settings of AM code jumpers W3 W4 and W5 3 5 programming values for default settings W3 W4 and W5 3 6 setting AM code bits AM5 AMO 3 6 DMA cycles Timing State Machine 6 7 DMA data transfers Dual Address Transfers 6 16 overview 5 8 to 5 9 polling during DMAs 5 17 sending END or EOS 5 17 Single Addressing Mode 6 16 terminating on END or EOS 5 19 terminating transfer and checking results 5 17 to 5 19 theory of operation 6 16 VMEbus interface 6 1 with car
196. mory This bit is cleared to 0 transfer from system memory to GPIB after power up or reset National Instruments Corporation 4 65 GPIB 1014 User Manual Register Descriptions Chapter 4 Configuration Register 2 CFG2 VMEbus Address Base Address 105 hex Attributes Write Only Internal to DMAC 7 6 5 4 3 2 1 0 ee CHEN W Configuration Register 2 CFG2 is an 8 bit write only register that is used to set the board access mode set the GPIB 1014 as System Controller and drive the VMEbus SYSFAIL line It also contains a Local Master Reset bit that can be used to reset the GPIB 1014 to a known state Bit Mnemonic Description 7 4w 0 Reserved Bits Write zeros to these bits 3w SFL System Fail Bit This board specific bit is used to drive the VMEbus SYSFAIL line and to control the color of the LED on the board On power up this bit is cleared the LED is red and the board drives the SYSFAIL line active Setting this bit to a 1 turns the LED green and releases the SYSFAIL line This bit is not cleared by a Local Master Reset O LED red SYSFAIL is driven active 1 LED green SYSFAIL is not driven active 2w SUP Supervisor Bit The Supervisor bit is used to select Supervisor Only or Supervisor and User access to the board A jumper is provided on the board to automatically select the value of this bit after power up or a system reset 0 1 Supervisor and User access to the board Supervisor Only access to th
197. n E 7 GPIB 1014 User Manual Appendix F Mnemonics Key This appendix contains a mnemonics key that defines the mnemonics abbreviations used throughout this manual for functions remote messages local messages states bits registers integrated circuits system functions and VMEbus operations and signals The mnemonic types in the key that follows are abbreviated to mean the following Bit Function Integrated Circuit GPIB Signal Local Message Local Signal Register Remote Message System Function State VMEbus Operation VMEbus Signal National Instruments Corporation GPIB 1014 User Manual Mnemonics Key Mnemonic A A 01 31 ACDS ACFAIL ACG ACK ACRS ACT AD 5 1 AD 5 0 1 0 AD 5 1 1 1 ADCS ADCS IE ADM 1 0 ADMR ADO ADR ADRO ADRI ADSC ADSC IE ADSR AH AIDS AM 0 5 ANRS APRS APT APT IE ARS AS ATN ATN AUXMR AUXRA AUXRB AUXRE AWNS B BBSY BCLR BERR BG 0 3 IN VBS VBS VBS VBS GPIB 1014 User Manual Appendix F Definition Address Lines 1 through 31 Acceptor Data State AH function Power Fail Signal Addressed Command Group DMA Acknowledge Signal Acceptor Ready State Channel Active Bit Talker Listener Controller TLC GPIB Address Bits 5 through 1 Mode 2 Primary TLC GPIB Address Bits 5 through 1 Mode 2 Secondary TLC GPIB Address Bits 5 through 1 Addressed Status Change Bit Enable Interrupt on Addressed Status Change Bit Address Mode Bits 1 through
198. n reading other registers to confirm that the functions were implemented A user must have available an appropriate mechanism for writing to and reading from I O and memory locations A program such as an interactive control program console emulator monitor or program debugger is ideal for this purpose DMA tests 11 through 14 can be done without using an external GPIB device Note Most operations in the test are 8 bits read and write Some registers inside the DMAC are 8 and 16 bits To access these users can use 8 or 16 bit R W operations to consecutive memory accesses Interpreting Test Procedures The following test procedures are written in the form of simple equations The left side of the equation contains the hexadecimal address offset from the GPIB 1014 base address and mnemonic for the register The right side of the equation contains a hexadecimal value Converting the hex value to binary results in a representation of the bit pattern in the register For example a hex value of FF corresponds to a bit pattern of 11111111 40 hex corresponds to a bit pattern of 01000000 Equations not followed by a question mark are instructions to the user to load the value shown into the designated register Equations followed by a question mark are instructions to the user to read the register and verify that the value in the register is the one indicated The column to the left of each test step contains the relative register address Com
199. ne of two states Remote State REMS or Remote With Lockout State RWLS The TLC RL function transfers to one of these states when the System Controller has asserted the Remote Enable line REN and the CIC addresses the TLC as a Listener DMA Input Enable Bit The DMAO bit must be set to allow data transfers from the DIR to VMEbus memory DI IE must be clear DMAI must be set and the TLC must be an active GPIB Listener when a DMA in operation is initiated If DMAI is set the DI condition causes a data transfer request rather than an interrupt request Command Out Bit Command Out Interrupt Enable Bit CO is set when CACS amp SGNS becomes true CO is cleared by read ISR2 CACS SGNS Notes CACS GPIB Controller Active State SGNS GPIB Source Generate State read ISR2 Bit is cleared immediately after it is read CO 1 indicates that the CDOR is empty and that another command can be written to it for transmission over the GPIB without overwriting a previous command 4 16 National Instruments Corporation Bit 2r 2w lr lw Or Ow Mnemonic LOKC LOKC IE REMC REMC IE ADSC ADSC IE Description Lockout Change Bit Lockout Change Interrupt Enable Bit LOKC is set by any change in LOK LOKC is cleared by pon read ISR2 Notes LOK ISR2 5 r pon Power On Reset read ISR2 Bit is cleared immediately after it is read LOKC is set when there is a change in the LOK bit ISR2 5 r REMS R
200. ning load the MFCR of Channel 0 with the proper data to generate the required Address Modifier Code to access the data blocks See Tables 3 1 and 3 2 for recommended values Setup the data blocks and the address amp transfer count array in VMEbus memory The total number of bytes in the data block should be n bytes Figures 6 1 and 6 2 describe how to set up the array for both chaining modes Finally interrupts are generally not enabled in Channel 0 The CPR NIVR DAR DFCR and EIVR of Channel 0 are generally not used 3 Channel 1 is used to control the interrupts from the board and to implement the carry cycle feature A carry cycle array is constructed in memory Chaining is used to transfer the array The carry cycle array is just an address amp transfer count array that is an array of pointers that point to the data blocks to be transferred The procedure for configuring Channel 1 is as follows a Write to the CCR of Channel with the SAB bit set to abort the channel operation in case it is still active Write OxFF hex to the CSR of Channel 1 to clear any leftover error or status bits Load the DCR of Channel 1 with the proper value to select the DMA transfer mode cycle steal without hold or cycle steal with hold Set the DTYP bits to 10 device with ACK implicitly addressed set the DPS bit to 0 8 bit port size and set the PCL bits to 00 status input or 01 status input with interrupt If the cycle steal wi
201. nnel 0 but enabled on Channel 1 The GPIB becoming synchronized however causes a negative transition on the PCL 1 requesting an interrupt Before another DMA transfer with the carry cycle is attempted Channel 1 must be stopped by issuing a software abort by writing to the CCR with the SAB set After the last byte in a DMA transfer has been transferred to or from the TLC writing any value to CFGI clears the circuitry which detects GPIB synchronization If GPIB synchronization has already been detected writing to CFGI pulls the PCL high Regardless of whether the carry cycle feature was used after a DMA transfer has completed the following actions must be taken in the order shown 1 Read ISR2 ISR2 must be read before reading ISR1 2 Read ISRI 3 Clear IMRI National Instruments Corporation 6 15 GPIB 1014 User Manual Theory of Operation Chapter 6 4 Clear IMR2 5 Write a value to CFGI to release PCL line perhaps use the same value as the last write to CFGI 6 Write a software abort to Channel 0 7 Check then clear the COC and ERR bits in CSRO 8 Write a software abort to Channel 1 if a carry cycle is used 9 Check then clear the PCT and ERR bits in CSRI The third step can cause a transition on the PCLI if the VMEbus BERR line is driven low while the DMAC is bus master indicating that the cycle cannot be completed This condition causes the DMAC BEC 1 line to go low which causes the DMAC to terminate t
202. nput Bit Service Request Input Interrupt Enable Bit SRQI is set when CIC amp SRQ amp RQS amp DAV becomes true or CIC amp SRQ amp RQS amp DAV becomes true SRQI is cleared by pon read ISR2 Notes CIC GPIB Controller In Charge SRQ GPIB Service Request message RQS GPIB Request Service message DAV GPIB Data Valid message pon Power On Reset read ISR2 Bit is cleared immediately after it is read The SRQI bit indicates that a GPIB Service Request SRQ message has been received while the TLC function is active CIC 1 Note The set SRQI equation only applies to situations in which two or more devices are issuing the SRQ message Register Bit Descriptions Bit 5r 5w 4r 4w 3r Mnemonic LOK DMAO REM DMAI CO CO IE GPIB 1014 User Manual Chapter 4 Description Lockout Bit LOK is used along with the REM bit to indicate the status of the TLC GPIB Remote Local RL function If set the LOK bit indicates that the TLC is in Local With Lockout State LWLS or Remote With Lockout State RWLS LOK is a Non Interrupt bit DMA Out Enable Bit The DMAO bit must be set to allow data transfers from VMEbus memory to the CDOR DO IE must be clear DMAO must be set and the TLC must be the active GPIB Talker when a DMAO bit is set the DO condition causes a data transfer request rather than an interrupt request Remote Bit This bit is true when the TLC GPIB RL function is in o
203. nsfer Counter Register Memory Function Code Register Device Address Register DAR 32 bits Device Function Code Register DFCR 8 bits Base Address Register Base Transfer Counter Register Base Function Code Register Channel Status Register Channel Error Register Device Control Register Operation Control Register Sequence Control Register Channel Control Register Channel Priority Register Normal Interrupt Vector Register NIVR 8 bits Error Interrupt Vector Register EIVR 8 bits The register set for each channel is addressed relative to the base address of the GPIB 1014 as outlined in Table 2 2 Figure 4 3 shows the DMA registers in order of their register offset Figure 4 3 is reprinted with permission of the copyright owner from the Motorola MC68440 Dual Channel Direct Memory Access Controller Advance Information February 1984 Edition p 3 20 Copyright 1984 Motorola Inc GPIB 1014 User Manual 4 46 National Instruments Corporation Chapter 4 Register Descriptions Key L Null Bit Position The GCR is located at FF only Channel Register Register Base Offset 15 0 Offset CHO 00 00 CHI 40 02 CH2 80 04 CH3 CO 22 24 26 28 2A 26 2E 30 32 34 36 38 3A 3C 3E Note The Register Address equals the Channel Base plus the Register Offset Reprinted from the Motorola MC68440 Advance Information manual Figure 4 3 DMA Register Memory Map National Instruments Corporation 4 47 GPIB
204. nts Corporation Chapter 2 General Description Receive control e Pass control Conduct a Parallel Poll Take control synchronously or asynchronously Table 2 6 contains the GPIB 1014 IEEE 1014 compliance levels Table 2 6 GPIB 1014 IEEE 1014 Interrupter Compliance Levels Bus Slave Compliance Levels D8 O 8 bit data path to TLC and two Configuration Registers D16 amp D8 EO 8 or 16 bit data path to DMAC registers A16 Responds to 16 bit short I O addresses when specified on the address modifier lines ADO Accommodate Address Only cycles Interrupter Compliance Levels D8 O Provides an 8 bit status ID byte on D00 D07 RORA Releases its interrupt request line when an onboard register is accessed Bus Master Compliance Levels D8 EO 8 bit data path for GPIB DMA transfers D16 amp D8 EO 8 or 16 bit memory to memory DMA transfers A24 24 bit memory address path DTB Requester Compliance Level ROR Programmable Release on Request Feature National Instruments Corporation 2 15 GPIB 1014 User Manual Chapter 3 Configuration and Installation This chapter describes the steps needed to configure and install the GPIB 1014 hardware Configuration Before installing the GPIB 1014 in the VMEbus backplane the following options must be configured with hardware jumpers that are located on the GPIB 1014 interface board e Access Mode jumper W2 Base Address jumper block W1 DMA Address Modifier AM Code Output
205. nual If the equipment does cause interference to radio or television reception which can be determined by turning the equipment on and off one or more of the following suggestions may reduce or eliminate the problem e Operate the equipment and the receiver on different branches of your AC electrical system e Move the equipment away from the receiver with which it is interfering e Reorient or relocate the receiver s antenna e Be sure that the equipment is plugged into a grounded outlet and that the grounding has not been defeated with a cheater plug Notice to user Changes or modifications not expressly approved by National Instruments could void the user s authority to operate the equipment under the FCC Rules If necessary consult National Instruments or an experienced radio television technician for additional suggestions The following booklet prepared by the FCC may also be helpful How to Identify and Resolve Radio TV Interference Problems This booklet is available from the U S Government Printing Office Washington DC 20402 Stock Number 004 000 00345 4 Contents About This Manual oe eat biases edibus MN aA xiii Orsamzaton of ThissManval scssn iris qutm id UR etx uiua o aa ede pole xiii Conventions Used m This Manual pollaio xiv Related Documentation rateale xiv Customer C mmu mcati OR celere XV Chapter 1 Intiwducuon areale 1 1 What Your Kit Should COBGBE o de rici een lina elena ira 1 3 Optional Equip
206. o 6 24 initialization of 5 1 to 5 2 operation of E 1 to E 2 overview 5 6 programmed implementation 5 6 sending receiving messages DMA transfers with carry cycle 5 13 to 5 17 DMA transfers without carry cycle 5 10 to 5 12 polling during DMAs 5 17 sending and receiving data 5 19 to 5 20 sending END or EOS 5 17 5 20 terminating on END or EOS 5 19 5 20 terminating transfer and checking results 5 17 to 5 19 using direct memory access 5 8 to 5 19 using programmed I O 5 19 to 5 20 VMEbus slave addressing 2 2 to 2 3 TCT Take Control command 4 25 Technical support vii test and troubleshooting See troubleshooting test procedures theory of operation 68450 DMAC block termination 6 19 to 6 22 DMAC channel operation 6 15 to 6 18 initialization and transfer phases 6 15 to 6 18 initiation and control of channel operation 6 18 to 6 19 overview 6 14 address decoding 6 3 to 6 4 clock and reset circuitry 6 4 Configuration Register 1 6 5 Configuration Register 2 6 6 DMA gating and control 6 7 to 6 8 DTB Requester and Controller 6 9 to 6 12 GPIB interface 6 23 to 6 24 GPIB Synchronization and Interrupt Control 6 12 to 6 14 interrupter 6 9 test and troubleshooting 6 24 Timing State Machine DMA cycles 6 7 slave cycles 6 6 to 6 7 VMEbus interface 6 1 to 6 3 Timing State Machine GPIB 1014 User Manual Index 19 National Instruments Corporation Index definition of 2 12 theory of operation DMA cycles 6 7 overv
207. of the first two data bytes two data bytes 4 byte address of the carry cycle array carry cycle array has two entries two small memory blocks to be transferred TLC Reset ton lon DMA in enable start channel 1 start channel 0 Immediate execute pon check if DI is cleared before write data byte to DIR write first data byte to TLC since DIR is full TLC will request for a DMA transfer to put the byte in DIR to memory after transferred the first data byte check if DI is cleared before write second byte to DIR write second data byte to TLC since DIR is full TLC will request for a DMA transfer to put the byte in DIR to memory channel 0 finished COC 7 8 National Instruments Corporation Chapter 7 113 111 04A 040 047 040 3000 3001 3002 ISR1 22 DIR 3 MTC1 0001 CSRI 0A CCRI 10 CSR1 FF data 01 data 02 data 03 National Instruments Corporation Diagnostic and Troubleshooting Test Procedures after transferred the first two bytes on Channel 0 and the carry cycle byte on Channel 1 check if DI is cleared before write the last data byte to DIR write the last data byte to TLC since DIR is full TLC will request for a DMA transfer to put the byte in DIR to memory count of 1 indicates last data byte has been transferred GPIB synchronized software abort check the first data byte that was transferred from TLC to memory check second data byte check last data byte Not
208. off The continuous mode is useful for monitoring the data block transfer without actually participating in the transfer no data reception In continuous mode the DI bit ISR1 0 r is not set by the reception of a data byte GPIB 1014 User Manual 4 56 National Instruments Corporation Chapter 4 Register Descriptions Auxiliary Register B AUXRB VMEbus Address Base Address 11B hex AUXMR Control Code 101 Binary Bits 7 5 Attributes Write Only Internal to TLC Accessed through AUXMR 4 3 2 1 0 CPT INV ss mw m SA ENABLE W Writing to Auxiliary Register B AUXRB is done via the AUXMR Writing the value 101 into the Control Code CNT 2 0 and a bit pattern into the Command Code portion COM 4 0 of the AUXMR causes the Command Code to be written to AUXRB When the data is written to AUXRB the bits are denoted as shown in the figure above This 5 bit code affects several interface functions as described in the following paragraphs Bit Mnemonic Description 4w ISS Individual Status Select Bit The ISS bit determines the value of the TLC ist message When ISS 1 ist becomes the same value as the TLC Service Request State SRQS The TLC is asserting the GPIB SRQ message when it is in SRQS When ISS 0 ist takes on the value of the TLC Parallel Poll Flag The Parallel Poll Flag is set and cleared using the Set Parallel Poll Flag and Clear Parallel Poll Flag auxiliary commands 3w INV Invert Bit The INV bit af
209. ograms Comments movb movb movb addw bsr movb movb movw movl bsr movb READ1 btst bne subw bsr movb rts cmdbuf cmdbuf 2 UNT cmdbuf UNL cmdbuf 1 2 cmdct CMD LTN AUXMR GTS AUXMR datct d0 datbuf a0 RCV TCS AUXMR NATN ADSR READ1 1 cmdct CMD LUN AUXMR National Instruments Corporation Put Untalk and Unlisten commands before Talker address in the buffer Command routine will address the Talker Program GPIB 1014 to be a Listener so it can take control synchronously later then go to standby and drop ATN Preset dO register with byte count Preset a0 register with buffer address Receive routine will read data Take control Wait for ATN indefinitely Unaddress all Talkers and Listeners using CMD Send Local Unlisten command C 13 GPIB 1014 User Manual Sample Programs GPIB 1014 User Manual Appendix C KR KKK KKK KKK ok ok ok KKK DATA SEND DSEND KR RK KKK ko ko ko k ok ok ok k kk Summary Called directly from the main program if the GPIB 1014 is not CIC Assumptions on entry The GPIB 1014 is Standby or Idle Controller GPIB 1014 is or will be addressed to talk If the GPIB 1014 is Idle Controller the current CIC will go to standby The dO register contains the byte count The a0 register contains the address of the data buffer The user specified variable veoi has been set properly Act
210. ons In Figure 6 1 BR is asserted by the DMAC to request the use of the VMEbus BGIN is asserted by the DTB Requester and Controller circuitry when a correct bus grant signal is National Instruments Corporation 6 11 GPIB 1014 User Manual Theory of Operation Chapter 6 received OWN is asserted by the DMAC to indicate that it now has ownership of the bus BUS REL is asserted by the DTB Requester and Controller circuitry to indicate that it is going to release the VMEbus RESET is asserted to reset all circuitry on the board Based on the output of the flip flops there are numerous combinational outputs The following equations contain these outputs Equation 1 LBROUT Q3 QI Equation 2 BG BUS REL amp Q1 amp MY BGIN OWNBUS Equation3 BGACK BBSY BGIN Equation 4 BGMATCH Q2 amp BGIN Equation 5 OWNBUS Q3 BBSY Q3 Equation 6 BUS REL ROR BRIN amp LBROUT amp OWN amp BR amp DEN amp BGIN In Equation 1 combinational output LBROUT is asserted if DMAC has a bus request pending and the board does not have control of the VMEbus While the GPIB 1014 is holding the bus and there is a request from the DMAC LBROUT and thus BGIN will not be asserted BG an input to the DMAC is asserted to inform the DMAC that it has been granted the bus Even with its BG asserted the DMAC will not assert OWN and start DMA cycle until BGACK is released unasserted Equation 3 in
211. ontrol CNT 2 0 set to 000 binary Represents all eight bits of the Auxiliary Mode Register 0 0 m C gt Ne 10000 CS 1 1 1 1 or 1 10100 GPIB 1014 User Manual 4 28 National Instruments Corporation Table 4 5 shows the functions that are executed when the AUXMR Control Code CNT2 through CNTO is loaded with 000 binary and the Command Code COMA through COMO is loaded Table 4 5 Auxiliary Commands Detail Description Command Code COM4 COM0 43210 Description Immediate Execute Pon This command generates a local pon message that places the following GPIB interface functions into these idle states AIDS Acceptor Idle State CIDS Controller Idle State LIDS Listener Idle State LOCS Local State LPIS Listener Primary Idle State NPRS Negative Poll Response State PPIS Parallel Poll Idle State PUCS Parallel Poll to Unaddressed to Configure State SIDS Source Idle State SUS System Control Interface Clear Idle State SPIS Serial Poll Idle State SRIS System Control Remote Enable Idle State TIDS Talker Idle State TPIS Talker Primary Idle State If the command is sent while a pon message is already active by either an external reset pulse or the Chip Reset auxiliary command the local pon message becomes false Chip Reset The Chip Reset command resets the TLC in the same way as an external reset pulse The System Controller bit is also cleared The TLC is reset to t
212. or A write to an unused location results in a normal bus cycle but no write occurs Like a read DMAC asserts DTACK to prevent a bus error When the GPIB 1014 has been addressed VMEbus address line A8 is a logic 1 A4 is a logic 1 the lower data strobe DSO is active and the TLC select signal TLCCS is driven active indicating that the TLC has been addressed Address lines A3 through Al are used to select the internal registers of the TLC These lines are gated with the onboard signal CCBYTE and are connected to the TLC register select lines RS2 through RSO The TLC functions as an 8 bit slave It transfers data on the lower eight bits of the VMEbus data bus The TLC registers are located at consecutive odd addresses and respond only when DSO is asserted The TLC responds to 16 bit transfers but the upper data byte is not used during an I O write and returns all ones during an I O read As described in the DMA Gating and Control section signal CCBYTE forces a write cycle to the Auxiliary Mode Register inside the TLC when it is asserted When the GPIB 1014 has been addressed VMEbus address line A8 is a logic 1 A4 is a logic 0 A2 is a logic 0 and Configuration Register 1 is addressed When A8 is a logic 1 A4 is a logic 0 A2 is a logic 1 and Configuration Register 2 is addressed These 8 bit registers respond only to I O write operations write only and are loaded via the lower eight data lines They can be accessed with an 8 or 16 bit I O
213. or communication functions GPIB 1014 User Manual 2 8 National Instruments Corporation Chapter 2 General Description Device A VMEbus Computer with GPIB 1014 Able to Talk Listen and Control Frequency Counter Able to Talk Device B Printer Able to Listen Device C Digital Voltmeter Able to Talk Data Lines and Listen DIO1 DIO8 Handshake Lines DAV Data Valid NRFD Not Ready for Data NDAC Not Data Accepted Management Lines IFC Interface Clear ATN Attention SRQ Service Request REN Remote Enable EOI End or Identify Figure 2 1 GPIB 1014 with a VMEbus Computer National Instruments Corporation 2 9 GPIB 1014 User Manual General Description Chapter 2 R amp D Lab s Microprocessor Work Station TT m o EBB EE EES ES VMEbus Computer with IBM PC with GPIB PC GPIB 1014 IEEE 488 Interface IEEE 488 Interface o GPIB 100 Bus Extender Up to 300 Meters RS 422 Computer Center GPIB 100 Bus Extender Production amp Testing PDP 11 44 with GPIB11 2 S 100 Computer IEEE 488 Interface GPIB 696P IEEE 488 Interface Figure 2 2 GPIB 1014 in a Multiprocessor Application GPIB 1014 User Manual 2 10 National Instruments Corporation General Description Figure 2 3 is a block diagram of the GPIB 1014 Chapter 2 AIII PS pue Jooo NU rcp Ej SZ 01u07 3dnirojug pue uonezruodjouAg ald Ja sonbay aLa SZ 0 3u0 pue Suneo YWA
214. orm as a reference for your current configuration National Instruments Products NI 488M Software Version Number on Distribution Medium e National Instruments board installed GPIB 1014 GPIB 1014D GPIB 1014P or GPIB 1014DP e GPIB 1014 Revision e Hardware Settings Base I O Interrupt Request DMA Address Line Channel Ist GPIB 1014 2nd GPIB 1014 e Software Settings Base I O Interrupt Vector DMA Address Number Channel gpib0 gpibl Other Products e Application Programming Language Version e Computer Make and Model e Microprocessor e Clock Frequency e Type of Video Board Installed e Type of other boards installed and their respective hardware settings Base I O Interrupt DMA Board Type Address Level Channel Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title GPIB 1014 User Manual Edition Date March 1997 Part Number 370945A 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone Mail to Technical Publications Fax to Technical Publications National Instr
215. outed to a pin PCL1 on the DMAC If enabled for interrupt the assertion of any of these three signals sets the pin and the DMAC asserts an interrupt request line on the VMEbus Thus you can set up and start the DMA transfer then simply wait for a GPIB synchronization interrupt if interrupts are not enabled polling is possible This indicates n bytes have been transferred and the GPIB handshake is synchronized National Instruments Corporation 5 9 GPIB 1014 User Manual Programming Considerations Chapter 5 DMA Transfers without the Carry Cycle VMEbus Data interrupt Block A Data TLC interrupt Block B Bus Error GPIB Sync Data Block C Total N bytes Total N bytes NO CHAINING CHAINING Figure 5 1 DMA Transfer without Carry Cycle If the carry cycle feature is not needed in a transfer sequence little programming is needed Channel 0 is used to transfer the entire block of data since the carry cycle byte does not need to be inserted before the last data byte Channel 1 DMA is not used and must not be started As indicated in Figure 5 1 depending upon the number of data blocks to be transferred you can use no chaining or chaining mode If interrupts are enabled on Channel 1 the TLC can interrupt the processor on the VMEbus system on one of 13 GPIB events Similarly if BERR occurs during a DMA transfer the processor is also interrupted When the GPIB handshake is synchronized the system is also interrupted and you can
216. owing characteristics of the code must be considered Standard 24 bit DMA memory addressing is used e The GPIB 1014 base address is FF2000 hex e Normal non extended GPIB addressing is used e Timeout on subroutine calls is not implemented Register values are not saved on subroutine calls e Program interrupt is not used status checking is by register polling e Constants and variables listed in the User Specified Constants section of the listings must be initialized to correct values e In operands containing expressions is used in place of logical OR for convenience An arithmetic addition yields the same result in the instances used here National Instruments Corporation C 1 GPIB 1014 User Manual Sample Programs BASE DIR CDOR ISR1 IMR1 ISR2 IMR2 SPSR SPMR ADSR ADMR CPTR AUXMR ADRO ADR ADR1 EOSR MTCO MARO MFCO CSRO DCRO OCRO SCRO CCRO MTC1 MAR1 MFC1 BTC1 BAR1 BFC1 CSR1 DCR1 OCR1 SCR1 CCRI CFG1 CFG2 OxFF2000 BASE 0x111 BASE 0x111 BASE 0x113 BASE 0x113 BASE 0x115 BASE 0x115 BASE 0x117 BASE 0x117 BASE 0x119 BASE 0x119 BASE 0x11B BASE 0x11B BASE 0x11D BASE 0x11D BASE 0x11F BASE 0x11F BASE 0x00A BASE 0x00C BASE 0x029 BASE 0x000 BASE 0x004 BASE 0x005 BASE 0x006 BASE 0x007 BASE 0x04A BASE 0x04C BASE 0x069 BASE 0x05A BASE 0x05C BASE 0x079 BASE 0x040 BASE 0x044 BASE 0x045 BASE 0x046 BASE 0x047 B
217. pecified The last four bytes in each entry the link address must be even or the entry fetch results in an address error The middle two bytes the transfer count of the data block must be non zero The first four bytes in each entry the starting address of the data block can be even or odd Altogether the address of first array entry must be even If a terminal count is loaded into the memory transfer counter the count error is signaled While it is not currently implemented in the GPIB 1014 software the linked chaining method could be used on Channel 0 to transfer large data blocks arbitrarily just like array chaining Similarly you can use linked chaining on Channel 1 to implement the carry cycle feature but array chaining is much simpler An example of the array format for linked chaining is shown in Figure 6 3 National Instruments Corporation 6 23 GPIB 1014 User Manual Theory of Operation Chapter 6 Address and Transfer Count Array Data Blocks Memory Address A Data Block Transfer Count A A Data Block Memory Address B Transfer Count B Data Block C Memory Address B Transfer Count B 0000 end link Figure 6 3 Array Format for Linked Chaining Modes Error Conditions When an error is signaled on a channel all activity on that channel is stopped The ACT bit of the CSR is cleared and the COC bit is set The ERR bit of the CSR is also set and the error code is recorded in the CER All pending operations are cl
218. place that is the transfer count is not changing This step is necessary because of a 68450 DMAC bug that can cause the VMEbus to hang If you do not wait for any pending DMA transfer to complete before issuing a SAB as called out in Step 7 below the 68450 may incorrectly remove its bus request before receiving a bus grant intended for it 7 Write a software abort to Channel 0 8 Clear the Status Register of Channel 0 9 Write a software abort to Channel 1 if a carry cycle was used 10 Clear Status Register of Channel 1 to clear any remaining interrupt Terminating on END or EOS The END RX bit in ISR1 is set when a GPIB END message is received The END RX bit is also set when an EOS message is received and the REOS bit of AUXR has been previously set Receipt of the EOS message is determined by the contents of the DIR the EOSR and the value of the BIN bit in the AUXRA The END RX bit in ISR1 may be polled during DMA transfers or if the END IE bit in IMR1 and the EINT bit in CCR Channel 1 are both set a VMEbus interrupt request GPIB IR occurs when END RX gets set National Instruments Corporation 5 19 GPIB 1014 User Manual Programming Considerations Chapter 5 Whether terminating on the END message or the EOS message or whenever the DMA transfer does not complete properly the DMAC must be stopped by issuing a software abort to Channels 0 and 1 by writing to the CCR with the SAB bit set You then must write to the CSR
219. pt the two bits in CFG2 LMR and SYSFAIL the Address Decoding circuitry and the DTACK generation circuitry BRDEN circuitry refer to the Address Decoding section earlier in this chapter The two bits in CFG2 are reset only by the SYSRESET signal or by a write to CFG2 The Address Decoding and DTACK generation circuitry can only be reset by SYSRESET The VMEbus signal BERR is monitored by the GPIB 1014 while it is bus master This signal is received by a 74LS241 receiver and is ANDed with the onboard signal OWN which is active while the GPIB 1014 is bus master If BERR is driven active during a DMA transfer the DMAC input BECI is driven low indicating to the DMAC that the cycle cannot be completed The DMAC responds to this condition by terminating the cycle and indicating a bus error condition in the channel CER Configuration Registers Two registers CFG1 and CFG2 are 8 bit write only registers used by the controlling software program application program and or interface handler to configure some of the operating characteristics of the GPIB 1014 Configuration Register 1 A 74L S273 octal D type flip flop and an LS74A are used to implement Configuration Register 1 CFG1 Data is written into each register on the rising edge of the WR signal generated by the Timing State Machine circuitry Except for the ROR bit all other bits in CFGI are cleared by the onboard RESET signal generated by the Clock and Reset circuitry This w
220. r to meet IEEE 488 requirements you must not issue the Set REN command until REN has been held false for at least 100 usec Disable System Control The Disable System Control command clears the local message rsc and clears the SC bit 4 32 National Instruments Corporation Chapter 4 Register Descriptions Hidden Registers The hidden registers are loaded through the Auxiliary Mode Register AUXMR AUXMR 7 5 is loaded with the hidden register number and AUXMR 4 0 is loaded with the data to be transferred to the hidden register The hidden registers cannot be read and in some cases the contents are setable only that is they can be cleared or reset to initialized conditions only by issuing the Chip Reset auxiliary command by a Power On Reset or by LMR CRO 2 w Figure 4 2 earlier in this chapter shows the five hidden registers and illustrates how they are loaded with data from the AUXMR National Instruments Corporation 4 33 GPIB 1014 User Manual Register Descriptions Chapter 4 Intemal Counter Register ICR VMEbus Address Base Address 11B hex AUXMR Control Code 001 Binary Bits 7 5 Attributes Write Only Internal to TLC Accessed through AUXMR 4 3 2 1 0 Ew CLK3 CLK2 CLKI CLKO W Bit Mnemonic Description 4w 0 Reserved Bit Write zero to this bit 3 0w CLK 3 0 Clock Bits 3 through 0 The contents of the ICR are used to divide internal counters that generate TLC state change delay times used by the IE
221. r Listener or Controller The SC bit of CFG2 when set to a logic one programs the 75162 transceiver to drive or receive the GPIB IFC and REN control lines The data lines are always driven in the 3 state mode unless the TLC receives a parallel poll message ATN and EOI both true at which time the drivers are switched to Open Collector mode Test and Troubleshooting The GPIB 1014 is designed to aid acceptance testing and troubleshooting of either hardware failures or software bugs The hardware provides several features that enable stand alone testing DMA Stand Alone Testing Most of the GPIB 1014 ICs and interconnecting circuitry are associated with implementing the DMA function From the system s point of view the best acceptance test for the interface is one in which DMA data is transferred between the VMEbus memory and a GPIB device Should there be problems associated with implementing this type of test a good troubleshooting tactic is to start removing variables in the system starting with the DMAC itself The GPIB 1014 is designed to perform DMA transfers without needing an external GPIB device This can be implemented using the flowthrough mode of the DMAC to perform memory to memory DMA transfers This feature allows test and verification of the DMAC the DTB Requester the Interrupter and the VMEbus interface Any of the DMAC channels can be configured to transfer a buffer of data from one location in memory to another and the n
222. r EOS 5 19 terminating transfer and checking results 5 17 to 5 19 using programmed I O 5 19 to 5 20 sending and receiving data 5 19 to 5 20 sending END or EOS 5 20 terminating on END or EOS 5 20 Sequence Control Register SCR 4 55 Serial Poll Mode Register SPMR 4 19 Serial Poll Status Register SPSR 4 19 serial polls conducting 5 22 responding to 5 22 Set IFC command codes for 4 28 description 4 32 Set Parallel Poll Flag command codes for 4 28 description 4 31 Set REN command codes for 4 28 description 4 32 SFL System Fail Bit 4 66 SH Source Handshake 4 7 signals and lines data lines E 2 GPIB 1014 pin assignment on VMEbus connector P1 3 8 GPIB 1014 pin assignment on VMEbus connector P2 3 9 GPIB connector and signal assignments illustration E 4 handshake lines DAV data valid E 3 NDAC not data accepted E 3 NRED not ready for data E 2 overview E 2 interface management lines ATN attention E 3 EOI end or identify E 3 IFC interface clear E 3 overview E 3 GPIB 1014 User Manual Index 17 Index National Instruments Corporation Index REN remote enable E 3 SRQ service request E 3 VMEbus signals chart of 2 1 to 2 2 control signals 6 2 operation 6 1 to 6 3 SIZE Size Bits 5 through 4 4 53 slave addressing VMEbus 2 2 to 2 3 slave cycles Timing State Machine 6 6 to 6 7 slave data VMEbus 2 5 slave read and write transfers 6 1 SPD Serial Poll Disable comman
223. r a FIN interrupt issue the Take Control Synchronously auxiliary command followed by the Finish Handshake auxiliary command Case3 The TLC as neither Talker nor Listener takes control synchronously with the Take Control Synchronously auxiliary command Because the Listen in Continuous Mode auxiliary function is active the Take Control Synchronously auxiliary command may be sent at any time When the Take Control Synchronously auxiliary command is used the TLC takes control of the GPIB only at the end of a data transfer This implies that one transfer must follow or be in progress when the Take Control Synchronously auxiliary command is issued If this is not the case the Take Control Asynchronously auxiliary command must be used Of course the Take Control Asynchronously auxiliary command may be used in place of the Take Control Synchronously auxiliary command when the possibility of disrupting an in progress GPIB handshake before all GPIB Listeners have accepted the data byte is acceptable In Cases 2 and 3 above the END IE bit in IMRI can also be set to indicate to the program that the TLC functioning as a GPIB Listener has received its last byte In all cases a CO bit status of 1 indicates that the GPIB 1014 is now Active Controller Going from Active to Idle Controller Going from Active to Idle GPIB Controller also known as passing control requires that the TLC be the Active Controller initially in order to send the necessary G
224. r channels in the DMAC Sample Interval 2BT BR 5 clock cycles Bit Mnemonic Description T 4rlw 0 Reserved Bits 7 through 4 Read write zeros from to these bits 3 2r w BT Burst Transfer Time Bits 3 through 2 00 16 clocks 01 32 clocks 10 64clocks 11 128 clocks 1 0r w BR Bandwidth Available to DMAC Bits 1 through 0 00 50 00 01 25 00 10 12 50 11 6 25 National Instruments Corporation 4 63 GPIB 1014 User Manual Register Descriptions Chapter 4 Configuration Registers The GPIB 1014 contains two 8 bit write only registers that are used to configure some of the board operating parameters Configuration Register 1 CFG1 VMEbus Address Base Address 101 hex Attributes Write Only Internal to DMAC 7 6 3 4 3 2 1 0 W Configuration Register 1 CFG1 is an 8 bit write only register used to configure the GPIB 1014 parameters The register bits define the following operating parameters Bit Mnemonic Description 7 Sw INTRQ Interrupt Request Bits 7 through 5 The interrupt request bits are used to select one of the seven VMEbus interrupt request lines used by the board to request service from the interrupt handler of the CPU 000 No interrupt request line selected 001 Interrupt request line IRQI selected 010 Interrupt request line IRQ2 selected 011 Interrupt request line IRQ3 selected 100 Interrupt request line IRQ4 selected 101 Interrupt request line IRQ5 selected 110 Interrupt requ
225. r of the bits ton or lon are set Mode ADMI ADMO Title 0 0 0 ton lon 1 0 1 Normal dual addressing 2 1 0 Extended single addressing 3 1 1 Extended dual addressing In mode 1 ADRO and ADRI contain the major and minor addresses respectively for dual primary GPIB address applications that is the TLC responds to two GPIB addresses a major address and a minor address The MJMN bit in the ADSR indicates which address was received In applications where the TLC needs to respond to only one address the major Talker and Listener function is used and the minor Talker and Listener function should be disabled The minor Talker and Listener function can be disabled by setting the Disable Talker DT and Disable Listener DL bits in ADRI set ADR and ADRI In mode 2 ADM1 1 ADMO 0 the TLC recognizes two sequential GPIB address bytes a primary followed by a secondary Both GPIB address bytes must be received in order to enable the TLC to talk or listen In this manner mode 2 addressing uses the Extended Talker and Extended Listener functions as defined in IEEE 488 without requiring computer program intervention In mode 2 ADRO and ADRI contain the TLC primary and secondary GPIB addresses respectively In mode 3 ADM1 1 ADMO z 1 the TLC handles addressing just as it does in mode 1 except that each major or minor GPIB primary address must be followed by a secondary address All secondary GPIB addresses must be verified by computer program w
226. rameters 3 7 requirements E 6 Supervisor or Non privileged access 3 3 Configuration Registers Configuration Register 1 CFG1 4 64 to 4 65 Configuration Register 2 CFG2 4 66 to 4 67 definition of 2 12 GPIB 1014 Configuration registers chart 2 5 register map 4 2 theory of operation 6 5 to 6 6 control equations of transceivers 6 3 Controller function becoming controller in charge CIC and active controller 5 3 Controller In Charge CIC and System Controller E 2 going from active to idle 5 5 going from active to standby 5 4 going from standby to active 5 5 operation of E 1 to E 2 sending remote multiline messages commands 5 4 CP Channel Priority Bits 1 through 0 4 61 CPR See Channel Priority Register CPR CPT Command Pass Through Bit 4 8 to 4 9 CPT 7 0 Command Pass Through Bits 7 through 0 4 25 to 4 26 CPT ENABLE Command Pass Through Enable Bit 4 40 CPT IE Command Pass Through Interrupt Enable Bit 4 8 to 4 9 CPTR See Command Pass Through Register CPTR CSR See Channel Status Register CSR Customer support vii D DAC Device Address Count Bits 1 through 0 4 55 DAR See Device Address Register DAR Data In Register DIR 4 6 data lines GPIB signals and lines E 2 National Instruments Corporation Index 4 GPIB 1014 User Manual Index VMEbus 6 3 data or data messages E 1 DATA SEND DSEND sample program C 14 to C 16 data transfer bus DTB requester description of 2 7 VMEbus
227. ration xiii GPIB 1014 User Manual About This Manual Appendix F Mnemonics Key contains a mnemonics key that defines the mnemonics abbreviations used throughout this manual for functions remote messages local messages states bits registers integrated circuits system functions and VMEbus operations and signals Appendix G Customer Communication contains forms for you to complete to facilitate communication with National Instruments concerning our products The Glossary contains an alphabetical list and description of terms used in this manual including abbreviations acronyms metric prefixes and symbols The ndex contains an alphabetical list of key terms and topics used in this manual including the pages where each one can be found Conventions Used in This Manual The following conventions are used to distinguish elements of text throughout this manual italic Italic text denotes emphasis a cross reference or an introduction to a key concept IEEE 488 IEEE 488 is used throughout this manual to refer to the ANSI IEEE Standard 488 1 1987 which defines the GPIB IEEE 1014 IEEE 1014 is used throughout this manual to refer to the ANSI IEEE Standard 1014 1987 which defines the GPIB Related Documentation The following documents contain information that you may find helpful as you read this manual ANSI IEEE Standard 488 1 1987 IEEE Standard Digital Interface for Programmable Instrumentation ANSI IEEE Stand
228. red at the factory Figure 3 3 Configuration for GPIB 1014 Base Address 2000 hex Default Setting Set Base Address Using Compare Address Lines Another method of setting the base address is to use the compare address lines located on the P2 connector The jumpers on jumper block W1 must be removed and TTL compatible voltages must be applied to pins CA9 through CA15 on the P2 connector when using this method Refer to Table 3 4 for the pin assignment numbers of the P2 connector A scrambler card and interface cable assembly described under Cabling later in this chapter available from National Instruments are necessary when setting the base address of the board using this method GPIB 1014 User Manual 3 4 National Instruments Corporation Chapter 3 Configuration and Installation DMA Address Modifier Code Output During a DMA cycle the GPIB 1014 sends out a 6 bit Address Modifier AM code to the VMEbus lines AMS through AMO The correct code is obtained by both programming the DMAC and setting jumpers W3 W4 and W5 Figure 3 4 shows the default settings of W3 W4 and WS Note Because jumper W5 is not located near jumpers W3 and WA Figure 3 4 outlines and labels the components on the GPIB 1014 interface board that are found between jumper WS and the other jumpers Figur
229. registers IMR1 and IMR2 If the TLC detects an interrupt condition it drives its INT pin high This action causes a negative transition on DMAC Channel 1 PCL which sets the PCT status bit and generates an interrupt if interrupts are enabled The interrupt condition can be detected by polling the TLC interrupt status registers Reading from the appropriate status register releases the TLC INT line and enables further interrupts Notice that the TLC must be properly configured in order to present an active high interrupt request output This is accomplished by clearing the INV bit of AUXRB The GPIB synchronization circuitry consists of two LS74A flip flops and various logic gates The circuitry detects GPIB synchronization after the last byte ina DMA transfer has been transferred to or from the TLC This is accomplished by monitoring the DAV line on the GPIB The circuitry begins when the ALLDONE signal becomes high which occurs during the last data byte transfer in the DMA transfer sequence If the carry cycle was not enabled as indicated by the CC bit in CFG1 the last byte is detected by DONE and ACKO which are both active at the same time DMAC asserts DONE when Channel 0 is transferring the last data byte in the last data block in Channel 0 chain ALLDONE is driven high during this time If a carry cycle was enabled and the carry cycle byte was sent as indicated by the flip flop in the DMA Gating circuitry being set the next DMA cycle to tr
230. releases control when TCT is sent Call CMD to send commands C 21 GPIB 1014 User Manual Appendix D Multiline Interface Messages This appendix lists the multiline interface messages and describes the mnemonics and messages that correspond to the interface functions These functions include initializing the bus addressing and unaddressing devices and setting device modes for local or remote programming The multiline interface messages are IEEE 488 defined commands that are sent and received with ATN TRUE For more information on these messages refer to the ANSI IEEE Std 488 1978 IEEE Standard Digital Interface for Programmable Instrumentation National Instruments Corporation D 1 GPIB 1014 User Manual Multiline Interface Messages Appendix D Multiline Interface Messages Hex Oct Dec ASCII Msg Hex Oct Dec ASCII Msg 00 000 0 NUL 20 040 32 SP MLAO 01 001 1 SOH GTL 21 041 33 MLAI 02 002 2 STX 22 042 34 MLA2 03 003 3 ETX 23 043 35 MLA3 04 004 4 EOT SDC 24 044 36 MLA4 05 005 5 ENQ PPC 25 045 37 MLAS 06 006 6 ACK 26 046 38 amp MLA6 07 007 7 BEL 27 047 39 MLA7 08 010 8 BS GET 28 050 40 MLA8 09 011 9 HT TCT 29 051 41 MLA9 0A 012 10 LF 2A 052 42 MLA10 OB 013 11 VT 2B 053 43 MLAII OC 014 12 FF 2C 054 44 MLA12 OD 015 13 CR 2D 055 45 MLA13 OE 016 14 SO 2E 056 46 MLA14 OF 017 15 SI 2F 057 47 MLA15 10 020 16 DLE 30 060 48 0 MLA16 11 021 17 DCI LLO 31 061 49 1 MLA17 12 022 18 DC2 32 062 50 2 MLA18 13
231. require a Controller For example one device may always be a Talker called a Talk only device and there may be one or more Listen only devices A Controller is necessary when the active or addressed Talker or Listener must be changed The Controller function is usually handled by a computer With the GPIB interface board and its software your personal computer plays all three roles Controller to manage the GPIB e Talker to send data e Listener to receive data The Controller In Charge and System Controller Although there can be multiple Controllers on the GPIB only one Controller at a time is active or Controller In Charge CIC Active control can be passed from the current CIC to an idle Controller Only one device on the bus the System Controller can make itself the CIC The GPIB interface board is usually the System Controller GPIB Signals and Lines The interface system consists of 16 signal lines and eight ground return or shield drain lines The 16 signal lines are divided into the following three groups e Eight data lines e Three handshake lines e Five interface management lines Data Lines The eight data lines DIO1 through DIO8 carry both data and command messages All commands and most data use the 7 bit ASCII or ISO code set in which case the eighth bit DIOS is unused or used for parity Handshake Lines Three lines asynchronously control the transfer of message bytes among devices The process is
232. rite only register is used for a variety of configuration functions including the following functions Selecting the VMEbus Interrupt Request Priority for the GPIB 1014 The three most significant bits are used to encode the desired interrupt priority This encoded value is used by the Interrupter circuitry to drive the appropriate VMEbus Interrupt Request line and to identify an interrupt acknowledge cycle of the proper priority Selecting the VMEbus Bus Request Grant line Two bits are used to encode the desired VMEbus Bus Request Grant line This encoded value is used by the DTB Requester and Controller circuitry to drive the appropriate Bus Request line and to monitor the appropriate Bus Grant In line e Enabling the automatic carry cycle feature Writing a 1 to this bit CC enables the carry cycle feature while writing a zero disables the carry cycle feature This bit is used by the DMA Gating and Control circuitry National Instruments Corporation 6 5 GPIB 1014 User Manual Theory of Operation Chapter 6 e Enabling the Release On Request feature Writing a 0 to this bit ROR enables the Release On Request feature while writing a 1 disables the Release On Request feature This bit is set to 1 during reset or power up This bit is used by the DTB Requester circuitry e Selecting the direction of the DMA transfer Writing a 1 to this bit DIR indicates that the transfer direction is from GPIB to VMEbus memory while writing a ze
233. ritten to the PPR prior to the poll Bit Mnemonic Description 4w U Unconfigure Bit The U bit determines whether or not the TLC participates in a Parallel Poll If U 0 the TLC participates in Parallel Polls and responds in the manner defined by PPR 3 through PPR 0 and by ist If Uz1 the TLC does not participate in a Parallel Poll The U bit is equivalent to the Local Poll Enable active low lpe message When U 0 S and P 3 1 mean the same as the bit of the same name in the PPE message and the I O write operation to the PPR is the same as the receipt of the PPE message from the GPIB Controller When U 1 S and P 3 1 do not carry any meaning but they must be cleared National Instruments Corporation 4 55 GPIB 1014 User Manual Register Descriptions Chapter 4 Bit Mnemonic Description 3w S Status Bit Polarity Sense Bit The S bit is used to indicate the polarity or sense of the TLC local ist message If S 1 the status is in phase meaning that if during a Parallel Poll response S ist 1 and U 0 the TLC responds to the Parallel Poll by driving one of the eight GPIB DIO lines low thus asserting it to a logic one If S 1 and ist 0 the TLC does not drive the DIO line If S 0 the status is in reverse phase meaning that if during a Parallel Poll ist 0 and U 0 the TLC responds to the Parallel Poll by driving one of the eight GPIB DIO lines low If S 0 and ist 1 the TLC does not drive the DIO line For more infor
234. ro indicates that the direction is from VMEbus memory to the GPIB This bit is used by the GPIB Synchronization and Interrupt Control circuitry e Writing any value to this register resets the circuitry which detects GPIB synchronization after a DMA transfer For more information see GPIB Synchronization and Interrupt Control later in this chapter GPIB 1014 User Manual 6 6 National Instruments Corporation Chapter 6 Theory of Operation Configuration Register 2 Four discrete 74LS74A D type flip flops are used to implement Configuration Register 2 CFG2 Data is written into each bit of this register on the rising edge of the WR signal generated by the Timing State Machine circuitry The SC bits are cleared by the onboard RESET signal generated by the Clock and Reset circuitry while the LMR and SFL bits are cleared only by the VMEbus signal SYSRESET or by writing to the register The S U bit is set or cleared to be in supervisor or slave mode depending upon the way you have set jumper W2 This write only register is used for a variety of configuration functions including the following functions e Issuing a Local Master Reset LMR to the GPIB 1014 The LMR bit is cleared to a 0 on SYSRESET Writing to CFG2 with this bit set to a 1 drives the GPIB 1014 local signal RESET Writing a 0 to this bit releases RESET e Configuring the GPIB 1014 to be System Controller Writing a 1 to this bit SC configures the GPIB 1014 as Syste
235. rohibits the setting of the CPT bit ISR1 7 r on receipt of an undefined command When CPT ENABLE is set and an undefined command has been received the DAC message is held and the Handshake stops until the Valid auxiliary command is issued The undefined command can be read from the CPTR and processed by the software 4 40 National Instruments Corporation Chapter 4 Register Descriptions Auxiliary Register E AUXRE VMEbus Address Base Address 11B hex AUXMR Control Code 110 Binary Bits 7 5 Attributes Write Only Internal to TLC Accessed through AUXMR 4 3 2 1 0 W Writing to Auxiliary Register E AUXRE is done via the AUXMR Writing the binary value 110 into the Control Code CNT 2 0 and a bit pattern into the the lower five bits of the AUXMR COM 4 0 causes the two lowest order bits to be written to AUXRE The 2 bit code DHDC and DHDT determines how the TLC may be placed into DAC Holdoff Bit Mnemonic Description 4 2w 0 Reserved Bits Write zeros to these bits lw DHDC DAC Holdoff on DCAS Bit Setting DHDC enables DAC Holdoff when the TLC enters Device Clear Active State DCAS Clearing DHDC disables DAC Holdoff on DCAS Issuing the Finish Handshake auxiliary command releases the Holdoff Ow DHDT DAC Holdoff on DTAS Bit Setting DHDT enables DAC Holdoff when the TLC enters Device Trigger Active State DTAS Clearing DHDT disables DAC Holdoff on DTAS Issuing the Finish Handshake auxiliary command releases
236. rol Signals An F241 and F1241 buffer pair is used to transceive the data bus control signals AS WRITE DSO and DS1 The OWN signal of the DMAC is used to control the direction of the buffer pair When the GPIB 1014 is a slave that is it does not have control of the bus control signals are directly routed onboard In contrast during DMA cycles control signals from the DMAC are somewhat altered before passing out to the VMEbus For example signal WRT of the DMAC is ORed with the onboard signal CCBYTE to implement the carry byte cycle see DMA Gating and Control in this chapter The UDS and LDS signals of the DMAC are delayed by the timing state machine output before being sent to the VMEbus see Timing State Machine later in this chapter In addition if DTACK of BERR from the last cycle is still asserted a flip flop prevents the GPIB 1014 from driving the data bus DSO or DS1 Address When the board is a VMEbus slave information from the VMEbus address bus lines A15 through A9 the Address Modifier Lines AMS through AMO and the VMEbus signals IACK and LWORD is received and decoded by two LS2521 8 bit comparators For more information see the Address Decoding section in this chapter When the board is a VMEbus master it drives the address lines A23 A1 the address modifier lines AM5 AMI IACK and LWORD The upper 16 bits of the address are driven by two transparent D type flip flop AS573s while the lower eight bit
237. ronization and Interrupt Control Interrupt Mask Register 1 IMR1 4 8 to 4 13 Interrupt Mask Register 2 IMR2 4 14 to 4 18 Interrupt Status Register 1 ISR1 4 8 to 4 13 Interrupt Status Register 2 ISR2 4 14 to 4 18 Interrupt Vector Registers 4 62 interrupter See also GPIB Synchronization and Interrupt Control definition 2 12 description of 2 6 GPIB 1014 IEEE 1014 interrupter compliance levels 2 15 programming considerations 5 20 to 5 21 theory of operation 6 9 INTRQ Interrupt Request Bits 7 through 5 4 64 INV Invert Bit 4 39 ISRI See Interrupt Status Register 1 ISR1 ISR2 See Interrupt Status Register 2 ISR2 ISS Individual Status Select Bit 4 39 J jumpers and switches base address 3 3 to 3 4 configuration 3 1 to 3 2 DMA address modifier code output default settings of AM code jumpers W3 W4 and W5 3 5 programming values for default settings W3 W4 and W5 3 6 setting AM code bits AM5 AMO 3 6 parts locator diagram 3 2 for Supervisor or Non privileged access 3 3 L LA Listener Active Bit 4 21 lines See signals and lines linked chaining operations 6 20 to 6 21 Listen command codes for 4 28 description 4 31 Listen in Continuous Mode command codes for 4 28 description 4 31 to 4 32 LLO Local Lockout command 4 25 GPIB 1014 User Manual Index 11 National Instruments Corporation Index LMR Local Master Reset Bit 4 67 Local Unlisten command codes for 4 28 description
238. ror Register 4 60 Channel Priority Register 4 61 Channel Status Register 4 58 to 4 59 Configuration Registers 4 64 to 4 67 Device Address Register BAR 4 48 Device Control Register 4 51 to 4 52 DMAC DMA channel register set chart 4 46 Function Code Registers 4 50 General Control Register 4 63 Interrupt Vector Registers 4 62 Memory Address Register MAR 4 48 Memory Transfer Counter Register MTCR 4 48 Operation Control Register 4 53 to 4 54 overview 4 46 to 4 48 register memory map 4 47 Sequence Control Register 4 55 transfer count registers 4 48 to 4 49 format for description of 4 3 interface registers Address Mode Register ADMR 4 22 to 4 24 Address Status Register ADSR 4 20 to 4 21 Auxiliary Mode Register AUXMR 4 27 to 4 33 Command Data Out Register CDOR 4 7 Command Pass Through Register CPTR 4 25 to 4 26 Data In Register DIR 4 6 hidden registers 4 33 to 4 41 illustration 4 4 Interrupt Mask Register 1 IMR1 4 8 to 4 13 Interrupt Mask Register 2 IMR2 4 14 to 4 18 GPIB 1014 User Manual Index 15 National Instruments Corporation Index Interrupt Status Register 1 ISR1 4 8 to 4 13 Interrupt Status Register 2 ISR2 4 14 to 4 18 uPD7210 internal GPIB interface registers chart 2 3 overview 4 3 Serial Poll Mode Register SPMR 4 19 Serial Poll Status Register SPSR 4 19 writing to hidden registers 4 4 mnemonics for 4 3 register map 4 1 to 4 2 size of 4 2 terminology relat
239. rrupt 2 Set the EINT bit in the CCR of Channel 1 to enable interrupts 3 Load the NIVR and EIVR of Channel 1 with the proper status ID byte to return to the VMEbus interrupt handler e If VMEbus interrupts are not used set the PCL bits in the DCR of Channel 1 to 00 for status input You can check the PCT and PCS bits in the CSR of Channel to see if the TLC has interrupted BERR has occurred or if GPIB handshake synchronization has occurred It is not necessary to write to the MTCR MAR DAR DFCR or CPR of Channel 1 GPIB 1014 User Manual 5 16 National Instruments Corporation Chapter 5 Programming Considerations 4 Once channels 0 and 1 have been configured properly start the DMA channels Start Channel 1 before starting Channel 0 The channels are started by writing to the CCRs with the STR bits set Channel 1 should also have the EINT bit set if you are using interrupts 5 Finally configure the TLC fora DMA operation The sequence is as follows a Set the END IE bit in IMRI if the TLC is a GPIB Listener Set the ERR IE bit in IMRI if the TLC is a GPIB Talker b Set the DMAO bit in IMR2 if the TLC is a GPIB Talker Otherwise clear DMAO c Set the DMAI bit in IMR2 if the TLC is a GPIB Listener Otherwise clear DMAI Polling During DMAs All the GPIB 1014 registers are accessible during DMA operations while the CPU has control of the bus If interrupts are not enabled the CSR of Channel 1 can be read to check
240. ry cycle 5 13 to 5 17 without carry cycle 5 10 to 5 12 GPIB 1014 User Manual Index 5 National Instruments Corporation Index DMA gating and control circuitry 6 7 to 6 8 DMA registers 68450 internal DMA registers chart 2 5 Address Registers 4 48 Base Address Register BAR 4 48 Base Transfer Counter Register BTCR 4 48 Channel Control Register CCR 4 56 to 4 57 Channel Error Register CER 4 60 Channel Priority Register CPR 4 61 Channel Status Register CSR 4 58 to 4 59 Configuration Register 1 CFG1 4 64 to 4 65 Configuration Register 2 CFG2 4 66 to 4 67 Device Address Register DAR 4 48 Device Control Register DCR 4 51 to 4 52 DMAC DMA channel register set chart 4 46 Function Code Registers 4 50 General Control Register GCR 4 63 Interrupt Vector Registers 4 62 Memory Address Register MAR 4 48 Memory Transfer Counter Register MTCR 4 48 Operation Control Register OCR 4 53 to 4 54 overview 4 46 to 4 48 register map 4 2 register memory map 4 47 Sequence Control Register SCR 4 55 Transfer Count Registers 4 48 to 4 49 DMAC 68450 definition of 2 12 initialization 5 2 theory of operation 6 14 to 6 22 DMAC channel operation block termination array chaining operations 6 19 to 6 20 continued operations 6 19 error conditions 6 21 to 6 22 linked chaining operations 6 20 to 6 21 multiple block operations 6 19 overview 6 19 initialization and transfer phases addr
241. s an array of pointers that point to the data blocks to be transferred 1 For array or linked chaining load the BFCR of Channel 0 with the proper data to generate the required Address Modifier Code to access the address amp transfer count array See Tables 3 1 and 3 2 for recommended values 2 For array or linked chaining load the BAR of Channel 0 with the starting physical address of the address amp transfer count array 3 For array chaining load the BTCR of Channel 0 with the number of entries in the address amp transfer count array Linked chaining does not use BTCR National Instruments Corporation 5 11 GPIB 1014 User Manual Programming Considerations Chapter 5 4 For array or linked chaining load the MFCR of Channel 0 with the proper data to generate the required Address Modifier Code to access the data blocks See Tables 3 1 and 3 2 for recommended values 5 Set up the data blocks and the address amp transfer count array in VMEbus memory Figures 6 1 and 6 2 describe how to set up the array for both chaining modes Interrupts are generally not enabled for Channel 0 The CPR NIVR DAR DFCR and EIVR of Channel 0 are generally not used 3 Channel 1 must be programmed before starting the transfer in the following manner a If VMEbus interrupts are used complete the following events e Set the PCL bits in the DCR of Channel 1 to 01 for status input with interrupt e Set the EINT bit in the CCR of Channel 1 to en
242. s memory DMA transfers the board can also perform 8 or 16 bit memory to memory DMA transfers National Instruments Corporation 2 5 GPIB 1014 User Manual General Description Chapter 2 Memory addresses generated by the GPIB 1014 are 24 bits wide and the VMEbus Address Modifier Lines AMS through AMO are fully programmable using function code registers located in the 68450 and three hardware jumpers W3 W4 and W5 See Chapter 3 for instructions on setting the hardware jumpers See Chapter 4 for a description of the DMAC Function Code Registers The 24 bit addresses along with selectable Address Modifier codes eliminate artificial memory boundaries and allow data transfers between the GPIB and data area program area or even devices located in the short I O area In VMEbus terminology the GPIB 1014 has A24 D08 EO amp D16 master capability The board does not use Unaligned Transfer UAT Block Transfer BLT or Read Modify Write RMW cycles The chaining feature of the 68450 allows data blocks of unlimited size to be transferred Interrupter Interrupt events that can drive a hardware programmed VMEbus interrupt request line are as follows e GPIB Data In DI Address Status Change ADSC e GPIB Data Out DO Secondary Address Pass Through APT END Message Received END RX Service Request Input SRQI e GPIB Command Out CO Device Execute Trigger DET Remote Mode Change REMC e Device Clear received DEC R
243. s are driven by an F245 The UAS signal of the DMAC is used to clock the AS573s GPIB 1014 User Manual 6 2 National Instruments Corporation Chapter 6 Theory of Operation Control Equations of Transceivers Table 6 1 lists the control equations for the address and data Table 6 1 Control Equations of Transceivers VMEbus Signals ontrol Equations A23 through A16 AS573 OC OWN output enable C UAS input clock A15 through A8 AS573 OC OWN output enable C UAS input clock A7 through Al F245 EN low output enable DIR OWN transceiver s direction HIBYTE transceiver EN HIBYTE DIR BWR amp OWN BWR amp OWN AM lines IACK LWORD F241 EN OWN D15 through A8 EN ACKEN amp DBEN NEW_CYCLE DIACK DIR BWR amp OWN BWR amp OWN D7 through DO EN ACKEN amp DBEN NEW CYCLE amp BRDEN DS HIBYTE DIR BWR amp OWN BWR amp Address Decoding During non DMA operations the GPIB 1014 acts as a VMEbus slave and monitors the lower 16 lines of the VMEbus address bus A15 through A01 the Address Modifier Lines AMS through AMO and the VMEbus signals LWORD and IACK Receivers and comparators are used to recognize the GPIB 1014 base address during short I O transfers Two 25LS2521 comparators recognize the short I O base address of the GPIB 1014 Except for Model 1S the base address is selectable with jumpers located on the board or wit
244. s is contrasted with Serial Polls where the overhead in the form of addressing and enabling command messages occurs with each poll Conducting a Parallel Poll The TLC as Active Controller has the capability to conduct a Parallel Poll When the Execute Parallel Poll auxiliary command is issued and the TLC internal local message rpp is set the Parallel Poll is executed that is the GPIB message IDY is sent true as soon as the TLC Controller interface function is placed in the proper state CAWS or CACS The Parallel Poll Response PPR is automatically read from the GPIB DIO lines into the CPTR and the rpp local message is cleared A program can determine that the Parallel Poll operation is complete based upon the condition of CO CO 1 when the poll is complete The response can be obtained by reading the contents of the CPTR The response is held in the CPTR until a GPIB command is transmitted or the TLC Controller function becomes inactive In response to IDY each device participating in the Parallel Poll drives one and only one GPIB DIO line its Parallel Poll response or PPRn active true or passive false while it drives the other lines passive false Because there are eight data lines and for each line there can be one response true or false for each device 2 lines device 16 responses are possible The line that a device uses and how that device drives the line depends upon how it was configured and whether its local individual stat
245. s must be set to choose one of four VMEbus request lines National Instruments Corporation 5 13 GPIB 1014 User Manual Programming Considerations Chapter 5 2 Channel 0 must be configured to provide a flyby transfer for the n 1 data bytes between the GPIB and the VME system memory The sequence is as follows a Write the CCR of Channel 0 with the SAB bit set to abort the channel operation in case it is still active Write a OxFF hex to the CSR of Channel 0 to clear any remaining error or status bits Load the DCR of Channel 0 with the proper value to select the DMA transfer mode Cycle Steal without Hold or Cycle Steal with Hold Set the DTYP bits to binary 10 device with ACK implicitly addressed set the DPS bit to 0 8 bit port size and set the PCL bits to 00 status input If the Cycle Steal with Hold transfer mode is selected write the GCR to select the required timeout See the GCR description for recommended values The OCR of Channel 0 is written to Set the DIR bit to reflect the direction of transfer 0 Memory to GPIB 1 GPIB to Memory Set the SIZE bits to 00 byte set the CHAIN bits to the desired value 00 if no chaining is used 10 if array chaining is used 11 if linked chaining is used and set the REQG bits to 10 REQ line initiates transfer Chaining is used to transfer a block of data greater than 64K or to transfer multiple blocks of data The SCR of Channel 0 is written to Set the MAC bits to de
246. se address configuration overview 3 3 setting with compare address lines 3 4 setting with jumper block W1 3 4 compare address lines 3 3 decoding 6 3 to 6 4 operands and addressing DMAC channel operation 6 17 VMEbus address lines 6 2 VMEbus slave addressing 2 2 to 2 3 Address Mode Register ADMR 4 22 to 4 24 address modifier code output See DMA address modifier code output Address Register ADR 4 43 Address Register 0 ADRO 4 42 Address Register 1 ADR1 4 44 Address Registers DMA Base Address Register BAR 4 48 Device Address Register DAR 4 48 GPIB 1014 User Manual Index 1 National Instruments Corporation Index Memory Address Register MAR 4 48 theory of operation 6 17 Address Status Register ADSR 4 20 to 4 21 addressed implementation of Talker and Listener 5 6 to 5 8 ADM I1 0 Address Mode Bits 1 through 0 4 23 to 4 24 ADMR See Address Mode Register ADMR ADR See Address Register ADR ADRO See Address Register 0 ADRO ADRI See Address Register 1 ADR1 ADSC Addressed Status Change Bit 4 17 to 4 18 ADSC IE Addressed Status Change Interrupt Enable Bit 4 17 to 4 18 ADSR See Address Status Register ADSR AM code output See DMA address modifier code output ANSIIEEE Standard 1014 1987 1 1 APT Address Pass Through Bit 4 9 to 4 10 APT IE Address Pass Through Interrupt Enable Bit 4 9 to 4 10 array chaining operations 6 19 to 6 20 ARS Address Register Select Bit 4 43 A TN
247. sed in the same way with minor exceptions described in the next section Using Direct Memory Access The onboard DMA Controller is the 68450 DMAC This chip provides four independent DMA channels of which two channels Channel 0 and 1 can be used by the GPIB 1014 to transfer data between the VMEbus memory and the GPIB The GPIB 1014 supports single address flyby mode DMA transfer to from the TLC where data bytes transfer directly between VMEbus memory and the TLC Although the 68450 supports several different DMA request generation modes it must be programmed for external cycle steal DMA request since the TLC asserts the DMA request line before each transfer The DMAC can be programmed via the REQG bits in the OCR to perform cycle steal with hold or cycle steal without hold mode transfers GPIB 1014 User Manual 5 6 National Instruments Corporation Chapter 5 Programming Considerations In cycle steal without hold mode upon receiving a DMA request from the TLC the DMAC requests use of the VMEbus Once the VMEbus is granted to the GPIB 1014 the DMAC performs the DMA transfer Then it immediately releases the bus In cycle steal with hold mode after performing a DMA transfer the DMAC will hold the VMEbus for a programmable time period waiting for another DMA request If no DMA request is received from the TLC in the time period specified the DMAC will relinquish ownership of the VMEbus If a DMA request is received from the TLC in
248. ses eee 6 15 Device TLC DMAC Communication eene 6 15 DNDLA ReQUESU lei Dus Dae ia ences alan 6 16 Data Lransferss eeosdeho duod etudes lola luis 6 16 Operands and AddressIDB se eire nte ortae Pe Rt rx S 6 17 Address Register Operations Eres eder oae e NUR Hut 6 17 Transfer Count Register Operation sees 6 17 Initiation and Control of Channel Operation eese 6 18 Initiating the Operas arl 6 18 The Continue Mode of Operation esee 6 18 loi M P 6 18 Software Abort calice irreali 6 18 Interrupt Pale areali 6 19 Block Termiiatiofi ne be e nie et lie 6 19 Multiple Block Operations ceded indies 6 19 Continued Operation edu ea diei cece iio b Se 6 19 Array Chaining Operations 3 oae eeepc ieget eden 6 19 Linked Chaining Operations c iaia 6 20 Err Condit ons cde ooa een ind e coc cate 6 21 GPIB Interrates stona MN DC 6 23 T st amd Treo gblesheoineul treu sua Sus better dia datore un fece Pp 6 24 DMA Stand Alone Testing 4 scope spe eee RE tura ie b e ac Rue en esas iE 6 24 GPIB Interface Testing uen e re Dee er e ant e De as reda RA Ua 6 24 Chapter 7 Diagnostic and Troubleshooting Test Procedures oo cece eee 7 1 Interpreting Test Procedures oos o px hu E deuda rod bane ma Uer ee 7 1 GPIB 1014 Hardware Installation Tests esee nennen 7 2 Appendix A Hardware Specifi
249. set in the CSR The BTC bit is set in the CSR The PCT bit is set and the PCL line is programmed to be an interrupt input For GPIB DMA transfers only channel 1 is used for interrupts This is described in more detail in Chapter 5 The interrupt vector returned to the CPU comes from either the NIVR or the EIVR for the channel The NIVR is used unless the ERR bit of the CSR is set in which case the error interrupt vector is used All interrupt vector registers in the DMAC are initialized to OxOF on power up or reset GPIB 1014 User Manual 4 62 National Instruments Corporation Chapter 4 Register Descriptions General Control Register VMEbus Address Base Address FF hex Attributes Read Write Internal to DMAC 7 6 5 4 3 2 1 0 EGNERUEXRUNGEE RENE When the transfer mode is cycle steal with hold the General Control Register GCR is used to define how long the DMAC after transferring the last byte will wait for another DMA request before relinquishing the bus The DMAC will retain control of the bus unless the device TLC pauses The TLC is determined to have paused if it does not make any requests during a full sample interval after the previous operand was transferred The sample interval is programmed via the GCR and is expressed in clock cycles The DMAC clock is 8 MHz If any of the four DMAC channels is programmed to operate in cycle steal with hold mode the same sample interval is used The GCR is shared by all fou
250. sserted as soon as the TLC enters CSBS Even though the TLC GPIB Controller state machine is in standby the CIC bit in the ADSR is still set Do not issue the Go To Standby auxiliary command unless the CO bit in ISR2 is set There are three cases to consider when going to standby Case 1 The TLC becomes the GPIB Talker when ATN is unasserted To do this wait for CO to be set send the TLC GPIB Talk Address MTA wait for CO to be set again and then issue the Go To Standby auxiliary command Case 2 The TLC becomes a GPIB Listener when ATN is unasserted To do this wait for CO to be set issue the TLC GPIB Listen Address MLA wait for CO to be set again and then issue the Go To Standby auxiliary command Case 3 The TLC is neither GPIB Talker nor Listener In this case issue the Listen In Continuous Mode auxiliary command before going to standby Once this mode is enabled the TLC participates in the GPIB handshake without setting the DI Data In bit or holding off the handshake at DAC until the DIR is read and it can then take control synchronously when necessary Going from Standby to Active Controller The manner in which the TLC resumes GPIB Active Control depends on how it went to standby Consider the following three cases Case 1 The TLC as a Talker takes control upon receipt of the Take Control Asynchronously auxiliary command Do not issue the Take Control Asynchronously auxiliary command until there are no more bytes
251. stener and to unaddress all other devices Go to standby and unassert ATN Transfer the contents of datct to the dO register Load a0 register with the address of datbuf Call DSEND to write the data When the last byte has been sent take control Call CMD to unaddress all devices Status on return The GPIB 1014 is Active Controller All GPIB devices are unaddressed C 17 GPIB 1014 User Manual Sample Programs 68000 Code movw 4 cmdct movb UNT cmdbuf movb UNL cmdbuf 1 movb MA 100 cmdbuf 2 movb ola cmdbuf 3 bsr CMD movb GTS AUXMR movw datct d0 movil datbuf a0 bsr DSEND WRITE1 beq btst WRITE1 movb TCA AUXMR subw 2 cmdct bsr CMD rts GPIB 1014 User Manual Appendix C Comments Put Untalk Unlisten MTA and OLA commands in the buffer all CMD to address GPIB devices o to standby and drop ATN IC G Preset dO register with byte count Preset a0 register with address of buffer IC all DSEND to send data DO ISR1 Wait until last byte has been sent hen take control T Use CMD to unaddress GPIB devices National Instruments Corporation Appendix C 68000 Code Sample Programs KR RRR KKK ck Ck Ck Ck Ck Ck k KK KKK KK COMMAND SEND CSEND ok ok ck ck ck ck ck ck ko Ck Ck Ck Ck k KK ko ko ko KK Summary Called by CMD to send interface messages Assumptions on entry T
252. t enable Immediate execute pon TLC immediately sets DO to request for a byte to be transferred using DMA to its internal register DMA channel finished COC GPIB synchronized PCL1 is pulled low PCT bit in CSR1 is set DO amp DI are both set DO is currently set to request another byte to be transferred verify data that was transferred to the TLC clear GPIB synchronization detecting circuitry also to pull PCL1 high clear PCT bit in CSRI PCT bit cleared PCLI high 12 Test DMA transfer flyby from GPIB to memory one byte memory write 105 105 CFG2 0A CFG2 08 National Instruments Corporation Set LMR and turn LED green Clear LMR 7 5 GPIB 1014 User Manual Diagnostic and Troubleshooting Test Procedures 00A 004 005 006 000 040 045 029 00C 101 11B 119 007 115 11B 113 111 000 040 113 101 040 040 MTCO 0001 DCRO AO OCRO 82 SCRO 0 CSRO FF CSR1 FF OCR1 0 MFCO 06 MARO daddr daddr 0 CFGI 19 AUXMR 2 ADMR CO CCRO 80 IMR2 10 AUXMR 0 ISR1 02 DIR 55 CSRO 81 CSRI 02 ISR1 2 02 daddr 55 CFG1 18 CSRI 02 CSRI 01 Chapter 7 one byte 4 byte data address clear data location BRG3 IN enable ROR feature TLC Reset ton lon Start channel 0 DMA in enable Immediate execute pon wait for DI cleared before writing a byte to TLC Data In Register send data to TLC DIR is full TLC request for a DMA transfer to p
253. t time after an operand transfer in anticipation of a new request from the TLC within that time period If a new request is not present during the hold period the DMAC relinquishes the bus by unasserting its signal OWN The sample period is defined by the values programmed into the GCR Data Transfers All DMAC transfers are assumed to be between a 16 bit 68000 device VMEbus memory and another device By programming the DCR the characteristics of the device can be assigned Each channel can communicate using the following protocols For GPIB 1014 GPIB DMA data transfers you must set the device type to 10 for Device with ACK for both Channel 0 and Channel 1 DTYP Device Type 00 68000 compatible device dual addressing 01 6800 compatible device dual addressing 10 Device with ACK single addressing 11 Device with ACK and READY single addressing Dual Address Transfers can be used with 68000 compatible VMEbus memory and 6800 compatible devices that must be explicitly addressed Because the address bus is used to address both the device and the memory the data cannot be directly transferred to or from the memory the source because the device receiver also requires addressing Instead the data is transferred from the source to the DMAC and held in internal holding register s This may take more than one bus cycle After that one or more transfers between the DMAC and the destination are required to complete the opera
254. ta into the TLC or the Configuration Registers As soon as the master has released DSO the board will release DTACK At the same time the circuitry will start a recovery cycle of 250 nsec Notice that recovery cycle is necessary to prevent another read or write cycle to the TLC DMA Cycles The Timing State Machine also controls the timing of the TLC RD and WR signals during a DMA operation The sequence is similar to a normal TLC access except that the 748139 decoder is used to drive the TLC RD and WR signals as required to effect the DMA transfer The DMAC begins a DMA transfer for the TLC by driving either ACK0 or ACK1 low The Timing State Machine also starts when this is detected When the transfer is from the TLC to the VMEbus memory the DMAC drives the VMEbus WRITE line low while the timing circuitry drives the TLC RD line low The timing circuitry counts 250 nsec data access time and then gates the DMAC data strobe signals UDS and LDS onto the VMEbus to drive the DS1 and DS0 lines The DMAC continues to drive the data strobes and the data lines with correct data until the memory drives the DTACK line When DMAC has received DTACK low it first releases its data strobes UDS and LDS then acknowledge lines ACK0 or ACK1 At this time the TLC RD line is released The timing circuitry then counts a recovery time of 250 nsec while the DMAC and VMEbus memory finish the cycle When the DMA transfer is from VMEbus memory to
255. talk address is formed by adding hex 40 to AD 5 0 1 0 while the listen address is formed by adding hex 20 GPIB 1014 User Manual 4 42 National Instruments Corporation Chapter 4 Register Descriptions Address Register ADR VMEbus Address Base Address 11D hex Attributes Write Only Internal to TLC The Address Register ADR is used to load the internal registers ADRO and ADR1 Both ADRO and ADRI must be loaded for all addressing modes Bit Mnemonic Description TW ARS Address Register Select Bit ARS is zero or one to select whether the seven low order bits of ADR must be loaded into internal registers ADRO or ADRI respectively 6w DT Disable Talker Bit DT must be set if recognition of the GPIB talk address formed from ADS through AD1 ADR 4 0 w is not to enable 5w DL Disable Listener Bit DL must be set if recognition of the GPIB listen address formed from ADS through ADI ADR 4 0 w is not to enable 4 0w AD 5 1 TLC GPIB Address Bits 5 through 1 These bits indicate the five low order bits of the GPIB address that is to be recognized by the TLC The corresponding GPIB talk address is formed by adding hex 40 to AD 5 1 while the corresponding GPIB listen address is formed by adding hex 20 The value written to AD 5 1 must not be all ones otherwise the corresponding talk and listen addresses would conflict with the GPIB Untalk UNT and GPIB Unlisten UNL commands National Instruments Corporation
256. tate CACS or when it enters CACS When the TLC leaves CACS gts is cleared Take Control Asynchronously The Take Control Asynchronously command pulses the local message tca Take Control Synchronously The Take Control Synchronously command sets the local message tcs The local message tcs is effective only when the TLC is in Controller Standby State CSBS or Controller Synchronous Wait State CSWS The local message tcs is cleared when the TLC enters Controller Active State CACS Take Control Synchronously on END The Take Control Synchronously on END command sets the local message tcs when the data block transfer End message END bit equal to one is generated at CSBS The tcs message is cleared when the TLC enters CACS Listen The listen command generates the local message ltn in the form of a pulse Listen in Continuous Mode The Listen in Continuous Mode command generates the local message ltn in the form of a pulse and places the TLC in continuous mode continues Register Bit Descriptions Chapter 4 Table 4 5 Auxiliary Commands Detail Description continued Command Code COM4 COM0 43210 11011 continued GPIB 1014 User Manual Description In continuous mode the local message rdy is issued when the Acceptor Not Ready State ANRS is initiated unless data block transfer end is detected END RX bit equals one When END is detected the TLC is placed in the RFD Holdoff state preventing g
257. ter is either initialized before the channel operation is started or is loaded during chaining or continue operations The BTCR is used for chaining and continue operations Both the MTCR and the BTCR have a terminal count of zero If either register is initialized or loaded with a terminal count when the channel is configured to use that register a count error is signaled Initiation and Control of Channel Operation The Channel Control Register CCR provides mechanisms for starting continuing halting or aborting an operation It also controls the enabling of interrupts from a channel Initiating the Operation To initiate the operation of a channel the STR bit of the CCR is set to start the operation Setting the STR bit causes the immediate activation of the channel The channel is ready to accept requests immediately In the GPIB applications the DMAC is ready to accept DMA requests from the TLC The channel initiates the operation by first clearing the STR bit and then setting the channel active ACT bit in the CSR Any pending requests are cleared and the channel is then ready to receive requests for the new operation If the channel is configured for an illegal operation the configuration error is signaled and no channel operation is run Illegal operations include selecting any of the operations marked undefined reserved If the DMA operation is dual address for memory to memory DMA the DAR must have been previously initialized The
258. termine if the MAC counts up or down 01 Up 10 Down The DAC bits are not used If no chaining is required complete the following events e Load the MFCR of Channel 0 with the proper data to generate the required Address Modifier Code to access the data buffer See Tables 3 1 and 3 2 for recommended values Load the MAR of Channel 0 with the starting physical address of the buffer of data that is to be transferred e Load the MTCR of Channel 0 with the number of bytes n 1 total in the buffer to be transferred must be less than or equal to 64K 65536 or OxFFFF hex If chaining is required complete the following events Note Chaining modes array or linked all use an address amp transfer count array which is an array of pointers that point to the data blocks to be transferred e For array or linked chaining load the BFCR of Channel 0 with the proper data to generate the required Address Modifier Code to access the address amp transfer count array See Tables 3 1 and 3 2 for recommended values e For array or linked chaining load the BAR of Channel 0 with the starting physical address of the address amp transfer count array e For array chaining load the BTCR of Channel 0 with the number of entries in the address amp transfer count array Linked chaining does not use the BTCR GPIB 1014 User Manual 5 14 National Instruments Corporation Chapter 5 Programming Considerations h e For array or linked chai
259. th hold transfer mode is selected write to the GCR to select the required timeout See the GCR description in Chapter 4 for recommended values Write to the OCR of Channel 1 Set the DIR bit to reflect the direction of transfer 0 Memory to GPIB 1 GPIB to Memory set the SIZE bits to 00 byte set the CHAIN bits to 10 or 11 array or linked chaining and set the REQG bits to 10 REQ line initiates transfer The array chaining feature is usually used to implement the carry cycle because of its simplicity Set the SCR of Channel 1 to 00 addresses do not count For array or linked chaining load the BFCR of Channel 1 with the proper value to generate the required address modifier code which then accesses the address amp transfer count array See Tables 3 1 and 3 2 for recommended values For array or linked chaining load Channel 1 BAR with the beginning address of the address amp transfer count array For array chaining load the BTCR of Channel 1 with 2 two entries in the carry cycle array Linked chaining does not use the BTCR National Instruments Corporation 5 15 GPIB 1014 User Manual Programming Considerations Chapter 5 i For array or linked chaining load the MFCR of Channel 1 with the proper value to generate the desired address modifier code which then accesses the data blocks See Tables 3 1 and 3 2 for recommended values Note If you are using the array chaining mode construct a special carry cycle arr
260. the carry cycle byte CCBYTE strobe and the DMA Acknowledge Enable signal DACKEN The main function of this circuitry is to gate the DMA request signal from the TLC DMAREQ to the proper DMA channel of the DMAC to perform the carry cycle function Upon RESET the DMA requests from the TLC are directed to Channel 0 This configuration remains unchanged unless a carry cycle DMA cycle is specified in CFG1 CC 1 The DMA requests are gated to Channel 0 until the DMAC DONE signal is active during a DMA transfer indicating that Channel 0 has completely finished that is all the blocks in the chain have been transferred The circuitry automatically gates the DONE pulse from Channel 0 to the DMA request pin REQ1 of Channel 1 requesting a transfer DREQ1 is asserted When the DMAC answers the request on Channel 1 with ACK1 asserted CCBYTE is asserted to indicate that the carry cycle byte transfer is in progress During the carry cycle byte transfer signal DACKEN is kept high to prevent the circuitry from asserting DMAACK In every DMA transfer except carry cycle byte transfer DACKEN causes DMAACK to go low to acknowledge a DMA request from the TLC The TLC can request DMA during the carry cycle transfer but will not be acknowledged until the carry cycle has completed In addition since Channel 0 has stopped DREQO can be asserted by the circuitry but has no effect The first byte to be transferred from Channel 1 is the carry cycle byte
261. the CSR of Channel 0 A timeout error no interrupt occurs if Channel 0 is improperly programmed If the PCT bit in Channel 1 is set and there are no errors on Channel 0 or 1 one of the following events has occurred The TLC is interrupting The DMA operation is complete and GPIB synchronization is detected The TLC should be examined for interrupt conditions if TLC interrupts are enabled This can be done by examining the INT bit in ISR2 Since reading ISR1 can clear the INT bit in ISR2 ISR2 should always be read before ISRI If the TLC did not request an interrupt the PCL transition was caused by the GPIB becoming synchronized To ensure that the DMA transfer was completed the CSR of Channel 0 must always be examined The COC bit must be set and the ERR bit should be cleared This check is sufficient if the carry cycle feature was not used If the carry cycle feature was used the CSR of Channel 1 must also be examined The Channel Operation Complete COC bit in Channel 1 must not be set and the MTCR must contain a because the second entry of the carry cycle array requests a 2 byte DMA transfer but only one byte the nth data byte is permitted to transfer A 2 byte transfer is requested for the following reason If Channel 1 was permitted to reach terminal count by requesting a 1 byte transfer the COC bit would set and an interrupt would occur the DMAC interrupts if either the COC bit or the PCT bit is set It is necessary for
262. the Holdoff National Instruments Corporation 4 4 GPIB 1014 User Manual Register Descriptions Chapter 4 Address Register 0 ADRO VMEbus Address Base Address 11D hex Attributes Read Only Internal to TLC Address Register 0 ADRO reflects the internal GPIB address status of the TLC as configured using the ADMR In addressing mode 2 ADRO indicates the address and enable bits for the primary GPIB address of the TLC In dual primary addressing modes 1 and 3 ADRO indicates the TLC major primary GPIB address Refer to the description of the Address Mode Register in this section for information on addressing modes Bit Mnemonic Description Tr X Don t Care Bit Reads as a zero or one 6r DTO Disable Talker 0 Bit If DTO is set it indicates that the mode 2 primary or mode 1 and 3 major Talker is not enabled that is the TLC does not respond to a GPIB talk address matching AD 5 0 1 0 If DTO 0 the TLC responds to a GPIB talk address matching bits AD 5 0 1 0 Sr DLO Disable Listener 0 Bit If DLO is set it indicates that the mode 2 primary or mode 1 and 3 major Listener is not enabled that is the TLC does not respond to a GPIB listen address matching bits AD 5 0 1 0 If DLO 0 the TLC responds to a GPIB listen address matching bits AD 5 0 1 0 4 Or AD 5 0 1 0 Mode 2 Primary TLC GPIB Address Bits 5 0 through 1 0 These are the lower five bits of the TLC GPIB primary or major address The primary
263. the TLC the sequence is similar The timing circuitry starts when ACKO or ACKI is detected low The DMAC drives the VMEbus data strobes as required and drives the VMEbus WRITE line high while the timing circuitry drives the TLC WR line low Unlike the case when the board reads the TLC and writes to the memory data strobes from DMAC UDS and LDS are not held off When the memory responds with DTACK indicating that the data is valid on the bus the DMAC waits a minimum of 190 nsec then releases the data strobes When the timing circuitry sees the data strobes released it immediately drives the TLC WR line high latching the data into the TLC When the DMAC has released ACK0 or ACKI the timing circuitry counts a recovery time of 250 nsec while the DMAC and memory finish the cycle Notice the function of the flip flop in preventing another read write cycle to the TLC during the recovery period The flip flop stays set Q 1 at all times before the recovery cycle is cleared Q 0 at the beginning of the recovery cycle and is set again at the end of the recovery period GPIB 1014 User Manual 6 6 National Instruments Corporation Chapter 6 Theory of Operation DMA Gating and Control The DMA Gating and Control circuitry is designed to control the DMA request acknowledge interface between the DMAC and the TLC The circuitry consists of an LS74 flip flop and miscellaneous logic gates to generate the DMA request signals DREQO and DREQ1
264. the interrupt handler must be determining what caused the interrupt A VMEbus interrupt can be caused by any of the following events National Instruments Corporation 5 17 GPIB 1014 User Manual Programming Considerations Chapter 5 e An interrupt from the TLC Abus or DMAC error that occurred during a DMA transfer e GPIB handshake synchronization To determine which condition caused the interrupt you must first examine the CSR of Channel 1 If the ERR bit of Channel 1 is set a DMAC error occurred while Channel 1 was transferring data The CER of Channel 1 indicates the type of error that occurred If Channel 1 is improperly programmed its operation terminates automatically and the ERR bit is set This does not cause an interrupt but rather a timeout error in your program The cause of the error can be found by examining the CER of Channel 1 See the CER register description in Chapter 4 for more information If the ERR bit of Channel 1 is zero and its PCT bit 1s a one which is the usual case one of the following conditions has occurred A bus error has occurred while Channel 0 is transferring data The TLC is interrupting e Synchronization on the GPIB is detected If a Channel 0 bus error has occurred the ERR bit is set in the CSR of Channel 0 and the CER of Channel 0 indicates a bus error Note A bus error on Channel 0 will set the PCT bit in the CSR of Channel 1 but will not set the ERR bit Instead it sets the ERR bit in
265. the time period specified the DMAC performs the transfer immediately The hold option is provided to reduce the VMEbus arbitration time during GPIB transfers The onboard TLC acts as a buffer between the VMEbus memory and the GPIB When the TLC is a GPIB Talker and its CDOR is empty the TLC asserts the DMA request line The DMAC in response to the DMA request transfers data from VMEbus memory to the CDOR The TLC then performs the necessary handshake sequence to transfer the byte to all GPIB Listeners Similarly when the TLC is a Listener and a byte of received data is in the DIR the TLC asserts the DMA request line The DMAC then transfers the data from the DIR to VMEbus memory The GPIB 1014 also provides the VMEbus Release On Request feature This feature which is enabled in CFGI causes the board to hold onto the VMEbus as long as no other board requests the VMEbus Even after the DMAC has relinquished the bus the board still asserts VMEbus signal BBSY to hold onto the bus If there is a DMAREQ while the board is holding the bus the DMAC is re granted the bus immediately to start the next DMA transfer If the board is holding the bus and if some other device requests the bus the GPIB 1014 will immediately release the bus The two DMAC channels used by the GPIB 1014 are channels 0 and 1 The DMAC can be configured to transfer data between the GPIB TLC and the VMEbus system memory with or without the carry cycle feature This feature is enabl
266. tion Single Addressing Mode is used for implicitly addressed devices that do not require addressing of the data register before the data can be transferred Such peripherals use the acknowledge ACK line to access the data register and require only one bus cycle to transfer the data between themselves and memory In case of a DMA write to a device data is transferred directly from the VMEbus memory into the device Similarly during a DMA read of a device data from a device is transferred directly into the VMEbus memory In both cases data is not temporarily kept in the internal holding register s of the DMAC GPIB 1014 User Manual 6 18 National Instruments Corporation Chapter 6 Theory of Operation Operands and Addressing Three factors affect how the actual data is handled device destination port size operand from source size and address sequencing e Device Port Size The DCR is also used to program the device port size to be 8 or 16 bits The port size is the number of data bits that the device can handle transmit or receive in a single bus cycle For GPIB DMA data transfers the device or TLC port size is eight bits For memory to memory transfers the port size can be 8 or 16 bits e Operand Size The OCR is used to program the operand size to be either byte word or longword The operand size is the number of bits of data to be transferred to honor a single DMA request Multiple bus cycles may be required to transfer th
267. tion 6 25 GPIB 1014 User Manual Theory of Operation Chapter 6 transfer the Memory Address and Device Address Registers point to the location of the next operand and the Memory Transfer Counter contains the number of operands yet to be transferred If an error occurs during a transfer that transfer has not completed and the registers contain the values they had before the transfer was attempted The DMAC logs the first error encountered in the Channel Error Register If an error is pending in the Error Register and another error is encountered the second error will not be logged GPIB Interface The GPIB 1014 is interfaced to the GPIB using an NEC uPD7210 Talker Listener Controller TLC large scale integrated circuit Access to the TLC is through a block of 16 VMEbus addresses that access the internal TLC registers When the GPIB 1014 is operating as a VMEbus slave the TLC is enabled TLCCS is asserted when the base address of the GPIB 1014 has been decoded and VMEbus address bit A8 is a logic 1 and bit A4 is a logic 1 The TLC register select signals RS2 through RSO are derived from VMEbus address lines A3 through Al Data is strobed into the TLC registers using WR Data is read from the TLC using RD Both RD and WR are generated by the Timing State Machine and are derived from the VMEbus WRITE line During DMA transfers the GPIB 1014 is acting as the VMEbus master and the TLCCS and RS2 through RSO signals are ignored by the T
268. to transfer an operand The REQG bits of the OCR determine the manner in which requests are generated Requests can be externally generated by the device or internally generated by the DMAC using its internal automatic request mechanism Internal automatic requests can be generated at a maximum rate so that the channel always has a request pending or at a limited rate monitoring the bus bandwidth use Any of the two modes are used when performing memory to memory DMA transfers In GPIB 1014 GPIB applications you must set the REQG bit to 10 to indicate that external REQ line will initiate a transfer After selecting external request generation mode you must also set the XRM bit in DCR to specify whether a channel must operate in cycle steal or cycle steal with hold mode Do not set XRM to 00 to select the burst transfer mode in the GPIB DMA application If internal request mode was chosen the XRM bit can be ignored The GPIB 1014 uses cycle steal mode with or without hold for GPIB DMA data transfers In the cycle steal mode the device TLC requests an operand transfer by generating a falling edge on the REQ line REQ0 or REQ1 The DMAC services the request by arbitrating for the system bus and then driving the ACK line active to transfer the operand If the XRM bits specify cycle steal without hold the DMAC relinquishes the bus after each operand transfer If the XRM bits specify cycle steal with hold the DMAC retains bus ownership for a shor
269. tory agencies Federal Communications Commission This device complies with Part 15 of the Federal Communications Commission FCC Rules for a Class A digital device Operation is subject to the following two conditions 1 This device may not cause harmful interference in commercial environments 2 This device must accept any interference received including interference that may cause undesired operation Canadian Department of Communications This device complies with the limits for radio noise emissions from digital apparatus set out in the Radio Interference Regulations of the Canadian Department of Communications DOC Le pr sent appareil num rique n miet pas de bruits radio lectriques d passant les limites applicables aux appareils num riques de classe A prescrites dans le r glement sur le brouillage radio lectrique dict par le minist re des communications du Canada Instructions to Users These regulations are designed to provide reasonable protection against harmful interference from the equipment to radio reception in commercial areas Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense There is no guarantee that interference will not occur in a particular installation However the chances of interference are much less if the equipment is installed and used according to this instruction ma
270. truments Corporation Contents Going from Standby to Active Controller eee 5 4 Going from Active to Idle Controller eee 5 5 The GPIB 1014 as GPIB Talker and Listener een 5 6 Programmed Implementation of Talker and Listener 5 6 Addressed Implementation of the Talker and Listener 5 6 Address Models allo e bot aep Lella olii ilao 5 6 Address MOS 2 ees olo ae orc sence Ma rit sto Desi il 5 6 Address Mode Soha asa ae ash testa eels ase is dd dedu uu E 5 7 5ending Recervins Messages lle 5 8 Using Direct Memory ACCESS siii re 5 8 DMA Transfers without the Carry Cycle eese 5 10 DMA Transfers with the Carry Cycle seen 5 13 Polling Durme DIMAS sprecato ete Pod ves abe aevo estt 5 17 Sending END Or EOS 5 17 Terminating the Transfer and Checking the Result 5 17 Terminating on END or EOS oec itti ea ria 5 19 Using Programmed IO cars deed te ei 5 19 Sending and Receiving Data ed ue cene oet esi 5 19 sending END or BOS iua sind e aee e iat icon d epi de btts 5 20 Terminating on END or BONS nace e tenti aaa 5 20 MMS WANS eti cq 5 20 Serial Polls Geil auricolari aule e EST Caer riae cM qudd 5 22 A ongiacunba Serial Poller tmc dt Bah bos e ec RANA ERN 9522 Responding to a Serial Poll 5 ancient c tudo tiam ade 5 22 Parallel Polls e eii aten e p bota bod du e
271. truments GPIB 400 or GPIB 410 that can monitor and control GPIB signal lines emulate GPIB Talker Listener and Controller devices and single step through the Source and Acceptor Handshakes GPIB 1014 User Manual 3 10 National Instruments Corporation Chapter 4 Register Bit Descnptions This chapter contains a description of the register map a list of interface registers and a description of the DMA registers Register Map The register map for the GPIB 1014 is shown in Table 4 1 This table gives the register name the register address the register size in bits and the register type read only write only or read and write Note For the sake of brevity only Channel 0 addresses for the DMA Register Group are listed in Table 4 1 See Table 2 3 for a complete listing of the addresses for all four channels of the DMA Register Group Table 4 1 GPIB 1014 Register Map GPIB Interface Register Group Data In Register Command Data Out Register Interrupt Status Register 1 Interrupt Mask Register 1 Interrupt Status Register 2 Interrupt Mask Register 2 Serial Poll Status Register Serial Poll Mode Register Address Status Register Address Mode Register Command Pass Through Register Auxiliary Mode Register Hidden Registers Internal Counter Register Parallel Poll Register Auxiliary Register A Auxiliary Register B Auxiliary Register E Address Register 0 Address Register Address Register 1 End Of String Register
272. ts Corporation 4 5 GPIB 1014 User Manual Register Bit Descriptions Chapter 4 lt q Control Code 11B AUXMR W TTI When CNT2 CNTO is ICR is loaded with 0 0 th AUXRE is loaded with o 0 pube pupr Figure 4 2 Writing to the Hidden Registers GPIB 1014 User Manual 4 6 National Instruments Corporation Chapter 4 Register Bit Descriptions Data In Register DIR VMEbus Address Base Address 111 hex Attributes Read Only Internal to TLC 7 6 9 4 3 2 1 0 R The Data In Register DIR is used to move data from the GPIB to the computer when the interface is a Listener The GPIB Ready For Data RFD message is held false until the byte is removed from the DIR either by a DMA transfer to the VMEbus memory or by an I O read from a VMEbus master DIO is the least significant bit of the data byte and corresponds to GPIB DIO1 DI7 is the most significant bit of the data byte and corresponds to GPIB DIOS Bit Mnemonic Description 7 Or DI 7 0 Data In Bits 7 through 0 National Instruments Corporation 4 7 GPIB 1014 User Manual Register Bit Descriptions Chapter 4 Command Data Out Register CDOR VMEbus Address Base Address 111 hex Attributes Write Only Internal to TLC 7 6 5 4 3 2 1 0 CDO7 CDO6 CDOS CDO4 CDO3 CDO2 CDOI CDOO The Command Data Out Register CDOR is used to move data from the VMEbus to the GPIB when the interface TLC is the GPIB Talker or the Active Controller Outgoing d
273. uments Corporation National Instruments Corporation 6504 Bridge Point Parkway 512 794 5678 Austin TX 78730 5039 9 V IA gt ANSI FCC GPIB hex IEEE in kbytes Mbytes sec VDC National Instruments Corporation is less than or equal to is greater than or equal to degrees amperes American National Standards Institute Celsius Federal Communications Commission General Purpose Interface Bus hexadecimal hertz Institute of Electrical and Electronic Engineers inches kilobyte 1 024 bytes 1 000 bytes meters megabytes of memory 1 000 000 bytes seconds volts volts direct current Glossary 1 GPIB 1014 User Manual Index Numbers 0 Reserved Bit Channel Error Register 4 60 Channel Priority Register 4 61 Channel Status Register 4 59 Configuration Register 2 CFG2 4 66 Device Control Register 4 52 General Control Register 4 63 Operation Control Register 4 53 Sequence Control Register 4 55 0 Reserved Bits Address Mode Register ADMR 4 22 Auxiliary Register E AUXRE 4 41 Internal Counter Register ICR 4 34 68450 DMAC See DMAC 68450 A abbreviations used in the manual vi access mode configuring 3 3 ACT Channel Active Bit 4 59 AD5 0 through AD1 0 Mode 2 Primary GPIB Address Bits 5 0 through 1 0 4 42 ADS 1 TLC GPIB Address Bit 5 through 1 4 42 AD 5 1 1 1 Mode 2 Secondary TLC GPIB Address Bits 5 1 through 1 1 4 44 address address decoder 2 12 ba
274. us message ist is one or zero Thus each device on the GPIB can be configured to drive its assigned DIO line true if ist 1 and to drive the DIO line false if ist 0 However it can also be configured to do exactly the opposite that is to drive the DIO line true if ist 0 and false if ist 1 The meaning of the value of ist whether one or zero is system or device dependent Because the data lines are driven Open Collector during Parallel Polls more than one device can respond on each line The device or devices asserting the line true overrides any device asserting the line false The Controller must know in advance whether a true response means the local ist message of the device is one or zero To do this the device must be configured to respond in the desired way The following two methods can be used to accomplish this e Local configuration Parallel Poll function subset PP2 involves assigning a response line and sense from the device side in a manner similar to assigning the device GPIB address Thus one device might be assigned to respond with remote message PPRI driving DIO1 while a second device might be assigned to respond with the remote message PPR3 driving DIO3 both positive that is true response if ist 1 Local configuration is static in that it does not change after the system is integrated that is the hardware is configured and installed e Remote configuration Parallel Poll function subset PP1 involves dynamically
275. ut If the cycle steal with hold transfer mode is selected the GCR must be written to select the required timeout See the GCR description for recommended values d Write to the OCR of Channel 0 The DIR bit must be set to reflect the direction of transfer 0 Memory to GPIB 1 GPIB to Memory The SIZE bits should be set to binary 00 byte the CHAIN bits should be set to the desired value binary 00 if no chaining is used binary 10 if array chaining is used binary 11 if linked chaining is used and the REQG bits should be set to binary 10 REQ line initiates transfer Chaining is used to transfer a block of data greater than 64K or to transfer multiple blocks of data e Write to the SCR of Channel 0 The MAC bits must be set to determine if the MAC counts up or down binary 01 Up binary 102Down The DAC bits are not used f If nochaining is required complete the following events e Load the MFCR of Channel 0 with the proper data to generate the required Address Modifier Code to access the data buffer See Tables 3 1 and 3 2 for recommended values Load the MAR of Channel 0 with the starting physical address of the buffer of data that is to be transferred e Load the MTCR of Channel 0 with the number of bytes in the buffer to be transferred must be less than or equal to 64K g If chaining is required complete the following events Note Chaining modes array or linked use an address amp transfer count array which i
276. ut the byte in DIR to memory DMA channel finished COC GPIB synchronized PCL DIR is empty DI is cleared verify data has been transferred from TLC to memory clear GPIB synchronization detecting circuitry also to pull PCL1 high clear PCT bit in CSR1 PCT bit cleared PCLI high 13 Test DMA transfer flyby to GPIB one byte memory read use the Carry Cycle feature Addresses 3000 to 300E are used for this test other locations may be used if required 3000 3002 3004 3006 3008 300A 300C 300E 105 105 101 004 044 data 0102 data 0306 data 0000 data 3003 data 0001 data 0000 data 3002 data 0002 CFG2 20A CFG2 08 CFGI 1C DCRO AO DCRI AO GPIB 1014 User Manual two data bytes 01 and 02 to be transferred on Channel 0 data byte 03 and CC byte 06 SEOI to be transferred on Channel 1 define carry cycle array s first entry 4 byte address of carry cycle byte 00003003 first entry s transfer count 0001 define carry cycle array s second entry 4 byte address of last data byte 00003002 second entry s transfer count 0002 Set LMR and turn LED green Clear LMR BRG3 OUT CC enable ROR feature 7 6 National Instruments Corporation Chapter 7 005 045 006 046 029 00C 00A 069 079 05C 05A 000 040 11B 119 115 047 007 11B 113 111 113 111 000 04A 113 111 040 047 040 OCRO 02 OCR1 0A SCRO 04 SCRI 04 MFCO 06 MA
277. w NDT Normal Device Termination Bit The Normal Device Termination bit is set when the transfer operation is terminated by the device This is not used in the GPIB 1014 application 0 1 No device termination Device terminated operation normally GPIB 1014 User Manual 4 58 National Instruments Corporation Chapter 4 Register Descriptions Bit Mnemonic Description Ar w ERR Error Bit The Error bit is used to report the occurrence of error conditions It is set if any errors have been signaled If bit ERR is set the CER logs the exact cause of the error If this bit is cleared the CER is also cleared 0 1 No errors Error as coded in CER 3r w ACT Channel Active Bit The Channel Active bit is asserted after the channel has been started The bit remains set until the channel operation terminates This bit is unaffected by write operations O Channel not active 1 Channel active 2r w 0 Reserved Bit Write zero to this bit 1r w PCT Peripheral Control Transition Bit The Peripheral Control Transition bit is set if a falling edge transition has occurred on the Peripheral Control Line PCL of the channel 0 No PCL transition occurred 1 High to low PCL transition occurred Or w PCS Peripheral Control Status Bit The Peripheral Control Status reflects the state of the channel s PCL This bit is unaffected by write operations 0 1 PCL low PCL high National Instruments Corporation 4 59 GPIB 1014 User Manual
278. wn talk or extended talk address while it is CIC or by receiving its talk address from another CIC It can also be programmed to talk using the Talk Only ton bit in the ADMR If the TLC is addressed to talk it is automatically unaddressed to listen TA is cleared by pon or by issuing the Chip Reset auxiliary command Major Minor Bit The MJMN bit is used to determine whether the information in the other ADSR bits applies to the TLC major or minor Talker and Listener functions MJMN is set to one when the TLC GPIB minor talk address or minor listen address is received MJMN is cleared on receipt of the TLC major talk or major listen address Note Only one Talker and Listener can be active at any one time thus the MJMN bit indicates which if either of the TLC Talker and Listener functions is addressed or active MJMN is always zero unless a dual primary addressing mode mode 1 or mode 3 is enabled see Address Mode Register later in this chapter Register Bit Descriptions Chapter 4 Address Mode Register ADMR VMEbus Address Base Address 119 hex Attributes Write Only Internal to TLC 7 6 5 4 3 2 1 0 W Bit Mnemonic Description TW ton Talk Only Bit By setting ton programs the TLC becomes a GPIB Talker If ton is set the lon ADMI and ADMO bits must be cleared This method must be used in place of the addressing method when the TLC will be only a Talker Note Clearing ton does not by itself take the TLC out of G
279. write operation A read from either of these registers results in a normal bus cycle but returns all ones In addition a pair of F74 flip flops is used to keep local signal BRDEN asserted until both Data Strobes DS0 and DS1 and Address Strobe AS from the VMEbus master have gone away and the board has released DTACK to end the current slave read write cycle Accesses to locations within the 512 byte block that do not specifically address either the DMAC the TLC or one of the Configuration Registers result in a bus error because the GPIB 1014 does not respond Clock and Reset Circuitry The clock and reset circuitry on the GPIB 1014 is used to generate the onboard clock and reset signals The VMEbus signal SYSCLK 16 MHz is received with a 74LS240 receiver and is divided by a 74LS74A flip flop to generate the onboard 8 MHz clock signal CLK This clock is used by the TLC and the DMAC The 16 MHz clock is used by the Timing State Machine to GPIB 1014 User Manual 6 4 National Instruments Corporation Chapter 6 Theory of Operation control the timing of local signal DTACK when the board is a slave and signal to control RD and WR to the TLC see Timing State Machine later in this chapter The VMEbus signal SYSRESET is monitored by the GPIB 1014 It is received with an LS240 receiver and is ORed with the LMR bit in CFG2 to generate the onboard RESET signal The RESET signal is used to initialize all circuitry on the GPIB 1014 exce
280. x B Parts List and Schematic Diagrams PITTTTE EZIO RIA EIER I e deed I RI ER DIG A IUE IHE HIC IH e nena eer AOC ITEM NO NI PART NO QTY REOD MFR MFR PART PRODUCT DESCRIPTION u34 700002 01 1 0000 TI SN74LS02n IC LS02 2 INP NOR 123 u35 700706 01 1 0000 Ti SN74F74N IC F74 FLIP FLOP 124 U36 700905 01 1 0000 DAL SEMI DS10124 25 IC DS1013M DDL 25NS 3 IN 1 125 u37 700431 01 1 0000 TI SN74FOSN IC F0B QUAD 2INPUT AND 126 U38 700418 01 1 0000 Ti SN74F32N IC F32 QUAD 2 1MPUT OR 127 U39 700706 01 1 0000 TI SN74F74N IC F74 FLIP FLOP 128 u40 760903 01 1 0000 TI SN74FOON IC FOO QUAD 2 INPUT WAND GATE 129 U41 700418 01 1 0000 TI SN74F32N 1C F32 QUAD 2 INPUT OR 130 u42 700234 01 1 0000 Ti SN74S02N 1C S02 2 INP NOR 131 U43 700750 01 1 0000 SIG T amp F27 IC F27 31NPUT NOR GATE 132 u45 700903 01 1 0000 TI SN74FOON IC FO0 QUAD 2 INPUT HAND GATE 133 u46 700049 01 1 0000 Ti SN74L 393N IC LS393 4 BIT BINARY COUNTER 124 U47 700011 01 1 0000 TI SN74LS32N IC L 32 2 INP OR 135 u48 700414 01 1 0000 TI SN74AS10N IC AS10 3 IMPUT NAND GATE 136 U49 700706 01 1 0000 TI SN74F74N IC F74 FLIP FLOP 137 u50 710004 01 1 0600 CTS 761 1 R10K RESNET 15x10K 2X 16 DIP 138 U51 700013 01 1 0000 TI SN74LS74AN IC LS74 FLIP FLOP 139 u52 700002 01 1 0000 TI SN74LSO2N IC LS02 2 INP NOR 140 u53 700002 01 1 0000 TI SN74LS02N IC LS02 2 INP NOR 141 u54 700431 01 1 0000 Ti SN74FO8N IC F08 QUAD 2INPUT AND 142 u55 700003 01 1 0000 ou SN74LSOGN IC LSO4 INVE
281. y or mode 1 and 3 minor listen function is not enabled that is the TLC does not respond to a secondary address or minor primary listen address formed from bits ADS 1 through AD1 1 If DL1 is cleared and the TLC received its primary listen address that is is in LPAS the secondary address is checked 4 Or AD 5 1 1 1 Mode 2 Secondary TLC GPIB Address Bits 5 1 through 1 1 These are the lower five bits of the TLC secondary or minor address The secondary address is formed by adding hex AO to bits AD 5 1 1 1 The minor talk address is formed by adding hex 40 to AD 5 1 1 1 while the listen address is formed by adding a hex 20 GPIB 1014 User Manual 4 44 National Instruments Corporation Chapter 4 Register Descriptions End of String Register EOSR VMEbus Address Base Address 11F hex Attributes Write Only Internal to TLC 7 6 5 4 3 2 1 0 EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOSO W The End Of String Register EOSR holds the byte used by the TLC to detect the end of a GPIB data block transfer A 7 or 8 bit byte ASCII or binary can be placed in the EOSR to be used in detecting the end of a block of data The length of the EOS byte to be used in the comparison is selected by the BIN bit in AUXRA AUXRA 4w If the TLC is a Listener and bit REOS of AUXRA is set the END bit is set in ISR1 whenever the byte in the DIR matches the EOSR If the TLC is a Talker and the data is being transmitted and bit XEOS of AU
282. y of Operation to service the request for the halted channel When this bit is reset the channel resumes operation and services any request that may have been received while the channel was halted The HLT bit must be cleared to zero when writing to the STR bit to avoid immediate halt of the channel Software Abort The CCR has a software abort bit SAB that can abort the current operation of the channel Writing a 1 into the SAB causes a channel abort error to be signaled The active channel is then terminated immediately the ACT bit is cleared and both COC and ERR bits are set The abort status can be read in the Channel Error Register CER When the CCR is read the SAB always reads as a 0 Interrupt Enable The CCR has an interrupt enable bit EINT that the channel can use to request interrupts on the completion of block transfers bit BTC is set on termination of channel operations bit COC is set or on a negative transition on the PCL bit PCT is set if desired While the GPIB 1014 uses Channel 0 and 1 the interrupt is usually enabled in Channel 1 only see Chapter 5 Programming Considerations Block Termination At the end of the transfer of an operand the DMAC decrements the MTCR If this counter is decreased to the terminal count the MTCR is exhausted and the operand is the last operand of the block The channel operation is complete if the operation is unchained and there is no continuation or if the operation is chained
283. y or linked array or linked Figure 5 2 DMA Transfer with Carry Cycle When the carry cycle feature is needed in a transfer it is transparent to the system CPU and is automatically handled by the GPIB 1014 once the channels have been properly configured As indicated earlier in this chapter Channel 1 is now used to transfer the carry cycle byte and the last data byte Setting up Channel 0 is similar to the steps used to program the DMA explained earlier in this chapter Channel 1 is set up to transfer two tiny blocks of data Itis easiest to use the array chaining mode on Channel 1 however linked chaining is also possible Channel 1 can also be configured to generate VMEbus interrupts When the GPIB is finally synchronized you can check the COC and ERR bit in the CSR of Channel 0 to determine the status of the DMA transfer of the first n 1 bytes The success of the DMA transfer is determined by examining the MTCR of Channel 1 Refer to the Terminating the Transfer and Checking the Result section later in this chapter for more details A detailed programming sequence for DMA transfers with a carry cycle is as follows 1 In CFGI set the CC bit in CFG1 to a 1 to enable the carry cycle feature Set the DIR bit to reflect the direction of the DMA transfer 12GPIB to Memory 0 Memory to GPIB Set the ROR bit if the Release On Request feature is to be enabled If interrupts are used the INTRQ bits are set to select the interrupt level BRG bit

GPIB-1014 User Manual - National Instruments

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