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eZ80F92/eZ80F93 Product Specification

1. Parameter Value Units Comments Frequency 20 MHz Resonance Parallel Mode Fundamental Series Resistance Rs 25 Q Maximum Load Capacitance C 20 pF Maximum Shunt Capacitance Co 7 pF Maximum Drive Level 1 mQ Maximum 32 KHz Real Time Clock Crystal Oscillator Operation Figure 51 illustrates a recommended configuration for connecting the Real Time Clock oscillator with an external 32 KHz fundamental mode parallel resonant crystal The rec ommended crystal specifications are provided in Recommended Crystal Oscillator Speci fications 32KHz Operation A printed circuit board layout should add no more than 4 pF of stray capacitance to either the RT C_Xyy or RTC_Xoyr pins If oscillation does not occur reduce the values of capacitors C and C to decrease loading An on chip MOS resistor sets the crystal drive current limit This configuration does not require an external bias resistor across the crystal An on chip MOS resistor provides the biasing On Chip Oscillator RTC Xw RTC Xour 32 MHz Crystal Ry 2200 Fundamental Mode C57 18 pF C57 18 pF Figure 51 Recommended Crystal Oscillator Configuration 32KHz operation PS015308 0404 PRELIMINARY On Chip Oscillators PS015308 0404 eZ80F92 eZ80F93 Product Specification Zi ZiLOG Table 144 Recommended Crystal Oscillator Specifications 32 KHz Operation Parameter Value Units Comments Frequency 32 KHz 32768 Hz Resona
2. gt ZCL 7 8 9 I 1 2 aaa 7 8 9 1 2 l msb Isb msb of DATA of DATA of DATA Byte 1 Byte 1 Byte 2 Isb of Single Bit Single Bit ZDI Address Byte Separator Byte Separator Figure 44 ZDI Block Data Read Timing Operation of the eZ80F92 Device During ZDI Breakpoints If the ZDI forces the CPU to BREAK only the CPU suspends operation The system clock continues to operate and drive other peripherals Those peripherals that can operate autonomously from the CPU may continue to operate if so enabled For example the Watch Dog Timer and Programmable Reload Timers continue to count during a ZDI BREAK point PS015308 0404 PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification 170 ZiLOG When using the ZDI interface any Write or Read operations of peripheral registers in the T O address space produces the same effect as Read or Write operations using the CPU Because many register Read Write operations exhibit secondary effects such as clearing flags or causing operations to commence the effects of the Read Write operations during a ZDI BREAK must be taken into consideration Bus Requests During ZDI DEBUG Mode The ZDI block on the eZ80F92 device allows an external device to take control of the address and data bus while the eZ80F92 device is in DEBUG mode ZDI BUSACK EN causes ZDI to allow or prevent acknowledgement of bus requests by external peripherals The bus acknowledge only occurs at the end
3. Parameter Control Register s Value PRT Enabled TMRx_CTL 0 1 Reload and Restart Enabled TMRx CTL 1 1 PRT Clock Divider 4 TMRx CTL 3 2 00b CONTINUOUS Mode TMRx CTL 4 1 PRT Reload Value TMRx RR H TMRx RR L 0003h Programmable Reload Timer Registers PS015308 0404 Each programmable reload timer is controlled using five 8 bit registers These registers are the TIMER Control register TIMER Reload Low Byte register TIMER Reload High Byte register TIMER Data Low Byte register and TIMER Data High Byte register The Timer Control register can be read or written to The timer reload registers are Write Only and are located at the same I O address as the timer data registers which are Read Only Timer Control Register The TIMER Control register detailed in Timer Control Register TMRO_CTL 0080h TMR1_CTL 0083h TMR2_CTL 0086h TMR3_CTL 0089h TMRA CTL 008Ch or TMR5_CTL 008Fh is used to control operation of the timer including PRELIMINARY Programmable Reload Timers eZ80F92 eZ80F93 Product Specification Z enabling the timer selecting the clock divider enabling the interrupt selecting between CONTINUOUS and SINGLE PASS modes and enabling the auto reload feature PS015308 0404 PRELIMINARY Programmable Reload Timers PS015308 0404 eZ80F92 eZ80F93 Product Specification VAF ZiLOG Table 33 Timer Control Register TMRO_CTL 0080h TMR1_CTL 0083h TMR2_CTL 0086h TMR3_CTL 00
4. Bit 7 6 5 2 Reset 0 0 0 0 0 0 0 0 CPU Access W W W W W W W Note W Write Only Bit Position Value Description 7 0 The ZDI BREAK on the next CPU instruction is disabled brk_next Clearing this bit releases the CPU from its current BREAK condition 1 The ZDI BREAK on the next CPU instruction is enabled The CPU can use multibyte Op Codes and multibyte operands BREAK points only occur on the first Op Code in a multibyte Op Code instruction If the ZCL pin is High and the ZDA pin is Low at the end of RESET this bit is set to 1 and a BREAK occurs on the first instruction following the RESET This bit is set automatically during ZDI BREAK on address match A BREAK can also be forced by writing a 1 to this bit 6 0 The ZDI BREAK upon matching BREAK address 3 is brk_addr3 disabled 1 The ZDI BREAK upon matching BREAK address 3 is enabled 5 0 The ZDI BREAK upon matching BREAK address 2 is brk_addr2 disabled 1 The ZDI BREAK upon matching BREAK address 2 is enabled 4 0 The ZDI BREAK upon matching BREAK address 1 is brk_addr1 disabled 1 The ZDI BREAK upon matching BREAK address 1 is enabled 3 0 The ZDI BREAK upon matching BREAK address 0 is brk_addrO disabled PS015308 0404 The ZDI BREAK upon matching BREAK address 0 is enabled PRELIMINARY ZiLOG Debug Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification VAR ZiLOG Bit Position Value Description 2 ign_low_1 0 The Ignore
5. l System Clock niinn nii l l l I l l l l l LI Internal RESET I I Signal l l l I l l l l l i i RESET mode ANA timer delay l eaa Figure 4 Voltage Brown Out Reset Operation PS015308 0404 PRELIMINARY Reset eZ80F92 eZ80F93 Product Specification Li ZiLOG Low Power Modes Overview The eZ80F92 device provides a range of power saving features The highest level of power reduction is provided by SLEEP mode The next level of power reduction is pro vided by the HALT instruction The lowest level of power reduction is provided by the clock peripheral power down registers SLEEP Mode Execution of the CPU s SLEEP instruction SLP places the eZ80F92 device into SLEEP mode In SLEEP mode the operating characteristics are The primary crystal oscillator is disabled The system clock is disabled The CPU is idle The Program Counter PC stops incrementing The 32KHz crystal oscillator continues to operate and drive the Real Time Clock and the Watch Dog Timer if WDT is configured to operate from the 32 KHz oscillator The CPU can be brought out of SLEEP mode by any of the following operations ARESET via the external RESET pin driven Low ARESET via a Real Time Clock alarm ARESET via execution of a Debug Reset command After exiting SLEEP mode the standard RESET delay occurs to allow the primary crystal oscillator to stabilize Refer to the Reset section on page 34 for
6. Bit Position Value Description 7 0 00h Least significant 8 bits of the 10 bit extended slave address SLAX FFh PC Data Register This register contains the data byte slave address to be transmitted or the data byte just received In transmit mode the most significant bit of the byte is transmitted first In receive mode the first bit received is placed in the most significant bit of the register After each byte is transmitted the I2C DR register contains the byte that is present on the bus in case a lost arbitration event occurs See I2C Data Registers I2C DR 00CAh Table 87 I C Data Registers I2C DR 00CAh Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RAV RW RW RW RW RW RW RW Note R W Read Write Bit Position Value Description 7 0 00h C data byte DATA FFh PC Control Register The I2C_CTL register is a control register that is used to control the interrupts and the master slave relationships on the PC bus When the Interrupt Enable bit IEN is set to 1 the interrupt line goes High when the IFLG is set to 1 When IEN is cleared to 0 the interrupt line always remains Low When the Bus Enable bit ENAB is set to 0 the PC bus inputs SCLx and SDAx are ignored and the C module does not respond to any address on the bus When ENAB is PRELIMINARY I2C Serial I O Interface eZ80F92 eZ80F93 Product Specification 157
7. 0 0 cece eee 86 Timer Reload Register Low Byte 0 0 cece eee eee eee 87 Timer Data Register High Byte 0 0 0 eee eee eee 87 Timer Reload Register High Byte 0 0 0c eee eee eee 88 Timer Input Source Select Register 0 0 0 e eee eee ee eee 89 Real Time Clock Seconds Register 0 0 0 ce eee eee eee 92 Real Time Clock Minutes Register 0 0 0 0 0 0 eere 93 Real Time Clock Hours Register 0 0 0 0c cece eee eee eee 94 Real Time Clock Day of the Week Register 0 95 Real Time Clock Day of the Month Register 0 96 Real Time Clock Month Register 0 cece eee eee eee 97 Real Time Clock Year Register 98 Real Time Clock Century Register 0 0 0 0 cee eee eee eee 99 Real Time Clock Alarm Seconds Register 0 005 100 Real Time Clock Alarm Minutes Register 005 101 PRELIMINARY List of Tables PS015308 0404 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 eZ80F92 eZ80F93
8. Poal Value Description 7 4 0000 Reserved 3 0 The day of the week alarm is disabled ARONEN 1 The day of the week alarm is enabled 2 0 The hours alarm is disabled ARIS TEN 1 The hours alarm is enabled 1 0 The minutes alarm is disabled AMINGEN 1 The minutes alarm is enabled 0 0 The seconds alarm is disabled ASEC_EN 1 The seconds alarm is enabled Real Time Clock Control Register This register contains control and status bits for the Real Time Clock Some bits in the RTC_CTRL register are cleared by a RESET The ALARM flag and associated interrupt if INT_EN is enabled are cleared by reading this register The ALARM flag is updated by clearing locking the RTC_UNLOCK bit or by an increment of the RTC count Writ ing to the RTC_CTRL register also resets the RTC count prescaler allowing the RTC to be synchronized to another time source SLP_WAKE indicates if an RTC alarm condition initiated the CPU recovery from SLEEP mode This bit can be checked after RESET to determine if a sleep mode recovery is caused by the RTC SLP_WAKE is cleared by a Read of the RTC_CTRL register Setting BCD_EN causes the RTC to use BCD counting in all registers including the alarm set points PRELIMINARY Real Time Clock 104 PS015308 0404 eZ80F92 eZ80F93 Product Specification 105 ZiLOG CLK_SEL and FREQ_SEL select the RTC clock source If the 32 KHz crystal option is selected the oscillator is enabled and the intern
9. BIT 0 BIT 1 IX d IX d BIT 2 BIT 3 IX d IX d 5 BIT 4 BIT 5 F IX d IX d L 7 BIT 6 BIT 7 2 IX d IX d s RES 0 RES 1 5 IX d IX d Qa 2 RES 2 RES 3 29 IX d IX d A RES 4 RES 5 IX d IX d B RES 6 RES 7 IX d IX d SET 0 SET 1 IX d IX d D SET 2 SET 3 IX d IX d z SET 4 SET 5 IX d IX d F SET 6 SET 7 IX d IX d Notes d 8 bit two s complement displacement PS015308 0404 PRELIMINARY Op Code Map eZ80F92 eZ80F93 Product Specification Zi ZiLOG Table 142 Op Code Map Fourth Byte After OFDh OCBh and dd Legend Lower Nibble of 4th Byte Upper Ds of Fou Byte 4 0 fl Vd Mnemonic First Operand Second Operand Lower Nibble Hex 0 1 2 3 4 5 6 7 8 9 A B e D E F RLC RRC IY d IY d RL RR IY d IY d 5 SLA SRA IY d IY d SRL IY d j BIT 0 BIT 1 IY d IY d i BIT 2 BIT 3 IY d IY d BIT 4 BIT 5 IY d IY d BIT 6 BIT 7 2 IY d IY d Z g RES 0 RES 1 5 IY d IY d Q 2 RES 2 RES 3 29 IY d Y d x RES 4 RES 5 IY d IY d B RES 6 RES 7 IY d IY d SET 0 SET 1 IY d IY d SET 2 SET 3 IY d IY d z SET 4 SET 5 IY d IY d F SET 6 SET 7 IY d IY d Notes d 8 bit two s complement displacement PS015308 0404 PRELIMIN
10. Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access R W RAW R IW R W R W RAW R W R W Note X Unchanged by RESET R W Read Only if RTC locked Read Write if RTC unlocked Binary Coded Decimal Operation BCD EN 1 Bit Position Value Description 7 4 0 3 The tens digit of the current day of the month count TENS_DOM 3 0 0 9 The ones digit of the current day of the month count DOM Binary Operation BCD_EN 0 Bit Position Value Description 7 0 01h The current day of the month count DOM 1Fh PRELIMINARY Real Time Clock PS015308 0404 eZ80F92 eZ80F93 Product Specification Z ZiLOG Real Time Clock Month Register This register contains the current month count See Real Time Clock Month Register RTC_MON 00E5h Table 44 Real Time Clock Month Register RTC MON 00E5h Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access R W RAW R IW R W R W RAW R W R W Note X Unchanged by RESET R W Read Only if RTC locked Read Write if RTC unlocked Binary Coded Decimal Operation BCD EN 1 Bit Position Value Description 7 4 0 1 The tens digit of the current month count TENS MON 3 0 0 9 The ones digit of the current month count MON Binary Operation BCD EN 0 Bit Position Value Description 7 0 O1h The current
11. R W Note R W Read Write if unlocked R Read Only if locked Key sequence required to unlock Bit Position Value Description 7 0 Disable Write Erase Protect on block 0x1C000 to 0x1FFFF BLK7_PROT 1 Enable Write Erase Protect on block 0x1C000 to Ox1FFFF 6 0 Disable Write Erase Protect on block 0x18000 to 0x1BFFF BLK6_PROT z 1 Enable Write Erase Protect on block 0x18000 to 0x1BFFF 5 0 Disable Write Erase Protect on block 0x14000 to 0x17FFF BLK5 PROT 1 Enable Write Erase Protect on block 0x14000 to Ox17FFF 4 0 Disable Write Erase Protect on block 0x10000 to 0x13FFF BLK4_PROT 1 Enable Write Erase Protect on block 0x10000 to 0x13FFF 3 0 Disable Write Erase Protect on block 0x0C000 to OxOFFFF BLK3 PROT 1 Enable Write Erase Protect on block 0xOC000 to OxOFFFF 2 0 Disable Write Erase Protect on block 0x08000 to OxOBFFF BLK2_PROT 1 Enable Write Erase Protect on block 0x08000 to OxOBFFF 1 0 Disable Write Erase Protect on block 0x04000 to OxO7FFF BLK1_PROT k Enable Write Erase Protect on block 0x04000 to 0x07FFF Note Unused in the eZ80F93 device PRELIMINARY Flash Memory 205 eZ80F92 eZ80F93 Product Specification Z 206 ZiLOG Bit Position Value Description 0 0 Disable Write Erase Protect on block 0x00000 to OxO3FFF BLKO PROT 1 Enable Write Erase Protect on block 0x00000 to OxO3FFF
12. Watch Dog Timer Operation PS015308 0404 Enabling and Disabling the WDT The Watch Dog Timer is disabled upon a RESET To enable the WDT the application pro gram must set the WDT_EN bit bit 7 of the WDT_CTL register When enabled the WDT cannot be disabled without a RESET Time Out Period Selection There are four choices of time out periods for the WDT 2 229 225 and 221 system clock cycles The WDT time out period is defined by the WDT PERIOD field of the WDT CTL register WDT_CTL 1 0 The approximate time out periods for two differ ent WDT clock sources is listed in Watch Dog Timer Approximate Time Out Delays Table 26 Watch Dog Timer Approximate Time Out Delays Clock Source Divider Value Time Out Delay 32 768KHz Crystal Oscillator 218 8 00s 32 768KHz Crystal Oscillator 222 128s 32 768KHz Crystal Oscillator 22 1024s 32 768KHz Crystal Oscillator 227 4096s 20MHz System Clock 218 13 1 ms 20MHz System Clock 222 209 7 ms 20MHz System Clock 225 1 68s 20MHz System Clock 227 6 71s 50 MHz System Clock 218 5 2ms 50MHz System Clock 222 83 9ms 50MHz System Clock 225 0 67s 50MHz System Clock 227 2 68s Note WDT time out values should be sufficiently long to allow Flash operations to complete RESET Or NMI Generation Upon a WDT time out the RST_FLAG bit in the WDT_CTL register is set to 1 In addi tion the WDT can cause a RESET or send a nonmaskable interrupt NMI signal t
13. When configured for dual edge triggered interrupt mode GPIO Mode 6 both a rising and a falling edge on the pin cause an interrupt request to be sent to the CPU When configured for single edge triggered interrupt mode GPIO Mode 9 the value in the Port x Data register determines if a positive or negative edge causes an interrupt request A O in the Port x Data register bit sets the selected pin to generate an interrupt request for falling edges A 1 in the Port x Data register bit sets the selected pin to generate an interrupt request for rising edges GPIO Control Registers The 12 GPIO Control Registers operate in groups of four with a set for each Port B C and D Each GPIO port features a Port Data register Port Data Direction register Port Alternate register 1 and Port Alternate register 2 Port x Data Registers When the port pins are configured for one of the output modes the data written to the Port x Data registers detailed in Port x Data Registers PB DR 009Ah PC DR 009Eh PD DR 00A2b are driven on the corresponding pins In all modes reading from the Port x Data registers always returns the current sampled value of the corresponding pins When the port pins are configured as edge triggered interrupt sources writing a 1 to the corresponding bit in the Port x Data register clears the interrupt signal that is sent to the CPU When the port pins are configured for edge selectable interrupts or level sensitive inte
14. 08h ZDI ADDR2 H 09h ZDI ADDR2 U 0Ah ZDI ADDR3 L 0Ch ZDI ADDR3 H 0Dh and ZDI ADDR3 U OEh in the ZDI Register Write Only Address Space Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access W W W W W W W W Note W Write Only Bit Position Value Description 7 0 00h The four sets of ZDI address match registers are used for ZDI ADDRx L FFh setting the addresses for generating BREAK points The ZDI ADDRx H 24 bit addresses are supplied by ZDI ADDRx U or ZDI ADDRx H ZDI ADDRXx L where x is 0 1 2 or 3 ZDI ADDRx U ZDI BREAK Control Register The ZDI BREAK Control register is used to enable BREAK points ZDI asserts a BREAK when the CPU instruction address ADDR 23 0 matches the value in the ZDI Address Match 3 registers ZDI ADDR3 U ZDI ADDR3 H ZDI ADDR3 Lj BREAKs can only occur on an instruction boundary If the instruction address is not the beginning of an instruction that is for multibyte instructions then the BREAK occurs at the end of the current instruction The BRK NEXT bit is set to 1 The BRK NEXT bit must be reset to 0 to release the BREAK See ZDI BREAK Control Register PS015308 0404 PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification VAR ZiLOG Table 97 ZDI BREAK Control Register ZDI BRK CTL 10h in the ZDI Write Only Register Address Space
15. 3 PRT3 OFF System clock to PRT3 is powered down System clock to PRT3 is powered up 2 PRT2 OFF System clock to PRT2 is powered down System clock to PRT2 is powered up 1 PRT1 OFF System clock to PRT1 is powered down System clock to PRT1 is powered up 0 PRTO OFF System clock to PRTO is powered down O o oOo gt oO oo ooo System clock to PRTO is powered up PS015308 0404 PRELIMINARY Low Power Modes eZ80F92 eZ80F93 Product Specification Z ZiLOG General Purpose Input Output GPIO Overview The eZ80F92 device features 24 General Purpose Input Output GPIO pins The GPIO pins are assembled as three 8 bit ports Port B Port C and Port D All port signals can be configured for use as either inputs or outputs In addition all of the port pins can be used as vectored interrupt sources for the CPU GPIO Operation The GPIO operation is the same for all 3 GPIO ports Ports B C and D Each port fea tures eight GPIO port pins The operating mode for each pin is controlled by four bits that are divided between four 8 bit registers These GPIO mode control registers are Port x Data Register Px DR Port x Data Direction Register Px DDR Port x Alternate Register 1 Px ALTI Port x Alternate Register 2 Px ALT2 where x can be B C or D representing any of the three GPIO ports B C or D The mode for each pin is controlled by setting each
16. DL D H DA EB EC ED suffix EH EL E HL EA gi D LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD HB HC HD HE HH HL H H HA LB L C L D LE LH LL L HL LA 7 D LD LD LD LD LD aig D LD LD LD LD LD LD LD LD HL B HL C HL D HL E HL H HL L HLJA AB AC AD AE AH AL A HL AA g ADD ADD ADD ADD ADD ADD ADD ADD ADC ADC ADC ADC ADC AD ADC ADC E AB AC AD AE AH AL A HLD AA AB AC AD AE AH AL A HL AA v g SUB SUB SUB SUB SUB SUB SUB SUB SBC SBC SBC SBC SBC SBC SBC SBC 2 AB AC AD AE AH AL A HHL AA AB AC AD AE AH AL A HL AA Z a AND AND AND AND AND AND AND AND XOR XOR XOR XOR XOR XOR XOR XOR 3 AB AC AD AE AH AL A HL AA AB AC AD AE AH AL A HL AA amp p OR OR OR OR OR OR OR OR CP CP CP CP CP CP CP CP AB AC AD AE AH AL A HL AA AB AC AD AE AH AL A HL AA Op Code JP CALL JP Map CALL RET POP JP PUSH ADD RST RET Map CALL ADC RST C NZ NZ RET Z Second O Z NZ BC mmn Mmn mmn BC An 00h Z Mmn Cadeafiel Mmn Mmn An 08h OCBh Op Code p RET POP NE OUT pis PUSH SUB RST RET cy E IN py Nor SBC RST NC DE mma MA uer DE A n 10h CF wie AAC gate A An 18h 0DDh Op Code p RET PoP ea EX jw PUSH AND RST RET JP BE EX en eorr XOR RST PO HL nma PPE Mmh HL An 20h PE
17. High Byte detailed in Timer Reload Register High Byte TMRO_RR_H 0082h TMR1_RR_H 0085h TMR2_RR_H 0088h TMR3_RR_H 008Bh TMR4 RR H 008Eh or TMR5 RR H 0091h stores the most significant byte MSB of the 2 byte timer reload value In CONTINUOUS mode the timer reload value is reloaded into the timer upon end of count When RST EN TMRx_CTL 1 is set to 1 to enable the automatic reload and restart function the timer reload value is written to the timer on the next rising edge of the clock y Note The Timer Data registers and Timer Reload registers share the same address space Table 37 Timer Reload Register High Byte TMRO RR H 0082h TMR1 RR H 0085h TMR2 RR H 0088h TMR3 RR H 008Bh TMRA4 RR H 008Eh or TMR5 RR H 0091h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access W W W W W W W Note W Write only Bit Position Value Description 7 0 OO0h FFh These bits represent the High byte of the 2 byte timer TMRx_RR_H reload value TMRx RR H 7 0 TMRx_RR_L 7 0 Bit 7 is bit 15 msb of the 16 bit timer reload value Bit 0 is bit 8 of the 16 bit timer reload value Timer Input Source Select Register The Timer Input Source Select register detailed in Timer Input Source Select Register TMR_ISS 0092h sets the input source for Programmable Reload Timer 0 3 TMRO TMR1 TMR2 TMR3 Event frequency must be less than one half of the system
18. Multiplexed Address and Data Bus PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification Le Motorola Bus Mode Chip selects configured for Motorola bus mode modify the CPU bus signals to duplicate an eight state memory transfer similar to that found on Motorola style microcontrollers The bus signals and eZ80F92 I O pins are mapped as illustrated in Figure 16 Bus Mode Controller eZ80 Bus Mode Motorola Bus Signals Pins Signal Equvalents INSTRD AS RD DS WR RW WAIT DTACK MREQ MREQ IORQ 3 IORQ ADDR 23 0 ADDR 23 0 DATA 7 0 3 gt DATA T7 0 Figure 16 Motorola Bus Mode Signal and Pin Mapping During Write operations the Motorola bus mode employs 8 states SO S1 S2 S3 S4 S5 S6 and S7 as described in Motorola Bus Mode Read States Table 20 Motorola Bus Mode Read States STATE SO The Read cycle starts in state SO The CPU drives R W High to identify a Read cycle STATE S1 Entering state S1 the CPU drives a valid address on the address bus ADDR 23 0 STATE S2 On the rising edge of state S2 the CPU asserts AS and DS STATE S3 During state S3 no bus signals are altered PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 20 Motorola Bus Mode Read States Continued STATE S4 During state S4 the CPU waits for a cycle termination signal DTACK WAIT
19. PS015308 0404 eZ80F92 eZ80F93 Product Specification ZiLOG Bus Clock Speed The C bus is defined for bus clock speeds up to 100KBPS 400 KBPS in FAST mode To ensure correct detection of START and STOP conditions on the bus the PC must sam ple the PC bus at least ten times faster than the bus clock speed of the fastest master on the bus The sampling frequency should therefore be at least 1 MHz 4MHz in FAST mode to guarantee correct operation with other bus masters The PC sampling frequency is determined by the frequency of the CPU system clock and the value in the I2C_CCR bits 2 to 0 The bus clock speed generated by the PC in MAS TER mode is determined by the frequency of the input clock and the values in DC CCR 2 0 and I2C_CCR 6 3 PC Software Reset Register The I2C SRR register is a Write Only register Writing any value to this register performs a software reset of the IPC module See I C Software Reset Register I2C_SRR 00CDh Table 92 C Software Reset Register I2C SRR 00CDh Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access W W W W W W W W Note W Write Only Bit Position Value Description 7 0 00h Writing any value to this register performs a software reset of SRR FFh the C module PRELIMINARY I2C Serial I O Interface 162 eZ80F92 eZ80F93 Product Specification Z 163 ZiLOoOG ZiLOG Debug Interface Introduction
20. ZiLOG set to 1 the C responds to calls to its slave address and to the general call address if the GCE bit I2C_SAR 0 is set to 1 When the Master Mode Start bit STA is set to 1 the IC enters MASTER mode and sends a START condition on the bus when the bus is free If the STA bit is set to 1 when the I C module is already in MASTER mode and one or more bytes are transmitted then a repeated START condition is sent If the STA bit is set to 1 when the PC block is being accessed in SLAVE mode the PC completes the data transfer in SLAVE mode and then enters MASTER mode when the bus is released The STA bit is automatically cleared after a START condition is set Writing a 0 to this bit produces no effect If the Master Mode Stop bit STP is set to 1 in MASTER mode a STOP condition is transmitted on the IC bus If the STP bit is set to 1 in slave move the I C module operates as if a STOP condition is received but no STOP condition is transmitted If both STA and STP bits are set the PC block first transmits the STOP condition if in MASTER mode and then transmit the START condition The STP bit is cleared automatically Writing a 0 to this bit produces no effect The IC Interrupt Flag IFLG is set to 1 automatically when any of 30 of the possible 31 IC states is entered The only state that does not set the IFLG bit is state F8h If IFLG is set to 1 and the IEN bit is also set an interrupt is generated When IFLG is set by the LC the L
21. a peripheral signal If the termination signal is not asserted at least one full CPU clock period prior to the rising clock edge at the end of S4 the CPU inserts WAIT Twajt states until DTACK is asserted Each WAIT state is a full bus mode cycle STATE S5 During state S5 no bus signals are altered STATE S6 During state S6 data from the external peripheral device is driven onto the data bus STATE S7 On the rising edge of the clock entering state S7 the CPU latches data from the addressed peripheral device and deasserts AS and DS The peripheral device deasserts DTACK at this time The eight states for a Write operation in Motorola bus mode are described in Motorola Bus Mode Write States Table 21 Motorola Bus Mode Write States STATE SO The Write cycle starts in SO The CPU drives R W High if a preceding Write cycle leaves R W Low STATE S1 Entering S1 the CPU drives a valid address on the address bus STATE S2 On the rising edge of S2 the CPU asserts AS and drives R W Low STATE S3 During S3 the data bus is driven out of the high impedance state as the data to be written is placed on the bus STATE S4 Atthe rising edge of S4 the CPU asserts DS The CPU waits for a cycle termination signal DTACK WAIT If the termination signal is not asserted at least one full CPU clock period prior to the rising clock edge at the end of S4 the CPU inserts WAIT Tyr states until DTA
22. eZ80Acclaim Flash Microcontrollers eZ80F92 eZ80F93 Product Specification PRELIMINARY PS015308 0404 ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com Z ZiLOG This publication is subject to replacement by a later edition To determine whether a later edition exists or to request copies of publications contact ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 Telephone 408 558 8500 Fax 408 558 8300 www zilog com ZiLOG is a registered trademark of ZiLOG Inc in the United States and in other countries All other products and or service names mentioned herein may be trademarks of the companies with which they are associated Document Disclaimer 2004 by ZiLOG Inc All rights reserved Information in this publication concerning the devices applications or technology described is intended to suggest possible uses and may be superseded ZiLOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION DEVICES OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE Except with the express written approval ZiLOG use of information devices or technology as critical components of life support systems is not authorized No licen
23. 14h ZDI WR DATA H Write Data High Byte XXh 15h ZDI WR DATA U Write Data Upper Byte XXh 16h ZDI RW CTL Read Write Control register 00h 17h ZDI BUS CTL Bus Control register 00h 21h ZDI IS4 Instruction Store 4 XXh 22h ZDI IS3 Instruction Store 3 XXh 23h ZDI IS2 Instruction Store 2 XXh 24h ZDI IS1 Instruction Store 1 XXh 25h ZDI ISO Instruction Store O XXh 30h ZDI WR MEM Write Memory register XXh PRELIMINARY ZiLOG Debug Interface 171 eZ80F92 eZ80F93 Product Specification VA ZiLOG ZDI Read Only Registers ZDI Read Only Registers lists the ZDI Read Only registers Many of the ZDI Read Only addresses are shared with ZDI Write Only registers Table 95 ZDI Read Only Registers ZDI Reset Address ZDI Register Name ZDI Register Function Value 00h ZDI ID L eZ80 Product ID Low Byte register 07h 01h ZDI ID H eZ80 Product ID High Byte register 00h 02h ZDI ID REV eZ80 Product ID Revision register XXh 03h ZDI_STAT Status register 00h 10h ZDI RD L Read Memory Address Low Byte XXh register 11h ZDI RD H Read Memory Address High Byte XXh register 12h ZDI RD U Read Memory Address Upper Byte XXh register 17h ZDI BUS STAT Bus Status register 00h 20h ZDI RD MEM Read Memory Data Value XXh ZDI Register Definitions PS015308 0404 ZDI Address Match Registers The four sets of address match registers are used for setting the addresses for generating BREAK points When the accompanying BRK
24. 22 Instruction Store 4 0 Registers 182 Intel Bus Mode 55 57 Multiplexed Address and Data Bus 62 Separate Address and Data Buses 58 internal pull up 42 internal system clock 53 Interrupt Controller 47 Interrupt Enable bit 11 91 109 156 Interrupt Enable Flag 49 186 interrupt input 13 16 18 19 Interrupt Request 43 45 47 49 85 206 Interrupt Service Routine 47 49 SPI 48 interrupt vector 47 48 address 47 49 interrupt highest priority 47 48 interrupts edge selectable 45 Introduction to On Chip Instrumentation 190 Introduction ZiLOG Debug Interface 163 PRELIMINARY Index IORQ see Input Output Request IR RxD modulation signal 13 127 131 IR TxD modulation signal 13 127 130 131 IrDA Encoder Decoder 13 39 130 131 IrDA specifications 126 IrDA standard 126 baud rates 126 IrDA transceiver 130 IrDA Transmit Data 13 IrDA see Infrared Data Association 126 IRQ see Interrupt Request IRQ EN bit 81 85 136 139 ISR see Interrupt Service Routine IVECT see interrupt vector address J Jitter Infrared Encoder Decoder 130 Joint Test Action Group and ZDI clock input 12 22 164 190 191 243 interface 190 mode select input 12 22 191 243 mode selection 191 Test Clock 12 Test Data In 12 22 164 191 243 Test Data Out 12 22 191 243 Test Mode 12 Test Trigger Output 12 JTAG see Joint Test Action Group L least significant bit 86 87 107 147 148 150 153 159 165 least significant byt
25. Ground GND Vss Block Diagram PS015308 0404 Figure 1 illustrates a block diagram of the eZ80F92 processor PRELIMINARY Architectural Overview SCL SDA SCK SS MISO MOSI CTS0 1 DCD0 1 DSR0 1 DTR0 1 RI0 1 RTS0 1 RXD0 1 TXD0 1 IrDA Encoder Decoder IR_RxD IR_TxD PS015308 0404 Real Time RTC_VDD Clock and RTC_XIN 32KHz RTC XOUT Oscillator Pc Serial Interface SPI Serial Parallel Interface eZ80 CPU 128KB 64KB Flash Memory JTAG ZDI Debug Interface ADDR 23 0 Interrupt 8KB 4KB UART SRAM VOD Universal Asynchronous Receiver Transmitter 2 Interrupt Controller Crystal 8 bit General Oscillator Purpose and I O Port System Clock 3 Generator 6 oO Z 5r zzzz E Mm amp x oa e eeu m oO A x FREE c a a Figure 1 eZ80F92 Block Diagram PRELIMINARY Programmable Reload Timer Counter T4_OUT T5 OUT eZ80F92 eZ80F93 Product Specification Z ZiLOG BUSACK BUSREQ INSTRD IORQ MREQ RD WR NMI RESET HALT SLP JTAG ZDI Signals 5 WAT Chip Select amp CSO Wait State CS1 Generator CS2 CS3 4 DATA 7 0 ADDR 23 0 Architectural Overview eZ80F92 eZ80F93 Product Specification Z Pin Description Figure 2 illustrates the pin layout of the eZ80F92 device in the 100 pin LQFP package 100 Pin LQFP Pin Identification of the eZ80F92 Device describes the
26. High byte of the I O address ADDR 15 8 Because the upper byte of the address bus ADDR 23 16 is ignored the I O devices can always be accessed from within any mem ory mode ADL or Z80 The MBASE offset value used for setting the Z80 MEMORY mode page is also always ignored Four I O Chip Selects are available with the eZ80F92 device To generate a particular I O Chip Select the following conditions must be met The Chip Select is enabled by setting CSX EN to 1 The Chip Select is configured for I O by setting CSX IO to 1 An VO Chip Select address match occurs ADDR 15 8 CSx LBR 7 0 No higher priority lower number Chip Select meets the above conditions The I O address is not within the on chip peripheral address range 0080h 00FFh On chip peripheral registers assume priority for all addresses where 0080h lt ADDR 15 0 x 00FFh An VO instruction must be executing PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification 53 ZiLOG If all of the foregoing conditions are met to generate an I O Chip Select then the following actions occur The appropriate Chip Select CSO CS1 CS2 or CS3 is asserted driven Low TORQ is asserted driven Low Depending upon the instruction either RD or WR is asserted driven Low WAIT States For each of the Chip Selects programmable WAIT states can be asserted to provide exter nal devices with additiona
27. I 7 0 IVECT 7 0 where I 7 0 is the CPU s Interrupt Page Address Regis ter Table 11 Interrupt Vector Sources by Priority Vector Source Vector Source Vector Source Vector Source 00h Unused 1Ah UART 1 34h Port B 2 4Eh Port C 7 02h Unused 1Ch Pc 36h Port B 3 50h Port D 0 04h Unused 1Eh SPI 38h Port B 4 52h Port D 1 06h Unused 20h Unused 3Ah Port B 5 54h Port D 2 08h Flash 22h Unused 3Ch Port B 6 56h Port D 3 OAh PRT 0 24h Unused 3Eh Port B 7 58h Port D 4 OCh PRT 1 26h Unused 40h Port C 0 5Ah Port D 5 OEh PRT 2 28h Unused 42h Port C 1 5Ch Port D 6 10h PRT 3 2Ah Unused 44h Port C 2 5Eh Port D 7 12h PRT 4 2Ch Unused 46h Port C 3 60h Unused 14h PRT 5 2Eh Unused 48h Port C 4 62h Unused 16h RTC 30h Port B 0 4Ah Port C 5 64h Unused 18h UART 0 32h Port B 1 4Ch Port C 6 66h Unused Note Absolute locations 00h 08h 10h 18h 20h 28h 30h 38h and 66h are reserved for hardware reset NMI and the RST instruction The user s program should store the starting address of the interrupt service routine ISR in the two byte interrupt vector locations For example for ADL mode the two byte address for the SPI interrupt service routine would be stored at 00h I 7 0 1Eh and PRELIMINARY Interrupt Controller eZ80F92 eZ80F93 Product Specification ZiLOoOG 00h I 7 0 1Fh In Z80 mode the two byte address for the SPI interrupt service rou tine would be stored at MBASE 7 0 I
28. In multidrop mode this indicates that the received character is an address byte PS015308 0404 The received character at the top of the FIFO does not contain an overrun error This bit is reset to O when the UARTx LSR register is read Overrun error is detected If the FIFO is not enabled this indicates that the data in the receive buffer register was not read before the next character was transferred into the receiver buffer register If the FIFO is enabled this indicates the FIFO was already full when an additional character was received by the receiver shift register The character in the receiver shift register is not put into the receiver FIFO PRELIMINARY Universal Asynchronous Receiver Transmitter PS015308 0404 eZ80F92 eZ80F93 Product Specification VAR ZiLOG Bit Position Value Description 0 0 This bit is reset to O when the UARTx RBR register is read or DR all bytes are read from the receiver FIFO 1 Data Ready If the FIFO is not enabled this bit is set to 1 when a complete incoming character is transferred into the receiver buffer register from the receiver shift register If the FIFO is enabled this bit is set to 1 when a character is received and transferred to the receiver FIFO UART Modem Status Register This register is used to show the status of the UART signals See UART Modem Status Registers UARTO MSR 00C6h UART1_MSR 00D6h Table 66 UART Modem Status Registers UARTO
29. Product Specification ZiLOG Real Time Clock Alarm Hours Register 0 00000 102 Real Time Clock Alarm Day of the Week Register 103 Real Time Clock Alarm Control Register 004 104 Real Time Clock Control Register 0 0 0 0 cece eee eee 105 UART Baud Rate Generator Register Low Bytes 112 UART Baud Rate Generator Register High Bytes 113 UART Receive Buffer Registers 0 0 0 0 cece eee eee eee 114 UART Transmit Holding Registers 0 0 0 0 0c eee eee 114 UART Interrupt Enable Registers 115 UART Interrupt Identification Registers 0 000005 116 UART Interrupt Status Codes 116 UART FIFO Control Registers 117 UART Line Control Registers 0 0 0 eee ee eee 118 UART Character Parameter Definition 004 120 Parity Select Definition for Multidrop Communications 120 UART Modem Control Registers lees 121 UART Line Status Registers eee 122 UART Modem Status Registers 0 0 0 0 cece eee eee 124 UART Scratch Pad Registers 0 0 eee eee eee 125 IrDA Physical Layer 1 4 Pulse Durations Specifications 128 Frequency Divider Values lessen 129 Infrared Encoder Decoder Control Registers 005 131 SPI Clock Phase and Clock Polarity Operation 0 134 SPI Baud Rate Generator Register Low
30. Reset Active Tristate Pull Trigger Open Drain Pin Symbol Direction Direction Low High Output Up Down Input Source 46 ADDRI WO O NA Yes No No Y No 17 ADDR14 y o O N A Yes No No No 18 Vpp 19 Vss 20 ADDR15 1 0 O N A Yes No No No 21 ADDR16 1 0 O N A Yes No No No 22 ADDR17 I O O N A Yes No No No 23 ADDR18 1 0 O N A Yes No No No 24 ADDR19 1 0 O N A Yes No No No 25 ADDR20 1 0 O N A Yes No No No 26 ADDR21 1 0 O N A Yes No No No 27 ADDR22 I O O N A Yes No No No 28 ADDR23 1 0 O N A Yes No No No 29 CSO O O Low No No No No 30 CS1 O O Low No No No No 31 CS2 O O Low No No No No 32 CS3 O O Low No No No No 33 VDD 34 Vss 35 DATAO I O N A Yes No No No 36 DATA1 1 0 N A Yes No No No 37 DATA2 I O N A Yes No No No 38 DATA3 I O N A Yes No No No 39 DATA4 I O N A Yes No No No 40 DATA5 1 0 N A Yes No No No 41 DATA6 0 N A Yes No No No 42 DATA7 I O N A Yes No No No 43 VDD PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification VAF ZiLOG Table 2 Pin Characteristics of the eZ80F92 Device Continued Schmitt Reset Active Tristate Pull Trigger Open Drain Pin Symbol Direction Direction Low High Output Up Down Input Source MA Vee 8 45 IORQ I O O Low Yes No No No 46 MREQ I O O Low Yes No No No 47 RD O O Low No No No No 48 WR O O Low No No No No 49 INSTRD O O Low No No No No 50 WAIT Low N
31. Zi ZiLOG Table 129 Exchange Instructions Mnemonic Instruction EX Exchange registers EXX Exchange CPU Multibyte register banks Table 130 Input Output Instructions Mnemonic Instruction IN Input from I O INO Input from I O on Page 0 IND INDR Input from I O and Decrement with Repeat INDRX Input from I O and Decrement Memory Address with Stationary I O Address IND2 IND2R Input from I O and Decrement with Repeat INDM INDMR Input from I O and Decrement with Repeat INI INIR Input from I O and Increment with Repeat INIRX Input from I O and Increment Memory Address with Stationary I O Address INI2 INI2R Input from I O and Increment with Repeat INIM INIMR Input from I O and Increment with Repeat OTDM OTDMR Output to I O and Decrement with Repeat OTDRX Output to I O and Decrement Memory Address with Stationary I O Address OTIM OTIMR Output to I O and Increment with Repeat OTIRX Output to I O and Increment Memory Address with Stationary I O Address OUT Output to I O OUTO Output to I O on Page 0 OUTD OTDR Output to I O and Decrement with Repeat OUTD2 OTD2R Output to I O and Decrement with Repeat OUTI OTIR Output to I O and Increment with Repeat OUTI2 OTI2R Output to I O and Increment with Repeat TSTIO Test I O PRELIMINARY eZ80 CPU Instruction Set PS015308 0404 eZ80F9
32. the RTS output port is the inverse of this bit In LOOP BACK mode this bit is connected to the CTS bit in the UART Status Register 0 0 1 Data Terminal Ready DTR In normal operation the DTR output port is the inverse of this bit In LOOP BACK mode this bit is connected to the DSR bit in the UART Status Register UART Line Status Register This register is used to show the status of UART interrupts and registers See UART Line Status Registers UARTO LSR 00C5h UART1_LSR 00D5h Table 65 UART Line Status Registers UARTO LSR 00C5h UART1 LSR 00D5h Bit 7 6 5 2 Reset 0 1 0 0 0 0 0 CPU Access R R R R Note R Read only Bit Position Value Description 7 0 Always 0 when operating in with the FIFO disabled With the ERR FIFO enabled this bit is reset when the UARTx_LSR register is read and there are no more bytes with error status in the FIFO 1 Error detected in the FIFO There is at least 1 parity framing or break indication error in the FIFO 6 0 Transmit holding register FIFO is not empty or transmit shift TEMT register is not empty or transmitter is not idle PS015308 0404 Transmit holding register FIFO and transmit shift register are empty and the transmitter is idle This bit cannot be set to 1 during the BREAK condition This bit only becomes 1 after the BREAK command is removed PRELIMINARY Universal Asynchronous Receiver Transmitter e
33. 0 I output l l l M EA E i l I d lt _T gt i r Tg E L T MREQ I A l l I 1 i l pe T gt Tig lt mu I WR l Figure 58 External Memory Write Timing PS015308 0404 PRELIMINARY Electrical Characteristics PS015308 0404 Table 150 External Write Timing eZ80F92 eZ80F93 Product Specification Zi ZiLOG Delay ns Parameter Abbreviation Min Max T4 Clock Rise to ADDR Valid Delay 13 T2 Clock Rise to ADDR Hold Time 2 0 T3 Clock Fall to Output DATA Valid Delay 11 T4 Clock Rise to DATA Hold Time 2 0 Ts Clock Rise to CSx Assertion Delay 2 0 19 0 Te Clock Rise to CSx Deassertion Delay 2 0 18 0 T Clock Rise to MREQ Assertion Delay 2 0 16 0 Tg Clock Rise to MREQ Deassertion Delay 2 0 16 0 To Clock Fall to WR Assertion Delay 1 8 6 5 T40 Clock Rise to WR Deassertion Delay 1 6 6 5 WR Deassertion to ADDR Hold Time 0 25 WR Deassertion to DATA Hold Time 0 25 WR Deassertion to CSx Hold Time 0 25 WR Deassertion to MREQ Hold Time 0 25 Note At the conclusion of a Write cycle deassertion of WR always occurs before any change to ADDR DATA CSx or MREQ PRELIMINARY Electrical Characteristics eZ80F92 eZ80F93 Product Specification 237 ZiLOG External I O Read Timing Figure 59 and External I O Read Timing diagram the timing for external I O Reads Clock rise fall to signal transition timing is i
34. 1 when a data byte is received and transferred to the UARTx_RBR register from the receiver shift register The DR bit is reset only when the processor reads all of the received data bytes If the number of bits received is less than eight the unused most significant bits of the data byte Read are 0 For 9 bit data the receiver checks incoming bytes for space parity This check routine gen erates a line status interrupt when an address byte is received because address bytes con tain mark parity bits The processor clears the interrupt determines if the address matches its own then configures the receiver to either accept the subsequent data bytes if the address matches or ignore the data if it does not The receiver uses the clock from the BRG for receiving the data This clock must be 16 times the appropriate baud rate The receiver synchronizes the shift clock on the falling edge of the RxD input start bit It then receives a complete byte according to the set parameters The receiver also implements logic to detect framing errors parity errors overrun errors and break signals UART Modem Control The modem control logic provides two outputs and four inputs for handshaking with the modem Any change in the modem status inputs except RI is detected and an interrupt can be generated For RI an interrupt is generated only when the trailing edge of the RI is detected The module also provides LOOP mode for self diagnostics UART Interrupt
35. 101 ZDI Bus Control Register ZDI BUS CTL 17h in the ZDI Register Write Only Address Space Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access W W W W W Note W Write Only Bit Position Value Description 7 0 Bus requests by external peripherals using the ZDI_BUSAK_EN BUSREQ pin are ignored The bus acknowledge signal BUSACK is not asserted in response to any bus requests 1 Bus requests by external peripherals using the BUSREQ pin are accepted A bus acknowledge occurs at the end of the current ZDI operation The bus acknowledge is indicated by asserting the BUSACK pin in response to a bus request 6 0 Deassert the bus acknowledge pin BUSACK to return ZDI_BUSAK control of the address and data buses back to ZDI 1 Assert the bus acknowledge pin BUSACK to pass control of the address and data buses to an external peripheral 5 0 000000 Reserved PS015308 0404 PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification 182 ZiLOG Instruction Store 4 0 Registers The ZDI Instruction Store registers are located in the ZDI Register Write Only address space They can be written with instruction data for direct execution by the CPU When the ZDI ISO register is written the eZ80F92 device exits the ZDI BREAK state and exe cutes a single instruction The Op Codes and operands for the instruction come from these Instruction Store reg
36. 126 G General Purpose Input Output 41 Control Registers 45 Interrupts 44 modes 42 43 Operation 41 Overview 41 Port Input Sample Timing 241 Port Output Timing 243 port pins 34 41 46 GND see Ground GPIO see General Purpose Input Output Ground 2 H HALT instruction 37 177 185 214 Op Code Map 216 HALT mode 1 11 37 38 227 228 232 HALT_SLP 11 handshake 106 147 high frequency system clock 136 I O Chip Select Operation 25 52 I O space 5 10 50 52 PC Acknowledge bit 144 148 150 152 153 157 IC bus 142 146 154 clock 142 protocol 143 PC Clock Control Register 161 PC Control Register 156 PC Data Register 156 C Extended Slave Address Register 155 PC General Characteristics 142 PC Registers 154 PS015308 0404 eZ80F92 eZ80F93 Product Specification Zi ZiLOG PC Serial Clock 20 24 142 144 161 PC Serial Data 20 PC Serial I O Interface 142 C Slave Address Register 154 IC Software Reset Register 162 PC Status Register 159 IEEE Standard 1149 1 190 191 IEF1 48 49 186 IEF2 48 49 IFLG bit 142 147 150 152 153 157 159 160 IM 0 Op Code Map 219 IM 1 Op Code Map 219 IM 2 Op Code Map 219 Information Page 196 197 200 205 207 209 Infrared Encoder Decoder 39 126 127 130 131 Register 131 Signal Pins 130 Input Output Request 10 11 22 53 55 56 58 59 62 Assertion Delay 237 238 Deassertion Delay 237 238 Hold Time 239 INSTRD see Instruction Read Instruction Read 11
37. 2 X SPI Baud Rate Generator Divisor SPI Data Rate bits s Upon RESET the 16 bit BRG divisor value resets to 0002h When the SPI is operating as a Master the BRG divisor value must be set to a value of 0003h or greater When the SPI is operating as a Slave the BRG divisor value must be set to a value of 0004h or greater A software Write to either the Low or High byte registers for the BRG Divisor Latch causes both the Low and High bytes to load into the BRG counter and causes the count to restart Data Transfer Procedure with SPI Configured as the Master 1 Load the SPI Baud Rate Generator Registers SPI BRG H and SPI BRG L 2 External device must deassert the SS pin if currently asserted 3 Load the SPI Control Register SPI CTL PS015308 0404 PRELIMINARY Serial Peripheral Interface eZ80F92 eZ80F93 Product Specification 137 ZiLOG 4 Assert the ENABLE pin of the slave device using a GPIO pin 5 Load the SPI Transmit Shift Register SPI_TSR 6 When the SPI data transfer is complete deassert the ENABLE pin of the slave device Data Transfer Procedure with SPI Configured as a Slave 1 Load the SPI Baud Rate Generator Registers SPI BRG H and SPI_BRG_L 2 Load the SPI Transmit Shift Register SPI TSR This load cannot occur while the SPI slave is currently receiving data 3 Wait for the external SPI Master device to initiate the data transfer by asserting SS SPI Registers PS015308 0404 There are
38. 5 D 5 E 5 H 5L 5 HL 5A E BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT 2 6 B 6 C 6 D 6 E 6 H 6L 6 HL 6A 7B 7C 7 D 7 E 7 H 7L 7 HL 7A a RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES 5 0 B 0 C 0 D 0 E 0 H OL O HL 0 A 1B 1 C 1D 4E 1 H 1 L 1 HL 1 4 Qa EI g RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES 2 B 2 C 2 D 2E 2 H 2L 2 HL 2A 3 B 3 C 3 D 3 E 3 H 3L 3 HL 3A A RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES 4B 4C 4D 4E 4 H 4L A4 HL 4A 5 B 5 C 5 D 5 E 5 H 5L 5 HL 5A g RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES 6 B 6 C 6 D 6 E 6 H 6L 6 HL 6A 7 B 7 C 7 D 7E 7 H 7L 7 HL 7A c SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET 0 B 0 C 0 D 0 E 0 H OL O HL 0 A 1B 1c 1D 4E 1 H 1 L 1 HL 1 4 p SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET 2 B 2 C 2 D 2E 2 H 2L 2 HL 2A 3 B 3C 3 D 3 E 3 H 3L 3 HL 3A g SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET 4B 4C 4D 4E 4 H 4L 4 HL 4A 5 B 5 C 5 D 5 E 5 H 5L 5 HL 5A p SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET 6 B 6 C 6 D 6 E 6 H 6L 6 HL 6A 7
39. 53 BUSREQ Bus Request Input Active Low External devices can request the CPU to release the memory interface bus for their use by driving this pin Low 54 BUSACK Bus Acknowledge Output Active Low The CPU responds to a Low on BUSREQ by tristating the address data and control signals and by driving the BUSACK line Low During bus acknowledge cycles ADDR 23 0 IORQ and MREQ are inputs 55 HALT SLP HALT and Output Active Low A Low on this pin indicates that the CPU SLEEP has entered either HALT or SLEEP mode Indicator because of execution of either a HALT or SLP instruction 56 VDD Power Supply Power Supply 57 Vss Ground Ground PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Continued Pin Symbol Function Signal Direction Description 58 RTC X Real Time Input This pin is the input to the low power Clock Crystal 32KHz crystal oscillator for the Real Time Input Clock 59 RTC_Xoyr Real Time Bidirectional This pin is the output from the low power Clock Crystal 32KHz crystal oscillator for the Real Time Output Clock This pin is an input when the RTC is configured to operate from 50 60 Hz input clock signals and the 32KHz crystal oscillator is disabled 60 RTC Vpp Real Time Power supply for the Real Time Clock and Clock Power associated 32KHz
40. 7 0 1Eh and MBASE I 7 0 irn The least significant byte is stored at the lower address When any one or more of the interrupt requests IRQs become active an interrupt request is generated by the interrupt controller and sent to the CPU The corresponding 8 bit inter rupt vector for the highest priority interrupt is placed on the 8 bit interrupt vector bus IVECT 7 0 The interrupt vector bus is internal to the eZ80F92 device and is therefore not visible externally The response time of the CPU to an interrupt request is a function of the current instruction being executed as well as the number of wait states being asserted The interrupt vector I 7 0 IVECT 7 0 is visible on the address bus ADDR 15 0 when the interrupt service routine begins The response of the CPU to a vectored interrupt on the eZ80F92 device is explained in Vectored Interrupt Operation Interrupt sources are required to be active until the interrupt service routine starts It is recommended that the Interrupt Page Address Register I value be changed by the user from its default value of 00h as this address can create conflicts between the nonmaskable interrupt vector the RST instruction addresses and the maskable interrupt vectors Table 12 Vectored Interrupt Operation Memory ADL MADL Mode Bit Bit Operation Z80 Mode 0 0 Read the LSB of the interrupt vector placed on the internal vectored interrupt bus IVECT 7 0 by the interrupting periphera
41. ADC dE MLT EB D BC BC D HL DE Wed IX d Al E C C E HL DE DE AR DE Mmn LD LD IBN OUT SBC TST PEA PEA IN OUT ADC MLT LD 6 Mmn RRD HL LDA MB RLD E H C BC H HLHL An IX d IY d L C OL HLHL aj HL MBA LD LD 2 SBC TSTIO IN OUT ADC MLT 2 7 Mmn SLP SP STMIX RSMIX a 2 HL SP Sp n A C OA HLSP quy SP amp 8 INIM OTIM INI2 INDM OTDM IND2 2 9 INIMR OTIMR INI2R INDMR OTDMR IND2R A LDI CPI INI OUTI OUTI2 LDD CPD IND OUTD OUTD2 B LDIR CPIR INIR OTIR OTI2R LDDR CPDR INDR OTDR OTD2R C INIRX OTIRX INDRX OTDRX D E F Notes n 8 bit data Mmn 16 or 24 bit addr or data d 8 bit two s complement displacement PS015308 0404 PRELIMINARY Op Code Map eZ80F92 eZ80F93 Product Specification 220 ZiLOG Table 140 Op Code Map Second Op Code After OFDh Legend Lower Nibble of 2nd Op Code Upper UE of Secon OpCode F Fy Mnemonic First Operand Second Operand Lower Nibble Hex 0 1 2 3 4 5 6 7 8 9 A B c D E F i LD BC ADD LD IY IY d lY BC d BC LD DE ADD LD IY IY d IY DE d DE LD m INC INC DEC LD LDHL ADD jy DEC INC DEC LD tb Y IY Mmn I ov YA IYH YHn Y 0 IYIY IY we IYL tn d HL Y Mmn i LD IX INC DEC LD IY LDN ADD LD IY LD IY IYd IY d IY d d n IY d IY SP d IX d IY L
42. Alarm Minutes Register RTC_AMIN 00E9h Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access RW RW RW RW RAN RW RW RW Note X Unchanged by RESET R W Read Write Binary Coded Decimal Operation BCD_EN 1 Bit Position Value Description 7 4 0 5 The tens digit of the alarm minutes value ATEN_MIN 3 0 0 9 The ones digit of the alarm minutes value AMIN Binary Operation BCD_EN 0 Bit Position Value Description 7 0 00h The alarm minutes value AMIN 3Bh PRELIMINARY Real Time Clock PS015308 0404 eZ80F92 eZ80F93 Product Specification Ll z ZiLOG Real Time Clock Alarm Hours Register This register contains the alarm hours value See Real Time Clock Alarm Hours Register RTC_AHRS 00EAh Table 49 Real Time Clock Alarm Hours Register RTC_AHRS 00EAh Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access RW RW RW RW RAN RW RW RW Note X Unchanged by RESET R W Read Write Binary Coded Decimal Operation BCD_EN 1 Bit Position Value Description 7 4 0 2 The tens digit of the alarm hours value ATEN_HRS 3 0 0 9 The ones digit of the alarm hours value AHRS Binary Operation BCD_EN 0 Bit Position Value Description 7 0 00h The alarm hours value AHRS 17h PRELIMINARY Real Time Clock PS015308 0404 eZ80F92 e
43. B pin when programmed as output can be selected to be an open drain or open source output T5 OUT Timer 5 Out Output Programmable Reload Timer 5 timer out signal This signal is multiplexed with PB5 94 PB6 GPIO Port B Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port B pin when programmed as output can be selected to be an open drain or open source output MISO Master In Slave Out Bidirectional The MISO line is configured as an input when the CPU is an SPI master device and as an output when CPU is an SPI slave device This signal is multiplexed with PB6 95 PB7 GPIO Port B Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port B pin when programmed as output can be selected to be an open drain or open source output MOSI Master Out Slave In Bidirectional The MOSI line is configured as an output when the CPU is an SPI master device and as an input when the CPU is an SPI slave device This signal is multiplexed with PB7 PS015308 0404 PRELIMINARY Architectural Overview 19 eZ80F92 eZ80F93 Product Specification VAF ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Contin
44. Binary Operation BCD EN 0 Bit Position Value Description 7 0 00h The current hours count HRS 17h PRELIMINARY Real Time Clock PS015308 0404 eZ80F92 eZ80F93 Product Specification L ZiLOG Real Time Clock Day of the Week Register This register contains the current day of the week count The RTC_DOW register begins counting at 01h See Real Time Clock Day of the Week Register RTC DOW 00E3h Table 42 Real Time Clock Day of the Week Register RTC DOW 00E3h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 X X X X CPU Access R R R R R W R AW R IW R W Note X Unchanged by RESET R Read Only R W Read Only if RTC locked Read Write if RTC unlocked Binary Coded Decimal Operation BCD_EN 1 Bit Position Value Description 7 4 0000 Reserved 3 0 1 7 The current day of the week count DOW Binary Operation BCD_EN 0 Bit Position Value Description 7 4 0000 Reserved 3 0 01h The current day of the week count DOW 07h PRELIMINARY Real Time Clock PS015308 0404 eZ80F92 eZ80F93 Product Specification 96 ZiLOG Real Time Clock Day of the Month Register This register contains the current day of the month count The RTC_DOM register begins counting at 01h See Real Time Clock Day of the Month Register RTC DOM 00EF4h Table 43 Real Time Clock Day of the Month Register RTC_DOM 00E4h
45. Byte 137 SPI Control Register 2 0 0 6 cle cade eee eee dete 139 SPI Baud Rate Generator Register High Byte 139 SPI Status Register Ji secedere ea e aer A ns 140 SPI Transmit Shift Register lesen 141 SPI Receive Buffer Register lesen 141 C Master Transmit Status Codes isses esee 148 PC Master Transmit Status Codes For Data BYt S Vos hee Rr es 149 PC 10 Bit Master Transmit Status Codes 0 0 00 eee ee 149 C Master Receive Status Codes 0 2 0 0 esses 150 IC Master Receive Status Codes For Data Bytes epe ees Res 152 PC Register Descriptions iioc et b per oes eR GER 154 IC Slave Address Regist tS 5 eye ee sd deer bee ne ERE 155 PC Data Registers MEC 156 C Extended Slave Address Registers lec eee 156 PC Control gu C RT 158 PC Status Repistefs 125 si sacdaicd pets deeds tad beta did x 159 JC Status Codes n naue n sUR ascen datu 159 PRELIMINARY List of Tables PS015308 0404 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 Table 109 Table 110 Table 111 Table 112 Table 113 Table 114 Table 115 Table 116 Table 117 Table 118 Table 119 eZ80F
46. HO pma BEBE Mma epe An 28h OEDh Op Code F RET POP i od PUSH OR RST RET LD ei os es CP RST P AF j AF A n 30h M SPHL pecOnCtD An 38h Mmn Mmn Mmn Mmn CodeAfter PS015308 0404 PRELIMINARY Op Code Map eZ80F92 eZ80F93 Product Specification ZiLOG Table 137 Op Code Map Second Op Code after OCBh Legend Lower Nibble of 2nd Op Code Upper j Nibble 4 of Secon OpCode A RES Mnemonic First Operand Second Operand Lower Nibble Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F o RLC RLC RLC RLC RLC RLC RLC RLC RRC RRC RRC RRC RRC RRC RRC RRC B C D E H L HL A B C D E H L HL A 4 RE RL RL RL RL RL RL RL RR RR RR RR RR RR RR RR B C D E H L HL A B C D E H L HL A 2 SLA SLA SLA SLA SLA SLA SLA SLA SRA SRA SRA SRA SRA SRA SRA SRA B C D E H L HL A B C D E H L HL A 3 SRL SRL SRL SRL SRL SRL SRL SRL B C D E H L HL A 4 BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT 0 B 0 C 0 D 0 E 0 H OL O HL OA 1B 1c 1D 4E 1 H 1 L 1 HL 1 4 5 BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT 2 B 2 C 2 D 2E 2 H 2L 2 HL 2A 3 B 3 C 3 D 3 E 3 H 3L 3 HL 3A e BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT g 4B 4C 4D 4E 4H 4L A4 HL 4A 5 B 5 C
47. ID Revision Register ZDI_ID_REV 02h in the ZDI Register Read Only Address Space Table 106 eZ80 Product ID Revision Register ZDI ID REV 02h in the ZDI Register Read Only Address Space Bit 7 6 5 4 3 2 1 0 Reset X X X X CPU Access R R R R R R R R Note X Undetermined R Read Only Bit Position Value Description 7 0 00h Identifies the current revision of the eZ80F92 product ZDI ID REV FFh ZDI Status Register The ZDI Status register provides current information on the eZ80F92 device See ZDI Sta tus Register ZDI STAT 03h in the ZDI Register Read Only Address Space Table 107 ZDI Status Register ZDI STAT 03h in the ZDI Register Read Only Address Space Bit 4 Reset 0 0 0 0 0 0 0 0 CPU Access R Note R Read Only Bit Position Value Description 7 0 The CPU is not functioning in ZDI mode Zone 1 The CPU is currently functioning in ZDI mode 6 0 Reserved 5 0 The CPU is not currently in HALT or SLEEP mode aj 1 The CPU is currently in HALT or SLEEP mode PRELIMINARY ZiLOG Debug Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification Ll ZiLOG Bit Position Value Description 4 0 The CPU is operating in Z80 MEMORY mode ADL ADL bit 0 1 The CPU is operating in ADL MEMORY mode ADL bit 1 3 0 The CPU s Mixed Memory mode MADL bit is reset
48. Low indicates that an access is occurring in the defined CS2 memory or I O address space 32 CS3 Chip Select 3 Output Active Low CS3 Low indicates that an access is occurring in the defined CS3 memory or I O address space 33 Power Supply Power Supply 34 Ground Ground 35 Data Bus Bidirectional The data bus transfers data to and from I O and memory devices The eZ80Acclaim drives these lines only during Write cycles when the CPU is the bus master 36 DATAT1 Data Bus Bidirectional The data bus transfers data to and from I O and memory devices The CPU drives these lines only during Write cycles when the CPU is the bus master PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Continued Pin Symbol Function Signal Direction Description 37 DATA2 Data Bus Bidirectional The data bus transfers data to and from I O and memory devices The CPU drives these lines only during Write cycles when the CPU is the bus master 38 DATA3 Data Bus Bidirectional The data bus transfers data to and from I O and memory devices The CPU drives these lines only during Write cycles when the CPU is the bus master 39 DATA4 Data Bus Bidirectional The data bus transfers data to and from I O and memory devices Th
49. MSR 00C6h UART1 MSR 00D6h Bit 7 6 5 4 3 2 1 0 Reset X x X CPU Access R R R R R R R R Note R Read only Bit Position Value Description 7 0 1 Data Carrier Detect DCD In NORMAL mode this bit reflects the inverted state of the DCDXx input pin In LOOP BACK mode this bit reflects the value of the UARTx MCTL 3 out2 6 0 1 Ring Indicator mE RI In NORMAL mode this bit reflects the inverted state of the RIx input pin In LOOP BACK mode this bit reflects the value of the UARTx MCTL 2 out1 5 0 1 Data Set Ready DSR In NORMAL mode this bit reflects the inverted state of the DSRx input pin In LOOP BACK mode this bit reflects the value of the UARTx MCTL 0 DTR 4 0 1 Clear To Send CTS In NORMAL mode this bit reflects the inverted state of the CTSx input pin In LOOP BACK mode this bit reflects the value of the UARTx MCTL 1 RTS PRELIMINARY Universal Asynchronous Receiver Transmitter PS015308 0404 eZ80F92 eZ80F93 Product Specification Ll ZiLOoOG Bit Position Value Description 3 0 1 Delta Status Change of DCD DDCD This bit is set to 1 whenever the DCDx pin changes state This bit is reset to 0 when the UARTx MSR register is read 2 0 1 Trailing Edge Change on RI TERI This bit is set to 1 whenever a falling edge is detected on the RIx pin This bit is reset to 0 when the UARTx MSR register is read 1 0 1 Delta
50. Memory Addressing Example 194 Recommended Crystal Oscillator Configuration 20MHz operation 223 Recommended Crystal Oscillator Configuration 32KHz operation 224 ICC Versus WAIT States as a Function of Frequency 229 ICC Versus Frequency as a Function of WAIT States 230 ICC Versus Temperature as a Function of Frequency 231 PRELIMINARY List of Figures vii PS015308 0404 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 eZ80F92 eZ80F93 Product Specification ICC Versus Frequency in HALT Mode 0 00 0 eana 232 ICC Versus Temperature in SLEEP Mode 0 233 External Memory Write Timing 0 0 0 0 eee eee ee eee 235 External I O Read Timing 0 0 0 cece ee eee 237 External I O Write Timing 0 0 0 cece eee eee 238 Wait State Timing for Read Operations 0 0 005 239 Wait State Timing for Write Operations 0 008 240 Port Input Sample Timing 0 0 0 eee eee 241 PRELIMINARY List of Figures eZ80F92 eZ80F93 Product Specification List of Tables PS015308 0404 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24
51. OVetvIeW descr cay eee ee eee ee nee eee eects wad Re e yea 41 GPIO Operation exco spo nia nda peta e eo Sa CE go oa eer a ota see 41 GPIO Interrupts o oe iui Se ee a de ee ee ee ee ee 44 GPIO Control Registers spee noc ten esac dee tee Ase ger ee eel ig 45 Interrupt Controller cero eR eia ea baa dnbie er este 47 Maskable Interrupts 0 0 cee enn n eens 47 Nonmaskable Interrupts 0 0 0 cece cece eee teenies 49 Chip Selects and Wait States llle 50 Memory and I O Chip Selects 0 0 0 eee eh 50 Memory Chip Select Operation 0 0 cee eee eee eee ene 50 I O Chip Select Operation 0 0 0 cece III 52 Walt States sc tiie gene eae id at eget oe ee oe ie bene dake Onde pelea E 53 WAIT Input Signal ec ot adele dade da Gia wade neta da eese 53 Chip Selects During Bus Request Bus Acknowledge Cycles 54 PS015308 0404 PRELIMINARY Table of Contents PS015308 0404 eZ80F92 eZ80F93 Product Specification ZiLOG Bus Mode Controller 2a tun ta bee cae Aas Le ee led Gaede nea 55 eZ80 Bus Mode cis es cee ee ee eee bbe ee hd n uber be ea be ee 55 Z80 Bus Mode cis ee RR ere Che aaa pdt eden a OE oie ete 55 Intel Bus Mode 5 debo ed weeded Hawes uaa vaa dose bc ate 57 Motorola Bus Mode 0 0 cece teen enna 65 Chip Select Registers ceecrege tiriti acta bedded ee pee e ope tend 69 Watch Dog Timer sssseseeeeeeeeee ehh re 74 Watch Dog Timer Overview 0 cee
52. Overview 78 Programming Flash Memory 198 pull up resistor external 42 142 PUSH Op Code Map 216 218 220 R RAM see Random Access Memory Random Access Memory 193 Address Upper Byte Register 195 Control Register 195 RD see Read instruction Read instruction 10 11 22 50 53 55 58 59 62 Assertion Delay 235 237 Deassertion Delay 235 237 Reading the Current Count Value 81 Real Time Clock 12 25 30 34 37 78 90 223 224 alarm condition 37 91 104 Alarm Control Register 104 Alarm Day of the Week Register 103 Alarm Hours Register 102 Alarm Minutes Register 101 alarm registers 91 Alarm Seconds Register 100 Battery Backup 91 Century Register 99 circuit 227 PRELIMINARY Index clock source 105 count 91 104 count registers 92 Control Register 104 Crystal Input 12 Crystal Output 12 Day of the Month Register 96 Day of the Week Register 95 Hours Register 94 Minutes Register 93 Month Register 97 Oscillator and Source Selection 91 Overview 90 Power Supply 12 Recommended Operation 91 Registers 92 Seconds Register 92 source 74 76 78 82 89 Supply Current 227 Supply Voltage 227 Year Register 98 Receive Infrared Encoder Decoder 127 Recommended Usage of the Baud Rate Generator 111 Register Map 25 Request To Send 13 16 122 124 130 RESET 10 11 22 34 35 37 38 42 50 74 76 91 92 104 111 113 131 136 137 175 177 190 191 193 195 203 205 228 Reset controller 34 35 RESET event 41 RESET mode t
53. PS015308 0404 The ZiLOG Debug Interface ZDI provides a built in debugging interface to the eZ80 CPU ZDI provides basic in circuit emulation features including Examining and modifying internal registers Examining and modifying memory Starting and stopping the user program Setting program and data BREAK points Single stepping the user program Executing user supplied instructions Debugging the final product with the inclusion of one small connector Downloading code into SRAM Csource level debugging using ZiLOG Developer Studio ZDS ID The above features are built into the silicon Control is provided via a two wire interface that is connected to the ZPAKII Debug Interface Tool Figure 36 illustrates a typical setup using a a target board ZPAKII and the host PC running ZiLOG Developer Studio Refer to the ZiLOG website for more information on ZPAKII and ZDSII Target Board C O N ZPAK N eZ80 Emulator C Product T O R Figure 36 Typical ZDI Debug Setup ZDI allows reading and writing of most internal registers without disturbing the state of the machine Reads and writes to memory may occur as fast as the ZDI can download and upload data with a maximum frequency of one half the CPU system clock frequency PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification zZ 164 ZiLOG Recommended ZDI Clock vs System Clock Frequency lists the recommended frequen cies of the ZDI
54. Reading the Flash Interrupt Control register clears all error condition flags and the done flag PS015308 0404 PRELIMINARY Flash Memory PS015308 0404 eZ80F92 eZ80F93 Product Specification L zr ZiLOG Table 121 Flash Interrupt Control Register FLASH_IRQ 00FBh Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RAW R W R R R R Note R W Read Write R Read Only Read resets bits 5 and 3 0 Bit Position Value Description 7 0 Flash Erase Row Program Done Interrupt is disabled DONE_IEN 1 Flash Erase Row Program Done Interrupt is enabled 6 0 Error Condition Interrupt is disabled EIRE AEN 1 Error Condition Interrupt is enabled 5 0 Erase Row Program Done Flag is not set DONE 1 Erase Row Program Done Flag is set 4 0 Reserved 3 0 The Write Violation Error Flag is not set vee 1 The Write Violation Error Flag is set 2 0 The Row Program Time out Error Flag is not set RP_TMO f B 1 The Row Program Time out Error Flag is set 1 0 The Page Erase Violation Error Flag is not set Pome 1 The Page Erase Violation Error Flag is set 0 0 The Mass Erase Violation Error Flag is not set MASS_VIO 4 The Mass Erase Violation Error Flag is set Flash Page Select Register The msb of this register is used to select whether all Flash access and Page Erases are directed to the 256 byte Information Page or to the main Flash m
55. Refer to the eZ80 CPU User Manual UM0077 for information regarding the CPU registers PRELIMINARY ZiLOG Debug Interface 178 PS015308 0404 Table 100 ZDI Read Write Control Register Functions eZ80F92 eZ80F93 Product Specification Zi ZiLOG ZDI RW CTL 16h in the ZDI Register Write Only Address Space Hex Hex Value Command Value Command 00 Read MBASE A F 80 Write AF ZDI RD U lt MBASE MBASE lt ZDI WR U ZDI RD H c F F ZDI WR H ZDI RD L A A lt ZDI WR L 01 Read BC 81 Write BC ZDI RD U BCU BCU ZDI WR U ZDI RD H B B lt ZDI WR H ZDI RDL C C e ZDI WR L 02 Read DE 82 Write DE ZDI RD U DEU DEU amp ZDI WR U ZDI RD H amp D D ZDI WR H ZDI RDL E E ZDI WR L 03 Read HL 83 Write HL ZDI RD U HLU HLU ZDI WR U ZDI RD H H H ZDI WR H ZDIRDL c L L ZDI WR L 04 Read IX 84 Write IX ZDI RD U lt IXU IXU ZDI WR U ZDI RD H IXH IXH ZDI WR H ZDI RD L IXL IXL ZDI WR L 05 Read IY 85 Write IY ZDI RD U amp IYU IYU ZDI WR U ZDI RD H IYH IYH ZDI WR H ZDI RD L amp IYL IYL ZDI WR L 06 Read SP 86 Write SP In ADL mode SP SPL In ADL mode SP SPL In Z80 mode SP SPS In Z80 mode SP SPS 07 Read PC 87 Write PC ZDI RD U c PC 23 16 PC 23 16 ZDI WR U ZDI RD H PC 15 8 PC 15 8 ZDI WR H ZDI RD L amp PC T7 0 PC 7 0 ZDI WR L 08 Set ADL 88 Reserved ADL lt 1 The eZ80 CPU
56. SPL stack Push a 00h byte onto the SPL stack to indicate an interrupt from Z80 mode because ADL 0 Set the ADL mode bit to 1 The interrupt vector address is located at 00h I 7 0 IVECT 7 0 PC 15 0 00h I 7 0 IVECT 7 0 The ending Program Counter is 00h PC 15 0 The interrupt service routine must end with RETI L ADL Mode 1 1 Read the LSB of the interrupt vector placed on the internal vectored interrupt bus IVECT 7 0 by the interrupting peripheral EF1 0 EF2 0 The Starting Program Counter is PC 23 0 Push the 3 byte return address PC 23 0 onto the SPL stack Push a 01h byte onto the SPL stack to indicate a restart from ADL mode because ADL 1 The ADL mode bit remains set to 1 The interrupt vector address is located at 00h I 7 0 IVECT 7 0 PC 15 0 00h I 7 0 IVECT 7 0 The ending Program Counter is 00h PC 15 0 The interrupt service routine must end with RETI L Nonmaskable Interrupts An active Low input on the NMI pin generates an interrupt request to the CPU This non maskable interrupt is always serviced by the CPU regardless of the state of the Interrupt Enable flags IEF1 and IEF2 The nonmaskable interrupt is prioritized higher than all maskable interrupts The response of the CPU to a nonmaskable interrupt is described in detail in the eZ80 CPU User Manual UM0077 PS015308 0404 PRELIMINARY Interrupt Controller eZ80F92 eZ80F93 Product
57. STOP condition START and STOP conditions are always generated by the master The bus is considered to be busy after the START condition The bus is considered to be free a defined time after the STOP condition E me i BO ee TC SDA Signal i l l l l l l I l SCL Signal Ta Y IS P l l l aia Ic START Condition STOP Condition Figure 32 START and STOP Conditions In I7C Protocol PS015308 0404 PRELIMINARY I2C Serial I O Interface eZ80F92 eZ80F93 Product Specification 144 ZiLOG Transferring Data Byte Format Every character transferred on the SDA line must be a single 8 bit byte The number of bytes that can be transmitted per transfer is unrestricted Each byte must be followed by an Acknowledge ACK Data is transferred with the most significant bit msb first See Figure 33 A receiver can hold the SCL line Low to force the transmitter into a wait state Data transfer then continues when the receiver is ready for another byte of data and releases SCL l i MSB Acknowledge from Acknowledge from i i Receiver Receiver SCL Signal f Jit 2 u 8 9 1 Ll 9N NO ACK HEC START Condition STOP Condition Clock Line Held Low By Receiver Figure 33 C Frame Structure Acknowledge Data transfer with an ACK function is obligatory The ACK related clock pulse is gener ated by the master The transmitter releases the SDA line High during the ACK clock pulse The receiver must pull down
58. Status Change of DSR DDSR This bit is set to 1 whenever the DSRx pin changes state This bit is reset to 0 when the UARTx_MSR register is read 0 0 1 Delta Status Change of CTS DCTS This bit is set to 1 whenever the CTSx pin changes state This bit is reset to O when the UARTx MSR register is read UART Scratch Pad Register The UARTx_SPR register can be used by the system as a general purpose Read Write reg ister See UART Scratch Pad Registers UARTO_SPR 00C7h UARTI SPR 00D7h Table 67 UART Scratch Pad Registers UARTO SPR 00C7h UART1 SPR 00D7h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RW RW RW RW RW RW RW RW Note R W Read Write Bit Position Value Description 7 0 00h The UART scratch pad register is available for use as a SPR FFh general purpose Read Write register PRELIMINARY Universal Asynchronous Receiver Transmitter eZ80F92 eZ80F93 Product Specification Ll ZiLOG Infrared Encoder Decoder The eZ80F92 device contains a UART to infrared encoder decoder endec The IrDA endec is integrated with the on chip UARTO to allow easy communication between the CPU and IrDA Physical Layer Specification Version 1 4 compatible infrared transceivers as illustrated in Figure 25 Infrared communication provides secure reliable high speed low cost point to point communication between PCs PDAs mobile telephones printers and
59. System Clock 3 3 ns Vpp 3 0 3 6V Fall Time TciK 50ns External Memory Read Timing Figure 57 and External Read Timing diagram the timing for external reads l l lt _ Terk lt _ T T l ADDR 23 0 l I l T5 lt gt T4 DATA 7 0 l input I I l LQ T P Te CSx l l l p T px Tg gt l ee l MREQ A I A l I lt Tg h RD l Figure 57 External Memory Read Timing PS015308 0404 PRELIMINARY Electrical Characteristics eZ80F92 eZ80F93 Product Specification Zi ZiLOG Table 149 External Read Timing Delay ns Parameter Abbreviation Min Max T4 Clock Rise to ADDR Valid Delay 13 T2 Clock Rise to ADDR Hold Time 2 0 T3 Input DATA Valid to Clock Rise Setup Time 1 0 T4 Clock Rise to DATA Hold Time 2 0 Ts Clock Rise to CSx Assertion Delay 2 0 19 0 Te Clock Rise to CSx Deassertion Delay 2 0 18 0 T7 Clock Rise to MREQ Assertion Delay 2 0 16 0 Tg Clock Rise to MREQ Deassertion Delay 2 0 16 0 To Clock Rise to RD Assertion Delay 2 0 16 0 T40 Clock Rise to RD Deassertion Delay 2 0 16 0 External Memory Write Timing Figure 58 and External Write Timing diagram the timing for external writes l l 1 Toi a I ji Xin l l I I I He T gt T H l wwa tT OOO KX l l I l l l T4 lt T DATA 7
60. Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 ZiLOG Clock Peripheral Power Down Register 1 00 0000 000 39 Clock Peripheral Power Down Register 2 0 0 00 0 eee eee 40 Port x Data Registers oues ate Qo he alate ha ede Rete 45 Port x Data Direction Registers 0 0 0 eee eee eee 46 Port x Alternate Registers 1 llleleeeee e 46 Port x Alternate Registers2 2 0 2 eee eA 46 Interrupt Vector Sources by Priority 47 Intel Bus Mode Read States llleleeeeeeeee 58 Intel Bus Mode Write States 0 0 0 ec eee 59 Intel Bus Mode Read States 20 0 cee cece eee 62 Intel Bus Mode Write States 62 Chip Select x Lower Bound Register 69 Chip Select x Upper Bound Register 0 0 0 0 000 eee eee 70 Chip Select x Control Register 0 0 0 eee eee eee 71 Chip Select x Bus Mode Control Register 000 72 Watch Dog Timer Approximate Time Out Delays 75 Watch Dog Timer Control Register 0 0 eee eee eee eee 76 Watch Dog Timer Reset Register 00 00 e eee eee TI PRT Single Pass Mode Operation Example 0 80 PRT Continuous Mode Operation Example 000 5 81 PRT Timer Out Operation Example 0 0 00 e eee eee eee 83 Timer Control Register 85 Timer Data Register Low Byte
61. W 161 00CD I2C_SRR C Software Reset Register XX W 162 Notes 1 After an external pin reset the Watch Dog Timer Control register is reset to OOh After a Watch Dog Timer time out reset the Watch Dog Timer Control register is reset to 20h 2 When the CPU reads this register the current sampled value of the port is read Read Only if RTC registers are locked Read Write if RTC registers are unlocked 3 4 After an external pin reset or a Watch Dog Timer reset the RTC Control register is reset to x0xxxxOOb After an RTC Alarm sleep mode recovery reset the RTC Control register is reset to X0xxxx10b 5 Read Only if Flash Memory is locked Read Write if Flash Memory is unlocked PS015308 0404 PRELIMINARY Register Map eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 3 Register Map Continued Address Reset CPU Page hex Mnemonic Name hex Access Universal Asynchronous Receiver Transmitter 1 UART1 Block 00DO UART1 RBR UART 1 Receive Buffer Register XX R 114 UART1 THR UART 1 Transmit Holding Register XX W 114 UART1_BRG_L UART 1 Baud Rate Generator Register 02 R W 112 Low Byte 00D1 UART1_IER UART 1 Interrupt Enable Register 00 R W 115 UART1_BRG_H UART 1 Baud Rate Generator Register 00 R W 113 High Byte 00D2 UART1_IIR UART 1 Interrupt Identification Register 01 R 116 UART1_FCTL UART 1 FIFO Control Register 00 W 117 00D3 UART1_LCTL UA
62. a completed transmission Upon this determination the application writes the pertinent transmit data bytes to the UARTx THR register The number of bytes that the application writes depends on whether or not the FIFO is enabled If the FIFO is enabled the applica tion can write 16 bytes at a time If not the application can write one byte at a time As a result of the first Write the interrupt is deactivated The processor then waits for the next interrupt When the interrupt is raised by the UART module the processor repeats the same process until it exhausts all of the data for transmission To control and check the modem status the application sets up the modem by writing to the UARTx MCTL register and reading the UARTx_MCTL register before starting the process mentioned above Receive The receiver is always enabled and it continually checks for the start bit on the RxD input signal When an interrupt is raised by the UART module the application reads the UARTx IIR register and determines the cause for the interrupt If the cause is a line status interrupt the application reads the UARTx LSR register reads the data byte and PRELIMINARY Universal Asynchronous Receiver Transmitter eZ80F92 eZ80F93 Product Specification zZ 111 ZiLOG then can discard the byte or take other appropriate action If the interrupt is caused by a receive data ready condition the application alternately reads the VARTx_LSR and UARTx_RBR registers and r
63. also be stretched for handshaking purposes This can be done after each bit transfer or each byte transfer The C stretches the clock after each byte transfer until the IFLG bit in the I2C_CTL register is cleared Bus Arbitration Overview In MASTER mode the C checks that each transmitted logic 1 appears on the IC bus as a logic 1 If another device on the bus overrules and pulls the SDA signal Low arbitration is lost If arbitration is lost during the transmission of a data byte or a Not Acknowledge bit the I7C returns to the idle state If arbitration is lost during the transmission of an address the I7C switches to SLAVE mode so that it can recognize its own slave address or the general call address PRELIMINARY I2C Serial I O Interface eZ80F92 eZ80F93 Product Specification 143 ZiLOG Data Validity The data on the SDA line must be stable during the High period of the clock The High or Low state of the data line can only change when the clock signal on the SCL line is Low as illustrated in Figure 31 SCL Signal Data Line Change of l Stable DataAllowed l Data Valid I Figure 31 17C Clock and Data Relationship START and STOP Conditions Within the C bus protocol unique situations arise which are defined as START and STOP conditions See Figure 32 A High to Low transition on the SDA line while SCL is High indicates a START condition A Low to High transition on the SDA line while SCL is High defines a
64. are successfully transmitted After this interrupt is serviced and the second part of the 10 bit address is transmitted the I2C SR register contains one of the codes in PC 10 Bit Master Transmit Status Codes PS015308 0404 PRELIMINARY I2C Serial I O Interface PS015308 0404 Table 80 PC 10 Bit Master Transmit Status Codes eZ80F92 eZ80F93 Product Specification Ll u ZiLOG Code 1C State Microcontroller Response Next IC Action 38h Arbitration lost Clear IFLG Return to idle Or set STA clear IFLG Transmit START when bus free 68h Arbitration lost Clear IFLG clear AAK 0 Receive data byte SLA W received transmit NACK pe Menem ee Or clear IFLG set AAK 1 Receive data byte transmit ACK BOh Arbitration lost Write byte to DATA Transmit last byte SLA R received clear IFLG clear AAK 0 receive ACK ATIS BRUSIIHSO Or write byte to DATA Transmit data byte clear IFLG set AAK 1 receive ACK DOh Second Address byte Write byte to DATA Transmit data byte W transmitted clear IFLG receive ACK AGK TeceNgd Or set STA clear IFLG Transmit repeated START Or set STP clear IFLG Transmit STOP Or set STA amp STP Transmit STOP then clear IFLG START D8h Second Address byte Same as code DOh Same as code DOh W transmitted ACK not received If a repeated START condition is transmitted the status code is 10h instead of 08h After each data byte is transmitted the IFLG is 1 and one of the
65. asynchronous communi cation protocol bits to the data byte being transmitted The transmitter block obtains the parameters for the protocol from the bits programmed via the UARTx LCTL register When enabled an interrupt is generated after the most recent protocol bit is transmitted which the processor may reset by loading data into the UARTx THR register The TxD output is set to 1 if the transmitter is idle it does not contain any data to be transmitted The transmitter operates with the Baud Rate Generator BRG clock The data bits are placed on the TxD output one time every 16 BRG clock cycles The transmitter block also implements a parity generator that attaches the parity bit to the byte if programmed For PRELIMINARY Universal Asynchronous Receiver Transmitter eZ80F92 eZ80F93 Product Specification 108 ZiLOG 9 bit data the host processor programs the parity bit generator so that it marks the byte as either address mark parity or data space parity UART Receiver The receiver block controls the data reception from the RxD signal The receiver block implements a receiver shift register receiver line error condition monitoring logic and Receiver Data Ready logic It also implements the parity checker The UARTx RBR is a Read Only register of the module The processor reads received data from this register The condition of the UARTx RBR register is monitored by the DR bit bit 0 of the UARTx LSR register The DR bit is
66. cee cent ene nee 74 Watch Dog Timer Operation 0 0 eee ene eens 75 Watch Dog Timer Registers llleeeeeeeee I 76 Programmable Reload Timers 0 0 cece cece e 78 Programmable Reload Timers Overview lees 78 Programmable Reload Timer Operation 0 0 0 cece eee eee ee 79 Programmable Reload Timer Registers 0 0 cece ee eee eee ee 83 Real Time Clock 125 a bye ER ep Od aac seno bie wets 90 Real Time Clock Overview eeseeeee eh 90 Real Time Clock Alarm seseeeeeeee III 91 Real Time Clock Oscillator and Source Selection 00005 91 Real Time Clock Battery Backup 0 0 0 c cece cece ee eee 91 Real Time Clock Recommended Operation 0 0 0 0 c eee eee eee 91 Real Time Clock Registers 0 0 0 cece III 92 Universal Asynchronous Receiver Transmitter 0 0 0 0c eee eee eee 106 UART Functional Description 0 0 0 eens 107 UART Functiolns re Ree RICE boe ooo Pate P areae 107 UART Intemupts pp eee tub Deomm e epe baee peo Dacos odia 108 UART Recommended Usage sssseeeeee ee 110 Baud Rate Generator 0 66 duele E oet pk wer p e EUR ERE dela aod 111 BRG Control Registers lleleeeleeeee eens 112 UART RESIST os eee eR Ree o e aaa nea ace aped ee bis 113 Infrared Encoder Decoder 0 0 eect eee 126 Functional Description i cis odo kd REG ek Gk Gb er eb EP DEUX gU Obr 126 kcu MT 127 RECE
67. clock in relation to the system clock Table 93 Recommended ZDI Clock vs System Clock Frequency System Clock ZDI Clock Frequency Frequency 3 10Mhz 1Mhz 8 16Mhz 2Mhz 12 24Mhz 4Mhz 20 50 Mhz 8Mhz ZDI Supported Protocol ZDI supports a bidirectional serial protocol The protocol defines any device that sends data as the transmitter and any receiving device as the receiver The device controlling the transfer is the master and the device being controlled is the slave The master always ini tiates the data transfers and provides the clock for both receive and transmit operations The ZDI block on the eZ80F92 device is considered a slave in all data transfers Figure 37 illustrates the schematic for building a connector on a target board This connec tor allows the user to connect directly to the ZPAKII debugger using a six pin header TVpp Target Vpp eZ80L92 6 Pin Target Connector E Figure 37 Schematic For Building a Target Board ZPAKII Connector ZDI Clock and Data Conventions The two pins used for communication with the ZDI block are the ZDI Clock pin ZCL and the ZDI Data pin ZDA On the eZ80F92 device the ZCL pin is shared with the TCK pin while the ZDA pin is shared with the TDI pin The ZCL and ZDA pin functions are PS015308 0404 PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification 165 ZiLOG only available when the On Chip Instrumentation is disabled and the ZDI is ther
68. drives the address onto the address bus the associated Chip Select signal is asserted and the data is driven onto the data bus The CPU drives the ALE signal High at the beginning of T1 During the middle of T1 the CPU drives ALE Low to facilitate the latching of the address STATE T2 During State T2 the CPU asserts the WR signal Depending on the instruction either the MREQ or IORQ signal is asserted STATE T3 During State T3 no bus signals are altered If the external READY WAIT pin is driven Low at least one CPU system clock cycle prior to the beginning of State T3 additional WAIT states Twat are asserted until the READY pin is driven High STATE T4 The CPU deasserts the WR signal at the beginning of State T4 The CPU holds the data and address buses through the end of T4 The bus cycle is completed at the end of T4 Intel bus mode timing is illustrated for a Read operation in Figure 12 and for a Write oper ation in Figure 13 If the READY signal external WAIT pin is driven Low prior to the beginning of State T3 additional wait states TywAjT are asserted until the READY signal is driven High The Intel bus mode states can be configured for 2 to 15 CPU system clock cycles In the figures each Intel bus mode state is 2 CPU system clock cycles in dura tion Figures 12 and 13 also illustrate the assertion of one WAIT state TwArr by the selected peripheral PS015308 0404 PRELIMINARY Chip Selects and Wait S
69. general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port D pin when programmed as output can be selected to be an open drain or open source output Port D is multiplexed with one UART CTSO Clear To Send Input Active Low Modem status signal to the UART This signal is multiplexed with PD3 72 PD4 GPIO Port D Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port D pin when programmed as output can be selected to be an open drain or open source output Port D is multiplexed with one UART DTRO Data Terminal Ready Output Active Low Modem control signal to the UART This signal is multiplexed with PD4 73 PD5 GPIO Port D Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port D pin when programmed as output can be selected to be an open drain or open source output Port D is multiplexed with one UART DSRO Data Set Ready Input Active Low Modem status signal to the UART This signal is multiplexed with PD5 74 PD6 GPIO Port D Bidirectional This pin can be used for general purpose O It can be individually programmed as
70. input or output and can also be used individually as an interrupt input Each Port D pin when programmed as output can be selected to be an open drain or open source output Port D is multiplexed with one UART DCDO Data Carrier Detect Input Active Low Modem status signal to the UART This signal is multiplexed with PD6 PS015308 0404 PRELIMINARY Architectural Overview 14 eZ80F92 eZ80F93 Product Specification ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Continued Pin Symbol Function Signal Direction Description 75 PD7 GPIO Port D Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port D pin when programmed as output can be selected to be an open drain or open source output Port D is multiplexed with one UART RIO Ring Indicator Input Active Low Modem status signal to the UART This signal is multiplexed with PD7 76 PCO GPIO Port C Bidirectional This pin can be used for general purpose l O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port C pin when programmed as output can be selected to be an open drain or open source output Port C is multiplexed with one UART TxD1 Transmit Data Output This pin is used by the U
71. mode MBASE PC 15 0 lt 8 bits of transferred data In ADL MEMORY mode PC 23 0 8 bits of transferred data PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification VAR ZiLOG eZ80 Product ID Low and High Byte Registers The eZ80 Product ID Low and High Byte registers combine to provide a means for an external device to determine the particular eZ80Acclaim ai product being addressed See Tables 104 and 105 Table 104 eZ80 Product ID Low Byte Register ZDI ID L 00h in the ZDI Register Read Only Address Space Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 1 1 1 CPU Access R R R R R R R R Note R Read Only Bit Position Value Description 7 0 07h ZDI ID H ZDI ID Lj 00h 07h indicates the ZDI ID L eZ80F92 product Table 105 eZ80 Product ID High Byte Register ZDI ID H 01h in the ZDI Register Read Only Address Space Bit Reset CPU Access Note R Read Only eo o o eo eo eo eo o Bit Position Value Description 7 0 00h ZDI ID H ZDI ID Lj 00h 07h indicates the ZDI ID H eZ80F92 product PS015308 0404 PRELIMINARY ZiLOG Debug Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification 185 ZiLOG eZ80 Product ID Revision Register The eZ80 Product ID Revision register identifies the current revision of the eZ80F92 prod uct See eZ80 Product
72. more information UN Caution During SLEEP mode the CPU freezes the last address and drives the address bus with this value The GPIO ports remain as configured by the user Prior to entering SLEEP mode the data bus is driven Low and the control signals MREQ CS3 0 INSTRD BUSACK IOREQ RD and WR are driven High HALT Mode Execution of the CPU s HALT instruction places the eZ80F92 device into HALT mode In HALT mode the operating characteristics are PS015308 0404 PRELIMINARY Low Power Modes eZ80F92 eZ80F93 Product Specification zZ 38 ZiLOG Primary crystal oscillator is enabled and continues to operate The system clock is enabled and continues to operate The CPU is idle The Program Counter PC stops incrementing The CPU can be brought out of HALT mode by any of the following operations Anonmaskable interrupt NMI Amaskable interrupt ARESET via the external RESET pin driven Low A Watch Dog Timer time out if configured to generate either an NMI or RESET upon time out ARESET via execution of a Debug RESET command To minimize current in HALT mode the system clock should be disabled for all unused on chip peripherals via the Clock Peripheral Power Down Registers UN Caution During HALT mode the CPU freezes the last address and drives the address bus with this value The GPIO Ports remain as configured by the user Prior to enter ing HALT mode the data bus is driven Low and the control s
73. ninth cycle and holds the ZCL signal High ZDI Data In ZDI Data In Write Write j j i Start Signal Figure 38 ZDI Write Timing PS015308 0404 PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification Z 166 ZiLOoOG ZDI Data Out ZDI Data Out Read Read f j l l l l l l l I l l zu Nf Nf NA l l l l l l l l l l l l i i i i i l l l l Start Signal Figure 39 ZDI Read Timing ZDI Single Bit Byte Separator Following each 8 bit ZDI data transfer a single bit byte separator is used To initiate a new ZDI command the single bit byte separator must be High logical 1 to allow for a new ZDI START command to be sent For all other cases the single bit byte separator can be either Low logical 0 or High logical 1 When ZDI is configured to allow the CPU to accept external bus requests the single bit byte separator should be Low logical 0 during all ZDI commands This Low value indicates that ZDI is still operating and is not ready to relinquish the Bus The CPU does not accept the external bus requests until the single bit byte separator is a High logical 1 For more information on accepting bus requests in ZDI DEBUG mode please see the Bus Requests During ZDI DEBUG Mode section on page 170 ZDI Register Addressing PS015308 0404 Following a START signal the ZDI master must output the ZDI register address All data transfers with the ZDI block use special ZDI reg
74. other infrared enabled devices eZ80F92 I I I System l Infrared Clock I Transceiver I RxD I RxD Infrared Baud Rate Encoder Decoder Clock TxD Interrupt I O Data I O Data Signal Address Address To eZ80 CPU Figure 25 Infrared System Block Diagram Functional Description When the IrDA endec is enabled the transmit data from the on chip UART is encoded as digital signals in accordance with the IrDA standard and output to the infrared transceiver Likewise data received from the infrared transceiver is decoded by the endec and passed to the UART Communication is half duplex meaning that simultaneous data transmission and reception is not allowed The baud rate is set by the UART Baud Rate Generator and supports IrDA standard baud rates from 9600bps to 115 2 kbps Higher baud rates than 115 2kbps are possible but do not meet IrDA specifications for these data rates The UART must be enabled to use the PS015308 0404 PRELIMINARY Infrared Encoder Decoder eZ80F92 eZ80F93 Product Specification ZiLOG endec Refer to the Universal Asynchronous Receiver Transmitter section on page 106 for more information on the UART and its Baud Rate Generator Transmit Baud Rate Clock UART_TxD The data to be transmitted via the IR transceiver is first sent to UARTO The UART trans mit signal TxD and Baud Rate Clock are used by the IrDA endec to generate the modu lation signal IR TxD that drives the infrared tran
75. output Slave Select Input Active Low The slave select input line is used to select a slave device in SPI mode This signal is multiplexed with PB2 91 PB3 GPIO Port B Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port B pin when programmed as output can be selected to be an open drain or open source output SCK SPI Serial Clock Bidirectional SPI serial clock This signal is multiplexed with PB3 PS015308 0404 PRELIMINARY Architectural Overview 18 eZ80F92 eZ80F93 Product Specification ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Continued Pin Symbol Function Signal Direction Description 92 PB4 GPIO Port B Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port B pin when programmed as output can be selected to be an open drain or open source output T4_OUT Timer 4 Out Output Programmable Reload Timer 4 timer out signal This signal is multiplexed with PB4 93 PBS GPIO Port B Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port
76. pin TDO Data Out Output The output data changes on the falling edge of the TCK signal TRIGOUT Trigger Output PS015308 0404 Output Generates an active High trigger pulse when valid OCI trigger events occur Output is tristate when no data is being driven out PRELIMINARY On Chip Instrumentation 191 eZ80F92 eZ80F93 Product Specification zZ 192 ZiLOG OCI Information Requests PS015308 0404 For additional information regarding On Chip Instrumentation or to order OCI debug tools please contact First Silicon Solutions Inc 5440 SW Westgate Drive Suite 240 Portland OR 97221 Phone 503 292 6730 Fax 503 292 5840 www fs2 com PRELIMINARY On Chip Instrumentation eZ80F92 eZ80F93 Product Specification 193 ZiLOG Random Access Memory PS015308 0404 The eZ80F92 features 8KB 8192 bytes single port data Random Access Memory RAM for general purpose use The eZ80F93 features 4KB 4096 bytes general purpose RAM RAM can be enabled or disabled and it can be relocated to the top of any 64KB page in memory Data is passed to and from RAM via the 8 bit data bus On chip RAM operates with zero WAIT states For the eZ80F92 RAM occupies memory addresses in the range RAM_ADDR_U 7 0 E000h to RAM_ADDR_U 7 0 FFFFh Following a RESET RAM is enabled with RAM_ADDR_U set to FFh Figure 45 illustrates a memory map of on chip RAM In this example the RAM Address Upper Byte register RAM_
77. pins and their func tions 55 BQOOOy 22 BREE a a ssergigce lmslalalole s J L uw arcoou0doq on2s5 naNO TOA AAMMAANMANAMAADCZAOVDVOOVCO0ODO oonon gt 0t0 0n n0 00n 0 00n x nun naoannunuonlsan ODMDAR QD LO t CO CN QO O OO rl QO 010 t CO CN QOO O 0O rl O ADDR1 2 74 PD6 DCDO ADDR2 3 73 PD5 DSRO ADDR3 4 72 PD4 DTRO ADDR4 5 71 PD3 CTSO ADDR5 6 70 PD2 RTSO Vpp 7 69 PD1 RxDO IR RxD Veg 8 68 PDO TxDO IR_TxD ADDR6 9 67 Vpp ADDR7 10 66 TDO ADDRS 11 65 TDI ADDRS 12 64 TRIGOUT ADDR10 13 100 Pin LQFP 63 TCK ADDR11 14 62 TMS ADDR12 15 61 Vss ADDR13 16 60 RTC Vpp ADDR14 17 59 RTC_XOUT Vpp 18 58 RTC_XIN Vss 19 57 Vss ADDR15 20 56 VDD ADDR16 21 55 HALT_SLP ADDR17 22 54 BUSACK ADDR18 23 53 BUSREQ ADDR19 24 52 NMI ADDR20 2 on co o o cw o x 0 9 ro 9 o v o0 x 10 i o o o 31 RESET CN CN CN CN CO CO CO CO C CO CO cO cO OTA SF SE SF SF SE SE SF SF wo CAMOrHIAIM AROTANTNON acco ciajicjaji 2 8 S888 Se ge E ZEER SAR els Q Q Q qgagaqaqaqaqaqaqaada gt z Figure 2 100 Pin LQFP Configuration of the eZ80F92 Device PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Pin Symbol Function Signal Direction Description 1 ADDRO Address Bus Bidirectional Configured as an outpu
78. provides control of the eZ80F92 device It is capable of forcing a RESET and waking up the eZ80F92 device from the low power modes HALT or SLEEP See ZDI Master Control Register ZDI MASTER CTL 11h in ZDI Regis ter Write Address Spaces Table 98 ZDI Master Control Register ZDI MASTER CTL 11h in ZDI Register Write Address Spaces Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access W W W W W W W Note W Write Only A Value Description 7 0 No action eel 1 Initiate a RESET of the CPU This bit is automatically cleared at the end of the RESET event 6 0 0000000 Reserved PRELIMINARY ZiLOG Debug Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification ZiLOG ZDI Write Data Registers These three registers are used in the ZDI Write Only register address space to store the data that is written when a Write instruction is sent to the ZDI Read Write Control register ZDI RW CTL The ZDI Read Write Control register is located at ZDI address 16h immediately following the ZDI Write Data registers As a result the ZDI Master is allowed to write the data to ZDI_WR_U ZDI_WR_H ZDI WR L and the Write com mand in one data transfer operation See ZDI Write Data Registers ZDI_WR_U 13h ZDI_WR_H 14h and ZDI_WR_L 15h in the ZDI Register Write Only Address Space Table 99 ZDI Write Data Registers ZDI WR U 13h ZDI WR H 14h and ZDI WR L 15h in th
79. receiver time out interrupt is generated it is cleared only after emptying the entire receive FIFO The first two interrupt sources from the receiver data ready and time out share an inter rupt enable bit The third source of a receiver interrupt is a line status error indicating an error in byte reception This error may result from Incorrect received parity For 9 bit data incorrect parity indicates detection of an address byte Incorrect framing that is the stop bit is not detected by receiver at the end of the byte Receiver over run condition ABREAK condition being detected on the receive data input An interrupt due to one of the above conditions is cleared when the UARTx LSR register is read In FIFO mode a line status interrupt is generated only after the received byte with an error reaches the top of the FIFO and is ready to be read A line status interrupt is activated provided this interrupt is enabled as long as the Read pointer of the receiver FIFO points to the location of the FIFO that contains a byte with the error The interrupt is immediately cleared when the UARTx_LSR register is read The ERR bit of the UARTx LSR register is active as long as an erroneous byte is present in the receiver FIFO UART Modem Status Interrupt The modem status interrupt is generated if there is any change in state of the modem status inputs to the UART This interrupt is cleared when the processor reads the UARTx MSR registe
80. register bit pertinent to the pin to be configured For example the operating mode for Port B Pin 7 PB7 is set by the values contained in PB DR 7 PB DDR 7 PB ALT1 7 and PB ALT2 7 The combination of the GPIO control register bits allows individual configuration of each port pin for nine modes In all modes reading of the Port x Data register returns the sam pled state or level of the signal on the corresponding pin GPIO Mode Selection indicates the function of each port signal based upon these four register bits After a RESET event all GPIO port pins are configured as standard digital inputs with interrupts disabled Table 6 GPIO Mode Selection GPIO Px ALT2 Px ALT1 Px DDR Px DR Mode Bits7 0 Bits7 0 Bits7 0 Bits7 0 Port Mode Output 1 0 0 0 0 Output 0 0 0 0 1 Output 1 2 0 0 1 0 Input from pin High impedance 0 0 1 1 Input from pin High impedance PS015308 0404 PRELIMINARY General Purpose Input Output eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 6 GPIO Mode Selection Continued GPIO Px ALT2 Px_ALT1 Px DDR Px DR Mode Bits7 0 Bits7 0 Bits7 0 Bits7 0 Port Mode Output 3 0 1 0 0 Open drain output 0 0 1 0 1 Open drain I O High impedance 4 0 1 1 0 Open source I O High impedance 0 1 1 1 Open source output 1 1 0 0 0 Reserved High impedance 1 0 0 1 Interrupt dual edge triggered High impedance 1 0 1 0 Port B C or D alternate function contro
81. register is reset to xOxxxx10b 5 Read Only if Flash Memory is locked Read Write if Flash Memory is unlocked PS015308 0404 PRELIMINARY Register Map eZ80 eZ80F92 eZ80F93 Product Specification ZiLOG CPU Core The eZ80 is the first 8 bit CPU to support 16MB linear addressing Each software mod ule or task under a real time executive or operating system can operate in Z80 compatible 64KB mode or full 24 bit 16 MB address mode The CPU instruction set is a superset of the instruction sets for the Z80 and Z180 CPUs Z80 and Z180 programs can be executed on an eZ80 CPU with little or no modification Features PS015308 0404 Code compatible with Z80 and Z180 products 24 bit linear address space Single cycle instruction fetch Pipelined fetch decode and execute Dual Stack Pointers for ADL 24 bit and Z80 16 bit memory modes 24 bit CPU registers and ALU Arithmetic Logic Unit Debug support Nonmaskable Interrupt NMI plus support for 128 maskable vectored interrupts For more information on the eZ80 CPU and its instruction set please refer to the eZ80 CPU User Manual UM0077 For eZ80Acclaim programming considerations please refer to the ZiLOG TCP IP Software Suite Programmer s Guide RM0008 available upon registering your eZ80F92 or eZ80F93 product on www zilog com PRELIMINARY eZ80 CPU Core 33 eZ80F92 eZ80F93 Product Specification Lla ZiLOG Reset Reset Oper
82. s alternate register set A F B C D E HL cannot be read directly The ZDI programmer must execute the exchange instruction EXX to gain access to the alternate eZ80 CPU register set PRELIMINARY ZiLOG Debug Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification Ll x ZiLOG Table 100 ZDI Read Write Control Register Functions ZDI RW CTL 16h in the ZDI Register Write Only Address Space Continued Hex Hex Value Command Value Command 09 Reset ADL 89 Reserved ADL 0 0A Exchange CPU register sets 8A Reserved AF lt AF BC BC DE DE HL HL OB Read memory from current 8B Write memory from current PC PC value increment PC value increment PC The eZ80 CPU s alternate register set A F B C D E HL cannot be read directly The ZDI programmer must execute the exchange instruction EXX to gain access to the alternate eZ80 CPU register set PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification L w ZiLOG ZDI Bus Control Register The ZDI Bus Control register controls bus requests during DEBUG mode It enables or disables bus acknowledge in ZDI DEBUG mode and allows ZDI to force assertion of the BUSACK signal This register should only be written during ZDI DEBUG mode that is following a BREAK See ZDI Bus Control Register ZDI_BUS_CTL 17h in the ZDI Register Write Only Address Space Table
83. six registers in the Serial Peripheral Interface which provide control status and data storage functions The SPI registers are described in the following paragraphs SPI Baud Rate Generator Registers Low Byte and High Byte These registers hold the Low and High bytes of the 16 bit divisor count loaded by the pro cessor for baud rate generation The 16 bit clock divisor value is returned by SPI_BRG_H SPI_BRG_L Upon RESET the 16 bit BRG divisor value resets to 0002h When configured as a Master the 16 bit divisor value must be between 0003h and FFFFh inclusive When configured as a Slave the 16 bit divisor value must be between 0004h and FFFFh inclusive A Write to either the Low or High byte registers for the BRG Divisor Latch causes both bytes to be loaded into the BRG counter and the count restarted See Tables 73 and 74 Table 73 SPI Baud Rate Generator Register Low Byte SPI BRG L 00B8h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 1 0 CPU Access RAV RW RW RW RAN RW RW RW Note R W Read Write Bit Position Value Description 7 0 00h These bits represent the Low byte of the 16 bit Baud Rate SPI BRGL FFh Generator divider value The complete BRG divisor value is returned by SPI BRG H SPI BRG Lj PRELIMINARY Serial Peripheral Interface eZ80F92 eZ80F93 Product Specification zZ 138 ZiLOG PS015308 0404 PRELIMINARY Serial Peripheral Interf
84. the Low Byte function of the ZDI Address Match 1 registers is disabled If BRK_ADDR1 is set to 1 ZDI initiates a BREAK when the entire 24 bit address ADDR 23 0 matches the 3 byte value ZDI ADDR1 U ZDI ADDR1 H ZDI ADDR1 Lj 1 The gnore the Low Byte function of the ZDI Address Match 1 registers is enabled If BRK ADDRI is set to 1 ZDI initiates a BREAK when only the upper 2 bytes of the 24 bit address ADDR 23 8 match the 2 byte value ZDI ADDR1 U ZDI ADDR1 HJ As a result a BREAK can occur anywhere within a 256 byte page ign low O0 0 The Ignore the Low Byte function of the ZDI Address Match 1 registers is disabled If BRK ADDRO is set to 1 ZDI initiates a BREAK when the entire 24 bit address ADDR 23 0 matches the 3 byte value ZDI ADDRO U ZDI ADDRO H ZDI ADDRO L 1 The gnore the Low Byte function of the ZDI Address Match 1 registers is enabled If the BRK ADDR 1 is set to 0 ZDI initiates a BREAK when only the upper 2 bytes of the 24 bit address ADDR 23 8 match the 2 bytes value ZDI ADDRO U ZDI_ADDRO_H As a result a BREAK can occur anywhere within a 256 byte page 0 single step 0 ZDI SINGLE STEP mode is disabled 1 ZDI SINGLE STEP mode is enabled ZDI asserts a BREAK following execution of each instruction PRELIMINARY ZiLOG Debug Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification Z4 ZiLOG ZDI Master Control Register The ZDI Master Control register
85. the MISO pin After transfer the SCK signal idles In SPI SLAVE mode the start logic receives a logic Low from the SS pin and a clock input at the SCK pin and the slave is synchronized to the master Data from the master is received serially from the slave MOSI signal and loads the 8 bit shift register After the 8 bit shift register is loaded its data is parallel transferred to the Read buffer During a Write cycle data is written into the shift register then the slave waits for the SPI master to initiate a data transfer supply a clock signal and shift the data out on the slave s MISO signal If the CPHA bit in the SPI_CTL register is 0 a transfer begins when SS pin signal goes Low and the transfer ends when SS goes High after eight clock cycles on SCK When the CPHA bit is set to 1 a transfer begins the first time SCK becomes active while SS is Low and the transfer ends when the SPIF flag gets set SPI Flags PS015308 0404 Mode Fault The Mode Fault flag MODF indicates that there may be a multimaster conflict for sys tem control The MODF bit is normally cleared to 0 and is only set to 1 when the master device s SS pin is pulled Low When a mode fault is detected the following occurs 1 The MODF flag SPI SR 4 is set to 1 2 The SPI device is disabled by clearing the SPI EN bit SPI CTL 5 to 0 3 The MASTER EN bit SPI CTL 4 is cleared to 0 forcing the device into SLAVE mode PRELIMINARY Serial Peripheral In
86. 0 The I7C bus SCL SDA is disabled and all inputs are ENAB ignored 1 The PC bus SCL SDA is enabled 5 0 Master mode START condition is sent STA 1 Master mode start transmit START condition on the bus 4 0 Master mode STOP condition is sent SPP 1 Master mode stop transmit STOP condition on the bus 3 0 re interrupt flag is not set Le 1 EC interrupt flag is set 2 0 Not Acknowledge PS 1 Acknowledge 1 0 00 Reserved PRELIMINARY I2C Serial I O Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification 159 ZiLOG C Status Register The I2C SR register is a Read Only register that contains a 5 bit status code in the five most significant bits the three least significant bits are always 0 The Read Only I2C SR registers share the same I O addresses as the Write Only I2C CCR registers See PC Sta tus Registers I2C SR 00CCh Table 89 I C Status Registers I2C SR 00CCh Bit 7 6 5 4 3 2 1 0 Reset 1 1 0 0 0 CPU Access R R R R R Note R Read only Bit Position Value Description 7 3 00000 5 bit I C status code STAT 11111 2 0 000 Reserved There are 29 possible status codes as listed in PC Status Codes When the I2C SR regis ter contains the status code F8h no relevant status information is available no interrupt is generated and the IFLG bit in the I2C CTL register is not set All other status codes corre spond to a defined state o
87. 002h and FFFFh as the values 0000h and 0001h are invalid and proper operation is not guaranteed As a result the minimum BRG clock divisor ratio is 2 A Write to either the Low or High byte registers for the BRG Divisor Latch causes both bytes to be loaded into the BRG counter The count is then restarted Bit 7 of the associated UART Line Control register UARTx LCTL must be set to 1 to access this register See Tables 53 and 54 Refer to the UART Line Control Register UARTx LCTL on page 118 for more information Note The UARTx_BRG_L registers share the same address space with the UARTx RBR and UARTx THR registers The UARTx BRG H registers share the same address space with the UARTx IER registers Bit 7 of the associated UART Line Control register UARTx LCTL must be set to 1 to enable access to the BRG registers Table 53 UART Baud Rate Generator Register Low Bytes UARTO BRG L 00COh UART1 BRG L 00D0h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 1 0 CPU Access RW RW RW RW RW RW RW RW Note R Read only R W Read Write Bit Position Value Description 7 0 00h These bits represent the Low byte of the 16 bit Baud Rate UART BRG L FFh Generator divider value The complete BRG divisor value is returned by UART BRG H UART BRG Lj PRELIMINARY Universal Asynchronous Receiver Transmitter Table 54 UART Baud Rate Generator Register High Bytes UARTO BRG
88. 00C4h UART1_MCTL 00D4h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access R R RAV RW RW RW RW R W Note R Read Only R W Read Write Bit Position Value Description 7 6 00b Reserved must be 00b 5 0 MULTIDROP mode disabled MoM 1 MULTIDROP mode enabled See Parity Select Definition for Multidrop Communications for parity select definitions 4 0 LOOP BACK mode is not enabled LOOP 1 LOOP BACK mode is enabled The UART operates in internal LOOP BACK mode The transmit data output port is disconnected from the internal transmit data output and set to 1 The receive data input port is disconnected and internal receive data is connected to internal transmit data The modem status input ports are disconnected and the four bits of the modem control register are connected as modem status inputs The two modem control output ports OUT 1 amp 2 are set to their inactive state 3 0 1 No function in normal operation OUT2 In LOOP BACK mode this bit is connected to the DCD bit in the UART Status Register 2 0 1 No function in normal operation OUT1 In LOOP BACK mode this bit is connected to the RI bit in the PS015308 0404 UART Status Register PRELIMINARY Universal Asynchronous Receiver Transmitter eZ80F92 eZ80F93 Product Specification Z ZiLOG Bit Position Value Description 1 0 1 Request To Send RTS In normal operation
89. 0F93 Product Specification Zi RAM Control Registers RAM Control Register The internal data RAM can be disabled by clearing the RAM EN bit The default upon RESET is for RAM to be enabled Table 112 RAM Control Register RAM_CTL 00B4h Bit 7 6 2 Reset 1 0 0 0 0 0 0 0 CPU Access R W R R Note R W Read Write R Read Only Bit Position Value Description 7 0 On chip general purpose RAM is disabled RAM_EN 1 On chip general purpose RAM is enabled 6 0 0000000 Reserved RAM Address Upper Byte Register The RAM_ADDR_U register defines the upper byte of the address for the on chip RAM If enabled RAM addresses assume priority over all Chip Selects The external Chip Select signals are not asserted if the corresponding RAM address is enabled Table 113 RAM Address Upper Byte Register RAM_ADDR_U 00B5h Bit 7 6 5 4 3 2 1 0 Reset 1 1 1 1 1 1 1 1 CPU Access RAW RW RW RW RW RW RW RW Note R W Read Write Bit Position Value Description 7 0 00h This byte defines the upper byte of the RAM address On chip RAM_ADDR_U FFh RAM is prioritized over all Memory Chip Selects If the enabled RAM and Chip Select addresses overlap the external Chip Select is not asserted PS015308 0404 PRELIMINARY Random Access Memory eZ80F92 eZ80F93 Product Specification Z 196 ZiLOG Flash Memory Flash Mem
90. 1 CS1 is not active for much of its defined address space Memory Location CS3_UBR FFh FFFFFFh CS3 Active 3 MB Address Space CS3_LBR DOh D00000h CS2 UBR CFh CFFFFFh CS2 Active CS2 LBR A0h 3 MB Address Space Aagon0k CS1_UBR 9Fh CS1 Active 9FFFFFh 2 MB Address Space 800000h CS0_UBR 7Fh 7FFFFFh CS0 Active 8 MB Address Space CSO_LBR CS1 LBR 00h 000000h Figure 6 Example Memory Chip Select PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification VAF ZiLOG Table 13 Register Values for Memory Chip Select Example in Figure 6 Chip CSx_CTL 3 CSx CTL 4 Select CSx EN CSx IO CSx LBR CSx UBR Description cso 1 0 00h 7Fh CSO is enabled as a Memory Chip Select Valid addresses range from 000000h 7FFFFFh CS1 1 0 00h 9Fh CS1 is enabled as a Memory Chip Select Valid addresses range from 800000h 9FFFFFh CS2 1 0 AOh CFh CS2 is enabled as a Memory Chip Select Valid addresses range from A00000h CFFFFFh CS3 1 0 DOh FFh CS3 is enabled as a Memory Chip Select Valid addresses range from D00000h FFFFFFh I O Chip Select Operation I O Chip Selects can only be active when the CPU is performing I O instructions Because the I O space is separate from the memory space in the eZ80F92 device there can never be a conflict between I O and memory addresses The eZ80F92 device supports a 16 bit I O address The I O Chip Select logic decodes the
91. 110 Third Character Time out 101 Fourth Transmission Complete PRELIMINARY Universal Asynchronous Receiver Transmitter eZ80F92 eZ80F93 Product Specification Z4 ZiLOG Table 59 UART Interrupt Status Codes Continued INSTS Value Priority Interrupt Type 001 Fifth Transmit Buffer Empty 000 Lowest Modem Status UART FIFO Control Register This register is used to monitor trigger levels clear FIFO pointers and enable or disable the FIFO The UARTx_FCTL registers share the same I O addresses as the UARTx IIR registers See UART FIFO Control Registers UARTO_FCTL 00C2h UART1_FCTL 00D2h Table 60 UART FIFO Control Registers UARTO FCTL 00C2h UART1 FCTL 00D2h Bit Reset 0 0 0 0 0 0 0 0 CPU Access W W W W W W W Note W Write only Bit Position Value Description 7 6 00 Receive FIFO trigger level set to 1 Receive data interrupt is TRIG generated when there is 1 byte in the FIFO Valid only if FIFO is enabled 01 Receive FIFO trigger level set to 4 Receive data interrupt is generated when there are 4 bytes in the FIFO Valid only if FIFO is enabled 10 Receive FIFO trigger level set to 8 Receive data interrupt is generated when there are 8 bytes in the FIFO Valid only if FIFO is enabled 11 Receive FIFO trigger level set to 14 Receive data interrupt is generated when there are 14 bytes in the FIFO Valid only if FIFO is enabled 5 3 000
92. 2 eZ80F93 Product Specification VAR ZiLOG Table 131 Load Instructions Mnemonic Instruction LD Load LEA Load Effective Address PEA Push Effective Address POP Pop PUSH Push Table 132 Logical Instructions Mnemonic Instruction AND Logical AND CPL Complement Accumulator OR Logical OR TST Test Accumulator XOR Logical Exclusive OR Table 133 Processor Control Instructions Mnemonic Instruction CCF Complement Carry Flag DI Disable Interrupts EI Enable Interrupts HALT Halt IM Interrupt Mode NOP No Operation RSMIX Reset Mixed Memory Mode Flag SCF Set Carry Flag SLP Sleep STMIX Set Mixed Memory Mode Flag PRELIMINARY eZ80 CPU Instruction Set PS015308 0404 eZ80F92 eZ80F93 Product Specification Zi ZiLOG Table 134 Program Control Instructions Mnemonic Instruction CALL Call Subroutine CALL cc Conditional Call Subroutine DJNZ Decrement and Jump if Nonzero JP Jump JP cc Conditional Jump JR Jump Relative JR cc Conditional Jump Relative RET Return RET cc Conditional Return RETI Return from Interrupt RETN Return from Nonmaskable interrupt RST Restart Table 135 Rotate and Shift Instructions Mnemonic Instruction RL Rotate Left RLA Rotate Left Accumulator RLC Rotate Left Circular RLCA Rotate Left Circular Accumulator RLD Rotate Left
93. 40 ZDI Address Write Timing ZDI Write Operations ZDI Single Byte Write For single byte Write operations the address and Write control bit are first written to the ZDI block Following the single bit byte separator the data is shifted into the ZDI block on the next 8 rising edges of ZCL The master terminates activity after 8 clock cycles Figure 41 illustrates the timing for ZDI single byte Write operations lt _ZDIDataByte gt l l msb lsb of DATA of DATA Isb of Single Bit End of Data ZDlAddress Byte Separator or New ZDI START Signal Figure 41 ZDI Single Byte Data Write Timing PS015308 0404 PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification 168 ZiLOG ZDI Block Write The Block Write operation is initiated in the same manner as the single byte Write opera tion but instead of terminating the Write operation after the first data byte is transferred the ZDI master can continue to transmit additional bytes of data to the ZDI slave on the eZ80F92 device After the receipt of each byte of data the ZDI register address increments by 1 If the ZDI register address reaches the end of the Write Only ZDI register address space 30h the address stops incrementing Figure 42 illustrates the timing for ZDI Block Write operations _ZDIDataBytes 9 l l msb Isb msb of DATA of DATA of DATA Byte 1 Byte 1 Byt
94. 41 seconds for all baud rates up to 115 2 KBPS IrDA Physical Layer 1 4 Pulse Durations Specifications outlines the minimum and maximum pulse durations for all baud rates supported by the eZ80 CPU A receiver frequency divider based upon the system clock frequency measures this time limit and allows legal signals to pass to UARTO Table 68 IrDA Physical Layer 1 4 Pulse Durations Specifications Minimum Pulse Maximum Pulse Baud Rate Width Width 9600 1 41s 22 13 s 19200 1 41s 11 07 s 38400 1 41s 5 96 s PS015308 0404 PRELIMINARY Infrared Encoder Decoder eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 68 IrDA Physical Layer 1 4 Pulse Durations Specifications Minimum Pulse Maximum Pulse Baud Rate Width Width 57600 1 415 4 34 s 115200 1 415 2 23s Receiver Frequency Divider PS015308 0404 The IrDA receiver uses a 6 bit frequency divider The value is derived from the system clock to measure IR_RxD pulses The IrDA endec detects pulses that are within the IrDA Physical Layer specified minimum and maximum ranges with system clock frequencies from 5MHz up to 50MHz The upper four bits of the frequency divider factor are set via the FREQ DIV bit in the IR CTL register based on the following equation System Clock Frequency MHz Frequency Divider Factor Target Frequency of 3 33MHz The remaining lower two bits of the divider are set to 03h The target frequency corre sponds to a period of 1 2 s
95. 7 Power Supply Power Supply PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Continued Pin Symbol Function Signal Direction Description 88 PBO GPIO Port B Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port B pin when programmed as output can be selected to be an open drain or open source output TO_IN Timer O In Input Alternate clock source for Programmable Reload Timers 0 and 2 This signal is multiplexed with PBO 89 PB1 GPIO Port B Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port B pin when programmed as output can be selected to be an open drain or open source output T1 IN Timer 1 In Input Alternate clock source for Programmable Reload Timers 1 and 3 This signal is multiplexed with PB1 90 PB2 GPIO Port B Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port B pin when programmed as output can be selected to be an open drain or open source
96. 8 0404 PRELIMINARY Electrical Characteristics eZ80F92 eZ80F93 Product Specification L ZiLOG lcc vs Frequency in HALT mode Typical 3 3V 25 20 15 T 3 E E 10 5 0 0 5 10 15 20 Frequency MHz Figure 55 lcc Versus Frequency in HALT Mode PS015308 0404 PRELIMINARY Electrical Characteristics eZ80F92 eZ80F93 Product Specification 233 lcc VS Temperature in SLEEP mode Typical 3 3V RTC operating at 32KHz 450 400 350 300 Current uA N Cc eo N o eo 150 100 50 0 20 40 60 80 100 Temperature C Figure 56 lcc Versus Temperature in SLEEP Mode AC Characteristics The section provides information on the AC characteristics and timing of the eZ80F92 device All AC timing information assumes a standard load of 50pF on all outputs See AC Characteristics gt Note All data is preliminary and subject to change following completion of production characterization PS015308 0404 PRELIMINARY Electrical Characteristics eZ80F92 eZ80F93 Product Specification Zz 234 ZiLOG Table 148 AC Characteristics Ty 0 C to 70 C Ta O C to 105 C Symbol Parameter Min Max Min Max Units Conditions TxIN System Clock 50 50 ns Vpp 3 0 3 6V Cycle Time TxinH System Clock 20 20 ns Vpp 3 0 3 6V High Time Terk 50ns TxINL System Clock 20 20 ns Vpp 3 0 3 6V Low Time Terk 50ns TxiInR System Clock 3 3 ns Vpp 3 0 3 6V Rise Time Terk 50ns Txin
97. 80F92 Device Continued Pin Symbol Function Signal Direction Description 47 RD Read Output Active Low RD Low indicates that the CPU is reading from the current address location This pin is tristated during bus acknowledge cycles 48 WR Write Output Active Low WR indicates that the CPU is writing to the current address location This pin is tristated during bus acknowledge cycles 49 INSTRD Instruction Read Indicator Output Active Low INSTRD with MREQ and RD indicates the CPU is fetching an instruction from memory This pin is tristated during bus acknowledge cycles 50 WAIT WAIT Request Input Active Low Driving the WAIT pin Low forces the CPU to wait additional clock cycles for an external peripheral or external memory to complete its Read or Write operation 51 RESET System Reset Schmitt Trigger Input Active Low This signal is used to initialize the CPU This input must be Low for a minimum of 3 system clock cycles and must be held Low until the clock is stable This input includes a Schmitt trigger to allow RC rise times 52 NMI Nonmaskable Interrupt Schmitt Trigger Input Active Low The NMI input is a higher priority input than the maskable interrupts It is always recognized at the end of an instruction regardless of the state of the interrupt enable control bits This input includes a Schmitt trigger to allow RC rise times
98. 80F93 Flash Memory Arrangement Flash Memory Overview PS015308 0404 Flash can be programmed a single byte at a time or in bursts of up to 128 bytes full row Write operations may be accomplished using either memory or I O instructions Reading Flash memory can be accomplished via internal memory access or through the ZDI and OCI interfaces The Flash memory controller contains a frequency divider Flash register interface address generator and the Flash control state machine A simplified block dia gram of the Flash controller is illustrated in Figure 49 PRELIMINARY Flash Memory eZ80F92 eZ80F93 Product Specification Clock Divider 8 bit downcounter eZ80 Core Interface Flash State Machine Flash Control Registers FLASH_IRQ Figure 49 Flash Memory Block Diagram Programming Flash Memory Flash memory is programmed using standard I O or memory Write operations which the Flash memory controller automatically translates to the detailed timing and protocol required for Flash memory The more efficient multibyte row programming mode is only available via I O Writes J Caution To ensure data integrity and device reliability two main restrictions exist when programming Flash memory 1 The cumulative programming time subsequent to the most recent Erase cannot exceed 16ms for any given row 2 The same byte cannot be programmed more than twice subsequent to the most recent Erase Single Byte I O Write Oper
99. 84 Vss 85 XIN N A N A No No N A 86 XouT O O N A No No No No 87 Vpp 88 PBO 1 0 N A Yes No No OD amp OS 89 PB1 1 0 N A Yes No No OD amp OS 90 PB2 1 0 N A Yes No No OD amp OS 91 PB3 1 0 N A Yes No No OD amp OS 92 PB4 1 0 N A Yes No No OD amp OS 93 PB5 1 0 N A Yes No No OD amp OS 94 PB6 1 0 N A Yes No No OD amp OS 95 PB7 I O N A Yes No No OD amp OS 96 VDD 97 Vss 98 SDA I O N A Yes Up No OD PS015308 0404 PRELIMINARY Architectural Overview Table 2 Pin Characteristics of the eZ80F92 Device Continued eZ80F92 eZ80F93 Product Specification Z ZiLOG Schmitt Reset Active Tristate Trigger Open Drain Pin Symbol Direction Direction Low High Output Up Down Input Source 99 SCL 1 0 N A Yes No OD 100 PHI O O N A Yes No No PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification VAP ZiLOG Register Map All on chip peripheral registers are accessed in the I O address space All I O operations employ 16 bit addresses The upper byte of the 24 bit address bus is undefined during all T O operations ADDR 23 16 uv All I O operations using 16 bit addresses within the range 0080h 00FFh are routed to the on chip peripherals External I O Chip Selects are not generated if the address space programmed for the I O Chip Selects overlaps the 0080h 00FFh address range Registers at unused addresses within the 0080h 00FFh range assigned to on chip periph erals
100. 89h TMR4_CTL 008Ch or TMR5_CTL 008Fh Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access R RAV RW RW RW R W RA RW Note R Read only R W Read Write Bit Position Value Description 7 0 The timer does not reach its end of count value This bit is PRT_IRQ reset to 0 every time the TMRx_CTL register is read 1 The timer reaches its end of count value If IRQ_EN is set to 1 an interrupt signal is sent to the CPU This bit remains 1 until the TMRx CTL register is read 6 0 Timer interrupt requests are disabled IRQ EN P 1 Timer interrupt requests are enabled 5 0 Reserved 4 0 The timer operates in SINGLE PASS mode PRT_EN bit 0 is PRT_MODE reset to 0 and counting stops when the end of count value is reached 1 The timer operates in CONTINUOUS mode The timer reload value is written to the counter when the end of count value is reached 3 2 00 Clock 4 is the timer input source CUR DIN 01 Clock 16 is the timer input source 10 Clock 64 is the timer input source 11 Clock 256 is the timer input source 1 0 The automatic reload and restart function is disabled mos 1 The automatic reload and restart function is enabled When a 1 is written to RST_EN the values in the reload registers are loaded into the downcounter and the timer restarts 0 0 The programmable reload timer is disabled PRT EN The programm
101. 92 eZ80F93 Product Specification ZiLOG PC Clock Control R gist t8 cue wae oe a ope d ee eke 161 PC Software Reset Register 2 ese eee eee ote IRR ah d 162 Recommended ZDI Clock vs System Clock Frequency 164 ZDI Write Only Registers 171 ZDI Read Only Registers leeeeeeeeeee e 172 ZDI Address Match Registers 0 0 0 cece eee ee eee 174 ZDI BREAK Control Register 175 ZDI Master Control Register 0 0 eee eee eee 177 ZDI Write Data Registers 0 eee eee 178 ZDI Read Write Control Register Functions 0 005 179 ZDI Bus Control Register 2 0 eee eee 181 Instruction Store 4 0 Registers 0 0 0 eee eee eee 182 ZDI Write Memory Register eee eee 183 eZ80 Product ID Low Byte Register 0 0 0 0 eee eee 184 eZ80 Product ID High Byte Register 184 eZ80 Product ID Revision Register 0 0 0 0 eee eee eee 185 ZDI Status ReGiSter ica c tule dae eee Faces x cedes es 185 ZDI Read Register Low High and Upper 004 186 ZDI Bus Control Register 0 0 0 eee ees 187 ZDI Read Memory Register 189 RAM Control Resistet Josie epe ak ae weed ek d ed os 195 RAM Address Upper Byte Register 0 0 0 0 ce ee eee eee 195 Flash Key Register cce scccais responi niso stonei III 201 Flash Address Upper Byte Register 0 0 0 0 c eee ee ee eee 202 Fl sh Data Resisti 12e aee acte RR ERA dont EUR aed 202 Flash Control Registe
102. A No No N A 51 RESET Low N A No Yes N A 52 NMI Low N A No Yes N A 53 BUSREQ Low N A No No N A 54 X BUSACK O O Low No No No No 55 HALT_SLP O O Low No No No No 56 Vpp 57 Vss 58 RTC Xn N A N A No No N A 59 RTC Xour I O U N A N A No No No 60 RTC_Vpp 61 Vss 62 TMS N A N A Up No N A 63 TCK Rising In N A Up No N A Falling Out 64 TRIGOUT I O O High Yes No No No 65 TDI I O N A Yes No No No 66 TDO O O N A Yes No No No 67 Vop 68 PDO O N A Yes No No OD amp OS 69 PD1 I O N A Yes No No OD amp OS 70 PD2 I O N A Yes No No OD amp OS PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 2 Pin Characteristics of the eZ80F92 Device Continued Schmitt Reset Active Tristate Pull Trigger Open Drain Pin Symbol Direction Direction Low High Output Up Down Input Source 71 PDS WO NA Ys No No OD amp OS 72 PD4 1 0 N A Yes No No OD amp OS 73 PD5 1 0 N A Yes No No OD amp OS 74 PD6 1 0 N A Yes No No OD amp OS 75 PD7 1 0 N A Yes No No OD amp OS 76 PCO 1 0 N A Yes No No OD amp OS 77 PC1 1 0 N A Yes No No OD amp OS 78 PC2 y o N A Yes No No OD amp OS 79 PC3 1 0 N A Yes No No OD amp OS 80 PC4 1 0 N A Yes No No OD amp OS 81 PC5 1 0 N A Yes No No OD amp OS 82 PC6 I O N A Yes No No OD amp OS 83 PC7 I O N A Yes No No OD amp OS
103. ADDR_JU is set to 7Ah Figure 45 is not drawn to scale as RAM occupies only a very small fraction of the avail able 16MB address space Memory Location 7AFFFFh 8KB General Purpose RAM_ADDR_U RAM 7AE000h 000000h Figure 45 eZ80F92 On Chip RAM Memory Addressing Example For the eZ80F93 device RAM occupies memory addresses in the range RAM ADDR U 7 0 F000h to RAM ADDR U 7 0 F000h Following a RESET RAM is enabled with RAM ADDR U set to FFh Figure 46 illustrates a memory map of on chip RAM In this example the RAM Address Upper Byte register RAM ADDR U is set to 7Ah Figure 45 is not drawn to scale as RAM occupies only a very small fraction of the available 16 MB address space PRELIMINARY Random Access Memory PS015308 0404 eZ80F92 eZ80F93 Product Specification zZ 194 ZiLOG Memory Location 7AFFFFh 4KB RAM ADDR U 7Ah General Purpose RAM 7AF000h 000000h 1 Figure 46 eZ80F93 On Chip RAM Memory Addressing Example When enabled on chip RAM assumes priority over on chip Flash Memory and any Mem ory Chip Selects that can also be enabled in the same address space If an address is gener ated in a range that is covered by both the RAM address space and a particular Memory Chip Select address space the Memory Chip Select is not activated On chip RAM is not accessible by external devices during Bus Acknowledge cycles PRELIMINARY Random Access Memory eZ80F92 eZ8
104. AG and ZDI clock input TDI see JTAG Test Data In TDO see JTAG Test Data Out TERI see Ring Indicator Trailing Edge on Test Access Port 190 Test Mode 191 Time Out Period Selection 75 Timer 0 In 18 Timer 1 In 18 Timer Control Register 83 Timer Data Register High Byte 86 Timer Data Register Low Byte 86 Timer Input Source Select Register 88 Timer Input Source Selection 82 Timer Interrupts 81 Timer Output 82 Timer Reload Register High Byte 88 TMS see JTAG mode select input Trace buffer memory 190 Trace history buffer 190 Transferring Data 144 transmit shift register 107 115 119 122 135 SPI 136 137 141 Transmit Infrared Encoder Decoder 127 Index TRIGOUT 12 22 191 TxDO 13 TxD1 15 U UART see Universal Asynchronous Receiver Transmitter Universal Asynchronous Receiver Transmitter Baud Rate Generator Register Low and High Bytes 112 FIFO Control Register 117 Functional Description 107 Functions 107 Interrupt Enable Register 115 Interrupt Identification Register 116 Interrupts 108 Line Control Register 118 Line Status Register 122 Modem Control 108 Modem Control Register 121 Modem Status Interrupt 109 Modem Status Register 124 Receive Buffer Register 114 Receiver 108 Receiver Interrupts 109 Recommended Usage 110 Registers 113 Scratch Pad Register 125 Transmit Holding Register 113 Transmitter 107 Transmitter Interrupt 109 V VBO see Voltage Brown Out Vcc see supply vol
105. ART to transmit asynchronous serial data This signal is multiplexed with PCO 77 PC1 GPIO Port C Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port C pin when programmed as output can be selected to be an open drain or open source output Port C is multiplexed with one UART RxD1 Receive Data Input This pin is used by the UART to receive asynchronous serial data This signal is multiplexed with PC1 PS015308 0404 PRELIMINARY Architectural Overview 15 eZ80F92 eZ80F93 Product Specification ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Continued Pin Symbol Function Signal Direction Description 78 PC2 GPIO Port C Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port C pin when programmed as output can be selected to be an open drain or open source output Port C is multiplexed with one UART RTS1 Request To Send Output Active Low Modem control signal from UART This signal is multiplexed with PC2 79 PC3 GPIO Port C Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually
106. ARY Op Code Map eZ80F92 eZ80F93 Product Specification 223 ZiLOG On Chip Oscillators The eZ80F92 device features two on chip oscillators for use with an external crystal The primary oscillator generates the system clock for the internal CPU and the majority of the on chip peripherals Alternatively the Xi input pin can also accept a CMOS level clock input signal If an external clock generator is used the Xoyry pin should be left uncon nected The secondary oscillator can drive a 32 KHz crystal to generate the time base for the Real Time Clock 20 MHz Primary Crystal Oscillator Operation Figure 50 illustrates a recommended configuration for connection with an external 20MHz fundamental mode parallel resonant crystal Recommended crystal specifica tions are provided in Recommended Crystal Oscillator Specifications 20MHz Opera tion Resistor R limits total power dissipation by the crystal Printed circuit board layout should add no more than 4pF of stray capacitance to either the Xj or Xoyt pins If oscil lation does not occur reduce the values of capacitors C and C to decrease loading On Chip Oscillator 20 MHz Crystal Fundamental Mode Co 22 pF Cy 22 pF Figure 50 Recommended Crystal Oscillator Configuration 20MHz operation PS015308 0404 PRELIMINARY On Chip Oscillators eZ80F92 eZ80F93 Product Specification zZ 224 ZiLOG Table 143 Recommended Crystal Oscillator Specifications 20MHz Operation
107. B 7C 7 D 7E 7 H 7L 7 HL 7A Notes n 8 bit data Mmn 16 or 24 bit addr or data d 8 bit two s complement displacement PS015308 0404 PRELIMINARY Op Code Map 217 eZ80F92 eZ80F93 Product Specification 218 ZiLOG Table 138 Op Code Map Second Op Code After 0ODDh Legend 9 Lower Nibble of 2nd Op Code Upper Nibble of Secon LD F Mnemonic Op Code SP IX First Operand Second Operand Lower Nibble Hex 1 2 3 4 5 6 7 8 9 A B C D E F LD BC ADD n IX d IX BC BC LD DE ADD Kou IX d IX DE DE ue oen INC INC DEC LD LDHL ADD i DEC INC DEC LD na Mais iit IX IXH IXH_ IXH n IX d XIX mmn X IXL XL IXLn Sy LD LD LD IY INC DEC LD IX LD 1X ADD IX d IX d IX d IX d IX d d n IX d IX SP ae LD LD LDB LD LD LDC B IXH B IXL IX d C IXH C IXL IX d LD LD LDD LD LD LDE D IXH D IXL IX d E IXH E IXL IX d LD LD LD LD LD LDH LD LD LD LD LD LD LD LDL LD IXH C IXH D IXH E IXH IXH IXH IXL IX d IXH A IXL B IXL C IXL D IXL E IXL IXH IXL IXL IX d IXL A LD LD LD LD LD LD LD Lg LA IX d C IX d D IX d E IX d H IX d L IX d A A IXH 7 IX d oO I ADD ADD ADDA ADC ADC ADCA 2 A IXH A IXL IX d A IXH A IXL IX d 2 SUB SUB SUBA SBC SBC SBCA 5 AJXH A IXL IX d AJXH A IXL IX d amp AND AND ANDA XOR XOR XORA A IXH A IXL
108. Bus Mode Read Timing Separate Address and Data BUSES i24 ts2asdautadisis oda aie eae da a ep tenete 60 Example Intel Bus Mode Write Timing Separate Address and Data BUSES ca seii hada erat A EAA de okies 61 Example Intel Bus Mode Read Timing Multiplexed Address and Data BUS sucer PL te cen ette edP ee ea ra 63 Example Intel M Bus Mode Write Timing Multiplexed Address and Data BUS iusserat eC eR edere A rd et gea 64 Motorola Bus Mode Signal and Pin Mapping 0000 65 Watch Dog Timer Block Diagram sllseleeeeeeeeeeens 74 PRT Single Pass Mode Operation Example lees 80 UART Block Diagram 0 0 0 eens 106 Infrared System Block Diagram 0 0 0c e eee eee eee 126 SPI Master Device s sis css eee ee eee ee ee ee ERE eee 132 SPU Slav DEVICE ioni eee ER eed ee eL 132 PC Clock and Data Relationship ssleeeeeeeeeee 143 START and STOP Conditions In C Protocol 0 0 0 0 00 0 143 PC Admowledee 22adueradrex s Deakededi tls Md d pad 145 Clock Synchronization In PC Protocol esses eese 146 Typical ZDI Debug Setup sssseleeeee eee 163 Schematic For Building a Target Board ZPAKII Connector 164 ZDI Write Timi 2 scene ieee xe t Rer nate bese an geared sal 165 ZDI Read Timing iR UPS run nea ERES 166 ZDI Address Write Timing 0 0 cee eee eee 167 eZ80F92 On Chip RAM Memory Addressing Example 193 eZ80F93 On Chip RAM
109. Bus Status Register 187 Clock and Data Conventions 164 Clock Frequency 164 data 164 165 175 191 data transfer 166 debug control 190 Debug mode 166 181 187 master 166 168 169 182 183 187 PS015308 0404 eZ80F92 eZ80F93 Product Specification Z z ZiLOG Master Control Register 177 Read Memory Register 187 Read Operations 168 Read Register Low High and Upper 186 Read Write Control Register 178 Read Only Registers 172 Register Addressing 166 Register Definitions 172 Single Bit Byte Separator 166 SINGLE BYTE READ 168 SINGLE BYTE WRITE 167 slave 165 168 169 START command 166 START condition 165 START signal 165 Status Register 185 Write Data Registers 178 Write Memory Register 183 Write Operations 167 Write Only Registers 171 PRELIMINARY Index eZ80F92 eZ80F93 Product Specification 257 ZiLOG Customer Feedback Form The eZ80F92 eZ80F93 Product Specification If you experience any problems while operating this product or if you note any inaccuracies while reading this Product Specification please copy and complete this form then mail or fax it to ZILOG see Return Information below We also welcome your suggestions Customer Information Name Country Company Phone Address Fax City State Zip Email Product Information Serial or Board Fab Rev Software Version Document Number Host Computer Description Type Return Information ZiLOG System
110. CK is asserted Each WAIT state is a full bus mode cycle STATE S5 During S5 no bus signals are altered STATE S6 During S6 no bus signals are altered STATE S7 Upon entering S7 the CPU deasserts AS and DS As the clock rises at the end of S7 the CPU drives R W High The peripheral device deasserts DTACK at this time PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification ZiLOG Signal timing for Motorola bus mode is illustrated for a Read operation in Figure 17 and for a Write operation in Figure 18 In these two figures each Motorola bus mode state is 2 CPU system clock cycles in duration l l l l l l l l l l So l S1 l S2 l S3 l S4 l S5 l S6 l S7 l System Clock AAA A DATA 7 0 Figure 17 Example Motorola Bus Mode Read Timing PS015308 0404 PRELIMINARY Chip Selects and Wait States 67 System Clock ADDR 23 0 DATA 7 0 CSx RW DTACK MREQ or IORQ eZ80F92 eZ80F93 Product Specification ZiLOG Figure 18 Example Motorola Bus Mode Write Timing Switching Between Bus Modes Each time the bus mode controller must switch from one bus mode to another there is a one cycle CPU system clock delay An extra clock cycle is not required for repeated access in any of the bus modes nor is it required when the eZ80F92 device switches to eZ80 bus mode The extra clock cycles are not shown in the timing examples Due to the asynchronous nature of these
111. D LD B LD LD LDC 1 BVH LP BIYO dyed C YH CJYL IY d LD LD LDD LD LDE 5 DJYH D IYL IY d EIVH ED EIYU ay ID ID tb ID ID ID IDH ID LD LD LD LD LDL 8 YHB IYHC IYHD IYH E IYHJYH IYHJYL l d IYH A bP YEB ivi c veo EP YHE i vu vivo iv a ED NAA LD Y LD IY LD IY LD IY LD IY LD IY LD IY LD aea DA g 0 B d C JD dE dH dL d A a yH LOAN vag N ADD ADD ADDA ADC ADC ADCA 2 AIYH AJYL IY d AIYH AJYL IY d a SUB SUB SUBA SBC SBC SBCA 5 AIYH AJYL IY d AIYH AJYL IY d B AND AND ANDA XOR XOR XORA A IYH AJYL IY d AIYH AJYL IY d a OR OR ORA CP CP CPA AIYH AJYL IY d AIYH AJYL IY d Op Code Map Fourth Byte e After OFDh 0CBh and dd D E POP EX PUSH JP IY SP IY IY lY LD F SPJY Notes n 8 bit data Mmn 16 or 24 bit addr or data d 8 bit two s complement displacement PS015308 0404 PRELIMINARY Op Code Map eZ80F92 eZ80F93 Product Specification VAR ZiLOG Table 141 Op Code Map Fourth Byte After ODDh OCBh and dd Legend ower Nibble of 4th Byte Upper Ds of Fou Byte 49 xed Mnemonic First Operand Second Operand Lower Nibble Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F b RLC RRC IX d IX d RL RR IX d IX d SLA SRA IX d IX d 5 SRL IX d
112. Decimal RR Rotate Right RRA Rotate Right Accumulator RRC Rotate Right Circular RRCA Rotate Right Circular Accumulator RRD Rotate Right Decimal SLA Shift Left Arithmetic SRA Shift Right Arithmetic SRL Shift Right Logical PRELIMINARY eZ80 CPU Instruction Set eZ80F92 eZ80F93 Product Specification 216 ZiLOG Op Code Map Tables 136 through 142 indicate the hex values for each of the eZ80 CPU instructions Table 136 Op Code Map First Op Code Legend Lower Op Code Nibble Upper Op Code 4 Nibble AAND Mnemonic AH First Operand Second Operand Lower Nibble Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F LD LD INC INC DEC LD EX ADD LD DEC INC DEC LD Ori NOR vid BC A BC B B Bn RECA agar HL Bc A BC BC C C TN 4 DINZ E LD INC INC DEC LD py JR ADD LD DEC INC DEC ED aen d Mma DBA DE D D D n d HLDE A DE DE E E Ein LD LD LD JR INC INC DEC LD JR ADD DEC INC DEC LD 2 nza HG Mmm qp H H Hn P za HHL Hb HL L L Ln CPL Mmn HL Mmn 3 R rD iima NC INC DEC LD gcc JR ADD K DEC wwe DEC LD ccf NC samy SP HL HL HL n CEd HLSP mmn SP A A An 4 38 LD LD LD LD LD LD LD LD TIS LD LD LD LD LD LD suffix B C BD BE BH BL B H BA CB suffix CD CE C H CL C HL CA 5 1D LD SIL LD LD LD LD LD LD LD LD TIL LD LD LD LD DB DC suffix DE DH
113. Description 82 PC6 GPIO Port C Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port C pin when programmed as output can be selected to be an open drain or open source output Port C is multiplexed with one UART DCD1 Data Carrier Input Active Low Detect Modem status signal to the UART This signal is multiplexed with PC6 83 PC7 GPIO Port C Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port C pin when programmed as output can be selected to be an open drain or open source output Port C is multiplexed with one UART RI Ring Indicator Input Active Low Modem status signal to the UART This signal is multiplexed with PC7 84 Vss Ground Ground 85 XIN System Clock Input Oscillator Input This pin is the input to the onboard crystal oscillator for the primary system clock If an external oscillator is used its clock output should be connected to this pin When a crystal is used it should be connected between Xi and X ouT 86 XouT System Clock Output Oscillator Output This pin is the output of the onboard crystal oscillator When used a crystal should be connected between Xqy and XouT 8
114. During the middle of T1 the CPU drives ALE Low to facilitate the latching of the address STATE T2 During State T2 the CPU removes the address from the DATA bus and asserts the RD signal Depending upon the instruction either the MREQ or IORQ signal is asserted STATE T3 During State T3 no bus signals are altered If the external READY WAIT pin is driven Low at least one CPU system clock cycle prior to the beginning of State T3 additional WAIT states Twat are asserted until the READY pin is driven High STATE T4 The CPU latches the Read data at the Beginning or State T4 The CPU deasserts the RD signal and completes the Intel M pus mode cycle During Write operations with multiplexed address and data the Intel M bus mode employs 4 states T1 T2 T3 and T4 as described in Intel Bus Mode Write States Multi plexed Address and Data Bus Table 19 Intel Bus Mode Write States Multiplexed Address and Data Bus STATE T1 The Write cycle begins in State T1 The CPU drives the address onto the DATA bus and drives the ALE signal High at the beginning of T1 During the middle of T1 the CPU drives ALE Low to facilitate the latching of the address STATE T2 During State T2 the CPU removes the address from the DATA bus and drives the Write data onto the DATA bus The WR signal is asserted to indicate a Write operation STATE T3 During State T3 no bus signals are altered If the external READY WAIT pin is driven Low at
115. Flash Control Registers leseleeeeeeeeee e 200 eZ80 CPU Instruction Set cies ree 211 Op Code Map i4 uper halbe RAE Ed A Ee ora RENE e a e oO Red RR 216 On Chip Oscillators secs kerin cuker ee eee a ae oe PE ERE EAE E nx e 223 20 MHz Primary Crystal Oscillator Operation 0 0 0 0 000008 223 32 KHz Real Time Clock Crystal Oscillator Operation 04 224 Electrical Characteristics 12 RR Claw ae aie eae a kad E aa AA 226 Absolute Maximum Ratings 0 0 0 c cece eect en ee 226 DC Characteristics remet RIP hand Madea dey e wed eke 226 POR and VBO Electrical Characteristics 0 0 0 2 cece ee eee 228 Typical Current Consumption Under Various Operating Conditions 228 AC Characteristics oer uet e E e UR lee pk bless ike dae dake 233 External Memory Read Timing eee 234 External Memory Write Timing 0 0 0 cece eee e 235 External 1 O Read Timing 00 ca case ke ee ee ee RA eee 237 External I O Write Timing 0 0 0 eee eee tees 238 Wait State Timing for Read Operations 0 0 eee eee eee ee 239 Wait State Timing for Write Operations 0 0 0 eee eee 240 General Purpose I O Port Input Sample Timing 008 241 External Bus Acknowledge Timing 0 0 0 eee ee eee ee eee 242 External System Clock Driver PHI Timing 0 0 0 000008 242 ZiLOG Debug Interface Timing 0 0 c
116. G clear AAK 0 SLA W received ACK transmitted Receive data byte transmit NACK Or clear IFLG set AAK 1 Receive data byte transmit ACK 78h Arbitration lost Same as code 68h General call addr received ACK transmitted Same as code 68h BOh Arbitration lost SLA R received ACK transmitted Write byte to DATA clear IFLG clear AAK 0 Transmit last byte receive ACK Or write byte to DATA clear IFLG set AAK 1 R Read bit that is the Isb is set to 1 Transmit data byte receive ACK If 10 bit addressing is being used the slave is first addressed using the full 10 bit address plus the Write bit The master then issues a restart followed by the first part of the 10 bit address again but with the Read bit The status code then becomes 40h or 48h It is the responsibility of the slave to remember that it had been selected prior to the restart If a repeated START condition is received the status code is 10n instead of 08h After each data byte is received the IFLG is set and one of the status codes listed in PC Master Receive Status Codes For Data Bytes is in the I2C_SR register PS015308 0404 PRELIMINARY I2C Serial I O Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification Ll iz ZiLOG Table 83 I C Master Receive Status Codes For Data Bytes Code I C State Microcontroller Response Next I C Action 50h Data byte received Read DATA cle
117. H 00C1h UART1_BRG_H 00D1h eZ80F92 eZ80F93 Product Specification VAR ZiLOG Bit 7 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RAW RW RW RW RW RW RW RW Note R Read only R W Read Write Bit Position Value Description 7 0 00h These bits represent the High byte of the 16 bit Baud Rate UART BRG H FFh Generator divider value The complete BRG divisor value is returned by UART BRG H UART BRG LJ UART Registers After a RESET all UART registers are set to their default values Any writes to unused registers or register bits are ignored and reads return a value of 0 For compatibility with future revisions unused bits within a register should always be written with a value of 0 Read Write attributes reset conditions and bit descriptions of all of the UART registers are provided in this section UART Transmit Holding Register If less than eight bits are programmed for transmission the lower bits of the byte written to this register are selected for transmission The transmit FIFO is mapped at this address The user can write up to 16 bytes for transmission at one time to this address if the FIFO is enabled by the application If the FIFO is disabled this buffer is only one byte deep These registers share the same address space as the UARTx RBR and UARTx_BRG_L registers See UART Transmit Holding Registers UARTO THR 00COh UART1_THR 00D
118. IVE cn See ied koe iene due Cup Reade parait oa 127 Receiver Frequency Divider 0 0 0 cece cece eee 129 Nr EM 130 Infrared Encoder Decoder Signal Pins 0 0 0 0c eee eee eee 130 Loopback Testing ccaycienca na cae nae eee ened eee ee Pene d 130 PRELIMINARY Table of Contents eZ80F92 eZ80F93 Product Specification ZiLOG Serial Peripheral Interface 20 20 cece eee leen 132 SPI Signals o o soos usi bee ede eed bb dr bed rer ee ee tas 133 SPI Functional Description 00 135 SPI Flis 222 eda ur er EE RERO patriarca is T AN edo A S N 135 SPI Baud Rate Generator rs scriiceadprsiea it a rann ER e 136 Data Transfer Procedure with SPI Configured as the Master 136 Data Transfer Procedure with SPI Configured as a Slave 137 SPI Registets rre Lupe aue prega baad e ad E E aT 137 IC Serial DO Interface na usa Dres nouni aeeoea aeara errereen 142 I C General Characteristics eee 142 Transfering Data 2 1 s eere e ee o ep alle DR US Re eR Ada 144 Clock Synchronization sipe eicecserrm ee tia aaa waa E xb dels dese S 145 Operating Modes sssr si edo ieee ERROR UHR EA REX ET dead e Rp 147 PC RGSIS CTS seco did oce ig e eod iaa etaa ctr disce baa ne 154 ZiLOG Debug Interface leeseeeeeeeeeeeee en 163 Introduction esia e Re FERE QE enda sce es eoa eden e ds 163 ZDI Supported Protocol 0 0 cece eee eene 164 ZDI Clock and Data Conventions 00 cece ee
119. IVE mode when it receives the general call address 00h if the GCE bit in the I2C_SAR register is set The status code is then 70h y Note When the I C contains a 10 bit slave address signified by FOh F7h in the I2C SAR register it transmits an acknowledge after the first address byte is received but no interrupt is generated IFLG is not set and the status does not change The PC generates an interrupt only after the second address byte is received The C sets the IFLG bit and loads the status code as described above PC goes from MASTER mode to SLAVE RECEIVE mode when arbitration is lost during the transmission of an address and the slave address and Write bit or the general call address if the CGE bit in the I2C_SAR register is set to 1 are received The status code in the I2C SR register is 68h if the slave address is received or 78h if the general call address is received The IFLG bit must be cleared to 0 to allow data transfer to continue If the AAK bit in the I2C CTL register is set to 1 then an acknowledge bit Low level on SDA is transmitted and the IFLG bit is set after each byte is received The I2C SR regis ter contains the status code 80h or 90h if SLAVE RECEIVE mode is entered with the general call address The received data byte can be read from the I2C DR register and the IFLG bit must be cleared to allow the transfer to continue If a STOP condition or a repeated START condition is detected after the acknowledge bit
120. IX d AJXH A IXL IX d OR OR ORA CP CP CPA AJXH A IXL IX d AJXH A IXL IX d Op Code Map Fourth Byte After ODDh OCBh and dd POP EX PUSH JP IX SP IX IX IX LD SP IX Notes n 8 bit data Mmn 16 or 24 bit addr or data d 8 bit two s complement displacement PS015308 0404 PRELIMINARY Op Code Map eZ80F92 eZ80F93 Product Specification 219 ZiLOG Table 139 Op Code Map Second Op Code After OEDh Legend ower Nibble of 2nd Op Code Upper Y Pr le of Secon OpCode 4 mE Mnemonic First Operand Second Operand Lower Nibble Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F o INO OUTO LEABCJLEABC TST LDBC INO OUTO TST LD HL B n n B IX d IY d AB HL C n n C AC BC 4 INO OUTO LEADE LEADE TST LDDE INO OUTO TST LD HL D n n D IX d IY d AD HL E n n E AE DE 2 INO OUTO LEAHL LEAHL TST LDHL INO OUTO TST LD HL H n n H IX d IY d AH HL L n n L AL HL LD IY LEAIX LEA IY TST LDIX INO OUTO TST LD LD HL HL IX d IY d A HL HL A n nA AA HL IY IX LD LD IN OUT SBC LD IN OUT ADC MLT LD 4 B Bc BC B HL Bc Mmn NEG RETN IMO FA eo oc HLBc BO gc RET RA BC Mmn 5 _ IN OUT SBC n LEA IX LEAIY i4 LD IN OUT
121. Memory Chip Select signal should be generated For I O Chip Selects CSX_IO 1 This byte specifies the Chip Select address value ADDR 15 8 is compared to the values contained in these registers for determining whether an I O Chip Select signal should be generated PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification 70 ZiLOG Chip Select x Upper Bound Register For Memory Chip Selects the Chip Select x Upper Bound registers detailed in Chip Select x Upper Bound Register CSO_UBR 00A9h CS1_UBR 00ACh CS2_UBR OOAFh CS3_UBR 00B2h defines the upper bound of the address range for which the corresponding Chip Select if enabled can be active For I O Chip Selects this register produces no effect The reset state for the Chip Select O Upper Bound register is FFh while the reset state for the other Chip Select upper bound registers is 00h Table 23 Chip Select x Upper Bound Register CSO_UBR 00A9h CS1_UBR 00ACh CS2 UBR 00AFh CS3 UBR 00B2h Bit CSO_UBR Reset CS1_UBR Reset CS2_UBR Reset CS3_UBR Reset CPU Access RAW RW RW RW RW RW RW RW Note R W Read Write oO oo gt N oO oo o oO oo o oO oo 2 tn oO oo o oO oo N oO oo oO oo o Bit Position Value Description 7 0 00h For Memory Chip Selects CSX IO 0 CSx UBR FFh This byte specifies the upper bound of the Chip
122. Name hex Access Chip Select Wait State Generator continued OOAE CS2_LBR Chip Select 2 Lower Bound Register 00 R W 69 OOAF CS2_UBR Chip Select 2 Upper Bound Register 00 R W 70 00BO CS2 CTL Chip Select 2 Control Register 00 R W Z1 00B1 CS3 LBR Chip Select 3 Lower Bound Register 00 R W 69 00B2 CS3 UBR Chip Select 3 Upper Bound Register 00 R W 70 00B3 CS3 CTL Chip Select 3 Control Register 00 R W T1 On Chip RAM Control 00B4 RAM_CTL RAM Control Register 80 R W 195 00B5 RAM_ADDR_U RAM Address Upper Byte Register FF R W 195 Serial Peripheral Interface SPI Block 00B8 SPI_BRG_L SPI Baud Rate Generator Register Low 02 R W 137 Byte 00B9 SPI_BRG_H SPI Baud Rate Generator Register High 00 R W 139 Byte 00BA SPI CTL SPI Control Register 04 R W 139 00BB SPI SR SPI Status Register 00 R 140 00BC SPI TSR SPI Transmit Shift Register XX 141 SPI RBR SPI Receive Buffer Register XX R 141 Infrared Encoder Decoder Block OOBF IR CTL Infrared Encoder Decoder Control 00 R W 131 Notes 1 2 3 4 After an external pin reset the Watch Dog Timer Control register is reset to 00h After a Watch Dog Timer time out reset the Watch Dog Timer Control register is reset to 20h When the CPU reads this register the current sampled value of the port is read Read Only if RTC registers are locked Read Write if RTC registers are unlocked After an external pin reset or a Watch Dog Timer reset the RTC Control register is reset to x0xxxxOOb A
123. Note Unused in the eZ80F93 device Flash Interrupt Control Register There are two sources of interrupts from the Flash controller These two sources are Page Erase Mass Erase or Row Program completed successfully An error condition occurred Either or both of the two interrupt sources can be enabled by setting the appropriate bits in the Flash Interrupt Control register The Flash Interrupt Control register contains four status bits to indicate the following error conditions Row Program Time out This bit signals a time out during Row Programming If the current Row Program operation does not complete within 2 432 Flash controller clocks 12 4 15 8 ms depending on the Flash controller clock period the Flash con troller terminates the Row Program operation by clearing Bit 2 of the Flash Program Control register and setting the RP TMO error bit to 1 Write Violation This bit indicates an attempt to write to a protected block of Flash memory the Write is not performed Page Erase Violation This bit indicates an attempt to erase a protected block of Flash memory the requested page is not erased Mass Erase Violation This bit indicates an attempt to Mass Erase when there are one more protected blocks in Flash memory the Mass Erase is not performed If the Error Condition Interrupt is enabled any of the four error conditions result in an interrupt request being sent to the eZ80F92 device s Interrupt Controller
124. O writes I O reads and memory Read Writes produce no effect the Flash Divider and Flash Write Erase Protection registers remain locked to pre vent accidental overwrites of these critical Flash control register settings Writing a value to either the Flash Frequency Divider register or the Flash Write Erase Protection register automatically relocks both of the registers again Table 114 Flash Key Register FLASH_KEY 00F5h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access W W W W W W W Note W Write Only Bit Position Value Description 7 0 B6h Sequential Write operations of the values B6h 49h to this FLASH_KEY 49h register unlock the Flash Frequency Divider and Flash Write Erase Protection registers Flash Data Register The Flash Data register stores the data values to be programmed to Flash memory via I O Write operations This register is used for all I O Write access to Flash both individual byte Writes and multibyte row programming For single byte I O Write operations a single byte Write to this I O register programs the data value into the single byte location pointed to by the page row and column registers For multibyte I O Write operations the Flash controller autoincrements the column address for each byte placed into this register A maximum of 128 bytes of data can be pro grammed into Flash during a multibyte I O Write operation The ROW_PGM bit in th
125. OG Poor Value Description 2 0 SS must go High after transfer of every byte of data cris 1 SS can remain Low to transfer any number of data bytes 1 0 00 Reserved SPI Status Register The SPI Status Read Only register returns the status of data transmitted using the serial peripheral interface Reading the SPI_SR register clears Bits 7 6 and 4 to a logical 0 See SPI Status Register SPI SR O0BBh Table 76 SPI Status Register SPI SR 00BBh Bit 6 5 Reset 0 0 0 0 0 0 0 0 CPU Access R R Note R Read Only Bit Position Value Description 7 0 SPI data transfer is not finished SIE 1 SPI data transfer is finished If enabled an interrupt is generated This bit flag is cleared to 0 by a Read of the SPI SR register 6 0 An SPI write collision is not detected WEOL 1 An SPI write collision is detected This bit flag is cleared to 0 by a Read of the SPI_SR registers 5 0 Reserved 4 0 A mode fault multimaster conflict is not detected MODE 1 A mode fault multimaster conflict is detected This bit flag is cleared to 0 by a Read of the SPI_SR register 3 0 0000 Reserved PS015308 0404 PRELIMINARY Serial Peripheral Interface eZ80F92 eZ80F93 Product Specification 141 ZiLOG SPI Transmit Shift Register The SPI Transmit Shift register SPI_TSR is used by the SPI master to transmit data onto the SPI serial bus to th
126. Oh PS015308 0404 PRELIMINARY Universal Asynchronous Receiver Transmitter Table 55 UART Transmit Holding Registers UARTO THR 00COh UART1_THR 00DOh eZ80F92 eZ80F93 Product Specification VAR ZiLOG Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access W W W W W W W W Note W Write only Bit Position Value Description 7 0 00h Transmit data byte TxD FFh UART Receive Buffer Register The bits in this register reflect the data received If less than eight bits are programmed for receive the lower bits of the byte reflect the bits received whereas upper unused bits are 0 The receive FIFO is mapped at this address If the FIFO is disabled this buffer is only one byte deep These registers share the same address space as the UARTx THR and UARTx BRG L registers See UART Receive Buffer Registers UARTO RBR 00COh UART1_RBR 00DOh Table 56 UART Receive Buffer Registers UARTO RBR 00C0h UART1 RBR 00DOh Bit 7 6 5 4 3 2 1 0 Reset X X X X X CPU Access R R R R R R R R Note R Read only Bit Position Value Description 7 0 00h Receive data byte RxD FFh PS015308 0404 PRELIMINARY Universal Asynchronous Receiver Transmitter eZ80F92 eZ80F93 Product Specification 115 ZiLOG UART Interrupt Enable Register The UARTXx IER register is used to enable and disable the UART interrupt
127. PASS mode 78 79 80 81 84 Single Byte I O Write Operations 198 SLA see Shift Left Arithmetic SLAVE mode 142 153 155 157 160 SPI 135 Slave Receive 142 153 Slave Select 18 133 136 140 SLAVE TRANSMIT mode 142 152 SLEEP Mode 11 37 104 177 185 227 228 233 sleep mode recovery 104 reset 25 Software break point instruction 190 SPI see Serial Peripheral Interface SPI Serial Clock 18 133 Idle State 134 pin 135 139 Receive Edge 134 signal 135 Transmit Edge 134 SPIF see Serial Peripheral Interface Flags SRA see Shift Right Arithmetic SRAM 1 163 202 245 SS see Slave Select STA see MASTER Mode Start bit standard mode 142 START bit 165 START condition 143 145 146 149 151 153 154 157 162 Start Condition ZDI 165 Starting Program Counter 48 49 STOP condition 143 144 146 147 150 152 153 157 158 160 162 STP see MASTER Mode Stop bit supply voltage 2 34 35 42 142 226 227 Switching Between Bus Modes 68 PS015308 0404 PRELIMINARY eZ80F92 eZ80F93 Product Specification 254 ZiLOG system clock 20 24 34 37 40 43 44 74 76 78 82 111 136 161 162 169 cycle CPU 55 56 59 62 cycles 11 53 55 59 63 67 75 190 delay 68 frequency 79 82 88 163 164 Oscillator Input 17 Oscillator Output 17 period 191 rising edge 88 111 136 system clock high frequency 136 system clock internal 53 System Reset 11 34 T TO_IN 18 T1_IN 18 T4_OUT 19 T5_OUT 19 TCK see JT
128. Page hex Mnemonic Name hex Access Real Time Clock continued 00E4 RTC_DOM RTC Day of the Month Register XX R W 96 00E5 RTC_MON RTC Month Register XX R W 97 00E6 RTC YR RTC Year Register XX R W 98 00E7 RTC_CEN RTC Century Register XX R W 99 00E8 RTC_ASEC RTC Alarm Seconds Register XX R W 100 00E9 RTC AMIN RTC Alarm Minutes Register XX R W 101 OOEA RTC_AHRS RTC Alarm Hours Register XX R W 102 O00EB RTC ADOW RTC Alarm Day of the Week Register OX R W 103 OOEC RTC_ACTRL RTC Alarm Control Register 00 R W 104 OOED RTC_CTRL RTC Control Register x0xxx000b R W 105 xOxxxx10b Chip Select Bus Mode Control OOFO CS0O_BMC Chip Select 0 Bus Mode Control Register 02 R W 72 OOF 1 CS1 BMC Chip Select 1 Bus Mode Control Register 02 R W 72 00F2 CS2 BMC Chip Select 2 Bus Mode Control Register 02 R W 72 00F3 CS3 BMC Chip Select 3 Bus Mode Control Register 02 R W 72 Flash Memory Control Registers 00F5 FLASH KEY Flash Key Register 00 W 201 OOF6 FLASH_DATA Flash Data Register XX R W 202 00F7 FLASH ADDR U Flash Address Upper Byte Register 0 R W 202 OOF8 FLASH_CTRL Flash Control Register 88 R W 203 OOF9 FLASH_FDIV Flash Frequency Divider Register 01 R W 204 OOFA FLASH_PROT Flash Write Erase Protection Register FF R W 205 Notes 1 2 3 4 5 After an external pin reset the Watch Dog Timer Control register is reset to 00h After a Watch Dog Timer time out reset the Watch Dog Timer Control register is reset to 20h When the CPU reads this regist
129. R L Downcounting continues on the next clock edge In CONTINUOUS mode the PRT continues to count until disabled An example of a PRT operating in CONTINU OUS mode is illustrated in Figure 30 Timer register information is indicated in PRT Con tinuous Mode Operation Example PS015308 0404 PRELIMINARY Programmable Reload Timers eZ80F92 eZ80F93 Product Specification Zz 81 ZiLOG PRT Clock Clock 4 IOWRN lt O Write to TMRx CTL Enables PRT PRT Count Interrupt Request Table 30 PRT CONTINUOUS Mode Operation Example Table 31 PRT CONTINUOUS Mode Operation Example Parameter Control Register s Value PRT Enabled TMRx_CTL 0 1 Reload and Restart Enabled TMRx CTL 1 1 PRT Clock Divider 4 TMRx CTL 3 2 00b CONTINUOUS Mode TMRx_CTL 4 1 PRT Interrupt Enabled TMRx CTL 6 1 PRT Reload Value TMRx RR H TMRx RR L 0004h Reading the Current Count Value The CPU is capable of reading the current count value while the timer is running This Read event does not affect timer operation The High byte of the current count value is latched during a Read of the Low byte Timer Interrupts The timer interrupt flag PRT IRQ is set to 1 whenever the timer reaches its end of count value 0000h in SINGLE PASS mode or when the timer reloads the start value in CON TINUOUS mode The interrupt flag is only set when the timer reaches 0000h or reloads from 0001h The timer interrupt flag is not set to 1 when the
130. RESET caused by WDT time out This flag is set by the WDT time out even if the NMI OUT flag is set to 1 The CPU can poll this bit to determine the source of the RESET or NMI 4 3 00 WDT clock source is system clock WDT CLK 01 WDT clock source is Real Time Clock source 32 KHz on chip oscillator or 50 60Hz input as set by RTC_CTRLI 4 10 Reserved 11 Reserved Note RST FLAG is only cleared by a non WDT RESET PRELIMINARY Watch Dog Timer PS015308 0404 eZ80F92 eZ80F93 Product Specification Z ZiLOG Pau Value Description 2 0 Reserved 1 0 00 WDT time out period is 2 clock cycles eT PERO 01 WDT time out period is 22 clock cycles 10 WDT time out period is 222 clock cycles 11 WDT time out period is 218 clock cycles Note RST FLAG is only cleared by a non WDT RESET Watch Dog Timer Reset Register The Watch Dog Timer Reset register detailed in Watch Dog Timer Reset Register is an 8 bit Write Only register The Watch Dog Timer is reset when an A5h value followed by 5Ah is written to this register Any amount of time can occur between the writing of the A5h value and the 5Ah value so long as the WDT time out does not occur prior to completion Table 28 Watch Dog Timer Reset Register WDT RR 0094h Bit 7 6 5 4 3 2 Reset X X X X CPU Access W W W W W W W W Note X Undefined W Write only e X X X x lt B
131. RT 1 Line Control Register 00 R W 118 00D4 UART1_MCTL UART 1 Modem Control Register 00 R W 121 00D5 UART1_LSR UART 1 Line Status Register 60 R W 122 00D6 UART1 MSR UART 1 Modem Status Register XX R W 124 00D7 UART1 SPR UART 1 Scratch Pad Register 00 R W 425 Low Power Control 00DB CLK PPD1 Clock Peripheral Power Down Register 1 00 R W 39 00DC CLK PPD2 Clock Peripheral Power Down Register 2 00 R W 40 Real Time Clock OOEO RTC_SEC RTC Seconds Register XX R W 92 00E1 RTC_MIN RTC Minutes Register XX R W 93 00E2 RTC HRS RTC Hours Register XX R W 94 00E3 RTC_DOW RTC Day of the Week Register 0X R W 95 Notes 1 After an external pin reset the Watch Dog Timer Control register is reset to 00h After a Watch Dog Timer time out reset the Watch Dog Timer Control register is reset to 20h 2 When the CPU reads this register the current sampled value of the port is read 3 Read Only if RTC registers are locked Read Write if RTC registers are unlocked 4 After an external pin reset or a Watch Dog Timer reset the RTC Control register is reset to x0xxxx0OOb After an RTC Alarm sleep mode recovery reset the RTC Control register is reset to xOxxxx10b 5 Read Only if Flash Memory is locked Read Write if Flash Memory is unlocked PS015308 0404 PRELIMINARY Register Map eZ80F92 eZ80F93 Product Specification Ll ZiLOG Table 3 Register Map Continued Address Reset CPU
132. RY modes The program counter PC increments after each data Read However the ZDI register address does not increment automatically when this register is accessed As a result the ZDI master can read any number of data bytes out of memory through the ZDI Read Memory register See ZDI Read Memory Register ZDI RD MEM 20h in the ZDI Register Read Only Address Space PRELIMINARY ZiLOG Debug Interface 187 eZ80F92 eZ80F93 Product Specification zZ 188 ZiLOG PS015308 0404 PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification Ll ZiLOG Table 110 ZDI Read Memory Register ZDI RD MEM 20h in the ZDI Register Read Only Address Space Bit 7 6 5 4 3 Reset 0 0 0 0 0 0 0 0 CPU Access R R R R R Note R Read Only Bit Position Value Description 7 0 00h 8 bit data read from the memory address indicated by the ZDI RD MEM FFh CPU s program counter In Za0 MEMORY mode 8 bit data is transferred out from address MBASE PC 15 0 In ADL Memory mode 8 bit data is transferred out from address PC 23 0 PS015308 0404 PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification zZ 190 ZiLOG On Chip Instrumentation Introduction to On Chip Instrumentation On Chip Instrumentation OCI for the eZ809 CPU core enables powerful debugging features The OCI provides run control memory and register visibility complex break poi
133. Reserved Note Receive FIFO is not enabled during MULTIDROP mode PS015308 0404 PRELIMINARY Universal Asynchronous Receiver Transmitter eZ80F92 eZ80F93 Product Specification VAR ZiLOG Bit Position Value Description 2 0 No effect CERT 1 Clear the transmit FIFO and reset the transmit FIFO pointer Valid only if the FIFO is enabled 1 0 No effect SERRAR 1 Clear the receive FIFO clear the receive error FIFO and reset the receive FIFO pointer Valid only if the FIFO is enabled 0 0 Transmit and receive FIFOs are disabled Transmit and FIFOEN receive buffers are only 1 byte deep 1 Transmit and receive FIFOs are enabled Note Receive FIFO is not enabled during MULTIDROP mode UART Line Control Register This register is used to control the communication control parameters See Tables 61 and 62 Table 61 UART Line Control Registers UARTO_LCTL 00C3h UART1_LCTL 00D3h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RAV RW RW RW RA RW RW RW Note R W Read Write Bit Position Value Description 7 0 Access to the UART registers at I O addresses UARTx_RBR DLAB UARTx THR and UARTx IER is enabled Access to the Baud Rate Generator registers at I O addresses UARTx BRG L and UARTx BRG Hiis enabled Note Receive Parity is set to SPACE in MULTIDROP mode PS015308 0404 PRELIMINARY Universal As
134. SLAVE TRANSMIT mode when arbitration is lost dur ing the transmission of an address and the slave address and Read bit are received This action is represented by the status code BOh in the I2C_SR register The data byte to be transmitted is loaded into the I2C DR register and the IFLG bit cleared After the I C transmits the byte and receives an acknowledge the IFLG bit is set and the I2C SR register contains B8h When the final byte to be transmitted is loaded into the I2C DR register the AAK bit is cleared when the IFLG is cleared After the final byte PRELIMINARY I2C Serial I O Interface eZ80F92 eZ80F93 Product Specification 153 ZiLOG is transmitted the IFLG is set and the I2C_SR register contains C8h and the PC returns to the idle state The AAK bit must be set to 1 before reentering SLAVE mode If no acknowledge is received after transmitting a byte the IFLG is set and the I2C_SR register contains COh The PC then returns to the idle state If a STOP condition is detected after an acknowledge bit the IC returns to the idle state Slave Receive In SLAVE RECEIVE mode a number of data bytes are received from a master transmit ter The I C enters SLAVE RECEIVE mode when it receives its own slave address and a Write bit Isb 0 after a START condition The PC transmits an acknowledge bit and sets the IFLG bit in the I2C_CTL register and the I2C_SR register contains the status code 60h The IC also enters SLAVE RECE
135. SR1 16 DTACK see cycle termination signal PS015308 0404 PRELIMINARY eZ80F92 eZ80F93 Product Specification Zi ZiLOG DTR see Data Terminal Ready DTRO 14 130 DTRI 16 E edge selectable interrupts 45 edge triggered interrupt input 130 edge triggered interrupt mode 43 45 Edge Triggered Interrupts 44 EI Op Code Map 216 Electrical Characteristics 226 ENAB see Bus Enable bit Enabling and Disabling the WDT 75 endec see Infrared Encoder Decoder Erase operations 196 197 Event Counter 82 External Bus Acknowledge Timing 242 external bus request 54 166 170 External I O Chip Selects 25 External I O Read Timing 237 External I O Write Timing 238 External Memory Read Timing 234 External Memory Write Timing 235 external pull down resistor 42 External System Clock Driver PHI Timing 242 eZ80 Bus mode 55 68 72 eZ80 CPU 10 37 54 58 59 66 172 190 Core 33 Instruction Set 211 eZ80 Product ID Low and High Byte Registers 184 eZ80 Product ID Revision Register 185 eZ809 system clock cycle 55 56 59 62 eZ80F92 device 1 4 5 9 25 37 41 47 48 50 52 68 74 78 82 110 111 154 164 166 168 172 177 178 182 183 185 187 223 226 228 233 242 F FAST mode 142 162 Features eZ80 CPU Core 33 Flash memory 1 194 196 Arrangement in the eZ80F93 197 Index Flash Memory Overview 197 framing error 106 108 115 full duplex transmission 135 Functional Description Infrared Encoder Decoder
136. Select address range The upper byte of the address bus ADDR 23 16 is compared to the values contained in these registers for determining whether a Chip Select signal should be generated For I O Chip Selects CSx IO 1 No effect Chip Select x Control Register The Chip Select x Control register detailed in Chip Select x Control Register CSO_CTL 00AAh CSI CTL 00ADh CS2 CTL 00BOh CS3 CTL 00B3h enables the Chip Selects specifies the type of Chip Select and sets the number of WAIT states The reset state for the Chip Select 0 Control register is E8h while the reset state for the 3 other Chip Select control registers is 00h PS015308 0404 PRELIMINARY Chip Selects and Wait States PS015308 0404 eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 24 Chip Select x Control Register CSO CTL 00AAh CS1_CTL 00ADh CS2 CTL 00BOh CS3 CTL 00B3h Bit CSO CTL Reset CS1 CTL Reset CS2 CTL Reset CS3 CTL Reset OOO gt N oO o o oa oO o o n a oO oO OC otn oO OC O gt amp CPU Access ylolololol ylololololo lololol olN RAV RW RW RW RW Note R W Read Write R Read Only S Value Description 7 5 000 0 WAIT states are asserted when this Chip Select is active Ca 001 1 WAIT state is asserted when this Chip Select is active 010 2 WAIT states are asserted wh
137. Specification VAF ZiLOoOG Chip Selects and Wait States The eZ80F92 device generates four Chip Selects for external devices Each Chip Select may be programmed to access either memory space or I O space The Memory Chip Selects can be individually programmed on a 64KB boundary The I O Chip Selects can each choose a 256 byte section of I O space In addition each Chip Select may be pro grammed for up to 7 wait states Memory and I O Chip Selects Each of the Chip Selects can be enabled for either the memory address space or the I O address space but not both To select the memory address space for a particular Chip Select CSX_IO CSx_CTL 4 must be reset to 0 To select the I O address space for a particular Chip Select CSX_IO must be set to 1 After RESET the default is for all Chip Selects to be configured for the memory address space For either the memory address space or the I O address space the individual Chip Selects must be enabled by setting CSx_EN CSx CTL 3 to 1 Memory Chip Select Operation PS015308 0404 Operation of each of the Memory Chip Selects is controlled by three control registers To enable a particular Memory Chip Select the following conditions must be met The Chip Select is enabled by setting CSx EN to 1 The Chip Select is configured for Memory by clearing CSX IO to 0 The address is in the associated Chip Select range CSx LBR 7 0 ADDR 23 16 lt CSx UBR 7 0 No higher priority lowe
138. Sx registers ZDI IS1 or contain any additional Op Codes or operand dates ZDI IS0 required for execution of the required instruction PS015308 0404 PRELIMINARY ZiLOG Debug Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification zZ 183 ZiLOG ZDI Write Memory Register A Write to the ZDI Write Memory register causes the eZ80F92 device to write the 8 bit data to the memory location specified by the current address in the program counter In Z80 MEMORY mode this address is MBASE PC 15 0 In ADL MEMORY mode this address is PC 23 0 The program counter PC increments after each data Write However the ZDI register address does not increment automatically when this register is accessed As a result the ZDI master is allowed to write any number of data bytes by writ ing to this address one time followed by any number of data bytes See ZDI Write Memory Register Table 103 ZDI Write Memory Register ZDI WR MEM 30h in the ZDI Register Write Only Address Space Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X x CPU Access W W W W W W W W Note X Undefined W Write Bit Position Value Description 7 0 00h The 8 bit data that is transferred to the ZDI slave following ZDI_WR_MEM FFh a Write to this address is written to the address indicated by the current program counter The program counter is incremented following each 8 bits of data In Z80 MEMORY
139. Test Customer Support 532 Race Street San Jose CA 95126 Phone 408 558 8500 Fax 408 558 8536 ZiLOG Customer Support Problem Description or Suggestion Provide a complete description of the problem or your suggestion If you are reporting a specific problem include all steps leading up to the occurrence of the problem Attach additional pages as necessary PS015308 0404 PRELIMINARY Customer Feedback Form
140. VAF ZiLOG l l l ssemco TTT T CSx l I I I MREQ l l or IORQ i l l l Figure 10 Example Z80 Bus Mode Write Timing Intel Bus Mode Chip selects configured for Intel bus mode modify the CPU bus signals to duplicate a four state memory transfer similar to that found on Intel style microcontrollers The bus signals and eZ80F92 device pins are mapped as illustrated in Figure 11 In Intel bus mode the user can select either multiplexed or nonmultiplexed address and data buses In nonmulti plexed operation the address and data buses are separate In multiplexed operation the lower byte of the address ADDR 7 0 also appears on the data bus DATA 7 0 during State T1 of the Intel bus mode cycle During multiplexed operation the lower byte of the address bus also appears on the address bus in addition to the data bus PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80 Bus Mode Signals Pins INSTRD RD WR WAIT MREQ IORQ ADDR 23 0 DATA 7 0 Figure 11 Intel Bus Mode Signal and Pin Mapping Bus Mode Controller Multiplexed Bus Controller eZ80F92 eZ80F93 Product Specification VAF ZiLOG Intel Bus Signal Equvalents ALE READY MREQ IORQ ADDR 23 0 lt gt DATA 7 0 Intel Bus Mode Separate Address and Data Buses During Read operations with separate address and data buses the Intel bus mode employs 4 states T1 T2 T3 and T4 as described in Intel Bus Mode Read States Sep
141. X X X X X CPU Access R R R R R R R R Note R Read Only Bit Position Value Description 7 0 00h SPI received data RX_DATA FFh PS015308 0404 PRELIMINARY Serial Peripheral Interface eZ80F92 eZ80F93 Product Specification zZ 142 ZiLOG I2C Serial I O Interface I C General Characteristics PS015308 0404 The I C serial I O bus is a two wire communication interface that can operate in four modes MASTER TRANSMIT MASTER RECEIVE SLAVE TRANSMIT SLAVE RECEIVE The IC interface consists of the Serial Clock SCL and the Serial Data SDA Both SDA and SCL are bidirectional lines connected to a positive supply voltage via an external pull up resistor When the bus is free both lines are High The output stages of devices connected to the bus must be configured as open drain outputs Data on the I C bus can be transferred at a rate of up to 100 KBPS in STANDARD mode or up to 400 KBPS in FAST mode One clock pulse is generated for each data bit transferred Clocking Overview If another device on the I C bus drives the clock line when the I C is in MASTER mode the PC synchronizes its clock to the PC bus clock The High period of the clock is deter mined by the device that generates the shortest High clock period The Low period of the clock is determined by the device that generates the longest Low clock period A slave may stretch the Low period of the clock to slow down the bus master The Low period may
142. Y Serial Peripheral Interface eZ80F92 eZ80F93 Product Specification 134 ZiLOG ated by the master the SCK pin becomes an input on a slave device The SPI contains an internal divide by two clock divider In MASTER mode the SPI serial clock is one half the frequency of the clock signal created by the SPI s Baud Rate Generator As demonstrated in Figure 30 and SPI Clock Phase and Clock Polarity Operation four possible timing relations may be chosen by using control bits CPOL and CPHA in the SPI Control register See the SPI Control Register SPI_CTL on page 139 Both the master and slave must operate with the identical timing clock polarity CPOL and clock phase CPHA The master device always places data on the MOSI line a half cycle before the clock edge SCK signal so that the slave device latches the data Number of Cycles on the SCK Signal l l l l l l l l l 2 l 3 l G l 5 l 6 l I l l l l l l l l l l l sck cPoLbit 0 NX f NA N N N NL ANLASS l I l l l l SCK CPOL bit 1 l l Y Y T DO EEOAE e CPHA bit 0 Data Out C2 D ALS Ad ANSA NIL AEA l l l S le Input Y Y Y Y Y Y i CPHA bit 1 Data Out A XMSBX 9 X 5 X 4 X 3 X 2 X 1 XLS l ENABLE To Slave Y Figure 30 SPI Timing PS015308 0404 Table 72 SPI Clock Phase and Clock Polarity Operation SS High SCK SCK SCK Transmit Receive Idle Between CPHA CPOL Edge Edge State Characters 0 0 Falling Rising Low Yes 0 1 R
143. Z80F92 eZ80F93 Product Specification Ll 2 ZiLOG Bit Position Value Description 5 THRE Transmit holding register FIFO is not empty Transmit holding register FIFO is empty This bit cannot be set to 1 during the BREAK condition This bit only becomes 1 after the BREAK command is removed Bl Receiver does not detect a BREAK condition This bit is reset to 0 when the UARTx_LSR register is read Receiver detects a BREAK condition on the receive input line This bit is 1 if the duration of BREAK condition on the receive data is longer than one character transmission time the time depends on the programming of the UARTx_LSR register In case of FIFO only one null character is loaded into the receiver FIFO with the framing error The framing error is revealed to the CPU whenever that particular data is read from the receiver FIFO FE No framing error detected for character at the top of the FIFO This bit is reset to O when the UARTx LSR register is read Framing error detected for the character at the top of the FIFO This bit is set to 1 when the stop bit following the data parity bit is logic O PE The received character at the top of the FIFO does not contain a parity error In multidrop mode this indicates that the received character is a data byte This bit is reset to 0 when the UARTx LSR register is read The received character at the top of the FIFO contains a parity error
144. Z80F93 Product Specification 103 ZiLOG Real Time Clock Alarm Day of the Week Register This register contains the alarm day of the week value See Real Time Clock Alarm Day of the Week Register RTC_ADOW OOEBh Table 50 Real Time Clock Alarm Day of the Week Register RTC_ADOW 00EBh Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 X X X X CPU Access R R R R R W R AW R IW R W Note X Unchanged by RESET R Read Only R W Read Only if RTC locked Read Write if RTC unlocked Binary Coded Decimal Operation BCD_EN 1 Bit Position Value Description 7 4 0000 Reserved 3 0 1 7 The alarm day of the week value ADOW Binary Operation BCD EN 0 Bit Position Value Description 7 4 0000 Reserved 3 0 01h The alarm day of the week value ADOW 07h PRELIMINARY Real Time Clock PS015308 0404 Real Time Clock Alarm Control Register eZ80F92 eZ80F93 Product Specification ZiLOG This register contains alarm enable bits for the Real Time Clock The RTC_ACTRL regis ter is cleared by a RESET See Real Time Clock Alarm Control Register RTC_ACTRL OOECh Table 51 Real Time Clock Alarm Control Register RTC_ACTRL 00ECh Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access R R R R RW RW RW RW Note X Unchanged by RESET R W Read Write R Read Only
145. _ADDRxX bit is set in the ZDI BREAK Control register to enable the particular address match the current eZ80F92 address is compared with the 3 byte address set ZDI_ADDRx_U ZDI ADDRx H ZDI ADDR x Lj If the CPU is operating in ADL mode the address is supplied by ADDR 23 0 If the CPU is operating in Z80 mode the address is supplied by MBASE 7 0 ADDR 15 0 If a match is found ZDI issues a BREAK to the eZ80F92 device placing the processor in ZDI mode pending further instructions from the ZDI inter face block If the address is not the first op code fetch the ZDI BREAK is executed at the end of the instruction in which it is executed There are four sets of address match regis ters They can be used in conjunction with each other to BREAK on branching instruc tions See ZDI Address Match Registers ZDI ADDRO L 00h ZDI ADDRO H 01h ZDI ADDRO U 02h ZDI ADDRI L 04h ZDI ADDRI H 05h ZDI ADDRI U 06h ZDI ADDR2 L 08h ZDI ADDR2 H 09h ZDI ADDR2 U 0Ah PRELIMINARY ZiLOG Debug Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification Z4 ZiLOG ZDI_ADDR3_L OCh ZDI ADDR3 H ODh and ZDI ADDR3 U OEh in the ZDI Register Write Only Address Space PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification Z4 ZiLOG Table 96 ZDI Address Match Registers ZDI ADDRO L 00h ZDI ADDRO H 01h ZDI ADDRO U 02h ZDI ADDR1 L 04h ZDI ADDR1 H 05h ZDI ADDR1 U 06h ZDI ADDR2 L
146. able reload timer is enabled PRELIMINARY Programmable Reload Timers PS015308 0404 eZ80F92 eZ80F93 Product Specification 86 ZiLOG Timer Data Register Low Byte This Read Only register returns the Low byte of the current count value of the selected timer The Timer Data Register Low Byte detailed in Timer Data Register Low Byte TMRO_DR_L 0081h TMR1_DR_L 0084h TMR2_DR_L 0087h TMR3_DR_L 008Ah TMR4 DR L 008Dh or TMR5_DR_L 0090h can be read while the timer is in operation Reading the current count value does not affect timer operation To read the 16 bit data of the current count value TMRx DR H 7 0 TMRx DR L 7 0 first read the Timer Data Register Low Byte and then read the Timer Data Register High Byte The Timer Data Register High Byte value is latched when a Read of the Timer Data Register Low Byte occurs Note The Timer Data registers and Timer Reload registers share the same address space Table 34 Timer Data Register Low Byte TMRO DR L 0081h TMR1 DR L 0084h TMR2 DR L 0087h TMR3 DR L 008Ah TMR4 DR L 008Dh or TMR5 DR L 0090h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 CPU Access Note R Read only Bit Position Value Description 7 0 O0h FFh These bits represent the Low byte of the 2 byte timer data TMRx DR L value TMRx DR H 7 0 TMRx DR L 7 0 Bit 7 is bit 7 of the 16 bit timer data value Bit 0 is
147. ace PS015308 0404 eZ80F92 eZ80F93 Product Specification VAR ZiLOG Table 74 SPI Baud Rate Generator Register High Byte SPI BRG H 00B9h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RAW RW RW RW RW RW RW RW Note R W Read Write Bit Position Value Description 7 0 00h These bits represent the High byte of the 16 bit Baud Rate SPI BRGH FFh Generator divider value The complete BRG divisor value is returned by SPI BRG H SPI BRG Lj SPI Control Register This register is used to control and setup the serial peripheral interface The SPI should be disabled prior to making any changes to CPHA or CPOL See SPI Control Register SPI CTL 00BAh Table 75 SPI Control Register SPI CTL 00BAh Bit 7 6 5 4 3 2 0 Reset 0 0 0 0 0 1 0 0 CPU Access R W R RAW RW RW RAW R Note R Read Only R W Read Write Poun Value Description 7 0 SPI system interrupt is disabled IRGLEN 1 SPI system interrupt is enabled 6 0 Reserved 5 0 SPI is disabled FRUEN 1 SPI is enabled 4 0 When enabled the SPI operates as a slave MASTER EN 1 When enabled the SPI operates as a master 3 0 Master SCK pin idles in a Low 0 state EP 1 Master SCK pin idles in a High 1 state PRELIMINARY Serial Peripheral Interface eZ80F92 eZ80F93 Product Specification Zi ZiL
148. ace and associated logic UART Functions PS015308 0404 The UART function implements The transmitter and associated control logic The receiver and associated control logic The modem interface and associated logic UART Transmitter The transmitter block controls the data transmitted on the TxD output It implements the FIFO accessed through the UARTx_THR register the transmit shift register the parity generator and control logic for the transmitter to control parameters for the asynchronous communication protocol The UARTx THR is a Write Only register The processor writes the data byte to be trans mitted into this register In the FIFO mode up to 16 data bytes can be written via the UARTx THR register The data byte from the FIFO is transferred to the transmit shift reg ister at the appropriate time and transmitted out on TxD output After SYNC RESET the UARTx THR register is empty Therefore the Transmit Holding Register Empty THRE bit bit 5 of the UARTx_LSR register is 1 and an interrupt is sent to the processor if interrupts are enabled The processor can reset this interrupt by loading data into the UARTx THR register which clears the transmitter interrupt The transmit shift register places the byte to be transmitted on the TxD signal serially The least significant bit of the byte to be transmitted is shifted out first and the most significant bit is shifted out last The control logic within the block adds the
149. ace to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects 22 ADDR17 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects 23 ADDR18 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects 24 ADDR19 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects 25 ADDR20 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects 26 ADDR21 Address Bus Bidirectional Configured as an outp
150. al prescaler is set to divide by 32768 If the power line frequency option is selected the prescale value is set by FREQ_SEL and the 32 Khz oscillator is disabled See Real Time Clock Control Register RTC_CTRL O0EDh Table 52 Real Time Clock Control Register RTC CTRL 00EDh Bit 7 6 5 4 3 2 1 0 Reset X 0 X X X X 0 1 0 CPU Access R RW RW RW RW R R R W Note X Unchanged by RESET R Read Only R W Read Write Bit Position Value Description 7 0 Alarm interrupt is inactive ALARM 1 Alarm interrupt is active 6 0 Interrupt on alarm condition is disabled INT_EN or 1 Interrupt on alarm condition is enabled 5 0 RTC count and alarm value registers are binary ENDE 1 RTC count and alarm value registers are binary coded decimal BCD 4 0 RTC clock source is crystal oscillator output 32768 Hz CLK_SEL On chip 32768Hz oscillator is enabled 1 RTC clock source is power line frequency input On chip 32768 Hz oscillator is disabled 3 0 Power line frequency is 60Hz PREG SEL 1 Power line frequency is 50Hz 2 0 Reserved 1 0 RTC does not generate a sleep mode recovery reset SERERE 1 RTC Alarm generates a sleep mode recovery reset 0 0 RTC count registers are locked to prevent Write access RTC_UNLOCK RTC counter is enabled RTC count registers are unlocked to allow Write access RTC counter is disabled PRELIMINARY Real Time Cl
151. amming 199 multimaster conflict 135 140 Index N NACK see Not Acknowledge NMI see Nonmaskable Interrupt NMI_FLAG bit 76 NMI_OUT bit 76 Nonmaskable Interrupt 11 22 33 38 47 49 74 76 return from 215 Not Acknowledge 144 148 152 157 160 O OCI see On Chip Instrumentation On Chip Instrumentation 190 Activation 190 clock pin 190 Information Requests 192 Interface 191 Introduction to 190 pins 191 On Chip Oscillators 223 On chip pull up 191 Op Code maps 216 open drain mode 42 Open drain output 42 142 open source mode 42 open source output 13 16 18 19 42 Operating Modes 147 Operation of the eZ80F92 Device During ZDI Breakpoints 169 Ordering Information 245 overrun error 106 108 115 123 Overview Low Power Modes 37 P Packaging 244 Page Erase operation 200 206 207 209 210 Page Erase Violation 206 Part Number Description 245 PB1 82 PHI see system clock Pin Characteristics 20 PS015308 0404 eZ80F92 eZ80F93 Product Specification Zi ZiLOG Pin Description 4 POP Op Code Map 216 218 220 POR see Power On Reset Port x Alternate Register 1 46 Port x Alternate Register 2 46 Port x Data Direction Registers 46 Port x Data Registers 45 Power connections 2 Power On Reset 34 228 and VBO Electrical Characteristics 228 voltage threshold 34 35 228 Precharacterization Product 246 Program Counter 37 38 48 49 Programmable Reload Timers 78 Operation 79 Registers 83
152. ansmit and receive is disabled Parity bit transmit and receive is enabled For transmit a parity bit is generated and transmitted with every data character For receive the parity is checked for every incoming data character In MULTIDROP mode receive parity is checked for space parity 2 0 CHAR 000 111 UART Character Parameter Selection see UART Character Parameter Definition for a description of the values Note Receive Parity is set to SPACE in MULTIDROP mode PS015308 0404 PRELIMINARY Universal Asynchronous Receiver Transmitter PS015308 0404 eZ80F92 eZ80F93 Product Specification VA ZiLOG Table 62 UART Character Parameter Definition Character Length Stop Bits CHAR 2 0 Tx Rx Data Bits Tx Stop Bits 000 5 1 001 6 1 010 7 1 011 8 1 100 5 2 101 6 2 110 7 2 111 8 2 Table 63 Parity Select Definition for Multidrop Communications MDM EPS UARTx_MGTL 5 UARTx_LCTL940 Parity Type 0 0 odd 0 1 even 1 0 space 1 1 mark Note In MULTIDROP mode EPS resets to O after the first character is sent PRELIMINARY Universal Asynchronous Receiver Transmitter eZ80F92 eZ80F93 Product Specification L i ZiLOG UART Modem Control Register This register is used to control and check the modem status as detailed in UART Modem Control Registers UARTO_MCTL 00C4h UART1_MCTL 00D4h Table 64 UART Modem Control Registers UARTO_MCTL
153. ar IFLG Receive data byte ACK transmitted clear AAK 0 transmit NACK Or read DATA clear IFLG Receive data byte set AAK 1 transmit ACK 58h Data byte received Read DATA set STA Transmit repeated START NACK transmitted clear IFLG Or read DATA set STP Transmit STOP clear IFLG Or read DATA set Transmit STOP then STA amp STP clear IFLG START 38h Arbitration lost in Same as master transmit Same as master transmit NACK bit When all bytes are received a NACK should be sent then the microcontroller should write a 1 to the STP bit in the I2C_CTL register The PC then transmits a STOP condition clears the STP bit and returns to the idle state Slave Transmit In SLAVE TRANSMIT mode a number of bytes are transmitted to a master receiver The I C enters SLAVE TRANSMIT mode when it receives its own slave address and a Read bit after a START condition The I C then transmits an acknowledge bit if the AAK bit is set to 1 and sets the IFLG bit in the I2C_CTL register and the I2C SR register con tains the status code A8h Note When C contains a 10 bit slave address signified by FOh F7h in the I2C_SAR register it transmits an acknowledge after the first address byte is received after a restart An interrupt is generated IFLG is set but the status does not change No second address byte is sent by the master It is up to the slave to remember it had been selected prior to the restart rc goes from MASTER mode to
154. arate Address and Data Buses Table 16 Intel Bus Mode Read States Separate Address and Data Buses STATE T1 The Read cycle begins in State T1 The CPU drives the address onto the address bus and the associated Chip Select signal is asserted The CPU drives the ALE signal High at the beginning of T1 During the middle of T1 the CPU drives ALE Low to facilitate the latching of the address STATE T2 During State T2 the CPU asserts the RD signal Depending on the instruction either the MREQ or IORQ signal is asserted PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification VAF ZiLOG Table 16 Intel Bus Mode Read States Separate Address and Data Buses STATE T3 During State T3 no bus signals are altered If the external READY WAIT pin is driven Low at least one CPU system clock cycle prior to the beginning of State T3 additional wait states TyyAjT are asserted until the READY pin is driven High STATE TA The CPU latches the Read data at the beginning of State T4 The CPU deasserts the RD signal and completes the Intel bus mode cycle During Write operations with separate address and data buses the Intel bus mode employs 4 states T1 T2 T3 and T4 as described in Intel Bus Mode Write States Separate Address and Data Buses Table 17 Intel Bus Mode Write States Separate Address and Data Buses STATE T1 The Write cycle begins in State T1 The CPU
155. are not implemented Read access to such addresses returns unpredictable values and Write access produces no effect Register Map diagrams the register map for the eZ80F92 device Table 3 Register Map Address Reset CPU Page hex Mnemonic Name hex Access Programmable Reload Counter Timers 0080 TMRO_CTL Timer 0 Control Register 00 R W 85 0081 TMRO_DR_L Timer 0 Data Register Low Byte 00 R 86 TMRO_RR_L Timer 0 Reload Register Low Byte 00 W 87 0082 TMRO_DR_H Timer 0 Data Register High Byte 00 R 87 TMRO_RR_H Timer 0 Reload Register High Byte 00 W 88 0083 TMR1_CTL Timer 1 Control Register 00 R W 85 0084 TMR1_DR_L Timer 1 Data Register Low Byte 00 R 86 TMR1_RR_L Timer 1 Reload Register Low Byte 00 W 87 0085 TMR1_DR_H Timer 1 Data Register High Byte 00 R 87 TMR1_RR_H Timer 1 Reload Register High Byte 00 W 88 0086 TMR2_CTL Timer 2 Control Register 00 R W 85 Notes 1 After an external pin reset the Watch Dog Timer Control register is reset to O0h After a Watch Dog Timer time out reset the Watch Dog Timer Control register is reset to 20h 2 When the CPU reads this register the current sampled value of the port is read 3 Read Only if RTC registers are locked Read Write if RTC registers are unlocked 4 After an external pin reset or a Watch Dog Timer reset the RTC Control register is reset to x0xxxx0OOb After an RTC Alarm sleep mode recovery reset the RTC Control register is rese
156. as an interrupt input Each Port C pin when programmed as output can be selected to be an open drain or open source output Port C is multiplexed with one UART CTS1 Clear To Send Input Active Low Modem status signal to the UART This signal is multiplexed with PC3 80 PC4 GPIO Port C Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port C pin when programmed as output can be selected to be an open drain or open source output Port C is multiplexed with one UART DTR1 Data Terminal Ready Output Active Low Modem control signal to the UART This signal is multiplexed with PC4 81 PC5 GPIO Port C Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port C pin when programmed as output can be selected to be an open drain or open source output Port C is multiplexed with one UART DSR1 Data Set Ready Input Active Low Modem status signal to the UART This signal is multiplexed with PC5 PS015308 0404 PRELIMINARY Architectural Overview 16 eZ80F92 eZ80F93 Product Specification 17 ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Continued Pin Symbol Function Signal Direction
157. asing Flash Memory Erasing bytes in Flash memory returns them to a value of FFh Both the Mass and Page Erase operations are self timed by the Flash controller leaving the CPU free to execute other operations in parallel The DONE status bit in the Flash Interrupt Control Register can be polled by software or used as an interrupt source to signal completion of an Erase operation If the CPU attempts to access Flash while an Erase is in progress the Flash con troller forces a WAIT state until the Erase operation completes Mass Erase Performing a Mass Erase operation on Flash memory erases all bits in Flash including the Information Page This self timed operation takes approximately 200ms to complete Page Erase The smallest erasable unit in Flash memory is a page Which of the main Flash memory pages or the single Information Page is to be erased is determined by the setting of the FLASH_PAGE register This self timed operation takes approximately 10ms to complete Flash Control Registers PS015308 0404 The Flash register interface contains all the registers used in Flash memory The defini tions below describe each register Flash Key Register Writing the two byte sequence B6h 49h in immediate succession to this register unlocks the Flash Divider and Flash Write Erase Protection registers If these values are not writ PRELIMINARY Flash Memory eZ80F92 eZ80F93 Product Specification 201 ZiLOG ten by consecutive CPU I
158. assed The PRT counters decrement on every rising edge of the port pin The port pins must be con figured as inputs Due to the input sampling on the pins the event input signal frequency is limited to one half the system clock frequency Input sampling on the port pins results in the PRT counter being updated on the fifth rising edge of the system clock after the rising edge occurs at the port pin Timer Output Two of the Programmable Reload Timers Timers 4 and 5 can be directed to GPIO Port B output pins PB4 and PBS respectively To enable the Timer Out feature the GPIO port pin must be configured for alternate functions After reset the Timer Output feature is dis abled by default The GPIO output pin toggles each time the PRT reaches its end of count value In CONTINUOUS mode operation the disabling of the Timer Output feature results in a Timer Output signal period that is twice the PRT time out period Examples of the Timer Output operation are illustrated in Figure 22 and PRT Timer Out Operation Example In these examples the GPIO output is assumed to be Low 0 when the Timer Output function is enabled PS015308 0404 PRELIMINARY Programmable Reload Timers CLK PRT Clock Clock 4 IOWRN PRT Count Value Timer Output eZ80F92 eZ80F93 Product Specification Z ZiLOG lt O Write to TMRx CTL Enables PRT Figure 22 PRT Timer Output Operation Example Table 32 PRT Timer Out Operation Example
159. ation The Reset controller within the eZ80F92 device provides a consistent reset function for all types of resets that can affect the system A system reset referred to in this document as RESET returns the eZ80F92 device to a defined state All internal registers affected by RESET return to their default conditions RESET configures the GPIO port pins as inputs and clears the CPU s Program Counter to 000000h Program code execution ceases dur ing RESET The events that can cause a RESET are Power On Reset POR Low Voltage Brown Out VBO External RESET pin assertion Watch Dog Timer WDT time out when configured to generate a RESET Real Time Clock alarm with the CPU in low power SLEEP mode Execution of a debug reset command During a RESET an internal RESET mode timer holds the system in RESET mode for 257 system clock SCLK cycles The RESET mode timer begins incrementing on the next rising edge of SCLK following deactivation of all RESET events gt Note The user must determine if 257 SCLK cycles provides sufficient time for the pri mary crystal oscillator to stabilize Power On Reset A Power On Reset POR occurs each time the supply voltage to the part rises from below the voltage brown out threshold to above the POR voltage threshold Vpop The internal bandgap referenced voltage detector sends a continuous RESET signal to the Reset con troller until the supply voltage Vcc exceeds the POR voltage thr
160. ation is complete 0 0 Mass Erase Disable Mass Erase completed MASS_ERASE Mass Erase Enable This bit automatically resets to 0 when the Mass Erase operation is complete PRELIMINARY Flash Memory eZ80F92 eZ80F93 Product Specification AR ZiLOG eZ80 CPU Instruction Set Tables 126 through 135 indicate the eZ809 CPU instructions available for use with the eZ80F92 device The instructions are grouped by class More detailed information is avail able in the eZ80 CPU User Manual UM0077 Table 126 Arithmetic Instructions Mnemonic Instruction ADC Add with Carry ADD Add without Carry CP Compare with Accumulator DAA Decimal Adjust Accumulator DEC Decrement INC Increment MLT Multiply NEG Negate Accumulator SBC Subtract with Carry SUB Subtract without Carry Table 127 Bit Manipulation Instructions Mnemonic Instruction BIT Bit Test RES Reset Bit SET Set Bit Table 128 Block Transfer and Compare Instructions Mnemonic Instruction CPD CPDR Compare and Decrement with Repeat CPI CPIR Compare and Increment with Repeat LDD LDDR Load and Decrement with Repeat LDI LDIR Load and Increment with Repeat PS015308 0404 PRELIMINARY eZ80 CPU Instruction Set eZ80F92 eZ80F93 Product Specification zZ 212 ZiLOG PS015308 0404 PRELIMINARY eZ80 CPU Instruction Set PS015308 0404 eZ80F92 eZ80F93 Product Specification
161. ations A single byte I O Write operation uses I O registers for setting the column page and row address to be programmed The FLASH_DATA register stores the data to be written While the CPU executes an output to I O instruction to load the data into the FLASH DATA register the Flash controller asserts the internal WAIT signal to stall the CPU until the Flash Write operation is complete A single byte Write takes between 66 us and 85s to complete Programming an entire row 128 bytes using single byte Writes therefore takes at most 10 8 ms This measure of time does not include the time required by the CPU to transfer data to the registers which is a function of the instructions employed and the system clock frequency PS015308 0404 PRELIMINARY Flash Memory PS015308 0404 eZ80F92 eZ80F93 Product Specification Z 199 ZiLOG A typical sequence that performs a single byte I O Write is detailed below Because the Write is self timed the sequence can be repeated back to back without any necessity for polling or interrupts 1 Write the FLASH_PAGE FLASH_ROW and FLASH_COL registers with the address of the byte to be written 2 Write the data value to the FLASH_DATA register Multibyte I O Write Row Programming Multibyte I O Write operations use the same I O registers as single byte Writes but use an internal address incrementer for subsequent Writes Multibyte Writes allow programming of a full row and are enabled by setting
162. ay ns Parameter Abbreviation Min Max T4 Clock Rise to Port Output Delay 2 0 15 0 PS015308 0404 PRELIMINARY Electrical Characteristics eZ80F92 eZ80F93 Product Specification External Bus Acknowledge Timing ZiLOG Bus Acknowledge Timing provides information on the bus acknowledge timing Once the external bus master detects BUSACK asserted and drives IORQN MREQN A 23 0 there is an asynchronous prop delay to the CS 3 0 outputs being valid Table 154 Bus Acknowledge Timing Delay ns Parameter Abbreviation Min Max Ti Clock Rise to BUSACK Assertion Delay 2 0 14 0 To Clock Rise to BUSACK Deassertion Delay 2 0 14 0 T3 IORQN MREQN A 23 0 input to CS 3 0 10 0 output prop delay External System Clock Driver PHI Timing PS015308 0404 PHI System Clock Timing provides timing information for the PHI pin The PHI pin allows external peripherals to synchronize with the internal system clock driver on the eZ80F92 device Table 155 PHI System Clock Timing Delay ns Parameter Abbreviation Min Max T4 Clock XIN Rise to PHI Rise 6 0 T2 Clock XIN Fall to PHI Fall 6 0 PRELIMINARY Electrical Characteristics 242 eZ80F92 eZ80F93 Product Specification 243 ZiLOG ZiLOG Debug Interface Timing Figure 64 and ZDI Timing Specifications provide timing information for TCK TDI TDO TMS pins TDO l X Figure 64 ZDI Timing Table 156 ZDI Timing Specifications De
163. bit O Isb of the 16 bit timer data value Timer Data Register High Byte This Read Only register returns the High byte of the current count value of the selected timer The Timer Data Register High Byte detailed in Timer Data Register High Byte TMRO DR H 0082h TMR1 DR H 0085h TMR2 DR H 0088h TMR3 DR H 008Bh TMRA DR H 008Eh or TMR5 DR H 0091h can be read while the timer is in operation Reading the current count value does not affect timer operation To read the 16 bit data of the current count value TMRx DR H 7 0 TMRx DR L 7 0 first read the Timer Data Register Low Byte and then read the Timer Data Register High Byte The Timer Data Register High Byte value is latched when a Read of the Timer Data Register Low Byte occurs Note The timer data registers and timer reload registers share the same address space PRELIMINARY Programmable Reload Timers PS015308 0404 eZ80F92 eZ80F93 Product Specification Liv ZiLOG Table 35 Timer Data Register High Byte TMRO_DR_H 0082h TMR1_DR_H 0085h TMR2_DR_H 0088h TMR3_DR_H 008Bh TMR4_DR_H 008Eh or TMR5 DR H 0091h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access R R R Note R Read only Bit Position Value Description 7 0 OO0h FFh These bits represent the High byte of the 2 byte timer data TMRx DR H value TMRx DR H 7 0 TMRx DR L 7 0 Bit 7 is bit 15 msb o
164. bus protocols the extra delay does not impact peripheral communication PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification 69 ZiLOG Chip Select Registers Chip Select x Lower Bound Register For Memory Chip Selects the Chip Select x Lower Bound register detailed in Chip Select x Lower Bound Register CSO_LBR 00A8h CS1_LBR 00ABh CS2 LBR OOAEh CS3_LBR OOB 1h defines the lower bound of the address range for which the corre sponding Memory Chip Select if enabled can be active For I O Chip Selects this regis ter defines the address to which ADDR 15 8 is compared to generate an I O Chip Select All Chip Select lower bound registers reset to 00h Table 22 Chip Select x Lower Bound Register CSO_LBR 00A8h CS1_LBR 00ABh CS2 LBR 00AEh CS3 LBR 00B1h Bit CSO0 LBR Reset CS1 LBR Reset CS2 LBR Reset CS3 LBR Reset CPU Access RW RW RW RW RW RW RW RW Note R W Read Write O o o o O o o o o oO o o o a oO oO O oO A oO CO CO O amp Oo Oo CO OC N oO oO o o oO oO oO o0 o Bit Position Value Description 7 0 00h For Memory Chip Selects CSX IO 0 CSx_LBR FFh This byte specifies the lower bound of the Chip Select address range The upper byte of the address bus ADDR 23 16 is compared to the values contained in these registers for determining whether a
165. cal ZiLOG Sales Office to order these devices ZiLOG provides additional assistance on its Customer Service page and is also here to help with technical support issues For ZILOG s valuable software development tools and downloadable software visit the ZiLOG website Part Number Description ZiLOG part numbers consist of a number of components as indicated in the following examples ZiLOG Base Products eZ80 ZiLOG eZ80 CPU F92 Product Number AZ Package 020 Speed SorE Temperature C Environmental Flow PS015308 0404 PRELIMINARY Ordering Information eZ80F92 eZ80F93 Product Specification Zi ZiLOG Package AZ LQFP also called the VQFP Speed 020 20MHz Standard Temperature S 0 C to 70 C Extended Temperature E 40 C to 105 C Environmental Flow C Plastic Standard Example Part number eZ80F92AZ020SC is an eZ80Acclaim product in an LQFP package operating with a 20M Hz external clock frequency over a 0 C to 70 C tempera ture range and built using the Plastic Standard environmental flow Precharacterization Product PS015308 0404 The product represented by this document is newly introduced and ZiLOG has not com pleted the full characterization of the product The document states what ZiLOG knows about this product at this time but additional features or nonconformance with some aspects of the document might be found either by ZiLOG or its custome
166. ccessed via the clock TCK and data TDI pins See the ZiLOG Debug Interface sec tion on page 163 for more information on ZDI OCI Interface There are five dedicated pins on the eZ80F92 device for the OCI interface Four pins TCK TMS TDI and TDO are required for IEEE Standard 1149 1 compliant JTAG ports The TRIGOUT pin provides additional testability features These five OCI pins are described in OCI Pins Table 111 OCI Pins Symbol Name Type Description TCK Clock Input Asynchronous to the primary CPU system clock The TCK period must be at least twice the system clock period During RESET this pin is sampled to select either OCI or ZDI DEBUG modes If Low during RESET the OCI is enabled If High during RESET the OCI is powered down and ZDI DEBUG mode is enabled When ZDI DEBUG mode is active this pin is the ZDI clock On chip pull up ensures a default value of 1 High TMS Test Mode Select Input This serial test mode input controls JTAG mode selection On chip pull up ensures a default value of 1 High The TMS signal is sampled on the rising edge of the TCK signal TDI Data In Input OCI enabled Serial test data input On chip pull up ensures a default value of 1 High This pin is input only when the OCI is enabled The input data is sampled on the rising edge of the TCK signal I O OCI disabled When the OCI is disabled this pin functions as the ZDA ZDI Data I O
167. cimal Operation BCD EN 1 Bit Position Value Description 7 4 0 9 The tens digit of the current century count TENS_CEN 3 0 0 9 The ones digit of the current century count CEN Binary Operation BCD_EN 0 Bit Position Value Description 7 0 00h The current century count CEN 63h PRELIMINARY Real Time Clock PS015308 0404 eZ80F92 eZ80F93 Product Specification 100 ZiLOG Real Time Clock Alarm Seconds Register This register contains the alarm seconds value See Real Time Clock Alarm Seconds Reg ister RTC_ASEC 00E8h Table 47 Real Time Clock Alarm Seconds Register RTC_ASEC 00E8h Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access RW RW RW RW RAW RW RW RW Note X Unchanged by RESET R W Read Write Binary Coded Decimal Operation BCD_EN 1 Bit Position Value Description 7 4 0 5 The tens digit of the alarm seconds value ATEN_SEC 3 0 0 9 The ones digit of the alarm seconds value ASEC Binary Operation BCD_EN 0 Bit Position Value Description 7 0 00h The alarm seconds value ASEC 3Bh PRELIMINARY Real Time Clock PS015308 0404 eZ80F92 eZ80F93 Product Specification 101 ZiLOG Real Time Clock Alarm Minutes Register This register contains the alarm minutes value See Real Time Clock Alarm Minutes Reg ister RTC_AMIN 00E9h Table 48 Real Time Clock
168. clock frequency When configured for event inputs through the port pins the Timers decrement on the fifth system clock rising edge following the rising edge of the port pin PS015308 0404 PRELIMINARY Programmable Reload Timers eZ80F92 eZ80F93 Product Specification Table 38 Timer Input Source Select Register TMR_ISS 0092h Z ZiLOG Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RAW RW RW RW RW RW RW RW Note R W Read Write Bit Position Value Description 7 6 00 The timer counts at the system clock divided by the TMR3_IN prescaler 01 The timer event input is the Real Time Clock source 32KHz or 50 60Hz refer to the Real Time Clock section on page 90 for details 10 The timer event input is the GPIO Port B pin 1 11 The timer event input is the GPIO Port B pin 1 5 4 00 The timer counts at the system clock divided by the TMR2_IN prescaler 01 The timer event input is the Real Time Clock source 32KHz or 50 60Hz refer to the Real Time Clock section on page 90 for details 10 The timer event input is the GPIO Port B pin 0 11 The timer event input is the GPIO Port B pin 0 3 2 00 The timer counts at the system clock divided by the TMR1_IN prescaler 01 The timer event input is the Real Time Clock source 32KHz or 50 60Hz refer to the Real Time Clock section on page 90 for details 10 The timer event in
169. coder PS015308 0404 eZ80F92 eZ80F93 Product Specification 131 ZiLOG Infrared Encoder Decoder Register After a RESET the Infrared Encoder Decoder register is set to its default value Any writes to unused register bits are ignored and reads return a value of 0 The IR_CTL regis ter is described in Infrared Encoder Decoder Control Registers IR_CTL OOBFh Table 71 Infrared Encoder Decoder Control Registers IR CTL 00BFh Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RW RW RW RW RAN RW RW RW Note R Read only R W Read Write ien Value Description 7 3 000000 Reserved 2 0 Internal LOOP BACK mode is disabled ERO BAGR 1 Internal LOOP BACK mode is enabled IR_TxD output is inverted and connected to IR_RxD input for internal loop back testing 1 0 IR_RxD data is ignored IBSEN 1 IR_RxD data is passed to UARTO RxD 0 0 IrDA endec is disabled IREN 1 IrDA endec is enabled PRELIMINARY Infrared Encoder Decoder eZ80F92 eZ80F93 Product Specification ZiLOG Serial Peripheral Interface The Serial Peripheral Interface SPD is a synchronous interface allowing several SPI type devices to be interconnected The SPI is a full duplex synchronous character oriented communication channel that employs a four wire interface The SPI block consists of a transmitter receiver baud rate generator and control unit During an SPI
170. cteristics DC Characteristics lists the DC characteristics of the eZ80F92 device gt Note All data is preliminary and subject to change following completion of production characterization PS015308 0404 PRELIMINARY Electrical Characteristics Table 146 DC Characteristics eZ80F92 eZ80F93 Product Specification Zi ZiLOG TA 0 C to 70 C TA 0 C to 105 C Symbol Parameter Min Max Min Max Units Conditions Vpp Supply Voltage 3 0 3 6 3 0 3 6 V Vi Low Level 0 3 0 8 0 3 0 8 V Input Voltage Vin High Level 0 7xVpp 5 5 0 7xVpp 5 5 V Input Voltage VoL Low Level 0 4 0 4 V Vpp 3 0V Output Voltage lol 1mA Vou High Level 24 24 V Vpp 3 0V Output Voltage lon 1mA li Input Leakage 10 10 20 20 HA Vpp 3 6V Current Vin Vpp or Vss Ir Tristate Leakage 10 10 20 20 HA Vpp 3 6V Current Ipy Internal Pull Up 100 100 HA Vpp 3 6V Current Typical Typical 25 C Power Dissipation 33 33 mA F 20MHz normal operation Typical Typical Vpp 3 3V 7 Wait States 25 C Power Dissipation 21 21 mA F 20MHz HALT mode Typical Typical Vpp 3 3V 25 C Power Dissipation 375 600 HA Vpp 3 3V Ipp SLEEP mode Typical Typical 25 C RTC Supply 3 0 3 6 3 0 3 6 V RTC Vpp Voltage RTC Supply 2 5 10 2 5 10 pA Supply current into Current Typical Typical RTC Vpp Igrc SLEEP mode Notes 1 This condition excludes all pins with on chip pull u
171. e Flash Program Control register must be set to 1 prior to beginning a multibyte I O Write operation This register does not return data from Flash memory If read this register returns the most recent data value written to the register PS015308 0404 PRELIMINARY Flash Memory eZ80F92 eZ80F93 Product Specification Zi ZiLOG Table 115 Flash Data Register FLASH_DATA 00F6h Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access RAV RW RW RW RAW RW RW RW Note R W Read Write Bit Position Value Description 7 0 00h Data value to be written to Flash during an I O Write FLASH_DATA FFh operation Flash Address Upper Byte Register The FLASH_ADDR_U register defines the upper 7 bits of the address for Flash memory Changing the value of FLASH_ADDR_U allows the on chip 128 KB 64KB Flash mem ory to be mapped to any location within the 16MB linear address space of the eZ80F92 device If the on chip Flash memory is enabled Flash address assumes priority over any external Chip Selects The external Chip Select signals are not asserted if the correspond ing Flash address is enabled The internal Flash memory does not hold priority over inter nal SRAM Table 116 Flash Address Upper Byte Register FLASH_ADDR_U 00F7h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RAW RW RW RW RW RW RW R Note R W Read W
172. e R W Read Write R Read Only Bit Position Value Description 7 3 00h Reserved 2 0 Oh 7h Row address of Flash memory to be used during an I O Write FLASH ROW to Flash memory When INFO EN is 1 in the Flash Page Select Register values for this field are restricted to Oh 1h which selects between the two rows in the Information Page PRELIMINARY Flash Memory eZ80F92 eZ80F93 Product Specification Z 209 ZiLOG Flash Column Select Register The column select register is a 7 bit value used to define one of the 128 bytes of Flash memory on a single row This register is used for all I O Write access to Flash This register must be set to the proper column location within a row to program using a single byte Write operation In multibyte row programming this register is used as the start address for the hardware incrementer Table 124 Flash Column Select Register FLASH_COL 00FEh Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access R RAW RW RW RW RW RW RW Note R W Read Write R Read Only Bit Position Value Description 7 0 Reserved 6 0 00h Column address within a row of Flash memory to be used FLASH_COL 7Fh during an I O Write of Flash memory Flash Program Control Register The Flash program control register is used to perform the functions of Mass Erase Page Erase and Row Program Mass Erase and Page Erase are
173. e 164 ZDI Start Condition i c ea eke die Pea Ra eno eta e hee ge bead es 165 ZDI Register Addressing 0 0 cece eect eee 166 ZDI Write Operations ceanna heal EUR LER E ea ee 167 ZDI Read Operations 0 0 eee nett eee 168 Operation of the eZ80F92 Device During ZDI Breakpoints 169 Bus Requests During ZDI DEBUG Mode 0 0 0 eee ee eee 170 ZDI Write Only Registers 2 eect eee 171 ZDI Read Only Registers 0 2 cece unune nrar 172 ZDI Register Definitions 000 e eee 172 On Chip Instrumentation 0 0 0 eee I 190 Introduction to On Chip Instrumentation 0 0 0 0 c eee eee eee 190 OCI Activation oie bc cea ed eee cre eges bee dcr bed der ee ee ta 190 OCI Interface sever ee ed ne ER e tap Us a e es sen e dg 191 OCI Information Requests sleleeeeeee III 192 Random Access Memory 0 cece eee cece mme 193 RAM Control Registers 2 0 0 cee cece eee nee 195 lash Memory esses gue REESE he E tee PR gage dda dates 196 Flash Memory Arrangement in the eZ80F92 0 0 eee eee eee 196 Flash Memory Arrangement in the eZ80F93 0 0 0 eee eee eee 197 Flash Memory Overview 0 ccc cece eee ee eens 197 Programming Flash Memory 00 cece eee cette teens 198 PS015308 0404 PRELIMINARY Table of Contents PS015308 0404 eZ80F92 eZ80F93 Product Specification ZiLOG Erasing Flash Memory i e re eae Rn Rd ded ded 200
174. e 2 Isb of Single Bit Single Bit ZDI Address Byte Separator Byte Separator Figure 42 ZDI Block Data Write Timing ZDI Read Operations ZDI Single Byte Read Single byte Read operations are initiated in the same manner as single byte Write opera tions with the exception that the R W bit of the ZDI register address is set to 1 Upon receipt of a slave address with the R W bit set to 1 the eZ80F92 device s ZDI block loads the selected data into the shifter at the beginning of the first cycle following the single bit data separator The most significant bit msb is shifted out first Figure 43 illustrates the timing for ZDI single byte Read operations PS015308 0404 PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification zZ 169 ZiLOG l lt ZDlDataBye 9 l l msb lsb f of DATA of DATA Isb of Single Bit End of Data ZDlAddress Byte Separator or New ZDI START Signal Figure 43 ZDI Single Byte Data Read Timing ZDI Block Read A Block Read operation is initiated the same as a single byte Read however the ZDI master continues to clock in the next byte from the ZDI slave as the ZDI slave continues to output data The ZDI register address counter increments with each Read If the ZDI regis ter address reaches the end of the Read Only ZDI register address space 20h the address stops incrementing Figure 44 illustrates the ZDI s Block Read timing l lt ZDlDataBytes 9
175. e 48 49 87 161 178 level sensitive interrupt 45 input 130 modes 43 Level Triggered Interrupts 44 Line break detection 106 Loopback Testing Infrared Encoder Decoder 130 low byte vector 47 Low Power Modes 37 LSB see least significant byte PS015308 0404 PRELIMINARY eZ80F92 eZ80F93 Product Specification Zi ZiLOG Isb see least significant bit M maskable interrupt 38 47 sources 47 vectors 48 Mass Erase operation 200 205 206 208 210 Mass Erase Violation 206 Master In Slave Out 19 133 135 MASTER mode 134 142 152 153 157 162 Start bit 147 149 151 152 154 157 158 160 Stop bit 148 149 151 152 154 157 158 160 MASTER mode SPI 135 Master Out Slave In 19 133 135 MASTER RECEIVE mode 142 150 MASTER TRANSMIT mode 142 147 MASTER EN bit 135 Memory and I O Chip Selects 50 Memory Chip Select Example 51 Memory Chip Select Operation 50 Memory Chip Select Priority 51 Memory Request 10 11 22 50 55 56 58 59 62 235 236 Hold Time 236 memory space 50 52 Memory Write 200 MISO see Master In Slave Out Mode Fault error flag 133 135 140 Modem status signal 14 16 MODF see Mode Fault error flag MOSI see Master Out Slave In most significant bit 87 88 107 108 133 144 156 159 165 168 207 most significant byte 88 Motorola Bus Mode 65 Motorola compatible 55 MREQ see Memory Request msb see most significant bit MSB see most significant byte Multibyte I O Write Row Progr
176. e CPU drives these lines only during Write cycles when the CPU is the bus master 40 DATAS Data Bus Bidirectional The data bus transfers data to and from I O and memory devices The CPU drives these lines only during Write cycles when the CPU is the bus master 41 DATA6 Data Bus Bidirectional The data bus transfers data to and from I O and memory devices The CPU drives these lines only during Write cycles when the CPU is the bus master 42 DATA Data Bus Bidirectional The data bus transfers data to and from I O and memory devices The CPU drives these lines only during Write cycles when the CPU is the bus master 43 Power Supply Power Supply 44 Vss Ground Ground 45 IORQ Input Output Request Bidirectional Active Low IORQ indicates that the CPU is accessing a location in I O space RD and WR indicate the type of access The CPU does not drive this line during RESET It is an input in bus acknowledge cycles 46 MREQ Memory Request Bidirectional Active Low MREQ Low indicates that the CPU is accessing a location in memory The RD WR and INSTRD signals indicate the type of access The CPU does not drive this line during RESET It is an input in bus acknowledge cycles PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ
177. e Real Time Clock Minutes Register RTC_MIN 00EI1h Table 40 Real Time Clock Minutes Register RTC MIN 00E1h Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access R W RAW R IW R W R W RAW R W R W Note X Unchanged by RESET R W Read Only if RTC locked Read Write if RTC unlocked Binary Coded Decimal Operation BCD EN 1 Bit Position Value Description 7 4 0 5 The tens digit of the current minutes count TEN_MIN 3 0 0 9 The ones digit of the current minutes count MIN Binary Operation BCD_EN 0 Bit Position Value Description 7 0 00h The current minutes count MIN 3Bh PRELIMINARY Real Time Clock PS015308 0404 eZ80F92 eZ80F93 Product Specification Z ZiLOG Real Time Clock Hours Register This register contains the current hours count See Real Time Clock Hours Register RTC HRS 00E2h Table 41 Real Time Clock Hours Register RTC HRS 00E2h Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access R W RAW R IW R W R W RAW R W R W Note X Unchanged by RESET R W Read Only if RTC locked Read Write if RTC unlocked Binary Coded Decimal Operation BCD EN 1 Bit Position Value Description 7 4 0 2 The tens digit of the current hours count TEN HRS 3 0 0 9 The ones digit of the current hours count HRS
178. e ZDI Register Write Only Address Space Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access W W W W W W W W Note X Undefined W Write Bit Position Value Description 7 0 00h These registers contain the data that is written during ZDI_WR_L FFh execution of a Write operation defined by the ZDI_WR_H ZDI_RW_CTL register The 24 bit data value is stored as or ZDI WR U ZDI WR H ZDI_WR_L If less than 24 bits ZDI WR L of data are required to complete the required operation the data is taken from the least significant byte s ZDI Read Write Control Register The ZDI Read Write Control register is used in the ZDI Write Only Register address to read data from write data to and manipulate the CPU s registers or memory locations When this register is written the eZ80F92 device immediately performs the operation cor responding to the data value written as described in ZDI Read Write Control Register Functions ZDI RW CTL 16h in the ZDI Register Write Only Address Space When a Read operation is executed via this register the requested data values are placed in the ZDI Read Data registers ZDI RD U ZDI RD H ZDI RD LJ When a Write operation is executed via this register the Write data is taken from the ZDI Write Data registers ZDI WR U ZDI WR H ZDI WR LJ See ZDI Read Write Control Register Func tions ZDI RW CTL 16h in the ZDI Register Write Only Address Space
179. e end of State T3 During Write operations Z80 bus mode employs 3 states T1 T2 and T3 as described in Z80 Bus Mode Write States PS015308 0404 PRELIMINARY Chip Selects and Wait States 55 eZ80F92 eZ80F93 Product Specification VAF ZiLOoOG Table 15 Z80 Bus Mode Write States STATE T1 The Write cycle begins in State T1 The CPU drives the address onto the address bus the associated Chip Select signal is asserted STATE T2 During State T2 the WR signal is asserted Depending upon the instruction either the MREQ or IORQ signal is asserted If the external WAIT pin is driven Low at least one CPU system clock cycle prior to the end of State T2 additional WAIT states TywAjT are asserted until the WAIT pin is driven High STATE T3 During State T3 no bus signals are altered Z80 bus mode Read and Write timing is illustrated in Figures 9 and 10 The Z80 bus mode states can be configured for 1 to 15 CPU system clock cycles In the figures each Z80 bus mode state is two CPU system clock cycles in duration Figures 9 and 10 also illustrate the assertion of 1 wait state Twarr by the external peripheral during each Z80 bus mode cycle l I System Clock I I DATA 7 0 l I I I l I I I I l l I d I l I 1 CSx I I l I I Figure 9 Example Z80 Bus Mode Read Timing PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification
180. e slave device A Write to the SPI_TSR register places data directly into the shift register for transmission A Write to this register within an SPI device config ured as a master initiates transmission of the byte of the data loaded into the register At the completion of transmitting a byte of data the SPIF status bit SPI_SR 7 is set to 1 in both the master and slave devices The SPI Transmit Shift Write Only register shares the same address space as the SPI Receive Buffer Read Only register See SPI Transmit Shift Register SPI TSR 00BCh Table 77 SPI Transmit Shift Register SPI TSR 00BCh Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access W W W W W W W W Note W Write only Bit Position Value Description 7 0 00h SPI transmit data TX_DATA FFh SPI Receive Buffer Register The SPI Receive Buffer register SPI_RBR is used by the SPI slave to receive data from the serial bus The SPIF bit must be cleared prior to a second transfer of data from the shift register or an overrun condition exists In cases of overrun the byte that caused the overrun is lost The SPI Receive Buffer Read Only register shares the same address space as the SPI Transmit Shift Write Only register See SPI Receive Buffer Register SPI_RBR 00BCh Table 78 SPI Receive Buffer Register SPI RBR 00BCh Bit 7 6 5 4 3 2 1 0 Reset X X X
181. ece eee 243 Packaging 222129 ye cle PR RO EG RE Sa pur Ee Ope Y ee ope d dasa 244 Ordering Information 0 nn e eee nea 245 Part Number Description 0 0 cece cece eee eens 245 Precharacterization Product 1 1 0 ccc eect eee 246 Document Information 0 0 cece me 247 Document Number Description 0 0 ee eee 247 Change Lot re ois cscs ayaa ecient a ead abides eee aaa 247 luno qe rr 248 Customer Feedback Form 0 cece cece eee ene ree 258 PRELIMINARY Table of Contents vi eZ80F92 eZ80F93 Product Specification List of Figures PS015308 0404 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 ZiLOG eZ80F92 Block Diagram 0 eee III 3 100 Pin LQFP Configuration of the eZ80F92 Device 4 GPIO Port Pin Block Diagram 0 0 2 cece eee 44 Example Memory Chip Select 0 0 0 0 cee eee eee eee eee 51 Wait Input Sampling Block Diagram esee 53 Example Z80 Bus Mode Write Timing 0 000000 ee eee 57 Intel Bus Mode Signal and Pin Mapping 0 0 5 58 Example Intel
182. econds The FREQ DIV value must be rounded to the nearest integer and the resulting period of the 6 bit frequency divider must not be larger than 1 4 seconds which is the IrDA defined minimum pulse width If the period is greater than 1 4 seconds FREQ DIV should be rounded to the next lower integer The receiver frequency divider value versus the system clock frequency is shown in Table 2 below Table 69 Frequency Divider Values System Clock FREQ DIV 5 0MHz 00h 5 0 7 8MHz 01h 7 8 10 8MHz 02h 10 8 13 6MHz 03h 13 6 25MHz FLOOR 4 bit Frequency Divider Factor 25 50 MHz ROUND 4 bit Frequency Divider Factor Note The frequency divider is disabled when set to OOh PRELIMINARY Infrared Encoder Decoder eZ80F92 eZ80F93 Product Specification 130 ZiLOG Setting the upper 4 bits of IR_CTL to 00h disables the frequency divider but not the IrDA receiver In this mode the IrDA receiver uses edge detection on the IR_RxD bit stream Jitter Due to the inherent sampling of the received IR_RxD signal by the BIt Rate Clock some jitter can be expected on the first bit in any sequence of data However all subsequent bits in the received data stream are a fixed 16 clock periods wide Infrared Encoder Decoder Signal Pins The IrDA endec signal pins IR TxD and IR RxD are multiplexed with General Purpose I O GPIO pins These GPIO pins must be configured for alternate function operation for the endec to ope
183. efore enabled For general data communication the data value on the ZDA pin can change only when ZCL is Low 0 The only exception is the ZDI START bit which is indicated by a High to Low transition falling edge on the ZDA pin while ZCL is High Data is shifted into and out of ZDI with the most significant bit bit 7 of each byte being first in time and the least significant bit bit 0 Jast in time All information is passed between the master and the slave in 8 bit single byte units Each byte is transferred with nine clock cycles eight to shift the data and the ninth for internal operations ZDI START Condition All ZDI commands are preceded by the ZDI START signal which is a High to Low tran sition of ZDA when ZCL is High The ZDI slave on the eZ80F92 device continually mon itors the ZDA and ZCL lines for the START signal and does not respond to any command until this condition is met The master pulls ZDA Low with ZCL High to indicate the beginning of a data transfer with the ZDI block Figures 38 and 39 illustrate a valid ZDI START signal prior to writing and reading data respectively A Low to High transition of ZDA while the ZCL is High yields no effect Data is shifted in during a Write to the ZDI block on the rising edge of ZCL as illustrated in Figure 38 Data is shifted out during a Read from the ZDI block on the falling edge of ZCL as illustrated in Figure 39 When an operation is completed the master stops during the
184. egisters or interrupt signals A simplified block diagram of a programmable reload timer is illustrated in Figure 20 Data 7 0 Data 7 0 Reload Registers Control Register TMRx RR H TMRx RR Lj TMRx CTL 16 Bit Down Counter Data Registers TMRx DR H TMRx DR Lj Data 7 0 System Clock x Adjustable IRQ to eZ80 CPU RTC Source 3 Clock Prescaler f F TMRx IN TMRx CTL 3 2 Timers 0 3 only Control Logic TOUT EN Timers 4 5 only Timer Out GPIO Pin gt Figure 20 Programmable Reload Timer Block Diagram PS015308 0404 PRELIMINARY Programmable Reload Timers eZ80F92 eZ80F93 Product Specification Z ZiLOG Programmable Reload Timer Operation PS015308 0404 Setting Timer Duration There are three factors to consider when determining Programmable Reload Timer dura tion clock frequency clock divider ratio and initial count value Minimum duration of the timer is achieved by loading 0001h Maximum duration is achieved by loading 0000h because the timer first rolls over to FFFFh and then continues counting down to 0000h The time out period of the PRT is returned by the following equation Clock Divider Ratio x Reload Value PRT Time Out Period System Clock Frequency To calculate the time out period with the above equation when using an initial value of 0000h enter a reload value of 65536 FFFFh 1 Minimum time out duration is 4 times longer tha
185. eiver decoder is enabled PRELIMINARY Infrared Encoder Decoder 127 eZ80F92 eZ80F93 Product Specification 128 ZiLOG The UART baud rate clock is used by the IrDA endec to generate the demodulated signal RxD that drives the UART Each UART bit period is sixteen baud clocks wide Each IR_RXD bit is encoded during a bit period such that a 0 is represented by a pulse and a 1 is represented by no pulse The IrDA Physical Layer Specification describes a nominal pulse as being 3 16 Of a bit period wide In this case if the data to be received is a logical 0 Low a 3 clock wide Low 0 pulse is received following a 7 clock High 1 period Fol lowing the 3 clock Low pulse is a 6 clock High pulse to complete the full 16 clock data period If the data to be received is a logical 1 High the IR_RxD signal is held High 1 for the full 16 clock period Data reception is illustrated in Figure 27 I I I I po gt l I I I Baud Rate Clock StartBitz 0 DataBito 1 DataBit1 0 DataBit2 1 DataBit3 1 IR RxD I I gt 14us l l I min pulse I I I I I I I UART RxD I I l l 16 clock PE 16 clock 16 clock 16 clock pe gt be period gt period gt I period gt lt period Figure 27 Infrared Data Reception The IrDA Physical Layer Specification allows for a minimum signal width as well as the nominal signal width described above By definition the received pulse duration can be as small as 1
186. emory array When the main array is selected the lower 7 bits 6 bits in the eZ80F93 device are used to select one of the 128 pages for Page Erase or I O Write operations To perform a Page Erase the software must set the proper page value prior to setting the Page Erase bit in the Flash control register PRELIMINARY Flash Memory PS015308 0404 eZ80F92 eZ80F93 Product Specification Zi ZiLOG Table 122 Flash Page Select Register FLASH_PAGE 00FCh Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RW RW RW RW RW RW RW RW Note R W Read Write R Read Only Bit Position Value Description 7 0 Flash accesses main Flash memory INFO_EN 1 Flash accesses the Information Page Page Erase and Mass Erase operations affect the Information Page only 6 0 00h Page address of Flash memory to be used during the Page FLASH_PAGE 7Fh Erase or I O Write of the main Flash memory When INFO EN is set to 1 this field is ignored Note Only 6 bits are available in the eZ80F93 device Flash Row Select Register The Flash Row Select register is a 3 bit value used to define one of the 8 rows of Flash memory on a single page This register is used for all I O Write access to Flash Table 123 Flash Row Select Register FLASH ROWZ00FDh Bit 7 6 5 4 3 2 1 0 Reset X X X X X 0 0 0 CPU Access R R R R R RAW RW RAW Not
187. emoves all of the received data bytes It reads the UARTXx LSR register before reading the UARTx_RBR register to determine that there is no error in the received data To control and check modem status the application sets up the modem by writing to the UARTx MCTL register and reading the UARTx MSR register before starting the process mentioned above Poll Mode Transfers When interrupts are disabled all data transfers are referred to as poll mode transfers In poll mode transfers the application must continually poll the UARTXx LSR register to transmit or receive data without enabling the interrupts The same is true for the UARTx_MSR register If the interrupts are not enabled the data in the UARTX IIR register cannot be used to determine the cause of an interrupt Baud Rate Generator The Baud Rate Generator consists of a 16 bit downcounter two registers and associated decoding logic The initial value of the Baud Rate Generator is defined by the two BRG Divisor Latch registers UARTx_BRG_H UARTx_BRG_L At the rising edge of each system clock the BRG decrements until it reaches the value 0001n On the next system clock rising edge the BRG reloads the initial value from UARTx_BRG_H UARTx_BRG_L and outputs a pulse to indicate the end of count Calculate the UART data rate with the following equation System Clock Frequency UART Data Rate bits s 16 X UART Baud Rate Generator Divisor Upon RESET the 16 bit BRG divis
188. en this Chip Select is active 011 3 WAIT states are asserted when this Chip Select is active 100 4 WAIT states are asserted when this Chip Select is active 101 5 WAIT states are asserted when this Chip Select is active 110 6 WAIT states are asserted when this Chip Select is active 111 7 WAIT states are asserted when this Chip Select is active 4 0 Chip Select is configured as a Memory Chip Select Ssk Jo 1 Chip Select is configured as an I O Chip Select 3 0 Chip Select is disabled CAREN 1 Chip Select is enabled 2 0 000 Reserved Chip Select x Bus Mode Control Register The Chip Select Bus Mode register detailed in Chip Select x Bus Mode Control Register configures the Chip Select for eZ80 Z80 Intel or Motorola bus modes Changing the bus mode allows the eZ80F92 device to interface to peripherals based on the Z80 Intel or Motorola style asynchronous bus interfaces When a bus mode other than CPU is pro grammed for a particular Chip Select the CSx_WAIT setting in that Chip Select Control Register is ignored PRELIMINARY Chip Selects and Wait States PS015308 0404 eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 25 Chip Select x Bus Mode Control Register CSO_BMC 00F0h CS1_BMC 00F1h CS2_BMC 00F2h CS3 BMC 00F3h Bit CS0 BMC Reset CS1 BMC Reset CS2 BMC Reset CS3 BMC Reset O o o o O o o oo O o oo o CO OC CO oo OOO OIN e E e E O o o oo CPU Acc
189. er the current sampled value of the port is read Read Only if RTC registers are locked Read Write if RTC registers are unlocked After an external pin reset or a Watch Dog Timer reset the RTC Control register is reset to x0xxxxOOb After an RTC Alarm sleep mode recovery reset the RTC Control register is reset to xOxxxx10b Read Only if Flash Memory is locked Read Write if Flash Memory is unlocked PS015308 0404 PRELIMINARY Register Map eZ80F92 eZ80F93 Product Specification Lz ZiLOG Table 3 Register Map Continued Address Reset CPU Page hex Mnemonic Name hex Access Flash Memory Control Registers continued OOFB FLASH_IRQ Flash Interrupt Control Register 00 R W 207 OOFC FLASH_PAGE Flash Page Select Register 00 R W 208 00FD FLASH ROW Flash Row Select Register 00 R W 208 OOFE FLASH_COL Flash Column Select Register 00 R W 209 OOFF FLASH PGCTL Flash Program Control Register 00 R W 210 Notes 1 After an external pin reset the Watch Dog Timer Control register is reset to 00h After a Watch Dog Timer time out reset the Watch Dog Timer Control register is reset to 20h 2 When the CPU reads this register the current sampled value of the port is read 3 Read Only if RTC registers are locked Read Write if RTC registers are unlocked 4 After an external pin reset or a Watch Dog Timer reset the RTC Control register is reset to x0xxxx0OOb After an RTC Alarm sleep mode recovery reset the RTC Control
190. er Out Slave In The Master Out Slave In MOST pin is configured as an output in a master device and as an input in a slave device It is one of the two lines that transfer serial data with the most significant bit sent first When the SPI is not enabled this signal is in a high impedance state Slave Select The active Low Slave Select SS input signal is used to select the SPI as a slave device It must be Low prior to all data communication and must stay Low for the duration of the data transfer The SS input signal must be High for the SPI to operate as a master device If the SS signal goes Low a Mode Fault error flag MODF is set in the SPI SR register See the SPI Sta tus Register SPI SR on page 140 for more information When the Clock Phase bit CPHA is set to 0 the shift clock is the logical OR of SS with SCK In this clock phase mode SS must go High between successive characters in an SPI message When CPHA is set to 1 SS can remain Low for several SPI characters In cases where there is only one SPI slave its SS line could be tied Low as long as CPHA is set to 1 See the SPI Control Register SPI CTL on page 139 for more information on CPHA Serial Clock The Serial Clock SCK is used to synchronize data movement both in and out of the device through its MOSI and MISO pins The master and slave are each capable of exchanging a byte of data during a sequence of eight clock cycles Because SCK is gener PRELIMINAR
191. eshold After Vcc rises above Vpog an on chip analog delay element briefly maintains the RESET signal to the Reset controller Tayna After this analog delay the eZ80F92 device is in RESET mode until the RESET mode timer expires POR operation is illustrated in Figure 3 The signals in this figure are not drawn to scale and are for illustration purposes only PS015308 0404 PRELIMINARY Reset eZ80F92 eZ80F93 Product Specification ZiLOG l System Clock annii SN l l l l l l Startup l Internal RESET l l l l l Signal Figure 3 Power On Reset Operation Voltage Brown Out Reset If after program execution begins the supply voltage Vcc drops below the Voltage Brown Out threshold Vygo the eZ80F92 device resets The VBO protection circuitry detects the low supply voltage and initiates the RESET via the Reset controller The eZ80F92 device remains in RESET mode until the supply voltage again returns above the POR voltage threshold Vpop and the Reset controller releases the internal RESET sig nal The VBO circuitry rejects very short negative brown out pulses to prevent spurious RESET events VBO operation is illustrated in Figure 4 The signals in this figure are not drawn to scale and are for illustration purposes only PS015308 0404 PRELIMINARY Reset eZ80F92 eZ80F93 Product Specification ZiLOG l l Voltage l l i Program Execution 1 Brown out I Program Execution 2 gt or 1 l lt
192. ess A oooo amp RW RW RAW RW RW RW RW Note R W Read Write R Read Only ee ilies Value Description 7 6 00 eZ80 bus mode Bip MODE 01 Z80 bus mode 10 Intel bus mode 11 Motorola bus mode 5 0 Separate address and data AD MUX 1 Multiplexed address and data appears on data bus DATA T7 0 4 0 Reserved PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification Liz ZiLOG Poalen Value Description 3 0 0000 Not valid BUS CYCLE 9004 Each bus mode state is 1 CPU clock cycle in duration 3 0010 Each bus mode state is 2 CPU clock cycles in duration 0011 Each bus mode state is 3 CPU clock cycles in duration 0100 Each bus mode state is 4 CPU clock cycles in duration 0101 Each bus mode state is 5 CPU clock cycles in duration 0110 Each bus mode state is 6 CPU clock cycles in duration 0111 Each bus mode state is 7 CPU clock cycles in duration 1000 Each bus mode state is 8 CPU clock cycles in duration 1001 Each bus mode state is 9 CPU clock cycles in duration 1010 Each bus mode state is 10 CPU clock cycles in duration 1011 Each bus mode state is 11 CPU clock cycles in duration 1100 Each bus mode state is 12 CPU clock cycles in duration 1101 Each bus mode state is 13 CPU clock cycles in duration 1110 Each bus mode state is 14 CPU clock cycles in duration 1111 Each bu
193. etermined by the one with the shortest clock High period PS015308 0404 PRELIMINARY I2C Serial I O Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification Ll us ZiLOG if 1 J 1 Wait 1 Start Counting 1 State High Period I I 1 CLK1 Signal N N Counter Reset CLK2 Signal SCL Signal N Figure 35 Clock Synchronization In PC Protocol Arbitration A master may start a transfer only if the bus is free Two or more masters may generate a START condition within the minimum hold time of the START condition which results in a defined START condition to the bus Arbitration takes place on the SDA line while the SCL line is at the High level in such a way that the master which transmits a High level while another master is transmitting a Low level switches off its data output stage because the level on the bus doesn t correspond to its own level Arbitration can continue for many bits Its first stage is comparison of the address bits If the masters are each trying to address the same device arbitration continues with compar ison of the data Because address and data information on the C bus is used for arbitra tion no information is lost during this process A master which loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration If a master also incorporates a slave function and it loses arbitration during the addressing stage it s possible tha
194. f the 16 bit timer data value Bit 0 is bit 8 of the 16 bit timer data value Timer Reload Register Low Byte The Timer Reload Register Low Byte detailed in Timer Reload Register Low Byte TMRO RR L 0081h TMR1 RR L 0084h TMR2 RR L 0087h TMR3 RR L 008Ah TMRA RR L 008Dh or TMR5 RR L 0090h stores the least significant byte LSB of the 2 byte timer reload value In CONTINUOUS mode the timer reload value is reloaded into the timer upon end of count When RST EN TMRx CTL 1 is set to 1 to enable the automatic reload and restart function the timer reload value is written to the timer on the next rising edge of the clock Note The Timer Data registers and Timer Reload registers share the same address space Table 36 Timer Reload Register Low Byte TMRO RR L 0081h TMR1 RR L 0084h TMR2 RR L 0087h TMR3 RR L 008Ah TMR4 RR L 008Dh or TMR5 RR L 0090h Bit 3 Reset 0 0 0 0 0 0 0 0 CPU Access W W W W W W W Note W Write only Bit Position Value Description 7 0 00h FFh These bits represent the Low byte of the 2 byte timer TMRx_RR_L reload value TMRx RR H 7 0 TMRx RR L 7 0 Bit 7 is bit 7 of the 16 bit timer reload value Bit 0 is bit O Isb of the 16 bit timer reload value PRELIMINARY Programmable Reload Timers eZ80F92 eZ80F93 Product Specification 88 ZiLOG Timer Reload Register High Byte The Timer Reload Register
195. f the re When each of these states is entered the corresponding status code appears in this register and the IFLG bit in the I2C_CTL register is set When the IFLG bit is cleared the status code returns to F8h Table 90 C Status Codes Code Status 00h Bus error 08h START condition transmitted 10h Repeated START condition transmitted 18h Address and Write bit transmitted ACK received 20h Address and Write bit transmitted ACK not received 28h Data byte transmitted in MASTER mode ACK received 30h Data byte transmitted in MASTER mode ACK not received 38h Arbitration lost in address or data byte PRELIMINARY I2C Serial I O Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification Z 160 ZiLOG Table 90 C Status Codes Continued Code Status 40h Address and Read bit transmitted ACK received 48h Address and Read bit transmitted ACK not received 50h Data byte received in MASTER mode ACK transmitted 58h Data byte received in MASTER mode NACK transmitted 60h Slave address and Write bit received ACK transmitted 68h Arbitration lost in address as master slave address and Write bit received ACK transmitted 70h General Call address received ACK transmitted 78h Arbitration lost in address as master General Call address received ACK transmitted 80h Data byte received after slave address received ACK tran
196. fication Table 79 PC Master Transmit Status Codes Zi ZiLOG Code 18h PC State Addr W transmitted ACK received Microcontroller Response For a 7 bit address write byte to DATA clear IFLG Next I2C Action Transmit data byte receive ACK Or set STA clear IFLG Transmit repeated START Or set STP clear IFLG Transmit STOP Or set STA amp STP clear Transmit STOP then IFLG START For a 10 bit address write extended address byte to DATA clear IFLG Transmit extended address byte 20h Addr W transmitted ACK not received Same as code 18h Same as code 18h 38h Arbitration lost Clear IFLG Return to idle Or set STA clear IFLG Transmit START when bus is free 68h Arbitration lost W received ACK transmitted Clear IFLG AAK 0 Receive data byte transmit NACK Or clear IFLG AAK 1 Receive data byte transmit ACK 78h Arbitration lost General call addr received ACK transmitted Same as code 68h Same as code 68h BOh Arbitration lost SLA R received ACK transmitted Write byte to DATA clear IFLG clear AAK 0 Transmit last byte receive ACK Or write byte to DATA clear IFLG set AAK 1 W Write bit that is the Isb is cleared to 0 Transmit data byte receive ACK If 10 bit addressing is being used then the status code is 18h or 20h after the first part of a 10 bit address plus the Write bit
197. fter an RTC Alarm sleep mode recovery reset the RTC Control register is reset to xOxxxx10b Read Only if Flash Memory is locked Read Write if Flash Memory is unlocked PS015308 0404 PRELIMINARY Register Map Table 3 Register Map Continued eZ80F92 eZ80F93 Product Specification VAF ZiLOG Address Reset CPU Page hex Mnemonic Name hex Access Universal Asynchronous Receiver Transmitter 0 UARTO Block 00CO UARTO RBR UART 0 Receive Buffer Register XX R 114 UARTO THR UART 0 Transmit Holding Register XX W 114 UARTO_BRG_L UART 0 Baud Rate Generator Register 02 R W 112 Low Byte 00C1 UARTO_IER UART 0 Interrupt Enable Register 00 R W 115 UARTO BRG H UART 0 Baud Rate Generator Register 00 R W 113 High Byte 00C2 UARTO_IIR UART 0 Interrupt Identification Register 01 R 116 UARTO_FCTL UART 0 FIFO Control Register 00 W 117 00C3 UARTO_LCTL UART 0 Line Control Register 00 R W 118 00C4 UARTO_MCTL UART 0 Modem Control Register 00 R W 121 00C5 UARTO_LSR UART 0 Line Status Register 60 R 122 00C6 UARTO MSR UART 0 Modem Status Register XX R 124 00C7 UARTO SPR UART 0 Scratch Pad Register 00 R W 125 C Block 00C8 I2C_SAR C Slave Address Register 00 R W 155 00C9 I2C_XSAR I C Extended Slave Address Register 00 R W 156 00CA I2C DR C Data Register 00 R W 156 00CB I2C_CTL C Control Register 00 R W 158 00CC 12C_SR C Status Register F8 R 159 I2C CCR I C Clock Control Register 00
198. gister 00 R W 89 Notes 1 After an external pin reset the Watch Dog Timer Control register is reset to OOh After a Watch Dog Timer time out reset the Watch Dog Timer Control register is reset to 20h 2 When the CPU reads this register the current sampled value of the port is read 3 Read Only if RTC registers are locked Read Write if RTC registers are unlocked 4 After an external pin reset or a Watch Dog Timer reset the RTC Control register is reset to x0xxxxOOb After an RTC Alarm sleep mode recovery reset the RTC Control register is reset to xOxxxx10b 5 Read Only if Flash Memory is locked Read Write if Flash Memory is unlocked PS015308 0404 PRELIMINARY Register Map eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 3 Register Map Continued Address Reset CPU Page hex Mnemonic Name hex Access Watch Dog Timer 0093 WDT_CTL Watch Dog Timer Control Register 00 20 R W 76 0094 WDT_RR Watch Dog Timer Reset Register XX W if General Purpose Input Output Ports 009A PB_DR Port B Data Register XX R W 45 009B PB_DDR Port B Data Direction Register FF R W 46 009C PB ALT1 Port B Alternate Register 1 00 R W 46 009D PB_ALT2 Port B Alternate Register 2 00 R W 46 009E PC_DR Port C Data Register XX R W 45 009F PC_DDR Port C Data Direction Register FF R W 46 00A0 PC ALT1 Port C Alternate Register 1 00 R W 46 00A1 PC ALT2 Port C Alternate Reg
199. h PD ALT1 00A4h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RAV RW RW RW RAN RW RW RW Note R W Read Write Port x Alternate Register 2 In conjunction with the other GPIO Control Registers the Port x Alternate Register 2 detailed in Port x Alternate Registers 2 PB_ALT2 009Dh PC_ALT2 00A1h PD_ALT2 00A5h control the operating modes of the GPIO port pins See GPIO Mode Selection for more information Table 10 Port x Alternate Registers 2 PB ALT2 009Dh PC ALT2 00A1h PD ALT2 00A5h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RW RW RW RW RAN RW RW RW Note R W Read Write PS015308 0404 PRELIMINARY General Purpose Input Output eZ80F92 eZ80F93 Product Specification Lla ZiLOG Interrupt Controller The interrupt controller on the eZ80F92 device routes the interrupt request signals from the internal peripherals and external devices via the GPIO pins to the CPU Maskable Interrupts PS015308 0404 On the eZ80F92 device all maskable interrupts use the CPU s vectored interrupt function Interrupt Vector Sources by Priority lists the low byte vector for each of the maskable interrupt sources The maskable interrupt sources are listed in order of priority with vector 00h being the highest priority interrupt The full 16 bit interrupt vector is located at start ing address
200. he Chip Select Control Register Xin ADDR 23 0 DATA 7 0 output INSTRD I l I lt _ Terk lt _ Twait 1 Figure 61 Wait State Timing for Read Operations PS015308 0404 PRELIMINARY UT a Va Electrical Characteristics eZ80F92 eZ80F93 Product Specification 240 ZiLOG Wait State Timing for Write Operations Figure 62 illustrates the extension of the memory access signals using a single WAIT state for a Write operation This WAIT state is generated by setting CS_WAIT to 001h in the Chip Select Control Register l I l M Terk Twarr B l DATA 7 0 I output l I l I l we ANG A l l Figure 62 Wait State Timing for Write Operations PS015308 0404 PRELIMINARY Electrical Characteristics eZ80F92 eZ80F93 Product Specification zZ 241 ZiLOG General Purpose I O Port Input Sample Timing Figure 63 illustrates timing of the GPIO input sampling The input value on a GPIO port pin is sampled on the rising edge of the system clock The port value is then available to the CPU on the second rising clock edge following the change of the port value l l l System Clock Port Value Changes to 0 GPIO Pin Input Value l l l GPIO Input 0 Latched I l Data Latch Into GPIO Data Register l l GPIO Data Register GPIO Data I Value 0 Read READ on Data Bus I by eZ80 Figure 63 Port Input Sample Timing Table 153 GPIO Port Output Timing Del
201. he port is configured for level triggered interrupts the corresponding port pin is tristated An interrupt request is generated when the level at the pin is the same as the level stored in the Port x Data register The port pin value is sampled by the system clock The input pin must be held at the selected interrupt level for a minimum of 2 consecutive clock cycles to initiate an interrupt The interrupt request remains active as long as this condition is maintained at the external source For example if PD3 is programmed for low level interrupt and the pin is forced Low for 2 consecutive clock cycles an interrupt request signal is generated from that port pin and sent to the CPU The interrupt request signal remains active until the external device driv ing PD3 forces the pin High Edge Triggered Interrupts When the port is configured for edge triggered interrupts the corresponding port pin is tristated If the pin receives the correct edge from an external device the port pin generates an interrupt request signal to the CPU Any time a port pin is configured for edge triggered PS015308 0404 PRELIMINARY General Purpose Input Output eZ80F92 eZ80F93 Product Specification 45 ZiLOG interrupt writing a 1 to that pin s Port x Data register causes a reset of the edge detected interrupt The programmer must set the bit in the Port x Data register to 1 before entering either single or dual edge triggered interrupt mode for that port pin
202. hole number e g CEILING 3 01 is 4 Table 119 Flash Frequency Divider Register FLASH FDIVz00F9h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 1 CPU Access R W R W R W R W RIW R W R W RAW Note R W Read Write R Read Only Key sequence required to enable Writes Bit Position Value Description 7 0 O1h Divider value for generating the required 5 1 6 5us Flash FLASH FDIV FFh controller clock period PS015308 0404 PRELIMINARY Flash Memory PS015308 0404 Flash Write Erase Protection Register eZ80F92 eZ80F93 Product Specification ZiLOG The Flash Write Erase Protection register prevents accidental Write or Erase operations The protection is limited to a resolution of eight 16 KB blocks Setting a bit to 1 protects that 16KB block of Flash memory from accidental writing or erasure Default on RESET is for all Flash memory blocks to be protected Note A protect bit is not available for the Information Page Mass Erase is prevented if any of the bits in this register are set to 1 Writes to this register are allowed only after it is unlocked via the FLASH KEY register Any attempted Writes to this register while locked sets it to FFh thereby protecting all blocks Table 120 Flash Write Erase Protection Register FLASH_PROT 00FAh Bit 7 6 5 4 3 2 1 0 Reset 1 1 1 1 1 1 1 1 CPU Access R W RAW R AW R W R W RAW R IW
203. idle and the STP STA and IFLG bits of the I2C_CTL register to 0 I C Slave Address Register The I2C_SAR register provides the 7 bit address of the PC when in SLAVE mode and allows 10 bit addressing in conjunction with the I2C_XSAR register I2C_SAR 7 1 sla 6 0 is the 7 bit address of the PC when in 7 bit SLAVE mode When the C receives this address after a START condition it enters SLAVE mode I2C_SAR 7 corresponds to the first bit received from the IC bus When the register receives an address starting with F7h to FOh I2C SAR 7 3 11110b the PC recognizes that a 10 bit slave addressing mode is being selected The PC sends an ACK after receiving the I2C_SAR byte the device does not generate an interrupt at this point After the next byte of the address I2C XSAR is received the Pc generates an interrupt and goes into SLAVE mode Then I2C_SAR 2 1 are used as the upper 2 bits for PRELIMINARY I2C Serial I O Interface 154 eZ80F92 eZ80F93 Product Specification Zi ZiLOG the 10 bit extended address The full 10 bit address is supplied by I2C SAR 2 1 I2C_XSAR 7 0 See IC Slave Address Registers I2C SAR 00C8h Table 85 IC Slave Address Registers I2C SAR 00C8h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access R W RW RW RW RW RW RW RW Note R W Read Write Bit Position Value Description 7 1 00h 7 bit slave address or u
204. ignals MREQ CS3 0 INSTRD BUSACK IOREQ RD and WR are driven High Clock Peripheral Power Down Registers PS015308 0404 To reduce power the Clock Peripheral Power Down Registers allow the system clock to be disabled unused on chip peripherals Upon RESET all peripherals are enabled The clock to unused peripherals can be disabled by setting the appropriate bit in the Clock Peripheral Power Down Registers to 1 When powered down the peripherals are com pletely disabled To reenable the bit in the Clock Peripheral Power Down Registers must be cleared to 0 Many peripherals feature separate enable disable control bits that must be appropriately set for operation These peripheral specific enable disable bits do not provide the same level of power reduction as the Clock Peripheral Power Down Registers When powered down the standard peripheral control registers are not accessible for Read or Write access See Tables 4 and 5 PRELIMINARY Low Power Modes PS015308 0404 eZ80F92 eZ80F93 Product Specification VAF ZiLOG Table 4 Clock Peripheral Power Down Register 1 CLK PPD1 00DBh Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RW RW RAW R RW RW RW RW Note R W Read Write R Read Only Po iien Value Description 7 1 System clock to GPIO Port D is powered down GPIO D OFF Port D alternate functions do not operate c
205. igure 60 External I O Write Timing Table 152 External I O Write Timing Delay ns Parameter Abbreviation Min Max T4 Clock Rise to ADDR Valid Delay 13 T2 Clock Rise to ADDR Hold Time 2 0 T3 Clock Fall to Output DATA Valid Delay 11 T4 Clock Rise to DATA Hold Time 2 0 Ts Clock Rise to CSx Assertion Delay 2 0 19 0 Te Clock Rise to CSx Deassertion Delay 2 0 18 0 fs Clock Rise to IORQ Assertion Delay 2 0 16 0 Tg Clock Rise to IORQ Deassertion Delay 2 0 16 0 Note At the conclusion of a Write cycle deassertion of WR always occurs before any change to ADDR DATA CSx or IORQ PS015308 0404 PRELIMINARY Electrical Characteristics 238 Table 152 External I O Write Timing Continued eZ80F92 eZ80F93 Product Specification zZ 239 ZiLOG Delay ns Parameter Abbreviation Min Max To Clock Fall to WR Assertion Delay 1 8 6 5 T40 Clock Rise to WR Deassertion Delay 1 6 6 5 WR Deassertion to ADDR Hold Time 0 25 WR Deassertion to DATA Hold Time 0 25 WR Deassertion to CSx Hold Time 0 25 WR Deassertion to IORQ Hold Time 0 25 Note At the conclusion of a Write cycle deassertion of WR always occurs before any change to ADDR DATA CSx or IORQ Wait State Timing for Read Operations Figure 61 illustrates the extension of the memory access signals using a single WAIT state for a Read operation This WAIT state is generated by setting C8 WAIT to 001h in t
206. imer 34 Reset Operation 34 RESET Or NMI Generation 75 Reset States 51 Resetting the Pc Registers 154 RI see Ring Indicator RIO 15 130 RII 17 43 Ring Indicator 15 17 108 121 124 Trailing Edge on 125 Row Program Time out 206 RST FLAG bit 75 RTC see Real Time Clock PS015308 0404 eZ80F92 eZ80F93 Product Specification Z z ZiLOG RTC_UNLOCK 105 RTC_UNLOCK bit 91 92 104 RTC_Vpp 12 22 RTC Xqy 12 22 RTC_Xoyrt 12 22 RTS see Request To Send RTSO 13 RTS1 16 RxDO 13 RxD1 15 S Schmitt Trigger 11 Input 20 SCK see SPI Serial Clock SCL see C Serial Clock SCL line 145 147 SCLK see system clock SDA 20 23 142 143 144 146 153 serial bus SPI 141 Serial Clock 133 142 PC 20 SPI 18 133 serial data 133 142 PC 20 Serial Peripheral Interface 39 47 132 133 135 Baud Rate Generator 136 Baud Rate Generator Register 28 Baud Rate Generator Registers Low Byte and High Byte 137 Block 28 Control Register 28 139 Data Rate 136 Flags 135 140 141 Functional Description 135 interrupt service routine 47 master device 19 137 MASTER mode 135 mode 18 Receive Buffer Register 28 141 Registers 137 serial bus 141 Signals 133 PRELIMINARY Index slave device 19 SLAVE mode 135 Status Register 28 136 140 Transmit Shift Register 28 136 137 141 Setting Timer Duration 79 Shift Left Arithmetic 149 151 155 215 Op Code Map 217 221 222 Shift Right Arithmetic 215 Op Code Map 217 221 SINGLE
207. in Writing a 0 to the Port x Data register results in a high impedance output GPIO Mode 5 Reserved This pin produces high impedance output PS015308 0404 PRELIMINARY General Purpose Input Output PS015308 0404 eZ80F92 eZ80F93 Product Specification ZiLOG GPIO Mode 6 This bit enables a dual edge triggered interrupt mode Both a rising and a falling edge on the pin cause an interrupt request to be sent to the CPU Writing a 1 to the Port x Data register bit position resets the corresponding interrupt request Writing a 0 pro duces no effect The programmer must set the Port x Data register before entering the edge triggered interrupt mode GPIO Mode 7 For Ports B C and D the port pin is configured to pass control over to the alternate secondary functions assigned to the pin For example the alternate mode func tion for PC7 is RII and the alternate mode function for PB4 is the Timer 4 Out When GPIO Mode 7 is enabled the pin output data and pin tristated control come from the alter nate function s data output and tristate control respectively The value in the Port x Data register produces no effect on operation Note Input signals are sampled by the system clock before being passed to the alternate function input GPIO Mode 8 The port pin is configured for level sensitive interrupt modes An interrupt request is generated when the level at the pin is the same as the level stored in the Port x Data register The port pin
208. ip Select Wait State Generator block to generate Chip Selects 12 ADDR9 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects 13 ADDR10 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Continued Pin Symbol Function Signal Direction Description 14 ADDR11 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects 15 ADDR12 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives
209. ising Falling High Yes 1 0 Rising Falling Low No 1 1 Falling Rising High No PRELIMINARY Serial Peripheral Interface eZ80F92 eZ80F93 Product Specification ZiLOG SPI Functional Description When a master transmits to a slave device via the MOSI signal the slave device responds by sending data to the master via the master s MISO signal The resulting implication is a full duplex transmission with both data out and data in synchronized with the same clock signal Thus the byte transmitted is replaced by the byte received and eliminates the requirement for separate transmit empty and receive full status bits A single status bit SPIF is used to signify that the I O operation is completed see the SPI Status Register SPI_SR on page 140 The SPI is double buffered on Read but not on Write If a Write is performed during data transfer the transfer occurs uninterrupted and the Write is unsuccessful This condition causes the WRITE COLLISION WCOL status bit in the SPI_SR register to be set After a data byte is shifted the SPIF flag of the SPI_SR register is set In SPI MASTER mode the SCK pin functions as an output It idles High or Low depend ing on the CPOL bit in the SPI_CTL register until data is written to the shift register Data transfer is initiated by writing to the transmit shift register SPI_TSR Eight clocks are then generated to shift the eight bits of transmit data out the MOSI pin while shifting in eight bits of data on
210. ister 2 00 R W 46 00A2 PD_DR Port D Data Register XX R W 45 00A3 PD DDR Port D Data Direction Register FF R W 46 00A4 PD_ALT1 Port D Alternate Register 1 00 R W 46 00A5 PD_ALT2 Port D Alternate Register 2 00 R W 46 Chip Select Wait State Generator 00A8 CSO_LBR Chip Select O Lower Bound Register 00 R W 69 00A9 CS0 UBR Chip Select 0 Upper Bound Register FF R W 70 00AA CSO CTL Chip Select 0 Control Register E8 R W Z1 00AB CS1 LBR Chip Select 1 Lower Bound Register 00 R W 69 00AC CS1 UBR Chip Select 1 Upper Bound Register 00 R W 70 00AD CS1 CTL Chip Select 1 Control Register 00 R W ral Notes 1 After an external pin reset the Watch Dog Timer Control register is reset to 00h After a Watch Dog Timer time out reset the Watch Dog Timer Control register is reset to 20h 2 When the CPU reads this register the current sampled value of the port is read 3 Read Only if RTC registers are locked Read Write if RTC registers are unlocked 4 After an external pin reset or a Watch Dog Timer reset the RTC Control register is reset to xOxxxx00b After an RTC Alarm sleep mode recovery reset the RTC Control register is reset to xOxxxx10b 5 Read Only if Flash Memory is locked Read Write if Flash Memory is unlocked PS015308 0404 PRELIMINARY Register Map eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 3 Register Map Continued Address Reset CPU Page hex Mnemonic
211. isters The Instruction Store Register 0 is the first byte fetched fol lowed by Instruction Store registers 1 2 3 and 4 as necessary Only the bytes the proces sor requires to execute the instruction must be stored in these registers Some CPU instructions when combined with the MEMORY mode suffixes SIS SIL LIS or LIL require 6 bytes to operate These 6 byte instructions cannot be executed directly using the ZDI Instruction Store registers See Instruction Store 4 0 Registers gt Note The Instruction Store 0 register is located at a higher ZDI address than the other Instruction Store registers This feature allows the use of the ZDI auto address increment function to load and execute a multibyte instruction with a single data stream from the ZDI master Execution of the instruction commences with writing the most recent byte to ZDI_ISO Table 102 Instruction Store 4 0 Registers ZDI_IS4 21h ZDI_IS3 22h ZDI_IS2 23h ZDI_IS1 24h and ZDI_ISO 25h in the ZDI Register Write Only Address Space Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access W W W W W W W W Note X Undefined W Write Bit Position Value Description 7 0 00h These registers contain the Op Codes and operands for ZDI_IS4 FFh immediate execution by the CPU following a Write to ZDI_IS3 ZDI ISO The ZDI_ISO register contains the first Op Code ZDI IS2 of the instruction The remaining ZDI I
212. isters The ZDI control registers that reside in the ZDI register address space should not be confused with the eZ80F92 device peripheral registers that reside in the I O address space Many locations in the ZDI control register address space are shared by two registers one for Read Only access and one for Write Only access As an example a Read from ZDI register address 00h returns the eZ80 Product ID Low Byte while a Write to this same location 00h stores the Low byte of one of the address match values used for generating BREAK points The format for a ZDI address is seven bits of address followed by one bit for Read or Write control and completed by a single bit byte separator The ZDI executes a Read or Write operation depending on the state of the R W bit 0 Write 1 Read If no new START command is issued at completion of the Read or Write operation the operation PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification Ll er ZiLOG can be repeated Repeated Read or Write operations can occur without requiring a resend of the ZDI command To initiate a new ZDI command a START signal must follow Figure 40 illustrates the timing for address Writes to ZDI registers Single Bit Byte Separator or new ZDI START Signal l l 4 ZDlAddress Byte gt ZCL S Vl 1 3 3 4 5 6 7 eM f o9 l l ZDA msb Isb I START 0 WRITE Signal 1 READ Figure
213. it Position Value Description 7 0 A5h The first Write value required to reset the WDT prior to a time WDT_RR out 5Ah The second Write value required to reset the WDT prior to a time out If an A5h 5Ah sequence is written to WDT_RR the WDT timer is reset to its initial count value and counting resumes PRELIMINARY Watch Dog Timer eZ80F92 eZ80F93 Product Specification Z ZiLOG Programmable Reload Timers Programmable Reload Timers Overview The eZ80F92 device features six Programmable Reload Timers PRT Each PRT contains a 16 bit downcounter and a 16 bit reload register In addition each PRT features a clock prescaler with four selectable taps for CLK 4 CLK 16 CLK 64 and CLK 256 Each timer can be individually enabled to operate in either SINGLE PASS or CONTINU OUS mode The timer can be programmed to start stop restart from the current value or restart from the initial value and generate interrupts to the CPU Four of the Programmable Reload Timers timers 0 3 feature a selectable clock source input The input for these timers can be either the system clock or the Real Time Clock RTC source Timers 0 3 can also be used for event counting with their inputs received from a GPIO port pin Output from timers 4 and 5 can be directed to a GPIO port pin Each of the six PRTs available on the eZ80F92 device can be controlled individually They do not share the same counters reload registers control r
214. k eZ80F92 eZ80F93 Product Specification 91 ZiLOG Real Time Clock Alarm The clock can be programmed to generate an alarm condition when the current count matches the alarm set point registers Alarm registers are available for seconds minutes hours and day of the week Each alarm can be independently enabled To generate an alarm condition the current time must match all enabled alarm values For example if the day of the week and hour alarms are both enabled the alarm only occurs at the specified hour on the specified day The alarm triggers an interrupt if the interrupt enable bit INT_EN is set The alarm flag ALARM and corresponding interrupt to the CPU are cleared by reading the RTC_CTRL register Alarm value registers and alarm control registers can be written at any time Alarm condi tions are generated when the count value matches the alarm value The comparison of alarm and count values occurs whenever the RTC count increments one time every sec ond The RTC can also be forced to perform a comparison at any time by writing a 0 to the RTC_UNLOCK bit RTC_UNLOCK is not required to be changed to a 1 first Real Time Clock Oscillator and Source Selection The RTC count is driven by either the on chip 32768 Hz crystal oscillator or a 50 60 Hz power line frequency input connected to the 32 KHz RTC_Xoyr pin An internal divider compensates for each of these options The clock source and power line frequencies are selected i
215. l EF1 0 EF2 0 The Starting Program Counter is effectively MBASE PC 15 0 Push the 2 byte return address PC 15 0 onto the MBASE SPS stack The ADL mode bit remains cleared to 0 The interrupt vector address is located at MBASE I 7 0 IVECT 7 0 PC 15 0 MBASE I 7 0 IVECT 7 0 The ending Program Counter is effectively MBASE PC 15 0 The interrupt service routine must end with RETI ADL Mode 1 PS015308 0404 0 Read the LSB of the interrupt vector placed on the internal vectored interrupt bus IVECT 7 0 by the interrupting peripheral EF1 0 EF2 0 The Starting Program Counter is PC 23 0 Push the 3 byte return address PC 23 0 onto the SPL stack The ADL mode bit remains set to 1 The interrupt vector address is located at 00h I 7 0 IVECT 7 0 PC 15 0 00h I 7 0 IVECT 7 0 The ending Program Counter is 00h PC 15 0 The interrupt service routine must end with RETI PRELIMINARY Interrupt Controller 48 eZ80F92 eZ80F93 Product Specification Zi Table 12 Vectored Interrupt Operation Continued Memory ADL MADL Mode Bit Bit Operation Z80 Mode 0 1 Read the LSB of the interrupt vector placed on the internal vectored interrupt bus IVECT 7 0 bus by the interrupting peripheral EF1 0 EF2 0 The Starting Program Counter is effectively MBASE PC 15 0 Push the 2 byte return address PC 15 0 onto the
216. l clock cycles to complete their Read or Write operations The number of WAIT states for a particular Chip Select is controlled by the 3 bit field CSx WAIT CSx_CTL 7 5 The WAIT states can be independently programmed to pro vide 0 to 7 WAIT states for each Chip Select The WAIT states idle the CPU for the speci fied number of system clock cycles WAIT Input Signal Similar to the programmable WAIT states an external peripheral can drive the WAIT input pin to force the CPU to provide additional clock cycles to complete its Read or Write oper ation Driving the WAIT pin Low stalls the CPU The CPU resumes operation on the first rising edge of the internal system clock following deassertion of the WAIT pin UN Caution If the WAIT pin is to be driven by an external device the corresponding Chip Select for the device must be programmed to provide at least one WAIT state Due to input sampling of the WAIT input pin shown in Figure 7 one program mable WAIT state is required to allow the external peripheral sufficient time to assert the WAIT pin It is recommended that the corresponding Chip Select for the external device be programmed to provide the maximum number of WAIT states seven System Clock Figure 7 Wait Input Sampling Block Diagram PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification ZiLOG An example of WAIT state operation is illustrated in Figure 8 In this exam
217. l data This signal is multiplexed with PDO 69 PD1 GPIO Port D Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port D pin when programmed as output can be selected to be an open drain or open source output Port D is multiplexed with one UART RxDO Receive Data Input This pin is used by the UART to receive asynchronous serial data This signal is multiplexed with PD1 IR RxD IrDA Receive Data Input This pin is used by the IrDA encoder decoder to receive serial data This signal is multiplexed with PD1 70 PD2 GPIO Port D Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port D pin when programmed as output can be selected to be an open drain or open source output Port D is multiplexed with one UART RTSO Request To Send Output Active Low Modem control signal from UART This signal is multiplexed with PD2 PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Continued Pin Symbol Function Signal Direction Description 71 PD3 GPIO Port D Bidirectional This pin can be used for
218. lay ns Parameter Abbreviation Min Max Trck TCK Period 2 X TxiN T4 TDI TMS setup to TCK Rise 4 To TDI TMS hold after TCK Rise Fall 4 T3 TCK Rise to TDO change 10 PS015308 0404 PRELIMINARY Electrical Characteristics eZ80F92 eZ80F93 Product Specification VAR ZiLOG Packaging Figure 65 illustrates the 100 pin low profile quad flat package LQFP for the eZ80F92 device m ws sw e pe Dee e E98 7 e osoec ore DETALA LE 043 1 CONTROLLING DIMENSIONS MM 2 MAX COPLANARITY 10mm 004 0 10 DETAIL A Figure 65 100 Lead Plastic Low Profile Quad Flat Package LQFP PS015308 0404 PRELIMINARY Packaging eZ80F92 eZ80F93 Product Specification 245 ZiLOG Ordering Information Ordering Information provides a part name a product specification index code and a brief description of each part Table 157 Ordering Information Part Name PSI Description eZ80F92 eZ80F92AZ020SC 100 pin LQFP 128KB Flash memory 8KB SRAM 20 MHz Standard Temperature eZ80F92AZ020EC 100 pin LQFP 128KB Flash memory 8KB SRAM 20 MHz Extended Temperature eZ80F93 eZ80F93AZ020SC 100 pin LQFP 64KB Flash memory 4KB SRAM 20 MHz Standard Temperature eZ80F93AZ020EC 100 pin LQFP 64KB Flash memory 4KB SRAM 20 MHz Extended Temperature Navigate your browser to ZiLOG s website to order the eZ80F92 or the eZ80F93 Or con tact your lo
219. least one CPU system clock cycle prior to the beginning of State T3 additional wait states Twat are asserted until the READY pin is driven High STATE T4 The CPU deasserts the Write signal at the beginning of T4 identifying the end of the Write operation The CPU holds the data and address buses through the end of T4 The bus cycle is completed at the end of T4 PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification ZiLOG Signal timing for Intel bus mode with multiplexed address and data is illustrated for a Read operation in Figure 14 and for a Write operation in Figure 15 In the figures each Intel bus mode state is 2 CPU system clock cycles in duration Figures 14 and 15 also illustrate the assertion of one wait state Ty yr by the selected peripheral o mnm Oo m t3 Tw M wwe ILLE LLP LILLE LEL T T l l l I I I l I E I I I I CSx l I I I I l I I l I I I l l ALE l l l l l i i l I I l l l l l l l l I l l l l l l l l l READY l l l l l l l l l l Figure 14 Example Intel Bus Mode Read Timing Multiplexed Address and Data Bus PS015308 0404 PRELIMINARY Chip Selects and Wait States 63 eZ80F92 eZ80F93 Product Specification Z ZiLOG IOM l 2 T Taat 7 so TT TY TELE LE LILLY LU LE I I l l I l l l l l ANE I I l l l l iam l l l l l l l l MREQ or IORQ l l Figure 15 Example Intel Bus Mode Write Timing
220. ls port I O 1 0 1 1 Port B C or D alternate function controls port I O 8 1 1 0 0 Interrupt active Low High impedance 1 1 0 1 Interrupt active High High impedance 9 1 1 1 0 Interrupt falling edge triggered High impedance 1 1 1 1 Interrupt Trising edge triggered High impedance GPIO Mode 1 The port pin is configured as a standard digital output pin The value writ ten to the Port x Data register Px DR is presented on the pin GPIO Mode 2 The port pin is configured as a standard digital input pin The output is tristated high impedance The value stored in the Port x Data register produces no effect As in all modes a Read from the Port x Data register returns the pin s value GPIO Mode 2 is the default operating mode following a RESET GPIO Mode 3 The port pin is configured as open drain I O The GPIO pins do not feature an internal pull up to the supply voltage To employ the GPIO pin in OPEN DRAIN mode an external pull up resistor must connect the pin to the supply voltage Writing a 0 to the Port x Data register outputs a Low at the pin Writing a 1 to the Port x Data register results in high impedance output GPIO Mode 4 The port pin is configured as open source I O The GPIO pins do not fea ture an internal pull down to the supply ground To employ the GPIO pin in OPEN SOURCE mode an external pull down resistor must connect the pin to the supply ground Writing a 1 to the Port x Data register outputs a High at the p
221. ly programmable For Intel bus mode multiplexed address and data can be selected in which the lower byte of the address and the data byte both use the data bus DATA 7 0 Each of the bus modes is explained in more detail in the following sections eZ80 Bus Mode Chip selects configured for eZ80 bus mode do not modify the bus signals from the CPU The timing diagrams for external Memory and I O Read and Write operations are shown in the AC Characteristics section on page 233 The default mode for each chip select is eZ80 mode Z80 Bus Mode Chip selects configured for Z80 mode modify the CPU bus signals to match the Z80 microprocessor address and data bus interface signal format and timing During read oper ations the Z80 bus mode employs three states T1 T2 and T3 as described in Z80 Bus Mode Read States Table 14 Z80 Bus Mode Read States STATE T1 The Read cycle begins in State T1 The CPU drives the address onto the address bus and the associated Chip Select signal is asserted STATE T2 During State T2 the RD signal is asserted Depending upon the instruction either the MREQ or IORQ signal is asserted If the external WAIT pin is driven Low at least one CPU system clock cycle prior to the end of State T2 additional WAIT states Twat are asserted until the WAIT pin is driven High STATE T3 During State T3 no bus signals are altered The data is latched by the eZ80F92 device at the rising edge of the CPU system clock at th
222. mechanism can function as a handshake enabling receivers to cope with fast data transfers on either a byte or bit level The byte level allows a device to receive a byte of data at a fast rate but allows the device more time to store the received byte or to prepare another byte for transmission Slaves hold the SCL line Low after recep tion and acknowledge the byte forcing the master into a wait state until the slave is ready for the next byte transfer in a handshake procedure Operating Modes PS015308 0404 Master Transmit In MASTER TRANSMIT mode the I7C transmits a number of bytes to a slave receiver Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL register to 1 The I C then tests the I C bus and transmits a START condition when the bus is free When a START condition is transmitted the IFLG bit is 1 and the status code in the I2C_SR register is 08h Before this interrupt is serviced the I2C_DR register must be loaded with either a 7 bit slave address or the first part of a 10 bit slave address with the Isb cleared to 0 to specify TRANSMIT mode The IFLG bit should now be cleared to 0 to prompt the transfer to continue After the 7 bit slave address or the first part of a 10 bit address plus the Write bit are transmitted the IFLG is set again A number of status codes are possible in the I2C SR register See C Master Transmit Status Codes PRELIMINARY I2C Serial I O Interface eZ80F92 eZ80F93 Product Speci
223. ming 0 0 lesse 235 External Write Timing 0 0 0 cece eee eee eee 236 External I O Read Timing 237 External I O Write Timing 0 0 0 cece eee ee eee 238 GPIO Port Output Timing 0 0 0 d anene ee ea 241 Bus Acknowledge Timing 0 0 0c cece ee eee 242 PHI System Clock Timing 0 0 0 cece eee eee 242 ZDI Timing Specifications 243 PRELIMINARY List of Tables xii eZ80F92 eZ80F93 Product Specification ZiLOG Architectural Overview The eZ80F92 device is a high speed single cycle instruction fetch microcontroller with a maximum clock speed of 20MHz It is the first member of ZiLOG s new eZ80Acclaim product family which offers on chip Flash program memory The eZ80F92 device can operate in Z80 compatible addressing mode 64 KB or full 24 bit addressing mode 16MB The rich peripheral set of the eZ80F92 device makes it suitable for a variety of applications including industrial control embedded communication and point of sale ter minals Note Additionally ZiLOG offers the eZ80F93 device which features scaled down mem ory options For purposes of clarity this document refers to both devices collec tively as the eZ80F92 device unless otherwise specified Features PS015308 0404 Single cycle instruction fetch high performance pipelined eZ809 CPU core eZ80F92 contains 128KB Flash memory and 8KB SRAM eZ80F93 contains 64KB Flash memory and 4KB SRAM Low power feat
224. monitors BUSACKs during ZDI DEBUG mode See ZDI Bus Control Register ZDI_BUS_STAT 17h in the ZDI Register Read Only Address Space Table 109 ZDI Bus Control Register ZDI BUS STAT 17h in the ZDI Register Read Only Address Space Bit Reset 0 0 0 0 0 0 0 0 CPU Access Note R Read Only Bit Position Value Description 7 0 Bus requests by external peripherals using the ZDI BUSACK EN BUSREQ pin are ignored The bus acknowledge signal BUSACK is not asserted 1 Bus requests by external peripherals using the BUSREQ pin are accepted A bus acknowledge occurs at the end of the current ZDI operation The bus acknowledge is indicated by asserting the BUSACK pin 6 0 Address and data buses are not relinquished to an ZDI BUS STAT external peripheral bus acknowledge is deasserted BUSACK pin is High 1 Address and data buses are relinquished to an external peripheral bus acknowledge is asserted BUSACK pin is Low 5 0 000000 Reserved ZDI Read Memory Register When a Read is executed from the ZDI Read Memory register the eZ80F92 device fetches the data from the memory address currently pointed to by the program counter PC the program counter is then incremented In Z80 MEMORY mode the memory address is MBASE PC 15 0 In ADL MEMORY mode the memory address is PC 23 0 Refer to the eZ80 CPU User Manual UM0077 for more information regarding Z80 and ADL MEMO
225. month count MON OCh PRELIMINARY Real Time Clock PS015308 0404 eZ80F92 eZ80F93 Product Specification Z ZiLOG Real Time Clock Year Register This register contains the current year count See Real Time Clock Year Register RTC_YR 00E6h Table 45 Real Time Clock Year Register RTC_YR 00E6h Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access R W RAW R IW R W R W RAW R W R W Note X Unchanged by RESET R W Read Only if RTC locked Read Write if RTC unlocked Binary Coded Decimal Operation BCD EN 1 Bit Position Value Description 7 4 0 9 The tens digit of the current year count TENS_YR 3 0 0 9 The ones digit of the current year count YR Binary Operation BCD_EN 0 Bit Position Value Description 7 0 00h The current year count YR 63h PRELIMINARY Real Time Clock PS015308 0404 eZ80F92 eZ80F93 Product Specification Z ZiLOG Real Time Clock Century Register This register contains the current century count See Real Time Clock Century Register RTC CEN 00E7h Table 46 Real Time Clock Century Register RTC CEN 00E7h Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access R W RAW R IW R W R W RAW R W R W Note X Unchanged by RESET R W Read Only if RTC locked Read Write if RTC unlocked Binary Coded De
226. n the RTC_CTRL register Writing to the RTC_CTRL register resets the clock divider Real Time Clock Battery Backup The power supply pin RTC_Vpp for the Real Time Clock and associated low power 32 KHz oscillator is isolated from the other power supply pins on the eZ80F92 device To ensure that the RTC continues to keep time in the event of loss of line power to the appli cation a battery can be used to supply power to the RTC and the oscillator via the RTC_Vpp pin All Vgg ground pins should be connected together on the printed circuit assembly Real Time Clock Recommended Operation Following a RESET from a powered down condition the counter values of the RTC are undefined and all alarms are disabled After a RESET from a powered down condition the following procedure is recommended Write to RTC_CTRL to set RTC_UNLOCK and CLK_SEL Write values to the RTC count registers to set the current time Write values to the RTC alarm registers to set the appropriate alarm conditions PS015308 0404 PRELIMINARY Real Time Clock eZ80F92 eZ80F93 Product Specification ZiLOG Write to RTC_CTRL to clear the RTC UNLOCK bit clearing the RTC_UNLOCK bit resets and enables the clock divider Real Time Clock Registers The Real Time Clock registers are accessed via the address and data bus using I O instruc tions RTC_UNLOCK controls access to the RTC count registers When unlocked RTC_UNLOCK 1 the RTC count is disabled and the count
227. n the input clock period and is generated by setting the clock divider ratio to 1 4 and the reload value to 0001h Maximum time out duration is 27 16 777 216 times longer than the input clock period and is generated by setting the clock divider ratio to 1 256 and the reload value to 0000h Single Pass Mode In SINGLE PASS mode when the end of count value 0000h is reached counting halts the timer is disabled and the PRT_EN bit resets to 0 To restart the timer the CPU must reenable the timer by setting the PRT_EN bit to 1 An example of a PRT operating in SIN GLE PASS mode is illustrated in Figure 21 Timer register information is indicated in PRT Single Pass Mode Operation Example PRELIMINARY Programmable Reload Timers eZ80F92 eZ80F93 Product Specification Zi CLKEN IOWRN tenth 7 0 0 mo o Ce 935 A4 2A 0 IRQ Figure 21 PRT SINGLE PASS Mode Operation Example Table 29 PRT SINGLE PASS Mode Operation Example Parameter Control Register s Value PRT Enabled TMRx_CTL 0 1 Reload and Restart Enabled TMRx CTL 1 1 PRT Clock Divider 4 TMRx CTL 3 2 00b SINGLE PASS Mode TMRx CTL 4 0 PRT Interrupt Enabled TMRx CTL 6 1 PRT Reload Value TMRx RR H TMRx RR L 0004h Continuous Mode In CONTINUOUS mode when the end of count value 0000h 1s reached the timer auto matically reloads the 16 bit start value from the Timer Reload registers TMRx RR H and TMRx R
228. nce Parallel Mode Fundamental Series Resistance Rs 40 KO Maximum Load Capacitance C 12 5 pF Maximum Shunt Capacitance Cg 3 pF Maximum Drive Level 1 uQ Maximum PRELIMINARY On Chip Oscillators Electrical Characteristics Absolute Maximum Ratings eZ80F92 eZ80F93 Product Specification Zi ZiLOG Stresses greater than those listed in Absolute Maximum Ratings may cause permanent damage to the device These ratings are stress ratings only Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability For improved reliability unused inputs should be tied to one of the sup ply voltages Vpp or Vss Table 145 Absolute Maximum Ratings Parameter Min Max Units Notes Ambient temperature under bias C 40 105 C 1 Storage temperature C 65 150 C Voltage on any pin with respect to Vas 0 3 5 5 V 2 Voltage on Vpp pin with respect to Vss 0 3 3 6 V Total power dissipation 520 mW Maximum current out of Vss 145 mA Maximum current into Vpp 145 mA Maximum current on input and or inactive output pin 25 25 pA Maximum output current from active output pin 8 8 mA Notes 1 Operating temperature is specified in DC Characteristics 2 This voltage applies to all pins except where noted otherwise DC Chara
229. ncy of the PC clock line SCL when the IC is in MASTER mode The Write Only I2C_CCR registers share the same I O addresses as the Read Only I2C SR registers See PC Clock Control Registers I2C CCR 00CCh Table 91 C Clock Control Registers I2C CCR 00CCh Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access W W W W W W W Note W Read only Eam Value Description 7 0 Reserved 6 3 0000 1I C clock divider scalar value M 1111 En em IC clock divider exponent The I7C clocks are derived from the CPU system clock The frequency of the CPU system clock is fscy The PC bus is sampled by the PC block at the frequency fs app supplied by f _ fscik SAMP 5N In MASTER mode the I C clock output frequency on SCL fsc is supplied by T fscLk SCL 10 M 1 2N The use of two separately programmable dividers allows the MASTER mode output fre quency to be set independently of the frequency at which the PC bus is sampled This fea ture is particularly useful in multimaster systems because the frequency at which the PC bus is sampled must be at least 10 times the frequency of the fastest master on the bus to ensure that START and STOP conditions are always detected By using two programma ble clock divider stages a high sampling frequency can be ensured while allowing the MASTER mode output to be set to a lower frequency PRELIMINARY I2C Serial I O Interface
230. ndependent of the particular bus mode employed eZ80 Z80 Intel or Motorola l l e Terk l l P T M d pa l l Ts e T4 DATA 7 0 input i i T p Ts gt I IORQ I l l Figure 59 External I O Read Timing Table 151 External I O Read Timing Delay ns Parameter Abbreviation Min Max T4 Clock Rise to ADDR Valid Delay 13 To Clock Rise to ADDR Hold Time 2 0 T3 Input DATA Valid to Clock Rise Setup Time 1 0 T4 Clock Rise to DATA Hold Time 2 0 Ts Clock Rise to CSx Assertion Delay 2 0 19 0 Te Clock Rise to CSx Deassertion Delay 2 0 18 0 T Clock Rise to IORQ Assertion Delay 2 0 16 0 Ts Clock Rise to IORQ Deassertion Delay 2 0 16 0 To Clock Rise to RD Assertion Delay 2 0 16 0 T40 Clock Rise to RD Deassertion Delay 2 0 16 0 PS015308 0404 PRELIMINARY Electrical Characteristics eZ80F92 eZ80F93 Product Specification ZiLOG External I O Write Timing Figure 60 and External I O Write Timing diagram the timing for external I O writes Clock rise fall to signal transition timing is independent of the particular bus mode employed eZ80 Z80 Intel or Motorola I I I l Xin l l l l T l T K I ADDR 23 0 l l I I I I 9 13 lt mel Ty lt DATA 7 0 I output l 1 l T L T ELE Te l 1 l 1 rt T l a Tg I l T I IORQ l l l I l l Tio lt F
231. nsmitter PS015308 0404 eZ80F92 eZ80F93 Product Specification 116 ZiLOG UART Interrupt Identification Register The Read Only UARTx_IIR register allows the user to check whether the FIFO is enabled and the status of interrupts These registers share the same I O addresses as the UARTXx FCTL registers See Tables 58 and 59 Table 58 UART Interrupt Identification Registers UARTO IIR 00C2h UART1 IIR 00D2h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 1 CPU Access R R Note R Read only Bit Position Value Description 7 6 00 FIFO is disabled Fors 10 Receive FIFO is disabled MULTIDROP mode 11 FIFO is enabled 5 4 00 Reserved 3 1 000 Interrupt Status Code INSTS 110 The code indicated in these three bits is valid only if INTBIT is 1 If two internal interrupt sources are active and their respective enable bits are High only the higher priority interrupt is seen by the application The lower priority interrupt code is indicated only after the higher priority interrupt is serviced UART Interrupt Status Codes lists the interrupt status codes 0 0 There is an active interrupt source within the UART INTBIT There is not an active interrupt source within the UART Table 59 UART Interrupt Status Codes INSTS Value Priority Interrupt Type 011 Highest Receiver Line Status 010 Second Receiver Data Ready or Trigger Level
232. nts and trace history features The OCI employs all of the functions of the ZiLOG Debug Interface ZDI as described in the ZDI section It also adds the following debug features Control via a 4 pin JTAG port that conforms to IEEE Standard 1149 1 Test Access Port and Boundary Scan Architecture Complex break point trigger functions Break point enhancements such as the ability to Define two break point addresses that form a range Break on masked data values Start or stop trace Assert a trigger output signal Trace history buffer Software break point instruction There are four sections to the OCI JTAG interface ZDI debug control Trace buffer memory Complex triggers OCI Activation OCI features clock initialization circuitry so that external debug hardware can be detected during power up The external debugger must drive the OCI clock pin TCK Low at least two system clock cycles prior to the end of the RESET to activate the OCI block If TCK is High at the end of the RESET the OCI block shuts down so that it does not draw power in normal product operation When the OCI is shut down ZDI is enabled directly and can PS015308 0404 1 On Chip Instrumentation and OCI are trademarks of First Silicon Solutions Inc 2 The eZ80F92 does not contain the boundary scan register required for 1149 1 compliance PRELIMINARY On Chip Instrumentation eZ80F92 eZ80F93 Product Specification ZiLOG be a
233. o the CPU The default operation is for the WDT to cause a RESET It asserts deasserts on the rising edge of the clock The RST_FLAG bit can be polled by the CPU to determine the source of the RESET event PRELIMINARY Watch Dog Timer 75 eZ80F92 eZ80F93 Product Specification Z ZiLOG If the NMI_OUT bit in the WDT_CTL register is set to 1 then upon time out the WDT asserts an NMI for CPU processing The NMI_FLAG bit can be polled by the CPU to determine the source of the NMI event Watch Dog Timer Registers PS015308 0404 Watch Dog Timer Control Register The Watch Dog Timer Control register detailed in Watch Dog Timer Control Register is an 8 bit Read Write register used to enable the Watch Dog Timer set the time out period indicate the source of the most recent RESET and select the required operation upon WDT time out Table 27 Watch Dog Timer Control Register WDT_CTL 0093h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 1 0 0 0 0 0 CPU Access R W RW R R W RW R R W RW Note R Read only R W Read Write Bit Position Value Description 7 0 WDT is disabled WDT EN 1 WDT is enabled When enabled the WDT cannot be disabled without a RESET 6 0 WDT time out resets the CPU NMI OUT 7 1 WDT time out generates a nonmaskable interrupt NMI to the CPU 5 0 RESET caused by external full chip reset or ZDI reset RST_FLAG 1
234. ock eZ80F92 eZ80F93 Product Specification zZ 106 ZiLOG Universal Asynchronous Receiver Transmitter PS015308 0404 The UART module implements all of the logic required to support several asynchronous communications protocols The module also implements two separate 16 byte deep FIFOs for both transmission and reception A block diagram of the UART is illustrated in Figure 24 to eZ80 CPU System Clock Receive Buffer RxDO RxD1 I O Address Data TxDO TxD1 Interrupt Signal CTSO CTS1 RTSO RTS1 DSRO DSR1 DTRO DTR1 DCDO DCD1 RIO RI re o 2 o c o o o g aa o 2 a o c o T o L E o E c 9 Oo ke c lt x 2 Figure 24 UART Block Diagram The UART module provides the following asynchronous communication protocol related features and functions 5 6 7 8 or 9 bit data transmission Even odd space mark or no parity bit generation and detection Start and stop bit generation and detection supports up to two stop bits Line break detection and generation Receiver overrun and framing errors detection Logic and associated I O to provide modem handshake capability PRELIMINARY Universal Asynchronous Receiver Transmitter eZ80F92 eZ80F93 Product Specification Z ZiLOG UART Functional Description The UART function implements The transmitter and associated control logic The receiver and associated control logic The modem interf
235. of the current ZDI operation indicated by a High during the single bit byte separator The default reset condition is for bus acknowl edgement to be disabled To allow bus acknowledgement the ZDI BUSACK EN must be written When an external bus request BUSREQ pin asserted is detected ZDI waits until comple tion of the current operation before responding ZDI acknowledges the bus request by asserting the bus acknowledge BUSACK signal If the ZDI block is not currently shift ing data it acknowledges the bus request immediately ZDI uses the single bit byte separa tor of each data word to determine if it is at the end of a ZDI operation If the bit is a logical 0 ZDI does not assert BUSACK to allow additional data Read or Write operations If the bit is a logical 1 indicating completion of the ZDI commands BUSACK is asserted Potential Hazards of Enabling Bus Requests During DEBUG Mode There are some potential hazards that the user must be aware of when enabling external bus requests during ZDI DEBUG mode First when the address and data bus are being used by an external source ZDI must only access ZDI registers and internal CPU registers to prevent possible Bus contention The bus acknowledge status is reported in the ZDI BUS STAT register The BUSACK output pin also indicates the bus acknowledge state A second hazard is that when a bus acknowledge is granted the ZDI is subject to any WAIT states that are assigned to the device cu
236. olute Maximum Ratings 226 AC Characteristics 233 ACK see Acknowledge Acknowledge 144 148 152 154 159 160 address bus 5 9 48 52 54 59 62 65 66 69 70 92 170 181 187 24 bit 25 Addressing 154 ADL Memory mode 183 187 alarm condition 91 104 105 alarm flag 104 Arbitration 146 Architectural Overview 1 asynchronous serial data 13 15 B Baud Rate Generator 111 Functional Description 136 BCD see binary coded decimal operation binary coded decimal operation 90 92 105 bit generation 106 Block Diagram 2 Boundary Scan Architecture 190 break detection 106 115 break point trigger functions 190 BRG Control Registers 112 Bus Acknowledge 11 22 54 170 181 187 242 pin 54 181 PS015308 0404 PRELIMINARY eZ80F92 eZ80F93 Product Specification Ziz ZiLOG Bus Arbitration Overview 142 Bus Enable bit 156 158 Bus Mode Controller 55 bus mode state 55 56 59 63 67 73 bus modes 55 68 71 Bus Request 11 22 54 170 181 187 During ZDI Debug Mode 170 BUSACK see Bus Acknowledge BUSREQ see Bus Request Byte Format 144 C Change Log 247 Characteristics Electrical Absolute Maximum Ratings 226 Chip Select 0 9 Chip Select 1 9 Chip Select 2 9 Chip Select 3 9 Chip Select Registers 69 Chip Select x Bus Mode Control Register 71 Chip Select x Control Register 70 Chip Select x Lower Bound Register 69 Chip Select x Upper Bound Register 70 Chip Select Wait State Generator block 5 6 7 8 9 Chi
237. or value resets to 0002h A minimum BRG divisor value of 0001h is also valid and effectively bypasses the BRG A software Write to either the Low or High byte registers for the BRG Divisor Latch causes both the Low and High bytes to load into the BRG counter and causes the count to restart The divisor registers can only be accessed if bit 7 of the UART Line Control register UARTx_LCTL is set to 1 After reset this bit is reset to 0 Recommended Usage of the Baud Rate Generator The following is the normal sequence of operations that should occur after the eZ80F92 device is powered on to configure the Baud Rate Generator Assert and deassert RESET Set UARTx_LCTL 7 to 1 to enable access of the BRG divisor registers PS015308 0404 PRELIMINARY Universal Asynchronous Receiver Transmitter eZ80F92 eZ80F93 Product Specification zZ 112 ZiLOG Program the UARTx_BRG_L and UARTx_BRG_H registers Clear UARTx_LCTL 7 to 0 to disable access of the BRG divisor registers BRG Control Registers PS015308 0404 UART Baud Rate Generator Register Low and High Bytes The registers hold the Low and High bytes of the 16 bit divisor count loaded by the pro cessor for UART baud rate generation The 16 bit clock divisor value is returned by UARTx_BRG_H UARTx_BRG_L where x is either 0 or 1 to identify the two available UART devices Upon RESET the 16 bit BRG divisor value resets to 0002h The initial 16 bit divisor value must be between 0
238. orrectly 0 System clock to GPIO Port D is powered up 6 1 System clock to GPIO Port C is powered down GPIO_C_OFF Port C alternate functions do not operate correctly 0 System clock to GPIO Port C is powered up 5 1 System clock to GPIO Port B is powered down GPIO B OFF Port B alternate functions do not operate correctly 0 System clock to GPIO Port B is powered up 4 Reserved 3 1 System clock to SPI is powered down SIDES 0 System clock to SPI is powered up 2 1 System clock to PC is powered down IC COEF 0 System clock to PC is powered up 1 1 System clock to UART1 is powered down SART OR 0 System clock to UART1 is powered up 0 1 System clock to UARTO and IrDA endec is powered down VAISTOCOIHE 0 System clock to UARTO and IrDA endec is powered up PRELIMINARY Low Power Modes eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 5 Clock Peripheral Power Down Register 2 CLK_PPD2 00DCh Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access R W R RAV RW RW RW RW RAW Note R W Read Write R Read Only Bit Position Value Description 7 PHI OFF PHI Clock output is disabled output is high impedance PHI Clock output is enabled 6 Reserved 5 PRT5 OFF System clock to PRT5 is powered down System clock to PRT5 is powered up 4 PRT4 OFF System clock to PRT4 is powered down System clock to PRT4 is powered up
239. ory Arrangement in the eZ80F92 The eZ80F92 device features 128 KB 131 072 bytes of nonvolative Flash memory with Read Write Erase capability The main Flash memory array is arranged in 128 pages with 8 rows per page and 128 bytes per row In addition to main Flash memory there are two separately addressable rows which comprise a 256 byte Information Page The 128 KB of main storage can be protected in eight 16KB blocks Protecting a 16KB block prevents Write or Erase operations The Flash memory arrangement is illustrated in Figure 47 16 8 8 2 KB pages 256 byte rows 32 KB blocks per block per page 256 single byte columns per row slam ie Figure 47 eZ80F92 Flash Memory Arrangement PS015308 0404 PRELIMINARY Flash Memory eZ80F92 eZ80F93 Product Specification Ll or ZiLOG Flash Memory Arrangement in the eZ80F93 The eZ80F92 features 64KB 65 536 bytes of nonvolative Flash memory with Read Write Erase capability The main Flash memory array is arranged in 64 pages with 8 rows per page and 128 bytes per row In addition to the main Flash memory there are two sepa rately addressable rows which comprise a 256 byte Information Page The 64 KB of main storage can be protected in four 16 KB blocks Protecting a 16KB block prevents Write or Erase operations The Flash memory arrangement is illustrated in Figure 48 16 8 1 KB pages 128 byte rows per block per page single byte columns per row s Figure 48 eZ
240. oscillator Isolated from Supply the power supply to the remainder of the chip A battery can be connected to this pin to supply constant power to the Real Time Clock and 32KHz oscillator 61 Vss Ground Ground 62 TMS JTAG Test Input JTAG Mode Select Input Mode Select 63 TCK JTAG Test Input JTAG and ZDI clock input Clock 64 TRIGOUT JTAG Test Output Active High trigger event indicator Trigger Output 65 TDI JTAG Test Bidirectional JTAG data input pin Functions as ZDI data Data In I O pin when JTAG is disabled 66 TDO JTAG Test Output JTAG data output pin Data Out 67 VDD Power Supply Power Supply PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification 13 ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Continued Pin Symbol Function Signal Direction Description 68 PDO GPIO Port D Bidirectional This pin can be used for general purpose O It can be individually programmed as input or output and can also be used individually as an interrupt input Each Port D pin when programmed as output can be selected to be an open drain or open source output Port D is multiplexed with one UART TxDO UART Transmit Data Output This pin is used by the UART to transmit asynchronous serial data This signal is multiplexed with PDO IR_TxD IrDA Transmit Data Output This pin is used by the IrDA encoder decoder to transmit seria
241. ow period of the PC bus clock line is stretched and the data transfer is suspended When a 0 is written to IFLG the interrupt is cleared and the IC clock line is released When the IPC Acknowledge bit AAK is set to 1 an Acknowledge is sent during the acknowledge clock pulse on the PC bus if Either the whole of a 7 bit slave address or the first or second byte of a 10 bit slave address is received The general call address is received and the General Call Enable bit in I2C_SAR is set to 1 A data byte is received while in MASTER or SLAVE modes When AAK is cleared to 0 a NACK is sent when a data byte is received in MASTER or SLAVE mode If AAK is cleared to 0 in the Slave Transmitter mode the byte in the I2C DR register is assumed to be the final byte After this byte is transmitted the Pc block enter states C8h then returns to the idle state The I7C module does not respond to its slave address unless AAK is set See I2C Control Registers I2C_CTL 00CBh PS015308 0404 PRELIMINARY I2C Serial I O Interface PS015308 0404 Table 88 I2C Control Registers I2C_CTL 00CBh eZ80F92 eZ80F93 Product Specification Zi ZiLOG Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RAV RW RW RW RW RW R Note R W Read Write R Read Only podion Value Description 7 0 Fe interrupt is disabled IEN 1 C interrupt is enabled 6
242. p Selects and Wait States 50 Chip Selects During Bus Request Bus Acknowl edge Cycles 54 Clear To Send 14 16 122 124 Delta Status Change of 125 clock divisor value 16 bit 112 137 clock initialization circuitry 190 Clock Peripheral Power Down Registers 38 Clock Phase 133 135 139 Clock Polarity 134 135 139 Clock Synchronization 145 Clocking Overview 142 Complex triggers 190 CONTINUOUS mode 78 80 83 85 87 88 Index CPHA see Clock Phase CPOL see Clock Polarity CPU system clock cycle 56 CSO 9 21 50 53 CS1 9 21 50 53 CS2 9 21 50 52 53 CS3 9 21 50 52 53 CTS see Clear To Send CTSO 14 130 CTS1 16 Customer Feedback Form 258 cycle termination signal 66 D data bus 9 54 55 57 59 62 66 72 92 170 181 187 Data Carrier Detect 14 17 121 124 Delta Status Change of 125 Data Set Ready 14 16 122 124 Delta Status Change of 125 Data Terminal Ready 14 16 122 124 Data Transfer Procedure with SPI configured as a Slave 137 Data Transfer Procedure with SPI Configured as the Master 136 data transfer SPI 140 Data Validity 143 DC Characteristics 226 DCD see Data Carrier Detect DCDO 14 130 DCDI 17 DCTS see Clear To Send Delta Status Change of DDCD see Data Carrier Detect Delta Status Change of DDSR see Data Set Ready Delta Status Change of divisor count 112 137 Document Information 247 Document Number Description 247 DSR see Data Set Ready DSRO 14 130 D
243. ple the Chip Select is configured to provide a single WAIT state The external peripheral being accessed drives the WAIT pin Low to request assertion of an additional WAIT state If the WAIT pin is asserted for additional system clock cycles WAIT states are added until the WAIT pin is deasserted High l l l lt Terk Twatt M DOC DO i DATA 7 0 output INSTRD l Figure 8 Example Wait State Operation Read Operation Chip Selects During Bus Request Bus Acknowledge Cycles When the CPU relinquishes the address bus to an external peripheral in response to an external bus request BUSREQ it drives the bus acknowledge pin BUSACK Low The external peripheral can then drive the address bus and data bus The CPU continues to generate Chip Select signals in response to the address on the bus External devices cannot access the internal registers of the eZ80F92 device PS015308 0404 PRELIMINARY Chip Selects and Wait States 54 eZ80F92 eZ80F93 Product Specification ZiLOG Bus Mode Controller The bus mode controller allows the address and data bus timing and signal formats of the eZ80F92 device to be configured to connect seamlessly with external eZ809 Z80 Intel or Motorola compatible devices Bus modes for each of the chip selects can be configured independently using the Chip Select Bus Mode Control Registers The number of CPU system clock cycles per bus mode state is also independent
244. pper 2 bits I2C_SAR 2 1 of address SLA 7Fh when operating in 10 bit mode 0 0 IC not enabled to recognize the General Call Address GCE C enabled to recognize the General Call Address IC Extended Slave Address Register The I2C XSAR register is used in conjunction with the I2C SAR register to provide 10 bit addressing of the PC when in SLAVE mode The I2C SAR value forms the lower 8 bits of the 10 bit slave address The full 10 bit address is supplied by I2C SAR 2 1 DC XSAR 7 0 When the register receives an address starting with F7h to FOh I2C SAR 7 3 11110b the C recognizes that a 10 bit slave addressing mode is being selected The IC sends an ACK after receiving the I2C XSAR byte the device does not generate an interrupt at this point After the next byte of the address I2C XSAR is received the PC generates an interrupt and goes into SLAVE mode Then I2C_SAR 2 1 are used as the upper 2 bits for the 10 bit extended address The full 10 bit address is supplied by I2C SAR 2 1 I2C_XSAR 7 0 See I C Extended Slave Address Registers I2C XSAR 00C9h PS015308 0404 PRELIMINARY I2C Serial I O Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification VAR ZiLOG Table 86 I C Extended Slave Address Registers I2C XSAR 00C9h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access RAV RW RW RW RW RW RW RW Note R W Read Write
245. ps when driven Low 2 RTC current increases when the eZ80F92 device is not in SLEEP mode as the RTC_VDD pin supplies power to system clock buffers within the Real Time Clock circuit PS015308 0404 PRELIMINARY Electrical Characteristics eZ80F92 eZ80F93 Product Specification 228 ZiLOG POR and VBO Electrical Characteristics DC Characteristics lists the Power On Reset and Voltage Brown Out characteristics of the eZ80F92 device Table 147 POR and VBO Electrical Characteristics TA 0 C to 105 C Symbol Parameter Min Typ Max Unit Conditions VvBo VBO Voltage Threshold 2 40 2 55 2 85 V Vec Vypgo Vpor POR Voltage Threshold 2 45 2 65 2 90 V Vcc Vpon Vuyst POR VBO Hysteresis 50 100 150 mV TANA POR VBO analog RESET duration 40 100 Hs Tyso mn VBO pulse reject period 10 Us VccRAMP Vcc ramp rate requirements to 0 1 100 Vims guarantee proper RESET occurs Typical Current Consumption Under Various Operating Conditions In the following pages Figure 52 illustrates the typical current consumption of the eZ80F92 device versus the number of WAIT states while operating 25 C 3 3V and with either a 1 MHz 10MHz 15 MHz or 20 MHz system clock Figure 53 illustrates the typical current consumption of the eZ80F92 device versus the system clock frequency while oper ating 25 C 3 3V and using 0 2 or 7 WAIT states Figure 54 illustrates the typical current consumption of the eZ80F92 device versu
246. put is the GPIO Port B pin 1 11 The timer event input is the GPIO Port B pin 1 1 0 00 Timer counts at system clock divided by prescaler TRIOS 01 Timer event input is Real Time Clock source 32KHz or 50 60Hz refer to the Real Time Clock section on page 90 for details 10 The timer event input is the GPIO Port B pin 0 11 The timer event input is the GPIO Port B pin 0 PS015308 0404 PRELIMINARY Programmable Reload Timers eZ80F92 eZ80F93 Product Specification VAF ZiLOG Real Time Clock Real Time Clock Overview The Real Time Clock RTC keeps time by maintaining a count of seconds minutes hours day of the week day of the month year and century The current time is kept in 24 hour format The format for all count and alarm registers is selectable between binary and binary coded decimal BCD The calendar operation maintains the correct day of the month and automatically compensates for leap year A simplified block diagram of the RTC and the associated on chip low power 32 KHz oscillator is illustrated in Figure 23 Connections to an external battery supply and 32 KHz crystal network are also demon strated in Figure 23 Vpp Battery Real Time Clock ADDR 15 0 to eZ80 CPU L DATA 0 RTC Clock el System Clock Low Power 32 KHz Oscillator 32 Kel Cystal E CLK_SEL RTC CTRLIA Figure 23 Real Time Clock and 32KHz Oscillator Block Diagram PS015308 0404 PRELIMINARY Real Time Cloc
247. r PRELIMINARY Universal Asynchronous Receiver Transmitter eZ80F92 eZ80F93 Product Specification VAR ZiLOG UART Recommended Usage PS015308 0404 The following is the standard sequence of events that occur in the eZ80F92 device using the UART A description of each follows Module reset Control transfers to configure UART operation Data transfers Module Reset Upon reset all internal registers are set to their default values All command status regis ters are programmed with their default values and the FIFOs are flushed Control Transfers Based on the requirements of the application the data transfer baud rate is determined and the BRG is configured to generate a 16X clock frequency Interrupts are disabled and the communication control parameters are programmed in the UARTx_LCTL register The FIFO configuration is determined and the receive trigger levels are set in the UARTx_FCTL register The status registers UARTx LSR and UARTx MSR are read and ensure that none of the interrupt sources are active The interrupts are enabled except for the transmit interrupt and the application is ready to use the module for transmission reception Data Transfers Transmit To transmit data the application enables the transmit interrupt An interrupt is immediately expected in response The application reads the UARTx IIR register and determines whether the interrupt occurs due to an empty UARTx THR register or due to
248. r 0 0 0 ee eee eee 203 Flash Frequency Divider Values 204 Flash Frequency Divider Register 0 0 0 0 0 0 cece eee eee ee 204 Flash Write Erase Protection Register 2 2 0 0 0 c eee eee eee 205 Flash Interrupt Control Register 0 0 0 0 0 cece eee eee 207 Flash Row Select Register 0 0 cece 208 Flash Page Select Register 0 0 0 eee eee ee eee 208 Flash Column Select Register leen 209 Flash Program Control Register 210 Arithmetic Instructions 0 0 cece eee 211 Bit Manipulation Instructions 0 0 0 cee eee eee eee 211 Block Transfer and Compare Instructions 005 211 Input Output Instructions 20 0 eee eee 213 Exchange Instructions 1 0 0 eee cee eens 213 Load Instructions 0 0 ee cence ees 214 Logical nstructions occ ee Orem be DAR ee ee 214 PRELIMINARY List of Tables xi PS015308 0404 Table 120 Table 121 Table 122 Table 123 Table 124 Table 125 Table 126 Table 127 Table 128 Table 129 Table 130 Table 131 Table 132 eZ80F92 eZ80F93 Product Specification ZiLOG Processor Control Instructions lel 214 Program Control Instructions llsleeleeee eee 215 Rotate and Shift Instructions 0 000 0 0 cc eee eee eee 215 Recommended Crystal Oscillator Specifications 20MHz Operation 224 Recommended Crystal Oscillator Specifications 32 KHz Operation 225 External Read Ti
249. r number Chip Select meets the above conditions A memory access instruction must be executing If all of the foregoing conditions are met to generate a Memory Chip Select then the fol lowing actions occur The appropriate Chip Select CS0 CS1 CS2 or CS3 is asserted driven Low MREQis asserted driven Low Depending upon the instruction either RD or WR is asserted driven Low If the upper and lower bounds are set to the same value CSx UBR CSx LBR then a particular Chip Select is valid for a single 64 KB page PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification Lis ZiLOG Memory Chip Select Priority A lower numbered Chip Select is granted priority over a higher numbered Chip Select For example if the address space of Chip Select 0 overlaps the Chip Select 1 address space Chip Select 0 is active Reset States On RESET Chip Select 0 is active for all addresses because its Lower Bound register resets to 00h and its Upper Bound register resets to FFh All of the other Chip Select Lower and Upper Bound registers reset to 00h Memory Chip Select Example The use of Memory Chip Selects is demonstrated in Figure 6 The associated control reg ister values indicated in Register Values for Memory Chip Select Example in Figure 6 In this example all 4 Chip Selects are enabled and configured for memory addresses Also CS1 overlaps with CSO Because CSO is prioritized higher than CS
250. ransmitter 1 zas i I Data Output T 1 by Receiver i I I SCL Signal T TN IN N Tx oN from Master J 1 2 Sai 8 9 START Condition Clock Pulse for Acknowledge Figure 34 PC Acknowledge Clock Synchronization All masters generate their own clocks on the SCL line to transfer messages on the PC bus Data is only valid during the High period of each clock Clock synchronization is performed using the wired AND connection of the IC interfaces to the SCL line meaning that a High to Low transition on the SCL line causes the relevant devices to start counting from their Low period When a device clock goes Low it holds the SCL line in that state until the clock High state is reached See Figure 35 The Low to High transition of this clock however may not change the state of the SCL line if another clock is still within its Low period The SCL line is held Low by the device with the long est Low period Devices with shorter Low periods enter a High wait state during this time When all devices concerned count off their Low period the clock line is released and goes High There is no difference between the device clocks and the state of the SCL line and all of the devices start counting their High periods The first device to complete its High period again pulls the SCL line Low In this way a synchronized SCL clock is generated with its Low period determined by the device with the longest clock Low period and its High period d
251. rate The remaining six UARTO pins CTSO DCDO DSRO DTRO RTS and RIO are not required for use with the endec The UARTO modem status interrupt should be disabled to prevent unwanted interrupts from these pins The GPIO pins corresponding to these six unused UARTO pins can be used for inputs outputs or interrupt sources Recommended GPIO Port D control register settings are provided in GPIO Mode Selection when using the IIDA Encoder Decoder Refer to the General Purpose Input Output section on page 41 for additional information on setting the GPIO Port modes Table 70 GPIO Mode Selection when using the IrDA Encoder Decoder Allowable GPIO GPIO Port D Bits Port Mode Allowable Port Mode Functions PDO 7 Alternate function PD1 7 Alternate function PD2 PD7 Any other than GPIO Mode 7 Output input open drain open source level 1 2 3 4 5 6 8 or 9 sensitive interrupt input or edge triggered interrupt input Loopback Testing Both internal and external loopback testing can be accomplished with the IrDA endec on the eZ80F92 device Setting the LOOP_BACK bit to 1 enables internal loopback testing During internal loopback the IR_TxD output signal is inverted and connected on chip to the IR_RxD input External loopback testing of the off chip IrDA transceiver can be accomplished by transmitting data from the UART while the receiver is enabled IR RxEN set to 1 PS015308 0404 PRELIMINARY Infrared Encoder De
252. registers are Read Write When locked RTC_UNLOCK 0 the RTC count is enabled and the count registers are Read Only The default at RESET is for the RTC to be locked Real Time Clock Seconds Register This register contains the current seconds count The value in the RTC_SEC register is unchanged by a RESET The current setting of BCD_EN determines whether the values in this register are binary BCD_EN 0 or binary coded decimal BCD_EN 1 Access to this register is Read Only if the RTC is locked and Read Write if the RTC is unlocked See Real Time Clock Seconds Register RTC_SEC 00EOh Table 39 Real Time Clock Seconds Register RTC SEC 00E0h Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access R W RAW R IW R W R W RAW R W R W Note X Unchanged by RESET R W Read Only if RTC locked Read Write if RTC unlocked Binary Coded Decimal Operation BCD EN 1 Bit Position Value Description 7 4 0 5 The tens digit of the current seconds count TEN SEC 3 0 0 9 The ones digit of the current seconds count SEC Binary Operation BCD EN 0 Bit Position Value Description 7 0 00h The current seconds count SEC 3Bh PS015308 0404 PRELIMINARY Real Time Clock 92 PS015308 0404 eZ80F92 eZ80F93 Product Specification Z ZiLOG Real Time Clock Minutes Register This register contains the current minutes count Se
253. rite R Read Only Bit Position Value Description 7 1 00h These bits define the upper byte of the Flash address When FLASH_ADDR_U FEh on chip Flash is enabled the Flash address space begins at address FLASH_ADDR_U Ob 0000h On chip Flash is prioritized over all external Chip Selects Reserved enforces alignment on a 128KB boundary PS015308 0404 PRELIMINARY Flash Memory eZ80F92 eZ80F93 Product Specification 203 ZiLOG Flash Control Register The Flash Control register enables or disables memory access to Flash I O access to the Flash control registers and I O programming to Flash memory are still possible while Flash memory space access is disabled The minimum access time of the internal Flash is 60ns The Flash control register must be configured to provide the appropriate number of WAIT states based on the system clock frequency of the eZ80F92 device Default on RESET is for 4 WAIT states to be inserted for Flash memory access Table 117 Flash Control Register FLASH_CTRL 00F8h Bit 7 6 5 4 3 2 Reset 1 0 0 0 1 0 0 0 CPU Access RW RW RW R R W R Note R W Read Write R Read Only Po ien Value Description 7 5 000 O Wait states are inserted when Flash is active ea 001 1 Wait state is inserted when Flash is active 010 2 Wait states are inserted when Flash is active 011 3 Wait states are in
254. rrently being accessed by the external peripheral To prevent data errors ZDI should avoid data transmission while another device is controlling the bus Finally exiting ZDI DEBUG mode while an external peripheral controls the address and data buses as indicated by BUSACK assertion may produce unpredictable results PS015308 0404 PRELIMINARY ZiLOG Debug Interface eZ80F92 eZ80F93 Product Specification ZiLOG ZDI Write Only Registers PS015308 0404 ZDI Write Only Registers lists the ZDI Write Only registers Many of the ZDI Write Only addresses are shared with ZDI Read Only registers Table 94 ZDI Write Only Registers ZDI Reset Address ZDI Register Name ZDI Register Function Value 00h ZDI ADDRO L Address Match 0 Low Byte XXh 01h ZDI ADDRO H Address Match 0 High Byte XXh 02h ZDI ADDRO U Address Match 0 Upper Byte XXh 04h ZDI ADDR1 L Address Match 1 Low Byte XXh 05h ZDI ADDR1 H Address Match 1 High Byte XXh 06h ZDI ADDR1 U Address Match 1 Upper Byte XXh 08h ZDI ADDR2 L Address Match 2 Low Byte XXh 09h ZDI ADDR2 H Address Match 2 High Byte XXh OAh ZDI ADDR2 U Address Match 2 Upper Byte XXh OCh ZDI ADDR3 L Address Match 3 Low Byte XXh ODh ZDI ADDR3 H Address Match 3 High Byte XXh OEh ZDI ADDR3 U Address Match 4 Upper Byte XXh 10h ZDI BRK CTL BREAK Control register 00h 11h ZDI MASTER CTL Master Control register 00h 13h ZDI WR DATA L Write Data Low Byte XXh
255. rrupts the value written to the Port x Data register bit selects the interrupt edge or interrupt level See GPIO Mode Selection for more information Table 7 Port x Data Registers PB DR 009Ah PC DR 009Eh PD DR 00A2h Bit 7 6 5 4 3 2 1 0 Reset X X X X X X X X CPU Access RAV RW RW RW RW RW RW RW Note X Undefined R W Read Write PS015308 0404 PRELIMINARY General Purpose Input Output eZ80F92 eZ80F93 Product Specification 46 ZiLOG Port x Data Direction Registers In conjunction with the other GPIO Control Registers the Port x Data Direction registers detailed in Port x Data Direction Registers PB_DDR 009Bh PC_DDR 009Fh PD_DDR 00A3h control the operating modes of the GPIO port pins See GPIO Mode Selection for more information Table 8 Port x Data Direction Registers PB DDR 009Bh PC DDR 009Fh PD DDR 00A3h Bit 7 6 5 4 3 2 1 0 Reset 1 1 1 1 1 1 1 1 CPU Access RW RW RW RW RW RW RW RAW Note R W Read Write Port x Alternate Register 1 In conjunction with the other GPIO Control Registers the Port x Alternate Register 1 detailed in Port x Alternate Registers 1 PB_ALT1 009Ch PC ALTI 00A0h PD ALTI 00A4h control the operating modes of the GPIO port pins See GPIO Mode Selection for more information Table 9 Port x Alternate Registers 1 PB ALT1 009Ch PC ALT1 00A0
256. rs in the course of further application and characterization work In addition ZiLOG cautions that delivery might be uncertain at times due to start up yield issues ZiLOG Inc 532 Race Street San Jose CA 95126 Telephone 408 558 8500 FAX 408 558 8300 Internet www zilog com PRELIMINARY Ordering Information Document Information Document Number Description eZ80F92 eZ80F93 Product Specification Zi ZiLOG The Document Control Number that appears in the footer on each page of this document contains unique identifying attributes as indicated in the following table PS Product Specification 0153 Unique Document Number 08 Revision Number 0404 Month and Year Published Change Log Rev Date Purpose By 01 06 02 Original issue J Eversmann R Beebe 02 01 03 Technical Updates J Eversmann 03 01 03 Technical Updates M Richmond R Beebe 04 02 03 Modified hyperlinks refs A Abuhakmeh A Koontz 05 08 03 Modified extended temp R Xue A Shaw 06 08 03 Minor revision R Beebe 07 02 04 Revised BRG in UART section C Bender 08 04 04 Added cautions for SLP HLT C Bender PS015308 0404 PRELIMINARY Document Information Index Numerics 100 pin LQFP package 4 20 16 bit clock divisor value 112 137 16 bit divisor count 112 137 20 MHz Primary Crystal Oscillator Operation 223 32 KHz Real Time Clock Crystal Oscillator Opera tion 224 A AAK see IC Acknowledge bit Abs
257. s There are six different sources of interrupts from the UART The six sources of interrupts are Transmitter two different interrupts Receiver three different interrupts Modem status PS015308 0404 PRELIMINARY Universal Asynchronous Receiver Transmitter PS015308 0404 eZ80F92 eZ80F93 Product Specification zZ 109 ZiLOG UART Transmitter Interrupt The transmitter hold register empty interrupt is generated if there is no data available in the hold register The transmission complete interrupt is generated after the data in the shift register is sent Both interrupts can be disabled using individual interrupt enable bits or cleared by writing data into the UARTx_THR register UART Receiver Interrupts A receiver interrupt can be generated by three possible sources The first source a Receiver Data Ready indicates that one or more data bytes are received and are ready to be read This interrupt is generated if the number of bytes in the receiver FIFO is greater than or equal to the trigger level If the FIFO is not enabled the interrupt is generated if the receive buffer contains a data byte This interrupt is cleared by reading the UARTx RBR The second interrupt source is the receiver time out A receiver time out interrupt is gener ated when there are fewer data bytes in the receiver FIFO than the trigger level and there are no reads and writes to or from the receiver FIFO for four consecutive byte times When the
258. s The UARTXx IER registers share the same I O addresses as the UARTx_BRG_H registers See UART Interrupt Enable Registers UARTO IER 00C1h UARTI IER 00D1h Table 57 UART Interrupt Enable Registers UARTO IER 00C1h UART1 IER 00D1h Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access R R R RW RW RW RW RW Note R Read Only R W Read Write Bit Position Value Description 7 5 000 Reserved 4 0 Transmission complete interrupt is disabled TIE 1 Transmission complete interrupt is generated when both the transmit hold register and the transmit shift register are empty 3 0 Modem interrupt on edge detect of status inputs is disabled MIE 1 Modem interrupt on edge detect of status inputs is enabled 2 0 Line status interrupt is disabled EE 1 Line status interrupt is enabled for receive data errors incorrect parity bit received framing error overrun error or break detection 1 0 Transmit interrupt is disabled WE 1 Transmit interrupt is enabled Interrupt is generated when the transmit FIFO buffer is empty indicating no more bytes available for transmission 0 0 Receive interrupt is disabled RIE Receive interrupt and receiver time out interrupt are enabled Interrupt is generated if the FIFO buffer contains data ready to be read or if the receiver times out PS015308 0404 PRELIMINARY Universal Asynchronous Receiver Tra
259. s mode state is 15 CPU clock cycles in duration Notes 1 Setting BUS CYCLE to 1 in Intel bus mode causes the ALE pin to not function properly 2 Use of the external WAIT input pin in Z80 mode requires that BUS CYCLE is set to a value greater than 1 3 BUS CYCLE produces no effect in eZ80 mode PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification Z ZiLOG Watch Dog Timer Watch Dog Timer Overview PS015308 0404 The Watch Dog Timer WDT helps protect against corrupt or unreliable software power faults and other system level problems which may place the CPU into unsuitable operat ing states The eZ80F92 WDT features Four programmable time out periods 218 9 27 gt and 27 clock cycles Two selectable WDT clock sources the system clock or the Real Time Clock source on chip 32 KHz crystal oscillator or 50 60Hz signal e A selectable time out response a time out can be configured to generate either a RESET or a nonmaskable interrupt NMI A WDT time out RESET indicator flag Figure 19 illustrates the block diagram for the Watch Dog Timer Data 7 0 Control Register Reset Register WDT Control Logic WDT CLK RTC Clock System Clock 28 Bit Upcounter Time out Compare Logic WDT_PERIOD RESET NMI to eZ80 CPU Figure 19 Watch Dog Timer Block Diagram PRELIMINARY Watch Dog Timer eZ80F92 eZ80F93 Product Specification ZiLOG
260. s temperature while operating at 3 3V 7 WAIT states and with either a 1 MHz 10MHz 15 MHz or 20 MHz system clock Figure 55 illus trates the typical current consumption of the eZ80F92 device versus system clock fre quency while operating in HALT mode Figure 56 illustrates the typical current consumption of the eZ80F92 device versus temperature while operating in SLEEP mode PS015308 0404 PRELIMINARY Electrical Characteristics eZ80F92 eZ80F93 Product Specification 229 lcc vs WAIT States Typical 3 3V 25C 60 00 50 00 40 00 5 MHz E m 10 MHz a 30 00 15 MHz 5 pe 20 MHz o 20 00 10 00 0 00 0 1 2 3 4 5 6 7 WAIT States Figure 52 lcc Versus WAIT States as a Function of Frequency PS015308 0404 PRELIMINARY Electrical Characteristics eZ80F92 eZ80F93 Product Specification zZ 230 ZiLOG lcc VS Frequency Typical 3 3V 25C 60 00 50 00 40 00 T 9 0 WAIT 30 00 8 2 WAIT t a7 WAIT 20 00 10 00 0 00 5 10 15 20 Frequency MHz Figure 53 lcc Versus Frequency as a Function of WAIT States PS015308 0404 PRELIMINARY Electrical Characteristics eZ80F92 eZ80F93 Product Specification 231 lcc versus Temp with 7 WAIT States Typical 3 3V 40 00 35 00 30 00 25 00 T 5 MHz m 10 MHz t 20 00 A 15 MHz se 20 MHz o 15 00 10 00 5 00 0 00 0 20 40 60 80 100 Temperature C Figure 54 lcc Versus Temperature as a Function of Frequency PS01530
261. sceiver To enable transmit encoding the IR RxEN bit in the IR CTL register must be set to 0 Each UART bit is 16 clocks wide If the data to be transmitted is a logical 1 High the IR TxD signal remains Low 0 for the full 16 clock period If the data to be transmitted is a logical 0 a 3 clock High 1 pulse is output following a 7 clock Low 0 period Follow ing the 3 clock High pulse a 6 clock Low pulse completes the full 16 clock data period Data transmission is illustrated in Figure 26 During data transmission the IR receive function should be disabled by clearing the IR RxEN bit in the IR CTL reg to 0 The SIR data format uses half duplex communication the UART does not transmit data while the receiver decoder is enabled l l l l l S 16 clock l period l Data Bit 3 1 Start Bit 0 Data Bit 0 1 Data Bit 1 2 0 Data Bit 2 1 3 clock l l l I l l l l pulse l l l l I I l I l Io gt I l I l l l I l l I l IR_TxD l l 7 clock gt H i i I delay Figure 26 Infrared Data Transmission Receive PS015308 0404 Data is received from the IR transceiver via the IR_RxD signal and decoded by the IrDA endec This decoded data is passed from the endec to UARTO To enable receiver decode the IR RxEN bit in the IR_CTL register must be set to 1 The SIR data format uses half duplex communication therefore the UART should not transmit data during normal oper ation while the rec
262. self clearing functions Mass Erase requires approximately 200 ms to erase the full 128 KB 64 KB of main Flash and the 256 byte Information Page Page Erase requires approximately 10ms to erase a 1 KB page Upon completion of either a Mass Erase or Page Erase the value of the corresponding bit is reset to 0 While Flash is being erased any Read or Write access of Flash memory force the CPU into a WAIT state until the Erase operation is complete and Flash can be accessed Reads and Writes to areas other than Flash can proceed as usual while an Erase operation is underway During row programming any Reads of Flash memory force a WAIT condition until the row programming operation completes or times out PS015308 0404 PRELIMINARY Flash Memory PS015308 0404 eZ80F92 eZ80F93 Product Specification Zi ZiLOG Table 125 Flash Program Control Register FLASH_PGCTL 00FFh Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access R R R R R RW RW RAW Note R W Read Write R Read Only Bit Position Value Description 7 3 0000 Reserved 2 0 Row Program Disable or Row Program completed ROW_PGM ue 1 Row Program Enable This bit automatically resets to 0 when the row address reaches 128 or when the Row Program operation times out 1 0 Page Erase Disable Page Erase completed PO ERASE Page Erase Enable This bit automatically resets to 0 when the Page Erase oper
263. serted when Flash is active 100 4 Wait states are inserted when Flash is active 101 5 Wait states are inserted when Flash is active 110 6 Wait states are inserted when Flash is active 111 7 Wait states are inserted when Flash is active 4 0 Reserved 3 0 Flash Memory Access is disabled PERSH EN 1 Flash Memory Access is enabled 2 0 000 Reserved PS015308 0404 PRELIMINARY Flash Memory eZ80F92 eZ80F93 Product Specification 204 ZiLOG Flash Frequency Divider Register The 8 bit frequency divider allows programming to Flash over a range of system clock fre quencies Flash can programmed with system clock frequencies ranging from 154 KHz through 50 MHz The Flash controller requires an input clock with a period that falls within the range of 5 1 6 5 us The period of the Flash controller clock is set via the Flash Frequency Divider register Writes to this register are allowed only after it is unlocked via the FLASH KEY register The Frequency Divider register value required vs system clock frequency is detailed in Flash Frequency Divider Values System clock frequencies outside of the ranges shown in this table are not supported Table 118 Flash Frequency Divider Values System Clock Frequency Flash Frequency Divider Value 154 196KHz 1 308 392KHz 2 462 588KHz 3 616KHz 50MHz CEILING System Clock Frequency MHz x 5 1 us Note The CEILING function rounds fractional values up to the next w
264. ses or other rights are conveyed implicitly or otherwise by this document under any intellectual property rights PS015308 0404 PRELIMINARY eZ80F92 eZ80F93 Product Specification ZiLOG List OF Figures MNCPCPPrP vii Lastof Tables 5 used guest a ent a er dont jefe nale ga tu Moped a iR ix Architectural OVerview 22 4050 peared ek rq Ober vba Perd bru wei e sas 1 PCatres iuste eres Re aren ne tee ated hase debi hae apod So o qe RR aad 1 Block Di gram po 23 neo et eke ORG ea RECEN Pee baa GN RENS 2 Pin Description oss csi eee cbs Hee eae Cae tds a RE WU a hE Re PEE 4 Pin Characteristics i s0 s 44 Weis pat An hed p espe edu e eee ea E 20 Register Map iia eoe eee ates EN E EEE EE epe 25 7280 COU Core MEINEN 33 pru pices ae ed ook teehee shee eee ek ween e ELE EN ee eee ed Gage Rees 33 RGSeL susra pu duos tue iare ed mans nate na EY jad hades trek le ene 34 R set Operation 23 22 244 eee eee eee bbe ee nya n uber bee dee be ee 34 Power On Reset i eee ber LNER he E Are edes a al edes ea d 34 Voltage Brown Out Reset llle eh 35 Low Power Modes sssseeeee e s 37 OVerVIeW sci woche are PE e bee pk eei wa eed pae 37 SLEEP MOd i3 ict bir desk Rue E CE RE recep edd du eS died ee 37 HALT Mode eee edt ee CORR ORE A CURRUS on a ne deena 37 Clock Peripheral Power Down Registers 0 0 0s cece ee ee eee een ee 38 General Purpose Input Output sese s 41 GPIO
265. smitted 88h Data byte received after slave address received NACK transmitted 90h Data byte received after General Call received ACK transmitted 98h Data byte received after General Call received NACK transmitted AOh STOP or repeated START condition received in SLAVE mode A8h Slave address and Read bit received ACK transmitted BOh Arbitration lost in address as master slave address and Read bit received ACK transmitted B8h Data byte transmitted in SLAVE mode ACK received COh Data byte transmitted in SLAVE mode ACK not received C8h Last byte transmitted in SLAVE mode ACK received DOh Second Address byte and Write bit transmitted ACK received D8h Second Address byte and Write bit transmitted ACK not received F8h No relevant status information IFLG 0 If an illegal condition occurs on the PC bus the bus error state is entered status code 00h To recover from this state the STP bit in the I2C_CTL register must be set and the IFLG bit cleared The I C then returns to the idle state No STOP condition is transmitted on the IC bus Note The STP and STA bits may be set to 1 at the same time to recover from the bus error The C then sends a START condition PRELIMINARY I2C Serial I O Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification 161 ZiLOG C Clock Control Register The I2C CCR register is a Write Only register The seven LSBs control the frequency at which the I C bus is sampled and the freque
266. st monitor the row time out error bit either by enabling this interrupt or through polling If a row time out occurs the Flash controller aborts the row programming operation and software must then assure that no further writes are performed to the row without it first being erased It is suggested that row pro gramming only be used one time per row and not in combination with single byte Writes to the same row without first erasing it Otherwise the burden is on software to ensure that PRELIMINARY Flash Memory eZ80F92 eZ80F93 Product Specification 200 ZiLOG the 16ms maximum cumulative programming time between erasures is not exceeded for a TOW Memory Write A single byte memory Write operation uses the address bus and data bus of the eZ80F92 device for programming a single data byte to Flash While the CPU executes a LOAD instruction the Flash controller asserts the internal WAIT signal to stall the CPU until the Write is complete A single byte Write takes between 66us and 85ys to complete Pro gramming an entire row using memory Writes therefore takes at most 10 8ms This time does not include time required by the CPU to transfer data to the registers which is a func tion of the instructions employed and the system clock frequency The memory Write function does not support multibyte row programming Because mem ory Writes are self timed they can be performed back to back without any necessity for polling or interrupts Er
267. status codes listed in PC Master Transmit Status Codes For Data Bytes is in the I2C_SR register Table 81 IC Master Transmit Status Codes For Data Bytes Code IC State Microcontroller Response Next IC Action 28h Data byte transmitted ACK Write byte to DATA clear IFLG Transmit data byte receive ACK received Or set STA clear IFLG Transmit repeated START Or set STP clear IFLG Transmit STOP Or set STA amp STP clear IFLG Transmit START then STOP PRELIMINARY I2C Serial I O Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification Lli ZiLOG Table 81 PC Master Transmit Status Codes For Data Bytes Continued Code IC State Microcontroller Response Next IC Action 30h Data byte Same as code 28h Same as code 28h transmitted ACK not received 38h Arbitration lost Clear IFLG Return to idle Or set STA clear IFLG Transmit START when bus free When all bytes are transmitted the microcontroller should write a 1 to the STP bit in the I2C CTL register The PC then transmits a STOP condition clears the STP bit and returns to the idle state Master Receive In MASTER RECEIVE mode the I C receives a number of bytes from a slave transmitter After the START condition is transmitted the IFLG bit is 1 and the status code 08h is loaded in the I2C SR register The I2C DR register should be loaded with the slave address or the first part of a 10 bit slave address
268. t in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects ADDR1 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects ADDR2 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects ADDR3 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects ADDR4 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects ADDR5 Address B
269. t the winning master is trying to address it The losing master must switch over immediately to its slave receiver mode Figure 35 illustrates the arbitration procedure for two masters Of course more may be involved depending on how many masters are connected to the bus The moment there is a difference between the internal data level of the master generating DATA 1 and the actual level on the SDA line its data output is switched off which means that a High output level is then connected to the bus As a result the data transfer initiated by the winning master is not affected Because con trol of the IC bus is decided solely on the address and data sent by competing masters there is no central master nor any order of priority on the bus Special attention must be paid if during a serial transfer the arbitration procedure is still in progress at the moment when a repeated START condition or a STOP condition is trans mitted to the C bus If it is possible for such a situation to occur the masters involved must send this repeated START condition or STOP condition at the same position in the format frame In other words arbitration 1s not allowed between Arepeated START condition and a data bit PRELIMINARY I2C Serial I O Interface eZ80F92 eZ80F93 Product Specification Z4 ZiLOG A STOP condition and a data bit A repeated START condition and a STOP condition Clock Synchronization for Handshake The Clock synchronizing
270. t to xOxxxx10b 5 Read Only if Flash Memory is locked Read Write if Flash Memory is unlocked PS015308 0404 PRELIMINARY Register Map eZ80F92 eZ80F93 Product Specification Z ZiLOG Table 3 Register Map Continued Address Reset CPU Page hex Mnemonic Name hex Access Programmable Reload Counter Timers continued 0087 TMR2_DR_L Timer 2 Data Register Low Byte 00 R 86 TMR2_RR_L Timer 2 Reload Register Low Byte 00 W 87 0088 TMR2_DR_H Timer 2 Data Register High Byte 00 R 87 TMR2_RR_H Timer 2 Reload Register High Byte 00 W 88 0089 TMR3_CTL Timer 3 Control Register 00 R W 85 008A TMR3_DR_L Timer 3 Data Register Low Byte 00 R 86 TMR3_RR_L Timer 3 Reload Register Low Byte 00 87 008B TMR3_DR_H Timer 3 Data Register High Byte 00 R 87 TMR3_RR_H Timer 3 Reload Register High Byte 00 W 88 008C TMR4_CTL Timer 4 Control Register 00 R W 85 008D TMR4_DR_L Timer 4 Data Register Low Byte 00 R 86 TMR4_RR_L Timer 4 Reload Register Low Byte 00 W 87 008E TMR4_DR_H Timer 4 Data Register High Byte 00 R 87 TMR4_RR_H Timer 4 Reload Register High Byte 00 W 88 008F TMR5 CTL Timer 5 Control Register 00 R W 85 0090 TMR5_DR_L Timer 5 Data Register Low Byte 00 R 86 TMR5 RR L Timer 5 Reload Register Low Byte 00 W 87 0091 TMR5_DR_H Timer 5 Data Register High Byte 00 R 87 TMR5 RR H Timer 5 Reload Register High Byte 00 W 88 0092 TMR_ISS Timer Input Source Select Re
271. tage 35 228 Voltage Brown Out 34 228 protection circuitry 35 Threshold 34 35 228 Brown Out Reset 35 voltage supply 2 34 35 42 142 226 227 Vvpo see Voltage Brown Out threshold PS015308 0404 PRELIMINARY eZ80F92 eZ80F93 Product Specification Z z ZiLOG W WAIT condition 1 11 22 59 62 66 209 WAIT Input Signal 53 WAIT pin external 55 56 WAIT Request 11 WAIT state 56 63 239 240 Timing for Read Operations 239 Timing for Write Operations 240 WAIT states 48 50 53 56 62 70 170 193 203 227 230 Watch Dog Timer 34 37 74 76 169 clock source 74 76 clock sources 75 Control Register 25 76 Operation 75 Overview 74 Registers 76 RESET 25 76 Reset Register 77 time out 38 74 77 time out period 75 77 time out reset 25 time out values 75 WCOL see Write Collision WDT see Watch Dog Timer WR see Write instruction Write Collision 135 136 140 SPI 140 Write instruction 10 11 22 50 53 56 59 62 236 239 Write Violation 206 X Xy 17 23 Xour 17 23 Z Z80 Bus Mode 55 Z80 Memory mode 183 187 ZCL see ZiLOG Debug Interface clock ZDA see ZiLOG Debug Interface data Index ZDI see ZiLOG Debug Interface 190 ZDI Supported Protocol 164 ZDI BUS STAT 170 172 187 ZDI BUSACK EN 170 187 ZiLOG Debug Interface190 clock 164 165 167 175 Address Match Registers 172 Block Read 169 BLOCK WRITE 168 Break 176 BREAK Control Register 174 BREAK mode 186 Bus Control Register 181
272. tates eZ80F92 eZ80F93 Product Specification Z ZiLOG n D m m twa 74 l l l l l l System Clock l l l l l l I I I I I l l l I I l l I l l l l l l I I I I I CSx I I l I I I l l l l l l l l l ALE l l l l l l l l l l l I l l l l l l l l l l l l l l l l l MREQ l I l or IORQ l l l l l l l Figure 12 Example Intel Bus Mode Read Timing Separate Address and Data Buses PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification Z ZiLOG Tf 2 m ar 4 smc I LELELEL LLL LILLY l l l l l l l l l ALE l l l l l l AEE l l l l l l l l l l READY MREQ l l or IORQ l I I Figure 13 Example Intel Bus Mode Write Timing Separate Address and Data Buses PS015308 0404 PRELIMINARY Chip Selects and Wait States eZ80F92 eZ80F93 Product Specification 62 ZiLOG Intel Bus Mode Multiplexed Address and Data Bus During Read operations with multiplexed address and data the Intel M bus mode employs 4 states T1 T2 T3 and T4 as described in Intel Bus Mode Read States Multiplexed Address and Data Bus Table 18 Intel Bus Mode Read States Multiplexed Address and Data Bus STATE T1 The Read cycle begins in State T1 The CPU drives the address onto the DATA bus and the associated Chip Select signal is asserted The CPU drives the ALE signal High at the beginning of T1
273. terface 135 eZ80F92 eZ80F93 Product Specification zZ 136 ZiLOG 4 Ifthe SPI interrupt is enabled by setting IRQ_EN SPI_CTL 7 High an SPI interrupt is generated Clearing the Mode Fault flag is performed by reading the SPI Status register The other SPI control bits SPI EN and MASTER EN must be restored to their original states by user software after the Mode Fault flag is cleared Write Collision The WRITE COLLISION flag WCOL SPI SR 5 is set to 1 when an attempt is made to write to the SPI Transmit Shift register SPI TSR while data transfer occurs Clearing the WCOL bit is performed by reading SPI SR with the WCOL bit set SPI Baud Rate Generator The SPI s Baud Rate Generator creates a lower frequency clock from the high frequency system clock The Baud Rate Generator output is used as the clock source by the SPI Baud Rate Generator Functional Description The SPI s Baud Rate Generator consists of a 16 bit downcounter two 8 bit registers and associated decoding logic The Baud Rate Generator s initial value is defined by the two BRG Divisor Latch registers SPI BRG H SPI BRG LJ At the rising edge of each system clock the BRG decrements until it reaches the value 0001n On the next system clock rising edge the BRG reloads the initial value from SPI BRG H SPI BRG L and outputs a pulse to indicate the end of count Calculate the SPI Data Rate with the follow ing equation System Clock Frequency
274. the Chip Select Wait State Generator block to generate Chip Selects 16 ADDR13 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects 17 ADDR14 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects 18 Vpp Power Supply Power Supply 19 Vss Ground Ground 20 ADDR15 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Continued Pin Symbol Function Signal Direction Description 21 ADDR16 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O sp
275. the IFLG bit is set and the I2C SR register contains status code AOh If the AAK bit is cleared to 0 during a transfer the PC transmits a not acknowledge bit High level on SDA after the next byte is received and set the IFLG bit The I2C_SR reg ister contains the status code 88h or 98h if SLAVE RECEIVE mode is entered with the general call address The IC returns to the idle state when the IFLG bit is cleared to 0 PS015308 0404 PRELIMINARY I2C Serial I O Interface eZ80F92 eZ80F93 Product Specification ZiLOG lC Registers PS015308 0404 Addressing The processor interface provides access to six 8 bit registers four Read Write registers one Read Only register and two Write Only registers as indicated in C Register Descrip tions Table 84 IC Register Descriptions Register Description I2C_SAR Slave address register I2C_XSAR Extended slave address register I2C_DR Data byte register I2C_CTL Control register I2C_SR Status register Read Only I2C_CCR Clock Control register Write Only I2C_SRR Software reset register Write Only Resetting the I C Registers Hardware reset When the IC is reset by a hardware reset of the eZ80F92 device the I2C_SAR I2C_XSAR I2C DR and I2C_CTL registers are cleared to 00h while the I2C_SR register is set to F8h Software Reset Perform a software reset by writing any value to the IC Software Reset Register IZC_SRR A software reset sets the IC back to
276. the ROW_PGM bit of the Flash Program Control Register For multibyte Writes the CPU sets the address registers enables row program ming and then executes a output to I O instruction with repeat to load the block of data into the FLASH_DATA register For each individual byte written to the FLASH_DATA register during the block move the Flash controller asserts the internal WAIT signal to stall the CPU until the current byte has been programmed During row programming the Flash controller continuously asserts Flash s high voltage until all bytes are programmed column address lt 127 As a consequence the row can be programmed faster than if the high voltage is toggled for each byte The per byte program ming time during row programming is between 41 us and 52 us As such programming the 128 bytes of a row in this mode takes at most 6 7ms leaving 9 3ms for the overhead of CPU instructions used to fetch the 128 bytes A typical sequence that performs a multibyte I O Write is shown in the following sequence 1 Check the FLASH_IRQ register to be sure any previous Row Program has completed 2 Write the FLASH_PAGE FLASH_ROW and FLASH_COL registers with the address of the first byte to be written 3 Set the ROW_PGM bit in the FLASH_PGCTL register to enable row programming mode 4 Write the next data value to the FLASH_DATA register If the end of the row has not been reached return to Step 4 During row programming software mu
277. the SDA line during the ACK clock pulse so that it remains stable Low during the High period of this clock pulse See Figure 34 A receiver that is addressed is obliged to generate an ACK after each byte is received When a slave receiver doesn t acknowledge the slave address for example unable to receive because it s performing some real time function the data line must be left High by the slave The master then generates a STOP condition to abort the transfer If a slave receiver acknowledges the slave address but cannot receive any more data bytes the master must abort the transfer The abort is indicated by the slave generating the Not Acknowledge NACK on the first byte to follow The slave leaves the data line High and the master generates the STOP condition If a master receiver is involved in a transfer it must signal the end of data to the slave transmitter by not generating an ACK on the final byte that is clocked out of the slave The 1 ACK is defined as a general Acknowledge bit By contrast the rc Acknowledge bit is represented as AAK bit 2 of the PC Control Register which identifies which ACK signal to transmit See IC Control Registers I2C CTL 00CBh on page 158 PS015308 0404 PRELIMINARY I2C Serial I O Interface eZ80F92 eZ80F93 Product Specification Ll us ZiLOG slave transmitter must release the data line to allow the master to generate a STOP or a repeated START condition Data Output zu X X 7 by T
278. timer is loaded with the value 0000h which selects the maximum time out period The CPU can be programmed to poll the PRT_IRQ bit for the time out event Alterna tively an interrupt service request signal can be sent to the CPU by setting IRQ EN to 1 PS015308 0404 PRELIMINARY Programmable Reload Timers eZ80F92 eZ80F93 Product Specification 82 ZiLOG Then when the end of count value 0000h is reached and PRT_IRQ is set to 1 an inter rupt service request signal is passed to the CPU PRT_IRQ is cleared to 0 and the interrupt service request signal is inactivated whenever the CPU reads from the timer control regis ters TMRx CTL Timer Input Source Selection Timers 0 3 feature programmable input source selection By default the input is taken from the eZ80F92 device s system clock Alternatively Timers 0 3 can take their input from port input pins PBO Timers 0 and 2 or PB1 Timers 1 and 3 Timers 0 3 can also use the Real Time Clock source 50 60 or 32768Hz as their clock sources When the timer clock source is the Real Time Clock signal the timer decrements on the second ris ing edge of the system clock following the falling edge of the RTC_Xoyrz pin The input source for these timers is set using the Timer Input Source Select register Event Counter When Timers 0 3 are configured to take their inputs from port input pins PBO and PB1 they function as event counters For event counting the clock prescaler is byp
279. to 0 MADI 1 The CPU s Mixed Memory mode MADL bit is set to 1 2 0 The CPU s Interrupt Enable Flag 1 is reset to 0 Maskable IEF 1 interrupts are disabled 1 The CPU s Interrupt Enable Flag 1 is set to 1 Maskable interrupts are enabled 1 0 00 Reserved ZDI Read Register Low High and Upper The ZDI register Read Only address space offers Low High and Upper functions which contain the value read by a Read operation from the ZDI Read Write Control register ZDI RW CTL This data is valid only while in ZDI BREAK mode and only if the instruction is read by a request from the ZDI Read Write Control register See ZDI Read Register Low High and Upper ZDI RD L 10h ZDI RD H 11h and ZDI RD U 12h in the ZDI Register Read Only Address Space Table 108 ZDI Read Register Low High and Upper ZDI RD L 10h ZDI RD H 11h and ZDI RD U 12h in the ZDI Register Read Only Address Space Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 CPU Access Note R Read Only Bit Position Value Description 7 0 00h Values read from the memory location as requested by ZDI RD L FFh the ZDI Read Control register during a ZDI Read ZDI RD H or operation The 24 bit value is supplied by ZDI RD U ZDI RD U ZDI RD H ZDI RD Lj PRELIMINARY ZiLOG Debug Interface PS015308 0404 eZ80F92 eZ80F93 Product Specification ZiLOG ZDI Bus Status Register The ZDI Bus Status register
280. transfer data is sent and received simultaneously by both the master and the slave SPI devices In a serial peripheral interface separate signals are required for data and clock The SPI may be configured as either a master or a slave The connection of two SPI devices one master and one slave and the direction of data transfer is demonstrated in Figures 28 and 29 MASTER DATAIN 3 MISO DATAOUT 8 Bit Shift Register CLKOUT Baud Rate Generator Figure 28 SPI Master Device ENABLE gt 5S DATAIN gt vosi DATAOUT CLKIN gt scx gt 8 Bit Shift Register Figure 29 SPI Slave Device PS015308 0404 PRELIMINARY Serial Peripheral Interface 132 eZ80F92 eZ80F93 Product Specification Z 133 ZiLOG SPI Signals PS015308 0404 The four basic SPI signals are MISO Master In Slave Out MOSI Master Out Slave In SCK SPI Serial Clock SS Slave Select These SPI signals are discussed in the following paragraphs Each signal is described in both MASTER and SLAVE modes Master In Slave Out The Master In Slave Out MISO pin is configured as an input in a master device and as an output in a slave device It is one of the two lines that transfer serial data with the most significant bit sent first The MISO pin of a slave device is placed in a high impedance state if the slave is not selected When the SPI is not enabled this signal is in a high impedance state Mast
281. ued Pin Symbol Function Signal Direction Description 96 VDD Power Supply Power Supply 97 Vss Ground Ground 98 SDA C Serial Data Bidirectional This pin carries the C data signal 99 SCL C Serial Bidirectional This pin is used to receive and transmit the Clock C clock 100 PHI System Clock Output This pin is an output driven by the internal system clock Pin Characteristics Pin Characteristics of the eZ80F92 Device describes the characteristics of each pin in the eZ80F92 device s 100 pin LQFP package Table 2 Pin Characteristics of the eZ80F92 Device Schmitt Reset Active Tristate Pull Trigger Open Drain Pin Symbol Direction Direction Low High Output Up Down Input Source 1 ADDRO 1 0 O N A Yes No No No 2 ADDR1 1 0 O N A Yes No No No 3 ADDR2 1 0 O N A Yes No No No 4 ADDR3 1 0 O N A Yes No No No 5 ADDR4 1 0 O N A Yes No No No 6 ADDR5 I O O N A Yes No No No 7 VDD 8 Vss 9 ADDR6 1 0 O N A Yes No No No 10 ADDR7 1 0 O N A Yes No No No 11 ADDR8 1 0 O N A Yes No No No 12 ADDR9 1 0 O N A Yes No No No 13 ADDR10 I O O N A Yes No No No 14 ADDR11 I O O N A Yes No No No 15 ADDR12 1 0 O N A Yes No No No PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification VAF ZiLOG Table 2 Pin Characteristics of the eZ80F92 Device Continued Schmitt
282. ures including SLEEP mode HALT mode and selective peripheral power down control Two UARTs with independent baud rate generators SPI with independent clock rate generator PC with independent clock rate generator IrDA compliant infrared encoder decoder New DMA like CPU instructions for efficient block data transfer Glueless external peripheral interface with 4 Chip Selects individual Wait State gen erators and an external WAIT input pin supports Z80 Intel and Motorola style buses Fixed priority vectored interrupts both internal and external and interrupt controller Real Time Clock with on chip 32 KHz oscillator selectable 50 60 Hz input and sepa rate Vpp pin for battery backup Six 16 bit Counter Timers with prescalers and direct input output drive Watch Dog Timer For simplicity the term eZ80 CPU is referred to as CPU for the bulk of this document PRELIMINARY Architectural Overview 24 bits of General Purpose I O and ZDI debug interfaces 100 pin LQFP package 3 0 3 6 V supply voltage with 5 V tolerant inputs Operating Temperature Range Standard 0 C to 70 C Extended 40 C to 105 C eZ80F92 eZ80F93 Product Specification ZiLOG Note All signals with an overline are active Low For example B W for which WORD is active Low and B W for which BYTE is active Low Power connections follow these conventional descriptions Connection Circuit Device Power Voc VDD
283. us Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Continued Pin Symbol Function Signal Direction Description 7 VDD Power Supply Power Supply 8 Vss Ground Ground 9 ADDR6 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects 10 ADDR7 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects 11 ADDR8 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Ch
284. ut in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects PS015308 0404 PRELIMINARY Architectural Overview eZ80F92 eZ80F93 Product Specification ZiLOG Table 1 100 Pin LQFP Pin Identification of the eZ80F92 Device Continued Pin Symbol Function Signal Direction Description 27 ADDR22 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects 28 ADDR23 Address Bus Bidirectional Configured as an output in normal operation The address bus selects a location in memory or I O space to be read or written Configured as an input during bus acknowledge cycles Drives the Chip Select Wait State Generator block to generate Chip Selects 29 CS0 Chip Select 0 Output Active Low CSO Low indicates that an access is occurring in the defined CSO memory or I O address space 30 CS1 Chip Select 1 Output Active Low CS1 Low indicates that an access is occurring in the defined CS1 memory or I O address space 31 CS2 Chip Select 2 Output Active Low CS2
285. value is sampled by the system clock The input pin must be held at the selected interrupt level for a minimum of 2 clock periods to initiate an interrupt The interrupt request remains active as long as this condition is maintained at the external source GPIO Mode 9 The port pin is configured for single edge triggered interrupt mode The value in the Port x Data register determines if a positive or negative edge causes an inter rupt request A 0 in the Port x Data register bit sets the selected pin to generate an interrupt request for falling edges A 1 in the Port x Data register bit sets the selected pin to generate an interrupt request for rising edges The interrupt request remains active until a 1 is writ ten to the corresponding interrupt request of the Port x Data register bit Writing a 0 pro duces no effect on operation The programmer must set the Port x Data register before entering the edge triggered interrupt mode A simplified block diagram of a GPIO port pin is illustrated in Figure 5 PRELIMINARY General Purpose Input Output 43 eZ80F92 eZ80F93 Product Specification Llu ZiLOoOG GPIO Register Data Input System Clock Mode 1 Mode 4 Data Bus System Clock GPIO Register Data Output Mode 1 Mode 3 Figure 5 GPIO Port Pin Block Diagram GPIO Interrupts Each port pin can be used as an interrupt source Interrupts can be either level or edge triggered Level Triggered Interrupts When t
286. with the Isb set to 1 to signify a Read The IFLG bit should be cleared to 0 as a prompt for the transfer to continue When the 7 bit slave address or the first part of a 10 bit address and the Read bit are transmitted the IFLG bit is set and one of the status codes listed in IC Master Receive Status Codes is in the I2C SR register Table 82 I2C Master Receive Status Codes Code I7C State Microcontroller Response Next IC Action 40h Addr R For a 7 bit address Receive data byte transmitted ACK clear IFLG AAK 0 transmit NACK racave Or clear IFLG AAK 1 Receive data byte transmit ACK For a 10 bit address Transmit extended Write extended address address byte byte to DATA clear IFLG R Read bit that is the Isb is set to 1 PRELIMINARY I2C Serial I O Interface Table 82 I2C Master Receive Status Codes eZ80F92 eZ80F93 Product Specification VAR ZiLOG Code 48h I2C State Addr R transmitted ACK not received Microcontroller Response For a 7 bit address Next I2C Action Transmit repeated Set STA clear IFLG START Or set STP clear IFLG Transmit STOP Or set STA amp STP Transmit STOP then clear IFLG START For a 10 bit address Write extended address byte to DATA clear IFLG Transmit extended address byte 38h Arbitration lost Clear IFLG Return to idle Or set STA clear IFLG Transmit START when bus is free 68h Arbitration lost Clear IFL
287. ynchronous Receiver Transmitter eZ80F92 eZ80F93 Product Specification Zi ZiLOG Bit Position Value Description 6 SB Do not send a BREAK signal Send Break UART sends continuous zeroes on the transmit output from the next bit boundary The transmit data in the transmit shift register is ignored After forcing this bit High the TxD output is O only after the bit boundary is reached Just before forcing TxD to 0 the transmit FIFO is cleared Any new data written to the transmit FIFO during a break should be written only after the THRE bit of UARTx LSR register goes High This new data is transmitted after the UART recovers from the break After the break is removed the UART recovers from the break for the next BRG edge FPE Do not force a parity error Force a parity error When this bit and the party enable bit PEN are both 1 an incorrect parity bit is transmitted with the data byte EPS Use odd parity for transmit and receive The total number of 1 bits in the transmit data plus parity bit is odd Use as a SPACE bit in MULTIDROP mode See Parity Select Definition for Multidrop Communications for parity select definitions Use even parity for transmit and receive The total number of 1 bits in the transmit data plus parity bit is even Use as a MARK bit in MULTIDROP mode See Parity Select Definition for Multidrop Communications for parity select definitions PEN Parity bit tr

eZ80F92/eZ80F93 Product Specification

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