Meeting 5 (05/19/09)
Contents
1. ac bd ad bc The rules correspond to those of working with vectors in the plane The value j is a handy bookkeeping artifice Alternatively we can work in terms of polar coordinates z 2vi r 0 Zo zi doesn t fit in space available Zo Z1 rori 0o 01 Of course the above values can also be functions of time Doing DSP Workshop Summer 2009 Meeting 5 Page 47 56 Tuesday May 19 2009 Simply bandlimited waveforms Lowpass Negligible energy X f 0 for all f gt B Single sided bandwidth is B If sampled at f gt 2B can exactly reconstruct Bandpass Negligible energy outsize of a band B f f not containing 0 Hz If sampled at f 2B can exactly reconstruct This needs to be done very carefully not all fs and B values necessarily work easily Note that for bandpass waveforms this is not necessarily fs gt 2f Doing DSP Workshop Summer 2009 Meeting 5 Page 48 56 Tuesday May 19 2009 Frequency shifting Consider s t a t cos 27 fet 0 t ae eflemfet 00 e Jmfeteo Multiplying s t by e 7 4t gives s tye nfat 20 ez efte on ejm fart 001 2 The spectrum is shifted left by f4 Hz If it should happen that fa fc then sttje trit 20 feit2n000 4 g it m fees 2 If we can filter out the energy around 2 fe then stt e rft 8D o ione 2 Doing DSP Workshop Summer 2009 Meeting 5 Page 49 56 Tuesday May 19 2009 Uniform time quantization2. go out STD LOGIC ramp a out STD LOGIC VECTOR 11 downto 0 ramp b out STD LOGIC VECTOR 11 downto 0 clk in STD LOGIO end rampgen architecture Behavioral of rampgen is signal a ramp b ramp std logic vector 11 downto 0 signal counter std logic vector 5 downto 0 6 bits begin ramp a lt a ramp ramp b b ramp process clk is begin if rising edge clk then counter lt counter 1 if counter 0 then divides clock down by 64 go lt 0 a_ramp lt a_ramp 1 b_ramp lt b_ramp 3 else go lt 1 end if end if end process end Behavioral Doing DSP Workshop Summer 2009 Meeting 5 Page 13 56 Tuesday May 19 2009 DDS for DTMF tone generation An entity reads slide switches row column numbers and selects FTV values Set only one row and one column switch at a time An entity divides the 50 MHz clock down to 1 MHz Uses two phase accumulators to generate ROM addresses ROM contains 256 samples of one period of a sine wave A block ram was initialized using table values generated using a MATLAB script Doing DSP Workshop Summer 2009 Meeting 5 Page 14 56 Tuesday May 19 2009 DDSO DTMF project VHDL organization DDSOtop fetch FTV select row column FTV value sample clock generates 1 MHz update clock DDSO DDS phase accumulator DDS1 DDS phase accumulator sine table sine rom dual port pmod DA2 module DA2 driver VHDL 2 DACs per DA2 spartan3
3. Doing DSP Workshop Summer 2009 Meeting 5 Page 36 56 Tuesday May 19 2009 Continuous time spectra Fourier transform 00 X f x t e ftdt where lt f lt o 00 xt X fye ftaf where o t lt o Fourier series t2 On F x t e J nn 2 t dt where oo n lt o ti 00 x t Y cpe t n where to E tj TJi oo Some restrictions apply Doing DSP Workshop Summer 2009 Meeting 5 Page 37 56 Tuesday May 19 2009 Discrete Fourier Transform Discrete Fourier Transform N 1 X k Y x n e PTN wherek 0 1 2 N 1 n 0 1 N 1 x n M X k e N where m 0 1 2 N 1 k 0 z Do any restrictions apply One can move the 1 N around or even use 1 VN on both Doing DSP Workshop Summer 2009 Meeting 5 Page 38 56 Tuesday May 19 2009 The z transform The z transform of a discrete set of values x n lt n lt oo is defined as oo X z 3 x nz n o where is z complex valued z can be written in polar form as z rele r is the magnitude of z and 0 is the angle of z When r 1 z 1 is the unit circle in the z plane For causal waveforms that start at n 0 oo X z 3 x n z n 0 Doing DSP Workshop Summer 2009 Meeting 5 Page 39 56 Tuesday May 19 2009 The inverse z transform x n ZI X 2 ma fxea Some methods of computation gt Long division method gt P
4. Doing DSP Workshop Summer 2009 Meeting 5 Page 52 56 Tuesday May 19 2009 Where does the alias land Assume the base frequency range is f 2 lt f lt f5 2 For a frequency component at fe gt 0 find K such that RI lt fc Kfs lt fs 2 The energy at f aliases to fea fr K fs For a frequency component at fe lt 0 find K such that f 2zfoctEf f The energy at f aliases to fog fe Kfs We can use aliasing to shift frequencies to baseband Doing DSP Workshop Summer 2009 Meeting 5 Page 53 56 Tuesday May 19 2009 Aliasing demonstration Using Euler s relation we can write eden ft e sem ft cos 27 ft 5 5 The movies were generated using a input frequency sweeping from 0 Hz to 24 000 Hz in 30 seconds The sample frequency was 8 kHz The first movie demonstrates what happens when the cosine is sampled The second movie demonstrates what happens when only the positive frequency component is sampled Both movies show the effects of using a slowly increasing frequency linear FM sweep swept sinusoid Movie swept complex exponential Movie Doing DSP Workshop Summer 2009 Meeting 5 Page 54 56 Tuesday May 19 2009 Comments on sampling The spectrum of an sampled waveform does NOT fold Common practice is to make the base frequency range f 2 fs 2 The frequency f 2 is called the Nyquist frequency Given a real valued
5. 1 bit D A delta sigma modulator implementation at 0 Hz gt Single supply level shift op amp circuit Use drivers to do A D in to D A out Combine A D D A with delta sigma DAC v v Doing DSP Workshop Summer 2009 Meeting 5 Page 7 56 Tuesday May 19 2009 Exercise 3 focus Exercise 3 S3SB filter implementation gt Single stage of all pass filter Cascade of above gt Bit serial multiply and accumulate unit v Bit serial FIR filter implementation v Transfer function measurement New Subject to change Doing DSP Workshop Summer 2009 Meeting 5 Page 8 56 Tuesday May 19 2009 DACtestO Generates two ramps one per PMod D A for viewing on oscilloscope Top level connects the ramp generator with the D A driver A first simple practice test illustrating D A driver use Doing DSP Workshop Summer 2009 Meeting 5 Page 9 56 Tuesday May 19 2009 And the DA2 pins are The DA2 block diagram copied from the user s manual did not include actual pin numbers These are given below The DA2 input pins FPGA side are pin function SYNC DINA DINB SCLK GND vcc au WN FR The DA2 output pins Top side are pin function DACO output no connection DACI output no connection GND VCC au RWNH Doing DSP Workshop Summer 2009 Meeting 5 Page 10 56 Tuesday May 19 2009 PMod DA2 port description entity pmod dacO is Port go in STD LOGIC da a in STD LOGIC V
6. 31 56 Tuesday May 19 2009 Xilinx LogiCore Delta Sigma DAG Module Register Delta Sigma Sigma Interface DACin 8 oo 10 Adder Latch A SRL L 0 DACout FIFO ilis RESET CE READ EN CLR L 0 L 0 0 0 0 0 0 0 0 0 L 0 DAC Clk EN Figure 2 OPB Delta Sigma DAC Internal Block Diagram Essentially as the theoretical model but modified for use with positive valued data Simple RC lowpass filter used to remove the high frequency content Doing DSP Workshop Summer 2009 Meeting 5 Page 32 56 Tuesday May 19 2009 Comments gt Switching waveforms on the board gt Xilinx s sign extension and making subtractors into adders gt Wasn t able to make the alternative H z to work gt Design gives 8 effective bits resolution at output gt Encountered surprises The A D D A code allows use of an sample rate that is 1 MHz ora submultiple It is interesting to observe the output using 1 MHz asa function of input sine wave frequency and also using 1 255 MHz sample rate For 1 MHz sample rate my implementation works reasonably well up to about 400 Hz Doing a good delta sigma implementation or understanding why one can t would be a good one or two person project Doing DSP Workshop Summer 2009 Meeting 5 Page 33 56 Tuesday May 19 2009 Changing stride Next week s exercise will involve imp
7. PMod AD1 module in MIB J3 which is pmod b in the ucf file Sample rate is 1 MHz divided down by a factor set into the slide switches Can be used to investigate aliasing Set a relatively low sample rate and use a variable oscillator Oscillator frequencies around f 2 and fs are the most interesting A D and D A use the same clock v Doing DSP Workshop Summer 2009 Meeting 5 Page 23 56 Tuesday May 19 2009 A D D A top mostly pmod_ad1 lt pmod b connect PMod AD1 module pmod d lt pmod da2 connect PMod DA2 module reset 0 timing module entity work timing port map strobe strobe swt gt swt clk gt clk reset gt reset AD module entity work pmod adcO port map go gt strobe ad a gt ado ad_b gt adl pmod gt pmod_b clk gt clk40 DA module entity work pmod dac0 port map C go gt strobe da a gt ad0 da b gt adl pmod gt pmod da2 clk gt clk drive leds entity work led driver port map C sample gt ad0 leds gt led clk gt clk Doing DSP Workshop Summer 2009 Meeting 5 Page 24 56 Tuesday May 19 2009 Sample clock generator architecture Behavioral of timing is signal ctr std logic vector 13 downto 0 others signal count std Logic vector 13 downto 0 signal local strobe std logic begin strobe local strobe multiply switches by 50 to allow sampling fractio
8. We won t actually be using it however it is a very good read and if you have some uncommitted money it is a very worthwhile investment You can occasionally find it at Borders Of course there is always amazon com Lyons has also collected together a set of notes from the IEEE Digital Signal Processing Magazine into the book Streamlining Digital Signal Processing IEEE Press Wiley Interscience These are at a tutorial and applied level Highly recommended Doing DSP Workshop Summer 2009 Meeting 5 Page 4 56 Tuesday May 19 2009 Change of emphasis First three labs will focus on the Spartan 3 FPGA Second three labs will focus on the Piccolo A few MSP430 boards will be obtained for those who wish to investigate MSP430 No structured lab exercises are planned We are giving up breadth on three devices for additional depth on two Doing DSP Workshop Summer 2009 Meeting 5 Page 5 56 Tuesday May 19 2009 Exercise 1 focus Exercise 1 Spartan 3 Starter Board gt Introduce ISE and Impact gt Basic Spartan 3 Starter Board peripherals v VHDL hardware design language gt Constraint file interface between VHDL and FPGA pins gt Practice Doing DSP Workshop Summer 2009 Meeting 5 Page 6 56 Tuesday May 19 2009 Exercise 2 focus Exercise 2 S3SB Analog in analog out gt Use D A driver and DA2 to generate ramps gt Implement synthesizer to generate sine wave D A out v
9. amp reconstruction amplitude amplitude amplitude Doing DSP Workshop Summer 2009 Analog waveform FT S b ET 0 2 0 4 0 6 0 8 1 Time quantized waveform 0 2 0 4 0 6 0 8 Reconstructed time quantized waveford 10 de 0 2 0 4 0 6 0 8 T time in seconds 3 x 10 Meeting 5 Page 50 56 Analog waveform Time quantized Reconstructed Tuesday May 19 2009 Aliasing Sample the waveform cos 2Tt ft at rate fs t n fs Write f f where is integer and 0 lt A lt fy cos 2T fn fs cos 277na 217nA fy cos 2TnNA fy The sample values do not provide any information about the value of The sample values for a frequency an integer multiple of f from A are undistinguishable from the sample values when f A The word alias means known by another name When 0 the sample values are said to have been aliased The range of frequencies aliased to is generally taken to be fs 2 lt A lt fs 2 Doing DSP Workshop Summer 2009 Meeting 5 Page 51 56 Tuesday May 19 2009 Units for aliased frequency range Units typically used to describe aliased frequency range units range limits nomalized radians 277 T lt W lt T Hz fs fsl2 lt f lt fs 2 normalized Hz 1 1 2xf 1 2 Note the inclusion and non inclusion of the end points As practitioners we will make exclusive use of Hz
10. lowpass spectrum with bandwidth BW the sample frequency equal to 2BW is often called the Nyquist sample rate Reality gets in the way One should sample at a rate of at least two or three times the Nyquist rate not frequency Common sample rates standard telephone system wideband telecommunications home music CDs professional audio DVD Audio instrumentation RF video 8 kHz 16 kHz 44 1 kHz 48 kHz 192 kHz extremely fast Doing DSP Workshop Summer 2009 Meeting 5 Page 55 56 Tuesday May 19 2009 Some interesting audio frequencies Many waveforms can have energy beyond a band of interest Voice fundamental around 150 Hz overtones to about 5 kHz male fundamental about 120 Hz female fundamental about 200 Hz bass low E is 82 4 Hz soprano high C is 1 046 5 Hz Piano 27 5 Hz AO to 4816 Hz C8 Harmonics may extend frequencies by a factor of 3 to 5 or more Normal young adult hearing range is 20 Hz to 20 000 Hz Telephone nominally passes range 300 Hz to 3200 Hz Doing DSP Workshop Summer 2009 Meeting 5 Page 56 56 Tuesday May 19 2009
11. Behavioral of get FTV is constant rowl std logic vector 31 downto 0 X 00000000 constant row2 std logic vector 31 downto 0 X 00000000 constant row3 std logic vector 31 downto 0 X 00000000 constant row4 std logic vector 31 downto 0 X 00000000 constant coll std logic vector 31 downto 0 X 00000000 constant col2 std logic vector 31 downto 0 X 00000000 constant col3 std logic vector 31 downto 0 X 00000000 constant col4 std logic vector 31 downto 0 X 00000000 begin FTVO lt rowl when swt 7 downto 4 1000 else row2 when swt 7 downto 4 0100 else row3 when swt 7 downto 4 0010 else row4 when swt 7 downto 4 0001 else X 00000000 FTV1 coll when swt 3 downto 0 1000 else col2 when swt 3 downto 0 0100 else col3 when swt 3 downto 0 0010 else col4 when swt 3 downto 0 0001 else X 00000000 end Behavioral Doing DSP Workshop Summer 2009 Meeting 5 Page 18 56 Tuesday May 19 2009 Comments gt Determining the row and column values are part of the exercise gt The two tones could be combined after the DACs using a summing analog op amp gt Will combine ROM outputs digitally Need to worry about overflow when adding ROM output values together Easy step is to sign extend values by one bit then sum Doing DSP Workshop Summer 2009 Meeting 5 Page 19 56 Tuesday May 19 2009 sample clock generator entity fs clock is Port f
12. ECTOR 11 downto 0 da b in STD LOGIC VECTOR 11 downto 0 pmod out STD LOGIC VECTOR 3 downto 0 clk in STD LOGIC end pmod dac0 gt Leading edge of go copies contents of da a and da b into the two DACSs There is a latency of about 32 clock cycles gt da a and da b are unsigned 0 goes to 0 volts 4095 goes to Vec Set of four lines to be connected to PModD module gt Max clock is 60 MHz Counted down by a factor of 2 to clock data Typically use with 50 MHz or 40 MHz clock Module is assumed to be in MIB J7 which has name pmod d Doing DSP Workshop Summer 2009 Meeting 5 Page 11 56 Tuesday May 19 2009 DAC test 0 top entity DACtestOtop is Port pmod d out STD LOGIC VECTOR 3 downto 0 led out STD LOGIC VECTOR 7 downto 0 mclk in STD LOGIC end DACtestOtop architecture Behavioral of DACtestOtop is signal clk go std logic signal pmod std logic vector 3 downto 0 signal ramp a ramp b std logic vector 11 downto 0 begin pmod d pmod clk lt mclk led lt ramp_b 11 downto 4 dac entity work pmod dacO port map go gt go da a gt ramp a da b gt ramp b pmod gt pmod clk gt clk ramper entity work rampgen port map go gt go ramp_a gt ramp_a ramp_b gt ramp_b clk gt clk end Behavioral Doing DSP Workshop Summer 2009 Meeting 5 Page 12 56 Tuesday May 19 2009 The ramp generator counters entity rampgen is Port
13. Meeting 5 Summer 2009 Doing DSP Workshop Today Lab exercise 2 exercise VHDL gt Linear systems gt Transforms gt Aliasing Education is when you read the fine print Experience is what you get if you don t Pete Seeger Doing DSP Workshop Summer 2009 Meeting 5 Page 1 56 Tuesday May 19 2009 An option This Workshop can be used to get EECS 499 credit in the Fall This would be optional Five people have expressed an interest The Workshop does not have any homework exams nor any lab reports Grade would be based on a project Could be team effort Base credits would be 2 hours Could be fewer or more Details would need to be worked out As we work our way through the lab exercises give thought to project possibilities Would like to have a poster demo show and tell activity early in the fall term Would like credit and non credit projects to participate Doing DSP Workshop Summer 2009 Meeting 5 Page 2 56 Tuesday May 19 2009 Check out fpga4fun com The posters on display in the EECS atrium today and likely tomorrow They illustrate the type of research work being done in the department by students and faculty Doing DSP Workshop Summer 2009 Meeting 5 Page 3 56 Tuesday May 19 2009 Two very good Doing DSP books I ve added Richard Lyons book Understanding Digital Signal Processing 2nd edition to the non required book list on the Workshop web page Prentice Hall 2004
14. a Sigma D A converter block diagram yin Doing DSP Workshop Summer 2009 M digital lowpass filter ain yulni yeln yin L bit 0 AU DAC Ts Meeting 5 Page 28 56 E analog lowpass filter analog output Tuesday May 19 2009 Input to output TF Ye z Yw z H z E z Yq Z Ye z E z Yq Z Ye z From this of set of equations it is seen that the transfer function between Y 2 and Y4 z equals 1 Ya z Q 2 Y G E z Yq Z Yo z Ye z H 2z E z Doing DSP Workshop Summer 2009 Meeting 5 Page 29 56 Tuesday May 19 2009 Quantization noise to output TF Solving no Ma In many texts H z z I m not sure that this is what is used in practice For this H z we have E z 1 e J2nf fs giving E f 4 sin rcf fs Doing DSP Workshop Summer 2009 Meeting 5 Page 30 56 Tuesday May 19 2009 Two useful H z The system performance can be improved by replacing the single z stage by more sophisticated filter A filter that has a high pass transfer function will provide improved performance One that I found in an article has transfer function z 2 2 IE f I 15 d o 810 8 55 800 B 500 Frequency Hz Solid line is for H z z Dashed line is for H z z 1 2 z7 fr 1000 Doing DSP Workshop Summer 2009 Meeting 5 Page
15. artial fraction expansion method gt Use of residues See Proakis or a similar text or Wikipedia for details Doing DSP Workshop Summer 2009 Meeting 5 Page 40 56 Tuesday May 19 2009 Uniform sampling at rate f We can describes angles in the z plane as 0 21 f fs where f 2x f lt fs 2 Then oo X z x n f re Tn Hfs n 0 If we restrict ourselves to the unit circle then oo X z 2 Y x n f e Pris n 0 Why would we want to do so It s useful Doing DSP Workshop Summer 2009 Meeting 5 Page 41 56 Tuesday May 19 2009 Why use transforms The waveform y t obtained by processing a waveform x t by a LTIC system having impulse response h t can written as t y t x T h t T dt In terms of the transforms of x t h t and y t Y f HCDOXCP gt It is often easier to think of the effects of LTIC in the frequency domain than in the time domain gt It is sometimes easier to operate on a waveform in the transform domain than it is in the time domain In spite of the computational costs of going between domains Doing DSP Workshop Summer 2009 Meeting 5 Page 42 56 Tuesday May 19 2009 Discrete time transforms The z transform will be used to model filter transfer functions in the frequency domain The DFT will be used as a computational tool for implementing filters overlap and xxx algorithm and for visualizing spectra Doing DSP Workshop Summe
16. lementing a finite impulse response FIR filter and one or two infinite impulse response IIR filters Filters are typically characterized by their effect on sine waves at various filters Both the effect on amplitude and phase are generally of interest Before we start digging into filter theory we need to lay some ground work More and probably more lucid information is contained in the two books on the Workshop CD Doing DSP Workshop Summer 2009 Meeting 5 Page 34 56 Tuesday May 19 2009 Linear systems Given two time functions x t and x t and a function h system such that o1 t h x1 t and y2 t h xo t then the system is linear if and only if ay t by 2 h ax3 t bx t This leads to the principle of superposition We can decompose a signal into components solve for the responses to the individual components and then construct the overall response by adding up the individual responses Nonlinear systems are not easy to work with Doing DSP Workshop Summer 2009 Meeting 5 Page 35 56 Tuesday May 19 2009 Stable time invariant causal systems We say that a system is stable if for all bounded inputs the system s output is bounded We say that h is time invariant if for y t h x t we have y t T hlx t 7 We say that a system is causal if the output never precedes the input We will restrict our attention to linear stable time invariant causal systems
17. ns 50 3241642 no check included for swt 0 2207 of 1 MHz count lt 0 amp swt amp 00000 00 amp swt amp 0000 00000 amp swt amp 0 process clk begin if rising_edge clk then ctr lt ctr 1 local_strobe lt 0 if ctr 1 then ctr lt count local strobe lt 1 end if end if end process end Behavioral Doing DSP Workshop Summer 2009 Meeting 5 Page 25 56 Tuesday May 19 2009 Comments Need to be careful with the setting of the slide switches Value of 1 gives sample clock of 1 MHz Value of N gives sample clock of 1 N MHz Setting a low sample rate allows easy investigation of aliasing See what happen the signal generator frequency is in the vicinity of 1 2N MHz and when in the vicinity of 1 N MHz Doing DSP Workshop Summer 2009 Meeting 5 Page 26 56 Tuesday May 19 2009 One bit DAC Basic idea is to generate a pulse train whose average value varies with the amplitude of a series of digital inputs Then lowpass filter The resolution of the pulse widths will depend upon the clock rate and the register sizes used A delta sigma modulator is used to control the pulse sizes and transition times to minimize the low frequency noise to the detriment of the high frequency noise The high frequency noise is easily attenuated using a lowpass filter Doing DSP Workshop Summer 2009 Meeting 5 Page 27 56 Tuesday May 19 2009 Delt
18. r 2009 Meeting 5 Page 43 56 Tuesday May 19 2009 LTI system connections v hi0 gt vO xO gt no v xO gt no hO gt vO x gt mO0emo L o0 cascade connection v hx x O yo ho v x gt mO mO vo parallel connection Doing DSP Workshop Summer 2009 Meeting 5 Page 44 56 Tuesday May 19 2009 Waveform spectra A waveform s power distribution as a function of frequency A real valued waveform must have a spectrum that is conjugate symmetric around 0 Hz A imaginary valued waveform is not so restricted Obviously real valued waveforms exist only because imaginary valued waveforms exist pjenft e J nft For example cos 21r ft 5 5 Doing DSP Workshop Summer 2009 Meeting 5 Page 45 56 Tuesday May 19 2009 Delta functions 1 0 Kronecker delta function 6 n i 0 n 0 Dieeddhatmneion sees e 9 irac delta function x 0 x 0 where x dx 1 Sampling f x x a dx f a Use context to determine whether 6 is Kronecker or Dirac Doing DSP Workshop Summer 2009 Meeting 5 Page 46 56 Tuesday May 19 2009 A touch of reality A complex number z x jy where j 1 can be thought of as a number pair of reals z x y with well defined rules of manipulation For example for zo a b and z c d Zo Z a c b a Zo Z
19. s out STD LOGIC clk in STD LOGIC end fs clock architecture Behavioral of fs clock is signal counter std logic vector 5 downto 0 begin tic process clk begin if rising edge clk then counter counter 1 fs lt 0 if counter 0 then counter lt 110001 49 fs lt 1 end if end if end process end Behavioral Doing DSP Workshop Summer 2009 Meeting 5 Page 20 56 Tuesday May 19 2009 Basic DDS entity DDS is Port C FTV in STD LOGIC VECTOR 31 downto 0 ROM address out std logic vector 7 downto 0 fs in STD LOGIC clk in STD LOGIC reset in std logic end DDS architecture Behavioral of DDS is signal accumulator std logic vector 31 downto 0 begin ROM address lt accumulator 31 downto 24 top 8 bits process clk reset begin if reset 1 then elsif rising edge clk then if fs 1 then accumulator lt accumulator FTV end if end if end process end Behavioral Doing DSP Workshop Summer 2009 Meeting 5 Page 21 56 Tuesday May 19 2009 Completing the DTMF Need to add the two rom values Have to make sum one bit larger to allow for carry Have to sign extend the ROM values before adding sum lt sine a 15 amp sine a sine b 15 amp sine b Connect the top 8 bits of sum to one of the DACs Doing DSP Workshop Summer 2009 Meeting 5 Page 22 56 Tuesday May 19 2009 A D in to D A out v Place
20. ucf project specific UCF file Basically two simple DDS units with outputs combined at the top level Very brute force but very straight forward Doing DSP Workshop Summer 2009 Meeting 5 Page 15 56 Tuesday May 19 2009 Top level part 1 begin clk lt mclk fetch_ftv entity work get_ftv port map swt gt swt slide switches FTVO gt FTVO FTVO FTV1 gt FTV1 FIV1 clk gt clk reset gt 0 sample_clock entity fs_clock port map fs gt fs clk gt clk DDSO entity work DDS port map FTV gt FTVO FTV value to be used by DDS channel 0 ROM address gt address a fs gt fs clk gt clk reset gt 0 DDS1 entity work DDS port map FTV gt FTV1 FTV value to be used by DDS channel 1 ROM address gt address b fs gt fs clk gt clk reset gt 0 Doing DSP Workshop Summer 2009 Meeting 5 Page 16 56 Tuesday May 19 2009 Top level part 2 sine table a entity work sine rom port map C address a address a data a gt sine a address b gt address b data b sine b clk gt clk pmod DA2 module entity work pmod dacO port map da a gt sine a 15 downto 4 truncating da b gt sine b 15 downto 4 truncating go gt not fs pmod gt pmod d clk gt clk end Behavioral Doing DSP Workshop Summer 2009 Meeting 5 Page 17 56 Tuesday May 19 2009 Switches to FTV architecture
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