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NetFusion-EXP Development-Kit Guide PDF

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1. IRIE 8 EI Bl 5 e 25 SOM MSS 0 RC2A RC 4 z2 z8z 8 Fam SmartFusion2 Die M2S050T Pkg 484FBGA Verilog Figure 41 Customized RESET logic 78 research and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 14 BIBUF Throughout the NetFusion EXP starter project s fabric logic design is scattered around Bi Directional macros These convert conveniently any IN OUT data flow when the RX and TX are kept separate in the IP cores The output side always routes up out of the SmartFusion2 FPGA to the NetFusion EXP PCB hardware where the signals are capable of input output operation using pull up resistors combining tri state operation The instantiated BIBUFs are illustrated in the Figure below They are controlled coe an output enable See that drives the state of the output pin Re P i D E BIBUF 11 zh BIBUF FAD D E Y i 18 i LEE L4 Y c imr Gs EEN GC M kee FE Z III i SEA lt Figure 42 Bi Directional Fabric Macros for input output signals 79 research and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide 13 15 CoreSF2
2. 78 Figure 42 Bi Directional Fabric Macros for input output signals sse 79 Figure 43 APB feedback Bus for Peripheral Configuration by Gofiware 0000144 80 Figure 44 AMBA Memory Interfaces from ARM for an AXI bus 81 Figure 45 AMBA Memory Interfaces from ARM for AHB Lite bus 82 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 Figure 46 APB3 fixed bus UART GPIO IO EXP slots and Counter Peripherals 83 Figure 47 Editing the APB3 Core settings 33 83 Figure 48 Default AXI Configuration ccsccscsssccssssseosecssscosscsssecsscsssenssocssensscsssensscsssensenessensensesessensesensenens 84 Figure 49 Default AHB Lite Configuration essere enne nennen rennen enne 85 Figure 50 Default APB Configuration entere 86 Figure 51 SOM Module of the ARM ME 87 Figure 52 Exploded View of the Modules in the NetFusion EXP ARM MSS 88 Figure 53 MDDR MSS Controlling LPDDR Memory with AXI from 89 Figure 54 USB OTG UTMI Host Co
3. ennt nentes nnns sn nnns entren 40 4 20 CAN DUAL TRANSCEIVER a 40 4 21 DUAL HIROSE EXPANSION DAUGHTER CARD LO 40 5 EXPANSION I O 42 5 1 DAUGHTER CARD DES 43 5 2 GPIO HIROSE CONNECTORS eene nnnren ter inr sid ihres dr se SEEN innert erri nn nsn 43 cesi 43 5 4 POWER TEST 44 n gsicdl idiJuedme 44 5 6 EARTH PROTECTION 44 5 7 DAUGHTER CARD EXPANSION I O CONNECTORS 44 5 7 1 Connector SUMMA o cer ngu dm pd A 44 5 7 2 Customer IDC Outputs ONLY Connector 4 45 5 7 3 Customer IDC I O Connector J5 uei sementem 46 5 7 4 Customer IDC VO Connector JO sirene semen eiie einen ed dmn rnnt kd dpa nn 47 5 7 5 Customer IDC Inputs ONLY Connector 7 48 6 HARDWARE DEVICE DRIVER nennen tenni nnn intr nnns nnne nns 49 el KEE 50 8 NETFUSION EXP DEVELOPMENT KIT nennen nnne 51 9 DEMO APPLICATION mS 53 CAT5E ETHERNET CABLE amp 8 nennen nnn enne nennt tinte nn intr nnns nen
4. MR PADSEI MDCR DOS 0 OUT MOOR CAS H MIR AK N MDOR_CKE MDDR_CS_N MOOR ODT 1 EH GE MDER RAS MDDR RESET N Fam SmartFusion2 De 250507 Pkg 484FBGA Verilog Figure 51 SOM Module of the ARM MSS 87 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 14 NetFusion EXP ARM Cortex MSS Default Configuration 7 Libero CAMorethanipSmartFusion SC rilog Project File Edit View Design Tools SmartDesign mom of x 2 0 X Ef 25050 SOM FG484 amp X gm M25 SOM MSS 8 X 8 5 Mj So or OO RA D Pod MSS 1 1 209 Fam SmartFusion2 Die 25050 Pkg 484FBGA Verilog Figure 52 Exploded View of the Modules in the NetFusion EXP ARM MSS The MSS in the heart of the SmartFusion2 NetFusion EXP design is defaulted and set to the exact current needs of the PCB product Modules 2C1 12C2 GPIO RTC are disabled currently but there is
5. Although the APB3 core is used extensively this be extended to allow any user instantiated core to be connected by adding another slave line to the core This can be obtained by double clicking on the core and editing the settings fm Configuring CoreAHBLite 0 CoreAHBLite 5 0100 ee Configuration Memory space Memory space 256MB addressable space apportioned into 16 slave slots each of size 16MB Address range seen by slave connected to huge 258 slot interface 00000 000 OX7FFFFFFF 0 80000000 FI Allocate memory space to combined region slave Slot 0 Soti Slot 2 Slot 3 sot 4 slot 5 7 Sot7 Slots St9 Slot 10 E Slot 11 Slot 12 Slot 13 Slot 14 E Slot 15 Enable Master access can access slot 0 vi 1 can access slot 0 I M2 can access slot 0 M3 can access slot 0 can access slot 1 1 can access slot 1 o M2 can access slot 1 M3 access slot 1 MO can access slot 2 can access slot 2 2 access slot 2 Ir M3 can access slot 2 can access slot 3 access slot 3 M2 can access slot 3 M3 can access slot 3 can access slot 4 E 1 can access slot 4 M2 can access slot 4 M3 access slot 4 el can access slot 5 1 can access slot 5 2 can access slot 5 M3 can access slot 5
6. sow 5050_5 484 TOP 8 X 82002 c ele oL 2555 BS OB og Sg GE TE g ODES ak Ge WE 502 CoreAHBLite 6 Fw eo 2 BE 2 ea E 2 01 BS E lt gt H OU Y E To LE um TV EE CT EE II E Fam SmartFusion2 Die 250507 Pkg 484 Verilog Figure 45 AMBA Memory Interfaces from ARM for an AHB Lite bus 82 research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 18 Core APB3 The SOM sheet design has a useful APB3 core instantiated as CoreAPBS3 0 which is by default used to collate and connect various important cores to the ARM MSS memory map Currently the temperature sensor counter GPIO CoreGPIO 1 the main GPIO core CoreGPIO 0 the UART core CoreUARTapb 0 the two audio SPI cores CORESPI 0 1 the SPI baseboard device IC chip select logic CoreGPIO 2 and finally the GPIO for the EXP daughter card slots CoreGPIO 3 CoreGPIO 4 CoreGPIO 5 KS 85 6 P E Figure 46 APB3 fixed bus UART GPIO IO EXP slots and Counter Peripherals
7. 13 11 CoreSPIO 1 Running as separated IP cores instantiated in the fabric to achieve higher speed sampling by SPI software are SPI blocks These are 0 and 1 and use an APB interface to the ARM MSS sub system Each core has a 4 wire SPI bus routed out of the FPGA to the wider NetFusion EXP PCB hardware These SPI interfaces connect to DAC and ADC stereo IC devices This allows for audio to be sent and received from the PCB and the digital samples can be processed by the ARM processor from network traffic if necessary SPI is used as it is full duplex and runs at over 2 during operation However bottlenecks in the processor application code and also human audible hearing limitations keep realistic sampling operations around lt 10KHz emp 45 si 83 82 se SCH Figure 39 Stereo Audio Line IN amp Line OUT research and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 12 Temperature Sensor Glue Logic The baseboard temperature sensor IC is mounted under the Emcraft SOM daughter card and monitors the temperature of the FPGA that can often be demanded to perform high switching tasks in the fabric of the device The sensor produces an output square wave in which the frequency in Hz is equal to the degrees Kelvin on the baseboard This is routed into the FPGA and the fabric an
8. Eet Heger E ible WS bet ECT Filename networking uImage Loading aE EE HR EE FE FE FE E AE HH EH PE EEE E E RATER ERR RATER ER FE AE AE AE AE ERR BEEF AEE AE AE AE AE FE FEAE E done Bytes transferred 2084704 1fcf60 hex 16384 KiB S25FL1288 64K at 0 0 is now current device Saving Environment to SPI Flash Erasing SPI flash Writing to SPI flash done M2S SOM gt Reset the NetFusion baseboard and verify that the newly programmed image boots in the autoboot mode M2S SOM gt reset resetting Usboot 2010 0S 1inux cortexm 1 12 0 Dec U6 2013 17219337 Starting kernel Gbale JEE 2118255 0 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 3 5 1 Full uCLinux Documentation amp Software Development The above steps serve as a simple guide to try to successfully establish an uCLinux re compilation build and the upload via TFTP CAT5 network cable using u boot However this topic and documented material is fully covered and explained with all pit falls and extensive explanation in the NetFusion Software uCLinux Guide PDF available from the Nine Ways website research 9 and development
9. can access slot 6 E 1 can access slot 6 IF M2 can access slot 6 M3 can access slot 6 can access slot 7 access slot 7 2 access slot 7 M3 access slot 7 e a RE d Figure 47 Editing the APB3 core settings Please Note the previous AXI and AHB Lite cores can be edited and changed with exactly the same method by double clicking on the cores themselves 83 EM research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 19 AXI AHB Lite amp APB3 default Memory Mapped Settings ME Configuration zu r Memory space Memory space NEE Ez n A AXI data width r Enable master access can access slave slot 0 canaccessslaveslot i canaccessslaveslot2 canaccessslaveslot3 can access slave slot A access slave slot 5 J 0 can access slave dote D access slave slot 7 access slave slot8 can access slave slot 10 0 can access slave slot 12 can access slave slot 14 access slave slot9 J can access slave slot 11 can access slave slot 13 IT can access slave slot 15 Select AXI channel ID width Testbench License Hep 7 Figure
10. ADLIE BIBUF Bank TRISTATE None No IOEXP24 Inout 1VCMOS25 ADLIB BIBUF Bank TRISTATE None No 8 IOEXP25 Inout mm E ADLIE BIBUF Bank3 TRISTATE None No IOEXP26 Inout TTL Bl ADLIE BIBUF Banka TRISTATE None No 47 10EXP27 Inout LVTTL B2 vi ADLIB BIBUF Bank amp TRISTATE None No 48 28 Inout TTL ADLIE BIBUF Bank8 TRISTATE None No 49 10EXP29 Inout mm A2 ADLIB BIBUF Bank TRISTATE None No 50 IOEXP30 Inout mm Z ADLIB BIBUF Bank TRISTATE None No e e papa eeng LE E AMIRAIRE __ TRISTATF None No Ready Fam SmartFusion2 Die 25050 Pkg 484 FBGA Figure 23 Example of Top List I O Ball Assignments research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 VO Editor M25 S File Edit View Tools Help 275 PortName A Direction 1 0 Standard Pin Number Name I OstateinFlash Freeze mode Resistor Pull available Flash Freeze mode Schmitt Trigger Odt static OdtImp Ohm Low Power Exit InputDelay TRISTATE None No off off OTG_CLKOUT Input Inout Inout TRISTATE None off off TRISTATE None off off Off TRISTATE None off off off off off TRISTATE None TRISTATE None TRISTATE None off off TRISTATE None off off off off TRISTATE None TRISTATE None
11. NetFusion has two screw terminal DC power inlets and a single molded power receptacle They are electrically all in parallel but all have protection for differing voltages and overvoltage Moreover the polarity cannot be reversed so as to damage the baseboard either It is generally the case that the power receptacle is commonly used on the desk and during development The screw terminal header inlets are for the industrial deployment arena and maybe the NetFusion EXP is sharing power with other equipment or a party bespoke DC power supplies are used There are two screw terminal connectors in parallel to assist in the frequent and common installation practice of daisy chaining power together for multiple devices Moreover it can also be used if two power supplies are required to provide the current needed for NetFusion EXP on a demanding high bandwidth switching application All accidental reverse polarity connection attempts are diode protected along with over voltage transzorb clamp protection 33 Ss research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 All three inputs can accept a wide voltage range between 9V 36V DC The higher the voltage the lower the current sourced for the DC DC module on the underside of the NetFusion EXP Please Note standard 18V soap on a rope desk AC power supply is preferred for the receptacle inlet
12. Then to clean the demo application separate build system type linuxPC Project linux cortexm 1 xx x projects netfusion source sqlite cd linuxPC Project linux cortexm 1 xx x projects netfusion source cd demoapp linuxPC Project linux cortexm 1 xx x projects netfusion source demoapp make clean Then to clean the linuxptp separate build system type linuxPC Project linux cortexm 1 xx x projects netfusion source demoapp cd linuxPC Project linux cortexm 1 xx x projects netfusion source cd linuxptp linuxPC Project linux cortexm 1 xx x projects netfusion source linuxptp make clean Then to clean the iperf test application separate build system type linuxPC Project linux cortexm 1 xx x projects netfusion source linuxptp cd linuxPC Project linux cortexm 1 xx x projects netfusion source cd testapp linuxPC Project linux cortexm 1 xx x projects netfusion source testapp make clean Then make the full uCLinux build with NetFusion including the SQLite3 linuxptp testapp amp demo application binaries by typing linuxPC Project linux cortexm 1 xx x projects netfusion source testapp cd linuxPC Project linux cortexm 1 xx x projects netfusion source cd liuxPC Project linux cortexm 1 xx x projects netfusion make f all Alternatively make just the source directory files only type liuxPC Project linux cortexm 1 xx x projects netfusion make Finally prepare the newly
13. Press CTRL A Z for help on special keys BOOTP broadcast 2 Using usb_ether device TFTP from server 192 168 3 1 our IP address is 192 168 3 101 Filename u boot restore img Load address Ox807fffcO Loading HH HE IEEE HE IEEE III HIC IEEE IU VG 663 1 KiB s done Bytes transferred 362688 588c0 hex U Boot 2013 01 01 Jun 25 2013 14 56 10 ready 1 GiB WARNING Caches not enabled 256 MiB OMAP SD MMC OMAP SD MMC 1 Using default environment musb hdrc ConfigData Oxde UTMI 8 dyn FIFOs bulk combine bulk split Rx HB ISO Tx SoftConn hdrc MHDRC RTL version 2 0 musb hdrc setup fifo mode 4 musb hdrc 28 31 max ep 16384 16384 memory USB Peripheral mode controller at 47401000 using PIO IRQ 0 musb hdrc ConfigData Oxde UTMI 8 dyn FIFOs bulk combine bulk split HB ISO Figure 13 An Example of a terminal screen connected through USB UART to Cortex M3 uCLinux 4 2 2 Ethernet Interface The RJ45 Etherent port is wired directly through the SOM connectors to the SOM on board PHY and dedicated MAC to the MSS for the ARM processor The maximum speed of this port is 100Mbit s This is due to the PHY on the SOM and the usage of only an MII 25MHz interface into the SmartFusion2 FPGA embedded MSS MAC By default it is used as a means to allow re compiled uCLinux kernels and application code to be programmed into the SPI FLASH memory using TFTP The commands are initiated using the USB UART interface abov
14. 96 15 2 INSTANTIATING INTO THE FARRI essen 97 15 2 1 Building and Synthesizing the NetFusion EXP Design 98 16 USING FLASHPRO4 IDE TO PROGRAM 100 17 MEER 103 18 ENVIRONMENTAL SPECIFICATIONS 105 19 CONTAC 106 20 DOCUMENT HISTORY irent taris ran nette tart 107 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 List of Figures Figure 1 Power Connector Options ccccssccssccsscosscsssenssosssensecessentecsssenseosssentecssensecesenseressensensesensensesensenens 15 Figure 2 Desk Mains Power Connected to Receptacle 2 16 Figure Screw Terminal Power 17 Figure 4 Microsemi FlashPro4 USB JTAG Programming sese 18 Figure 5 USB Cable Connected to the USB UART Interface from 19 Figure 6 Example of opening PUTTY in Windows 7 sse enne enne nnne 20 Figure 7 An example on Ubuntu Linux of the Terminal being launched 20 Figure 8 Screen shot of a User entering into the u boot screen o
15. NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 4 NetFusion EXP Hardware PCB 4 1 1 Net Fusion EXP Baseboard Block Diagram EXP Connectors J27 J31 SOM Connectors J12 J13 JTAG VF ULPI USB USB UART J26 J28 PHY U26 Bridge U33 Reset Button 51 Debug Reset emm P Supervisor U15 ower Distribution 3 5V routed to 10 100 Ethernet rail a D all components that require relevant SOM has 3 3V 5V generated external utput supplied to connector 45V Out EXP ADC DAC SPI UB U11 2x DB9 has seperate 3 3V 5V 2xCAN Male DualCAN Transiver 2 5V Voltage Input 1 2 V 037 157 Bus AMIS 42770 2x Peripheral U13 Header 135 J56 USB OTG I F JP1 USB Host amp UART Nl MA E USB Device F LCD Header U17 J17 JP2 UO LCD Buttons 84 55 S6 09 U12 U19 Voltage Free Solid State amp Coiled Relays U2 U7 RL1 RL2 8 x Analogue Contact Inputs U1 GPIO U14 Earth Protection LIII Peripheral Connectors 71 28 J10 J11 J15 J16 J19 J29 U16 u20 U21 DC In Vert J30 J32 Figure 10 Block Diagram Architecture of the NetFusion EXP main board PCB 27 Peripheral User Interface DC Power Inlet research 9 and development eo NINE WAYS NetFusion EXP Ether
16. Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 10 2 Installation Libero software is downloadable for free from http www microsemi com products fpga soc designresources design software libero soc downloads Some Libero features are optional during installation You can minimize the disk space required by only installing tools you use You must have a license to run Libero the license type that you obtain determines what devices you can use and what IP is included The following license types exist for Libero Libero Platinum All devices and RTL IP Bundle Libero Gold Limited devices and Obfuscated IP Bundle View the complete descriptions of the above Libero installations at http www microsemi com products fpga soc design resources design software libero soc licensing View the IP Bundle contents at http www microsemi com products fpga soc design resources ip cores Libero installation is covered in Installing Libero Software on page 16 Note You must have Admin rights on the installation machine to install Libero SoC 10 3 Starting a Project and Basic Understanding Before attempting to modify or implement any project in Libero it is advised that you download and read the following PDF references System on Chip installation Libero SoC v11 X User s Guide Libero SoC Quick Start Guide for Software v10 0 Integrated Development Environment installation Libero IDE and Software Installation
17. FPGAs Antifuse FPGAs and Legacy amp Discontinued Flash FPGAs and managing the entire design flow from design entry synthesis and simulation through place and route timing and power analysis PCN 1108 Silicon Family Support in Libero IDE Libero IDE Software Features e Powerful project and design flow management e Full suite of integrated design entry tools and methodologies e SmartDesign graphical SoC design creation with automatic abstraction to HDL e P Core Catalog and configuration e User defined block creation flow for design re use e Synplify Pro ME synthesis fully optimizes Microsemi FPGA device performance and area utilization Synphony Model Compiler ME performs high level synthesis optimizations within a Simulink environment e Modelsim ME VHDL or Verilog behavioral post synthesis and post layout simulation capability e Physical design implementation floor planning physical constraints and layout e Timing driven and power driven place and route e SmartTime environment for timing constraint management and analysis SmartPower provides comprehensive power analysis for actual and what if power scenarios Interface to FlashPro programmers e Post route On Chip Debug Tools and Identify ME debugging software for Microsemi flash designs e Silicon Explorer debugging software for Microsemi antifuse designs iol 56 SC research 9 and development Ki NINE WAYS NetFusion EXP
18. MSS to FPGA Fabric Reset MSS RESET M2F Iv e 2 Figure 57 Reset MSS Module NetFusion EXP by default enables the MSS RESET F2M RESET N and the MSS RESET M2F negative reset signals to come in from the SmartFusion2 FPGA fabric This gives more functionality to the user However if it is not a required functionality when the design is customized then they can be de selected iol 92 NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 14 7 FIC 0 Mss Fabric Interface Controller FIC 0 Configurator MSS To FPGA Fabric Interface Interface Type Use Slave Interface r r Advanced AHBLite Options Use Bypass Mode AHBLite only Expose Master Identity Port 7 FPGA Fabric Address Regions MSS Master View FIC32 0 FIC32_1 Fabric Region D 0 30000000 Ox3FFFFFFF Fabric Region 1 0 50000000 Ox5FFFFFFF EE e Figure 58 AHB APB Fabric Interface 1 The NetFusion EXP FIC 0 has been chosen to be assigned for the AHB Lite fabric interface It is a MASTER which connects to the SLAVES in the fabric as the ARM processor has complete control By default the AHB Lite only interfaces to the AMBA DMA Controller used for 3rd party Ethernet IP cores Although the DMA Controller uses AXI for the main data throughput the AHB Lite is used to access the configuration registers Note you will observe t
19. None off None None None off amp 8 8 8 8 8 8 8 8 8 8 8 8 88 None None off None off None None off None off None off None None off SERERE E E UE EE EE EE EE E EE E None off None JOBILCOHDOPDBHODBEBBCBECILIELIIEEBDSEE Inout Inout Inout Inout Inout Inout Input Input Output Output Input Output Inout Input Output Inout Inout Input Output Inout Input Output Input Pins Package Viewer J SmartFusion2 De M2S050T Pkg 484 FBGA Figure 24 Example of Bottom List I O Ball Assignments The I O assignment dialog is selected from the I O Constraints anchor in Place and Route section below constraint 25 SOM FG484 TOP designer G constraintM25 SOM FG484 TOP synthesis g Floorplan Constraints Implement Design nthesize Ay synplify log Ay M25 SOM srr run options txt E 2 Compile f M2S SOM rwnetlist log b Post Synthesis Implementation M2S SOM compil Bl Simulate M25 SOM compilexml Compile M2S_SOM_combinatio 21 Configure Flash Freeze Place and Route Place and Route 25 SOM gp report Generate Programmin PE VO Constraints M2S_SOM_generatePr Timing Constraints Ay Run PROGRAM Action Floorplan Constraints A 25 SOM PROGR 4 b Verify Post Layout Implementation 1 Generate Ba
20. O SmartFusion2 050 F484 ball F21 bank 1 20 GND POWER OV Chassis Ground research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 5 7 5 Customer IDC Inputs ONLY Connector J7 Table 7 IDC Connector J7 Customer Interface Pin Signal Type NetFusion Usage 1 3 3V POWER Separately generated 3 3V 9 IOEXP23 Input SmartFusion2 050 F484 ball P6 bank 7 3 IOEXP22 Input SmartFusion2 050 F484 ball M5 bank 7 4 IOEXP21 Input SmartFusion2 050 F484 ball K5 bank 7 5 IOEXP20 Input SmartFusion2 050 F484 ball N6 bank 7 6 IOEXP19 Input SmartFusion2 050 F484 ball K4 bank 7 7 IOEXP18 Input SmartFusion2 050 F484 ball N5 bank 7 8 IOEXP17 Input SmartFusion2 050 F484 ball L5 bank 7 9 IOEXP16 Input SmartFusion2 050 F484 ball L3 bank 7 10 IOEXP15 Input SmartFusion2 050 F484 ball 14 bank 7 11 IOEXP14 Input SmartFusion2 050 F484 ball 12 bank 7 12 IOEXP13 Input SmartFusion2 050 F484 ball M3 bank 7 13 IOEXP12 Input SmartFusion2 050 F484 ball P4 bank 7 14 IOEXP11 Input SmartFusion2 050 F484 ball M4 bank 7 15 IOEXP10 Input SmartFusion2 050 F484 ball N3 bank 7 16 IOEXP9 Input SmartFusion2 050 F484 ball N4 bank 7 17 IOEXP8 Input SmartFusion2 050 F484 ball P3 bank 7 18 IOEXP7 Input SmartFusion2 050 F484 ball P2 bank 7 19 IOEXP6 Input SmartFusion2 050 F484 ball R1 bank 7 20 GND POWER OV Chas
21. RCOSC 1MHZ osc_comps v 25050 SOM FG484 TOP Eg 25 EN M2S_SOM_COREAXI_0_COREAXI cor CoreGPIO coregpio v A CoreSF2Config coresf2config v CoreSF2Reset coresf2reset v H CORESPI corespi v Eh M25 SOM CoreUARTapb 0 CoreUAR 2 M Set As Root Instantiate in 25 SOM WEI mt Open HDL File v h CheckHDL File Gel un Cc fy Edit Core Definition E COREAHBLITE Remove Core Definition H K COREAPB3_LIE COREAXI_OBF Delete from Project 5 Delete from Disk and Project Create I O Constraint from Module Properties Figure 62 Instantiating an Imported IP Core in your Fabric Design Whether you wish to instantiate into the SmartFusion2 fabric an imported 3rd party source code core from VHDL Verilog or it is from the vault downloaded from ACTEL the process to get the core into the design sheets is the same and relatively simple Even if the core is a macro as part of the ASIC area of the FPGA the process is the same no matter what area of the design it involves Simply move the left panel to select Design Hierarchy and then right click on the listed core of your choice Select Instantiate in M2S SOM or whichever sheet is displayed on the right pane of Libero IDE The core will appear in the design for you to move and anchor ready for connection routing Note f the core has errors the error report page will appear and
22. What connection topologies does NetFusion support As uCLinux is the native processor OS with NetFusion all STP RSTP SNMP ICMP can be used This will allow for a meshed multi route system with bridge protocol packets flowing around a NetFusion EXP connected Ethernet network Is a Web server in each NetFusion EXP the only way to access or change its configuration No A user can access via SSH USB UART serial port LCD display with buttons telnet or a range of other proprietary network protocols 5 V 103 research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 What are the temperature limits for a NetFusion EXP system It confirms to Industrial Temperature Ranges Specifically that is 40 to 85 degrees Celsius What is the maximum serial speed of communication on the serial ports 230 400 baud What is the reason for two CAN buses support from the dual transceiver Although there is only a single CAN Controller in the SmartFusion2 MSS using GPIO strobe control the ARM application uCLinux software applications can select different buses This is application specific and only a user would know why they would want to use two separate buses However it is provided to allow for greater flexibility and support for customers and users to develop with and deploy if needed What is the simplest work needed to get a
23. all NetFusion EXP Development Kit products the firmware code is shipped with an LCD demonstration application This demonstrates most of the hardware and board without having to compile or install any IDEs Once the user has installed all of the uCLinux cross compile tools they can remove the demonstration application from the LCD by commenting out the demoapp entry in the local rc control boot script file It is ideal for an out of the box play and familiarization with the features and functions of the NetFusion EXP product Eventually the user will want to cut this out of the boot up script file once the user wants to progress For information on how to operate and use the LCD demo please refer to the Demonstration Application Guide PDF iol 53 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 CAT5e Ethernet Cable amp Connectors CAT5e cable connections should be made using RJ45 plugs To comply with NetFusion EXP s temperature range requirements all cables and connectors must be specified to industrial standard with an operating temperature range of 40 C to 85 C The maximum length of CAT5 6e connections specified in this document is 100m To operate reliably over distances close to this limit high quality cables and connectors should always be used If the location of the cable is subject to large amount of e
24. and terminates at unused block 0 91 research development eo NINE WAYS Fusion NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 14 5 MSS_CCC Clock Source CLK BASE 83 000 MHz I Monitor FPGA Fabric PLL Lock CLK BASE PL LOCK Cortex M3 and MSS Main Clock M3 166 MHz 166 000 MHz MSS CCC MDDR Clocks v MDDR CLK M3_CLK 1 z 166 000 MHz M SMC FIC MOER 2 83 000 55 0 1 Sub busses Clocks 0 CLK M3 _CLK 2 83 000 MHz v APB 1 M3ak zl 83 000 MHz FPGA Fabric Interface Clocks FIC 0 CLK 2 83 000 MHz v 2 zl 83 000 MHz ee MUNDI Figure 56 MSS CCC Divider from the CLK BASE with in ARM Sub System The main 166MHz clock into the MSS from the fabric is configured to be split up and if necessary divided down to the different areas of the sub system It is derived from the Div 2 83MHz from the PLL in the fabric In the case of NetFusion EXP and the Starter Pack Libero 11 X IDE project all peripherals memory controllers and fabric interfaces run at half the base clock frequency at 83MHz 14 6 RESET Controller RESET MSS_RESET 1 0 100 Configuration Enable FPGA Fabric to MSS Reset MSS RESET F2M Iv Enable FPGA Fabric to Reset M3 RESET Enable
25. as this is the most optimum voltage for noise reduction for these types of supplies Figure 16 A Standard typical 18V DC Desk Mains Supply 4 6 Reset Button The main reset button on the NetFusion EXP board controls the reset sequence across the hardware By pressing and releasing an IP core in the FPGA fabric initiates a wave of reset flow that accurately brings up the Cortex M3 FPGA fabric SOM hardware and the NetFusion baseboard devices There is no ability to distinguish different desirable resets It s the whole environment as one You cannot just reset the Cortex M3 only for instance and also want to independently reset other parts of the hardware on different occasions The reason for this is there is only one reset button and trace line routed into the SOM then into the SmartFusion2 FPGA A solution to having NetFusion EXP provide multiple reset signals is to use some of the available hardware on the baseboard For instance using the LCD buttons and re wiring the connection inside the FPGA fabric using Libero IDE Moreover allowing the software to control output GPIO that is then re wired in the fabric 4 7 Generic Option Switches and Configuration Dials Use the option switches and the rotary switches to control and bootstrap your firmware application code of these signals are routed to the GPIO core inside the SmartFusion2 FPGA fabric which is memory addressable from the ARM Cortex M3 processor This enables softwar
26. illustrations and instructions as this is written to test on an Emcraft Development Kit board However the principles are the same and the instructions on how to launch and test end to end connectivity do not differ 2 6 Relevant References As additional help and support of the Software and the uCLinux environment please consider the following resources Visit Emcraft s web site at www emcraft com to obtain additional materials related to Linux Cortex M Emcraft Systems provides detailed kit information and materials from this page http www emcraft com som m2s As new SmartFusion2 and kit related materials become available they will be posted on the Microsemi and Emcraft Systems web sites Microsemi recommends that you sign up for Product Updates to be notified when new material is available Microsemi product updates https www actel com portal default aspx r 2 Emcraft Systems product updates http www emcraft com som m2s register Refer to Emcraft Systems SmartFusion2 SOM System On Module Hardware Architecture for detailed information on the hardware architecture of the Emcraft Systems SmartFusion2 SOM board Refer to Emcraft Systems SOM BSB EXT Baseboard Hardware Architecture for detailed information on the hardware architecture of the Emcraft Systems SOM BSB EXT baseboard NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 Refer to Linux Cortex M User s Manual for detailed i
27. simple working system Open the box attached power supply power up attached USB cable to the USB UART open putty or a PC terminal plug in CAT5 6e cable into the RJ45 Ethernet port and link to your PC press the reset button on NetFusion EXP set u boot IP settings use u boot to download new Linux code reboot execute fe V 104 research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 18 Environmental Specifications e Power Supply 110 240V AC 50 60Hz Desk Supply 31W ideally with 18V DC output connected to 9 36V wide range Power Receptacle e Screw Terminal Alternative Supply Connectors 9 36V DC with maximum current consumption 1500mA e Max Power Consumption of Worst Case Operation 15W e Operating Temperature Range Industrial 40 C to 85 C degrees e EMC EMI BSEN 61000 6 2 2001 USA FCC Part 15 2011 Non weatherproof deployed enclosures must be located inside in an IP65 compliant box for industrially mounted situations e NetFusion EXP PCB uses Lead free ROHS and WEEE compliant materials e PCB Dimensions 170mm x 170mm x 1 8mm e Weight Fully populated with LCD screen amp SOM F484 System On Module 1 4kg iol 105 OQ research and development NINE WAYS F FUSIOn NetFusion EXP Ethernet SWITCH Development Kit Reference Guide 19 C
28. 1 lt lt o OR20 OO ree de ECP Li Fg LESTLE PT err ttt tf ERERSS ERE Fam SmartFusion2 Die 250507 Pkg 484FBGA Verilog Figure 37 CAN Controller Interface Logic research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 10 CoreUARTapb As there is no way in the SmartFusion2 ARM MSS block for standard UART connections dev ttySO and dev ttyS1 already used the RS484 PCB hardware has to be controlled and handled from a fabric UART core This was instantiated as CoreUARTabp 0 and has an APB connection to the MSS block The uClinux device driver for this hardware access the core as a block of memory and the FIFO RX and TX data is stored in the fabric core The RX ad TX signals to the NetFusion EXP PCB hardware are TTL levels and then get converted to RS485 voltage signals in the electronics Libero C Morethanip SmartFusion SON Fus Project File Edit View Design Tools SmartDesign Help Mao Ce 25 sod x El wasoso sow rese ax B 22292052 64 6 Fam SmartFusion2 De 25050 Pkg 484FBGA Verilog Figure 38 RS485 UART IP core research and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015
29. 1 0 July 2015 3 3 4 JTAG Programming With the on board PCB JTAG programming mode LINK removed and not present the SmartFusion2 FPGA on the SOM will accept normal JTAG programming validation and verification This is all controlled using the FlashPro IDE from Microsemi or the FlashPro embedded in Libero SoC IDE Figure 4 Microsemi FlashPro4 USB JTAG Programming Firstly check that the two Red LED power indicators are illuminated on the NetFusion EXP PCB With the JTAG programming mode LINK removed plug in the USB programmer as shown above Using the Microsemi IDE application program your IP fabric and eNVM u boot image Note for Libero IDE FlashPro4 amp uCLinux compilation please see the other NetFusion EXP PDF guides Once the Microsemi IDE has signaled that the programming operation was successful and completed you can optionally remove the JTAG ribbon cable from the header on the PCB You must remove and then re apply the DC power Once the power is restored and the NetFusion EXP System On Module s SmartFusion2 FPGA is operating and the Cortex M3 is launching the eNVM RAM u boot progress to the following sub section below 18 NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 3 3 5 USB UART Terminal As the SOM s Cortex M3 processor embedded inside the SmartFusion2 FPGA begins to boot up the debug and process can be observed using the USB UART interfa
30. 13 Dual high speed CAN transceiver This transceiver then connects to the fabric in the FPGA on the SOM via tracks to Hirose connectors J12 J13 4 21 Dual Hirose Expansion Daughter Card Slot Two Hirose DF40 connectors J27 J31 along with for fixing support holes and a cleared non populated area of the NetFusion EXP baseboard allow for daughter card expansion PCBs to be affixed There is one standard GPIO daughter card that is available from Nine Ways R amp D and provides just basic I O access with Zener diode protection However a customer user can develop bespoke daughter cards The Altium PCB starter design is available from the Nine Ways website in the NetFusion product section This allows the user to start with the correct board shape and Hirose connector positions and reduces the time for development and lowers the risk of first time mistakes in the design process Earlier in this document tables show the pin out usages of the Hirose expansion slots connectors but the Altium starter design and the availability of the standard I O Nine Ways daughter card PCB are available from the NetFusion product page at nineways co uk iol 40 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 The connectors are 80 pin 0 4mm pitch receptacles providing 4mm stacking height implying that the daughter board may fit low on the base board PCB or on the unders
31. 16 IOEXP68 Output SmartFusion2 050 F484 ball K20 bank 3 17 IOEXP69 Output SmartFusion2 050 F484 ball K21 bank 3 18 IOEXP71 Output SmartFusion2 050 F484 ball E22 bank 1 19 IOEXP65 Output SmartFusion2 050 F484 ball F20 bank 1 20 GND POWER OV Chassis Ground 45 do research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 5 7 3 Customer IDC I O Connector J5 Table 5 IDC Connector J5 Customer Interface Pin Signal Type NetFusion Usage 1 3 3V POWER Separately generated 3 3V 2 IOEXP1 I O SmartFusion2 050 F484 ball K7 bank 7 3 IOEXP2 I O SmartFusion2 050 F484 ball K2 bank 7 4 IOEXP3 I O SmartFusion2 050 F484 ball M1 bank 7 5 I O SmartFusion2 050 F484 ball N1 bank 7 6 5 I O SmartFusion2 050 F484 ball P1 bank 7 7 IOEXP25 I O SmartFusion2 050 F484 ball K18 bank 3 8 IOEXP26 I O SmartFusion2 050 F484 ball B1 bank 8 9 IOEXP27 I O SmartFusion2 050 F484 ball B2 bank 8 10 IOEXP28 I O SmartFusion2 050 F484 ball C3 bank 8 11 IOEXP29 I O SmartFusion2 050 F484 ball A2 bank 8 12 IOEXP30 I O SmartFusion2 050 F484 ball C4 bank 8 13 IOEXP31 I O SmartFusion2 050 F484 ball F5 bank 8 14 IOEXP32 I O SmartFusion2 050 F484 ball E4 bank 8 15 IOEXP33 I O SmartFusion2 050 F484 ball D4 bank 8 16 IOEXP34 I O SmartFusion2 050 F484 ball F5 bank 8 17 IOEXP36 I O SmartFusion2 0
32. 18 3 3 5 USB UART Ma rae a den ad Ea Maden pad dd 19 3 4 CONNECTING A 5 CABLE FOR TFTP 22 3 5 BUILDING THE NETFUSION CUSTOMIZED UCLINUX KERNEL essen enne nnns 22 3 5 1 Building the SQLite linuxptp testapp amp demo application incrementally 24 3 5 2 Building the main uCLinux with NetFusion Incrementally 24 3 5 3 Uploading the kernel to the Nett usion ssseseessesesrneessnnssesnnaassnnaaennnnasannaannnnaanannaatnnnnanannaane 25 3 5 1 Full uCLinux Documentation amp Software Development 26 4 NETFUSION EXP HARDWARE 2 24222 42 nn 27 4 1 1 Net Fusion EXP Baseboard Block 27 4 2 COMPONENT DESCRIPTION DETAILS 29 4 2 1 USB UART Interface cii eei to redet p ht ud pa hk gud eni gua dL Pa NUR e 29 4 2 2 Ethernet Interface re rre es ERRORES 30 4 1 222 d aeta ane agde oon 31 4 2 FLASHPRO JTAG INTERFACE ode adea Sie FU es e dua 31 4 3 CARMI STAG INTERFACE dao desta od ee aha gt ed Fea ewe stude Leda eu Hd 32 44 BNC CONX S OG
33. 48 Default AXI Configuration 84 research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 E Configuring CoreAHBLite 0 CoreAHBLite 5 0 100 Configuration r Memory space Address range seen by slave connected to huge 2GB slot interface 0 00000000 OX7FFFFFET 0 80000000 Allocate memory space to combined region slave Sto Slot 2 Slot 3 Slot 4 Slot6 Slot 7 Slots Slot 10 Slot 11 Slot 12 Slot 14 Slot 15 Enable Master access 0 can access slot 0 access slot 0 2 can access slot 0 M3 can access slot 0 0 can access slot 1 access slot 1 M2 can access slot 1 M3 can access slot 1 can access slot 2 access slot 2 2 can access slot 2 M3 can access slot 2 0 can access slot 3 M1 access slot 3 M2 can access slot 3 M3 can access slot 3 can access slot 4 can access slot 4 M2 can access slot 4 M3 can access slot 4 Lee 7 Figure 49 Default AHB Lite Configuration 85 research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 EI Configuring CoreAPB3 0 CoreAPB3 Configuration Data Widt
34. 50 F484 ball G6 bank 8 18 IOEXP38 I O SmartFusion2 050 F484 ball F6 bank 8 19 IOEXP40 I O SmartFusion2 050 F484 ball G7 bank 8 20 GND POWER OV Chassis Ground research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 5 7 4 Customer IDC I O Connector J6 Table 6 IDC Connector J6 Customer Interface Pin Signal Type NetFusion Usage 1 3 3V POWER Separately generated 3 3V 2 IOEXP46 I O SmartFusion2 050 F484 ball K7 bank 8 3 IOEXP48 I O SmartFusion2 050 F484 ball K6 bank 8 4 IOEXP49 I O SmartFusion2 050 F484 ball H6 bank 8 5 IOEXP50 I O SmartFusion2 050 F484 ball K15 bank 3 6 IOEXP51 I O SmartFusion2 050 F484 ball 116 bank 3 7 IOEXP52 I O SmartFusion2 050 F484 ball P16 bank 3 8 IOEXP53 1 0 SmartFusion2 050 F484 ball R16 bank 3 9 IOEXP54 I O SmartFusion2 050 F484 ball H16 bank 3 10 IOEXP55 I O SmartFusion2 050 F484 ball N16 bank 3 11 IOEXP56 I O SmartFusion2 050 F484 ball P18 bank 3 12 IOEXP57 I O SmartFusion2 050 F484 ball K17 bank 3 13 IOEXP58 I O SmartFusion2 050 F484 ball F18 bank 1 14 IOEXP59 I O SmartFusion2 050 F484 ball F19 bank 1 15 IOEXP60 I O SmartFusion2 050 F484 ball L18 bank 1 16 IOEXP61 I O SmartFusion2 050 F484 ball L19 bank 3 17 IOEXP62 I O SmartFusion2 050 F484 ball G19 bank 1 18 IOEXP63 I O SmartFusion2 050 F484 ball H20 bank 1 19 IOEXP67 I
35. 73Hz is freezing point of water and 373Hz is 100 Celsius and this relationship continues uniformly theoretically with in the operating limits of the industrial temperature range The output trace from this device routes into the SmartFusion2 FPGA fabric where a counter allows user software to address how many cycles per second is occurring From this the UIO temperature device driver can interface with user application programs 4 11 Voltage Monitor This device does not appear as a connector on the NetFusion EXP baseboard In fact it is an on board component that checks and monitors the state of the PCB An 2 device allows most of the power rails to feed in as inputs and an analogue reading is taken software UIO device driver reads the values over I2C and applies simple mathematics to allow the voltages to be revealed to the customer user application programs This can be used by the user customer to check for malfunction or sever over voltage conditions and send warnings to a control station for instance iol 36 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 4 12 Real Time Clock Although the SmartFusion2 FPGA has an in built clock timer module in the MSS surviving power down and maintaining good accuracy are not guaranteed Therefore NetFusion EXP has incorporated a battery backed up Real Time Clock RTC funct
36. 95 88958589 o Vt 1 S5 9 05 00 09 P 25 E EH lt S 59 553 B5 838858899252 52222955 222 Bi Zi esgeanegeg 8565005 i utat 2 WE 58 5 Fam SmartFusion2 De 25050 Pkg 484FBGA Verilog Figure 44 AMBA Memory Interfaces from ARM for an AXI bus research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 17 Core AHB Lite In the SOM sheet of the design there exists an IP core used for AHB lite memory bus accessing It does not have any memory core attached as default when you open and view the project initially However this stub is the user to use to attach to any AHB lite memory bus interface IP core that they wish to use All of the signals not used are either tied LOW or HIGH if required for input signals and marked as unused if output signals The AHB core is instantiated as CoreAHBLite 0 in the SOM sheet design and currently has no intended functionality other than providing the user with a hook access point to the AHB ARM MSS system The AHB core has an associated location in the overall ARM AHB matrix memory map and therefore attached IP cores can then have hardware address visibility from the ARM processor software environment Libero C Morethanip SmartFusion 501 etFusion Project File Edit View Design Tools SmartDesign 248 of
37. CH Development Kit Reference Guide V1 0 July 2015 Project File Edit View Design Tools SmartDesign us gt cK amp Suz ax Kf 25050 50 484 X B 2220209 6 9 ANG xm V E SAE WEST GE GE GT TAR E GE GE MG TT E E i S Hh Fam SmartFusion2 25050 Pkg 484FBGA Verilog Figure 28 Screenshot of Lower Level SOM sheet of the Starter Pack Libero Project 13 1 Emcraft Systems The above figure overview encapsulates the whole of the NetFusion EXP SOM sheet However it was built on the basic project supplied currently by Emcraft They designed and developed the M2S SOM F484 that is housed on the NetFusion EXP baseboard PCB Various IP cores were added to accommodate the need to support and facilitate the vast multitude of NetFusion EXP s PCB hardware available to the ARM MSS sub system in the SmartFusion2 FPGA on the Emcraft M2S SOM F484 housed on NetFusion EXP as one product As the MSS can only drive and support some of the pins on the SOM unit there was a requirement therefore to add more IP cores in the fabric to interface through the I O assignments to the PCB hardware not connected directly to the MSS These additional cores and the default statutory parts of the SOM design in the Fabric are described in the sub sections below 65 research 9 and development N
38. Config V1 0 July 2015 The SmartFusion2 MSS processor sub system always as standard has a default CoreSF2Config block which loops back an APB bus out and then back into the MSS block This seems at first strange and can be very confusing However it is the inherent architecture of the FPGA ASIC area that most of the peripheral devices inside the MSS ARM processor core are not actually controlled by the selections made in the Libero 11 X IDE It is the software in u boot during boot up that configures If say for instance an AHB Lite interface is selected in Libero then this does not configure the SmartFusion2 FPGA itself It saves a configuration file that can be included by software in either bare metal programming or the u boot from Emcraft uClinux environment Only when the boot up code access the APB feedback bus via CoreSF2Config 0 and manipulates hardware peripheral memory address does the peripherals in the MSS get the correct mode of operation intended for them Libero C Morethanip SmartFusion 501 Fus Project File Edit Design Tools SmartDesign Help Meno et Edw sow Edwasoso soM resss TOP es 25 502 0 5 9 9 CoreSF2Config 0 IP ZS a DE ig ga lt iL E AND z KEK lt lt SE Io zo cz 38 o lll 1 Fam SmartFusion2 De 25050 Pkg 484FBGA Verilog Figure 43 APB feedback Bus for
39. DAUGHTER CARD 72 13 8 BIBUF BI DIRECTION BUFFERS FOR DAUGHTER CARD GI 73 13 9 CAN CONTROLLER 74 13 10 eer EE 75 13 11 0 e 76 13 12 TEMPERATURE SENSOR GLUE LOGIC 12 52 cas E RR Rae ona TT 13 13 COORDINATED RESET eiecerunt eeu ee lated eaten 78 1374 CU EE 79 1315 CORESFZCONFIG iit O 80 1326 CORE EE 81 19217 AAB EITE 82 1318 COREAPBJ EE 83 13 19 AXI AHB LiTE amp APB3 DEFAULT MEMORY MAPPED SETTINGS seen 84 19 20 SMARTFUSION2 MSS E 87 14 NETFUSION EXP ARM CORTEX MSS DEFAULT CONFIGURATION 88 14 1 CAN CONTROLLER 88 14 2 O 89 14 3 BRI 90 14 4 ETHERNET 91 14 5 CGC Rm 92 14 6 RESET CONTROLLER C EET 92 147 93 14 8 gem 94 14 9 FIC 2 PERIPHERAL INITIALIZATION cesses 8 95 15 ADDING IP CORES FROM nnne nnne nnn rien rien 96 15 1 IMPORTING SOURCE FILES
40. De 25050 Pkg 484FBGA Verilog Figure 30 SmartFusion2 Reset Controller IP Core oD research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 4 FCCC The entire FPGA sub system comprising of the MSS ARM processor and the main fabric run on clocks all generated from this core It is the main coordination of the clock lines that are distributed The input is 12MHz from an off chip crystal IC The CCC PLL divides down the 12MHz source by 12 to 2 Then this is multiplied up by differing amounts for GLO You can add more clock PLL lines as you wish when you are modifying the design FCCC_0 XTLOSC_CCC_IN Figure 31 Clock PLL Macro Core The core as been instantiated as FCCC 0 There is also a LOCK output signal that is used by the MSS to determine when the PLL has settled and locked onto the desired output frequencies All clock outputs are digital square waves 68 E NINE WAYS FUSIOn NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 E Advanced options have been modified The information displayed in this tab might be inaccurate please use the advanced tab for the actual configuration Figure 32 PLL Clock Macro Settings Output signal GLO is distributed to the memory bus and the MSS ARM block The m
41. F Bank TRISTATE None No IOEXP3 Inout 1VCMOS25 1 e ADLIE BIBUF Bank TRISTATE None No 24 IOEXP4 Inout 1VCMOS25 ADLIB BIBUF Bank TRISTATE None No 25 IOEXPS Inout 0525 Pl ADLIE BIBUF Bank TRISTATE None No E 26 IOEXP6 Inout 0525 RL ADLIE BIBUF Bank TRISTATE None No IOEXP7 Inout 1VCMOS25 P2 E ADLIB BIBUF Bank TRISTATE None No IOEXP8 Inout LVCMOS25 E ADLIB BIBUF Bank TRISTATE None No m 29 IOEXP9 Inout 1VCMOS25 ADLIE BIBUF Bank TRISTATE None No 30 10EXP10 Inout LVCMOS25 ti ADLIB BIBUF Bank TRISTATE None No IOEXP11 Inout 0525 2 ADLIB BIBUF Bank7 TRISTATE None No EZ IOEXP12 Inout 1VCMOS25 P4 ADLIE BIBUF Bank TRISTATE None No IOEXP13 Inout 1VCMOS25 M3 rz ADLIB BIBUF Bank TRISTATE None No IOEXP14 Inout 1 0525 ADLIE BIBUF Bank TRISTATE None No 35 IOEXP15 Inout 1VCMOS25 u ADLIB BIBUF Bank TRISTATE None No 36 TOEXP16 Inout LVCMOS25 ADLIB BIBUF Bank TRISTATE None No 37 IOEXP17 Inout 1VCMOS25 15 E ADLIE BIBUF Bank TRISTATE None No 38 10EXP18 Inout LVCMOS25 N5 ADLIB BIBUF Bank TRISTATE None No 39 10EXP19 Inout LVCMOS25 K4 ii ADLIB BIBUF Bank TRISTATE None No IOEXP20 Inout LVCMOS25 ADLIE BIBUF Bank TRISTATE None No a IOEXP21 Inout 1 0525 S ADLIB BIBUF Bank TRISTATE None No 22 Inout LVCMOS25 M5 ADLIE BIBUF Bank TRISTATE None No IOEXP23 Inout 0525 P6
42. GmbH customized and locked down projects can be tailored for customer requests but that also is separate to this project ip research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 10 5 Product Development At the point where the Libero IDE SoC has been installed the NetFusion EXP starter project has been downloaded and exploded into a target directory on your PC the project has been loaded synthesized programmed and shown to be running on the NetFusion EXP PCB product you are ready to begin your development As standard the main fast Ethernet pathways into the SmartFusion2 FPGA fabric are wired in through the FPGA ball I O assigned the I O editor brought down through the Top Level and then into the SOM level of the design in the project They then terminate at a dummy IP core for all un assigned wires this makes life a lot easier for the developer knowing that all the NetFusion EXP traces coming into the M2S SOM F484 are wired into the SOM level of the fabric design Changes are therefore quick and easy to then re assign in that lower level sheet to new instantiated IP cores of the user s choice The category of wires left terminated and not used are the GMII Ethernet pathways Users can download and use Vendor specific MAC SWITCH cores or chose to privately purchase cores from reputable design houses such as Moretha
43. INE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 2 ULPI UTMI OTG USB On the SmartFusion2 F484 package that is used with Emcraft s M2S SOM F484 System On Module the ULPI MSS interface is not supported However the UTMI OTG USB signals are supported As the track routing and the IC USB device on the NetFusion EXP PCB support ULPI an IP core in the fabric is require to convert between the two different USB On The Go protocols and signals This has been instantiated as ulpi port 0 This OTG core was used from OpenCores at http www opencores com and resides in the NetFusion EXP starter project s hdl sub directory Libero C Morethanip SmartFusion 50 etFusio Project File Edit View Design Tools SmartDesign Help A mop 89 2 sod x 25050 50 FG4B4 TOP X nn o OW j uipi portio ASS 2 ulpi dir ulpi stp ulpi nxt ulpi reset ulpi_clk60 utmi_clkout utmi databus16 8 utmi txready 0 H 4H H H utmi reset utmi rxvalid pa RSRRRRRRRRRRR O Uu uL Tete utmi_termselect utmi_rxerror T E 4 4 utmitxvalid ulpi data out 7 0 E ZEN B up data PHHH i BETEN ulpi data in 7 data out 6 Kr T T ulpi data in 6 ulpi data out 5 111 r r rz ulpi data in 5 ulpi data out 4 Kr rz ulpi data i
44. KETS ite dese etait ta uode Lage e desinet E FL e uud 33 4 5 POWER SUPPLY Gottes edd tede Fare etude Led cu ee CERE oe cd at eda 33 4 6 RESET BUTTON I necesse ure desee edi dvo Gao cuis edu edat NE 34 4 7 GENERIC OPTION SWITCHES AND CONFIGURATION DALL 34 4 8 USERB TIONS amp cest aeta ek dadd aeta we e d 35 4 9 5 6 thecal idea Lada Du ae Hd FEE 35 4 10 TEMPERATURE SENSOR dieitur ta sehe adt aa oe cui Cer Re dat we Ld ede 36 4 11 VOLTAGE MONITOR 5 36 4 12 REA CLOCK cacani P 37 4 13 RS232 SERIAL INTERFACE 37 4 14 RS9485 SERIAL INTERFACE o ta en area EA 38 4 15 VOLTAGE FREE RELAYS Qa a da ee ad da aad 38 4 16 ANALOGUE CONTACT INPUTS 39 iol research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 4 17 EARTH AND LIGHTNING DROTECTION eene 39 4 18 LED INDICATORS ELEME 40 4 19 NETFUSION EXP SPECIFIC 8 1
45. P Program Design e Generate Programming Data Debug De Update and Run Reading file mt Figure 63 Selecting Full NetFusion EXP Synthesis and FPGA Programming Once you are ready to synthesize and program the SmartFusion2 FPGA on the M2S SOM F484 housed on NetFusion EXP select the option shown above Note This should take around 20 minutes on a standard Windows XP 7 8 PC However larger customized design will add significant time especially if the design has strict time constraints 99 research and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 16 Using FlashPro4 IDE to Program NetFusion EXP Install and make use of FlashPro IDE on Windows XP 7 8 OS to allow for the stand alone programming of the baseboard without the need for launching installing or using the full Libero 11 X SoC IDE E FlashPro File Edit View Tools Programmers Configuration Customize Help ngue lt gt Microsemi FlashPro Version 11 4 1 17 Release vil 4 5 1 ER han Errors Warnings Info Ready No project loaded Figure 64 Opening screen of FlashPro IDE Launch the IDE so that you see the above screen Also if you have just installed the IDE ensure that you have also installed the FlashPro4 USB device driver in the Windows Device Manager Note the device drive
46. Peripheral Configuration by Software research and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 16 Core AXI In the SOM sheet of the design there exists an IP core used for AXI memory bus accessing It does not have any memory core attached as default when you open and view the project initially However this stub is the user to use to attach to any AXI memory bus interface IP core that they wish to use of the signals not used are either tied LOW or HIGH if required for input signals and marked as unused if output signals The AXI core is instantiated as COREAXI 0 in the SOM sheet design and currently has no intended functionality other than providing the user with a hook access point to the AXI ARM MSS system The AXI core has an associated location in the overall ARM AHB matrix memory map and therefore attached IP cores can then have hardware address visibility from the ARM processor software environment Libero C Morethanip SmartFusion 501 Project File Edit Design Tools SmartDesign Help Dn sow s x E m25050_s0M_FG484_TOP amp X x 2552050 989 e i 588 S 55 Q n 2 82 Bez 20 250 zta BLL pled 0 OS RR X MEM X PRV VV VV VV X RR 552585 555556565
47. SOM sheets are built and prepared they propagate information up automatically to this higher sheet New ports suddenly appear and you must then compile this sheet before the main synthesis Note you can instantiate normal IP cores into this top sheet if you wish and it makes sense according to your design requirements This is just the starter project so everything by default is kept in the lower SOM module But this can change rapidly as your customization starts to take effect The lower SOM sheet of the NetFusion EXP starter Libero project contains all of the default designs and linkage 63 ua research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 This SOM sheet lower layer contains the ARM Cortex M3 MSS block and then all of the necessary associated IP core blocks to allow the processor the Emcraft SOM and the wider surrounding NetFusion EXP baseboard hardware to operate and be accessed 4 H Er slay MODR DDR Save 1 H LES VIE OOA SAEN N Figure 27 Lower Level SOM sheet MSS block The next screenshot shows a rats nest but the following sub sections illustrate the different parts in more detail Note ncidentally the largest module center left is the MSS ARM cortex processor zoomed above 64 research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWIT
48. SmartFusion2 FPGA In particular the actions relate to programming the eNVM Flash with the u boot code to boot the device from reset Moreover it access and re programs all of the FPGA fabric flash that houses the IP cores and project integration The programmer is controller on a host PC by Libero IDE or FlashPro4 stand alone application Just connect the ribbon from the programmer onto the header make sure that the RED ribbon line is on the same side as the PCB silkscreen dot The IDE handles all of the integration of the u boot code and the fabric This goes beyond the scope of the document from here Once the SmartFusion2 FPGA on the SOM is released from a full reset the fabric flash is loaded into the SDRAM of the core and provides the RAM based fabric operation Additionally the eNVM flash is loaded into the eNVM RAM for u boot execution It is at this stage that the u boot loads the uCLinux from the SPI external flash on the SOM into the external LPDDR SDRAM memory The Linux environment then boots and execution of the user applications can begin research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 4 3 ARM JTAG Interface The NetFusion EXP PCB provides an ARM JTAG interface for debugging of the SmartFusion2 SoC FPGA on the SmartFusion2 SOM The connector is a standard 20 pin JTAG port supported by standard Cortex M3 programmers emula
49. TCH Development Kit Reference Guide V1 0 July 2015 In the drop down menus choose Configuration then select Load Programming File Chose your STP file to program NetFusion EXP Click on the main PROGRAM button center right of the above screen Wait for the programming to complete typically after several minutes If you cannot select the USB programmer correctly check it is plugged in and also click on Refresh Rescan for Programmers button towards the bottom of the screen above Important Note once the operation to program NetFusion EXP is complete the SmartFusion2 FPGA will re power and start automatically 102 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 17 FAQ Why even bother with NetFusion EXP PCB baseboard If you want an evaluation PCB something to develop with before during or after your own custom PCB development or because it provides everything you need for your own product idea NetFusion EXP is immediately available for use All you need to implement is your own software programs change the uCLinux configuration write device drivers and maybe if necessary add in Libero IDE more IP cores in the fabric Why is the LCD screen not provided as standard This can add unwanted cost to the baseboard As there are so many different manufacturers this is removed from the default b
50. age as a command helper 9 research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 8 NetFusion EXP Development Kit Web Server The NetFusion EXP default uCLinux bundle has a working and ready to run apache2 web server This is compiled and guised in the form of httpd from busybox The httpd html directory contains the web page echo system where you can change and re design to you own desires and architectural requirements As a start point in the bundled NetFusion uCLinux Development Kit package the web page system shows a demonstration of the PCB hardware and the SQLite capabilities Also the NetFusion user space UIO drivers are all used to facilitate the web content which can aid and help the user see how the cgi mechanism by default can allow hardware to interact with the web front end Moreover you can then grasp the value of the SQLite database system be able to use the hardware and the web page to create a truly useful product which all takes advantage of the flash mounted SPI hardware using the JFFS2 partition to allow for the persistent storage e 1 Nineways Research and D Y m 5 10 1 17 cgi bin mydemo cgi 57 i NINE WAYS Research amp Development NetFusion Demo Site Home Board Checks Drivers SQL Server Nineways Contact Details Welcome to the NetFusion inbuilt de
51. ain base clock frequency for the 166MHz ARM processor is scaled up inside the MSS block do research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 5 Counter CoreGPIO NetFusion EXP PCB has an on board temperature sensor The output of which is a square wave signal that has a frequency is equivalent to degrees Kelvin down to absolute zero This signal is routed into the SmartFusion2 FPGA fabric and clocks the 16 bit counter counter 6 0 The counter s 16 bit output value is wired into GPIO input CoreGPIO 1 which is memory addressable from the ARM uClinux applications This serves as a simple 32 bit memory location to read and makes the software algorithm for determining the temperature incredibly simple Note the memory interface from the ARM MSS is an APB interface TEMP SENSOR 8548514 Figure 33 Temperature Sensor Logic 4 oD research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide 13 6 NetFusion EXP Baseboard Peripheral CoreGPIO V1 0 July 2015 The vast majority of the hardware on the NetFusion EXP PCB is connected through this core The obvious exceptions are the Ethernet pathways RS485 UART and the SPI audio input output However all of the 2C Relays I O expanders Real Time clock IC voltage monitor expansio
52. all of the necessary current In some cases LVTTL allows for 2 5V to drive 3 3V but this is not guaranteed and over time signal distortion can occur with drift In order to get round this one of the IDC connectors will have outputs only converted to 3 3V via reverse diodes and a pull up and a second IDC as input only series drop resistors The remaining I O IDC can be assigned as inputs or outputs For the two IDC that are designated as input ONLY or output ONLY attempting to assign them oppositely in the Libero IDE will result in no physical damage but will produce unpredictable results The output IC will not work as inputs at all due to the series diode For the input IDC trying to use them as outputs in Libero IDE may work if the target IC device can cope with around 1 8V threshold or less In general keep inputs and output IDC signals dedicated and the rest can change or be randomly connected to the two I O IDC connectors 5 2 GPIO Hirose connectors The EXP daughterlO PCB houses two Hirose DF40 series connectors J1 J2 for mating with the NetFusion EXP baseboard PCB The connectors are 80 pin 0 4mm pitch plugs providing 1mm stacking height Only the 5V and GN pins are used for power on the daughter card All other power pins are not used as this board re generated the 3 3V via a regulator so as not to load the existing 3 3V on the base board of the 72 GPIO signals are connected via Zener clamping to protect the FPGA from o
53. and development NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 NetFusion EXP Development Kit Reference Guide io research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 Table of Contents 1 INTRODUCTION E 8 2 ESTABLISHED DOCUMENTATION 4 RRE RRE RRE RRE 9 2 1 BASIC NETFUSION CONCEPT BENEFITS AND BRIEFE 9 2 2 LIBERO SMARTFUSION2 FPGA FEaApnc 9 2 3 HARDWARE tenens entr sienten seen nens 9 2 4 FULL SOFTWARE amp UCLINUX SUPPORT AND OPERATIONAL 44 4 442000 9 2 5 NETWORK PERFORMANCE AND SPEED TESTING 9 2 6 MEE uidiidem 9 3 OUT OF THE DEVELOPMENT KIT POWERING UP amp PROGRAMMING 11 KIT CONTENTS c Mase 11 3 2 APPLYING POWER E 15 3 9 15 3 3 1 Bench SUPPLY ER 16 3 3 2 Screw Terminal Installation 17 3 3 3 Output SV EDU MEE 17 3 9 4 JTAG Programming eite oe dci edes t Lo dt dE
54. and Licensing Guide Libero IDE License Troubleshooting Guide Note Press CNTL and click to download the links research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 10 3 1 Libero 11 X IDE First Launch Y Libero Project File Edit View Design Tools Help a StartPage Libefo System on Chip C Morethanip Smart 3PSWITCH F484 SE Welcome To Microsemi s Libero SoC v11 4 Software F484 Libero SoC is a comprehensive software suite for designing with Microsemi s SmartFusion2 and SmartFusion SoC FPGAs IGLOO2 ProASIC3 and Fusion FPGA families Visit the Documents tab on your device page at www microsemi com to obtain silicon Datasheets Silicon User s Guides Tutorials and Application Notes Development Kits and Starter Kits are available from the Microsemi website Links Welcome to Libero SoC What s New in Libero SoC Libero SoC Quickstart Libero SoC Interface Description Libero SoC Release Notes on the Web Libero Ul Enhancements New Tool flow for Simulation e Support for VHDL Constructs like Records Array of Arrays Libero Tutorials Non IDE Flow New HDL Text Editor Product Tutorials New Reporting Structure Training Webcasts Dynamic On Die Termination ODT added in DDR Mode Microsemi SoC Website Design Entry and Implem
55. and over engineered power supply system NetFusions are sold as variants of a core family and the EXP variant concentrates on the hardware supporting 10 100 Ethernet with a wide ranging functional daughter card expansion capability Obviously the PCB hosts a range of supporting hardware for customer interfacing and communication to allow the product to have a usage and functional reason to be deployed by the user research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 2 Established Documentation 2 1 Basic NetFusion Concept Benefits and Brief Please download and refer to the NetFusion Baseboard Product Brief PDF at the Nine Ways R amp D website 2 2 Libero SmartFusion2 FPGA Fabric The NetFusion EXP Development Kit promotes the use of a free Libero IDE project to download into the baseboard PCB via JTAG 2 3 Hardware PCB Reference Please download and refer to the NetFusion EXP Hardware Reference Guide PDF at the Nine Ways R amp D website 2 4 Full Software amp uCLinux Support and Operational Support Please download and refer to the NetFusion Software uCLinux User Guide PDF at the Nine Ways R amp D website 2 5 Network Performance and Speed Testing Please download and refer to the DMA iperf Test App User Guide PDF at the Nine Ways R amp D website Note You may be slightly confused by some of the documented
56. aster interface from the fabric where the default connection is to the AMBA DMA Controller for 3rd party MACs and Ethernet SWITCH If you do not wish to keep the DMA Controller or any AXI interface for that matter then you can de select the Fabric Interface and the SOM sheet will adjust accordingly Important You will have to remove and delete the instantiated DMA Controller however Note NetFusion EXP has to follow the architecture of the SOM F484 so this is primarily based upon the Emcraft starter project for this block 89 research and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 14 3 USB MSS USB Configurator IO Group Selection UTMI UTMI LINE STATE UTMI RX DATA UTMI TX READY UTMI EN VALID UTMI RX ACTIVE Click on a signal row to see the preview UTMI ERROR UTMI VBUS VALID UTMI AVALID UTMI SESSION END UTMI HOST DISCONNECT 2 2 2 2 2 2 IS Ki UTMI ID DIG Figure 54 USB OTG UTMI Host Controller NetFusion EXP does utilize on the PCB hardware an OTG USB interface In the fabric the ULPI is converted to UTMI and then connected to this MSS internal block The ARM uClinux application code will be able to access this USB block as a block of memory registers and device drivers will be able to control th
57. ce This is a USB device that your connected PC will recognize as a USB Serial Device and allocate a COM port to it Windows XP 7 8 Note dev ttySO 1 2 for Linux PCs Figure 5 USB Cable Connected to the USB UART Interface from a PC The IDE on the PC should open a window that can see the debug and allow for commands and text to be entered This will interact with the u boot Once you have programmed the SPI Flash with the uCLinux see NetFusion uCLinux Guide PDF then the interaction and debug will be with the booted uCLinux This includes how to connect a CATS to the 10 100 RJ45 for TFTP network transfer of the Linux kernel file 19 research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide X PuTTY Configuration Basic options for your PuTTY session MPG Specify the destination you want to connect to wn Seral l 5 Keyboard pens Be COM 115200 Features Connection type Window ORaw ORogn OSSH Seral Load save or delete a stored session Saved Sessions Connection Data Defaut Settings Close window on exit O Always V1 0 July 2015 O Never Only on clean ext Figure 6 Example of opening PuTTY in Windows 7 fei Applications Places System 5 Accessories Games P Graphics internet FA office Sound amp Video y Ubuntu Software Center Calculator
58. character Map p Disk Usage Analyzer Zi Manage Print Jobs Search for Files Take Screenshot F T Terminal 4 Text Editor Use the comm Tomboy Notes Figure 7 An example on Ubuntu Linux of the Terminal being launched Figure 8 Screen shot of a User entering into the u boot screen on the USB UART terminal session 20 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 Figure 9 Screen shot of allowing the boot process to execute uCLinux and initialize Your IDE on the PC should open a window that can see the debug and allow for commands and text to be entered This will interact with the u boot and once you have programmed the SPI Flash with the uCLinux see then the interaction and debug will be with the booted uCLinux This includes how to connect a CAT5 to the 10 100 RJ45 for TFTP network transfer of the Linux kernel file IO 21 research 9 and development o NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 3 4 Connecting a CAT5 Cable for TFTP Upload This document specifically does not go into detail on the installation cross compiling of the embedded code but below in simplistic ways illustrates the steps to upload the compiled and built uCLinux kernel and software Place a CAT5 cable prov
59. ck Annotated Files SS Simulate Verify Timing k Verify Power 4 gt Edit Design Hardware Configuration Programming Connectivity and Interface 62 research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 NetFusion EXP Libero 11 X IDE SoC Top Level Within the NetFusion EXP starter Libero project the M2S_SOM Top Level sheet illustrates the lower modules to the design just before the I O ports go out to the real world PCB The ports labeled in this sheet correspond to the I O assignments shown in the previous section This sheet is effectively the linkage from the inner SOM design see next section up to the I O balls of the SmartFusion2 FPGA Libero C Morethanip SmartFusion SON Project File Edit View Design Tools SmartDesign 2 087 Ef 5050 SOM FG484 8 X EIS SZ of AQHA M2S SOM 0 RESET N USER FAB RESET HISA_1_PADS TTL 1 PADS EJMMUART 0 PADS PADS 958 o PADS gion ge ge D Fam SmartFusion2 Die 25050 Pkg 484FBGA Verilog Figure 26 NetFusion EXP Top Level Sheet When lower level
60. d is represented on the SOM design sheet as TEMP SENSOR This in turn clocks the counter16 0 which has a 16 bit register output and be read into the ARM software environment via the CoreGPIO 1 APB3 core Although this read value wraps around 16 bit values the software can use a one second timer to run comparisons and then calculate the temperature in Kelvin Figure 40 Temp Sensor Counter Logic 77 10 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 13 Coordinated RESET The customized IP core instantiated as mtip reset 1 coordinates a longer reset pulse than the power on reset core often provides The source SYSRESET 0 feeds into the mtip reset 1 which then provides an output to the whole SOM sheet design This includes the ARM MSS block memory cores GPIO and all peripherals Libero C Morethanip SmartFusion SCH Project File Edit View Design Tools SmartDesign Help s mot sow x Bugs soM teg TOP 8 X SEILER 822202646446 2 Al SYSRESET 0 DEVRST POWER ON RESET FIC 2 APB M MDDR DER SLAVE MDDR APB SLAVE FIC 2 MASTER MDDR DDR AXI RMW EIMSS INT F2M 15 0
61. directly These flicker and blink when data is communicating on the USB UART and this can be used to diagnose if the user is having problems with talking to the NetFusion Linux environment from their PC Note The USB UART RED LEDs are driven direct from the USB device on the PCB and not the software application code 4 19 NetFusion EXP Specific Interfaces The main difference of the EXP variant against the CAT5 and SFP is not only that the Marvell 1Gbit s Ethernet feature has been removed but additionally that a dual Hirose expansion pluggable daughter card slot and secondly a CAN transceiver with connectors has been added 4 20 CAN Dual Transceiver The NetFusion EXP hosts the capability to allow the CAN Controller in the Smartfusion2 MSS to connect out to the real world via a baseboard CAN transceiver The device is a dual bus capable IC which enables independent buses to be controlled and managed by the CAN controller in the FPGA Only one bus individually can be accessed and driven at any given time this is controlled by GPIO enable lines visible to the ARM and directly strobes the CAN transceiver The CAN buses are protected by transzorb clamps to allow for the NetFusion EXP to be exposed to the more harsh industrial environments especially ESD The interfaces are two removable screw terminal headers for wired access J35 J56 and two DB9 connectors J37 J57 for a direct legacy use These both connect to an AMIS 42770 SM IC device U
62. e It also is then useful as the default dev ethO in the Linux system and provides an immediate Ethernet interface without any added IP cores in the FPGA fabric LED Definitions Note For DUPLEX LEDs ON FULL OFF HALF For SPEED LEDs ON 100Mbit s OFF 10Mbit s 30 do research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 SOM MSS SOM MSS Link ACT Port Speed 4 1 USB OTG Interface The second USB port on the NetFusion EXP PCB baseboard has no default purpose The traces from the USB host hardware on the PCB trace route through to the SOM SmartFusion2 FPGA fabric and present to a ULPI UTMI converter IP core This can be used either in the fabric or to the MSS ARM Cortex M3 processor embedded MSS USB support A customer user can choose how to use this port and has complete control of the usage and purpose The OTG on the go mechanism is very flexible and is widely recommended in the USB industry Important Note the SmartFusion2 SOM M2S 050 does not implement ULPI in the MSS USB peripheral so the fabric has the ULPI UTMI converter for the user s convenience when they plan how to use the USB For useful documents on understanding USB OTG then please refer to OTG Specification USB org 4 2 FlashPro JTAG Interface The JTAG header allows for the 10 way ribbon cable from a FlashPro USB programmer to access the
63. e ARM processor This can be bare metal code or early boot code from uClinux called u boot This MSS module block enables the signals to connect a feedback APB interface from the ARM processor to the other peripherals in the MSS itself It seems overkill but that is the architecture we are ruled by it seems In the case of NetFusion EXP we configure the FIC 0 and FIC 1 fabric interface controllers and also select the AXI Slave interface for the MDDR block Important Note do not ever remove this feature from the design of NetFusion EXP The system will not operate if deleted iol 95 research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 15 Adding IP Cores from Verilog VHDL 15 1 Importing Source Files Libero C NetFusion M2S SOM F484 CAT5 NetFusion F484 prjx Project File Edit View Design Tools SmartDesign Help DSH Design Flow 8 sow amp x 69 25050 soM rc s4 amp x M2S SOM o 6 Eb MS g PIA m H b Create Design amp System Builder v amp Configure MSS Create F amp View Cor Import Files gt Verify F B 5 7 Create Constraints E 1 0 Constraints constraint jo M2S050_SOM_FG484_ constraint io M2S_SOM io pdc Si constraint io M2S_SOM_FG484_TO E Timing Constraints synthesis M2S_SOM_sdc sdc constrai
64. e USB OTG as a USB stack Note the UTMI signals do not get routed to the I O pins directly but the fabric for the use of the ULPI UTMI converter IP core 90 research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 14 4 Ethernet DN MSs Ethernet MAC Configurator Interface MII Fabric Line Speed 100 Management Interface TXD 3 0 MI TX EN MI TX ER E Fari iy Fo RXD 3 0 g MII RX ER MII RX DV Click on a signal row to see the preview n 4 MII_CRS MII COL MI RX TX Figure 55 MSS MAC for 10 100 Ethernet Using SOM PHY This is a very strategic and important module in the MSS of the SmartFusion2 of NetFusion EXP The RJ45 Ethernet connector on the NetFusion EXP is routed directly to the PHY on the M2S SOM F484 which in turn connects into the SmartFusion2 FPGA and directly into the ARM MSS Once in the MSS the Ethernet MAC receives the connections which then provide a memory interface internally for the ARM uClinux device drivers for the network interfaces Note The connections route to the fabric before going up through to the I O assignments It is important to emphasize that with NetFusion EXP all of the Expander GPIO that routes into the SOM sheet of the starter project
65. e application code to use one of the UIO device drivers to ascertain the state and configuration of the option switches and the rotary switches For instance you can set parts of a MAC address or change fundamental MII modes The most common usage is for user application program specific initialization settings 34 research and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 4 8 User Buttons amp LCD The LCD is not fitted as standard to a NetFusion EXP baseboard unless you have purchased the development kit bundle It is a 16 x 2 digit alpha numeric screen with just black monochrome as a color A rotary dial controls the contrast and also another dial controls the backlight power The contents of the screen are controlled by application software via the GPIO core in the SmartFusion2 FPGA fabric The contents of the screen survive a hardware reset which is why it must be cleared and re initialized upon software boot up if the screen is to re establish an initialized message announcement The customer user can use the screen if required to show whatever content they desire and is only designed in for user purposes The LCD buttons are just input signals available to the application code as well Monochrome 16x2 Alpha Numeric Backlit Contrast adjustable LCD 4 9 Stereo Audio Phono Jacks The two stereo 3 5mm phono jacks pr
66. eboard PCB whether it is for evaluation test or full industrial deployment and mass production purposes the Development Kit EXP bundles a whole item list of additional equipment Tailored for the Research amp Development process if you choose to order and use the Development Kit EXP you will be provided and equipped with cabling USB cables LCD screen desk pillar support Ethernet CAT5 6e patch cable audio phone stereo patch cables RS232 modem cable and an L T E 19V 120W desk mains brick These are all additional items over the standard NetFusion EXP PCB deliverable that you will receive as part of the Development Kit package The core of the architecture is the System On Module SOM M2S050 SOM F484 is the Smartfusion2 FPGA and ARM Cortex M3 sub system The Flash RAM clocks default Ethernet PHY FPGA and all essential voltage level generation are contained on the SOM plug in to the NetFusion EXP All the connections from the SOM to the NetFusion EXP baseboard go through durable connectors and allow for inter changeability if needed or required by the user The usage of a SOM on the baseboard reduces the risk of writing off the value of the sub system when interfacing to the real world damage occurs or installation faults As a baseboard it is ideal for a user to take advantage of the Smartfusion2 FPGA technology whilst at the same time binding it with the industrial hardware interfaces and environmental protection on the connectors
67. ector J6 Customer Interface 47 Table 7 IDC Connector J7 Customer Interface 48 Table 8 Full NetFusion User Space Hardware Drivers 49 Table 9 Typical CAT5 6 cable wiring sess eren entere 55 Table 10 Document History Entry Log 107 10 9 research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 About This Document This specification fully documents and describes the NetFusion EXP PCB incorporated as a Development Kit package for R amp D purposes Use this manual to fully acquire a good understanding of the significant difference of the Development Kit over and above the normal NetFusion EXP delivery Important this document although a Reference Guide PDF it does contain a section that warrants User Guide material regarding quick setup and operational usage when interacting with the Development Kit from your PC Intended Audience This document is fully written for Nine Ways customers using the hardware NetFusion EXP Development Kit for evaluation and R amp D research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 1 Introduction The NetFusion EXP Ethernet SWITCH Development Kit is an added layer of deliverable package to the customer Whereas the ordinary NetFusion EXP product delivery is a packaged bas
68. entation Learn more System Builder Update o Added Independent PCle resets for M28090 GL090 LIDI i Ontinn far Log Bx Szen nfo Fem Die Pkg Figure 21 Libero 11 X IDE Boot Up Screen 10 4 NetFusion EXP When purchasing any NetFusion EXP variant an important component of the overall product is the NetFusion EXP Libero starter project that is provided by Nine Ways Research amp Development Ltd This is downloadable from Nine Ways R amp D Ltd and when expanded into a target directory on your development PC provides an immediate project for your needs Instead of having to start and debug creating an ARM sub system with all of the supporting IP cores required to have a functioning NetFusion EXP PCB just use the provided project From installation you can program the IDE project once synthesized into your NetFusion EXP product using the FlashPro4 USB device This will provide the standard functionality in the Smartfusion2 FPGA fabric on the M2S SOM F484 SOM System On Module to see a working project In the software bundle to this product the uClinux device drivers will drive and control the hardware on the NetFusion EXP PCB through the IP cores in this project for the FPGA fabric Users can contact Nine Ways R amp D for special functionality to be developed and deployed but this serves as an addition to this starter Libero 11 X IDE project Moreover in conjunction with MorethanIP
69. generated uCLinux kernel package binary for TFTP upload linuxPC Project linux cortexm 1 xx x projects netfusion savetftp research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 3 5 1 Building the SQLite linuxptp testapp amp demo application incrementally Change into the netfusion source sqlite directory and build the binary with make linuxPC Project linux cortexm 1 xx x cd projects netfusion source sqlite linuxPC Project linux cortexm 1 xx x projects netfusion source sqlite make Change into the inuxptp directory and build the binary with make linuxPC Project linux cortexm 1 xx x cd linuxptp linuxPC Project linux cortexm 1 xx x projects netfusion source linuxptp make Change into the demoapp directory and build the binary with make linuxPC Project linux cortexm 1 xx x cd demoapp linuxPC Project linux cortexm 1 xx x projects netfusion source demoapp make Change into the testapp directory and build the binary with make linuxPC Project linux cortexm 1 xx x cd testapp linuxPC Project linux cortexm 1 xx x projects netfusion source testapp make 3 5 2 Building the main uCLinux with NetFusion Incrementally Then change into the netfusion directory and build the binary with make linuxPC Project linux cortexm 1 xx x cd projects netfusion linuxPC P
70. h Configuration APB Master Data Bus Width 32bit em sit Address Configuration Number of address bits driven by master 28 x Position in slave address of upper 4 bits of master address 27 24 Ignored if master address width gt 32 bits sl Indirect Addressing vet inuse g Allocate memory space to combined region slave Soto 5 Soti Slot 2 E Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 Slot 11 Slot 12 Slot 13 E Slot 14 E Slot 15 Enabled APB Slave Slots Soto Soti V Slot 2 V Slot 3 V Slot4 V Slot 5 V 5 6 Sot 7 V Sots V Slot 9 Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15 Testbench User License Obfuscated 7 RTL Figure 50 Default APB Configuration Important Note as a Libero 11 X designer and developer the user may change these defaults and added or remove memory accessible IP cores to from the fabric research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide 13 20 SmartFusion2 MSS In the SOM layer sheet of the NetFusion EXP starter project the MSS ARM processor main core is situated in the middle and is shown below If you double click on the MSS block it will expanded and c
71. hat Fabric Region 2 0x7000000 Ox7FFFFFF has been allocated to the next FIC 1 block next sub section The configuration on the left panel above selects mapping for both FIC 0 and FIC 1 NetFusion EXP assigns Fabric Region 2 to the APB memory interface so that the UART SPI and GPIO can be accessed in the fabric otherwise only this AHB Lite interface would be mapped which would severely limit the NetFusion EXP functionality and capability 93 NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 14 8 FIC 1 Mss Fabric Interface Controller FIC 1 Configurator Figure 59 APB3 AHB Lite Fabric Interface 2 Using the configuration from the previous FIC 0 block previous this MSS module enables the interface to access the GPIO SPI and UART in the NetFusion EXP SmartFusion2 fabric Note this is also an APB Master as the ARM processor has complete control 94 e development NINE WAYS FUSIOn NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 14 9 FIC 2 Peripheral Initialization Initialize Peripherals Using cortexws zl MSS DDR Vv Fabric DDR and or SERDES Blocks v E ONFIG PRESET CoreSF2Config Figure 60 APB Peripheral Hardware Configuration As described earlier in this document the SmartFusion2 FPGA is setup and primarily configured by boot up software executed by th
72. ide of the NetFusion EXP baseboard if necessary All power supply levels I2C buses SPI buses JTAG spare I O from the SOM headers Ethernet channels old expansion I O GND interleave switches buttons jumpers and all other parallel useful signals are routed through the expansion Hirose connectors for daughterboard functionality and general usage 00000066 ek 00 oo DIS QS 00 Figure 18 Expansion Slot Area 41 iol Q development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 5 Expansion I O Daughter Card 1 Wm d jj itii The EXP daughterlO PCB product implements the following functionalities e Four 20 way IDC polarized connectors for customer real world interfacing e Two 80 pin SOM connectors e Full ISO EN 61000 2011 EMI EMC compatibility for electrical noise emission immunity for both radiated and conducted categories e Industrial temperature capability of 40C to 85C degree Celsius for the main PCB e Full protection of the 2 5V I O ball assignments of the SmartFusion2 050 F484 FPGA Two IDC connectors are direction limited and two are input output The 2 5V signals are split into input IDC and output IDC as the conversion from 2 5 to from 3 3V TTL is simpler e All signals are protected with 3 3V Zener diodes to stop over voltage to the FPGA This pro
73. ided between your Laptop PC s Ethernet port and the NetFusion EXP Ethernet port 3 5 Building the NetFusion Customized uCLinux Kernel The entire NetFusion uCLinux environment can be built from clean in two simple steps For a normal incremental make which just updates any changes then it can be generally built in a single step Important Note if you have just booted your PC or have closed down a terminal session and then re started you will have to go through an initialization step first You must activate your uCLinux Cortex M development session by navigating to the top of your uCLinux Cortex M installation and run psl pvr linux cortexm 1 12 0 source ACTIVATE sh Then change into the netfusion directory linuxPC Project linux cortexm 1 xx x cd projects netfusion Also if you had to run the source ACTIVATE sh above then you must also run the following linuxPC Project linux cortexm 1 xx x projects netfusion startftftp To clean the entire project type linuxPC Project linux cortexm 1 xx x projects netfusion make clean 22 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 Then to clean the SQLite separate build system type linuxPC Project linux cortexm 1 xx x projects netfusion cd source sqlite linuxPC Project linux cortexm 1 xx x projects netfusion source sqlite make clean
74. if the user is keeping this starter project design they will still have to configure the associated GPIO core to reflect the I O setup 73 research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 9 CAN Controller The CAN transceiver on the NetFusion EXP baseboard PCB is connected to the CAN Controller inside the MSS block either directly for the RX and TX or via OR gate logic for the enable lines These are instantiated as OR2 0 OR2 1 and serve as a mask to either allow bus bus2 or both to be used during transmission The masks are controlled by signals from the small GPIO core CoreGPIO 2 The signals from the GPIO core to mask the enable lines ensures that application software controls the dual bus behavior for the CAN interface on NetFusion EXP Corresponding GPIO bits that are cleared disable that CAN bus and those which are set enable it Project File Edit View Design Tools SmartDesign Help Jee Oa on a 25 SOM ax ET m2s050_SOM_FG484_TOP 8 X 6 DEMP 2550505 AQHA j ODY nv 7ZWZVIX SOLL DI Y Y Y x USB VCONTROL 3 0 BX CAN FABRICEI d Fog CAN RX F2M B R WNPRMSREMNENEMES d i 14 CAN_TX_M2F 1 1 TX EN LI I I Yb i 1 5 Ew B 2 1 1 I lt lt Ier 1
75. imple initial software testing and probing before major design changes are implemented The CoreGPIO blocks are visible to the ARM MSS processor via an APB interface memory bus Lines can be configured as inputs or outputs and are all individually controlled and observed by the uClinux UIO device driver CH Libero C Morethanip SmartFusion SO SmartDesign Help Dee eon amp x 25050_5 FG4s4 TOP X 6 Seb Borer AAHS Project File Edit View Design Tools Par win CoreGPIO 4 Es np gr Rari or 3 258844445 888328235 TIE 4 Figure 35 Main CoreGPIO for the Daughter Card Expansion IO slots ed Fe i BIBUF 55 i gt g Ju n 1 i BIBUF 36 i BIBUF 56 H Fam SmartFusion2 De M2S050T Pkg 484FBGA Verilog 72 uo research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 8 BIBUF Bi Direction buffers for Daughter Card GPIO Throughout the NetFusion EXP starter project s fabric logic design
76. ion directly on the baseboard The battery is capable of maintaining power to the RTC device for 3 years approximately without the board being powered The Battery charges when power is present The RTC device is accessed via the FPGA fabric using an I2C bus A UIO Linux device driver accesses the device and presents a time and date to user application programs or the Linux BASH script environment This function can maintain a ticking time during power off and runs of a 32 kHz crystal maintaining a good level of accuracy If your Libero IDE NetFusion EXP project has the on board MSS RTC enabled then that will be able to run in parallel and independently of this RTC hardware on the baseboard 4 13 RS232 Serial Interface The first UART interface of the uCLinux system in the Cortex M3 processor is used for the USB UART as described early in this section This presents itself as dev ttySO in the uCLinux file system of devices available to use However for dev ttsS1 the second serial port NetFusion EXP exposes this as industrial DB9 RS232 interface in parallel with an adjacent screw terminal header with the exact same RS232 level pins The NetFusion EXP uses an RS232 level shifter to convert from the LVTTL of the SOM and also provides 1000V isolation from induced voltages on the RS232 lines This is very useful in the industrially deployed arena where typically NetFusion EXP may be installed The normal RX and TX signals are routed direct
77. is scattered around Bi Directional macros However the group shown below pertains to the bi directional switching capability of the IO lines for ALL 72 IO EXP daughter card signals These convert conveniently any IN OUT data flow when the RX and TX are kept separate in the IP cores The output side always routes up out of the SmartFusion2 FPGA to the NetFusion EXP daughter card slots where the signals are capable of input output operation using pull up resistors combining tri state operation The instantiated BIBUFs are illustrated in the Figure below Libero C Morethanip SmartFusion SCHER Project File Edit View Design Tools SmartDesign Help ose 2 8 x Ed 25050 50 4 4 EE t smiao 252 0 BIBUF_89 BIBUF_27 4mD Fam SmartFusion2 Die M2S050T Pkg 484FBGA Verilog Figure 36 Bi Directional Buffers for the Daughter Card Expansion IO slots Important Note the Libero logic design of this NetFusion EXP start project is capable of ALL 7210 lines to the daughter card slots to support input or output configuration As the user customizes and changes the design this may become more specific to input or output depending the required design Additionally some daughter card s themselves may have input only or output only circuitry present which means
78. kaging Be careful not to static discharge yourself through the PCB as this can cause severe if not irreparable damage Note always try to use earth straps when handling the NetFusion EXP PCB 3 3 Applying Power There are two different methods of supplying the DC power to the NetFusion EXP product They are electrically wired in parallel and should not be used simultaneously even though there is on board protection for such a circumstance Auxiliary 5V derived output connector Figure 1 Power Connector Options Both power methods allow for 9 36V DC voltage variation Important Note you should always consider equipping and providing a power supply delivery unit that provides at least twice the maximum current consumption in the table below 15 research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 Important Note The below table assumes a current consumption of an average of 500mA constant from a daughter card expansion DO 9 1920 12 1390 18 1130 24 850 36 660 Table 1 Voltage and Current Consumption on Power Supply 3 3 1 Bench Supply You can use a standard 18V L T E or similar mains desk supply The molded connector on the mains supply will plug directly into the power receptacle Q2 on the NetFusion EXP PCB Figure 2 Desk Mains P
79. lectromagnetic noise this may affect the maximum distance for cable runs 9 1 RJ45 plug and CAT5 6e cable connections Copper network connections within a NetFusion EXP system must always be made using standard CAT5 6e straight through cables These can be wired using either 568A or 568B pin layout but both ends of the cable should use the same pin layout 568A Wiring 345 Pair Wire Pin number ANZ Blue Blue White 4 5 White Blue 5 Green Green White 2 White Green 1 Orange Orange White 6 White Orange 3 Brown Brown White 8 White Brown 7 568B Wiring 54 research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 A 45 Pair Wire Pin number Blue Blue White 4 White Blue 5 Green Green White 6 White Green 3 Orange Orange White 2 White Orange 1 Brown Brown White 8 White Brown 7 Table 9 Typical CAT5 6 cable wiring s research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 10 SmartFusion2 FPGA NetFusion EXP Fabric Development 10 1 Libero SoC IDE Version 11 x Derivatives Microsemi s Libero IDE software release for designing with Microsemi Rad Tolerant
80. ly to the DB9 and the screw header terminal for statutory use but the extra DTR DSR CTS RTS RI signals go through selector switches described early in this document before potentially routing to the DB9 headers The purpose of the extra LVTTL signals being switched is to give the user a choice of whether these signals are needed They can be routed instead to the GPIO auxiliary interface to be used for other customer intended functionality Most commonly RS232 only uses RX and TX so by switching the extra signals to the GPIO it allows for the pins from the SOM to be re used for other features These extra DSR DTR RTS CTS signals are not controlled in the MSS ARM but from the general GPIO driver in the NetFusion Linux system The signals excluding the RX and TX route back through the SmartFusion2 FPGA fabric through a UART core which is addressable as memory from the UART device driver However the RX and TX are connected direct to the MSS UART iol 37 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 4 14 RS485 Serial Interface The USB and RS232 ports are not the only UART functions available to the user Another driver has been installed to allow for an RS484 interface for much longer distances of legacy communication As the baseboard has been designed to allow for a lot of legacy interfacing including bringi
81. mo site From the menu above you can test all the DRIVERS currently loaded onto this board as well as options to check the date and time and all current proccessors running on the board If you have any quieres or issues please contact Nineways via the Contact Details link above Figure 19 Main opening screen for the NetFusion EXP Demo Website 51 doy ooooG e O OS research 9 and OOO development oooeo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 Ern y 7 Nineways Research and D bo em gt 10 1 17 drivers main html Ode NINE WAYS Research amp Development FUSIOn NetFusion Demo Site Home Drivers Temperature Sensor Voltage Supervisor DS1307 ACI LCD PCF Drivers for the NetFusion Product Above you will see the list of DRIVERS currently installed and operational on this NetFusion PCB They all have pre set parameters input which will output 4 basic operation for the particular driver If you have any quieres or issues please contact Nineways via the Contact Details link above Figure 20 Drivers Hardware Page for the NetFusion EXP Demo Website research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 9 Demo Application As part of
82. n 4 ulpi data out 3 BESEN ulpi data in 3 ulpi data out 2 T ulpi data in 2 ulpi data out 1 1 L BEES ulpi data in 1 ulpi data out 0 PFT rr ulpi data in 0 utmi linestate 1 0 TT utmi opmode 1 0 utmi datain 7 0 utmi dataout 7 0 1 SUN FAR LI Fam SmartFusion2 De M2SOSOT Pkg 484FBGA Verilog Figure 29 ULPI UTMI USB Converter IP Core 66 research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 3 CoreSF2Reset This core is used to co ordinate the reset across all of the FPGA in strict timed sequence It is important for the peripheral logic to be released after the MSS ARM processor and then the fabric logic following the MSS This is a standard Libero ACTEL core from the vault The EXT RESET OUT signal is routed out of the FPGA device to the NetFusion EXP PCB The input to this core is the POWER ON RESET This core was instantiated as CoreSF2Reset 0 Libero C Morethanip SmartFusion 50 Fus Project File Edit Design Tools SmartDesign Help Meonog x E 25050 SCH 484 X 22 55 502 Pw Aa CoreSF2Reset 0 MSS RESET POWER RESET EXT RESET IN N USER RESET IN RCOSC 25 5 2 CONFIG DONE CLR INIT DONE Fam SmartFusion2
83. n I O and all other slow speed communications are handled through this coreGP O 0 instantiated block It is visible to the ARM MSS processor via an APB interface memory bus Lines can be configured as inputs or outputs and are all individually controlled and observed by the uClinux UIO device driver E X GAD ECH 43120 DOES GPIO N31 Se E ss CoreGPIO 0 PRESEIN 21 POK XXXX a A Corel PRESETN ca PRESETN n miso 5 mos 5 sck sss cq PAK PRESEIN niso s nos 5 sck EX Figure 34 Main PCB GPIO Interface with APB bus from the ARM Processor MSS block 71 iol research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 7 NetFusion EXP IO EXP Daughter Card GPIO The IO EXP Daughter Card expansion slots on the NetFusion EXP PCB are connected through these cores The expansion slot functionality is handled through coreGP O 3 coreGPIO 4 coreGPIO 5 instantiated block and as a basic example for the user and all 72 GPIOs for the expansion daughter card are connected to these cores for the ARM processor software to handle It will in most cases of user development be changed from this processor visible design to a bespoke customer logic design but the initial design in this provided Libero project allows s
84. n the USB UART terminal session 20 Figure 9 Screen shot of allowing the boot process to execute uCLinux and initialize 21 Figure 10 Block Diagram Architecture of the NetFusion EXP main board 27 Figure 11 Inner FPGA Functional Block Diagram sese 28 Figure 12 USB UART PC Typical Settings Configuration ssssssseseeeneeneennenennn nens 29 Figure 13 An Example of a terminal screen connected through USB UART to Cortex M3 uCLinux 30 Figure 14 ARM JTAG Emulator amp enne enne 32 Figure 15 Other Examples of JTAG Emulation Hardware 33 Figure 16 A Standard typical 18V DC Desk Mains Guppiy sse 34 Figure 17 3 5mm Phono Plug 3 pin sese eene enne enne enne enne tener nennen 35 Figure 18 Expansion Slot Area 41 Figure 19 Main opening screen for the NetFusion EXP Demo 51 Figure 20 Drivers Hardware Page for the NetFusion EXP Demo 52 Figure 21 Libero 11 X IDE Boot Up Green 58 Figure 22 Libero Updating IP Core mthevauht eene 60 Figure 23 Example of Top List I O Ball Aesionments nennen 61 Figure 24 Example of Bottom List I O Ball Assignments sss 62 Figure 25 Selecting the UO Constraint
85. nIP All other used hardware on the NetFusion EXP PCB is wired and connected in the SOM sheet layer to SPI UART USB I2C etc as standard in the starter project If you decide to write and author your own IP cores in Verilog or VHDL you can drop and place the code into the Project Dir hdl directory Note Once you have started to customize and tailor the project to your own needs and functionality obviously renaming the project is easy just rename the project directory and inside that directory just rename the prj file Close and re open the Libero IDE research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 11 Downloading New IP Core s into the Libero IDE Installation Libero C Morethanip SmartFusic Project File Edit View Design Tools SmartDesign Help Dee amp sow x sow cass TOP X s 50 San a aa Fam SmartFusion2 Die 25050 Pkg 484FBGA Figure 22 Libero Updating IP Core in the Vault When you first load the NetFusion EXP starter project into the IDE the most likely occurrence to happen is a system message warning you to update New IP Cores This is because the design includes cores that you possibly do not have on your vault on your local hard drive Click YES to p
86. net SWITCH Development Kit Reference Guide V1 0 July 2015 SOM Connectors P1 P2 TX RX USB ULPI JTAG I F Ethernet 16MB SPI aa Reset Fiash Interfaces Controller Ethernet 10 100 i PHY 10 100 1000 EMAC SmartFusion2 18V LDO Regulator DDR MAIN OSC Cortex M3 Controller 12 MHz Main Crystal Figure 11 Inner FPGA Functional Block Diagram The NetFusion EXP Development Kit which is based on the NetFusion EXP PCB baseboard has two layers of functionality in hardware The first block diagram is the actual main PCB that houses the SOM The SOM contains the FPGA and the surrounding hardware echo system This is shown in the diagram directly above Essentially in both diagrams the SOM Headers are the same connector mated together research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 4 2 Component Description Details Before you read the sub sections on the hardware elements available to the user please refer to the NetFusion EXP Hardware Reference Guide PDF available from the Nine Ways R amp D website for all tables and pin outs that you can cross reference with the hardware listed and described below 4 2 1 USB UART Interface The NetFusion EXP PCB provides a USB UART interface on the type B mini USB co
87. nformation on the software architecture of the Linux SmartFusion2 distribution For more of the interested readers on the hardware resources for the NetFusion EXP PCB Robust Electronic Design Reference Book Volumes and 11 Surge Protection Reference Guide Emerson Network Power Earthing guide for surge protection MTL Instruments Group What s The Difference Between The RS 232 And RS 485 GMII Timing and Electrical Specification Design Resources FPGA amp SoC Products Microsemi Engineer s guide to High Quality PCB Design document research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 3 Out of the Box Development Kit Powering Up amp Programming The product should be presented boxed bubble wrapped and protected with anti static packaging Be careful not to static discharge yourself through the PCB as this can cause severe if not irreparable damage Note always try to use earth straps when handling the NetFusion EXP PCB 3 1 Kit Contents 1 x NetFusion EXP PCB with LCD nuts bolts screws washers 4 pillar legs for desk usage 1 x RJ45 Cat5 6e Ethernet patch lead 11 NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 1 x USB USB UART lead for using with PuTTY communicating with a terminal session 2 x Stereo phono jack to indi
88. ng modern high speed Ethernet communications alongside old infrastructure that needs supporting it is statutory that RS485 is at the heart of the system Just a single screw terminal header brings the R R T T 5V differential pair signal levels onto the NetFusion EXP baseboard in which they route through 2000V isolation protection in a level shifter LVTTL connects the level shifter IC with the SOM whereby they route through the SmartFusion2 FPGA fabric through a UART core which is addressable as memory from the UART device driver Unlike the RS232 interface there is only RX and TX functionality which are all handled by a single device driver which streams the received and transmitted data from the uCLinux environment MAX Distance End to End BAUD 125m 230400 300m 115200 900m 57600 1800m 38400 3000m 9600 5500m 1200 Table 2 RS485 Distance capabilities with respect to BAUD rate 4 15 Voltage Free Relays The NetFusion EXP hosts two mains voltage relays that can be used for user general purpose activity Each has a separate screw terminal connector for ease of installation and deployment and the voltage rating of such a switched secondary voltage is mains AC 110 230V Although the current throughput is limited to much less than 1000mA this mains switched voltage can be used to control further large industrial control beyond and away from NetFusion EXP The isolation voltage fo
89. nnector JP2 The interface is provided using an FTDI FT232RL USB UART bridge 033 The FT232RL UART TX and RX pins are connected to the SOM serial console UART port The main USB interface is a more default statutory interface for the reason of commanding the NetFusion EXP on loading code into the memory and viewing debug It is the main viewing portal for the Linux OS inside the SOM although a user customer can during run time change the usage of this port to suit their own needs The FL232 SM IC on the NetFusion PCB is a USB device that presents itself on a connected Windows Linux Mac PC as a USB Serial Device This has a programmed baud rate and other attributes as you would logically expect but the default is 115200 8 1 Basic options for your PuTTY session Specify the destination you want to connect to Serial line Speed COM3 115200 Connection type Raw Telnet SSH Load save or delete a stored session Saved Sessions Default Settings Close window on exit Always Never Only on clean exit Figure 12 USB UART PC Typical Settings Configuration fob research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 Target Console File Edit View Search Terminal Help Welcome to minicom 2 5 OPTIONS I18n Compiled on May 2 2011 00 39 27 Port dev ttyUSBO
90. nothing stopping the user from enabling and wiring out the modules to the SOM sheet The blue modules are currently enabled for the NetFusion EXP design as they have functional requirements and the signals are wired out to the SOM sheet then if necessary up to the I O assignments then out of the FPGA device itself 14 1 CAN Controller The CAN Controller shown in the above block handles the processing of the data streams in and out of the two transceiver buses The uCLinux environment is capable of supporting the hardware and is represented as a file descriptor in the typical UNIX way 88 d research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 14 2 MDDR MSS External Memory Configurator Import Configuration Export Configuration Restore Defaults General Memory Initialization Memory Timing p Memory Settings Memory Type Data Width 16 SECDED Enabled ECC Arbitration Scheme Type 3 HghestPotyD P o Address Mapping ROW BANK COLUMN Fabric Interface Settings Use AXI interface Use an AHBLite Interface C Use two AHBLite Interfaces Figure 53 MDDR MSS Controlling LPDDR Memory with AXI from Fabric The MDDR has been configured to use a single data rate LPDDR SDRAM device on the M2S SOM F484 using 16 bit data width Priority has been given to the AXI m
91. nsor temp_sensor c An on board temperature sensor on the baseboard Voltage PCB Supervisor vs_ad7998 c Monitor and check all voltages and rails on the PCB Expansion GPIO Controller Assert outputs and read inputs from the IOEXP CAN Controller Transceiver coreCAN c Data management and test of the CAN buses Table 8 Full NetFusion User Space Hardware Drivers Note the source files are located on your PC installed uCLinux cross compile environment in the netfusion source directory alongside the DMA Controller device driver source and the shell scripts For a fully extensive and detailed description of the entire user space hardware drivers of NetFusion EXP as a Development Kit please refer to the NetFusion Software uCLinux User Guide PDF iol 49 9 research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 7 SQLite Usage The SQLite is a specifically ported uCLinux orientated MySQL query binary application As discussed the Source code compiles to the binary using make However once the user is running and using in the target NetFusion uCLinux system a whole level of support and documentation is needed for those users who are not as familiar with the service Please refer to the following documentation SQLite Official Website Also type sqlite3 help on the NetFusion prompt for full descriptive options and us
92. nt M2S_SOM_FG484_TOP_ S constraint M2S_SOM_FG484_TOP_ 9 Floorplan Constraints gt Implement Design C Synthesize CL b Verify Post Synthesis Implement Figure 61 Importing a single Verilog VHDL file into the NetFusion EXP Libero Project From time to time you may want to deviate from the default NetFusion EXP Libero 11 X Starter Project If you need to add catalogue cores especially for the fabric macros then download using the vault Also as illustrated above you also may wish to import 3rd party source IP cores To do this on the panel on the left of the Libero IDE right click on Create HDL and then select Import Files This will bring the Verilog VHDL into the main system You can check if the source code has syntax errors and is valid for the synthesizer Libero 11 XSynplify Pro that Libero 11 X uses This mechanism enables the NetFusion EXP project to be customized and built on for a user s system requirement iol 96 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 15 2 Instantiating into the Fabric Libero C WetFusion M2S SOM F484 CAT5NetFusion F484 prjx Project View Geess Tools 35 2 m Desic m x Suz m x 25050 soM rasa s x oe 2 om nea EDIT ua OW work mm LL lM A XTLOSC FAB osc_comps v B RCOSC_1MHZ_FAB osc_comps v E
93. nt nnn 54 9 1 RJ45 PLUG AND CAT5 6E CABLE CONNECTIONS nennen nennen nnn nnne en 54 10 SMARTFUSION2 FPGA NETFUSION EXP FABRIC DEVELOPMENT 56 10 1 LIBERO SOC IDE VERSION 11 X DERWMATIWVES enne nennen nennen nn nnn nennen 56 10 2 INSTALLATION p 57 10 3 STARTING A PROJECT AND BASIC UNDERSTANDING isset 57 10 3 1 Libero 11 X IDE First La nch itte eee 58 10 4 leie ae edere D Heed 58 10 5 PRODUCT DEVELOPMENT eee ir eic dev ed ga V et 59 11 DOWNLOADING NEW IP CORE S INTO THE LIBERO IDE INSTALLATION 60 12 NETFUSION EXP LIBERO UO 55 8 1 1 1 nennen 61 13 NETFUSION EXP LIBERO 11 X IDE SOC 1 1 63 13 1 EMCRAFT SYSTEMS cssssoianenini kucana inaaianei a a a aa A TA a aa aaa aaa 65 13 2 ULPI UTMI OTG USB MEM 66 13 3 CORESF2RESET aaa aaa aiaa eeu daa eas eastside 67 13 4 CG 68 13 5 COUNTER COREGPIO REN 70 iol NINE WAYS research and development NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 13 6 NETFUSION EXP BASEBOARD PERIPHERAL 71 13 7 NETFUSION EXP IO EXP
94. ntroller A 90 Figure 55 MSS MAC for 10 100 Ethernet Using SOM PHY sse eene enne 91 Figure 56 MSS CCC Divider from the CLK BASE with in ARM Sub System 92 Figure 57 Reset MSS Module eene teens 92 Figure 58 AHB APB Fabric Interface fl 93 Figure 59 APB3 AHB Lite Fabric Interface DI 94 Figure 60 APB Peripheral Hardware Confiouration eene 95 Figure 61 Importing a single Verilog VHDL file into the NetFusion EXP Libero 96 Figure 62 Instantiating an Imported IP Core in your Fabric 97 Figure 63 Selecting Full NetFusion EXP Synthesis and FPGA 99 Figure 64 Opening screen of FlashPro IDEA 100 Figure 65 Microsemi FlashPro4 ribbon connection 0000600 00 6000 00050508 101 Figure 66 FlashPro Programming Green 101 List of Tables Table 1 Voltage and Current Consumption on Power Supply 16 Table 2 RS485 Distance capabilities with respect to BAUD rate 000000000 38 Table 3 Summary of PCB Connectors sse eene 44 Table 4 IDC Connector J4 Customer Interface 45 Table 5 IDC Connector J5 Customer Interface 46 Table 6 IDC Conn
95. ontact Nine Ways Research amp Development Ltd V1 0 July 2015 E Mail pbates nineways co uk Internet WWW nineways co uk UK Unit A 3 iDCentre Lathkill House rtc Business Park London Road Derby DE24 8UP United Kingdom Tel 44 0 1332 258847 FAX 44 0 1332 258823 iol 106 research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 20 Document History Document Change Notices DCO Version Description Created Changed By Date Version 1 0 Initial Release according to Paul Bates Nine Ways 12 July 2015 Version 1 0 Copyright Nine Ways R amp D Ltd 2015 All Rights Reserved Table 10 Document History Entry Log 107
96. ovide for audio line IN and audio line OUT The usage can obviously go beyond audio as the sampling rate of the DAC ADC devices can extend as high as 41 5kHz The SPI DACs sample at MHz but in practice the software pipelines for the data can only cope with kHz Figure 17 3 5mm Phono Plug 3 pin 35 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 Analogue waveforms incoming through both left and right channel of the audio line IN are sampled by an ADC This is polled and read over SPI by application software The same happens in reverse for the audio line OUT left and right channels Line OUT impedance 100ohms Line IN impedance 8 2 Note they appear to the uCLinux environment as pipes of data streams from the UIO audio drivers 4 10 Temperature Sensor This device does not appear as a connector on the NetFusion EXP baseboard Specifically it is an on board component that checks and monitors the state of the PCB The temperature sensor IC is located on the surface of the PCB where the temperature is likely to be the hottest This can be used by the application code and the user customer to check for overheating and send warnings to a control station for instance The temperature IC sends a square wave signal with an even duty cycle that has a cyclic Hz rate equal to the temperature in Kelvin degrees So 2
97. ovided for this function It is for the user to install their specific surge and noise suppression if it is deemed necessary Critical Do not expose more than 5 5V to these inputs absolute maximum rating 4 17 Earth and Lightning Protection Power supplies to industrially installed components should be robust and fully protected against short circuit and overvoltage conditions including lightning strikes NetFusion EXP s legacy interfaces all have heavy duty lightning protection devices which protect the main system board from lightning strikes but to ensure maximum protection the earth terminal spade on the baseboard must be connected to a good quality earth located close by using a deep spike or lattice 39 e research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 4 18 LED Indicators There are two RED power LEDs that indicate 2 5V rail and 5V rail levels From this diagnosis of a faulty baseboard is much easier if it is visual as to whether the power regulators and the DC DC module are to blame Dim RED power LEDs can also indicate a near short or faulty component with the NetFusion EXP PCB A GREEN user LED is controlled fully by the application programs via the GPIO UIO device driver This is for general purpose usage by the user customer A set of RED RX and TX LEDs are driven from the FL232 USB UART device on NetFusion EXP
98. ower Connected to Receptacle Q2 This method of connection is ideal for desk evaluation development and test It avoids the cumbersome bench supply and allows for product usage when there is no industrial supply If you use NetFusion EXP as a Development Kit for instance this supply will be provided with the delivery research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 3 3 2 Screw Terminal Installation Figure 3 Screw Terminal P Whilst only one of the two pairs of power is necessary having a dual approach allows for daisy chaining equipment or having two parallel bench or industrial power available if current is limited to less than 500mA per output unit 3 3 3 Output 5V Auxiliary Next to the two screw terminal power supply connectors is a 5V DC derived output supply This is generated on board NetFusion EXP and can be used to supply external TTL CMOS peripheral devices connected to the baseboard This may not be necessary when powering up the board for the first time or getting started but it is mentioned so that you do not get this confused with the input DC power supply connectors Please Note maximum current delivery capability of the auxiliary supply is 350mA 5V 17 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V
99. r safety purposes is rated at 3500V if transient or surge spikes affect the relay wiring In fact the baseboard houses an inner solid state relay inside of the mechanical set to further protect the SOM device controlling the whole PCB Control of the relays is obtained with an uCLinux device driver for the GPIO The ON or OFF state is driven through a core in the FPGA fabric which then routes to a set of selector switches on the PCB located in close proximity to the relays on the PCB These selectors allow for the relay signals to be used in the GPIO interface instead if the relays are not required If the relays are selected then the signals connect to the inner solid state relays then to the main mechanical set Note normally open NO and normally closed NC controlled by other selector switches iol 38 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 4 16 Analogue Contact Inputs ACI The most un talked about feature of NetFusion EXP is actually one of its best functions it can provide the user There are 8 screw terminal connectors that individually each allow for an analogue input The connectors are all individual as this makes wiring and interfacing in an installed and deployed environment especially in tight or restrictive spacing Each input is biased with a 5V pull up on the positive pin and GND on the other This vol
100. r should be automatically installed with the FlashPro installation which is downloadable from the Microsemi website 100 research 9 and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 Ensure that the NetFusion EXP PCB has the ribbon cable attached from the FlashPro4 USB programmer below Figure 65 Microsemi FlashPro4 ribbon connection On the FlashPro IDE screen click on New Project Enter any project name and make sure you have write permissions to the selected directory you choose 72 FlashPro a 0 File Edit View Tools Programmers Configuration Customize Help EE Configure Device View Programmers oi gt pen Project a Programmer Programmer Port Programmer Programmer Name Type Status Enabled 1 80945 FlashPro4 usb80945 USB 2 0 v 1x Programmer List Window Refresh Rescan for Programmers creating folder C dell a Driver 3 0 0 build 1 programmer 80945 FlashPro4 Created new project 11 4 m A Errors Warnings Info Ready no programming file loaded SINGLE Figure 66 FlashPro Programming Screen 101 9 research 9 and development NINE WAYS NetFusion EXP Ethernet SWI
101. reate another window in Libero 11 X on screen Note Refer to the next section for the MSS documentation V1 0 July 2015 Libero CAMorethaniplmartFusion Project File Edit Design Tools SmartDesign roye 15 07 gt sow x E 25050 SOM FG484 TOP X QE 22525252 Aq ANO MDCR BA MDDR 005 TMATCH 0 IN NFO DNET gos 535 Z gx TA lt 58 g kE a M2S SOM MSS 0 MCOC QLK BASE FIG 2 AFB M FRESET MCCC QLK BASE LOOK FIC 2 M ME S FRESET H NM MDDR S F COMM BLK INT MSS RESET N F2M MSS RESET M2F M3 RESET N WD TIMEOUT MDER DDR CORE RESET 55 INT 2 150 B DOR AXI 5 RMW 1 P EMSS F2 150 MMUART 1 PADSEI L MSS NT F2W15 MMUART 1 D I XB MSS INTF2M 14 MMUART 1 RXD ZK uss NrF2M13 0 PADSEI XB veM Faw FA BRICE ZK MSS NTF2M MAC MI 03 0 4 MSS INT F2M 10 MAC MIL TX EN LR MSS INT FMO MAC MILTX t ZK MSS NT FMS 0 XB MSS NLF2M7 MAC MI RX ER Lp MSS INT FMS MAC MIL RX DV ZK MSS NT FM MAC MI CRS gt MSS INTF2M MAC MI COL A MSS Ha MAG MM RCOK LB MSS NTF2M MAC MI TX CLK SNFA MAC MI MSS INT EA MAC MI
102. roceed and let the download process complete Note this may take several minutes and you MUST have a network connection and gateway to the internet 60 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 12 NetFusion EXP Libero I O Assignments NetFusion EXP Libero starter project is delivered already with the I O balls of the FPGA assigned ready for the user These all correspond with the pin out tracking assignments on the NetFusion EXP PCB product This means that you will not have to consider any of these assignments unless you are planning any major changes to the inherent default design This is very unlikely as you would need then to request changes to the PCB design However this section highlights the assignments in case you also want to make minor changes to the direction of the port default output values and or change internal SmartFusion2 FPGA pull up values VO Editor 25 SOM ra Die Edit View Tools ee ep Pors Package Pins Package Viewer Port Name t Direction v VO Standard Pin Number MacroCel v BenkName v VO state in Flash Freezemode v Resistor Pull VO available in Flas Freezemode v Schm a 1 Inout 1VCMOS25 ADLIE BIBUF Bank TRISTATE None No 22 2 Inout 0525 K2 ADLIE BIBU
103. roject linux cortexm 1 xx x projects netfusion make Finally prepare the newly generated uCLinux kernel package binary for TFTP upload linuxPC Project linux cortexm 1 xx x projects netfusion savetftp 24 EN research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 3 5 3 Uploading the kernel to the NetFusion To load the image directly use the netboot u boot macro M2S SOM gt setenv image netfusion uImage M2S SOM gt run netboot from server 122 017 0 1 our IP address L 2 17 5 100 Filename networking uImage Loading FEE E AE E AE FE FE E E AE FE FE FE E AE E AE FE AE FE E AE AE AE FEAE FE AE AE FE FE E E AE FE AE E E AE E AE FE AE FE AE AE FE AE AE AE FE AE AE AE FE FE AE AE FE AE AE EHE E FEAE AE AE AE AE FE FE HH E done Bytes transferred 2084704 1fcf60 hex Image Name Linux 2 6 33 ar ml Image Type ARM Linux Kernel Image uncompressed Verifying Checksum OK Loading Kernel Image OK OK Starting kernel Linux version 2 6 33 arml gcc version 4 4 1 Sourcery Gt Lite 2010q1 189 1 Fri Dec 06 15 43 44 MSK 2013 To load the image into the flash use the u boot upaate macro M2S SOM gt setenv image netfusion ulImage M2S SOM gt run update
104. s enne 62 Figure 26 NetFusion EXP Top Level Sheet sssscssssssscsssscssssssssessssesessesesseseesessenensessessnsessensnsensenensenses 63 Figure 27 Lower Level SOM sheet MSS block 64 Figure 28 Screenshot of Lower Level SOM sheet of the Starter Pack Libero 65 Figure 29 ULPI UTMI USB Converter IP Core 66 Figure 30 SmartFusion2 Reset Controller IP Core 67 Figure 31 Clock PLE Macro Core isis sitter ees Ete 68 Figure 32 PLE Clock Macro Settings tiene tito epe theirs eet 69 Figure 33 Temperature Sensor LOgiC eterne eene trente theater ek teeth eee ta esaet eene eh inre eret 70 Figure 34 Main PCB GPIO Interface with APB bus from the ARM Processor MSS block 71 Figure 35 Main CoreGPIO for the Daughter Card Expansion slots esee 72 Figure 36 Bi Directional Buffers for the Daughter Card Expansion slots sss 73 Figure 37 CAN Controller Interface Logic eene 74 Figure 38 RS485 UART IP COFG nitet retten reet tre err teret rro erre 75 Figure 39 Stereo Audio Line IN amp Line OUT eese eene teen 76 Figure 40 Temp Sensor Counter 2 2 2 412 2402 224 ener enne nennen enne nennt enne 77 Figure 41 Customized RESET Jg 5
105. sis Ground research 000 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 6 Hardware Device Driver Support Netfusion EXP currently has 11 x user space hardware drivers They are compiled as applications all separate to each other and are structured and designed such that they interface to the NetFusion EXP PCB hardware via resource protected memory accessible FPGA IP cores The driver establishes the lt Uiox gt interface between the hardware and the user space During normal operation i e when the user space application accesses the hardware no additional software layers are involved Memory accesses performed by the software are directly interchanged with the hardware Name of Driver Source File Description Analogue Contacts ACI aci ad7998 c Read analogue voltages from connector input RS485 UART coreUART c Data in out through RS485 bus interface Real Time Clock RTC ds1307rtc c Separate PCB baseboard battery backed clock LCD Controller pcf5074 c LCD optional display controller of text and format General I O GPIO pcf5074 c Individual spare pins and the LEDs Switches amp Jumpers Line OUT Stereo Audio spi_audio_line_out c Stream digital audio to analogue Line OUT audio Line IN Stereo Audio spi_audio_line_in c_ Line IN audio analogue to digital output stream PCB Temperature Se
106. tage applied input allows for relays of other equipment to close or keep open the input as a form of legacy communication and furthermore the analogue orientation allows for parallel and series tamper resistors to be used to detect sabotage attempts Other uses for these inputs could be to directly measure and monitor scaled proportional voltages of 3 party connected equipment These inputs are compatible with other voltage applied equipment that assert their own 5V reference voltage as NetFusion EXP only uses a weak pull up resistor to its own 5V Note t is feasible to use these as high frequency sampling of the voltages However new device drivers will have to be implemented in the uCLinux system Each of the 8 Analogue Contact Inputs AC is read by an ADC device on the PCB which is accessed from the SmartFusion2 fabric via an I2C bus The core in the fabric is GPIO which is memory addressable from the Cortex M3 processor This allows our uCLinux device driver to read the voltage readings and present them to user application code It is for the user to decide how to use these input when they tailor NetFusion EXP as their own product and the possibilities of usage are widespread such as linking to the SQLite database in our uCLinux system and then displaying on a webpage for instance Important Note Due to sensitive analogue input levels clamping and in line protection to unwanted harsh electric voltage spikes transients etc are not pr
107. tects accidental voltage damage and or incorrect wiring from harming the silicon device All voltage 3 3V are clipped both positive and negative amplitudes and the current is dissipated via the EARTH conductive holes to the Netfusion EXP baseboard e Red power LED to indicate the separately generated 3 3V is good 42 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 5 1 Daughter Card Design The EXP daughterlO card is the first generic I O expander for the Netfusion EXP variant product On its own the NetFusion EXP cannot be easily interfaced to via the expansion Hirose connectors from the baseboard This is because the connectors have to be of high quality low attenuation high frequency and low noise as any wide range of usages can be created as an expansion card This EXP daughterlO allows a simple 72 GPIO line interface from the SmartFusion2 FPGA on the SOM to be interfaced to the outside world via IDC headers The headers will provide useful 3 3V and GND for pull ups and GND referencing etc As the SmartFusion2 has different voltages for some banks of signals some of the I O is 3 3V and the rest 2 5V This mixes LVTTL 3 3 with LVCMOS25 2 5 and over volt aging an input can damage the FPGA over time Moreover the lines used as outputs at 2 5V may not drive a device needing 3 3V close threshold and certainly would not provide
108. the instantiation will not occur iol 97 research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 15 2 1 Building and Synthesizing the NetFusion EXP Design Open the Top Level SOM and the MSS sheets Start with the MSS and right click Generate Component If errors eliminate then perform previous instruction over again Once successful move to the SOM sheet Right click Generate Component If errors eliminate then perform previous instruction over again Once successful move to the Top Level sheet Right click Generate Component If errors eliminate then perform previous instruction over again 98 EN development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 Libero C NetFusion M2S SOM F484 CATS5 NetFusion F484 prjx Project File Edit View Design Tools SmartDesign Help E 25 50 x t BB Del c MESS o o i Floorplan Constraints E b Verify Post Layout Implementation sl Generate Back Annotated Files ll simulate Ch Verify Timing f verify Power P Edit Design Hardware Configuration Programming Connectivity and Interface amp Programmer Settings iii Device I O States During Programming Configure Security and Programming Security Policy Manager Bitstream Configuration Update eNVM Memory Content
109. tors When using this function make sure that the option jumper L NK setting is correct for the JTAG mode Figure 14 ARM JTAG Emulator amp Debugger For specific information on the usage and the datasheet of the Cortex M3 ARM Debugger please refer to the following document Download JTAGJET CORTEXMS datasheet 32 research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 There are other manufacturers of similar applicable products that interface with the M3 Debugging JTAG interface below Figure 15 Other Examples of M3 JTAG Emulation Hardware 4 4 BNC Coax Sockets The 4 x BNC bayonet sockets situated in the middle central area of the NetFusion EXP baseboard allow for a screened coax cable transmission of the audio line IN and audio line OUT function Whilst these are already provided as 2 x 3 5mm phono jacks elsewhere on the board the BNC feature allows for either oscilloscope analysis for clean noise free observation or for critical clean analogue waveforms to be shielded from surrounding industrial environmental interference All of the BNC sockets are labeled on the PCB so installation engineers or development programmer can access and identify which channel and direction of the audio with each connector For audio line IN there are stereo left and right channels and the same with the audio line OUT 4 5 Power Supply
110. uild list and the user can choose their own Why is the USB OTG connector not available by default out of the box As the USB UART interface allows all of the initial start up interfacing the user requires there is no point in providing a second USB The user can use the OTG interface to suit their own needs once they start to develop their own customization and product development This is done through the ULPI USB core in the MSS of the SmartFusion2 ARM environment Why are the power supplies over engineered and the interfaces highly clamped and protected The voltage regulators and the dc dc modules are highly designed for noise transient surge and ESD suppression This gives rise to an industrial capability with EM certification which is extremely useful with customer requirements and an added advantage over rival solutions Can l use the LCD buttons without the LCD present Yes these are just normal input signals to the SOM GPIO What is the battery used for on the PCB The baseboard housed Real Time Clock which can continue maintaining a time for 3 years When the power is applied to the NetFusion EXP PCB the battery is re charged slowly up to full charge Do we really need such a wide range power voltage input This is for the many wide range of power supplies used and already deployed in industry around the world Obviously little power is wasted as NetFusion EXP uses a dc dc module so that a higher voltage uses less current
111. ummary Table 3 Summary of PCB Connectors Connector Description J1 J2 SOM header interface connectors J5 J6 Input Output IDC customer 20 way connectors J4 Output ONLY IDC customer 20 way connector J7 Input ONLY IDC customer 20 way connector J3 3 3V test probe point research and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 5 7 2 Customer IDC Outputs ONLY Connector J4 Table 4 IDC Connector J4 Customer Interface Pin Signal Type NetFusion Usage 1 3 3V POWER Separately generated 3 3V 2 IOEXP24 Output SmartFusion2 050 F484 ball N8 bank 5 3 IOEXP35 Output SmartFusion2 050 F484 ball Y9 bank 5 4 IOEXP37 Output SmartFusion2 050 F484 ball W9 bank 5 5 IOEXP39 Output SmartFusion2 050 F484 ball Y10 bank 5 6 41 Output SmartFusion2 050 F484 ball W10 bank 5 7 IOEXP43 Output SmartFusion2 050 F484 ball W11 bank 5 8 IOEXP45 Output SmartFusion2 050 F484 ball V11 bank 5 9 IOEXP47 Output SmartFusion2 050 F484 ball 773 bank 5 10 IOEXP64 Output SmartFusion2 050 F484 ball M7 bank 7 11 IOEXP66 Output SmartFusion2 050 F484 ball 17 bank 7 12 IOEXP70 Output SmartFusion2 050 F484 ball AB15 bank 5 13 IOEXP72 Output SmartFusion2 050 F484 ball AA15 bank 5 14 IOEXP42 Output SmartFusion2 050 F484 ball H7 bank 8 15 IOEXP44 Output SmartFusion2 050 F484 ball J6 bank 8
112. ver voltage or incorrect connection 5 3 Power Supply The 5V from the baseboard is used to generate U1 a new 3 3V on the daughter card The incoming 5V are supplied from the DC DC source on the NetFusion EXP baseboard PCB and can deliver high current The 3 3V on the daughter PCB then provides power to the IDC target board via the IDC ribbon cabling This can be used for pull ups for instance or to power active circuit logic and devices iol 43 SC research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 5 4 Power Test Test point J3 above the RED LED allows for inspection of the 3 3V power rail from the daughter card regulator U1 5 5 IDC Interfaces Connectors J4 J5 J6 and J7 provide the simple customer interfaces These can provide up to 10MHz signaling with little attenuation or noise Power and GND are provided and all signals GPIO are bi directionally capable The exceptions are J4 output ONLY and J7 input ONLY 5 6 Earth Protection The holes in the PCB either side of the Hirose mating connectors are the stabilizing and structural holes for screw and nut mounting They are also conductive with the EARTH for power dissipation of ESD and low current induction Metal washers and stand offs are recommended here to the NetFusion EXP baseboard PCB 5 7 Daughter Card Expansion I O Connectors 5 7 1 Connector S
113. vidual socket phono cables this is often supplied as metal plugs for the user to solder to with their own cabling shown on the right above 1 x RS232 Straight modem cable 12 research 9 and development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 1 x 19V 120W desk mains supply 110 230V 50 60Hz Depending on the country of order the mains plug will be one of the following 1 x British Plug cable 1 x Euro Plug cable OR 1 x USA Standard Plug cable 13 Q development NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 Slot on the EXP Daughter Card PCB This just utilizes the top space on the overall much larger expansion area on the NetFusion Exp base board You do not have to worry about fixing into the screw holes for this test either AM TIE i Te 1 x Expander I O the Dev Kit always has this even if the user wishes to use their own designed plug in board eventually Note 7he ribbon cable shown are not included 14 research and development eo NINE WAYS NetFusion EXP Ethernet SWITCH Development Kit Reference Guide V1 0 July 2015 3 2 Applying Power The product should be presented boxed bubble wrapped and protected with anti static pac

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