CYPD1120 Datasheet USB Power Delivery Alternate
Contents
1. Spec ID Parameter Description Min Typ Max Units Details Conditions SID153 Fioct Bit rate 1 0 Mbps Memory Table 11 Flash DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID173 VpE Erase and program voltage 1 8 5 5 V Table 12 Flash AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions Row block write time erase SID174 Trowwarre ROY BS 200 ms Row block 128 bytes SID175 Trowerase Row erase time 13 0 ms SID176 TROWPROGRAMI Row program time after erase 7 0 ms SID178 TBULKERASEL Bulk erase time 32 KB 2 35 ms SID180 Tpoeverog Total device program time 7 0 ete Guaranteed by characterization SID181 FEND Flash endurance 100K cycles Guaranteed by characterization 9 Flash retention TA lt 55 C _ m SID182 FRET 100 K P E cycles 20 years Guaranteed by characterization Flash retention TA lt 85 C NUN SID182A 10 K PIE cycles 10 years Guaranteed by characterization Flash retention 85 C lt TA TA SID182B x 105 C 10K P E cycles 3 years Guaranteed by characterization System Resources Power on Reset POR with Brown Out Table 13 Imprecise Power On Reset PRES Spec ID Parameter Description Min Typ Max Units Details Conditions SID185 VRISEIPOR Rising trip voltage 0 80 1 45 V Guarante2. Spec ID Parameter Description Min Typ Max Units Details Conditions SID140 TPWMFREQ Operating frequency 48 0 MHz SID141 TpwMPwiNT Pulse width internal 42 0 ns SID142 TPWMEXT Pulse width external 42 0 ns SID143 TPwMkiLLINT Kill pulse width internal 42 0 ns SID144 TPwMkiLLExr Kill pulse width external 42 0 ES ns SID145 TPWMEINT Enable pulse width internal 42 0 ns SID146 TpwMENExr Enable pulse width external 42 0 ns SID147 Tpwmreswint Reset pulse width internal 42 0 ns SID148 Tpwmreswext Reset pulse width external 42 0 7 ns FC Table 9 Fixed I C DC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Conditions Block current consumption at SID149 li2c1 100 kHz 10 5 pA Block current consumption at SID150 lice 400 kHz 135 0 HA Block current consumption at 1 SID151 ljcs Mbps P z Z 310 0 pA I C enabled in Deep Sleep SID152 loca mode 1 4 UA Document Number 001 96786 Rev A Page 11 of 24 ae 2 j ames Z CYPRESS PERFORM Table 10 Fixed I C AC Specifications Guaranteed by Characterization CYPD1120 Datasheet
3. Spec ID Parameter Description Min Typ Max Units Details Conditions SID213 F_SWDCLK1 33V lt Vppp lt 5 5 V 140 MHz ong Ua Gr eines SID244 F SWDCLK2 1 8V lt Vppp lt 3 3V 70 MHz Miseni 1 3 CPU glock SID215 T SWDI SETUP T 1 f SWDCLK 0 25 T ns Guaranteed by characterization SID216 T SWDI HOLD T 1 f SWDCLK 0 25 T ns Guaranteed by characterization SID217 T SWDO VALID T 1 f SWDCLK 0 5 T ns Guaranteed by characterization SID217A T SWDO HOLD T 1 f SWDCLK ns Guaranteed by characterization Internal Main Oscillator Table 16 IMO DC Specifications Guaranteed by Design Spec ID Parameter Description Typ Max Units Details Conditions SID218 limo IMO operating current at 48 MHz 1000 0 pA Table 17 IMO AC Specifications Spec ID Parameter Description Typ Max Units Details Conditions SID223 Fimoto1 Frequency variation 2 0 With API called calibration SID226 TsrARTIMO IMO startup time 12 0 Hs SID229 T JITRMSIMO3 RMS Jitter at 48 MHz 139 0 ps Internal Low Speed Oscillator Table 18 ILO DC Specifications Guaranteed by Design Spec ID Parameter Description Min Typ Max Units Details Conditions SID231 jo ILO operating current at 32 kHz 0 30 1 05 pA Guaranteed by characterization SID233 li oi gAK ILO leakage current 2 0 15 0 nA Guaranteed by design Table 19 ILO AC Specifications Spec ID Parameter Description Min Typ Max Units D
4. Ordering Code Definitions CY PD X XXX XX XX XXX T Tape and reel for CSP N A for other packages Temperature Range Industrial Q Extended industrial Lead X Pb free Package Type LQ QFN FN CSP Number of pins in the package 0X OCP and OVP not supported 1X reserved 2X 3X OCP and OVP supported Number of Type C Ports 1 1 Port 2 2 Port Product Type 1 First generation product family CCG1 Marketing Code PD Power delivery product family ie Company ID CY Cypress Notes 10 All part numbers support Input voltage range from 1 8 to 5 5 V Industrial parts support 40 C to 85 C Extended Industrial parts support 40 C to 105 C 11 Number of USB Type C Ports Supported 12 Default Vconn Termination 13 PD Role 14 Type C Cable Termination 15 35 WLCSP 1 pinout 16 40 QFN 3 pinout 17 Downstream Facing Port Document Number 001 96786 Rev A Page 18 of 24 _ gt QU CYPRESS CYPD1120 Datasheet PERFORM Packaging Table 21 Package Characteristics Parameter Description Conditions Min Typ Max Units T4 40 QFN 35 CSP Operating ambient temperature 40 25 00 85 C Ty 40 QFN 35 CSP Operating junction temperature 40 100 C TJA Package 0JA 40 pin QFN 15 34 C Watt TJA Package 0JA 35 CSP 28 00 C Watt Tuc Package 0c 40 pin QFN 02 50 C Watt Table 22 S
5. Wu 1 Q d NU CYPD1120 Datasheet lt had A b em B lt SWD_CLK C a gt D L DP_AUX_C E e wy Page 6 of 24 _ ZA CYPRESS PERFORM Power The following power system diagram shows the minimum set of power supply pins as implemented for the CCG1 The system has one regulator in Active mode for the digital circuitry There is no analog regulator the analog circuits run directly from the VDDA input There is a separate regulator for the Deep Sleep mode There is a separate low noise regulator for the bandgap The supply voltage range is 1 8 V to 5 5 V with all functions and circuits operating over that range The CCG1 is powered by an external power supply that can be anywhere in the range of 1 8 V to 5 5 V This range is also designed for battery powered operation For example the chip can be powered from a battery system that starts at 3 5 V and works down to 1 8 V In this mode the internal regulator of the CCG1 supplies the internal logic and the VCCD output of the CCG1 must be bypassed to ground via an external capacitor in the range of 1 pF to 1 6 uF X5R ceramic or better No voltage source should be applied to this pin CYPD1120 Datasheet VDDA and VDDD must be shorted together the grounds VSSA and VSS must also be shorted together Bypass capacitors must be used from VDDD to ground The typical practice for systems in this frequency range is to use a
6. Document Conventions Units of Measure Table 25 Units of Measure Symbol Unit of Measure C degrees Celsius Hz hertz KB 1024 bytes kHz kilohertz kQ kilo ohm Mbps megabits per second MHz megahertz MQ mega ohm Msps megasamples per second pA microampere uF microfarad Hs microsecond uV microvolt uW microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond Q ohm pF picofarad ppm parts per million ps picosecond S second sps samples per second V volt Document Number 001 96786 Rev A Page 22 of 24 CYPD1120 Datasheet _ SSF CYPRESS PERFORM Revision History Description Title CYPD1120 Datasheet USB Power Delivery Alternate Mode Controller on Type C Document Number 001 9678 ei Orig of Submission Revision ECN Change Date Description of Change di 4686071 VGT 05 13 2015 New datasheet A 4829889 VGT 07 20 2015 Added CYPD1120 40LQXIT in Ordering Information Page 23 of 24 Document Number 001 96786 Rev A ies F CYPRESS CYPD1120 Datasheet PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at Cypress Locations Products PSoC Solutions Auto
7. 20kQ 1 VCONN ES CC1 LPREF 100k 1 IRA DISCONNECT 100kQ 1 VCONN DET cc Z54kQ 196 24kOQ 1 WW 02 2kQ 1 SBU 1 2 cc1 TX CC1 RX CC1 LPRX 40QFN TX REF OUT TX REF IN CC VREF AUX CH AUX CH DP AU P CTRL N CTRL X CTRL CYPD1120 40LOXI VCCD 1uF 25V SWD_IO 10 SWD_CLK VBUS TX U 20 TX M 400kO 1 vBUS per 2 ANN h 100kO 1 HOTPLUG_DET GPIO 0 GPIO 1 GPIO 2 GPIO GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 8 XRES O 01uF L 25V Tio 47pF L 25V 25 221 10 HotPlug Detect ADC_BYPASS BYPASS TX GND 8 7 Display Port Data Lanes SW for AUX AUX P N HDMI DVI aav 1Y VGA Receptacle DP to HDMI DVI VGA Convertor Document Number 001 96786 Rev A Paddle Card on Type C Plug Page 17 of 24 CY PRESS CYPD1120 Datasheet PERFORM Ordering Information The CCG1 part numbers and features are listed in the following table Table 20 CCG1 Ordering Information Part Number Application paper DOOR A Ea EEREN Role 3l Package SiID CYPD1120 35FNXIT D P E 1 No No RJ 4 Cable 35 WLCSPI 8 0492 CYPD4120 40LQXI D I HOM 1 Yes Yes Ra DFPI 7 40 QFN SI 0488 CYPD1120 40LQXIT ia t DM 1 Yes Yes Ra pFPI 7 40 QFN SI 0488
8. Regulator USB Billboard SDA XRES INT SOH 2 2kQ 5 D6 A2 B1 B2 2 2kO 5 BILLBOA 2c_ 2C SCL I2C SDA RD CTRL INT SWD IO SWD CLK IRA DISCONNECT VBUS DET HOTPLUG DET CYPD1120 35FNXIT 35CSP BYPASS TX GND AUX CH AUX CH DP AU TRL N CTRL X CTRL GPIO_0 ADC_BYPASS VCCD CYPD1120 Datasheet 1uF 25V 10 VBUS TXU TXM A00KQ 1 SA aen 100kO 1 HotPlug Detect VSSA E2 E3 Et 3 3V 1 2V HDMI DVI SW for AUX AUX PIN D VDDD 100kQ 1 T CC1_LPREF 9 UCONN 20kQ 1 100ko 1 1 IVCONN DET S 100ko 1 i lcc1 TX CC ICC1_RX CC1 LPRX 54kO 1 TX REF OUT 24kQ 1 W TX REF IN oo CC VREF 2ko 196 H P SBU 1 2 Display Port Data Lanes Document Number 001 96786 Rev A VGA Receptacle DP to HDMI DVIVGA Convertor Paddle Card on Type C Plug Page 16 of 24 Type C Plug BuckBoost Regulator D CYPD1120 Datasheet USB Billboard SDA xRES INT SCL 2 2kO 5 1 20 18 2 2kO 5 19 BILLBOA I2C INT I2C SCL I2C SDA Um RD CTRL 100kQ 1965 VDDA
9. uses 16 bit instructions and executes a subset of the Thumb 2 instruction set This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex M3 and M4 thus enabling upward compatibility The Cypress implementation includes a hardware multiplier that provides a 32 bit result in one cycle It includes a nested vectored interrupt controller NVIC block with 32 interrupt inputs and a Wakeup Interrupt Controller WIC The WIC can wake the processor up from the Deep Sleep mode allowing power to be switched off to the main processor when the chip is in the Deep Sleep mode The Cortex MO CPU provides a Non Maskable Interrupt NMI input which is made available to the user when it is not in use for system functions requested by the user The CPU also includes a debug interface the serial wire debug SWD interface which is a 2 wire form of JTAG the debug configuration used for CCG1 has four break point address comparators and two watchpoint data comparators Flash The CCG1 device has a flash module with a flash accelerator tightly coupled to the CPU to improve average access times from the flash block The flash block is designed to deliver 1 wait state WS access time at 48 MHz and 0 WS access time at 24 MHz The flash accelerator delivers 85 of single cycle SRAM access performance on average Part of the flash module can be used to emulate EEPROM operation if required SROM A
10. 196 SBU 1 2 AUX_PIN SW for AUX Display Port Data Lanes Document Number 001 96786 Rev A Page 14 of 24 7 CYPRESS CYPD1120 Datasheet PERFORM Figure 7 Type C to DisplayPort mini DisplayPort Application Using 40 QFN Package Paddle Card on Type C Plug Regulator Dil USB Billboard SDA XRES INT SCL ve 22kQ 5 2 2kO 5 100ko 1 T o 1 20 hs 19 Lap T4128 BILLBOA 12C_ I2C SCL 12C_SDA 80014 sig RD CTRL INT 19 2 78 duF 100k2 1 VDDA vecD avi 1 1uF iT CC1_LPREF Lasy VGONN 20kQ 1 SWD_IO 10 N l 1 SWD CLK VBUS l mDP Type C TX U DP Plug RA DISCONNECT TX M 400K 1 IS Z q00kQ 1 VBUS DET AW HotPlug Detect g VCONN_DET HOTPLUG_DET 100kQ 1 Z o 100k 1 _ Exe s CYPD1120 40LQXI cae cc CC1_RX 40QFN E CC1 LPRX Gera GPIO 4 GPIO 5 S5 1k2 1 GPIO 6 4 GPIO 7 I GPIO 8 ETE TX REF OUT XRES S AKQ 1 Wy TX REF IN ADC BYPASS BYPASS oQ CC_VREF E 2ko 1 TX GND AUX CH AUX CH DP AU P CIRL N CTRL X CTRL 8 7 ho SBU_1 2 AUX_P N SW for AUX Display Port Data Lanes Document Number 001 96786 Rev A Page 15 of 24 Type C Plug BuckBoost 5V
11. M 4 CYPRESS PERFORM General Description CYPD1120 Datasheet USB Power Delivery Alternate Mode Controller on Type C The CYPD1120 device belongs to Cypress s CCG1 product family which provides a complete USB Type C and USB Power Delivery port control solution The scalable and reconfigurable core architecture of CCG1 enables a base Type C solution that can scale to a complete 100 W USB Power Delivery with Alternate Mode mux support CCG1 is also a Type C cable ID IC for active and passive cables The ARM Cortex MO CPU based core can use common open source firmware or custom solutions developed with common libraries and APIs CCG1 is the CC controller that detects connector insert plug orientation and Vconn switching signals CCG1 makes it easier to add USB Power Delivery to any architecture because it provides the control signals to manage external VBUS and Vconn Power management solutions as well as external mux controls for most single cable docking solutions CCG1 s packaging options and programmability enables any USB Type C and USB Power Delivery solution Applications m Dongles docking stations m Type C to DisplayPort m Type C to HDMI m Type C to DVI m Typec C to VGA Features 32 bit MCU Subsystem m 48 MHz ARM Cortex MO CPU with 32 KB flash and 4 KB SRAM Integrated analog blocks m 12 bit 1 Msps ADC for VBUS voltage and current monitoring Integrated digital blocks m Two configurable 16 bit TCPWM b
12. VCCD and Ground 32 VDDD C7 POWER VCONN Supply VDDA C7 33 POWER VSSA B7 34 GND Ground VSS 9 GND Ground CC_VREF C5 36 l Data reference signal for CC lines ADC_BYPASS E7 40 l No Connect TX_U B3 26 O Signals for internal use only The TX U output signal TX M B5 29 should be connected to the TX_M signal Reference signal for internal use Connect to TX_REF DESSEN D3 3 l output via a 2 4K 1 resistor TX_GND A3 25 l Connect to GND via 2K 1 resistor Reference signal generated by connecting internal TXREF OUI Da 39 9 current source to two 1K external resistors Optional control signal to remove RA after assertion of RA_DISCONNECT E4 4 6 n 0 RA disconnected 1 RA connected Reference signal for internal use Connect to the output GOL EDISER p 23 l of resistor divider from VDDD VCONN DET E5 5 o Detects presence of VCONN before responding to CC communication D5 A BYPASS 37 l Bypass capacitor for internal analog circuits CC1 LPRX C3 22 Configuration Channel 1 RX signal for Low Power E States VBUS DET BA 28 Detects presence of VBUS before enabling Billboard device Document Number 001 96786 Rev A Page 4 of 24 Table 1 Pin Definition for 40 Pin QFN and 35 Ball WLCSP continued PERFORM CYPD1120 Datasheet Functional Pin CYPD1120 35FNXIT CYPD1120 40LQXI Type Description Name D6 5 BILLBOARD CTRL 1 O Enables Billboard Device Close
13. capacitor in the 1 uF range in parallel with a smaller capacitor 0 1 uF for example Note that these are simply rules of thumb and that for critical applications the PCB layout lead inductance and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing Examples of bypass schemes follow Figure 4 40 pin QFN Example VSS TX_REF_OUT iur o O 9898859929885 BILLBD_CTRL fa 1 GPIO_4 B2 TX REF IN gt 3 RA DISCONNECT fa 4 QFN VCONN DET B5 Top View HOTPLUG DET AUX CH N SENSE AUX CH P SENSE R6 7 Be VSS VSS GPIO_2 I2C SCL Document Number 001 96786 Rev A I2C SDA 9 DP AUX CTRL f 10 SN go ex Doc s Que I2C INT C4 1yF 30 XRES 29 et TX M 28 e VBUS DET 27 elcPio 1 26 m TX U 25 TX GND 24 md GPIO_5 23 CC1 LPREF 22 m CC1 LPRX 21 B GPIO 0 VSS Page 7 of 24 7 CYPRESS CYPD1120 Datasheet Figure 5 35 ball WLCSP Example 7 4 WIS CN emo s j D D WW Document Number 001 96786 Rev A Page 8 of 24 a Z CYPRESS PERFORM CYPD1120 Datasheet Electrical Specifications Absolute Maximum Ratings Table 2 Absolute Maximum Ratings e Details Spec ID Parameter Description Min Typ Max Units Conditions SID1 VDDD_ABS Digital supply relative to Vssp 0 5 6 0 V Absolute max SID2 Mem ams e digital core voltage input
14. e ees LG A d B q L 8 c l T E e D D E i J E m la EE t NOTES 1 REFERENCE JEDEC PUBLICATION 95 DESIGN GUIDE 4 18 2 ALL DIMENSIONS ARE IN MILLIMETERS 001 93741 Document Number 001 96786 Rev A Page 20 of 24 R ae CYPR ESS FORM Description Acronyms Table 24 Acronyms Used in this Document CYPD1120 Datasheet Description Table 24 Acronyms Used in this Document continued Acronym operational amplifier opamp Overcurrent protection OCP Overvoltage protection OVP printed circuit board layer PCB programmable gain amplifier PGA physical PHY power on reset precise power on reset POR analog to digital converter PRES Programmable System on Chip application programming interface PSoC9 pulse width modulator advanced RISC machine a CPU architecture random access memory PWM Configuration Channel RAM reduced instruction set computing central processing unit RISC root mean square protocol cyclic redundancy check an error checking real time clock RMS Current Sense Downstream Facing Port RTC re ceive RX successive approximation register digital input output GPIO with only digital capabilities no analog See GPIO I C serial clock SAR SCL Displa
15. ec in the following respects m GPIO cells are not overvoltage tolerant and therefore cannot be hot swapped or powered up independently of the rest of the 2c system m Fast mode Plus has an lo specification of 20 mA at a Vo of 0 4 V The GPIO cells can sink a maximum of 8 mA lo with a Voy maximum of 0 6 V m Fast mode and Fast mode Plus specify minimum Fall times which are not met with the GPIO cell Slow strong mode can help meet this spec depending on the Bus Load m When the SCB is an I C Master it interposes an IDLE state between NACK and Repeated Start the 2c spec defines Bus free as following a Stop condition so other Active Masters do not intervene but a Master that has just become activated may start an Arbitration cycle m When the SCB is in the I2C Slave mode and Address Match on External Clock is enabled EC AM 1 along with operation in the internally clocked mode EC OP 0 then its C address must be even GPIO The CCG1 has up to 10 GPIOs which are configured for various functions Refer to the pinout tables for the definitions The GPIO block implements the following m Eight drive strength modes a Analog input mode input and output buffers disabled a Input only a Weak pull up with strong pull down a Strong pull up with weak pull down a Open drain with strong pull down a Open drain with strong pull up ao Strong pull up with strong pull down a Weak pull up with weak pull down m Input thre
16. ed by characterization SID186 VFALLIPOR Falling trip voltage 0 75 1 40 V Guaranteed by characterization SID187 ViPORHYST Hysteresis 15 0 200 0 mV Guaranteed by characterization Table 14 Precise Power On Reset POR Spec ID Parameter Description Min Typ Max Units Details Conditions BOD trip voltage in active and SID190 VrALi PPOR sleep modes 1 64 V Guaranteed by characterization SID192 VrauipPsiP BOD trip voltage in Deep Sleep 1 40 7 x V Guaranteed by characterization Note 8 It can take as much as 20 milliseconds to write to flash During this time the device should not be Reset or flash operations will be interrupted and cannot be relied on to have completed Reset sources include the XRES pin software resets CPU lockup states and privilege violations improper power supply levels and watchdogs Make certain that these are not inadvertently activated 9 Cypress provides a retention calculator to calculate the retention lifetime based on customers individual temperature profiles for operation over the 40 C to 105 C ambient temperature range Contact customercare cypress com Document Number 001 96786 Rev A Page 12 of 24 Br d a Z CYPRESS PERFORM SWD Interface Table 15 SWD Interface Specifications CYPD1120 Datasheet
17. etails Conditions SID234 TSTARTILO1 ILO startup time 2 0 ms Guaranteed by characterization SID236 TiLopuTY ILO duty cycle 40 0 50 0 60 0 Guaranteed by characterization SID237 FILOTRIM1 32 kHz trimmed frequency 15 0 32 0 50 0 kHz 60 with trim Document Number 001 96786 Rev A Page 13 of 24 __ m _ D ag b CYPRESS PERFORM Applications in Detail Figure 6 Type C to DisplayPort Mini DisplayPort Application Using 35 CSP Package Type C Plug Regulator y USB Billboard SDA XRES INT SCL 2 2kQ 5 D6 EN B1 B2 2 2kO 5 pii BILLBOA 12C_ 12C_SCL I2C SDA RD_CTRL INT CC1 LPREF RA DISCONNECT T CYPD1120 35FNXIT GPo 9 35CSP TX REF OUT AUX CH AUX CH DP AU TRL N CTRL X CTRL VCCD SWD IO SWD CLK TXU TXM VBUS_DET HOTPLUG_DET GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 XRES ADC BYPASS BYPASS TX GND VSSA 3100kC 1 NW 100kQ 1 CYPD1120 Datasheet Paddle Card on Type C Plug HotPlug Detect mDP DP Plug A3 2K91 B7 E2 E3 E1 D VDDD 100kO 1 20kQ 1 S 100ko 1 VCONN_DE S TOOK 220 196 M cC1 TX cc CC1_RX CC1_LPRX 5 1kQ 1 2 4kQ 1 ANN TX REF IN oo CC VREF 2kQ
18. itions eeeeeeeeeeee nennen hnnc dos M Electrical Specifications Absolute Maximum Ratings eene 9 Device Level Specifications essssss 9 Digital Peripherals ceee 11 sp MM e Aaaa a a ari a iE 12 System RESOUICES 1 esee tetendit 12 Applications in Detail eere 14 Document Number 001 96786 Rev A CYPD1120 Datasheet Ordering Information eren 18 Ordering Code Definitions suussss 18 Packaging eeeeeeeeeeeeeseeee eene enne nennen nennen 19 ACrONYMS g saas 21 Document Conventions eene 22 Units of Measure rnnt trt ee tee 22 Revision History cccsssceesesersscceesnsceeeeseneessceesenenenenes 23 Sales Solutions and Legal Information 24 Worldwide Sales and Design Support 24 laici c cates PSoC Solutions Cypress Developer Community sssse 24 Technical Support aceite eene n 24 Page 2 of 24 n gt I E CYPRESS PERFORM Functional Definition CPU and Memory Subsystem CPU The Cortex MO CPU in the CCG1 is part of the 32 bit MCU subsystem which is optimized for low power operation with extensive clock gating It mostly
19. locks m One IC master or slave Type C Support m Integrated transceiver BB PHY PD Support m Supports VESA DisplayPort Alternate Mode on USB Type C Standard Version 1 0 Low power operation m 1 8 V to 5 5 V operation m Sleep 1 3 mA Deep Sleep 1 3 uA Packages m 40 pin QFN m 35 ball wafer level CSP WLCSP Figure 1 CCG1 Block Diagram 51 CCG1 USB Type C Port Controller with PD MCU Subsystem Integrated Analog Blocks ARM CORTEX M0 Programmable Interconnect and 48 MHZ Routing cc Flash 32KB SRAM 4KB e Control MUX Control Profiles and Configurations T I Pi ise e fd t S E 2 v e 2 L 2 v X Hotplug Detect d Serial Wire Debug GPIO BB PHY Port Notes 1 Values measured for CCG1 silicon only Application specific power numbers may be higher 2 Timer counter pulse width modulation block 3 Serial communication block configurable as PC 4 Base band 5 Termination resistor denoting an Alternate Mode Adaptor San Jose CA 95134 1709 408 943 2600 Revised July 21 2015 Cypress Semiconductor Corporation Document Number 001 96786 Rev A 198 Champion Court gt een ac CYPRESS PERFORM i Contents Functional Definition eere 3 CPU and Memory Subsystem sees 3 System ResOUrces eene eietenenne ettet es GPIO e Pin Defin
20. motive cypress com go automotive psoc cypress com solutions Clocks amp Buffers cypress com go clocks PSoC 1 PSoC 3 PSoC 4 PSoC 5LP Interface cypress com go interface Cypress Developer Community Power Control cypress com go powerpsoc Community Forums Blogs Video Training Memory cypress com go memory PSoC cypress com go psoc Technical Support Touch Sensing cypress com go touch cypress com go support USB Controllers cypress com go USB Wireless RF cypress com go wireless Cypress Semiconductor Corporation 2015 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypres
21. older Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature 40 pin QFN 260 C 30 seconds 35 ball WLCSP 260 C 30 seconds Table 23 Package Moisture Sensitivity Level MSL IPC JEDEC J STD 2 Package MSL 40 pin QFN MSL 3 35 ball WLCSP MSL 1 Document Number 001 96786 Rev A Page 19 of 24 I EV I E CYPRESS CYPD1120 Datasheet m PERFORM Figure 10 40 pin QFN Package Outline 001 80659 TOP VIEW SIDE VIEW BOTTOM VIEW 6 00 0 10 PIN 1 ID 40 31 31 9 50 40 p UUUUUUUUU 1 30 q I 30 Ch D C 0 50 X PIN 1 DOT 4 E qt o 5 d e pi B E P 0 25 9 05 8 H 9 D Cr 0 e q Pi D e 1 IIRIS 7 o I aD OSSA C hnnannaannf 11 20 0 08 MAX 20 put zz ee 4 60 0 10 NOTES 1 RS HATCH AREA IS SOLDERABLE EXPOSED PAD 2 REFERENCE JEDEC MO 248 3 PACKAGE WEIGHT 68 2 mg 001 80659 A 4 ALL DIMENSIONS ARE IN MILLIMETERS The center pad on the QFN package should be connected to ground VSS for best mechanical thermal and electrical performance If not connected to ground it should be electrically floating and not connected to any other signal Figure 11 35 Ball WLCSP Package Outline 001 93741 TOP VIEW SIDE VIEW BOTTOM VIEW d 35x 123 4 5 6 7 76 5432 1 H
22. p and comparators on 1 7 2 2 mA Deep Sleep Mode Vppp 1 8 to 3 6 V Regulator on SID31 Ipp26 12C wakeup on 1 3 WA T 25 C 3 6V SID32 Ipp27 I C wakeup on E 50 0 pA T 85 C Deep Sleep Mode Vppp 3 6 to 5 5 V SID34 Ipp2o 12C wakeup 15 0 HA T 25 C 5 5V XRES Current SID307 lpp xr Supply current while XRES asserted 2 0 5 0 mA Note 6 Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device Exposure to absolute maximum conditions for extended periods of time may affect device reliability The maximum storage temperature is 150 C in compliance with JEDEC Standard JESD22 A103 High Temperature Storage Life When used below absolute maximum conditions but above normal operating conditions the device may not operate to specification Document Number 001 96786 Rev A Page 9 of 24 ae a Z CYPRESS PERFORM Table 4 AC Specifications CYPD1120 Datasheet e Details Spec ID Parameter Description Min Typ Max Units Conditions S1D48 Fcpu CPU frequency DC 48 0 MHz 1 8 lt Vpp lt 5 5 SID49 TSLEEP Wakeup from sleep mode 0 Us Guaranteed by characterization 24 MHz IMO Guaranteed by SID50 TpeepsLeep Wakeup from Deep Sleep mode 25 0 Hs cha ractensatisn SID52 TREsETWIDTH External re
23. relative 05 _ 1 95 V l Absolute max o Vssp SID3 VGPIO_ABS GPIO voltage 0 5 Vppp 0 5 V Absolute max SIDA IcPio ABS Maximum current per GPIO 25 0 25 0 mA Absolute max GPIO injection current Max for Vi gt Absolute max current SIDS IGPIO_injection Vppp and Min for Vi lt Vss i oe a mA injected per pin BID44 ESD_HBM Electrostatic discharge human body 2200 _ _ V model BID45 ESD_CDM Electrostatic discharge charged device 500 _ i V _ model BID46 LU Pin current for latch up 200 200 mA Device Level Specifications All specifications are valid for 40 C lt T4 lt 85 C and T lt 100 C for 35 CSP and 40 QFN package options Specifications are valid for 1 8 V to 5 5 V except where noted Table 3 DC Specifications Spec ID Parameter Description Min Typ Max Units C kieres 5 SID53 Vppp Power supply input voltage 1 8 5 5 V With regulator enabled SID54 Vccp Output voltage for core logic 1 8 V SID55 CErc External regulator voltage bypass 1 0 1 3 1 6 UF X5R ceramic or better SID56 CExc Power supply decoupling capacitor 1 0 HF X5R ceramic or better Active Mode Vppp 1 8 to 5 5 V Typical values measured at Vpp 3 3 V SID19 Ipp14 Execute from flash CPU at 48 MHz 12 8 mA T 25 C SID20 Ipp45 Execute from flash CPU at 48 MHz 13 8 mA Sleep Mode Vppp 1 8 to 5 5 V SID25A Ipp2oA I C wakeu
24. s AUX_P N switch after successful Alternate DP_AUX_CTRL E1 10 O Mode entry AUX_CH_P_SENSE E2 l Senses presence of DisplayPort on UFP_D AUX_CH_N_SENSE E3 l Senses presence of DisplayPort on DFP_D HOTPLUG_DET EG 6 o OM Detection Driver for DisplayPort Alternate GPIO 0 A1 21 lO GPIO GPIO 1 A6 27 lO GPIO GPIO 2 C2 14 lO GPIO GPIO 3 D2 11 lO GPIO C6 GPIO 4 2 lO GPIO GPIO 5 A4 24 lO GPIO GPIO_6 15 lO GPIO GPIO_7 16 lO GPIO GPIO_8 17 lO GPIO Document Number 001 96786 Rev A Page 5 of 24 S Cypress Pinouts 7 6 5 4 3 2 an ES p N E diis gt y ON p b 4 h 4 N gt W b d A Y ePio 1 CCLLPRE amos Txenp J WcINT Document Number 001 96786 Rev A D_CTRL Figure 2 40 pin QFN Pinout 95 E x 0 m x auar EEE EET EFE F omoo 5 5 52 BSQSSGs 885 BILLBD CTRL E 1 30 XRES GPIO 4 amp 2 29m TX M TX REF IN n 3 28 mVBUS DET RA DISCONNECT f 4 QFN 27 dlepio 1 VCONN DET B 5 Top View 26 TX U HOTPLUG DET E 6 255 TX GND AUX CH N SENSE f 7 24 e GPIO 5 AUX CH P SENSE 8 23 m CC1 LPREF VSS 9 22 CC1 LPRX DP AUX CTRL P 10 21 GPIO 0 SENOS POS Seog LC popoonnipong P o O Y Ww QO r 0o EE ogoooood G 55o5555gg8 oz Sg o gt b 4 TXM VBUS DET JN N O o TXU Q as Q gt TX_REF_O Ur TX REF IN Y A d ine n mis o gt gt w EA Uu a
25. s Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implie
26. s that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 96786 Rev A Revised July 21 2015 Page 24 of 24 All products and company names mentioned in this document may be the trademarks of their respective holders
27. set pulse width 1 0 HS Guaranteed by characterization VO Table 5 I O DC Specifications x Details Spec ID Parameter Description Min Typ Max Units Conditions SID57 v4 Input voltage high threshold vale E V CMOS Input SID58 V Input voltage low threshold Vr V CMOS Input SID241 V LVTTL input Vppp lt 2 7 V rM MES v VDDD F 0 3 x SID242 V LVTTL input V lt 2 7V V IL put Vppp Vion SID243 Vil LVTTL input Vppp 2 2 7 V 2 0 V SID244 Vi LVTTL input Vppp 2 2 7 V 0 8 V SID59 Vou Output voltage high level Vpop V lgu 4 mA at 3 V Vppp SID60 Vou Output voltage high level Vpop V logg 1 mA at 1 8 V Vppp SID61 VoL Output voltage low level x 0 6 V loL 4 mA at 1 8 V Vppp SID62 VoL Output voltage low level 0 6 V flop 8 mA at 3 V Vppp SID62A Vo oL Output voltage low level 0 4 V lol 3 mA at 3 V Vppp SID63 RPuLLUP Pull up resistor 3 5 5 6 8 5 kQ SID64 RpuLLDOWN Pull down resistor 3 5 5 6 8 5 kQ 2 SID65 lii Input leakage current absolute 7 _ 20 nA 25 C Vpop 3 0 V value Input leakage current absolute SID65A l crBM value for analog pins T a nA B SID66 Cin Input capacitance 7 0 pF E Vppp 2 2 7 V Guaranteed by SID67 VHYSTTL Input hysteresis LVTTL 15 0 40 0 mV characterization Vppp gt 4 5V SID68 Vuvscwos Input hysteresis CMOS 200 0 mV Guaranteed by characterization Current through protection diode _ oy SID69 IDIODE to Vpp Vss 100 0 pA G
28. shold select CMOS or LVTTL m Individual control of input and output buffer enabling disabling in addition to the drive strength modes m Hold mode for latching previous state used for retaining I O state in Deep Sleep mode m Selectable slew rates for dV dt related noise control to improve EMI During power on and reset the I O pins are forced to the disable state so as not to crowbar any inputs and or cause excess turn on current A multiplexing network known as a high speed I O matrix is used to multiplex between various signals that may connect to an I O pin Page 3 of 24 gt ge Pin Definitions Z CYPRESS PERFORM CYPD1120 Datasheet Table 1 provides the pin definitions for 40 pin QFN and 35 ball WLCSP for the notebook tablet smartphone and monitor applications Refer to Table 20 on page 18 for par numbers to package mapping Table 1 Pin Definition for 40 Pin QFN and 35 Ball WLCSP Functional Pin Name CYPD1120 35FNXIT CYPD1120 40LQXI Type Description CC1 control CC1 RX C4 35 l 0 TX enabled z RX sense CC1_TX D7 38 O Configuration Channel 1 SWD IO D1 12 lO SWDIO SWD CLK C1 13 l SWD Clock I2C_SCL B1 18 l IC Slave Clock signal I2C_SDA B2 19 1 0 I C Slave Data signal I2C INT A2 20 O 12C INT XRES B6 30 l Active Low Reset VCCD AT 31 POWER Connect 1 pF capacitor between
29. supervisory ROM that contains boot and configuration routines is provided System Resources Power System The power system is described in detail in the section Power on page 7 It provides assurance that voltage levels are as required for each respective mode and either delay mode entry on power on reset POR for example until voltage levels are as required for proper function or generate resets Brown Out Detect BOD or interrupts Low Voltage Detect LVD The CCG1 operates with a single external supply over the range of 1 8 to 5 5 V and has three different power modes Active Sleep and Deep Sleep transitions between modes are managed by the power system Serial Communication Blocks SCB The CCG1 has one SCB which can implement an 12C interface The hardware I C block implements a full multi master and slave interface itis capable of multimaster arbitration In addition the block supports an 8 deep FIFO for receive and transmit which by increasing the time given for the CPU to read data greatly reduces the need for clock stretching caused by the CPU not having read data on time Document Number 001 96786 Rev A CYPD1120 Datasheet The IC peripheral is compatible with the I C Standard mode Fast mode and Fast mode Plus devices as defined in the NXP I C bus specification and user manual UM10204 The IC bus I O is implemented with GPIO in open drain modes The CCG1 is not completely compliant with the 2c sp
30. uaranteed by characterization Maximum Total Source or Sink SID69A lror apio Chip Current 200 0 mA Guaranteed by characterization Note 7 Vj must not exceed Vppp 0 2 V Document Number 001 96786 Rev A Page 10 of 24 i E Fp ED CYPRESS PERFORM Table 6 I O AC Specifications Guaranteed by Characterization CYPD1120 Datasheet M 4 Details Spec ID Parameter Description Min Typ Max Units Conditions SID70 TRISEF Rise time 2 0 12 0 ns 3 3 V Vppp Cload 25 pF SID71 TFALLF Fall time 2 0 12 0 ns 3 3 V Vppp Cload 25 pF XRES Table 7 XRES DC Specifications Details SpecID Parameter Description Min Typ Max Units Conditions SID77 Vi Input voltage high threshold v s E V CMOS input DDD SID78 Vy Input voltage low threshold gt J8 v CMOS input DDD SID79 RPuLLUP Pull up resistor 3 5 5 6 8 5 kQ SID80 Cin Input capacitance 3 0 pF 7 SID81 VuvsxRES Input voltage hysteresis 100 0 mV Guaranteed by characterization Current through protection SID82 IDIODE diode to Vppp Vss 100 0 HA Guaranteed by characterization Digital Peripherals The following specifications apply to the Timer Counter PWM peripherals in the Timer mode Pulse Width Modulation PWM for VSEL and CUR LIM Pins Table 8 PWM AC Specifications Guaranteed by Characterization
31. yPort SDA sample and hold memory electrically erasable programmable read only S H I C serial data Serial Peripheral Interface a communications protocol eceiver a electromagnetic interference EMI electrostatic discharge ESD flash patch and breakpoint full speed FPB FS general purpose input output applies to a PSoC GPIO IC pin integrated circuit integrated development environment Inter Integrated Circuit a communications IDE I C or IIC protocol internal low speed oscillator see also IMO SPI static random access memory SRAM serial wire debug a test protocol SWD transmit Universal Asynchronous Transmitter R TX communications protocol UART Upstream Facing Port Universal Serial Bus UFP USB a USB port USB input output PSoC pins used to connect to USBIO Video Electronics Standards Association external reset I O pin ILO internal main oscillator see also ILO VESA XRES input output see also GPIO DIO SIO USBIO IMO 1 0 LVD low voltage detect low voltage transistor transistor logic LVTTL microcontroller unit no connect MCU NC nonmaskable interrupt nested vectored interrupt controller NMI NVIC Document Number 001 96786 Rev A Page 21 of 24 ES CYPRESS CYPD1120 Datasheet
Download Pdf Manuals
Related Search