EMMA Mobile1 Application Note DDR SDRAM Interface
Contents
1. System Cache ON ON or OFF read out the data from DDR memory area A amp B Data RAW Validate Process i Y Enable System Cache Mode Data Compare Data R W Validate Process Disable System Cache Mode YES Result DDR RESULT ERROR Hesult Get the difference of time consuming DDR RESULT OK between Enable System Cache mode and Disable System Cache mode RETURN Ret Figure 3 5 Flow of Enable Disable System Cache Note In this figure start address of memory area A is 0x30000000 Start address of memory area B is 0 30010 0 Application Note 819908EJ 1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 22 57 3 4 2 Operation Detail 1 Enable or disable system cache function of DDR SDRAM interface by call function ddr enable sys cache About function detail of ddr enable sys cache please refer to the link 2 After enable or disable system cache it is necessary to validate the read write operation of DDR SDRAM still can works normally By the difference of operation time consuming between enable system cache mode and disable system cache mode user can find the effect of system cache Data validate procedure of enable disable system cache mode Write the test data to memory area A Write the same data to m2. 37 Table 4 4 Register Setting of Connection Case 4 39 Table 1 DDR Driver Function List aa 40 Table A 2 Clock Frequency Setting Table iiie Eo tise Fer bts ui Fa e ES dr dees 52 Application Note 819908EJ1VOANOO INDEX 7157 LIST OF FIGURES Figure 1 1 Normal DDR SDRAM Process Flow 9 Figure 3 1 DDR SDRAM Connection Method of EMMA Mobile 1 Evaluation Board 16 Figure 3 2 Mode Register Set of K41X1G323PC 8GOC6 18 Figure 3 3 Extended Mode Register Set of 2 8 6 18 Figure 3 4 Flow of Check ALL 19 Figure 3 5 Flow of Enable Disable System Cache 21 Figure 3 6 Flow of Change Clock Frequency 23 Figure 3 7 Flow of Set PEL Half Mode ii ns Ae ie eei teta 24 Figure 3 8 Flow of CPU Transfer Mode Sample 25 Figure 3 9 Flow of 1CH DMA Transfer Mode Sample 27 Figure 3 10 Flow of 1H DMA Transfer Mode Sample 28 Figure 4 1 32Mwor
3. Note Initialize the DDR SDRAM interface And this function need to be performed when system power ON Application Note 819908EJ 1VOANOO 44 57 APPENDIX A DDR SDRAM DRIVER FUNCTION 45 57 A 3 4 Get State of DDR SDRAM Function Name ddr get CS state Format DRV RESULT ddr get CS state ulCsNum SDR pulState Argument Parameter Type Detail CS number Can be set with ulCsNum 0 CS0 1 CS1 pulState SDR STATE Return the DDR state Function Return DRV OK DRV ERR PARAM Function Flow None Note Get the current state of CSO or CS1 by read register DDR STATES It should be one of the following states SDR_STATE_IDLE SDR_STATE_EMRS SDR_STATE_INVALID SDR_STATE_SELFREF SDR_STATE_AUTO PD SDR_STATE_SELFREF_EXIT SDR STATE DEEP PD SDR STATE PRECHG SDR STATE RDWR SDR STATE FRC CBR STATE CBR STATE 5 j Application Note 819908EJ1VOANOO APPENDIX A DDR SDRAM DRIVER FUNCTION 46 57 A 3 5 Switch to Self Refresh Mode Function Name ddr set SelfRefresh Format DRV RESULT ddr set SelfRefresh uint 5 Argument Parameter Type Detail CS number Can be set with ulCsNum 0 50 or 1 CS1 Function Return DRV OK DRV ERR STATE Application Note 819908EJ1VOANOO APPENDIX A DDR SDRAM DRIVER FUNCTION 47 57 Function Flow 6 S
4. a au nennen 25 ODS 25 3 7 2 Operation 25 3 8 DDR Sample6 Transfer with DMA 27 S ox FOW M 27 3 5 2 Operation Deval hy c 29 Chapter 4 Hardware Connection of DDR SDRANMN J 31 4 1 Connection Method of uuu u yun Qa ua u nnn nnns 31 Appendix A DDR SDRAM Driver Function J J 40 AU DDBR SDRANEAPLIT nCHOOS uuu 40 Application Note S19903EJ1V0AN00 INDEX 5 57 A2 DONE P 40 cac uuu uu boe erasa alone 40 F222 OW UC IIS 40 Function EE _ _____ 41 AS t Preconi ig raga c 41 fte 42 A 3 3 Initialize DDR SDRAM Interface a 43 A Oder SlaleorpbE SEBRANu 45 3 5 Switeh to Selr Berresh rh roa rie east
5. det 13 2 2 3 Enable Disable System 14 2 24 DDR SDRAM Data TranSten haier oaks vea sete ee ee alee 14 22599 saus asum me Nuus 14 Chapter Example of DDR SDRAM Operation J 15 3 1 Outline of DDR SDRAM Operation Example 15 3 2 Connection Method of 5 nnne nnne nnn nnns nnns 16 3 3 DDR Sample1 Check ALL Memory Area 19 SES NI ODS FAO ERE IT 19 3 3 2 Operation 20 3 4 DDR Sample2 Enable Disable System Cache 21 ox OW 21 3 4 2 Operation 22 3 5 DDR Samples Change Sete 23 9 5 OpEraUoM m e 23 3 5 2 Operation 23 3 6 DDR Sample4 Set PLL Mode 24 9 6 T OW HE 24 3 6 2 Operation C 24 3 7 DDR Sampled Transfer with CPU
6. register used in this and the following figures please refer to Mobile 1 DMA Interface User s Manual Application Note 819908EJ 1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 29 57 3 8 2 Operation Detail The procedure of 1 channel and 3 channels DMA transfer sample almost are same 1 Set the DDR DMA interrupt handler For 1 channel LCHO DMA transfer The handler will get the INT status and clear the INT source of LCHO Then mask the INT source For 3 channels LCH 0 1 2 DMA transfer The handler will get the INT status and clear the INT source of LCHO 1 2 Then mask the INT source 2 Enable DMA INT Enable ACPU secure INT Enable ACPU INT Enable LENG INT of LCHO for 1 channel DMA transfer or Enable LENG INT of LCH 0 1 2 for 3 channels DMA transfer 3 Set DMA channel For 1 channel LCHO DMA transfer Setting Value ARM AADD 3000 0000H DMA ARM LCHO AOFF OH DMA ARM LCHO ASIZE COUNT 0H ARM LCHO BADD 3080 0000H ARM LCHO BOFF OH DMA ARM LCHO BSIZE COUNT 0H ARM 60 0000H FFFFH ARM LCHO MODE E4E4 0000H For channels DMA transfer in LCHx 3x00 0000H and 3x80 0000H x 0 1 2 Setting Value DMA ARM LCHx AADD 3x00 0000H DMA ARM LCHx AOFF OH DMA ARM LCHx ASIZE COUNT 0H ARM LCHx BADD 3x80 0000H DMA ARM LCHx BOFF OH DMA ARM LCHx BSIZE COUNT 0H 20 0000H DMA ARM LCHx SIZE FFFFH DMA ARM LCHx MODE 4 4 0000H
7. Enable setting MEMC RST bit ASMU_RESETREQOENA Y Set MEMC RST bit ASMU RESETREQO Y Figure A 2 Reset Operation of DDR SDRAM Note Heset the DDR SDRAM module Application Note 819908EJ 1VOANOO 42 57 APPENDIX A DDR SDRAM DRIVER FUNCTION A 3 3 Initialize DDR SDRAM Interface Function Name init Format RESULT dar init void Argument None Function Return DRV OK DRV ERR ALREADY INITIALIZED Application Note 819908EJ1VOANOO 43 57 APPENDIX A DDR SDRAM DRIVER FUNCTION Function Flow 6 START Y Configure CHG register Call function ddr preconfig Y Set the external memory controller register MEMC DDR CONFIGT2 MEMC DDR CONFIGT1 MEMC DDR CONFIGF MEMC DDR CONFIGA1 MEMC DDR 2 Y Command Set Enable CKE MEMC DDR 2 Y Initialize MRS and EMRS MEMC_DDR_CONFIGC1 Y Command Set execute SDRAM initialization sequence MEMC DDR 2 Y Set memory request schedule mode register MEMC REQSCH Y Issue command MEMC DDR 2 Y Set the refrence cycle MEMC DDR CONFIGH1 Y Set Auto Self Refresh MEMC DDR CONFIGR 2 Y Set Auto Power Down MEMC DDR CONFIGR3 Y Figure 3 Initialization of DDR SDRAM Interface
8. bat A 46 A 3 6 Disable Self Refresh 2 0000200000 0 0 00000000 nennen enne nnne 48 A 3 7 Enter Deep Power Down 49 A 3 6 Ser Glock Fredileliey sedilia d 50 AS 9 Sel eb DIV uuu y uuu uuu E a 53 A 9 10 Delay E 55 1 Eriable Disable System u uuu uu u perito etae 56 ANNEX Modification HIStory oe l u 57 Application Note 819908EJ1VOANOO INDEX 6 57 LIST OF TABLES Table t Hardware EnDvironttiels uku c er Tote cosy v 8 Table 1 2 Software 8 Table 2 1 PULLO Register 11 Table 2 2 DRIVEO Register 11 Table 2 S ASNU zio co iater 12 Table 3 1 Related Register Setting of the External Memory Chip 17 Table 4 1 Register Setting of Connection Case 1 33 Table 4 2 Register Setting of Connection Case 2 35 Table 4 3 Register Setting of Connection Case 3
9. Format DRV RESULT ddr set div SDR MODE ulDiv Argument Parameter Type Detail PLL Mode Can be set with PLL HALF OFF PLL HALF DIV2 PLL HALF DIVA PLL HALF DIV6 PLL HALF PLL HALF DIV10 PLL HALF DIV12 PLL HALF DIV14 or PLL HALF DIV16 ulDiv SDR PLL MODE Function Return DRV OK DRV ERR ABNORMAL 6 START gt Disable Auto Frequency Change ASMU AUTO FRQ CHANGE Disable PLL Half mode ASMU DFS HALFMODE Check operation result ASMU CLK MODE SEL Auto Fregq Change function becomes Normal status BE d Return DRV OK Return DRV ERR ABNORMAL Figure A 8 Disable PLL Half Mode Function Flow Application Note 819908EJ 1VOANOO APPENDIX A DDR SDRAM DRIVER FUNCTION C START 2 Enable Auto Frequency Change ASMU AUTO FRQ CHANGE Enable setting PLL Half Mode ASMU DFS HALFMODE Set PLL Half Mode ASMU DFS HALFMODE Check operation result ASMU CLK MODE SEL o Freq Change function becomes Busy status 6 Return OK D Return DRV_ERR_ABNORMAL Figure A 9 Set PLL Half Mode Note None Application Note 819908EJ 1VOANOO 54 57 APPENDIX A DDR SDRAM DRIVER FUNCTION A 3 10 Delay Auto Calibrate Function Name ddr delay auto Format void em1 ddr dela
10. 4 Start DMA transfer by set register ARM CONT Application Note 819908EJ1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 30 57 5 Wait for the transfer complete Because only LENG INT is enabled so the INT only occurs when DMA transfer is finished Note In this sample 1 LED will light when process the CPU data transfer is used for the output port Application Note 819908EJ1VOANOO CHAPTER 4 HARDWARE CONNECTION OF DDR SDRAM 31 57 Chapter 4 Hardware Connection of DDR SDRAM 4 1 Connection Method of DDR SDRAM EMMA Mobile 1 DDR SDRAM interface has 2 CS each CS can connect Max 1Gbit external memory chip with 32bits data bus In this chapter 4 connection cases are described e 256MB 32M words x 32 bit x 2 chips e 128MB 16M words x 16 bit x 2 chips e 128MB 32M words x 32 bit x 1 chip e 256MB 32M words x 16 bit x 2 chips The connection method of each case is shown in the following figures Application Note 819908EJ1VOANOO EMMA Mobile 1 DDR CSB O0 DDR CKE O0 DDR MCLK DDR MCLKB DDR A 12 0 DDR DATA 31 0 DDR DQS 3 0 DDR DQM 3 0 DDR BA 1 0 DDR RASB DDR CASB DDR WEB DDR CSB 1 DDR CKE 1 CHAPTER 4 HARDWARE CONNECTION OF DDR SDRAM Case 1 128MB x 2 chips 32 bit data bus Use CSO and CS1 Chip 1 32Mwords x 32bit CSB CKE CK CKB A 12 0 31 0 DQS 3 0 DM 3 0 BA 1 0 RASB CASB WEB Chip 2 32Mwor
11. A 12 0 12 0 DDR DATA 15 0 DQ 15 0 DDR DGS 3 0 00 1 3 0 DDR DQM 0 0 DDR BA 1 0 BA 1 0 DDR RASB RASB DDR CASB CASB DDR WEB WEB DDR DATAT 91 16 Chip 2 DDR_DQM 3 2 16Mwords x 16bit DDR A 13 N C CSB DDR CSB 1 N C CKE DDR CKE 1 N C CK CKB A 12 0 DQ 15 0 DQS 3 0 CSB CS DM 1 0 CKB CK BA 1 0 RAS RASB CAS CASB WEB WE WEB Figure 4 2 16Mwordx16bitx2chip DDR SDRAM Connection Method Application Note 819908EJ 1VOANOO CHAPTER 4 HARDWARE CONNECTION OF DDR SDRAM 35 57 Table 4 2 Register Setting of Connection Case 2 Register Setting Explanation MEMC DDR CONFIGF 0000 001DH CSO ENABLE 1b CSO enable CSO DENSITY 11b CSO memory size 1Gbit CSO DOUBLE 1b connect 16bit x 2 chips CSO BANK SPLIT 00b 4 bank interleave CS1 ENABLE 06 CS1 disable CS1 DENSITY 006 ignore it when CS1 disable CS1 DOUBLE Ob ignore it when CS1 disable CS1 BANK SPLIT 00b ignore it when CS1 disable DDR CONFIGC1 YYYY XXXXH MRS XXXXH EMRS YYYYH Note The value of MRS and 5 registers listed in this table should be set according to the data sheet of the connected external memory chip Application Note 819908EJ1VOANOO EMMA Mobile 1 CHAPTER 4 HARDWARE CONNECTION OF DDR SDRAM Case 3 128MB x 1 chip 32 bit data bus Use 0 only DDR CSB 0 DDR CKE O0 DDR MCLK DDR MCLKB DDR A 12 0 DDR DA
12. DDR CASB DDR WEB DDR DATA 31 16 Case 4 128MB x 2 chips 16 bit data bus Use CS0 and CS1 Chip 1 32Mwords x 16bit CSB CKE CK CKB A 12 0 DQ 15 0 DQS 3 0 DM 1 0 BA 1 0 RASB CASB WEB Chip 2 32Mwords x 16bit CSB Figure 4 4 32Mwordsx1 6bitx2chips DDR SDRAM Connection Method DDR DQN 3 2 DDR CSB t1 DDR CKE 1 DDR A 13 _ __ N C CSB CS CAS A 12 0 DQ 15 0 00 13 0 0 BA 1 0 RASB CASB WEB Application Note 819908EJ 1VOANOO 38 57 CHAPTER 4 HARDWARE CONNECTION OF DDR SDRAM 39 57 Table 4 4 Register Setting of Connection Case 4 Register Setting Explanation MEMC DDR CONFIGF 0000 ODODH CS0 ENABLE 1b CSO enable CS0 DENSITY 11b CSO memory size 1Gbit CSO DOUBLE Ob only connect 16bit x 1 chip CS0 BANK SPLIT 00b 4 bank interleave CS1 ENABLE 1b CS1 enable CS1 DENSITY 11b CS1 memory size 1Gbit CS1 DOUBLE Ob only connect 1x16bit chip CS1 BANK SPLIT 00b 4 bank interleave MEMC DDR CONFIGC1 YYYY XXXXH MRS 9 EMRS YYYYH Note The value of MRS and 5 registers listed in this table should be set according to the data sheet of the connected external me
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15. 55 55 55 55 AA AA AA AA 55 55 55 55 2 write data 0x55555555 with 1 word skip to the whole memory area The memory after write data should be as below ex Little Endian 0x3000 0000 55 55 55 55 55 55 55 55 0x3000 0010 55 55 55 55 55 55 55 55 OxS7FF FFFO 55 55 55 55 55 55 55 55 Caution In this sample means the data is the original data before writing 0x55555555 3 write the address value to the related memory area The memory after write data should be as below ex Little Endian 0 3000 0000 30 00 00 0C 00 00 08 00 00 04 30 00 00 00 0x3000 0010 30 00 00 1C 30 00 00 18 30 00 00 14 30 00 00 10 Ox37FF FFFO 37 FF 37 FF FF F8 37 FF FF F4 37 FF FF Then read out these data and compare with the written data If same it means the Write Read operation of the whole DDR SDRAM memory is OK otherwise itis abnormally Application Note 819908EJ1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 21 57 3 4 DDR Sample2 Enable Disable System Cache In this sample data transfer with without system cache will be evaluated 3 4 1 Operation Flow Operation flow chart of this sample is shown as below start Data R W vamp operation Enable Disable system cache Write Data to call function cache Dom TT area Write the same Data to DDR memory area B
16. Bus pi d ee ee pt ru aj ofo R PASR Mode Register PASR 1 2 Array 1 4 Array NOTE 1 RFU Reserved for future use should stay 0 during EMRS cycle Figure 3 3 Extended Mode Register Set of K4X1G323PC 8GC6 Application Note 819908EJ 1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 19 57 3 3 DDR Sample1 Check ALL Memory Area In this sample all memory area of the external DDR SDRAM chip is checked 3 3 1 Operation Flow Operation flow chart of this sample is shown as below start Memory Check Write Data to DDR memory 0x3000 0000 read out the data from the same DDR memory area Data Compare YES Return DDR RESULT ERR Heturn DDR RESULT OK Figure 3 4 Flow of Check ALL Memory Note 1 Checking all memory is from 0x3000 0000 to Ox37FF FFFF for EMMA Mobile 1 evaluation board PSKCH2Y S 001 6 01 Application Note 819908EJ 1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 20 57 3 3 2 Operation Detail In this part 3 group operations are performed 1 write data 0x55555555 and OxAAAAAAAA to the whole memory area interleaved The memory after write data should be as below ex Little Endian 0x3000 0000 AA AA AA 55 55 55 55 AA AA AA AA 55 55 55 55 0 3000 0010 AA AA AA 55 55 55 55 AA AA AA AA 55 55 55 55 OxS7FF FFFO AA AA AA AA
17. Lock Time 1586us NORMALA_DIV 2X XXxxH set MEMCDOMAIN A222 NOTE MEMC FREQ PLL1x1 3 499 712 3MHz 166 571MHz 2 Divisor 16 Divisor 2 DIVMEMCRCLK Default value DIVOxxx 2 0 100b DIV1xxx 3 0 20000b gt MEMC RCLK PLL3 16 229 276 16 MHz 14 336MHz 2 00000 MEMCCLKETO SEL o dotor Buz ___ ___ o ASMU HS FAKE Defaut vawe S Note Only need set NORMALA DIV 22 20 for DDR SDRAM module Application Note 819908EJ1VOANOO CHAPTER 2 USAGE OF DDR SDRAM INTERFACE 13 57 2 2 2 Initialize DDR SDRAM module Configure the external memory control register according to the data sheet of the connected external DDR memory chip As reference the following items need to be set External memory delay setting External memory chip related configuration External memory AC timing setting External memory MRS EMRS setting External memory command issue control External memory refreshes setting NOTE Note Please enable self refresh function of mobile DDR SDRAM The explanation about EMMA Mobile 1 self refresh mode please refer 4 1 2 Refresh control of EMMA Mobile 1 DDR SDRAM User s Manual Memory request schedule register MEMC REQSCH also need to configure Remark MRS Mode Register Setting EMRS Extended Mode Register Setting Related register
18. MEMC CONFIGT2 MEMC DDR CONFIGF MEMC DDR CONFIGA1 MEMC DDR CONFIGA2 MEMC DDR CONFIGC1 MEMC DDR CONFIGC2 DDR CONFIGH1 MEMC DDR CONFIGR2 MEMC DDR CONFIGR3 MEMC REQSCH Application Note 819908EJ1VOANOO CHAPTER 2 USAGE OF DDR SDRAM INTERFACE 14 57 2 2 3 Enable Disable System Cache EMMA Mobile 1 supports system cache function to storing data temporarily read from memory 50 when the same data is used multiple times the read cache function is useful Under this case enable system cache function can reduce memory access User can decide use system cache for read write or not Enable or disable system cache function by configuring register MEMC DEGFUN Related register MEMC DEGFUN 2 2 4 DDR SDRAM Data Transfer Usually the DDR SDRAM can be accessed after initialization without setting system cache User can perform basic transfer and with system cache transfer Only when perform the system cache data transfer it is necessary to set the system cache function There are two mode of data transfer CPU mode and DMA mode About these two modes please find its process flow in Chapter 3 7 and Chapter 3 8 2 2 5 DDR SDRAM Power OFF This step will be performed when system power off There are 2 register of ASMU DDR will be set to stop the clock supply of DDR SDRAM And then reset the DDR register to disable DDR input port Related register CHG PULLO RESETREQO RESETREQOENA Application Not
19. MPLE OF DDR SDRAM OPERATION 17 57 Table 3 1 Related Register Setting of the External Memory Chip Register Setting Explanation MEMC DDR CONFIGF 0000 000DH CS0 ENABLE 1b CS0 enable CS0 DENSITY 11b CSO memory size 1Gbit CSO DOUBLE Ob only connect 1x32bit chip 50 BANK SPLIT 00b 4 bank interleave 51 ENABLE 06 CS1 disable CS1 DENSITY 006 ignore it when CS1 disable CS1 DOUBLE Ob ignore it when CS1 disable CS1 BANK SPLIT 00b ignore it when CS1 disable MEMC DDR 8020 0033H MRS 0033H Burst Length 011b 8 burst Ob sequential CAS Latency 011b 3 EMRS 8020H 000b Full Array DS 01b 1 2 Note All these registers listed in this table should be set according to the data sheet of the connected external memory chip Application Note 819908EJ1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 18 57 For MRS and EMRS setting of K4X1G323PC 8GC6 please refer to below figures ndm i j _ o o mu oj oj o c staeny BT Eusttengn Mode Register Burst Type 0 Sequentat _ Bus po fo fo pepo o e ENKENNNN o o ENENENN 1 RFU Reserved for future use should stay O during MRS cycle Figure 3 2 Mode Register Set of K4X1G323PC 8GC6 AD Address
20. MU NORMALA DIV Y Release STANDBY of PLL1 ASMU_PLL1CTRL1 Y Switch to Normal mode A ASMU MODEL SEL Y Check operation result ASMU MODE SEL NO Return DRV ERR ABNORMAL PLL clock mode Normal mode A Retum DRV OK Figure A 7 Set Clock Frequency Application Note 819908EJ 1VOANOO 51 57 APPENDIX A DDR SDRAM DRIVER FUNCTION 52 57 Note EMMA Mobile 1 DDR SDRAM interface only supports clock frequencies 166MHz 133MHz and 125MHz For each frequency the PLL1 setting value and clock divisor are listed in the below table Table A 2 Clock Frequency Setting Table Target Frequency 166MHz 133MHz 125MHz PLL1 Value 1 target value 499 712MHz 397 312MHz 499 712MHz Set REG PLLICTRLO Clock Divisor Set REGINORMALA 0 00244200 0x00244200 0 00355300 Domain Clock Frequency ACPU divisor 500MHz 1 1 400MHz 1 1 500MMHz 1 1 2 ADSP divisor 500MHz 1 1 400MHz 1 1 500 1 1 HBUS divisor 166MHz 1 3 133MHz 1 3 125MHz 1 4 LBUS divisor 83 3MHz 1 6 66 6MHz 1 6 62 5MHz 1 8 FLASH divisor 83 3MHz 1 6 66 6MHz 1 6 62 5MHz 1 8 MEMC divisor 166MHz 1 3 133MHz 1 3 125MHz 1 4 Application Note 819908EJ1VOANOO APPENDIX A DDR SDRAM DRIVER FUNCTION 53 57 A 3 9 Set PLL Div Mode Function Name PLL
21. R Power OFF Y C END gt Figure 1 1 Normal DDR SDRAM Process Flow NO NO Note 1 About the explanation of all the DDR SDRAM registers mentioned in this document please refer to EMMA Mobile 1 DDR SDRAM Interface User s Manual 2 About the explanation of all the ASMU registers mentioned in this document please refer to EMMA Mobile 1 ASMU GIO Interface User s Manual 3 About the explanation of all the CHG registers mentioned in this document please refer to EMMA Mobile 1 One Chip User s Manual Application Note 819908EJ 1VOANOO CHAPTER 2 USAGE OF DDR SDRAM INTERFACE 10 57 2 2 Detail of Normal DDR SDRAM Data Transfer Procedure 2 2 1 Configure DDR CHG and DDR ASMU Register Its necessary to configure the EMMA Mobile 1 CHG register before initialize and use DDR SDRAM e Pull down and enable the input port Set the port driver ability to 12mA NOTE Note Please set the drive ability according to the DC character of the external DDR SDRAM chip In order to supply the higher drive ability this value is set to the maximum value here After CHG register configuration set ASMU registers for DDR SDRAM Related register CHG PULLO CHG DRIVEO RESETREQO RESETREQOENA CLK MODE SEL PLL1CTRLO PLLSCTRLO PLLLOCKTIME NORMALA DIV STANDBY DIV POWERON DIV DIVMEMCRCLK CLKCTRL MEMCCLK270_ SEL IO LO L1 BUZ ASMU MEMC HS FAKE Appli
22. RESULT ddr set DeepPowerDown uint Argument Parameter Type Detail CS number Can be set with ulCsNum 0 50 or 1 CS1 Function Return DRV OK DRV ERR STATE Function Flow 6 START D Set CS0 1 Self Refresh count value MEMC DDR CONFIGR2 Y Enter Deep Power Down mode MEMC DDR CONFIGC2 Y Check the current state of DDR SDRAM call function em1 ddr get CS state NO STATE SDR STATE DEEP PD 6 Return STATE Figure 6 Switch to Deep Power Down Mode Note None Application Note 819908EJ 1VOANOO APPENDIX A DDR SDRAM DRIVER FUNCTION A 3 8 Set Clock Frequency Function Name ddr chg freq Format DRV RESULT em1 ddr chg freq uint ulFreq Argument Parameter Type Detail 50 57 T Frequecy value MHz Can be set with 166 133 or 125 Function Return DRV OK DRV ERR ABNORMAL Application Note 819908EJ1VOANOO APPENDIX A DDR SDRAM DRIVER FUNCTION Function Flow 1 START Y Set to Power ON mode ASMU CLK MODEL SEL Y Check operation result ASMU MODE SEL NO PLL clock mode Power ON mode Return 2 Lock PLL1 with STANDBY status DRV ERR ABNORMAL ASMU_PLL1CTRL1 Y Set PLL1 value ASMU PLL1CTRLO Y Set divisor of Normal mode A AS
23. TA 31 0 DDR DOGS 3 0 DDR DQM 3 0 DDR BA 1 0 DDR RASB DDR CASB DDR WEB Chip 1 32Mwords x 32bit CSB CKE CK CKB A 12 0 DQ 31 0 DQS 3 0 DM 3 0 BA 1 0 RASB CASB WEB DDR A 13 ___ N C DDR CSB 1 DDR CKE 1 CSB CS CK RASB RAS CAS Figure 4 3 32Mwordsx32bitx1chip DDR SDRAM Connection Method Application Note 819908EJ 1VOANOO 36 57 CHAPTER 4 HARDWARE CONNECTION OF DDR SDRAM 37 57 Table 4 3 Register Setting of Connection Case 3 Register Setting Explanation MEMC DDR CONFIGF 0000 000DH CSO ENABLE 1b CSO enable 50 DENSITY 11b CSO memory size 1Gbit 50 DOUBLE Ob only connect 32bit x 1 chip 50 BANK SPLIT 00b 4 bank interleave CS1 ENABLE 06 CS1 disable CS1 DENSITY 006 ignore it when CS1 disable CS1 DOUBLE Ob ignore it when CS1 disable CS1 BANK SPLIT 00b ignore it when CS1 disable DDR CONFIGC1 YYYY XXXXH MRS XXXXH EMRS YYYYH Note The value of MRS and 5 registers listed in this table should be set according to the data sheet of the connected external memory chip Application Note 819908EJ1VOANOO EMMA Mobile 1 CHAPTER 4 HARDWARE CONNECTION OF DDR SDRAM DDR CSB 0 DDR CKE O0 DDR MCLK DDR MCLKB DDR A 12 0 DDR DATA 15 0 DDR DOS 3 0 DDR DOM 0 DDR BA 1 0 DDR RASB
24. TART Y Check the current state of DDR SDRAM call function em1 ddr get CS state YES STATE SDR STATE SELFREF Switch to Self Refresh mode MEMC DDR CONFIGC2 Check the current state of DDR SDRAM call function em1 ddr get CS state STATE SDR STATE SELFREF NO Y rn ERR STATE 6 Return Figure 4 Switch to Self Refresh Mode Note Entry Self Refresh mode by setting register MEMC DDR CONFIGC2 Application Note 819908EJ 1VOANOO APPENDIX A DDR SDRAM DRIVER FUNCTION A 3 6 Disable Self Refresh Mode Function Name ddr exit SelfRefresh Format DRV RESULT ddr exit SelfRefresh uint Argument Parameter Type Detail CS number Can be set with ulCsNum 0 50 or 48 57 1 CS1 Function Return DRV OK DRV ERR STATE Function Flow START gt Exit from Self Refresh mode MEMC DDR CONFIGC2 Check the current state of DDR SDRAM call function em1 ddr get CS state NO STATE SDR STATE SELFHREF 2 em ERR S T Figure A 5 Exit from Self Refresh Mode Note None Application Note 819908EJ 1VOANOO APPENDIX A DDR SDRAM DRIVER FUNCTION 49 57 A 3 7 Enter Deep Power Down Mode Function Name ddr set DeepPowerDown Format DRV
25. TO_IEN1 ARM PEO LCHOLCHS3 INT Data Transfer LE Set LCHO reigster 9 DMA ARM LCHO AADD Wait for DMA transfer complete INT DMA ARM LCHO AOFF DMA Transfer Complete DMA ARM LCHO ASIZE COUNT DMA ARM LCHO BADD DMA ARM LCHO BOFF DMA ARM LCHO BSIZE COUNT DMA ARM LCHO LENG ARM LCHO SIZE DMA ARM MODE Figure 3 9 Flow of 1CH DMA Transfer Mode Sample Application Note 819908EJ 1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 28 57 Operation flow chart of the sample with 3 DMA channels is shown as below START gt Set the DDR Int handler call function ddr 2 Start DMA LCHx transfer x 0 1 and 2 Enable DMA INT ARM CONT SEC ITO 51 Y INTC ITO IEN1 ARM PEO LCHOLCH3 INT ENAB Data Transfer Set LCHx reigster 975 ARM LCHx ASIZE COUNT DMA ARM LCHx BADD DMA ARM LCHx BOFF x 0 1 and 2 Wait for DMA transfer complete INT DMA ARM LCHx BSIZE COUNT DMA ARM LCHx LENG DMA ARM LCHx AADD DMA Transfer Complete DMA ARM LCHx SIZE DMA ARM LCHx DMA ARM LCHx MODE 1 END Figure 3 10 Flow of 1CH DMA Transfer Mode Sample Note About detail of the
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27. cation Note 819908EJ1VOANOO CHAPTER 2 USAGE OF DDR SDRAM INTERFACE 11 57 Explanation e In CHG PULLO only bit 6 4 need to be set for DDR SDRAM Bit 6 DOS IE Bit 5 4 DQS xx For DDR SDRAM configure CHG PULLO as below Table 2 1 CHG PULLO Register Setting Allows input UPC 0 Pull Down POENB Enable Pull Up Down e In CHG_DRIVEO only bit 19 10 need to be set for DDR SDRAM Bit 19 18 00 Bit 17 16 DQM Bit 15 14 DQ Bit 13 12 DDR CK Bit 11 10 DDR A For DDR SDRAM configure CHG DRIVEO as below Table 2 2 CHG DRIVEO Register Setting Set the driving capability 00b 2mA 01b 4mA Default value 10b 6mA 8mA 11b 8mA 12mA Normally using the default value for drive DDR SDRAM is enough Application Note 819908EJ1VOANOO CHAPTER 2 USAGE OF DDR SDRAM INTERFACE 12 57 e ASMU Register Setting for DDR For example set PLL1 to about 500MHz set PLL3 to 229 276MHz As DDR333 memory chip set DDR frequency to about 166MHz Table 2 3 ASMU Register Setting Setting RESETREQOENA Set MEMC RST ENA 1 to enable set register EN e Set MEMC HST 0 to disable set register RESETREQO RESETREQO SetMEMC RST 0toresetDDR SDRAM m After reset it is Power ON mode After Initialization it will be Normal A mode eese TI Pl3CTRO Befautvalue 0x37 gt PLL3 229 376MHz value 0x37 gt PLL3 229 376MHz PLLLOCKTIME PLL1 amp PLL3 Lock Time enable And
28. ds x 32bit DDR A 13 N C CSB CS CKB CK RASB RAS CASB CAS WEB WE Figure 4 1 32Mwordsx32bitsx2chip DDR SDRAM Connection Method CSB CKE CK CKB A 12 0 DQ 31 0 DQS 3 0 DM 3 0 BA 1 0 RASB CASB WEB Application Note 819908EJ 1VOANOO 32 57 CHAPTER 4 HARDWARE CONNECTION OF DDR SDRAM 33 57 Table 4 1 Register Setting of Connection Case 1 Register Setting Explanation MEMC DDR CONFIGF 0000 ODODH CS0 ENABLE 1b CS0 enable CSO DENSITY 11b CSO memory size 1Gbit 50 DOUBLE Ob only connect 32bit x 1 chip CS0 BANK SPLIT 00b 4 bank interleave CS1 ENABLE 1b CS1 enable CS1 DENSITY 11b CS1 memory size 1Gbit CS1 DOUBLE Ob only connect 1x32bit chip CS1 BANK SPLIT 00b 4 bank interleave DDR CONFIGC1 YYYY XXXXH MRS XXXXH EMRS YYYYH Note The value of MRS and 5 registers listed in this table should be set according to the data sheet of the connected external memory chip Application Note 819908EJ1VOANOO CHAPTER 4 HARDWARE CONNECTION OF DDR SDRAM 34 57 Case 2 64MB x 2 chips 16 bit data bus Use CSO only X DDR CSB O0 CSB DDR CKE 0 CKE DDR MCLK CK DDR MCLKB CKB DDR
29. dsx32bitsx2chip DDR SDRAM Connection Method 32 Figure 4 2 16Mwordx16bitx2chip DDR SDRAM Connection Method 34 Figure 4 3 32Mwordsx32bitx1chip DDR SDRAM Connection 36 Figure 4 4 32Mwordsx16bitx2chips DDR SDRAM Connection Method 38 Figure 1 Preconfig for DDR Initialization 41 Figure 2 Reset Operation of DDR SDRAM 42 Figure Initialization of DDR SDRAM Interface 44 Figure 4 Switch to Self Refresh Mode 47 Figure 5 Exit from Self Refresh Mode 48 Figure 6 Switch to Deep Power Down Mode 49 Figure 7 Set Clock 51 Figure A 9 Disable PELE Halt Mode uisi uu u vita ale eu iv oae o eto eere bun 53 Figure A 9 5et PLL Half ai asas Roo 54 Figure 10 Set Delay Auto Calibration aa nnn 55 Application Note 819908EJ1VOANOO CHAPTER 1 OVERVIEW 8 57 Chapter 1 Overview 1 1 Introduction In this document the below contents of EMMA Mobile 1 mob
30. e 819908EJ1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 15 57 Chapter 3 Example of DDR SDRAM Operation 3 1 Outline of DDR SDRAM Operation Example In the EMMA Mobile 1 DDR SDRAM operation sample 6 samples are performed based on the EMMA Mobile 1 evaluation board PSKCH2Y S 001 6 01 By these samples user can know the below usages of EMMA Mobile 1 DDR SDRAM module How to check the external memory chip area System cache usage How to change clock How to set PLL Full Half Quarter mode CPU transfer mode usage e DMA transfer mode usage Application Note 819908EJ1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 16 57 3 2 Connection Method of DDR SDRAM On the NECEL EMMA Mobile 1 evaluation board PSKCH2Y S 0016 01 one 128MB size mobile DDR SDRAM memory chip K4X1G323PC 8GC6 DDR333 32Mwords x 32bit manufacture SAMSUNG is connected And the connection method is below EMMA Mobile 1 K4X1G323PC 8GC6 DDR CSB 0 CSB DDR CKE 0 CKE DDR MCLK CK DDR MCLKB CKB DDR A 12 0 12 0 DDR DATA 81 0 DQ 31 0 DDR DQS 3 0 DQS 3 0 DDR DQN 3 0 DM 3 0 DDR BA 1 0 BA 1 0 DDR RASB RASB DDR CASB CASB DDR WEB WEB CSB CS DDR A 13 NC CKB CK DDR CSB qc RASB RAS DDR Nc CASB CAS WEB Figure 3 1 DDR SDRAM Connection Method of EMMA Mobile 1 Evaluation Board Application Note 819908EJ 1VOANOO CHAPTER 3 EXA
31. emory area B Then read out the data from memory area Head out the data from memory area B Then compare the read out data If they are same it indicates the read write operation is OK otherwise the system cache function is abnormal Application Note 819908EJ1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 23 57 3 5 DDR Sample3 Change Clock This sample will show how to change the clock frequency of DDR SDRAM 3 5 1 Operation Flow Operation flow chart of this sample is shown as below START Y Set the clock frequency call function ddr chg freq Operation is OK Return YES Set delay auto calibration call function em1_ddr_delay_auto_cal Return DDR RESULT OK Figure 3 6 Flow of Change Clock Frequency Note Operation is OK in this figure means had change clock frequency successfully 3 5 2 Operation Detail 1 Change the clock frequency of DDR SDRAM by call function ddr chg About function detail of ddr chg freq please refer to the link It supports 166 2 133MHz and 125MHz 2 If change the clock frequency successfully then set delay auto calibration by call function em1 ddr delay auto cal Otherwise return error information DDR SDRAM auto calibration function can set up the initial relationship between clocks automatically The initial calibration is done only once at syste
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33. future Refer to the latest applicable data sheet s and User s Manual when designing a product for mass production No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this documents or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customers equipment shall be done under the full responsibility of the customer NEC Electronics assume no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that possibility of defects thereof cannot be eliminated e
34. ics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics tENESAS Application Note Multimedia Processor for Mobile Applications DDR SDRAM Interface EMMA Mobile 1 Document No S19903EJ1VOANOO Date Published Aug 2009 NEC Electronics Corporation 2009 Printed in Japan PREFACE PREFACE Purpose The purpose of this document is to introduce the usage of EMMA Mobile 1 DDR SDRAM interface Organization This document includes the following Chapter 1 Introduction Chapter 2 Usage of DDR SDRAM Interface Chapter 3 Example of DDR SDRAM Operation Chapter 4 Hardware connection of DDR SDRAM memory Appendix DDR SDRAM API Function Notation Here explains the meaning of following words in text Note Explanation of item indicated in the text Caution Information to which user should afford special attention Remark Supplementary information Related document The following tables list related documents Reference Document DocumentName Version date Author Description 7 Application Note 819908EJ1VOANOO PREFACE Disclaimers The information contained in this document is subject to change without prior notice in the
35. ile DDR SDRAM interface will be described 1 the normal process procedure of mobile DDR SDRAM 2 usage sample of mobile DDR SDRAM 3 hardware connection method between EMMA Mobile 1 and external mobile DDR SDRAM memory As additional the EMMA Mobile 1 DDR driver interface of EMMA Mobile 1 evaluation program will be explained About detail of DDR SDRAM interface please refer to Mobile 1 DDR SDRAM Interface User s Manual 1 2 Development Environment e Hardware environment of this project is listed as below Table 1 1 Hardware Environment Name Version __ Mar EMMA Mobile 1 evaluation board NEC Electronics PSKCH2Y S 001 6 01 PARTNER Jet ICE ARM Kyoto Microcomputer Co Ltd e Software used in this project is listed as below Table 1 2 Software Environment Version Mar ____ GNUARM Toolchain V4 3 2 WJETSET ARM V5 10a Kyoto Microcomputer Co Ltd Application Note S19903EJ1V0AN00 CHAPTER 2 USAGE OF DDR SDRAM INTERFACE 9 57 Chapter 2 Usage of DDR SDRAM Interface 2 1 Normal Procedure of DDR SDRAM Operation Normal DDR SDRAM data transfer procedure is shown as below 6 START p Y Configure DDR CHG amp DDR ASMU Registers Y DDR Initialization se System Cache NO YES Disable Cache Enable Cache eed to Chang Setting DDR Data Transfer Transfer End System Power OFF y YES DD
36. m reset after device initialization is complete The calibration process can center the resynchronization clock phase into the middle of the captured data valid window to maximize the resynchronization setup and hold margin center the read data capture valid window instead of the resynchronization window picks the correct clock edge to align and resynchronize the captured data in the clock domain About function detail of ddr delay auto cal please refer to the link Application Note 819908EJ 1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 24 57 3 6 DDR Sample4 Set PLL Mode This sample will show how to set PLL Half mode of DDR SDRAM 3 6 1 Operation Flow Operation flow chart of this sample is shown as below 6 START Y Set PLL Half mode call function ddr set div Operation is OK Return k DDR RESULT ERR Heturn DDR RESULT OK Figure 3 7 Flow of Set PLL Half Mode Note Operation is OK in this figure means had set PLL divisor successfully 3 6 2 Operation Detail 1 Set the PLL Half mode of DDR SDRAM by call function ddr set div About function detail of ddr set div please refer to the link It supports Full mode 1 1 Half mode 1 2 and Quarter mode 1 4 Application Note 819908EJ 1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 25 57 3 7 DDR Sample5 Transfer with CPU Mode This sample shows the data transfe
37. mory chip Application Note 819908EJ1VOANOO APPENDIX A DDR SDRAM DRIVER FUNCTION 40 57 Appendix A DDR SDRAM Driver Function A 1 DDR SDRAM API function list The following table shows the DDR SDRAM interface functions Table A 1 DDR Driver Function List Change the clock frequency of DDR SDRAM Set PLL div mode A 2 Type Define A 2 1 Naming rule and coding rule About naming rule and coding rule please refer to SPEC AN amp TP pdf A 2 2 Structure None Application Note 819908EJ1VOANOO APPENDIX A DDR SDRAM DRIVER FUNCTION A 3 Function Detail A 3 1 Preconfig Function Function Name em1_ddr_preconfig Format void em1 ddr preconfig void Argument None Function Return None Function Flow START Enbale Input Port CHG PULLO Y Set Port Drive Ability to 12mA CHG DRIVEO Figure A 1 Preconfig for DDR Initialization Note Set EMMA Mobile 1 CHG register for DDR SDRAM interface initialization 1 Set the port to INPUT port and Pull down 2 Set the drive ability to 12mA About CHG register please refer to EMMA Mobile 1 One Chip User s Manual Application Note 819908EJ 1VOANOO 41 57 APPENDIX A DDR SDRAM DRIVER FUNCTION A 3 2 Reset Function Function Name ddr reset Format void em1 ddr reset void Argument None Function Return None Function Flow C START E Y
38. ntirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundanoy fire containment and anti failure features Note 1 NEC Electronics as used in this document means NEC Electronics Corporation and also includes its majority owned subsidiaries NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above All trademarks or registered trademarks are the property of their respective owners Registered trademarks and trademarks are not noted in this document Application Note 819908EJ1VOANOO INDEX 4 57 CONTENTS Chapter T E 8 Len 8 1 2 Development eue 8 Chapter 2 Usage of DDR SDRAM Interface J J J J J 9 2 1 Normal Procedure of DDR SDRAM Operation 9 2 2 Detail of Normal DDR SDRAM Data Transfer Procedure 10 2 2 1 Configure DDR and DDR ASMU Register 10 2 2 2 Initialize DDR SDRBAM TIOGdUle siii race
39. r procedure of CPU transfer mode 3 7 1 Operation Flow Operation flow chart of this sample is shown as below C START gt Set the target memory Data Transfer Figure 3 8 Flow of CPU Transfer Mode Sample 3 7 2 Operation Detail 1 Set the source data area and the destination data area The source address is set to 0x3000 0000 The destination address is set to 0 3080 0000 Application Note 819908EJ 1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 26 57 2 Start data transfer by CPU mode Data is transferred from the source address to the destination address by each 32 bits 0 3000 0000 Source area 0x307F FFFF 0x3080 0000 T Destination Ox30FF FFFF Note In this sample 1 LED will light when process the CPU data transfer is used for the output port Application Note 819908EJ 1VOANOO CHAPTER 3 EXAMPLE OF DDR SDRAM OPERATION 27 57 3 8 DDR Sample6 Transfer with Mode This sample shows the data transfer procedure of DMA transfer mode with 1 channel and 3 channels 3 8 1 Operation Flow Operation flow chart of the sample with 1 DMA channel is shown as below 6 START Set the DDR Int handler call function ddr Y Start DMA transfer ARM CONT Enable INT SEC ITO 51 Y INTC_I
40. rtain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electron
41. y auto cal void Argument None Function Return None Function Flow START E Turn OFF MEMC CLK auto control mode ASMU_AHBCLKCTRL41 Turn OFF MEMC CLK270 auto control mode ASMU_CLKCTRL Set MEMC CLK270 to MEMC CLK ASMU MEMCCLK 270 SEL Set calibration pattern to gt 0 5555 MEMC DDR Set the delay time MEMC DDR 2 Recovery MEMC CLK auto control mode ASMU AHBCLKCTRL1 Recovery MEMC CLK270 auto control mode ASMU_CLKCTRL Reset MEMC CLK270 ASMU 270 SEL Y uL Figure A 10 Set Delay Auto Calibration Note None Application Note 819908EJ1VOANOO 55 57 APPENDIX A DDR SDRAM DRIVER FUNCTION A 3 11 Enable Disable System Cache Function Name ddr enable sys cache Format void em1 ddr enable sys cache BOOL bEnable Argument Parameter Type Detail Enbale Disable Flag bEnable BOOL TRUE Enable system cache 56 57 FALSE Disable system cache Function Return None Function Flow None Note Enable Disable system cache function by set register DEGFUN Application Note 819908EJ1VOANOO ANNEX MODIFICATION HISTORY 57 57 ANNEX Modification History Application Note 819908EJ 1VOANOO
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