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1. eau aape ebeduppe lt lt lt INVHX juo Auo ejeq uAy Auo lt sng od e sngc od e 24 04 sng od e sng od e sngce od e aovdx pesn 51 pesn 51 pesn 5 pesn 1 pesn 51 pesn 5 2 2 2 2 2 uw auta eoe WVYX lt O I lt d lt lt O I lt d lt gt IH sng od e sng od e sng od e sng od e sng od e sngce od e 3ovdX XAOW 1 pesn si WWHX 9 1 pesn si WWHxX 9 9 pesn s 5 9 pesn si ssouppe uw daa INVHX eyeq HAy ejeq HAW Auo ejeq HA z sngc ed od e sna c zd od e O re zd od e snge zd od e sng zd od e sng zd od e 1 1 1 1 51 1 SSoJppe 2
2. internal external internal external Status Voltage range ROM ROM ROM ROM at pin PO Data float Data float P1 Data alt Data alt Data last Data last floating outputs outputs outputs outputs P2 Data Address Data Data output P3 Data alt Data alt Data Data outputs outputs outputs last output last output P4 Data alt Data alt Data last Data disabled Vss lt Vin lt outputs outputs outputs last output P5 Data Data Data Data input alt output alt output last output last output P6 Data Data Data Data function alt output alt output output last output P7 P8 EA active input Vi Vin Vss PE SWD active input Vin pull up Vss disabled XTAL1 active output pin not be driven XTAL2 disabled Vss lt lt input functions Semiconductor Group 7 52 SIEMENS Device Specification Table 8 Status of all pins during Idle Mode Power Down Mode and Hardware Power Down Mode cont d Pins Idle Mode Power Down Mode Hardware Power Down Last instruction Last instruction executed from executed from internal external internal external Status Voltage range ROM ROM ROM ROM at pin PSEN floating Vss lt ViNS outp dis ALE abled input functions VAREF active sup lt VIN VAGND ply pins lt OWE active input must be high pull up disabl RESET active i
3. 2 2 2 2 INVHX eAnoe euo gt Hlda sngc ezd od e sng zd od e sng e zd od e sng zd od e sng zd od e sng ed od e XAON OL 00 LX OL 00 OdVINX Ld VINX OdVINX Ld VINX L Vai 0 3 17 Semiconductor Group SIEMENS System Reset 4 System Reset 41 Additional Hardware Power Down Mode in the SAB 80C517A SAB 80C517A has an additional Power Down Mode which be initiated by an external signal at a dedicated pin This pin is labeled HWPD and is a floating input line active low This pin substitutes one of the VSS pins of the base types SAB 800517 PLCC84 Pin60 100 2 Pin36 Because this new power down mode is activated by an external hardware signal this mode is referred to as Hardware Power Down Mode in opposite to the program controlled Software Power Down Mode For a correct function of the Hardware Power Down Mode the oscillator watchdog unit including its internal RC oscillator is needed Therefore this unit must be enabled by pin OWE OWE High if the Hardware Power Down Mode shall be used However the control pin PE SWD has no control function for the Hardware Power Down Mode it enables and disables only the use of all software controlled power savin
4. WVYX gt XAOW Hldao XAOW 1 23 Semiconductor Group SIEMENS Device Specification Multiple Datapointers As a functional enhancement to standard 8051 controllers the SAB 80C517A contains eight 16 bit datapointers The instruction set uses just one of these datapointers at a time The selection of the actual datapointer is done in special function register DPSEL data pointer select addr 924 Figure illustrates the addressing mechanism DPSEL 92y DPTR7 DPSEL Selected Data 2 1 0 pointer 0 0 0 DPTR O S DPTRO 0 0 1 DPTR 1 0 1 0 DPTR 2 85 DPL 82y 0 1 1 DPTR 3 1 0 0 DPTR 4 1 DPTR 5 External Data Memory 1 1 0 DPTR 6 MCD00779 1 1 1 DPTR 7 Figure 3 Addressing of External Data Memory Semiconductor Group 7 24 SIEMENS Device Specification Special Function Registers All registers except the program counter and the four general purpose register banks reside in the special function register area The 81 special function registers include arithmetic registers pointers and registers that provide an interface between the CPU and the on chip peripherals There are also 128 directly addressable bits within the SFR area All special function registers are listed in table 1 and table 2 In table 1 they are organized in numeric order of their addresses In table 2 they are orga
5. 1 or if addresses outside the XRAM address range are used for MOVX accesses XMAP1 0 The signals RD and WR are not activated during accesses to XRAM XMAP1 1 The signals RD and WR are activated during accesses to XRAM Reset value of SYSCON is XXXX XX01B The control bit is a global enable disable bit for the additional On Chip RAM If this bit is set the XRAM is disabled all MOVX accesses use external memory via the external bus In this case the SAB80C517A can t use the additional On Chip RAM and is compatible with the types without XRAM Semiconductor Group 3 15 SIEMENS Memory Organization A hardware protection is done by an unsymetric latch at XMAPO bit A unintentional disabling of XRAM could be dangerous since indeterminate values could be read from external bus To avoid this the XMAP bit is forced to 1 only by reset Additional during reset an internal capacitor is loaded So the reset state is a disabled XRAM Because of the load time of the capacitor XMAPO bit once written to 0 that is discharging capacitor cannot be set to 1 again by software On the other hand any distortion software hang up noise is not able to load this capacitor too That is the stable status is XRAM enabled The only way to disable XRAM after it was enabled is a reset The clear instruction for the XMAPO bit should be integrated in the program initialization routine before XRAM is used
6. 20 ns Fall time CcHCL 20 ns Oscillator frequency l teic 3 5 18 MHz Voc 0 5V 0 2 0 1 External Clock Cycle Semiconductor Group 7 69 SIEMENS Device Specification AC Characteristics cont d Parameter Symbol Limit values Unit 18 MHz clock Variable clock 1 t cL cL 3 5 MHz to 18 MHz min max min max System Clock Timing ALE to CLKOUT fLLSH 349 7 40 ns CLKOUT high time tSHSL 71 2 40 l 5 CLKOUT low time 516 101 40 ns low to ALE SLLH 16 96 40 40 9 CLKOUT his Programm Memory Access Data Memory Access RD WR MCTO0794 System Clock Timing Semiconductor Group 7 70 SIEMENS Device Specification ROM Verification Characteristics 25 5 5 10 Vss Parameter Symbol Limit values Unit min max ROM Verification Mode 1 Standard Verify Mode for not Read Protected ROM Address to valid data fAVQV E 48 tei c ns ENABLE to valid data fELQV 48 tci cL ns Data float after ENABLE teyoz 0 48 tci cL ns Oscillator frequency 4 6 2 1 0 1 7 2 0 2 6 Data Out Port 0 2 7 ENABLE MCD01 498 Address P1 0 P1 7 A0 A7 Inputs
7. 14 21 2 is a bidirectional port with internal pull up resistors Port 2 pins that have 1s written to them are pulled high by the internal pull up resistors and in that state can be used as in puts As inputs port 2 pins being externally pulled low will source current 11 in the DC characteristics because of the internal pull up resistors Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pull up resistors when issuing1 s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 issues the contents of the P2 special function register Input O Output Semiconductor Group SIEMENS Device Specification Pin Definitions and Functions cont d Symbol Pin Number P LCC 84 100 2 Function PSEN 49 22 The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations It is activated every six oscillator periodes except during external data memory accesses Remains high during internal program execution ALE 50 23 The Address Latch Enable output is used for latching the address into external memory during normal operation It is activated every six oscillator perio
8. 46 10 ns after PSEN Address valid after 48 8 ns PSEN Address to valid instr in tayiy 218 60 5 Address float to PSEN 0 0 Interfacing the SAB 80C51 7A to devices with float times up to 45 ns is permissible This limited bus contention will not cause any damage to port 0 drivers Semiconductor Group 7 65 SIEMENS Device Specification AC Characteristics cont d Parameter Symbol Limit values Unit 18 MHz clock Variable clock 1 t 3 5 MHz to 18 MHz min max min max External Data Memory Characteristics RD pulse width 233 100 WR pulse width 233 100 Address hold after 81 214 30 ns RD to valid data in RLDV 128 150 ns Data hold after RD tRHDX 0 0 Data float after RD tRHDZ 51 2 60 ns ALE to valid data in fLLDV 294 815 0 150 ins Address to valid data in 335 9 165 ins ALE to WR or RD 117 217 50 50 WR RD high to ALE 16 96 40 40 high Address valid to WR fAVWL 92 4 180 Data valid to WR tavwx 11 45 transition Data setup before
9. The registers ADDATH 009 and ADDATL ODAH contain the 10 bit conversion result The data is read as two 8 bit bytes Data is presented in left justified format i e the msb is the most left hand bit in a 16 bit word To get a 10 bit conversion result two READ operations are required Otherwise ADDATH contains the 8 bit conversion result Semiconductor Group 5 6 SIEMENS On Chip Peripheral Components A D Converter Timing After a conversion has been started by a write to ADDATL external start by P6 0 ADST or in continous mode the analog input voltage is sampled for 4 clock cycles The analog source must be capable of charging the capacitor network of appr 50 pF to full accuracy in this time During this period the converter is susceptable to spikes and noise at the analog input which may cause wrong codes at the digital outputs Therefore RC filtering at the analog inputs is recommended see figure 5 2 below Conversion of the sampled analog voltage takes place between the 4th an 14th clock cycle Analog Input o e A INx AGnd 00 2 SAB 80 517 00 nF Ceramic SAB 83 517 5 02250 Figure 5 2 Recommended RC filtering at the Analog Inputs Semiconductor Group 5 7 SIEMENS On Chip Peripheral Components 5 3 Additional Compare Mode for the Concurrent Compare Unit The SAB 80C517A has an additional compare mode compare mode 2 in the Compare Capture Unit which can be
10. taywu 239 7 150 ns Data hold after WR tWHOX 16 40 Address float after RD tp az 0 0 Semiconductor Group 7 66 SIEMENS Device Specification ALE PSEN Port 0 Port 2 8 A15 A8 A15 00096 ALE PSEN lt gt Port 0 Data In C XN NN 7 from PCL 2 2 0 2 7 8 15 from DPH 8 15 from PCH 00791 Data Memory Read Cycle Semiconductor Group 7 67 SIEMENS Device Specification m ALE PSEN a t LLWL E WLWH lovwx LLAX2 twHax A0 A7 from X AO A7 Ri or DPL Data OUT from PCL law Port 2 P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH Port 0 Instr IN MCT00098 Data Memory Write Cycle Semiconductor Group 7 68 SIEMENS Device Specification AC Characteristics cont d Parameter Symbol Limit values Unit Variable clock Frequ 3 5 MHz to 18 MHz min max External Clock Drive Oscillator period 55 6 285 ns High time tCHCX 20 tCLOL LCHCX ns Low time 20 ICLCL CHCX ns Rise time
11. because of the internal pull up resistors Port 6 also contains the external A D converter control pin and the transmit and receive pins for serial channel 1 The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate The secondary functions are assigned to the pins of port 6 as follows ADST P6 0 external A D converter start pin 1 P6 1 receiver data input of serial interface 1 TxD1 P6 2 transmitter data output of serial interface 1 P8 0 P8 3 78 81 57 60 Port 8 is a 4 bit unidirectional input port Port pins can be used for digital input if voltage levels meet the specified input high low voltages and for the higher 4 bit of the multiplexed analog inputs of the A D converter simultaneously Input Output Semiconductor Group SIEMENS Device Specification Pin Definitions and Functions cont d Symbol Pin Number lO Function P LCC 84 P MQFP 100 2 RO 82 61 Reset Output This pin outputs the internally synchronized reset request signal This signal may be generated by an external hardware reset a watchdog timer reset or an oscillator watch dog reset The reset output is active low Vss 37 83 10 62 Circuit ground potential Voc 38 84 11 63 Supply Terminal for all operating modes N C 2 5 25 Not connected 28 29 51 53 74 77 8
12. A small internal pull up resistor permits power on reset using only a capacitor connected to V AREF 11 78 Reference voltage for the A D con verter V AGND 12 79 Reference ground for the A D converter P7 7 P7 0 80 87 Port 7 is an 8 bit unidirectional input port Port pins can be used for digital input if voltage levels meet the specified input high low voltages and for the lower 8 bit of the multiplexed analog inputs of the A D converter simultaneously Input Output Semiconductor Group SIEMENS Device Specification Pin Definitions and Functions cont d Symbol Pin Number P LCC 84 100 2 0 Function P3 0 P3 7 21 28 90 97 3 is a bidirectional I O port with internal pull up resistors Port 3 pins that have 1s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs port 3 pins being externally pulled low will source current the DC characteristics because of the internal pull up resistors Port 3 also contains the interrupt timer serial port 0 and external memory strobe pins that are used by various options The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate The secondary functions are assigned to the pins of port 3 as follows Rx 00
13. D8H ADCONO F8H 5 1 FFy D9H ADDATH 00H 9 DAW ADDATL 00H FAH P6 FFH DBH P7 XXH FBH DCy ADCON1 XXXX 0000p DDH P8 XXH FDH CTRELL 00H FEH DFH CTRELH 00H 1 Bit addressable Special Function Register Semiconductor Group 3 5 SIEMENS Memory Organization Table 3 1 Special Function Register cont d Block Symbol Name Address Contents after Reset XRAM XPAGE Page Address Reg for extended onchip 91 4 00H RAM SYSCON XRAM Control Reg BiH XXXX XX01 p CPU ACC Accumulator E0y 00H B B Register 00H DPH Data Pointer High Byte 83H 00H DPL Data Pointer Low Byte 824 00H DPSEL Data Pointer Select Register 924 XXXXX000p PSW Program Status Word Register 00H SP Stack Pointer 81 07 ADCONO A D Converter Control Register 0 8 00H Converter ADCON1 A D Converter Control Register 1 DH 00H ADDATH A D Converter Data Register High Byte D9H 00H ADDATL A D Converter Data Register Low Byte DAH 00H Interrupt Interrupt Enable Register 0 8 00H System CTCON Com Timer Control Register 1 0X00 000053 Interrupt Enable Register 1 B8y 00H IEN2 Interrupt Enable Register 2 9AH XX00 00 0 IPO Interrupt Priority Register 0 AgH 00H Interrupt Priority Register 1 9 XX00 00006 IRCONO Interrupt Request Control Register 00H IRCON1 Interrupt Request Control Register Dig 00H TCON 2 Timer
14. implemented Its successive approximation technige provides 7 us conversion time 16 MHz The conversion principle is upward compatible to the one used in the SAB 80C517 The major components are shown in figure 5 1 The comparator is a fully differential comparator for a high power supply rejection ratio and very low offset voltages The capacitor network is binary weighted providing 10 bit resolution The table 5 1 below shows the sample time 7 and the conversion time including 75 which depend on fosc and the selected prescaler see also Bit ADCL in SFR ADCON 1 Table 5 1 ADC Convertion Time fosc MHz Prescaler fapc MHz Ts us us incl 75 12 8 1 5 1 33 8 16 0 75 2 8 16 16 8 2 0 2 0 7 0 16 1 0 4 0 14 0 18 8 16 1 125 3 555 12 4 Semiconductor Group 5 3 SIEMENS On Chip Peripheral Components P 8 DDy internal Bus P 7 DBy yp ADCON DCH ADCONO 08 y ADEX BSY ADM MX 2 MX 7A 5 4 3 2 1 2 Y ADDATH ADDATL Port 8 Single 09 Continous Mode MUX Port 7 A D Converter P6 0 ADST Write to ADDATL internal Bus Shaded areas are not used in ADC functions MCBO1 488 Figure 5 1 10 Bit A D Converter Semiconductor Group 5 4 SIEMENS On Chip Peripheral C
15. 1 cd sng od e pesn s 9 uy qu 9 eyeq uw Sn8 zd od e 9 q O le ed 5184 04 pesn s WWHX O le 2d 0d e s 2 9 0 sng od pasn 9 9 5 0 9 gau 9 01 518 044 pesn s Nvux 9 9 eyeq 9 0 1 lt 518 044 e pesn 9 HM du eyed Sna8 ed od INVHX gt WVYX lt pesn pesn pesn pesn pesn pesn 9 s 2 SI 1x9 2 s 2 s 2 s 1xe 2 9 9 9 9 9 sng ed od sng ed od 0 e sng zed od 2 0 2 0 LX 01 00 LX OL 00 Od VINX Ld VINX OdVINX Ld VINX Wa 0 PU Zd Od 10 L
16. Contents Address Register Contents after Reset after Reset 1 00H F8y P5 1 reserved XXH F9H reserved XXH F2u CML6 00H FAH P6 OFFy F3y CMH6 00H reserved XXy F44 CML7 00H FCH reserved XXH Foy CMH7 150 XXH 00H FEy 151 XXy F7y CMSEL 001 reserved XXH 1 Bit addressable special function registers 2 X means that the value is indeterminate and the location is reserved 9 SFRs not user accessable Semiconductor Group 7 27 SIEMENS Device Specification Table 3 Special Function Registers Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC Accumulator 00 B B Register OFO 7 00 Data Pointer High Byte 83H 00H DPL Data Pointer Low Byte 82 00H DPSEL Data Pointer Select Register 924 XXXX X000B PSW Program Status Word Register 00H SP Stack Pointer 81 07 A D ADCONO A D Converter Control Register 0 008 7 00 Converter 1 A D Converter Control Register 1 00H ADDATH A D Converter Data Reg High Byte ADDATL A D Converter Data Reg Low Byte ODA 00H Interrupt Interrupt Enable Register 0 8 00 System CTCON 2 Com Timer Control Register 1 0X00 0000B IEN1 Interrupt Enable Register 1 00 IEN2 Interrupt Enable Register 2 XX00 00X0B IPO Interrupt Priority Register O 0 9 00H IP1 Interrupt P
17. Control Register 88H 00H T2CON Timer 2 Control Register MUL DIV ARCON Arithmetic Control Register XXXXp Unit MDO Multiplication Division Register 0 XXH MD1 Multiplication Division Register 1 XXH MD2 Multiplication Division Register 2 EBH XXH MD3 Multiplication Division Register 3 ECH XXH MD4 Multiplication Division Register 4 EDH XXH MD5 Multiplication Division Register 5 EEH XXH Compare Comp Capture Enable Reg 1 00H Capture CC4EN Comp Capture 4 Enable Reg 00H Unit CCH1 Comp Capture Reg 1 High Byte C3y 00H CCU CCH2 Comp Capture Reg 2 High Byte 5 00H Timer2 CCH3 Comp Capture Reg 3 High Byte C7H 00H CCH4 Comp Capture Reg 4 High Byte 00H CCL1 Comp Capture Reg 1 Low Byte C2y 00H 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is indeterminate Semiconductor Group SIEMENS Memory Organization Table 3 1 Special Function Register Block Symbol Name Address Contents after Reset Compare CCL2 Comp Capture Reg 2 Low Byte 00H Capture CCL3 Comp Capture Reg 3 Low Byte 00H Unit CCU CCL4 Comp Capture Reg 4 Low Byte 00H cont d CMEM Compare Enable Register F6H 00H CMHO Compare Reg 0 High Byte 00H 1 Compare Reg 1 High Byt
18. FFH 91H XPAGE 00H 1 SYSCON XXXX XX01p 92H DPSEL XXXXX000B 2 93H 94 4 95H 5 96H 97H B7H E 98 SOCON 00H IEN1 00H 99H SOBUF XXH XX00 0000 IEN2 XX00 00X0p SORELH XXXX XX11p 9By 91 0X00 0000p BBy S1RELH XXXX XX11p 9CH S1BUF XXH BCH S1RELL 00H BDH 1 Bit addressable Special Function Register Semiconductor Group 3 4 SIEMENS Memory Organization Table 3 1 Special Function Register cont d Address Register Contents Address Register Contents after Reset after Reset IRCONO 00H 00H 1 00H 1 0X00 0000p C2y CCL1 00H E24 CML3 00H C3H CCH1 00H E3H CMH3 00H CCL2 00H 4 CML4 00H C5y CCH2 00H E5H CMH4 00H C6H CCL3 00H CML5 00H C7H CCH3 00H E7H CMH5 00H T2CON 00H E8y P4 FFy CC4EN 00H E9H MDO XXH CAH CRCL 00H EAH MD1 XXH CBH CRCH 00H EBH MD2 XXH CCH TL2 00H ECH MD3 XXH CDH TH2 00H EDH MD4 XXH CEH CCL4 00H MD5 XXH 4 00H EFH ARCON XXXXp DOW PSW 1 00H FO B 00H Diy IRCON1 00H D2y CMLO 2 CML6 D3H CMHO 00H CMH6 00H D4y 00H CML7 00H D5H CMH1 00H F5H CMH7 00H D6H CML2 00H 00H D7y CMH2 00H F7u CMSEL 00H
19. PSEN Vs 2 0 2 6 8 14 ALE EA Data 0 0 0 7 00 07 RESET ROM Verification Mode 1 Semiconductor Group 7 71 SIEMENS Device Specification ROM Verification Mode 2 New Verify Mode for Protected and not Protected ROM 55 54 55 5 4 595 91 52 54 5 4 52 54 SS P2 p Pl P2 p p p 1 sample RESET int EE ALE ey ATATA ROM Code ROM Code ROM Code Port 0 adr 00004 adr 00014 adr 00024 1 00149 Y Y MCD01499 RESET State Increment Address counter for external ROM Inputs ALE forced to low level a weak pull down resistor 4000 during RESET activ ROM Code Port 0 00 07 Outputs Port 3 5 shows all 1024 cycles low level for one cycle when compared ROM Code was not alright ROM Verification Mode 2 Semiconductor Group 7 72 SIEMENS Device Specification Compare Result Logic SAB 83C517A 5 Address Counter 16 bit Reset Adr Counter Compare ROM H Reset pare Code MCB01541 Application Circuitry for Verifying the Internal ROM Semiconductor Group 7 73 SIEMENS Device Specification Vor 0 5V 0 2 Voc 0 9V Test Points 0 2 Vee 0 1V 0 45V 00697 AC Inputs during testing are driven at 0 5 V for a l
20. ROM SAB 83C517A 5 only ROM Protection available 256x8 on chip RAM 2Kx8 on chip RAM XRAM Superset of SAB 80C51 architecture 1 Us instruction cycle time at 12 MHz 666 ns instruction cycle time at 18 MHz 256 directly addressable bits Boolean processor 64 Kbyte external data and program memory addressing Four 16 bit timer counters Powerful 16 bit compare capture unit CCU with up to 21 high speed or PWM output channels and 5 capture inputs Versatile fail safe provisions Fast 32 bit division 16 bit multiplication 32 bit normalize and shift by peripheral MUL DIV unit MDU Eight data pointers for external memory addressing Seventeen interrupt vectors four priority levels selectable genuine 10 bit A D converter with 12 multiplexed inputs Two full duplex serial interfaces with programmable Baudrate Generators Fully upward compatible with SAB 80C515 SAB 806517 SAB 80C515A Extended power saving modes Fast Power On Reset Nine ports 56 I O lines 12 input lines Three temperature ranges available 0 to 70 C T1 40 to 85 4010 110 4 Plastic packages P LCC 84 P MQFP 100 2 The pin functions of the SAB 80C517A are identical with those of the SAB 80C517 80C537 with one exception Package SAB 80C517A SAB 80C517 80C537 PLCC 84 60 HWPD Vas 100 72 Semiconductor Group 1 2 SIEMENS Fundamental Structure 2 Fundamenta
21. XPAGE MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr 914 XPAGE The reset value of XPAGE is XPAGE can be set and read by software Figures 3 2 to 3 4 show the dependencies of XPAGE and Port 2 addressing in order to explain the differencies in accessing XRAM ext RAM or what is to do when Port 2 is used as an l O port Semiconductor Group 3 10 SIEMENS Memory Organization gt Port 0 Address Data XRAM Write to Port 2 gt lt gt Page Address Se MEN ER P COL NUN ME CON EN MCB02112 Figure 3 2 Write Page Address to Port 2 MOV P2 pageaddress will write the page address to Port 2 and XPAGE Register When external RAM is to be accessed in the XRAM address range F800 XRAM has to be disabled When additional external RAM is to be addressed in an address range lt XRAM 800 XRAM may remain being enabled and there is no need to overwrite XPAGE by a second move Semiconductor Group 3 11 SIEMENS Memory Organization gt Port 0 K 5 Address Data XRAM Write to XPAGE Address gt E 0 Data 12 2113 Figure 3 3 Write Page Address to XPAGE The page address is only written to XPAGE register Port 2 is available for addresses or l O Data See figure 3 4 to see what happens when Port 2 is
22. design From the device s point of view it cannot be decided whether the Port 2 data is used externally as address or as data Hence a special page register is implemented into the SAB 80C517A to provide the possibility of accessing the XRAM also with the MOVX Ri instructions i e XPAGE serves the same function for the XRAM as Port 2 for external data memory Semiconductor Group 7 19 SIEMENS Device Specification Special Function Register XPAGE Addr 914 XPAGE The reset value of XPAGE is XPAGE can be set and read by software The register XPAGE provides the upper address byte for accesses to XRAM with MOVX Ri instructions If the address formed from XPAGE and Ri is less than the XRAM address range then an external access is performed For the SAB 80C517A the contents of XPAGE must be greater or equal than F8y in order to use the XRAM Of course the XRAM must be enabled if it shall be used with MOVX Ri instructions Thus the register XPAGE is used for addressing of the XRAM additionally its contents are used for generating the internal XRAM select If the contents of XPAGE is less than the address range then an external bus access is performed where the upper address byte is provided by P2 and not by XPAGE Therefore the software has to distinguish two cases if the MOVX Ri instructions with paging shall be used Access to XRAM The upper address byte must be wr
23. reset time MCT02254 Figure 4 2 Timing Diagram of Leaving Hardware Power Down Mode Semiconductor Group 4 6 SIEMENS System Reset 92 0 91 54 S3 S4 S5 S6 SI S2 S3 S4 S5 S6 SI S2 S3 S4 509075259 S4 S5 S6 Epp n n Ug 1 Sample HWPD HWPD MMMM Pg Pa eee es ew VR ae ULIS ah oe tee P te lt Ce eRe TA 02253 Figure 4 3 Timing Diagram of Hardware Power Down Mode HWPD Pin is Active for only one cycle Semiconductor Group SIEMENS System Reset 4 3 Fast internal Reset after Power On The SAB 80C517A can use the oscillator watchdog unit for a fast internal reset procedure after power on Figure 4 4 shows the power on sequence under control of the oscillator watchdog Normally the devices of the 8051 family like the SAB 80C517 enter their default reset state not before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 1ms During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins In the SAB 80C517A the oscillator watchdog unit can avoid this situation For doing this the oscillator watchdog must be enabled In
24. setting or clearing one bit in special function register IPO and one in Figure 9 shows the interrupt request sources the enabling and the priority level structure Semiconductor Group 7 42 SIEMENS Device Specification Highest Priority Level gt Lowest Priority Level Receiver Ser Channel Transmitter A D Converter 5 070 Timer 0 Overflow MCS01 492 Figure 10 Interrupt Structure of the SAB 80 517 Semiconductor Group 7 43 SIEMENS Device Specification Highest Priority Level gt Lowest Priority Level nil P i n g 5 q n Timer 1 Overflow TF1 Compare Timer CTF Overflow P1 1 INT4 CC1 4 501 493 Figure 10 Interrupt Structure of the SAB 80C517A cont d Semiconductor Group 7 44 SIEMENS Device Specification Highest Priority Level Receiver Ser Channel 0 Transmitter P1 2 INT5 CC2 Match COMSET P i n g 5 q u e Timer 2 Overflow 1 5 2 P1 3 INT6 CC3 Match in COMCLR 501 494 Figure 10 Interrupt Structure of the SAB 80C517A cont d Semiconductor Group 7 45 SIEMENS Device Specification Multiplication Division Unit This on chip arithmetic unit provides fast 32 bit division 16 bit multiplication a
25. the following formula oscillator frequency 32 x 210 51 Mode A B baud rate with S1REL S1RELH 1 0 STRELL 7 0 Figure 5 6 shows a block diagram of the baud rate generator for Serial Interface 1 SRELH 1 0 Baud Rate Clock Phase 2 CLK fsc 2 gt 10 Bit Timer Overflow MCT02119 Figure 5 6 Baud Rate Generator for Serial Interface 1 Semiconductor Group 5 17 SIEMENS On Chip Peripheral Components Special Function Register SRELH SRELL MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr OBBY msb MSB LSB Bit No 7 6 5 4 3 2 1 0 Isb Addr 09 shaded areas are not used for programming the baudrate timer S1RELH S1RELL Bit Function S1RELH 0 1 Reload value Upper two bits of the timer reload value S1RELL 0 7 Reload value Lower 8 bit of timer reload value Reset value of S1RELL is 00H STRELH contains XXXX XXX11B Semiconductor Group 5 18 SIEMENS On Chip Peripheral Components 5 5 Modified Oscillator Watchdog Unit The SAB 80C517A has a new oscillator watchdog unit that has an improved functionality with respect to the SAB 80C517 s oscillator watchdog Use of the Oscillator Watchdog Unit The unit serves three functions Monitoring of the on chip oscillator s function The watchdog supervises the on chip oscillator s frequency if it is lower than t
26. typ less than 2 microseconds Because the oscillator watchdog is active it detects a failure condition if the on chip oscillator hasn t yet started Hence the watchdog keeps the part in reset and supplies the internal clock from the RC oscillator Finally when the on chip oscillator has started the oscillator watchdog releases the part from reset after it performed a final internal reset sequence and switches the clock supply to the on chip oscillator This is exactly the same procedure as when the oscillator watchdog detects first a failure and then a recovering of the oscillator during normal operation Therefore also the oscillator watchdog status flag is set after restart from Hardware Power Down Mode When automatic start of the watchdog was enabled PE SWD connected to the Watchdog Timer will start too with its default reload value for time out period The SWD Function of the PE SWD Pin is sampled only by a hardware reset Therefore at least one Power On Reset has to be performed Semiconductor Group 4 3 SIEMENS System Reset 4 2 Hardware Power Down Reset Timing Following figures are showing the timing diagrams for entering figure 4 1 and leaving figure 4 2 the Hardware Power Down Mode If there is only a short signal at pin HWPD i e HWPD is sampled active only once then a complete internal reset is executed Afterwards the normal program execution starts again figure 4 3 Note Delay time caused by in
27. used for the compare functions The secondary functions are assigned to the port 1 pins as follows P1 0 interrupt 3 input compare 0 output capture 0 input INT4 CC1 P1 1 interrupt 4 input compare 1 output capture 1 input INT5 CC2 P1 2 interrupt 5 input compare 2 output capture 2 input INT6 CC3 P1 3 interrupt 6 input compare 3 output capture 3 input INT2 CC4 P1 4 interrupt 2 input compare 4 output capture 4 input T2EX P1 5 timer 2 external reload trigger input CLKOUT 1 6 system clock output T2 P1 7 counter 2 input Input O Output Semiconductor Group SIEMENS Device Specification Pin Definitions and Functions cont d Symbol Pin Number P LCC 84 P MQFP 100 2 Function XTAL2 39 12 XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits XTAL1 13 XTAL1 Output of the inverting oscillator amplifier To drive the device from an external clock source XTAL2 should be driven while XTAL1 is left unconnected There no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is devided down by a divide by two flip flop Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed P2 0 P2 7 41 48
28. watchdog s reset request is released figure 4 4 However an externally applied reset still remains figure 4 4 IV active and the device does not start program execution figure 4 4 V before the external reset is also released Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up The reasons are as follows Termination of Hardware Power Down Mode a HWPD signal is overridden by reset Termination of Software Power Down Mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence The external reset signal must be hold active at least until the on chip oscillator has started and the internal watchdog reset phase is completed An external reset time of more than 5 ms should be sufficient in typical applications If only a capacitor at pin Reset is used a value of 100 nF provides the desired reset time Semiconductor Group 4 9 System Reset SIEMENS 60Z0VON 91249 89 04 250 Aq aouanbas jouBisjasay xo PES gt lt 10 95 gt 4 19594 DUL4 gt 959 ul SUIDWa 8151 950 9149 00 STI _ sng dl p UQ JeMog josoy 994 950 OY 250 diu5 uo F
29. 119 Figure 5 4 Baud Rate Generator for Serial Interface 0 The default value after reset of SORELL is 50 RELH contains XX11B Semiconductor Group 5 14 SIEMENS On Chip Peripheral Components Special Function Register SORELH SORELL MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr OBAY msb MSB LSB Bit No 7 6 5 4 3 2 1 0 Isb Addr shaded areas are not used for programming the baudrate timer SORELH SORELL Bit Function SORELH 0 1 Reload value Upper two bits of the timer reload value SORELL 0 7 Reload value Lower 8 bit of timer reload value Reset value of SORELL is OD9 SORELH contains XXXX XXX11B Semiconductor Group 5 15 SIEMENS On Chip Peripheral Components Figure 5 5 shows a block diagram of the options available for baud rate generation of Serial Channel 0 It is a fully compatible superset of the functionality of the SAB 80C517 The new baud rate generator can be used in modes 1 and 3 of the Serial Channel 0 It is activated by setting bit BD ADCONO 7 This also starts the baud rate timer When Timer1 shall be used for baud rate generation bit BD must be cleared In any case bit SMOD PCON 7 selects an additional divider by two The default values after reset in registers SORELL and SORELH provide a baud rate of 4 8 kBaud with SMOD 0 or 9 6 kBaud with SMOD 1 at 12 MHz oscillato
30. 2 Low Byte 0C4y 00H CCL3 Comp Capture Reg 3 Low Byte 0C6 CCL4 Comp Capture Reg 4 Low Byte 00H CMEN Compare Enable Register 00H CMHO Compare Register 0 High Byte 00H CMH1 Compare Register 1 High Byte 5 00H CMH2 Compare Register 2 High Byte OD7y CMH3 Compare Register 3 High Byte 00H CMH4 Compare Register 4 High Byte OE5y 00H CMH5 Compare Register 5 High Byte 7 00H CMH6 Compare Register 6 High Byte OF3y CMH7 Compare Register 7 High Byte OFSy CMLO Compare Register 0 Low Byte 002 00H CML1 Compare Register 1 Low Byte 004 CML2 Compare Register 2 Low Byte 00H CML3 Compare Register 3 Low Byte OE2y 00H CML4 Compare Register 4 Low Byte OE4y 00H CML5 Compare Register 5 Low Byte 00H CML6 Compare Register 6 Low Byte OF2y 00H CML7 Compare Register 7 Low Byte 00 CMSEL Compare Input Select OF7y Com Rel Capt Reg High Byte OCBy 00H CRCL Com Rel Capt Reg Low Byte 00H COMSETL Compare Register Low Byte 0 1 00H COMSETH Compare Register High Byte 0A24 00H COMCLRL Compare Register Low Byte 00H COMCLRH Compare Register High Byte 0 4 SETMSK Mask Register concerning 5 00H COMSET 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means th
31. 2 Interrupt Request shaded areas are not used for this function 01490 Figure 6 Block Diagram of Timer 2 Semiconductor Group 7 39 SIEMENS Device Specification Control CTCON Compare Timer fosc 2 05 3 Bit Prescaler 16 Compare Timer 16 Reload CTREL gt Circuitry gt To Interrupt Circuitry Overflow MCB00783 Figure 7 Block Diagram of the Compare Timer 6 Overflow Compare Timer Compare Latch Compare Register CTF Output PA x CMx Circuit MCA00784 Figure 8 Compare Mode 0 with Registers CMO to CM7 Semiconductor Group 7 40 SIEMENS Device Specification Timer COMSET COMCLR 9 o P5 0 Number of Pins ICS ICR for this functions is id selectable from 1 to 8 S ECS by bit IEN2 4 IEN2 5 COCONO COCON2 di IPs CC4EN Int Request Int Request Vector O0A3y Vector 501491 Figure 9 Compare Mode 2 Port 5 only Semiconductor Group 7 41 SIEMENS Device Specification Interrupt Structure The SAB 80C517A has 17 interrupt vectors with the following vector addresses and request flags Table 5 Interrupt Sources and Vectors Interrupt Request F
32. 5 7 P5 0 61 68 37 44 I O Port 5 is a bidirectional port with internal pull up resistors Port 5 pins that have 1s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs port 5 pins being externally pulled low will source current 11 in the DC characteristics because of the internal pull up resistors This port also serves the alternate function Concurrent Compare and Set Reset Compare The secondary functions are assigned to the port 5 pins as follows CCMO CCM7 P5 0 to P5 7 concurrent compare or Set Reset OWE 69 45 Oscillator Watchdog Enable A high level on this pin enables the oscillator watchdog When left unconnected this pin is pulled high by a weak internal pull up resistor When held at low level the oscillator watchdog function is off Input O Output Semiconductor Group SIEMENS Device Specification Pin Definitions and Functions cont d Symbol Pin Number P LCC 84 P MQFP 100 2 0 Function P6 0 P6 7 70 77 46 50 54 56 I O Port 6 is a bidirectional I O port with internal pull up resistors Port 6 pins that have 1s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs port 6 pins being externally pulled low will source current in the DC characteristics
33. 8 89 Input O Output Semiconductor Group 7 14 SIEMENS Device Specification gt Oscillator ME Watchdog OSC amp XRAM RAM ROM Timing 2k x 8 256 x 8 32k x 8 SAB 83C517A 5 only RESET gt CPU lt ALE Programmable Port D Watchdog Timer 8 bit digit 1 0 i i Port 1 Div Mul Unit lt wi lt gt rcu 1 ibi es Le e 1 n Port 2 8 bit digit 1 0 Port 3 8 bit digit 1 0 gt gt gt 2 apture pare Unit Port 8 Compare Timer Port 6 Interrupt Unit 8 bit digit 1 0 Serial Channel 0 Port 7 Progr Baud Rate Port 7 is digit Generator analog Input Port 8 Serial Channel 1 Port 8 KZ Abit digit analog Input Progr Baud Rate Generator Virer 1 A D Converter Vic 10 bit MCBO1486 Figure 1 Block Diagram Semiconductor Group 7 15 SIEMENS Device Specification Functional Description The SAB 80C517A is based on 8051 architecture It is a fully compatible member of the Siemens SAB 8051 80C51 microcontroller family being an significantly enhanced SAB 800517 The SAB 80C517A is therefore compatible with code written for the SAB 806517 Having an 8 bit CPU with extensive facilities for bit handling and binary BCD arithmetics the SAB 80C517A is optimized f
34. 90 00 low byte S1RELH Serial Channel 1 Relaod Reg BBH XXXX XX11B 9 high byte 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is indeterminate and the location is reserved Semiconductor Group 7 30 SIEMENS Device Specification Table 3 Special Function Registers Functional Blocks cont d Block Symbol Name Address Contents after Reset Timer 0 TCON Timer Control Register 88 00H Timer 1 THO Timer 0 High Byte 8 00H 1 Timer 1 High Byte 8Dy 00H TLO Timer 0 Low Byte 00H TL1 Timer 1 Low Byte 8By 00H TMOD Timer Mode Register 894 00H Watchdog IENO 2 Interrupt Enable Register 0 8 IEN1 2 Interrupt Enable Register 1 7 00 IPO 2 Interrupt Priority Register 0 0 9 00H IP12 Interrupt Priority Register 1 9 XX00 00008 9 WDTREL Watchdog Timer Reload Reg 86H 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is indeterminate and the location is reserved Semiconductor Group 7 31 Device Specification SIEMENS A D Converter In the SAB 80C517A a new high performance high speed 12 channel 10 bit A D Converter is implemented Its successive approxi
35. AB 80C517A does not use the additional On Chip RAM and is compatible with the types without XRAM Semiconductor Group 7 21 SIEMENS Device Specification is hardware protected by an unsymmetric latch An unintentional disabling of XRAM could be dangerous since indeterminate values would be read from external bus To avoid this the is forced to 1 only by reset Additionally during reset an internal capacitor is loaded So after reset state XRAM is disabled Because of the load time of the capacitor XMAPO bit once written to 0 that is discharging capacitor cannot be set to 71 again by software On the other hand any distortion software hang up noise is not able to load this capacitor too That is the stable status is XRAM enabled The only way to disable XRAM after it was enabled is a reset The clear instruction for XMAPO should be integrated in the program initialization routine before XRAM is used In extremely noisy systems the user may have redundant clear instructions The control bit XMAP1 is relevant only if the XRAM is accessed In this case the externa RD and WR signals at P3 6 and P3 7 are not activated during the access if XMAP1 is cleared For debug purposes it might be useful to have these signals and the addresses at Ports 0 2 available This is performed if XMAP1 is set The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register SYSCON and on the s
36. CCAL P5 7 CCM7 Comp mode 1 COMSETL COMSETH P5 0 CCMO Comp mode 2 P5 7 CCM7 Comp mode 2 COMCLRL P5 0 CCMO Comp mode 2 COMCLRH P5 7 CCM7 Comp mode 2 4 0 1 CMOH CMOL 4 7 7 Comp mode 1 CM7H CM7L Compare CMOH CMOL P4 0 CMO Comp mode 0 timer with shadow latches Comp mode 0 CM7H CM7L P4 7 CM7 with shadow latches Semiconductor Group 7 35 SIEMENS Device Specification 16 Reload CTREL Compare Timer U Max Clock fosc 2 Timer ock fosc 12 16 Bit Rel Capt Comp CRC Figure 5 Capt Com 4 Capt Com 3 CC3 RIN Capt Com 2 2 Capt Com 1 CC1 MCBO1 489 Block Diagram of the Compare Capture Unit Semiconductor Group 7 36 SIEMENS Device Specification Compare In compare mode the 16 bit values stored in the dedicated compare registers are compared to the contents of the timer 2 register or the compare timer register If the count value in the timer registers matches one of the stored value an appropriate output signal is generated at the corresponding pin s and an interrupt is requested Three compare modes are provided Mode 0 Upon match the output signal changes from low to high It returns to low level at timer overflow Mode 1 The transition of the outpu
37. D5 D orH MD5 M orH First Read MDO QuoL MDO QuoL MDO PrL MD1 Quo MD1 QuoH MD1 MD2 Quo MD3 QuoH MD4 RemL MD2 MD4 RemL Last Read MD5 RemH MD5 RemH MD3 PrH Table 7 Shift Operation with the MDU Operation Normalize Shift Left Shift Right First Write MDO least significant byte MD1 MD2 MD3 most significant byte Last Write ARCON start of conversion First Read MDO least significant byte MD1 MD2 Last Read MD3 most significant byte Abbreviations Dividend 1st operand of division Dior Divisor 2nd operand of division Multiplicand 1st operand of multiplication Multiplicator 2nd operand of multiplication Pr Product result of multiplication Rem Remainder Quo Quotient result of division n means that this byte is the least significant of the 16 bit or 32 bit operand H means that this byte is the most significant of the 16 bit or 32 bit operand Ports The SAB 80C517A has seven 8 bit I O ports and two input ports 8 bit and 4 bit wide Port 0 is an open drain bidirectional port while ports 1 to 6 are quasi bidirectional I O ports Semiconductor Group 7 47 SIEMENS Device Specification with internal pull up resistors That means when configured as inputs ports 1 to 6 will be pulled high and will source current when externally pulled low Port 0 will float when configured as input Port 0 and port 2 can be used to expand the program and data memory externally Du
38. If HWPD goes to high level inactive state an automatic start up procedure is performed First the pins leave their floating condition and enter their default reset state as they had immediately before going to float state Both oscillators are enabled only if OWE high The oscillator watchdog s RC oscillator starts up very fast typ less than 2 microssepruitg Because the oscillator watchdog is active it detects a failure condition if the on chip oscillator hasn t yet started Hence the watchdog keeps the part in reset and supplies the internal clock from the RC oscillator Finally when the on chip oscillator has started the oscillator watchdog releases the part from reset with oscillator watchdog status flag not set When automatic start of the watchdog was enabled PE SWD connected to the Watchdog Timer will start too with its default reload value for time out period The Reset pin overrides the Hardware Power Down function i e if reset gets active during Hardware Power Down it is terminated and the device performs the normal reset function Thus pin Reset has to be inactive during Hardware Power Down Mode Semiconductor Group 7 51 SIEMENS Device Specification Table 8 Status of all pins during Idle Mode Power Down Mode and Hardware Power Down Mode Pins Idle Mode Power Down Mode Hardware Power Down Last instruction executed from Last instruction executed from
39. In extremely noisy systems the user may have redundant clear instructions The control bit XMAP1 is relevant only if the XRAM is accessed In this case the external RD and WR signals at P3 6 and P3 7 are not activated during the access if XMAP1 is cleared For debug purposes it might be useful to have these signals available This is performed if 1 is set 3 4 3 Behaviour of PortO and Port2 The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register SYSCON and on the state of pin EA The table 3 3 lists the various operating conditions It shows the following characteristics a Use of and P2 pins during the MOVX access Bus The pins work as external address data bus If internal XRAM is accessed the data read from the XRAM can not be seen on the bus 1 0 The pins work as Input Output lines under control of their latch b Activation of the RD and WR pin during the access C Use of internal or external XDATA memory The shaded areas describe the standard operation as each 80C51 device without on chip XRAM behaves Semiconductor Group 3 16 Memory Organization SIEMENS XAOW ud 0 Jo 5 5 Augy 608 01 pesn 1 pesn 1 2 pesn s 2 pesn s WWHX 9 AJOWSW X9 9 pesn s 2 pesn s WWHX 9
40. M Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM Note reset occurs during a write operation to XRAM the effect on XRAM depends on the cycle which the reset is detected at MOVX is a 2 cycle instruction Reset detection at cycle 1 The new value will not be written to XRAM The old value is not affected Reset detection at cycle 2 The old value in XRAM is overwritten by the new value Accesses to XRAM using the DPTR There are a Read and a Write instruction from and to XRAM which use one of the 16 bit DPTR for indirect addressing The instructions are MOVXA DPTR Read MOVX DPTR A Write Normally the use of these instructions would use a physically external memory However in the SAB 80C517A the is accessed if it is enabled and if the DPTR points to the XRAM address space 2 F800 Accesses to XRAM using the Registers RO R1 The 8051 architecture provides also instructions for accesses to external data memory range which use only an 8 bit address indirect addressing with registers RO or R1 The instructions are MOVXA Qhi Read MOVX Ri A Write In application systems either a real 8 bit bus with 8 bit address is used or Port 2 serves as page register which selects pages of 256 byte However the distinction whether Port 2 is used as general purpose or as page address is made by the external system
41. MCLRH 0 4 00H SETMSK 0 5 00H CLRMSK 0A6H 00H CTCON 1 0X00 00008 CC4EN 0 9 00H The compare registers COMSET and COMCLR have their dedicated interrupt vectors The corresponding request flags are ICS for register COMSET and ICR for register COMCLR The flags are set by a match in registers COMSET and COMCLR when enabled As long as the match condition is valid the request flags can t be reset neither by hardware nor software The request flags are located in SFR CTCON Special Function Register CTCON Bit No MSB LSB 7 6 5 4 3 2 1 0 T2PS1 ICR ISC CLK2 CLK1 CLKO Bit Function CLKO Same function as SAB 80C517 CLK1 CLK2 CTF ICS Interrupt request flag for Compare register COMSET ICS is set when a compare match occured Cleared when interrupt is processed ICR Interrupt request flag for Compare register COMRES ICR is set when a compare match occured Cleared when interrupt is processed T2PS1 Prescaler select bit for Timer 2 See table 5 5 The default value of CTCON after reset is 00008 Semiconductor Group 5 12 SIEMENS On Chip Peripheral Components Extended Prescaler for Timer 2 The prescaler for Timer 2 has an extended range This prescaler divides the input clock for Timer 2 when it is operated in timer mode In addition to the 2 option there are now scale ratings of 4 and 8 available The rate is sele
42. MQFP 100 2 added 4 Pin differences updated 6 14 Pin numbers for P MQFP 100 2 package added several Correction of P MRFP 100 into P MQFP 100 2 2 Ordering information for 40 to 110 versions 25 26 30 Correction of register names SORELL SCON ADCON ICRON and SBUF 33 Figure 4 corrected 39 Figure 8 corrected 57 PE SWD function description completed 60 Correct ordering numbers 62 Test condition for Voy corrected 65 corrected fazp Values corrected several Minimum clock frequence is now 3 5 MHz 66 data setup before WR corrected and added 68 corrected Page Subjects changes since last version 08 93 25 Corrected SFR name SORELL 51 Below Termination of HWPD Mode 4th paragraph with ident corrected 65 Description of 1 corrected 67 Program Memory Read Cycle fpxay added 74 Oscillator circuit drawings MQFP 100 2 pin numbers added Page Subjects changes since last revision 01 94 Minor changes on several pages 47 Table 6 corrected SIEMENS 80C517A 83C517A 5 Contents Page 1 Introduction 355 tees es 1 1 2 Fundamental Structure 2 1 3 Memory Organization 3 1 3 1 Program Memory ROM Protection 3 2 3 2 EE aac E 3 3 3 3 Special Function Registers 3 4 3 4 Archite
43. N Like in concurrent compare mode associated with CC4 the number of port pins at P5 which serve the compare output function can be selected by bits COCONO COCON2 in SFR CC4EN If a set and reset request occurs at the same time identical values in COMSET and COMCLR the set operation takes precedence It is also possible to use only the interrupts which are generated by matches in COMSET and COMCLR without affecting P5 software compare For this interrupt only mode it is not necessary that the compare function at CCA is selected Semiconductor Group 5 8 SIEMENS On Chip Peripheral Components ilis COMSET COMCLR SETMSK e o S Bit 0 R Q 5 0 Number of Pins e e o S for this Bit 1 R Q P5 1 function is selectable e o from Bit 2 1 to 8 ICS ICR by Bit S COCONO 2 4 u ECS u ECS 5 IEN2 4 3 IEN2 5 CLRMSK v Int Int Request Request Vector Vector 00A3 OOAB y 02249 Figure 5 3 2 5 Semiconductor Group 5 9 SIEMENS On Chip Peripheral Components Special Function Register CC4EN Bit No MSB LSB 7 6 5 4 3 2 1 0 9 2 1 COCAL4 COMO CC4EN Bit Function COCON2 Selects number of compare outputs at P5 for compare mod
44. P3 0 receiver data input asynchronous or data input output synchronous of serial interface Tx DO P3 1 transmitter data output asynchronous or clock output synchronous of serial interface 0 INTO P3 2 interrupt 0 input timer 0 gate control INT1 P3 3 interrupt 1 input timer 1 gate control TO P3 4 counter 0 input P3 5 counter 1 input WR P3 6 the write control signal latches the data byte from port 0 into the external data memory RD P3 7 the read control signal enables the external data memory to port 0 Input Output Semiconductor Group SIEMENS Device Specification Pin Definitions and Functions cont d Symbol Pin Number P LCC 84 100 2 0 Function P1 7 P1 0 29 36 98 100 1 6 9 Port 1 is a bidirectional I O port with internal pull up resistors Port 1 pins that have 1 5 written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs port 1 pins being externally pulled low will source current 11 in the DC characteristics because of the internal pull up resistors It is used for the low order address byte during program verification It also contains the interrupt timer clock capture and compare pins that are used by various options The output latch must be programmed to a one 1 for that function to operate except when
45. ROM Verification Mode Restrictions see Characteristics no ROM Verification Mode 1 standard 8051 Verification Mode ROM Verification Mode 2 yes ROM Verification Mode 2 standard 8051 Verification Mode is disabled externally applied MOVC accessing to internal ROM is disabled Semiconductor Group 3 2 SIEMENS Memory Organization 3 2 Data Memory The data memory space consists of an internal and an external memory space The SAB 80C517A contains another 2 kByte of On Chip RAM above the 256 Bytes internal RAM of the base type SAB 80 517 This RAM is called XRAM in this document External Data Memory Up to 64 Kbyte external data memory can be addressed by instructions that use 8 bit or 16 bit indirect addressing For 8 bit addressing MOVX instructions in combination with registers RO and 1 can be used A 16 bit external memory addressing is supported by eight 16 bit datapointers Registers XPAGE and SYSCON are controlling whether data fetches at addresses F800 to FFFFy are done from internal XRAM or from external data memory Internal Data Memory The internal data memory is divided into four physically distinct blocks the lower 128 bytes of RAM including four banks containing eight registers each the upper 128 byte of RAM the 128 byte special function register area 2 8 area which is accessed like external RAM MOVX instructions called XRAM implemented on chip at the add
46. SIEMENS Microcomputer Components SAB 80 517 83 517 5 8 Bit CM OS Single Chip M icrocontroller Addendum to User s M anual SAB 80C517 80C537 05 94 Edition 05 94 This edition was realized using the software system FrameMaker Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 Munchen Siemens AG 1994 All Rights Reserved Attention please As far as patents or other rights of third par ties are concerned liability is only assumed for components not for applications pro cesses and circuits implemented within com ponents or assemblies The information describes the type of compo nent and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list Due to technical requirements components may contain dangerous substances For in formation on the types in question please contact your nearest Siemens Office Semi conductor Group Siemens AG is an approved CECC manufac turer Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the costs of transport For packing mater
47. al Interrupt 5 Timer 2 Interrupt Match in COMCLR External Interrupt 6 Table 6 2 Priority within Level Interrupt Source Priority High gt Low IEO TI IADC High TFO 2 IE1 ICMPO 7 1 IEX4 RIO TIO ICS IEX5 TF2 EXF2 ICR IEX6 Low Semiconductor Group Si 5 Device Specification High Performance SAB 80 517 83 517 5 8 Bit CMOS Single Chip Microcontroller Preliminary SAB 83C517A 5 Microcontroller with factory mask programmable ROM SAB 80 517 Microcontroller for external ROM e SAB 80C517A 83C517A 5 e Fight data pointers for external memory up to 18 MHz operation addressing e 32K x 8 ROM SAB 83C517A 5 only Seventeen interrupt vectors four priority ROM Protection available levels selectable 256 x 8 on chip RAM e Genuine 10 bit A D converter with e 2 x8 on chip RAM XRAM 12 multiplexed inputs e Superset of SAB 80C51 architecture e Two full duplex serial interfaces with 1 us instruction cycle time at 12 MHz programmable Baudrate Generators 666 ns instruction cycle time at 18 MHz Fully upward compatible with SAB 80C515 256 directly addressable bits SAB 80C517 SAB 80C515A Boolean processor e Extended power saving mode 64 Kbyte external data and e Fast Power On Reset program memory addressing e Nine ports 56 I O lines 12 input lines e Four 16 bit timer counters e Three temperature ranges available e Powerful 16 bit compar
48. and the priority within level table 6 2 The principle of the priority level selection is identical to the SAB 80C517 i e a pair or triple can be programmed to one of four priority levels Special Function Register IEN2 MSB LSB Bit No 7 6 5 4 3 2 1 0 09 ECR ECS ECT ECMP ES1 IEN2 Bit Function ES1 Enable serial interrupt of interface 1 Enables or disables the interrupt of serial interface 1 If ES1 0 the interrupt is disabled ECMP Enables interrupt on compare match in compare registers CMO CM7 If ECMP the interrupt is disabled ECT Enable compare timer interrupt Enables or disables the interrupt at compare timer overflow If ECT 0 the interrupt is disabled ECS Enables interrupt on compare match in compare register COMSET If ECS 0 the interrupt is disabled ECR Enabled interrupt on compare match in compare register 1 If ECR 0 the interrupt is disabled The reset value of IEN2 is XX00 OOXOB Semiconductor Group 6 5 SIEMENS Interrupt System Table 6 1 Pairs and triplets of interrupt sources External Interrupt 0 Serial Channel 1 Interrupt A D Converter Interrupt Timer 0 Interrupt External Interrupt 2 External Interrupt 1 Match in CMO CM7 External Interrupt 3 Timer 1 Interrupt Compare Timer Overflow External Interrupt 4 Serial Channel 0 Interrupt Match in COMSET Extern
49. at the value is indeterminate and the location is reserved Semiconductor Group 7 29 SIEMENS Device Specification Table 3 Special Function Registers Functional Blocks cont d Block Symbol Name Address Contents after Reset CLRMSK _ Mask Register concerning 00H Capture COMCLR Unit CTCON Com Timer Control Reg 1 0X00 0000B CCU CTRELH Timer Rel Reg High Byte _ 00H cont d CTRELL Timer Rel Reg Low Byte ODE 00H TH2 Timer 2 High Byte 00H TL2 Timer 2 Low Byte 0CCH 00H T2CON Timer 2 Control Register 0 00H Ports PO Port 0 804 1 1 90 2 Port 2 7 7 4 Port 4 8 5 5 OFFj P6 Port 6 P7 Port 7 Analog Digital Input ODBy P8 Port 8 Analog Digital Input 4 bit ODD Pow Sav PCON Power Control Register 874 00H Modes Serial ADCON 92 A D Converter Control Reg OD8y 00 Channels 2 Power Control Register 87 00H SOBUF Serial Channel 0 Buffer Reg 99H OXXy 3 SOCON Serial Channel 0 Control Reg 98 00 SORELL Serial Channel 0 Reload Reg 2 low byte SORELH Serial Channel 0 Reload Reg XXXX XX11B 3 high byte S1BUF Serial Channel 1 Buffer Reg 9 OXXy 9 S1CON Serial Channel 1 Control Reg 9By 0X00 0008 S1RELL Serial Channel 1 Reload Reg
50. cted by the control bits T2PS T2CON 7 and T2PS1 CTCON 7 Table 5 5 lists all available options This prescaler must not be used when Timer 2 is operated in counter mode Table 5 5 Timer 2 Prescaler T2PS1 CTCON 7 T2PS T2CON 7 Prescaler Ratio 0 0 1 0 1 2 1 0 4 1 1 8 Semiconductor Group 5 13 SIEMENS On Chip Peripheral Components 5 4 New Baud Rate Generators for Serial Channel 0 and Serial Channel 1 5 4 1 Serial Channel 0 Baud Rate Generator The Serial Channel 0 has a new baud rate generator which provides greater flexibility and better resolution It substitutes the 80C517 s baud rate generator at Serial Channel 0 which provides only 4 8 kBaud or 9 6 kBaud at 12 MHz crystal frequency Since the new generator offers greater flexibility it is often possible to use it instead of Timer1 which is then free for other tasks Figure 5 4 shows a block diagram of the new baud rate generator for Serial Channel 0 It consists of a free running 10 bit timer with fosc 2 input frequency On overflow of this timer there is an automatic reload from the registers SORELL address and SORELH address The lower 8 bits of the timer are reloaded from SORELL while the upper two bits are reloaded from bit 0 and 1 of register SORELH The baud rate timer is reloaded by writing to SORELL SRELH 1 0 Baud Rate Clock Phase 2 CLK fsc 2 gt 10 Bit Timer Overflow MCTO2
51. cture for the XRAM 3 9 3 4 1 Accesses to XRAM 3 9 3 4 2 Control of XRAM in the SAB 80C517A 3 15 3 4 3 Behaviour of Ponto and 2 3 16 4 System Reset ita ote RET 4 1 4 1 Additional Hardware Power Down Mode in the SAB 80C517A 4 1 4 2 Hardware Power Down Reset Timing 4 4 4 3 Fast internal Reset after Power On 4 8 5 On Chip Peripheral Components 5 1 5 1 Digital I O Port Circuitry 5 1 5 2 TO Dib A D COBVErTer cd A 5 3 5 3 Additional Compare Mode for the Concurrent Compare Unit 5 8 5 4 New Baud Rate Generators for Serial Channel 0 and Serial Channel 1 5 14 5 4 1 Serial Channel 0 Baud Rate Generator 5 14 5 4 2 Serial Channel 1 Baud Rate Generator 5 17 5 5 Modified Oscillator Watchdog Unit 5 19 6 Interrupt Syste ERR 6 1 6 1 Additional Interrupt for Compare Registers to CM7 6 1 6 2 Interrupt Structure c ed ara doeet 6 4 6 3 Priority Level Structure 6 5 7 Device Specif
52. des except during an external data memory access 51 24 xternal Access Enable When held at high level instructions are fetched from the internal ROM SAB 83C517A 5 only when the PC is less than 8000H When held at low level the SAB 80C517A fetches all instructions from ex ternal program memory For the SAB 80C517A this pin must be tied low 0 0 7 52 59 26 27 30 35 I O Port 0 is 8 bit open drain bidirectional port Port 0 pins that have 1 s written to them float and in that state can be used as high impe dance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory In this application it uses strong internal pull up resistors when issuing 1 5 Port 0 also out puts the code bytes during program verification in the SAB 83C517A if ROM Protection was not enabled External pull up resistors are required during program verification 1 Input O Output Semiconductor Group SIEMENS Device Specification Pin Definitions and Functions cont d Symbol Pin Number P LCC 84 P MQFP 100 2 Function HWPD 60 36 Hardware Power Down A low level on this pin for the duration of one machine cycle while the oscillator is running resets the SAB 80 517 low level for a longer period will force the part to Power Down Mode with the pins floating see table 7 P
53. ding port 1 pins CCO to CC3 Mode 1 Write operation into the low order byte of the dedicated capture register causes the timer 2 contents to be latched into this register Semiconductor Group 7 37 SIEMENS Device Specification Reload of Timer 2 A 16 bit reload can be performed with the 16 bit CRC register which is a concatenation of the 8 bit registers CRCL and CRCH There are two modes from which to select Mode 0 Reload is caused by timer overflow auto reload Mode 1 Reload is caused in response to a negative transition at pin T2EX P1 5 which can also request an interrupt Timer Counters 0 and 1 These timer counters are fully compatible with timer counter 0 or 1 of the SAB 8051 and can operate in four modes Mode 0 8 bit timer counter with 32 1 prescaler Mode 1 16 bit timer counter Mode 2 8 bit timer counter with 8 bit auto reload Mode 3 Timer counter 0 is configured as one 8 bit timer timer counter 1 in this mode holds its count External inputs INTO and INT1 can be programmed to function as a gate for timer counters 0 and 1 to facilitate pulse width measurements Semiconductor Group 7 38 SIEMENS Device Specification OETH 0 8 rano rat 120 T2CON E Counter function input at P1 7 T2 Prescaler Timer 2 input selection Timer 2 input clock TL2 TH2 9 P1 5 T2EX EXF
54. e CCU contains one 16 bit timer counter timer2 with 2 bit prescaler reload capability and a max clock frequency of fosc 12 1 MHz with a 12 MHz crystal one 16 bit timer compare timer with 8 bit prescaler reload capability and a max clock frequency of fosc o 6 MHz with a 12 MHz crystal fifteen 16 bit compare registers five of which can be used as 16 bit capture registers upto 21 output lines controlled by the CCU nine interrupts which can be generated by CCU events Figure 5 shows a block diagram of the CCU Eight compare registers CMO to CM7 can individually be assigned to either timer 2 or the compare timer Diagrams of the two timers are shown in figures 6 and 7 The four compare capture registers the compare reload capture register and the comset comclr register are always connected to timer 2 Depending on the register type and the assigned timer three different compare modes can be selected Table 3 illustrates possible combinations and the corresponding output lines Semiconductor Group 7 34 SIEMENS Device Specification Table 4 CCU Compare Configuration Assigned Timer Compare Register Compare Output Modes Timer 2 CRCH CRCL P1 0 INT3 CCO Comp mode 0 1 Reload CC1H CC1L P1 1 INT4 CC1 Comp mode 0 1 CC2H CC2L P1 2 INT5 CC2 Comp mode 0 1 CC3H CC3L P1 3 INT6 CC3 Comp mode 0 1 CC4H CC4L P1 4 INT2 CC4 Comp mode 0 1 CC4H CC4L P5 0 CCMO Comp mode 1 CCAH
55. e D5y 00H CMH2 Compare Reg 2 High Byte D7H 00H CMH3 Compare Reg 3 High Byte E3H 00H CMH4 Compare Reg 4 High Byte E5H 00H CMH5 Compare Reg 5 High Byte E7H 00H CMH6 Compare Reg 6 High Byte F3y 00H CMH7 Compare Reg 7 High Byte F5H 00H CMLO Compare Register 0 Low Byte D2y 00H CML1 Compare Register 1 Low Byte D44 00H CML2 Compare Register 2 Low Byte D6H CML3 Compare Register 3 Low Byte E2y 00H CML4 Compare Register 4 Low Byte E4y 00H CML5 Compare Register 5 Low Byte 00H CML6 Compare Register 6 Low Byte 2 00H CML7 Compare Register 7 Low Byte 00H CMSEL Compare Input Select F7y 00H CRCH Com Rel Capt Reg High Byte CBH 00H CRCL Com Rel Capt Reg Low Byte CAH 00H COMSETL Compare register Low Byte Aly 00H COMSETH Compare register High Byte A2y 00H COMCLRL Compare register Low Byte 00H COMCLRH Compare register High Byte A4H 00H SETMSK mask register concerning COMSET Ady 00H CLRMSK mask register concerning COMCLR Com Timer Control Reg 1 0X00 0000p 3 Com Timer Rel Reg High Byte DFH 00H CTRELL Com Timer Rel Reg Low Byte DEH 00H TH2 Timer 2 High Byte CDH 00H TL2 Timer 2 Low Byte CCH 00H T2CON Timer 2 Control Register 00H 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value i
56. e capture unit 0 to 70 T1 CCU with up to 21 high speed or PWM 40 to 85 output channels and 5 capture inputs 40 to 110 T4 e Versatile fail safe provisions e Plastic packages P LCC 84 e Fast 32 bit division 16 bit multiplication P MQFP 100 2 32 bit normalize and shift by peripheral MUL DIV unit MDU The SAB 80C517A 83C517A 5 is a high end member of the Siemens SAB 8051 family of microcontrollers It is designed in Siemens ACMOS technology and based on SAB 8051 architecture ACMOS is a technology which combines high speed and density characteristics with low power consumption or dissipation While maintaining all the SAB 80C517 features and operating characteristics the SAB 80 517 is expanded in its fail safe characteristics and timer capabilities The SAB 80C517A is identical with the SAB 83C517A 5 except that it lacks the on chip program memory The SAB 80C517A 83C517A 5 is supplied in a 84 pin plastic leaded chip carrier package P LCC 84 and in a 100 pin plastic quad flat package P MQFP 100 2 7 1 05 94 SIEMENS Device Specification improved functionality Ordering Information YA om V s XRAM 80C51 mm ROM 8k x 8 ROM Protection available Analog Analog 1 0 1 0 1 0 Digital _ Digital Input 24k x 8 ROM Protection available MCAO1481 Type Ordering Package Descripti
57. ed slow down mode is measured with all output pins disconnected and with all peripher als disabled XTAL2 driven with ICLCH CHCL 5 ns ViL Vss 0 5 V Vin 0 5 V XTAL1 N C RESET HWPD Port Port8 EA PE SWD all other pins are disconnected Icc at other frequencies is given by active mode 1 50 fosc 10 idle mode cc 1 17 f osc 10 where fosc is the oscillator frequency in MHz values are given in mA and measured at Voc 5 V Semiconductor Group 7 63 SIEMENS Device Specification A D Converter Characteristics 5 10 15 0 V VAREF 5 VAGND Vss 0 2 V O to 70 for the SAB 80 517 83 517 5 T a 40 to 85 for the SAB 80051 7A T3 83C517A 5 T3 4010 110 C for the SAB 80C517A T4 83C517A 5 T4 Parameter Symbol Limit values Unit Test condition min typ max Analog input capacitance 25 70 pF Sample time Ts 4100 lus 2 inc load time Conversion time 14 tg lus 3 inc sample time Total unadjusted error TUE 2 LSB Varner VaGND Vss Varer Supply current IREF 20 x ADCL ADCL toy 8 2 tcv fane fosc 8 2 This parameter specifies the time during the input capacitance C can be charged discharged by the external source It must be guaranteed t
58. ere is no way of disabling the ROM Protection Effect access to internal ROM done by an externally fetched MOVC instruction is disabled Nevertheless an access from internal ROM to external ROM is possible To verify the read protected ROM Code a special ROM Verify Mode is implemented This mode also can be used to verify unprotected internal ROM ROM Protection ROM Verification Mode Restrictions see AC Characteristics no ROM Verification Mode 1 standard 8051 Verification Mode ROM Verification Mode 2 yes ROM Verification Mode 2 standard 8051 Verification Mode is disabled externally applied MOVC accessing internal ROM is disabled Semiconductor Group 7 17 SIEMENS Device Specification Data Memory Code Space The data memory space consists of an internal and an external memory space The SAB 80C517A contains another 2 Kbyte RAM above the 256 bytes internal RAM of the base type SAB 80C517 This RAM is called XRAM in this document External Data Memory Up to 64 Kbyte external data memory can be addressed by instructions that use 8 bit or 16 bit indirect addressing For 8 bit addressing instructions in combination with registers RO and R1 can be used A 16 bit external memory addressing is supported by eight 16 bit datapointers Registers XPAGE and SYSCON are controlling whether data fetches at addresses F800 to FFFFy are done from internal XRAM or f
59. ernal pullup This is done to provide system protection on default The logic level applied to pin PE SWD can be changed during program execution to allow or to block the use of the power saving modes without any effect on the on chip watchdog circuitry Semiconductor Group 7 49 SIEMENS Device Specification Requirements for Hardware Power Down Mode There is no dedicated pin to enable the Hardware Power Down Mode Nevertheless for a correct function of the Hardware Power Down Mode the oscillator watchdog unit including its internal RC oscillator is needed Therefore this unit must be enabled by pin OWE OWE high However the control pin PE SWD has no control function in this mode It enables and disables only the use of software controlled power saving modes Software controlled power saving modes All of these modes are entered by software Special function register PCON power control register address is 87 4 is used to select one of these modes Slow Down Mode During slow down operation all signal frequencies that are derived from the oscillator clock are divided by eight also the clockout signal and the watchdog timer count The slow down mode is enabled by setting bit SD The controller actually enters the slow down mode after a short synchronisation period max 2 machine cycles The slow down mode is disabled by clearing bit SD Idle Mode During idle mode all peripherals of the SAB 80 517 except for the watc
60. es 1 and 2 see table 2 2 COCONO COCAH4 Compare capture mode for register CC4 and compare modes 1 and 2 at P5 COCAL4 Compare capture at CC4 disabled Capture on falling rising edge at pin P1 4 INT2 CC4 0 0 Compare enabled at CC4 0 1 Capture on write operation into register CCL4 1 0 1 1 COCOEN 1 Selection of compare modes 1 and 2 at P5 valid only in combination with COCOENO certain configurations in COCAL4 see table 2 3 Setting of bit COCOENO automatically sets COMO COMO Compare Mode for register CC4 COMO 0 selects compare mode 0 COMO 1 selects compare mode 1 Setting of bit COCOENO automatically sets COMO The reset value of SFR is COCON2 COCON1 COCONO Function 0 0 0 One additional output of CC4 at P5 0 0 0 1 Additional outputs of CC4 at P5 0 to P5 1 0 1 0 Additional outputs of CC4 at P5 0 to P5 2 0 1 1 Additional outputs of CC4 at P5 0 to P5 3 1 0 0 Additional outputs of CC4 at P5 0 to P5 4 1 0 1 Additional outputs of 4 at P5 0 to P5 5 1 1 0 Additional outputs of 4 at P5 0 to P5 6 1 1 1 Additional outputs of CC4 at P5 0 to P5 7 Semiconductor Group 5 10 SIEMENS On Chip Peripheral Components Table 5 3 Configurations for Concurrent Compare Mode and Compare Mode 2 at P5 COCAH4 COCAL4 COCOEN1 COCOENO Function of CC4 Function of Compare Modes at P5 0 0 0 0 Compare Capture Disabled disabled 0 0 1 0 Compare Capture Co
61. eset 1 OFFy DOH PSW 1 BiH SYSCON XXXX XX01B 1 IRCON1 2 reserved XX D2y CMLO 00 reserved XXH D3y CMHO 00H reserved 3 00H reserved XXH D54 CMH1 00H reserved XXH CML2 00 B7 reserved XXH D74 CMH2 IEN1 1 00H ADCONO 00 B94 00008 ADDATH 00H SORELH XXXX XX11B ADDATL S1RELH XXXX XX11B P7 XX BCy reserved XXH DCH ADCON1 XXXX 0000B BDy reserved XXH DDy P8 reserved XXH CTRELL reserved XXH DFy CTRELH 00 IRCONO 1 00H E0H 7 00H 1 1 0X00 000B C24 CCL1 00H 2 CML3 00H CCH1 OOH CCL2 00H E44 CML4 00 C5y CCH2 00H E5y CMH4 004 CCL3 CML5 00H C7u 00 E74 CMH5 00H T2CON 1 00H E8H P4 1 OFFy CC4EN 00H MDO XXH CAH CRCL 00H EAH MD1 XXH CRCH 00H EBH MD2 XXH CCH TL2 00H ECH MD3 XXH CDy TH2 00H EDH MD4 XXH CEH CCL4 00H EEH MD5 XXH 4 00H EFy ARCON OXXX XXXXB 9 Bit addressable special function registers 2 X means that the value is indeterminate and the location is reserved 3 SFRs not user accessable Semiconductor Group 7 26 SIEMENS Device Specification Table 2 Special Function Register cont d Address Register
62. g modes Slow Down Mode Idle Mode Software Power Down Mode The function of the new Hardware Power Down Mode is as follows The pin HWPD controls this mode If it is on logic high level inactive the part is running in the normal operating modes If pin HWPD gets active low level the part enters the Hardware Power Down Mode as mentioned above this is independent of the state of pin PE SWD HWPD is sampled once per machine cycle If it is found active the device starts a complete internal reset sequence This takes two machine cycles all pins have their default reset states during this time This reset has exactly the same effects as a hardware reset i e especially the watchdog timer is stopped and its status flag WDTS is cleared In this phase the power consumption is not yet reduced After completion of the internal reset both oscillators of the chip are disabled the on chip oscillator as well as the oscillator watchdog s RC oscillator At the same time the port pins and several control lines enter a floating state as shown in table 4 1 In this state the power consumption is reduced to the power down current IPD Also the supply voltage can be reduced Table 4 1 also lists the voltages which may be applied at the pins during Hardware Power Down Mode without affecting the low power consumption Semiconductor Group 4 1 SIEMENS System Reset Table 4 1 Status of all Pins During Hardware Power Down Mode Pins Status Vol
63. gs in IRCON 1 is set Figure 6 1 shows a functional block diagram of the new structure concerning the interrupts The further functions of this compare unit keep full compatibility to the SAB 80C517 Semiconductor Group 6 1 SIEMENS Interrupt System Timer II v Output Comparator 7 Eirci gt P4 7 v A Comparator 6 Comparator 5 Comparator 4 e v Comparator 3 e v Comparator 2 A e Y rd 7 Comparator 1 CM6 Comparator 0 gt P4 0 CM 5 ICMP ICMP ICMP ICMP ICMP ICMP ICMP ICMP IRCON1 7 6 5 h 3 2 1 0 Addr 0D1H ECMP IEN2 2 Interrupt vector to location 0093H MCA02256 Figure 6 1 Interrupts of Compare Registers 7 Assigned to Timer Semiconductor Group 6 2 SIEMENS Interrupt System Special Function Register IRCON1 MSB LSB Bit No 7 6 5 4 3 2 1 0 1 ICMP7 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 ICMP1 ICMPO IRCON1 Bit Function ICMPx Compare x interrupt request flag Set by hardware when a compare match in compare mode 1 with compare regis
64. hat the input capacitance is fully loaded within this time 4 is 2 us at the fogc 16 MHz After the end of the sample time Ts changes of the analog input voltage have no effect on the conversion result 3 This parameter includes the sample time 14TCY is 7 us at fosc 16 MHz The differencial impedance rp of the analog reference source must be less than 1 KO at reference supply voltage Semiconductor Group 7 64 SIEMENS Device Specification AC Characteristics 5 V 10 15 0 V 01070 for the SAB 80C517A 83C517A 5 40 to 85 C for the SAB 80C517A T3 83C517A 5 T3 T a 40 10110 C for the SAB 80C517A T4 83C517A 5 T4 C port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Parameter Symbol Limit values Unit 18 MHz clock Variable clock 1 t 3 5 MHz to 18 MHz min max min max Program Memory Characteristics ALE pulse width fLHLL 71 2tc cL 740 ns Address setup to ALE tAVLL 26 30 ns Address hold after ALE t j Ax 26 30 ns ALE to valid instruction 122 100 ins ALE to PSEN 31 25 PSEN pulse width 132 35 l PSEN to valid instruction jy 92 cL 75 Input instruction hold 0 0 ns after PSEN Input instruction float
65. hdog timer are still supplied by the oscillator clock Thus the user has to take care which peripheral should continue to run and which has to be stopped during Idle The procedure to enter the idle mode is similar to the one entering the power down mode The two bits IDLE and IDLS must be set by two consecutive instructions to minimize the chance of unintentional activating of the idle mode There are two ways to terminate the idle mode The idle mode can be terminated by activating any enabled interrupt This interrupt will be serviced and the instruction to be executed following the RETI instruction will be the one following the instruction that set the bit IDLS The other way to terminate the idle mode is a hardware reset Since the oscillator is still running the hardware reset must be held active only for two machine cycles for a complete reset Normally the port pins hold the logical state they had at the time idle mode was activated If some pins are programmed to serve their alternate functions they still continue to output during idle mode if the assigned function is on The control signals ALE and hold at logic high levels PSEN see table 8 Semiconductor Group 7 50 SIEMENS Device Specification Power Down Mode The power down mode is entered by two consecutive instructions directly following each other The first instruction has to set the flag PDE power down enable and must not set PDS power down set The f
66. he eight compare channels eight request flags are available New baud rate generator for Serial Channel 0 Expanded baud rate range for Serial Channel 1 Hardware controlled Power Down Mode Improved functionality of the Oscillator Watchdog High speed operation of the device up to 18 MHz crystal frequency Figure 2 1 shows a block diagram of the SAB 80C517A Semiconductor Group 2 1 SIEMENS Fundamental Structure Oscillator OSC 4 ROM Timing 2k x 8 256 x 8 32k x 8 SAB 83C517A 5 only 80 CPU d PSEN Programmable Port 0 RE eb eu nem ol 1 5 gt it digit 1 0 im PS 1 lt gt it digit 1 0 or hit diat Timer 2 8 bit digit 1 0 Port 4 ug B bit digit 1 0 Compare Unit Compare Timer tuu 1 0 Interrupt Unit Port gt eb us Serial Channel 0 Progr Baud Rate Generator Port 7 8 bit digit analog Input Port 8 4 bit digit analog Input Serial Channel 1 Generator A D Converter 10 bit lt Progr Baud Rate 1 486 Figure 2 1 Block Diagram of the SAB 80C517A Semiconductor Group 2 2 SIEMENS Memory Organization 3 Memory Organization According to the SAB 8051 architectu
67. he frequency of the auxiliary RC oscillator in the watchdog unit the internal clock is supplied by the RC oscillator and the device is brought into reset if the failure condition disappears i e the on chip oscillator has a higher frequency than the RC oscillator the part executes a final reset phase of appr 0 5 ms in order to allow the oscillatior to stabilize then the oscillator watchdog reset is released and the part starts program execution again Restart from the Hardware Power Down Mode If the Hardware Power Down Mode is terminated the oscillator watchdog has to control the correct start up of the on chip oscillator and to restart the program The oscillator watchdog function is only part of the complete Hardware Power Down sequence however the watchdog works identically to the monitoring function Fast internal reset after power on In this function the oscillator watchdog unit provides a clock supply for the reset before the on chip oscillator has started In this case the oscillator watchdog unit also works identically to the monitoring function If the oscillator watchdog unit shall be used it must be enabled this is done by applying high level to the control pin OWE Semiconductor Group 5 19 SIEMENS On Chip Peripheral Components Detailled Description of the Oscillator Watchdog Unit Figure 5 7 shows the block diagram of the oscillator watchdog unit It consists of an internal RC oscillator which provides the
68. ial that is returned to us un sorted or which we are not obliged to accept we shall have to invoice you for any costs in curred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or with the ex press written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support de vice or system or to affect its safety or ef fectiveness of that device or system 2 Life support devices or systems are in tended a to be implanted in the human body or b to support and or maintain and sustain human life If they fail it is reasonable to assume that the health of the user may be endangered SAB 80 517 83 517 5 Revision History 05 94 Previous Version 11 92 Page Subjects major changes since last revision 11 92 3 8 SORELL adresses corrected 4 1 HWPD pin number corrected 5 3 Tg in table 5 1 corrected 5 10 5 11 CC4EN bit names and table 5 3 corrected Device Specifications SAB 80 517 83 517 5 Revision History 05 94 Previous Releases 01 94 08 93 11 92 10 91 04 91 Page Subjects changes since last revision 04 91 5 Pin configuration P
69. ication 7 1 Semiconductor Group SIEMENS Introduction 1 Introduction SAB 80C517A is a superset of the high end microcontroller SAB 806517 While maintaining all architectural and operational characteristics of the SAB 80C517 the SAB 80C517A incorporates more on chip RAM as well as some enhancements in the compare capture unit The oscillator watchdog got an improved functionality Also the operating frequency is higher than that of the SAB 80C517 10 bit ADC _ SAB 80 517 80 557 8 2 777 Port 0 et ROM 8k x 8 Wa bit Port 8 7 Port 6 Port 5 Port 4 ROM Protection available Port 0 0 Analog Analog 1 0 1 0 1 0 ROM Digital Digital 24k x 8 Input ROM Protection available improved functionality m SAB 80C517A 83C517A 5 In this manual any reference made to the SAB 80C517A applies to both versions the SAB 80 517 and the SAB 83C517A 5 unless otherwise noted Furthermore only new features of the SAB 80C517A in addition to the features of the SAB 80C517A 83C517A 5 are described For additional reference the user s manual of the SAB 80C517 80C537 Ord No B258 H6075 G1 X 7600 should be used Semiconductor Group 1 1 SIEMENS Introduction Listed below is a summary of the main features of the SAB 80C517A SAB 80C517A 83C517A 5 up to 18 MHz operation frequency 32 Kx8
70. igure 4 4 Power On of the SAB 80C517A 4 10 Semiconductor Group SIEMENS On Chip Peripheral Components 5 On Chip Peripheral Components 51 Digital Port Circuitry To realize the Hardware Power Down Mode with floating Port pins in the SAB 80 517 83 517 5 the standard port structure used in the 8051 Family is modified figure 5 1 The FETs p4 p5 and n2 are added During Hardware Power Down this FETs disconnect the port pins from internal logic 1 gt 1 p2 P3 p4 Port Pin 0 e 5 Input Data Read Pin 4 1 e HWPD n2 02252 5 1 Port Structure Semiconductor Group 5 1 SIEMENS On Chip Peripheral Components P1 and p3 are not active during Hardware Power Down P1 is activated only for two oscillator periods if a 0 1 transition is programmed to the port pin not possible during HWPD P3 is turned off during reset state also HWPD For detailled description of the port structure please refer to the SAB 80C517 80C537 User s Manual Semiconductor Group 5 2 On Chip Peripheral Components SIEMENS 5 2 10 bit A D Converter In the SAB 80C517A is a new high performance high speed 12 channel 10 bit A D Converter is
71. is not implied Exposure to absolute maximum rating conditions for longer periods may affect device reliability During overload conditions gt or Vin lt Vss theVoltage on pins with respect to ground Vss must not exeed the values definded by the absolute maximum ratings DC Characteristics 5 10 96 15 0 01070 C for the SAB 80C517A 83C517A 5 T a 4010 85 C for the SAB 80C517A T3 83C517A 5 T3 Ta 40to 110 C forthe SAB 80C517A T4 83C51 7A 5 T4 Parameter Symbol Limit Values Unit Test condition min max Input low voltage VL 0 5 0 2 except EA RESET HWPD 0 1 Input low voltage EA 0 5 0 2 Vcc IV 0 3 Input low voltage HWPD Vito 0 5 0 2 RESET 0 1 Input high voltage except 0 2 0 5 RESET XTAL2 HWPD 0 9 Input high voltage to XTAL2 1 0 7 0 5 V Input high voltage to RESET Vio 0 6 0 5 and HWPD Semiconductor Group 7 61 SIEMENS Device Specification DC Characteristics cont d Parameter Symbol Limit Values Unit Test condition min max Output low voltage VoL 0 45 V 10 21 6 mA ports 1 2 3 4 5 6 Output low voltage Vout 0 45 V Ip 3 2 mA ports ALE PSEN RO Output high voltage Vou 2 4 V 80 pA po
72. itten to XPAGE or P2 both writes selects the XRAM address range b Access to external memory The upper address byte must be written to P2 XPAGE will be loaded with the same address in order to deselect the XRAM Semiconductor Group 7 20 SIEMENS Device Specification Control of XRAM in the SAB 80C517A There are two control bits in register SYSCON which control the use and the bus operation during accesses to the additional On Chip RAM XRAM Special Function Register SYSCON Addr OB1y 1 SYSCON Bit Function XMAPO Global enable disable bit for XRAM memory 0 The access to XRAM On Chip XDATA memory is abled 1 The access to XRAM is disabled All MOVX accesses are formed by the external bus reset state XMAP1 Control bit for RD WR signals during accesses to XRAM this bit has no effect if XRAM is disabled XMAPO 1 or if addresses exceeding the XRAM address range are used for MOVX accesses XMAP1 0 The signals RD and WR are not activated during accesses to XRAM XMAP1 1 The signals RD and WR are activated during accesses to XRAM Reset value of SYSCON is xx01B The control bit XMAPO is a global enable disable bit for the additional On Chip RAM XRAM If this bitis set the XRAM is disabled all MOVX accesses use external memory via the external bus In this case the S
73. ity Register 1 BOY XX00 0000p WDTREL Watchdog Timer Reload Reg 86 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is indeterminate Semiconductor Group SIEMENS Memory Organization 3 4 Architecture for the XRAM The contents of the XRAM is not affected by a reset or HW Power Down After power up the contents is undefined while it remains unchanged during and after a reset or HW Power Down if the power supply is not turned off The additional On Chip RAM is logically located in the external data memory range at the upper end of the 64 KByte address range 800 It is possible to enable and disable only by reset the XRAM If it is disabled the device shows the same behaviour as the parts without XRAM i e all MOVX accesses use the external bus to physically external data memory 3 4 1 Accesses to XRAM Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM Note If a reset occurs during a write operation to XRAM the effect on XRAM depends on the cycle which the reset is detected at MOVX is a 2 cycle instruction Reset detection at cycle 1 The new value will not be written to XRAM The old value is not affected Reset detection at cycle 2 The old value in XRAM is o
74. l Structure The SAB 80 517 83 51 7 5 is a high end member of the Siemens SAB 8051 family of microcontrollers It is designed in Siemens ACMOS technology and based on the SAB 8051 architecture ACMOS is a technology which combines high speed and density characteristics with low power consumption or dissipation While maintaining all the SAB 80C517 features and operating characteristics the SAB 80C517A is expanded in its fail safe characteristics and timer capabilities Furthermore the SAB 80C517A additionally contains 2 kByte of on chip RAM called XRAM a 10bit A D converter with 12 multiplexed inputs enhanced Baud Rate Generators and the capabilities of the Compare Capture Unit are improved The SAB 80C517A is identical with the SAB 83C517A 5 except that it lacks the on chip program memory The SAB 80C517A 83C517A 5 is supplied in a 84 pin plastic leaded chip carrier package P LCC 84 and in a 100 pin plastic metric rectangular flat package P MRFP 100 The essential enhancements to the SAB 80C517 are Additional 2KByte RAM on chip 32 kByte on chip program memory SAB 83C517A 5 only 12 channel 10 bit A D Converter Additional Compare Mode for Concurrent Compare function at Port 5 up to eight pins on P5 can be either set or reset on a compare match in two additional compare registers Dedicated interrupt vector for the 16 bit compare registers 7 Interrupt requested on a compare match in one of t
75. lags Interrupt Vector Address Interrupt Source IEO 0003 External interrupt 0 TFO 000 Timer 0 overflow IE1 00134 External interrupt 1 TF1 001BH Timer 1 overflow RIO TIO 0023H Serial channel 0 TF2 EXF2 002By Timer 2 overflow ext reload ADC 00436 A D converter IEX2 004 External interrupt 2 IEX3 0053 External interrupt 3 IEX4 005Bu External interrupt 4 IEX5 0063 External interrupt 5 006Bu External interrupt 6 008314 Serial channel 1 ICMPO to ICMP7 00936 Compare match interrupt of Compare Registers CM7 assigned to Timer 2 CTF 009 Compare timer overflow ICS Compare match interrupt of Compare Register COMSET ICR OOABH Compare match interrupt of Compare Register COMCLR Each interrupt vector can be individually enabled disabled The response time to an interrupt request is more than 3 machine cycles and less than 9 machine cycles External interrupts 0 and 1 can be activated by a low level or a negative transition selectable at their corresponding input pin external interrupts 2 and 3 can be programmed for triggering on a negative or a positive transition The external interrupts 2 to 6 are combined with the corresponding alternate functions compare output and capture input on port 1 For programming of the priority levels the interrupt vectors are combined to pairs or triples Each pair or triple can be programmed individually to one of four priority levels by
76. mable 9th and a stop bit 1 In fact mode 3 is the same as mode 2 in all respects except the baud rate The baud rate in mode 3 is variable Variable Baud Rates for Serial Interface 0 Variable baud rates for modes 1 and 3 of serial interface 0 can be derived from either timer 1 or a dedicated Baudrate Generator The baud rate is generated by a free running 10 bit timer with programmable reload register 2 SMOD f osc Mode 1 3 baud rate 64 2 SOREL The default value after reset in the reload registers SORELL and SORELH provide a baud rate of 4 8 SMOD 0 or 9 6 kBaud SMOD 1 at 12 MHz oscillator frequency This guar antees full compatibility to the SAB 80C517 Semiconductor Group 7 55 SIEMENS Device Specification Serial Interface 1 Serial interface 1 can operate in two asynchronous modes Mode 9 UART variable baud rate 11 bits are transmitted through T x D1 or received through R x D1 a start bit 0 8 data bits LSB first a programmable 9th and a stop bit 1 On transmission the 9th data bit TB81 51 can be assigned to the value of 0 or 1 For example the parity bit in the PSW could be moved into TB81 or a second stop bit by setting TB81 to 1 On reception the 9th data bit goes into 81 in special function register S1CON while the stop bit is ignored Mode 8 bit UART variable baud rate 10 bits are transmitted through T x D1 or received through R
77. mation technique provides 7 us con version time fosc 16 MHz The conversion principle is upward compatible to the one used in the SAB 80C517 The main functional blocks are shown in figure 4 The comparator is a fully differential comparator for a high power supply rejection ratio and very low offset voltages The capacitor network is binary weighted providing genuine 10 bit resolution The table below shows the sample time 7 s and the conversion time which dependend On fosc and a new prescaler see also Bit ADCL in SFR ADCON 1 f osc MHz Prescaler f Apc MHz Sample Time Conversion Time incl sample time Ts us Tc us 12 8 1 5 2 67 9 33 16 0 75 5 33 18 66 16 8 2 0 2 0 7 0 16 1 0 4 0 14 0 18 8 16 1 125 3 55 12 4 Semiconductor Group 7 32 SIEMENS Device Specification 8 T internal Bus 2 MX 1 1 ADDATH ADDATL D94 Continous Mode A D Converter P6 0 ADST Write to ADDATL internal Bus Z Shaded areas are not used in ADC functions 1 488 Figure 4 Block Diagram A D Converter Semiconductor Group 7 33 SIEMENS Device Specification Compare Capture Unit CCU The compare capture unit is a complex timer register array for applications that require high speed I O pulse width modulation and more timer counter capabilities Th
78. mpare mode 2 disabled selected but only interrupt generation ICR ICS no output signals 0 0 1 1 Compare Capture Compare Mode 2 disabled selected at P5 0 1 0 0 Capture on falling Disabled rising edge at pin P1 4 INT2 CC4 0 1 1 0 Compare modes 2 selected but olny interrupt generation ICR ICS no output signals at P5 1 0 0 0 Compare enable at Disabled Mode 9 is selected by COMO 1 0 0 1 Compare mode 1 Concurrent compare enabled at CC4 mode 1 selected at COMO is P5 automatically set 1 0 1 0 Compare enable at Compare mode 2 CC4 mode 9 is selected but only selected by COMO interrupt generation ICR ICS no output signals at P5 1 0 1 1 Compare mode 1 Compare Mode 2 abled at CC4 COMO selected at P5 is automatically set 1 1 0 0 Capture on write Disabled operation into register CCL4 1 1 1 0 Capture on write Compare mode 2 operation into register CCL4 selected but only interrupt generation ICR ICS no output signals at P5 The other combinations are reserved and must not be used Semiconductor Group 5 11 SIEMENS On Chip Peripheral Components The following table 5 4 lists the SFR s with their addresses and default values after reset which are used in compare mode 2 Table 5 4 Compare Mode 2 used SFR s and their default Reset Value SFR Address Default Value after Reset COMSETL 0 1 00H COMSETH 0 2 00H COMCLRL 00H CO
79. nfiguration P LCC 84 Semiconductor Group 7 4 SIEMENS Device Specification P1 5 T2EX P1 6 CLKOUT CC4 INT2 P1 4 N C N C CC3 INT6 P1 3 CC2 INT5 P1 2 CC1 INT4 P1 1 CCO INT3 P1 0 5 P3 4 T0 5 P3 3 INT P3 2 INTO 5 P3 1 TxDO 5 P3 0 RxDO NC 5 N C 5 P7 0 5 P7 1 9 P7 2 5 PAS 5 P7 4 5 P7 5 5 P7 6 SAB 80C517A 83C517A 5 P7 7 VAGND VAREF N C N C N C N C RESET P4 7 CM7 P4 6 CM6 P4 5 CM5 P4 4 CM4 P4 3 CM3 PE SWD P4 2 CM2 P4 1 CM1 P4 0 CMO Vec Vss RO P8 3 P8 2 P8 1 P8 0 P6 7 P6 6 P6 5 N C N C N C LJ LJ J IJ e V ENTO CX O GO oO GO GO Q io i0 10 i0 10 10 10 6 na a a a a a O a a a US E eS Sooo Oo 7 02151 Pin Configuration P MQFP 100 2 Semiconductor Group 7 5 SIEMENS Device Specification Pin Definitions and Functions Symbol Pin Number P LCC 84 P MQFP 100 2 Function 4 0 P4 7 1 3 5 9 64 66 68 72 Port 4 is a bidirectional port with internal pull up resistors Port 4 pins that have 1 s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs por
80. nized in groups which refer to the functional blocks of the SAB 80C517A Table 2 Special Function Register Address Register Contents Address Register Contents after Reset after Reset PO 981 SOCON 00 81H SP 074 99H SOBUF XXH 82H DPL 00H 9 IEN2 XX00 00X0B 83 DPH 001 9By S1CON 0X00 0000B 844 WDTL 9 9CH S1BUF XXH 85H WDTH 001 S1RELL 00H 86H WDTREL reserved XXy 874 PCON 00H reserved XXH 88H TCON 00H P2 89 TMOD 004 COMSETL 00 TLO 00H A24 COMSETH 00H 8By TL1 COMCLRL 00 8CH THO 00H COMCLRH 004 8 TH1 004 SETMSK 00 reserved 2 CLRMSK reserved XXH 2 A74 reserved XXH 90H P1 OFFy 8 IENO 7 00H 91H XPAGE 00H IPO 00H 92H DPSEL XXXXX000B SORELL 93H reserved XXH ABH reserved XXH 944 reserved XX4 reserved 2 95 reserved ADH reserved XXH 964 reserved reserved 2 974 reserved 2 AFy reserved XXH 1 Bit addressable special function registers 2 X means that the value is indeterminate and the location is reserved 9 SFRs not user accessable Semiconductor Group 7 25 SIEMENS Device Specification Table 2 Special Function Register cont d Address Register Contents Address Register Contents after Reset after R
81. nput Vin must be high RO floating Vss lt output Semiconductor Group 7 53 SIEMENS Device Specification Serial Interfaces The SAB 80C517A has two serial interfaces Both interfaces are full duplex and receive buffered They are functionally identical with the serial interface of the SAB 8051 when working as asynchronous channels Serial interface 0 additionally has a synchronous mode Table 9 shows possible configurations and the according baud rates Table 9 Baud Rate Generation Mode Mode 0 8 Bit Baud fosc 1 1MHz 2 MHz chron Josce 1 33 MHz us 16 MHz channel fosc 1 5 MHz 18 MHz derived from fosc Mode Mode 1 Mode B 8 Bit Baud fosc 1 Baud 183 Baud 366 Baud UART rate 12 MHz 62 5 kBaud 375 kBaud 375 kBaud fosc 1 Baud 244 Baud 244 Baud 16 MHz 83 kBaud 500 kBaud 500 kBaud fosc 1 Baud 2375 Baud 549 Baud 18 MHz 93 7 kBaud 562 5 kBaud 562 5 kBaud derived from Timer 1 10 Bit 10 Bit Baudrate Baudrate Generator Generator Mode Mode 2 Mode 3 Mode A 9 Bit Baud fosc 187 5 kBaud 1 Baud 183 Baud 183 UART rate 12 MHz 375 kBaud 62 5 75 kBaud 75 kBaud fosc 250 Baud 1 Baud 244 Baud 244 Baud 16 MHz 500 kBaud 83 3 500 kBaud 500 kBaud fosc 281 2 kBaud 1 Baud 275 Baud 549 Baud 18 MHz 562 5 kBaud 93 7 kBaud 562 5 kBa
82. nput of the internal clock system to the output of the RC oscillator This means that the part is being clocked even if the on chip oscillator has stopped or has not yet started At the same time the watchdog activates the internal reset in order to bring the part in its defined reset state The reset is performed because clock is available from the RC oscillator This internal watchdog reset has the same effects as an externally applied reset signal with the following exception The Watchdog Timer Status flag WDTS 0 6 is not reset the Watchdog Timer however is stopped and bit OWDS is set This allows the software to examine error conditions detected by the Watchdog Timer even if meanwhile an oscillator failure occured The oscillator watchdog is able to detect a recovery of the on chip oscillator after a failure If the frequency derived from the on chip oscillator is again higher than the reference the watchdog starts a final reset sequence which takes typ 1 ms Within that time the clock is still supplied by the RC oscillator and the part is held in reset This allows a reliable stabilization of the on chip oscillator After that the watchdog toggles the clock supply back to the on chip oscillator and releases the reset request If no external reset is applied in this moment the part will start program execution If an external reset is active however the device will keep the reset state until also the external reset request disappears Fur
83. ntents of XPAGE is less than the XRAM address range then an external bus access is performed where the upper address byte is provided by P2 and not by XPAGE Therefore the software has to distinguish two cases if the MOVX Ri instructions with paging shall be used a Access to The upper address byte must be written to XPAGE or P2 both writes selects the XRAM address range b Access to external memory The upper address byte must be written to P2 XPAGE will be loaded with the same address in order to deselect the XRAM The behaviour of Port2 and the RD WR signals depends on the state of pin EA and on the control bits XMAPO and in register SYSCON Semiconductor Group 3 14 SIEMENS Memory Organization 3 4 2 Control of XRAM in the SAB 80 517 There are two control bits in register SYSCON which control the use and the bus operation during accesses to the additional On Chip RAM in XDATA range 4 XRAM Special Function Register SYSCON MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr 1 ES XMAP1 SYSCON Bit Function XMAPO Global enable disable bit for XRAM memory 0 The access to XRAM On Chip XDATA memory is enabled 1 The access to XRAM is disabled All MOVX accesses are performed by the external bus XMAP 1 Control bit for RD WR signals during accesses to XRAM this bit has no effect if XRAM is disabled
84. oes not include plastic or metal protrusions of 0 15max per side Dimensions in mm Plastic Package P MQFP 100 2 SMD Plastic Metric Rectangular Flat Package 2 18 H o lora 1885 1 035 101 0 7 008 2 0319 91 042 100 2821025 ja 02 A BIDI50x 201019 4 0 2 A BIDIHI2x White bar i 501 Ww E GS E Est 100 lt 1 30 Bottom side 1 Index Marking 2 Does not include dambar protrusion of 0 08 max per side 1 Does not include plastic or metal protrusion of 0 25 max per side Dimensions in mm SMD Surface Mounted Device Semiconductor Group 7 75
85. ogic 1 and 0 45 V for a logic 07 Timing measure ments are made at for a logic 1 and max for a logic 0 AC Testing Input Output Waveforms 0 1V Vou 0 1V Timing Reference Points 0 1V VoL 0 1V MCA00606 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when 100 mV change from the loaded V op Va level occurs Ig gt 20 mA AC Testing Float Waveforms XTALI N C XTALI MQFP 100 2 Pin 13 100 2 13 P LCC 84 Pin 40 P LCC 84 Pin 40 3 5 18 MHz XTAL2 XTAL2 P LCC 84 Pin 39 External Oscillator P LCC 84 Pin 39 MQFP 100 2 Pin 12 Signal MQFP 100 2 Pin 12 10pF incl stray capacitance Crystal Oscillator Mode Driving from External Source Recommended Oscillator Circuits Semiconductor Group 7 74 SIEMENS Device Specification Package Outlines Plastic Package P LCC 84 SMD Plastic Leaded Chip Carrier 1 2 45 MILE zl sur aO SZ gt 127 0 81 i 28 2 05 j 0 43 0 1 224 0 1 M 294 27 25 4 4 30 35 0 25 GPL05029 mood 841 Index Marking 1445 30 35 95 gt 1 D
86. ollowing instruction has to set the start bit PDS Bits PDE and PDS will automatically be cleared after having been set The instruction that sets bit PDS is the last instruction executed before going into power down mode The only exit from power down mode is a hardware reset The status of all output lines of the controller can be looked up in table 8 Hardware Controlled Power Down Mode The pin HWPD controls this mode If it is on logic high level inactive the part is running in the normal operating modes If pin HWPD gets active low level the part enters the Hardware Power Down Mode this is independent of the state of pin PE SWD HWPD is sampled once per machine cycle If it is found active the device starts a complete internal reset sequence The watchdog timer is stopped and its status flag WDTS is cleared exactly the same effects as a hardware reset In this phase the power consumption is not yet reduced After completion of the internal reset both oscillators of the chip are disabled At the same time the port pins and several control lines enter a floating state as shown in table 8 In this state the power consumption is reduced to the power down current IPD Also the supply voltage can be reduced Table 8 also lists the voltages which may be applied at the pins during Hardware Power Down Mode without affecting the low power consumption Termination of HWPD Mode This power down state is maintained while pin HWPD is held active
87. omponents Special Function Registers ADCONO ADCON1 MSB Bit No 7 LSB Addr OD8 BSY ADM 2 1 ADCONO Bit No 7 LSB 6 5 4 3 2 1 0 Addr ODCy ADCL 2 1 ADCON1 These bits are not used in controlling A D converter functions in the 80 517 Bit Function ADEX Internal external start of conversion When set the external start of conversion by P6 0 ADST is enabled BSY Busy flag This flag indicates whether a conversion is in progress BSY 1 The flag is cleared by hardware when the conversion is finished ADM A D Conversion mode When set a continous conversion is selected If cleared the converter stops after one conversion Select 12 input channels of the ADC Bits to MX2 con be written or read either in ADCONO or in ADCON1 ADCL ADC Clock When set fosc 16 Has to be set when fosc gt 16 MHz The reset value of ADCONO ADCON1 is 00 Semiconductor Group 5 5 SIEMENS On Chip Peripheral Components Special Function Register ADDATH ADDATL MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr OD9 msb ADDATH MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr ODAH Isb ADDATL These bits are not used for conversion result The reset value of ADDATH and ADDATL is 00
88. on code 8 bit CMOS microcontroller SAB 80 517 18 Q67120 C583 P LCC 84 for external memory 18 MHz SAB 80 517 18 TBD P MRFP 100 18 MHz SAB 80C517A N18 T3 Q67120 C769 P LCC 84 for external memory 18 MHz ext temperature 40 to 85 SAB 83C517A 5N18 T3 067120 771 P LCC 84 with mask programmable ROM 18 MHz ext temperature 40 to 85 SAB 83C517A N18 T4 TBD P LCC 84 for external memory 18 MHz ext temperature 40 to 110 C SAB 83 517 5 18 4 P LCC 84 with mask programmable ROM 18 MHz ext temperature 40 to 110 C Semiconductor Group 7 2 SIEMENS Device Specification SAB _ 80C517A ET 83C517A 5 XTAL2 WCLO1478 Logic Symbol Semiconductor Group 7 3 Port 0 8 bit Port 1 8 bit Port 2 8 bit Port 3 8 bit Port 4 8 bit Port 5 8 bit Port 6 8 bit SIEMENS Device Specification The pin functions of the SAB 80C51 7A are identical with those of the SAB 80051 7 80C537 with one exception Typ SAB 80C517A SAB 80 517 80 537 P LCC 84 Pin 60 P MQFP 100 2 Pin 36 HWPD N C 7 7 6 3 7 6 P6 2 7 5 P6 1 7 4 P6 0 P7 3 OWE P7 2 P5 0 P7 1 P5 1 P7 0 5 2 3 0 SAB P5 3 P3 1 P5 4 P3 2 80C517A 83C517A 5 P5 5 P3 3 P5 6 P3 4 P5 7 P3 5 HWPD P3 6 P0 7 P3 7 P0 6 P1 7 P0 5 P1 6 P0 4 P1 5 P0 3 P1 4 P0 2 LJ ILILTLILI MAN Ope ue 5 ao ae fearkaereeay lt 1 479 Pin Co
89. or control applications With a 18 MHz crystal 58 of the instructions are executed in 666 67 ns Being designed to close the performance gap to the 16 bit microcontroller world the SAB 80C517A s CPU is supported by a powerful 32 16 bit arithmetic unit and a more flexible addressing of external memory by eight 16 bit datapointers Memory Organisation According to the SAB 8051 architecture the SAB 80C517A has separate address spaces for program and data memory Figure 2 illustrates the mapping of address spaces H int ext 0 0 XMAPO 1 is F800g F800H addr F7FFH 7FFFY int RAM ext 0 ext int RAM L Lm aa U Code Space external Data Space internal Data Space 1487 Figure 2 Memory Semiconductor Group 7 16 SIEMENS Device Specification Program Memory Code Space The SAB 83C517A 5 has 32 Kbyte of on chip ROM while the SAB 80C517A has internal ROM The program memory can externally be expanded up to 64 Kbyte Pin EA controls whether program fetches below address 8000H are done from internal or external memory As a new feature the SAB 83C517A 5 offers the possibility of protecting the internal ROM against unauthorized access This protection is implemented in the ROM Mask Therefore the decision ROM Protection yes or has to be made when delivering the ROM Code Once enabled th
90. ort 2 pins when these pins make 1 to 0 transitions during bus operation In the worst case capacitive loading 100 pF the noise pulse on ALE line may exceed 0 8 V In such cases it may be desirable to qualify ALE with a schmitt trigger or use an address latch with a schmitt trigger strobe input Capacitive loading on ports 0 and 2 may cause the on ALE and PSEN to momentarily fall below the 0 9 specification when the address lines are stabilizing Ipp Power down mode is measured with EA RESET Voc PortO Port7 Port8 XTAL2 PE SWD OWE gs HWDP Software Power Down mode Vaner VAGND ss all other pins are disconnected Hardware Powerdown OWE Vss No certain pin connection for the other pins active mode is measured with XTAL2 driven with ICLCH 5 5 Vss 0 5 0 5 V XTAL1 N C EA PE SWD Porto Port7 Port8 HWPD RESET all other pins are disconnected cc would be slightly higher if a crystal oscillator is used appr 1 mA Icc Idle mode is measured with all output pins disconnected and with all peripherals disabled XTAL2 driven with cLCH 5 ns ViL E Vss 0 5 V Vin 0 5 V XTAL1 RESET HWPD Porto Port7 Port8 EA PE SWD all other pins are disconnect
91. own Mode If the Hardware Power Down Mode is terminated the oscillator watchdog has to control the correct start up of the on chip oscillator and to restart the program The oscillator watchdog function is only part of the complete Hardware Power Down sequence however the watchdog works identically to the monitoring function Fast internal reset after power on In this function the oscillator watchdog unit provides a clock supply for the reset before the on chip oscillator has started In this case the oscillator watchdog unit also works identically to the monitoring function If the oscillator watchdog unit is to be used it must be enabled this is done by applying high level to the control pin OWE Figure 12 shows the block diagram of the oscillator watchdog unit It consists of an internal RC oscillator which provides the reference frequency of the on chip oscillator The RC oscillator can be enabled disabled by the control pin OWE If it is disabled the complete unit has no function Semiconductor Group 7 58 SIEMENS Device Specification RC Fre Oscillator 1 5MHz Reset Frequency fa lt fi Comparator Dalay int XTALI 9 0 9 On Chip int Clock 2 MCB01496 Figure 12 Functional Block Diagram of the Oscillator Watchdog Semiconductor Group 7 59 SIEMENS Device Specification Fast internal reset after
92. power on The SAB 80C517A can use the oscillator watchdog unit for a fast internal reset procedure after power on Normally members of the 8051 family like the SAB 80C517 enter their default reset state not before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 1 ms During this time period the pins have an undefined state which could have severe effects e g to actuators connected to port pins In the SAB 80C517A the oscillator watchdog unit avoids this situation However the oscillator watchdog must be enabled In this case after power on the oscillator watch dog s RC oscillator starts working within a very short start up time typ less than 2 micro seconds In the following the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is valid the watchdog uses the RC oscillator output as clock source for the chip rather than the on chip oscillator s output This allows correct resetting of the part and brings also all ports to the defined state Delay time between power on and correct reset state Typ 18 us Max 34 us Instruction Se
93. r frequency This guarantees full compatibility to the SAB 80C517 Timer 1 Overflow ADCONO 7 PCON 7 Baud Rate BD dd SMOD 2 9 Generator Mode 13 a 2 705 2 unt ON Clock Mode 2 MCB02248 Figure 5 5 Block Diagram of Baud Rate Generation for Serial Interface 0 If the new baud rate generator is used the baud rate of Serial Channel 0 in Mode 1 and 3 can be determined as follows 23VOP x oscillator frequency 64 x 210 SOREL Mode 1 3 baud rate with SOREL SORELH 1 0 SORELL 7 0 Semiconductor Group 5 16 SIEMENS On Chip Peripheral Components 5 4 2 Serial Channel 1 Baud Rate Generator A new baud rate generator for Serial Channel 1 now offers a wider range of selectable baud rates Especially a baud rate of 1200 baud can be achieved now The baud rate generator itself is identical with the one used for Serial Channel 0 It consists of a free running 10 bit timer with 2 input frequency On overflow of this timer there is an automatic reload from the registers S1RELL address 9 and S1RELH address The lower 8 bits of the timer are reloaded from S1RELL while the upper two bits are reloaded from bit 0 and 1 of register S1RELH The baud rate timer is reloaded by writing to S1RELL The baud rate in mode A and B can be determined by
94. re the SAB 80C517A has separate address spaces for program and data memory Figure 3 1 illustrates the mapping of address spaces int ext xMAPO 0 _ XMAPO ext indirect direct F800 F8004 addr 7 int RAM SFR 80H ext int RAM 00004 004 D Code Space external Data Space internal Data Space MCD01 487 Figure 3 1 Memory Map Semiconductor Group 3 1 SIEMENS Memory Organization 31 Program Memory ROM Protection The SAB 83C517A 5 has 32 Kbyte of on chip ROM while the SAB 80C517A has no internal ROM The program memory can externally be expanded up to 64 Kbyte Pin EA controls whether program fetches below address 8000H are done from internal or external memory As a new feature the SAB 83C517A 5 offers the possibillity of protecting the internal ROM against unauthorized access This protection is implemented in the ROM Mask Therefore the decision ROM Protection yes or has to be made when delivering the ROM Code Once enabled there is no way of disabling the ROM Protection Effect The access to internal ROM done by an externally fetched MOVC instruction is disabled Nevertheless an access from internal ROM to external ROM is possible To verify the read protected ROM Code a special ROM Verify Mode is implemented This mode also can be used to verify unprotected internal ROM ROM Protection
95. reference frequency for the comparison with the frequency of the on chip oscillator The RC oscillator can be enabled disabled by the control pin OWE If it is disabled the complete unit has no function RC Oscillator f OWE Ismiz c Enable Frequency lt Delay f Comparator Int XTAL1 Reset 0A9 4 XTAL2 OWDS c Oscillator 1 2 Int Clock MCS02247 Figure 5 7 Oscillator Watchdog Unit Special Function Register IPO Address 0A9H Bit No MSB LSB 7 3 2 1 0 9 OWDS WDTS 0 5 IPO IPO These bits are not used in controlling the fail safe mechanisms Bit Function OWDS Oscillator watchdog timer status flag Set by hardware when an oscillator watchdog reset occurred Can be cleared or set by software Reset value of IPO is 00 Semiconductor Group 5 20 SIEMENS On Chip Peripheral Components The frequency coming from the RC oscillator is divided by 5 and compared to the on chip oscillator s frequency If the frequency coming from the on chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects a failure condition the oscillation at the on chip oscillator could stop because of crystal damage etc In this case it switches the i
96. ress range fromF800y to FFFFy Special Function Register SYSCON controls whether data is read or written to XRAM or external RAM Semiconductor Group 3 3 SIEMENS Memory Organization 3 3 Special Function Registers All registers except the program counter and the four general purpose register banks reside in the special function register area The 81 special function registers include arithmetic registers pointers and registers that provide an interface between the CPU and the on chip peripherals There are also 128 directly addressable bits within the SFR area All special function registers are listed in table 3 1 and table 3 2 In table 3 1 they are organized in numeric order of their addresses In table 3 2 they are organized in groups which refer to the functional blocks of the SAB 80C517A Table 3 1 Special Function Register Address Register Contents Address Register Contents after Reset after Reset 80H FFy Ady P2 81 SP 07 Aly COMSETL 00H 824 DPL 00H A2H COMSETH 83H DPH 00H A3H COMCLRL 00H 84H WDTL A4y COMCLRH 00H 85H WDTH A5H SETMSK 00H 86H WDTREL 00H A6H CJRMSK 00H 87H PCON 00H 88 00H 8 1 00H 89H TMOD 00H 8AH TLO 00H AAH SORELL D9H 8By TL1 00H ABH 8CH THO ACy 1 00H ADH 8EH AFy 1 1 FFy
97. ring an access to external memory port 0 emits the low order address byte and reads writes the data byte while port 2 emits the high order address byte In this function port 0 is not an open drain port but uses a strong internal pull up FET Port 1 3 4 5 and port 6 provide several alternate functions Please see the Pin Description for details Port pins show the information written to the port latches when used as general purpose port When an alternate function is used the port pin is controlled by the respective peripheral unit Therefore the port latch must contain a one for that function to operate The same applies when the port pins are used as inputs Ports 1 3 4 and 5 are bit addressable The SAB 80C517A has two dual purpose input ports The twelve port lines at port 7 and port 8 can be used as analog inputs for the A D converter If input voltages at P7 and P8 meet the specified digital input levels Vj and the port can also be used as digital input port In Hardware Power Down Mode the port pins and several control lines enter a floating state For more details see the section about Hardware Power Down Mode Semiconductor Group 7 48 SIEMENS Device Specification Power Saving Modes SAB 80C517A provides due to Siemens ACMOS technology four modes in which pow er consumption can be significantly reduced The Slow Down Mode The controller keeps up the full operating functionality but is d
98. riority Register 1 0 9 XX00 0000B IRCONO Interrupt Request Control Register 7 00 IRCON1 Interrupt Request Control Register 001 H 001 TCON 2 Timer Control Register 884 0014 TCON 2 Timer 2 Control Register 0 8 ARCON Arithmetic Control Register XXXXB Unit MDO Multiplication Division Register 0 9 XXH MD1 Multiplication Division Register 1 XXH MD2 Multiplication Division Register 2 XXH MD3 Multiplication Division Register 3 XXH MD4 Multiplication Division Register 4 XXH MD5 Multiplication Division Register 5 OEE XXH 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is indeterminate and the location is reserved Semiconductor Group 7 28 SIEMENS Device Specification Table 3 Special Function Registers Functional Blocks Block Symbol Name Address Contents after Reset Compare Comp Capture Enable Reg 0C1y 00H Capture CC4EN Comp Capture Enable 4 Reg 9 00H Unit CCH1 Comp Capture Reg 1 High Byte 0C3j 00H CCU CCH2 Comp Capture Reg 2 High Byte 0 5 00 Timer 2 CCH3 Comp Capture Reg 3 High Byte 0 7 00 4 Comp Capture Reg 4 High Byte 00H CCL1 Comp Capture Reg 1 Low Byte 0C2y 00H CCL2 Comp Capture Reg
99. riven with one eighth of its normal operating frequency Slowing down the frequency remarkable reduces power consumption The Idle Mode The CPU is gated off from the oscillator but all peripherals are still supplied with the clock and continue working The Power Down Mode Operation of the SAB 80C517A is stopped the on chip oscillator and the RC oscillator are turned off This mode is used to save the contents of the internal RAM with a very low standby current The Hardware Power Down Mode Operation of the SAB 80C517A is stopped the on chip oscillator and the RC Oscillator are turned off The pin HWPD controls this mode Port pins and several control lines enter a floating state The Hardware Power Down Mode is independent of the state of pin PE SWD Hardware Enable for Software controlled Power Saving Modes A dedicated Pin PE SWD of the SAB 80C517A allows to block the Software controlled power saving modes Since this pin is mostly used in noise critical application it is combined with an automatic start of the Watchdog Timer PE SWD logic high level Using of the power saving modes is not possible The watchdog timer starts immediately after reset The instruction sequences used for entering of power saving modes will not affect the normal operation of the device PE SWD V logic low level power saving modes can be activated by software When left unconnected Pin PE SWD is pulled high by a weak int
100. rom external data memory Internal Data Memory The internal data memory is divided into four physically distinct blocks the lower 128 bytes of RAM including four banks containing eight registers each the upper 128 byte of RAM the 128 byte special function register area a2 8 area which is accessed like external RAM MOVX instructions implemented on chip at the address range from F800 to FFFFy Special Function Register SYSCON controls whether data is read or written to XRAM or external RAM A mapping of the internal data memory is also shown in figure 2 The overlapping address spaces are accessed by different addressing modes see User s Manual SAB 80C517 The stack can be located anywhere in the internal data memory Architecture for the The contents of the XRAM is not affected by a reset or HW Power Down After power up the contents is undefined while it remains unchanged during and after a reset or HW Power Down if the power supply is not turned off The additional On Chip RAM is logically located in the external data memory range at the upper end of the 64 Kbyte address range It is possible to enable and disable only by reset the XRAM If it is disabled the device shows the same behaviour as the parts without XRAM i e all MOVX accesses use the external bus to physically external data memory Semiconductor Group 7 18 SIEMENS Device Specification Accesses to XRA
101. rts 1 2 3 4 5 6 0 9 V 210 pA Output high voltage Vout 2 4 V 2 800 pA port O in external bus mode 0 9 80 pA ALE PSEN RO Logic input low current Iy 10 70 uA Vij 0 45 V ports 1 2 3 4 5 6 Logical 1 to 0 transition current 65 650 2 ports 1 2 3 4 5 6 Input leakage current Ij 100 0 45 lt ViN lt 7 8 HWPD port 0 EA ports 7 8 150 nA 10 45 lt V lt Vec gt 100 Input low current to RESET 2 10 100 Vin 0 45 V for reset Input low current XTAL2 113 15 Vin 0 45 V Input low current 20 Vin 0 45 V PE SWD OWE Pin capacitance 10 pF 1 MHz 25 Power supply current Active mode 12 MHz Icc 28 mA 5 Active mode 18 MHz 37 mA 5 Idle mode 12 MHz Icc 24 mA 5 9 Idle mode 18 MHz 31 mA 5 Slow down mode 12 MHz loc 12 mA 5 9 Slow down mode 18 MHz 16 mA 5 Power Down Mode Ipp 50 pA 2 5 5 V 9 Notes see page 63 Semiconductor Group 7 62 SIEMENS Device Specification Notes for page 62 1 Y C2 e Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo of ALE and ports 1 3 4 5 and 6 The noise is due to external bus capacitance discharging into the port O and p
102. s indeterminate Semiconductor Group SIEMENS Memory Organization Table 3 1 Special Function Register Block Symbol Name Address Contents after Reset Ports PO Port 0 80H FFH P1 Port 1 90H 2 Port 2 Port 3 4 Port 4 E8y 5 5 F8y 6 6 FFH P7 Port 7 Analog Digital Input DBH 8 Port 8 Analog Digital Input 4 bit DDy Power Control Register 87H 00H Modes Serial ADCONO A D Converter Control Reg D8y 00H Channels PCON Power Control Register 87H 00H SOBUF Serial Channel 0 Buffer Reg 99H XXH SOCON Serial Channel 0 Control Reg 98 00H SORELL Serial Channel 0 Reload Reg low byte SORELH Serial Channel 0 Reload Reg high byte XXXX XX11p S1BUF Serial Channel 1 Buffer Reg 9CH 3 51 Serial Channel 1 Control Reg 0X00 0000p S1RELL Serial Channel 1 Reload Reg low byte 9Dy 00H S1RELH Serial Channel 1 Reload Reg high byte BBy XXXX XX1 1p Timer 0 TCON Timer Control Register 88H 00H Timer 1 THO Timer 0 High Byte 8CH 1 Timer 1 High Byte 00H TLO Timer 0 Low Byte 8 00H TL1 Timer 1 Low Byte 8BH 00H TMOD Timer Mode Register 89H 00H Watchdog IENO 2 Interrupt Enable Register 0 8 00H 2 Interrupt Enable Register 1 8 00H 2 Interrupt Priority Register 0 00H 2 Interrupt Prior
103. s well as shift and normalize features All operations are integer operation Operation Result Remainder Execution Time 32 bit 16 bit 32 bit 16 bit 6 toy 16 bit 16 bit 16 bit 16 bit Aty 16 bit 16 bit 32 bit 41 32 bit normalize Etga 32 bit shift left right 6 toy Te 31 Icy 1 us 12 MHz oscillator frequency 2 The maximal shift speed is 6 shifts cycle The MDU consists of six registers used for operands and results and one control register Operation of the MDU can be divided in three phases 1st Write MDO Last Write MD5 or ARCON First Read Last Read MDO MD3 or MD5 1 gt Phase 2 P Phase 3 Load Registers Calculate Read Registers Time 00787 Operation of the MDU To start an operation register MDO to MD5 or ARCON must be written to in a certain se quence according to table 5 or 6 The order the registers are accessed determines the type of the operation A shift operation is started by a final write operation to register ARCON see also the register description Semiconductor Group 7 46 SIEMENS Device Specification Table 6 Performing a MDU Calculation Operation 32 Bit 16 Bit 16 Bit 16 Bit 16 Bit 16 Bit First Write MDO D endL D endL MDO MD1 D end MD1 D endH MD4 M orL MD2 D end MD3 D endH MD4 D orL MD1 M andH MD4 D orL Last Write MD5 D orH M
104. t SAB 80C517A 83 517 5 has the same instruction set as the industry standard 8051 microcontroller A pocket guide is available which contains the complete instruction set in functional and hexadecimal order Furtheron it provides helpful information about Special Function Registers Interrupt Vectors and Assembler Directives Literature Information Title Ordering No Microcontroller Family SAB 8051 Pocket Guide B158 H6497 X X 7600 Semiconductor Group 7 60 SIEMENS Device Specification Absolute Maximum Ratings Ambient temperature under 2 44111 4010 110 C Storade termperatUle c uoo oo rni pra de a rte E kar E 65 to 150 Voltage on pins with respect to ground 4 22 2221 0 5 Vto6 5 V Voltage on any pin with respect to ground Vas 0 5 to Vcc 40 5 V Input current on any pin during overload condition 10 to 10 Absolute sum of all input currents during overload condition 100mAl 1W Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
105. t 4 pins being externally pulled low will source current in the DC char acteristics because of the internal pull up resistors This port also serves alternate compare functions The secondary functions are assigned to the pins of port 4 as follows CMO 4 0 Compare Channel 0 CM1 P4 1 Compare Channel 1 CM2 P4 2 Compare Channel 2 P4 3 Compare Channel 3 P4 4 Compare Channel 4 5 4 5 Compare Channel 5 CM6 P4 6 Compare Channel 6 CM7 P4 7 Compare Channel 7 PE SWD 67 Power saving modes enable Start Watchdog Timer A low level on this pin allows the soft ware to enter the power down idle and slow down mode In case the low level is also seen during reset the watchdog timer function is off on default Use of the software controlled power saving modes is blocked when this pin is held on high level A high level during reset performs an automatic start of the watchdog timer immediately after reset When left unconnected this pin is pulled high by a weak internal pull up resistor 1 Input O Output Semiconductor Group SIEMENS Device Specification Pin Definitions and Functions cont d Symbol Pin Number P LCC 84 P MQFP 100 2 Function RESET 10 73 RESET A low level on this pin for the duration of one machine cycle while the oscillator is running resets the SAB 80C517A
106. t signal can be determined by software A timer overflow signal does not affect the compare output Mode 2 compare mode 2 the concurrent compare output pins on Port 5 are used as follows see figure 9 When a compare match occurs with register COMSET a high level appears at the pins of port 5 whose corresponding bits in the mask register SETMSK address 0A5 are set When a compare match occurs in register COMCLR a low level appears at the pins of port 5 whose corresponding bits in the mask register CLRMSK address are set Additionally the Port 5 pins used for compare mode 2 may also be directly written to by write instructions to SFR P5 Of course the pins can also be read under program control Compare registers CMO to CM7 use additional compare latches when operated in mode 0 Figure 8 shows the function of these latches The latches are implemented to prevent from loss of compare matches which may occur when loading of the compare values is not correlated with the timer count The compare latches are automatically loaded from the compare registers at every timer overflow Capture This feature permits saving of the actual timer counter contents into a selected register upon an external event or a software write operation Two modes are provided to freeze the current 16 bit value of timer 2 registers into a dedicated capture register Mode 0 Capture is performed in response to a transition at the correspon
107. tage Range at Pin During HW Power Down PO P1 P2 P3 P4 Floating outputs Vss S Vin S P5 P6 P7 P8 Disabled input function EA active input Vin Voc OF Vin Vss PE SWD active input Pull up resistor disabled Vin or Vin Vss during HW power down XTAL1 active output pin may not be driven XTAL2 disabled input function Vss Vin lt PSEN ALE Floating outputs Vss lt Vin lt Disabled input function for test modes only VAREF VAGND active supply pins lt Vin lt Voc OWE active input must be at high level for Vin start up after HW PD pull up resistor or disabled during HW power down Vin Vss Reset active input must be on high level if Vin HW PD is used RO Floating output Vss lt Vin lt Vec Semiconductor Group SIEMENS System Reset The power down state is maintained while pin HWPD is held active If HWPD goes to high level inactive state an automatic start up procedure is performed First the pins leave their floating condition and enter their default reset state as they had immediately before going to float state Both oscillators are enabled only if OWE high While the on chip oscillator with pins XTAL1 and XTAL2 usually needs a longer time for start up if not externally driven with crystal approx 1 ms the oscillator watchdog s RC oscillator has a very short start up time
108. tate of pin EA The table 1 lists the various operating conditions It shows the following characteristics a Use of and P2 pins during the MOVX access Bus The pins work as external address data bus If internal XRAM is accessed the data written to the XRAM can be seen on the bus in debug mode 0 The pins work as Input Output lines under control of their latch b Activation of the RD and WR pin during the access Use of internal or external XDATA memory The shaded areas describe the standard operation as each 80C51 device without on chip XRAM behaves Semiconductor Group 7 22 Device Specification SIEMENS 608 01 pesn s 2 pesn s WWHX 9 SI 2 pesn s Nvux 9 9 pesn WWHX 9 ennoeul Pesnsimvux o a T 0 eyeg SALU 9 O le ed Ajuo eeg Ajuo eyeq ppe sng od e sna c od e O le 2d 0d e sng 0 e e INVHX pesn pesn pesn pesn pesn pesn SI 9 9 1 9 O le 2d sng od pesn SI 9 YM GY 9 sng 2ed od s 5 9 0
109. ter CMx occured only if compare function enabled for must be cleared by software CMSEL x 0 and CMEN x 1 The reset value of IRCON1 is 00 Semiconductor Group 6 3 SIEMENS Interrupt System 6 2 Interrupt Structure This section summarizes the expanded interrupt structure of the SAB 80C517A which has 3 new interrupt vectors in addition to the 14 vectors of the SAB 80C517 Thus 17 vectors are available now The new interrupt sources are 1 Request Flags to ICMP7 Interrupt vector Enable Bit Priority Request Flag ICS Interrupt Vector Enable Bit Priority Request Flag ICR Interrupt Vector Enable Bit Priority Semiconductor Group These eight request flags are set by compare matches in the compare registers CMO 7 if the compare function is enabled and compare mode 1 is selected for the corresponding register SCMO 7 0093H ECMP IEN2 2 Same priority as IE1 IEX3 programmed by IP1 2 IP0 2 This request flag is set by a compare match in compare register COMSET 00A3H ECS IEN2 4 Same priority as RIO TIO IEX5 programmed by IP1 4 IPO 4 This request flag is set by a compare match in compare register COMCLR ECR IEN2 5 Same priority as TF2 EXF2 IEX6 programmed by IP1 5 IP0 5 SIEMENS Interrupt System 31 Priority Level Structure The following tables show the SFR IEN2 the priority level grouping table 6 1
110. ternal logic is not included The Reset pin overrides the Hardware Power Down function i e if reset gets active during Hardware Power Down it is terminated and the device performs the normal reset function Thus pin Reset has to be inactive during Hardware Power Down Mode Semiconductor Group 4 4 SIEMENS System Reset Internal Reset Ports On Chip Oscillator 99 90 SI S2 SS 54 S3 S6 SI S2 S3 4 S3 S6 91 92 S3 54 S3 S6 S1 52 S3 S4 S3 S6 MANU E MES Son HWPD HWPD P1 Reset Float State RESET T Float State Normal Internal Reset Sequence Reduced Power Operation Consumption m Figure 4 1 Timing Diagram of Entering Hardware Power Down Mode Semiconductor Group SIEMENS System Reset S6 51 52 S3 54 55 56 P2 P2 Inactive EE Y HWPD _ Internal Reset Ports Float State si CMM Oscillator 44 Vf 2 RC Oscillator E _ RESET T Float State pd Pad gt lt gt lt Normal Operation Oscillator watchdog detects on chip OWD detects oscillator failure RC oscillator start up on chip oscillator time appr 2us delay between HWPD is ok add 768 inactive and correct reset state is clock cycles typ 18 us max 34 us
111. the WDT is not possible Software initialization is done by setting bit SWDT A refresh of the watchdog timer is done by setting bits WDT and SWDT consecutively A block diagram of the watchdog timer is shown in figure 11 When a watchdog timer resest occurs the watchdog timer keeps on running but a status flag WDTS is set This flag can also be cleared by software O WDT Reset Request WDTH 0 9 Hardware Power Down HWPD External HW Reset PE SWD Nm WDTREL Control Logic 01495 o Figure 11 Block Diagram of the Programmable Watchdog Timer Semiconductor Group 7 57 SIEMENS Device Specification Oscillator Watchdog The unit serves three functions Monitoring of the on chip oscillator s function The watchdog supervises the on chip oscillator s frequency if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit the internal clock is supplied by the RC oscillator and the device is forced into reset if the failure condition disappears i e the on chip oscillator has again a higher frequency than the RC oscillator the part executes a final reset phase of appr 0 25 ms in order to allow the oscillator to stabilize then the oscillator watchdog reset is released and the part starts program execution again Restart from the Hardware Power D
112. thermore the status flag OWDS 0 7 is set if the oscillator watchdog was active The status flag can be evaluated by software to detect that a reset was caused by the oscillator watchdog The flag OWDS can be set or cleared by software An external reset request however also resets OWDS and WDTS Semiconductor Group 5 21 SIEMENS Interrupt System 6 Interrupt System 6 4 Additional Interrupt for Compare Registers to CM7 There is an additional interrupt which is vectored to on a compare match in one of the eight comparators of the compare registers CMO to CM7 when compare mode 1 is selected for the corresponding channel assigned to Timer 2 by control bit CMSEL x For that purpose the SAB 80C517A provides eight interrupt request flags in SFR IRCON1 address 0D1H which ORed to form the interrupt request for that vector i e each of the eight comparators has its own request flag Thus the service routine may decide which compare match requested the interrupt The corresponding request flag is set by every match in the compare channel when the Compare Mode 1 is selected for this channel assigned to Timer 2 If Compare Mode 0 is selected for a channel assigned to the Compare Timer the corresponding interrupt request flag will not be set on a compare match This interrupt is enabled by setting the enable bit ECMP in SFR IEN2 If this bit is set the program vectors to location if one of the eight request fla
113. this case after power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 microseconds In the following the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on chip oscillator s output This allows correct resetting of the part and brings also all ports to the defined state see figure 4 4 I The time period from power on till reaching the reset state at the ports adds from the following terms RC oscillator start up lt 2us synchronization of the RC oscillators divider by 5 lt 6T synchronization of the state and cycle counters lt 6T reset procedure till correct port states are reached lt 12T Delay between power on and correct reset state 18 us Max 34 us Semiconductor Group 4 8 SIEMENS System Reset After the on chip oscillator finally has started the oscillator watchdog detects the correct function then the watchdog still holds the reset active for a time period of 768 cycles of the RC oscillator in order to allow the oscillation of the on chip oscillator to stabilize figure 4 4 Subsequently the clock is supplied by the on chip oscillator and the oscillator
114. ud 562 5 kBaud derived 2 Timer 1 10 Bit 10 Bit from Baudrate Baudrate Generator Generator Semiconductor Group 7 54 SIEMENS Device Specification Serial Interface 0 Serial Interface 0 can operate in 4 modes Mode 0 Shift register mode Serial data enters and exits through R x DO T x DO outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at 1 12 of the oscillator frequency Mode 1 8 bit UART variable baud rate 10 bit are transmitted through T x DO or received through R x DO a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit goes into 80 in special function register SOCON The baud rate is variable Mode 2 9 bit UART fixed baud rate 11 bit are transmitted through T x DO or received through R x DO a start bit 0 8 data bits LSB first a programmable 9th and a stop bit 1 On transmission the 9th data bit TB80 in SOCON can be assigned to the value of 0 or 1 For example the parity bit in the PSW could be moved into TB80 or a second stop bit by setting TB80 to 1 On reception the 9th data bit goes into RB80 in special function register SOCON while the stop bit is ignored The baud rate is programmable to either 1 32 or 1 64 of the oscillator frequency Mode 3 9 UART variable baud rate 11 bit are transmitted through T x DO or received through R x DO a start bit 0 8 data bits LSB first a program
115. used as l O Port Semiconductor Group 3 12 SIEMENS Memory Organization Port 0 Address Data XRAM Write 1 0 Data to Port 2 gt 1 0 Data 02114 Figure 3 4 Use of Port 2 as l O Port At a write to Port 2 XRAM address in XPAGE register will be overwritten because of the concurrent write to Port 2 and XPAGE register So whenever XRAM is used and the XRAM address differs from the byte written to Port 2 latch it is absolutely nessesary to rewrite XPAGE with page address Example l O Data at Port 2 shall be OAAH A Byte shall be fetched from XRAM at address 8 MOV 30H MOV P2 0AAH P2 shows MOV XPAGE 0F8H P2 still shows but XRAM is addressed MOVX A RO the contents of XRAM at 8 is moved to accu Semiconductor Group 3 13 SIEMENS Memory Organization The register XPAGE provides the upper address byte for accesses to XRAM with MOVX Ri instructions If the address formed from XPAGE and Ri is less than the XRAM address range then an external access is performed For the SAB 80C517A the contents of XPAGE must be greater or equal than F84 in order to use the XRAM Of course the XRAM must be enabled if it shall be used with MOVX Ri instructions Thus the register XPAGE is used for addressing of the XRAM additionally its contents are used for generating the internal XRAM select If the co
116. used for the Concurrent Compare Output at P5 In this compare mode 2 the P5 pins are no longer general purpose pins or under control of compare capture register but under control of the new compare registers COMSET COMCLR These both 16 bit registers are always associated with Timer 2 same as CRC CC1 to CC4 Each of these registers consists of two 8 bit portions COMSET consists of COMSETL address 0A1 4 and COMSETH address 2 COMCLR consists of COMCLRL address 0A34 and COMCLRH address 0 4 In compare mode 2 the concurrent compare output pins on Port 5 are used as follows see figure 5 3 When compare match occurs with register COMSET high level appears at the pins of port 5 whose corresponding bits in the mask register SETMSK address 5 are set When a compare match occurs in register COMCLR a low level appears at the pins of port 5 whose corresponding bits in the mask register CLRMSK address 0A6p are set Additionally the Port 5 pins used for compare mode 2 may also be directly written to by write instructions to SFR P5 Of course the pins can also be read under program control If compare mode 2 shall be selected register CC4 must operate in compare mode 1 with the corresponding output pin P1 4 thus compare mode 2 is selected by enabling compare function for register CC4 COCAH4 1 4 0 SFR CCAEN by programming bits COCOENO and in SFR CCAE
117. verwritten by the new value Accesses to XRAM using the DPTR There are a Read and a Write instruction from and to XRAM which use one of the 16 bit DPTR for indirect addressing The instructions are MOVX A QDPTR Read MOVX DPTR A_ Write Normally the use of these instructions would use a physically external memory However in the SAB 80C517A the XRAM is accessed if it is enabled and if the DPTR points to the XRAM address space gt F800j Semiconductor Group 3 9 SIEMENS Memory Organization Accesses to XRAM using the Registers RO R1 The 8051 architecture provides also instructions for access to external data memory range which use only an 8 bit address indirect addressing with registers RO or R1 The instructions are MOVX Read MOVX Ri A Write In application systems either a real 8 bit bus with 8 bit address is used or Port 2 serves as page register which selects pages of 256 Byte However the distinction whether Port 2 is used as general purpose l 0 or as page address is made by the external system design From the device s point of view it cannot be decided whether the Port 2 data is used externally as address or as 1 0 data Hence a special page register is implemented into the SAB 80C517A to provide the possibility of accessing the XRAM also with the MOVX Ri instructions i e XPAGE serves the same function for the XRAM as Port 2 for external data memory Special Function Register
118. x D1 a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit goes into RB81 in special function register S1CON Variable Baud Rates for Serial Interface 1 Variable baud rates for modes A and B of serial interface 1 are derived from a dedicated baud rate generator The baud rate clock baud rate ee is generated by an 10 bit free running timer with programmable reload register 8 fosc Mode A B baudrate 32 2 10 SREL Semiconductor Group 7 56 SIEMENS Device Specification Watchdog Units The SAB 80C517A offers two enhanced fail safe mechanisms which allow an automatic recovery from hardware failure or software upset programmable watchdog timer WDT variable from 512 us up to appr 1 1 s time out period 12 MHz Upward compatible to SAB 80515 watchdog oscillator watchdog OWD monitors the on chip oscillator and forces the micro controller into reset state in case the on chip oscillator fails controls the restart from the Hardware Power Down Mode and provides clock for a fast internal reset after power on Programmable Watchdog Timer The WDT can be activated by hardware or software Hardware initialization is done when pin PE SWD Pin 4 is held high during RESET The SAB 80C517A then starts program execution with the WDT running Since Pin PE SWD is only sampled during Reset and hardware power down at parts with stepping code AD and later dynamical switching of

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