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AGILE and ACTIVE Cube

1. 350 Integrator b b i i 351 Differentiator b 360 Absolute value function E E b E 361 SQR I1 96 b 96 96 362 Cube I1 b E 96 363 Square root x s b 364 Modulo b 370 P controller b 9o i 371 PI Controller ms b i i 372 PI Controller s b i i 373 PD T1 Controller ms b i i 374 PID T1 controller ms 96 b i i 375 PID T1 controller s b i 380 PT1 element b b i 381 Time average b a E 382 Ramp limitation b b i 383 Spike filter b b 390 Analog multiplexer b b 391 Mi changeover 5 Analog multiplexer for 392 position values data Pos Pos b b Pos Pos Pos Pos set number Analog changeover 393 switch for position val Pos Pos Pos Pos Pos Pos ues Writing frequency pa 401 rametere yo b b b b b i i 402 s current parame 96 b b b b b i i _ Write voltage parame 5 k 403 ter eff yo b b b b b i i Write voltage parame 404 ter peak Yo b b b b b i i 405 E percent parame 96 b b b b b i i 406 ua position parame p s Pog b b i i 407 Write long parameter b b b b i i 408 Write word parameter int b b b b b i i _ Read frequency para i 4
2. 1 AND Input 1 Input 2 Input 3 Input 4 2 OR Input 1 Input 2 Input 3 Input 4 3 XOR 71 Input 1 Input 2 Input 3 Input 4 4 XOR 1 3 Input 1 Input 2 Input 3 Input 4 Superior 10 RS Flip Flop Superior Set Reset Superior Set Reset _ Toggle Flip Flop Supe J s Superior 20 rior Input Input Superior Set Reset 30 D Flip Flop Superior Clock input C Data input D Superior Set Ta _ Delay Superior retrig y Superior 4x gerable Input Superior Set Reset _ Delay Superior non ae Superior 5x retriggerable Input Superior Set Reset _ Monoflop Superior re Ww Superior 6x triggerable Input Input Superior Set Reset Monoflop Superior non ar Superior 7x retriggerable Input Input Superior Set Reset 8x Clock generator Superior Input Input Superior Set n 90 Digital multiplexer Input 1 Input 2 Input 3 Input 4 91 Dataset changeover Input 1 Input 2 Input 3 Input 4 95 Triggering of an error Trigger Trigger Trigger Trigger 96 Acknowledging an error Acknowledge Acknowledge z E 97 Debouncer Input Master Set Master Reset 99 NOP i Activate jump Update input Update out 100 Jump function function Jump target buffer put buffer p p Update input Update out 101 Jump function for loops Finish loop Restart loop buffer put buffer 110 RS Flip Flop Master Set Reset Master Set Master Reset
3. Description The input value at I1 is differentiated The derivative action time indicates how long a linear ramp must rise until it has the same value as the output of the differentiator Orono pine dt If an integrator and a differentiator are connected in series a p element is obtained with ampli fication V 2 Td Ti If for example the output value is limited in the case of a jump at the input the limited value will be output longer In the case of a jump at the input the jump height sampling time is assumed as the ramp gra dient As long as status TRUE is present at I4 Master Reset the output value O1 is 0 Note Percentages 96 have two decimals For example Value 12345 123 45 1 2345 5 3 10 360 Absolute value function Input value O1 I H inverted output 1 Master Reset Description The absolute value of the input value at I1 is calculated The output value at O1 is always posi tive O1 02 r1 As long as status TRUE is present at I4 Master Reset the output value O1 is 0 08 10 VPLC PLC 99 Bonfiglioli Vectron Note Percentages 96 have two decimals For example Value 12345m 123 45 1 2345 5 3 11 361 X2 SQR I1 Input value 01 I1 inverted output 1 Master Reset Limitation of output value Description The input value at I1 is squar
4. eeesessssss 80 ose 36 POSILIODSS 1 22 nente iore itan 81 digital ine irt i tis eres 35 Window comparator Installation sinuca erana 8 Constant Variable 84 Instructions Variables eee 83 OVET NEW sis eane ae erit cick cres ce Evi Eve SER 28 Controlling digital output 44 Integrator ze iere e reden 97 COUNTErS s feet sects cet neuer e 118 119 J ero TTT 99 Jump function sce 48 75 Current parameter tor dOODSiussce n terere ases Quee t etis dius 76 read scio ceci be cond eva 115 Jump target WEG 4 ono idet een Seer E ee Doer 112 Chronological behavior 48 D L DebOUhCeL uie eei ager taa 74 Limiter Dr REN 48 CONSTAN eoi eie nien 117 160 VPLC PLC 08 10 Bonfiglioli Vectron Variable sii in iei a E as tote 118 WIIUG 22 eoe PI Rev E 113 List of parameters 154 position Long parameter FOG eie eet retia 116 gc 117 Mini 113 WILE Sissi tens tition 114 voltage eff M Gad cie esent aae ede 116 Mainternarice i rre eere aaa 9 WIIte rem tte 112 Maste vevecivors vesesseegstvosbeesssantteen tesitans 47 voltage peak Mathematical functions 89 FEAG i cia edet Id d teri Meses 116 IDNAUTE 86 WIILG Leo eere crea itte eren 113 Min Max word for position values 87 ead saccis iva tires eu deve vete 117 for positions in time window
5. For PLC signal Fixed General Value of the input buffer values without physical unit can be en tered The setting range is 327 68 327 68 08 10 VPLC PLC 27 Bonfiglioli Vectron 3 Overview of instructions C is a configurable constant value V is a variable input value P1 and P2 are input fields in the function block setup for adapting the function to the appli cation Digital functions 0 Off last table item Return jump to Instruction 1 in Index 1 Last function processed in function table See chapter 2 1 Boolean operations Digital functions 1 AND Up to 4 inputs are AND combined with one another Output is TRUE if all inputs are TRUE See chapter 0 2 OR Up to 4 inputs are OR combined with one another Output is logic TRUE if at least one input is TRUE See chapter 4 3 2 37 ORGY put is TRUE only if exactly one input is TRUE See chapter 4 3 3 4 XOR 1 3 Up to 4 inputs are EXCLUSIVE OR combined with one another Out Up to 4 inputs are EXCLUSIVE OR combined with one another The output is TRUE if TRUE is present on an odd number of inputs The output is FALSE if TRUE is present on a straight number of inputs See chapter 4 3 4 Flip Flop types Digital functions Input 1 Set TRUE sets output to TRUE Input 2 Reset TRUE sets output to FALSE 10 RS Flip Flop Input 3 Superior Set TRUE
6. 88 dir 114 in time window eeeeeeeees 87 PD T1 controller 103 Modulo citatis 100 Percent parameter MONOflOp RET EN 48 redd ich aane 116 Master cep a TEE 113 non retriggerable 68 PI controller retriggerable sss 66 Tn in milliseconds 102 Superior Tn in seconds eeeseeeenee 102 non retriggerable 67 PID T1 controller retriggerable ss 65 Tn in milliseconds 103 Motion block Tn in seconds sessesee 104 COMUMUC eee aati Ente neon Du 123 Position parameter K LITE 123 116 SLOP irat eer aa 122 icm 113 Multiplexer Positioning functions 120 analogie ic ter eta ee 109 motion block digital aissis HIER 71 continue eeeeeeeee nenne nenne 123 position values esss 110 feSulie c ee pee tenir ive er RR 123 Multiplication eeeeseseeeses 91 Start homing eeneee 124 and division eeeee 95 Start motion block as single motion 121 by fraction eee Cerere neni 92 Start motion block in automatic mode 122 Eong result 5 inicie 91 Stop motion block 122 Lorig percent 1 retento 92 PT1 element nece 106
7. Pos tion High word lb Release E b Wait until motion block I is finished Description Stopped motion blocks will be continued The function is only executed if input I3 release is set If input I4 wait is set further instructions will only be processed when the motion block in cluding repetitions if applicable or automatic sequence of motion blocks is finished The process cannot be stopped by other instructions or resetting I3 504 O1 I3 Enable I4 Wait 02 I3 I4 Function 1 0 Continue stopped motion block 1 1 Wait until the end of the motion block or the automatic se quence 5 10 5 505 Resume motion block Wait until motion block is finished Description Motion blocks stopped by error cut off or mains off will be continued The function is only executed if input I3 release is set Pos Actual posi Pos tion Low word High word 124 VPLC PLC 08 10 Bonfiglioli Vectron If input I4 wait is set further instructions will only be processed when the motion block in cluding repetitions if applicable or automatic sequence of motion blocks is finished The process cannot be stopped by other instructions or resetting I3 505 O1 I3 Enable I4 Wait 02 I3 I4 Function 1 0 Resume Motion Block 1 1 Wait until the end of the motion block or the automatic se quence
8. S3IND 21 S4IND S5IND Function Table Input Buffer Index 1 Index2 Index3 Index4 Index5 FT input buffer 1362 70 7 72 73 74 Inverter Release S2IND S3IND S4IND S5IND Function Table Index 1 Index 2 Index 3 FT instruction 1343 2 OR 1 AND 3 XOR 1 FT input 1 1344 2002 2001 2102 FT input 2 1345 2003 2101 2004 FT input 3 1346 2005 FT input 4 1347 FT output 1 1350 FT output 1 1351 142 VPLC PLC 08 10 Bonfiglioli Vectron 7 Actual values output signals and messages 7 1 Actual values of digital functions Actual values of input and output buffers The actual values of the global outputs 2401 to 2416 PLC output buffer are indicated by parameter PLC actual values output buffer 1357 The actual values of the global inputs 2001 to 2016 PLC input buffer are indicated by parameter PLC actual values input buffer 1358 Example e g display AET E MITT n um Ac Ecc es pur d ran ae i 2 3 4 5 67 8 9 10 11 12 13 14 15 16 FALSE TRUE In the example the following is TRUE 2405 PLC output buffer 5 2407 PLC output buffer 7 2409 PLC output buffer 9 2410 PLC output buffer 10 2411 PLC output buffer 11 2412 PLC output buffer 12 2414 PLC output buffer 14 08 10 VPLC PLC 143 Bonfiglioli Vectron Actual values of digital instructions The actual values o
9. Description I1 bitwise shifted by P2 sign bit is maintained inverted output Number of shifts OxFOOF 0x7807 The input value at I1 is shifted to the right bitwise by the number of shifts P2 The most sig nificant bit sign bit is maintained Master Set sets all bits of the output value Output OxFFFF Master Reset deletes all bits of the output value Output 0x0000 Example P2 I1 O1 02 1 1 One shift OxFOOF OxF807 0x07F8 2 4 Four shifts OxOOFF 0x000F OxFFFO 3 8 Eight shifts OxFFOO OxFFFF 0x0000 In example 1 Ti 1 1 1 1 0000 0 00 01 1 1 1 OxFOOF 1x SHR ET Oi 0 0 1 1 1 1 00 00 00 00 1 1 1 1 0x7807 5 11 7 212 Bit shift left input value 1 I1 bitwise shifted by P2 inverted output ra Master Set Master Reset i Number of shifts Description The input value at I1 is shifted to the left bitwise by the number of shifts P2 Right side is filled with zeroes Master Set sets all bits of the output value Output OxFFFF Master Reset deletes all bits of the output value Output 0x0000 130 VPLC PLC 08 10 Bonfiglioli Vectron Example P2 I1 O1 02 1 1 One shift OxFOOF OxEOIE OxiFIl 2 4 Four shifts OxOOFF OxOFFO OxFOOF 3 8 Eight shifts OxFFOO 0x0000 OxFFFF In example 1
10. Instruction Motion Block P1 Homing Mode type 1130 5 10 6 506 Start homing Pos _ Actual posi Low word Pos tion High word b Release Homing Mode Wait until reference b position has been reached Description The homing operation defined in P1 is started Running motion blocks will be stopped Configuration 30 x40 The function is only executed if input I3 release is set If input I4 wait is set further instructions will only be processed when the reference position has been reached The process cannot be stopped by other instructions or resetting I3 506 O1 I3 Enable I4 Wait 02 I3 I4 Function 1 0 Start homing P1 1 1 Wait until reference position has been reached 5 10 7 507 Check state b TRUE if motion block running b FALSE if motion block run ning Wait until motion block is finished 08 10 VPLC PLC 125 Bonfiglioli Vectron Description The function sets output O1 to TRUE if a motion block is running If input I4 wait is set further instructions will only be processed when the motion block in cluding repetitions if applicable or automatic sequence of motion blocks is finished The process cannot be stopped by other instructions or resetting I3 Motion block is active O1 1 02 Motion block I4 O1 run
11. Note If output 1 is connected with input 1 faults are acknowledged automatically 08 10 VPLC PLC 73 Bonfiglioli Vectron 4 10 Debouncer 4 10 1 97 Debouncer input value 1 b Debounced input value 1 b inverted output O1 Master Set delay positive edge in ms Master Reset i delay negative edge in ms Description The input value will be forwarded to the output only if it has had a constant value for the confi gured delay The delay for the positive edge of the input signal can be set via P1 The delay for the negative edge of the input signal can be set via P2 I1 4 b O1 b Master Set TRUE at I3 sets O1 to TRUE Master Reset TRUE at I4 sets O1 to FALSE Master Reset has priority over Master Set O1 I3 I4 4 11 No operation 4 11 1 99 NOP no operation Description This function can be used as a placeholder if it is expected that function will be added to the programming later It does not carry out an operation 74 VPLC PLC 08 10 Bonfiglioli Vectron 4 12 Jump functions 4 12 1 100 Jump function Jump function active Jump target P1 P2 b Update input buffer Jump target P1 b Update output buffer i Jump target P2 Description This function enables jumps in the sequence of the instructions to other instructions Activation Input 1 activates the jump function Input 1 TR
12. n 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 OxFOOF 1x SHL Lp dd oi 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 OxEOIE 5 11 8 213 Bit roll right I1 bitwise shifted by P2 with 9o input value 1 bits r iriserted inverted output Ih Master Set Master Reset i Number of shifts Description The input value at I1 is shifted to the right bitwise by the number of shifts P2 On the left side the bits leaving on the right side will be inserted Master Set sets all bits of the output value Output OxFFFF Master Reset deletes all bits of the output value Output 0x0000 Note Rolling by 8 bits exchanges the most significant bit and least significant byte Rolling by 15 bits to the right corresponds to rolling by one bit to the left After rolling by 16 bits the output value at O1 is the same as the input value at I1 Example P2 I1 01 02 1 1 One shift OxFOOF OxF807 0x07F8 2 4 Four shifts OxOOFF OxFOOF OxOFFO 3 8 Eight shifts OxFFOO OxOOFF OxFFOO In example 1 I1 1 1 1 1 00 00 0 0 00 1 1 OxFOOF 1x Na Ww WO O1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 OxF807 input value 1 b One bit of I1 selected via P1 b inverted output B Master Set Number of bit 0 15 Master Reset a Description A
13. 97 5 3 8 350 Integrator eie E tte ent wi aa tren edere oam e UE Vau 98 5 3 9 351 Differentiator D element eeseeeeeeeeeeene nnne nmn nnne 99 5 3 10 360 Absolute value function ssseeeeeeeeee nennen nemen nnne nnns 99 5 3 11 36 LT X2 SQR GI etii een detecte n eee mec aree cured Nees teer uu 100 5 3 12 62 X3 Cube L1 5 ie esee eret ueteri oer eee E eee nea ED ERES 100 5 3 13 363 VX square root of TL acie coc c op tube nte date c Pad e doo 100 5 3 14 364 Modulo 55 ii iiio ti ean Gis cere tete ee rhe sa vecta core One Bla vas 101 BA Controller 3 dodenus tipos ce De ad eus v eo obA3 CONTE Een TEC QNAT EXRE DEO Y E RDAY CEU TA EUO 102 5 4 1 870 P controller noe cereo tne Ee te aree tras Cree LC Ex v RAE SEEN ER aa 102 5 4 2 371 PI controller Tn in milliseconds eeeeeeeenemm m 103 5 4 3 372 PI controller Tn in seconds eeeseeeeeenneenm enn 103 5 44 373 PD TL controller eiiis eter epn eco e rect etr tte t nete eon iie eaae sete 104 5 4 5 374 PID T1 controller Tn in milliseconds eeeeeeennes 104 5 4 6 375 PID T1 controller Tn in seconds eeeeeneemm me 105 LEX Filters eee M Ka 107 5 5 1 380 PT L elemerit 2i in ener tr eee ee e Mies RI ct Mr DRERR TUER dS 107 5 5 2 381 Time average pte UE ee En ode a ire tiae teed gas 107 5 5 3 382
14. I1 96 gt A 402 I2 Delete buffer 01 FT instruction 1343 I3 Write enable Parameter Parameter 02 5 7 1 3 403 Write voltage parameter eff 9o input value 1 b IL 90 H V b Delete buffer b inverted output 1 lb Write release Parameter number Wait until writing b is finished i Data set 0 9 or index Description The effective value at the input is converted from percent to V and written as int parameter It 90 H V 123 4596 123 45 V I1 96 gt V 403 I2 4 Delete buffer Ol FT instruction 1343 I3 Write enable Parameter Parameter 02 08 10 VPLC PLC 113 Bonfiglioli Vectron 5 7 1 4 9o input value 1 b Delete buffer b Write release Wait until writing is finished Description The peak value at the input is converted from percent to V and written as int parameter H 96 Ii V 123 4596 123 45 V I1 4 960 V I2 Delete buffer 404 Write voltage parameter peak b O1 96 gt O1 V b inverted output 1 Parameter number i Data set 0 9 or index O1 FT instruction 1343 Parameter I3 4 Write enable I4 1 Wait 5 7 1 5 9o input value 1 b Delete buffer b Write release Wait until writing is finished Description The input value is not changed and written as int parameter In this way this function can also 02 405 Write perc
15. 152 VPLC PLC 08 10 Bonfiglioli Vectron Initialization Initialization is a jump function with three targets For this reason 2 jump functions are re quired The initialization must start with index 1 because the function table always starts at index 1 after a restart No initiator FT instruction 1343 FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT Parameter 1 1348 FT Parameter 2 1349 FT instruction 1343 FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT Parameter 1 1348 FT Parameter 2 1349 100 Jump function 2004 Input buffer 4 6 TRUE 6 TRUE 6 TRUE Jump target state 5 No jump next step 100 Jump function 6 TRUE 2002 Input buffer 2 6 TRUE 6 TRUE Jump target state 3 Jump target state 2 Now all blocks are defined These blocks are entered in the table the placeholders are re placed by indices The states are marked in different colors Non relevant items are hidden FT instruction 1343 FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT Parameter 1 1348 FT Parameter 2 1349 FT Target Output 1 1350 FT Target Output 2 1351 FT Commentary 1352 FT instruction 1343 FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT Parameter 1 1348 FT Parameter 2 1349 FT Target Output 1 1350 FT Target Output 2 1351 FT Commentary 1352 Index 1 100 Jump function 2004 I
16. 220 O tp t One bit iiic rin err eee tree deere ren dre aaas 131 5 11 10 221 Unite four bits to form a word seeeeeeenen nnnm 132 5 11 11 222 Add two bits to a word eeeseeeeeeeeneneene nme 133 6 1 Write index and read index 1 ee sese seinen nenne nennen nnn nnn 134 6 1 1 Write index and read index for FT instructions eeeeeneennee 134 6 1 2 Write index and read index for the digital input buffer sssessssss 135 6 1 3 Write index and read index for the analog input buffer and FT fixed values 136 6 2 E a itc io bir CE Ea davai E LoEAR ERN FE eu RACER RA EERRE EE UR acess T 137 6 24 Example RUM StOp a odere eso reserva Ear ae Tak ya Da e dx Rao NERA E Te gni oa 138 6 3 Example 1 Combining two digital outputs 2 eese 138 6 4 Example 2 Combining several FT instructions eene 139 6 5 Example 3 Parameterization of logic diagram es 142 7 1 Actual values of digital functions eeeseeseee eee 143 7 2 Actual values of analog functions eeeeeeee eene nn 145 7 3 Signals for digital outputs of device 1 eere 146 7 4 Signals for analog outputs of device eese nnns 146 7 5 Signal sources for device function eeeeeeeeee eee 14
17. 5 9 Counters 014 5 9 1 450 Up Down counter with analog output Up counter DER Down counter ram Master Set Master Reset Description O1 counter I1 counter I2 inverted output 1 Steps up for 100 0096 Steps down for 100 0096 Each positive edge at I1 increases the output value O1 by 100 00 P1 Each positive edge at I2 reduces the output value O1 by 100 00 P2 The output value is limited to the range 0 00 100 0096 Master Set I3 sets the output to 100 0096 This input has priority over edges at 11 or I2 Master Reset 14 sets the output to 0 00 This input has priority over edges at I1 I2 and Master Set I3 VPLC PLC 119 Bonfiglioli Vectron 100 450 I1 Clock x ne O 1 7 9o O 1 s I3 MS 01 100 I4 MR O2 096 Possible applications Definition of reference values by means of two pushbuttons If one of the two buttons is pressed the reference value is to be raised or lowered by an adjustable amount Counting of error events With each event the counter counts up The counter can trigger other functions such as reporting errors occurring too often Example P1 6 P2 4 1 2 3 4 5 6 7 8 9 10 11 TURN noo E ELELELE Clock down i Master Set Master Reset A1 1 Master Reset sets output O1 to zero 2 Three counting pulses up each 100 00 P1 100
18. 9 zero PLC input buffer cur rent Selection 9 zero PLC input buffer per cent Selection 9 zero PLC input buffer vol tage Selection 9 zero SPS input buffer gen eral source 0 2147483647 Numerator general source input 1383 327 68 327 67 100 00 Denominator general source input 1383 0 01 327 67 100 00 Numerator general source output 2551 327 68 327 67 100 00 Denominator general source output 2551 0 01 327 67 100 00 PLC fixed frequency value 999 99 999 99 50 00 156 VPLC PLC 08 10 Bonfiglioli Vectron E Factory Chap No Description Unit Setting range setting ter 1389 m fixed current vat A Se es os 6 1 3 PLC fixed percent 1390 s Sion 327 67 327 67 100 00 6 1 3 PLC fixed voltage val 1391 E Tiked voltage val v 1000 0 1000 0 565 7 6 13 PLC fixed position l 2147483647 1392 wale units 2147483647 65536 6 1 3 PLC fixed speed value 2147483647 1393 tab pos u s 2147483647 163840 6 1 3 PLC fixed ramp value 2 1394 Ty MR u s 1 2147483647 327680 6 1 3 1395 v fixed general val 32767 32767 0 6 1 3 Numerator fixed gen i3gg Mumendtor fixed gen 327 68 327 67 100 6 1 3 eral value 1395 Denominator fixed E e Yo 0 01 327 67 100 6 1 3 1399 PLC RunMode
19. The output value comprises a High word O1 and a Low word O2 The positions offset which is added is also separated in High word and Low word As long as status TRUE is present at I4 Master Reset the output value is 0 Note Output value O2 is not the inverted value of O1 The output can be combined with inputs for position values Long The function can also be used for ramp settings in configurations x40 The availability of configuration x40 depends on the device series 08 10 VPLC PLC 91 Bonfiglioli Example I1 35468240 O 35468240 5613 27028 270000 I2 5613 35770881 I3 27028 221D201 hex P 270000 41EBOhex O1 D201 4 53761 Pi 1EB0 7856 O2 0221h 545 P2 0004hex 4 5 3 2 Multiplication 5 3 2 1 332 Multiplication input value 1 O1 I1xI2xP1 input value 2 inverted output 1 Factor numerator Master Reset Description This function multiplies inputs I1 by I2 and by factor P1 O1 0O2 I1xI2xP1 The result of the multiplication is limited to 327 6790 As long as status TRUE is present at I4 Master Reset the output value O1 is 0 Note 100 00 100 0096 100 0096 Example 11 3240 32 40 O1 32 40 3 58 270 0096 12 358 23 5896 0 324 0 0358 2 70 P1 270 270 00 0 0313 3 13 Note Percentages have two decimals For example Value 12345m 123 45 1 2345 5 3 2 2 333 Multiplication Long re
20. b b 9o 9o E i 220 output one bit b b b b i Unite four bits to form I 221 a word b b b b Yo yo i 222 Add two bits to a word b b b i i 301 Comp 2 inp b b b b X XxX 302 Comp 2 inp abs val b b b b 303 Comp inp with const z b b b b _ Comp inp with const i 5 304 abe val yo b b b b yo yo Comp active motion 308 block b b b b i i 309 Comp Position Pos Pos b b b b Pos Pos 310 Analog hysteresis b b 311 W comp 2V b b b b 312 W comp 2V abs val b b b b 313 W comp VC z b b b b 314 W comp VC abs val b b b b 320 Min Max b b Min Max for position 321 vales Pos Pos b b Pos Pos Pos Pos Min Max in time win i A I 322 iow Jo b b Yo Yo EA Max i UME Wie CE ay 6 Boss kBog RE dow for positions 330 Add with offset b 331 E POSINON iby et Pos Pos Pos b Pos Pos Pos Pos 332 Mult b 333 Mult with long result b 334 Mult with fraction z 2 b 335 Mult long with percent long b 336 Div b 337 Div by const 96 b 338 Reciprocal b 339 Mult amp Div b 340 Average b i i 341 LUN VAMP NESS ns Ir es td b 96 96 96 96 342 d value JONE b 36 VPLC PLC 08 10 Bonfiglioli Vectron
21. ccceeeeeecsseeeeesssseeeesesaeeeesesaeeeeeessaaeeeesaaaes 115 VPLC PLC 08 10 Bonfiglioli Vectron 57 2 R aditig parameters iiie eei nannaa Ed ben ead qe va ceed rne da ges canes Lata soa aSa 116 5 7 2 1 421 Read frequency parameter ccccsseceeeesseeeeessseeeeeseaaeeeeseaaeeeesenaaaes 116 5 7 2 2 422 Read current parameter cceececeeseeeeeeeseeeeesssaeeeeeeaaeeeessaaaeeeesnaaaes 116 5 7 2 3 423 Read voltage parameter eff seen 117 5 7 2 4 424 Read voltage parameter peak eeeeeeennen 117 5 7 2 5 425 Read percent parameter eeeseeeeeenenene nemen 117 5 7 2 6 426 Read position parameter esee 117 5 7 2 7 427 Read long parameter ccccssseeeecssseeeeceeeeeessaseeeeesaseaeensesaaeeesasages 118 5 7 2 8 428 Read word parameter ccceeeeeeeesseeeeeesaaeeeeessseeeeeesaeseeesssaaeeeesaaaes 118 E OMBE ETT CEPR TEITDIDIELILOLEBEITCTDINODE LU IU OIEI OE D DIE 118 5 81 440 Limiter Const 5 iori tere sage esee eto rete ee eoe eer ea en pepe ARE 118 5 8 2 441 Limiter variable sesseeeeeeeeee nennen nnne nnne 119 5 9 Counters M 119 5 9 1 450 Up Down counter with analog output sssssssssssssrssrsrrnssrrrnensnrrnnrerennsn 119 5 9 2 451 Stopwatch with analog output sssssssssssrssrrssnnsrrrsnntnrnnnnnnrnnnnnnnnnnnnnnns 120 5 10 Positioning func
22. eeeennennnnn 66 4 6 3 70 71 72 Monoflop non retriggerable Superior eese 67 4 6 4 170 171 172 Monoflop non retriggerable Master eeeeeeeee 68 4 6 5 80 81 82 Clock generator Superior eeeeeeenneenne menn 69 4 6 6 180 181 182 Clock generator Master eee 70 4 7 Digital multiplexer 11 eeoiee eene rere nenne nennen nnne nnnm nnn nnnm nnnm 71 4 7 1 90 Digital Multiplexer Data Set Number enm 71 SERE 71 4 8 1 91 Switch Data SQL oet reece e Pr en eren reci ediad kaia 71 4 9 Error functions 1 eecieeee seien nene nennen Aaaa anapa annu aua nu uana sana auam uana unn 72 4 9 1 95 Triggering Of an error eee nn rre nr nentur ee 72 4 9 2 96 Acknowledging an error eeeeeeeenemmmH eem 73 410 DeboUncer ieesiceseueusav o i nud LE oaa ara y cann LC NE CEU RAO UER CERE RARO RA ERE RX MES aaia NO RRKRENIYR 74 40 1 T97 DebOUllICer e eor otio an ooa ee trs ey ok oso riens euet e Et A EDESTEN aA 74 4 11 Nooperation 1 ec onere enin neen enne nennen nnne nn anu nnam anam nanus aan nana a unn nnn 74 4 11 1 99 NOP no operation eneeeeeeeneenenn nennen nnne nnne n nnn 74 4 12 Jump functions 11eee isis pinnana inamaana nnne nna nun annu nhan u hun a ana auum ana nnn 75 4 2 1 100 Jum
23. I2 P1 O1 remains unchanged Range 3 I1 I2 P2 O1 FALSE 02 Ol The output value can be changed by means of the two Boolean inputs Master Set sets output O1 to TRUE Master Reset sets output O1 to FALSE Master Reset has priority over Master Set 309 I1 gt I2 P1 I1 gt 12 P1 82 VPLC PLC 08 10 Bonfiglioli Vectron 5 2 5 310 Analog hysteresis Input value b Output Variable hysteresis b O1 inverted lb Start Constant hysteresis Master Reset Description Signal status controlled at I3 saves actual value at I1 The hysteresis values I2 variable and P1 constant are added to and subtracted from the saved value If the value of I1 is within the hysteresis the saved value is output If the value of I1 is outside of the hysteresis the current value of I1 is output If the start input I3 is set the input value I1 is maintained F I1 I1 gt F 12 P1 gt 01 I1 I1 lt F 12 Pi gt 01 T1 F I2 P1 lt I1 lt F 12 P1 gt 0O1 F Master Reset sets output O1 to FALSE If Master Reset is reset the process must be started again via I3 Output A f input E Output A f t A I3 Speichern gt t F 12 P1 12 P1 Ae X zu speichernder Ww F Wert E I2 P1 ae F 12 P1 3 O1 gespeicherter Wert I3 14 Function 1 0 Keep I1 at O1 constant X 1 Set O1 to FALSE Note Percent
24. Off Low state Representation of signal statuses in function descriptions On High state Representation of signal statuses in function descriptions 5 1 Behavior The behavior of the instructions can be set up via P1 and P2 The function of these parameters depends on the selected instruction Description Min Max 08 10 VPLC PLC 77 Bonfiglioli Vectron 5 2 Comparators 5 2 1 301 302 Comparator comparison of two variables Comparative b Output I1 gt I2 value 1 Comparative O1 inverted value 2 b Master Set positive hysteresis xxx xx b Master Reset negat hysteresis xxx xx Comparison of two variables Description This function compares inputs I1 and I2 O1 is TRUE if I1 I2 O1 is FALSE if I1 lt I2 If a hysteresis P1 and P2 is set up O1 is TRUE if T1 gt I2 P1 O1 is FALSE if I1 I2 P2 The comparator has three working ranges Range 1 I2 P1 I1 O1 TRUE Range 2 I2 P2 lt Il lt I2 P1 O1 remains unchanged Range 3 I1 I2 P2 O1 FALSE 02 O1 Description This function compares the absolute values of inputs I1 and 12 O1 is TRUE if I1 gt I2 O1 is FALSE if T1 lt I2 If a hysteresis P1 and P2 is set up O1 is TRUE if I1 gt I2 P1 O1 is FALSE if I1 lt I2 P2 The comparator has three working ranges Range 1 II2 P1 lt I1 O1 TRUE Range 2 II2 P2 lt
25. Selection 0 Stop 6 2 Setting range and factory settings depend on device type 08 10 VPLC PLC 157 Bonfiglioli Vectron 10 Annex 10 1 Mask Diagram for digital instructions of function table FT Eingangspuffer 1362 Index i Index2 Index3 Index4 Index5 Index6 Index7 Index8 Index9 Index 10 Indexii Indexi2 Indexi3 Index 14 Index 15 Index 16 Quelle 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 Werkseinstellung 70 ZA a B 7 76 7 7 7 160 161 162 163 7 7 j FU Freigabe S2IND S3IND S4IND S5IND S6IND MFI1D Aus Aus Aus Bereitmeldung Laufmeldung Stoermeldung Frequenzsollwert Aus Aus erreicht Ge nderte Einstellung E1 1344 Al E1 1344 AL 11344 A E1 1344 Al FT 1343 FT 1343 FT 1343 FT 1343 E2 1345 A1 1350 E2 1345 Ai 1350 E2 1345 A1 1350 E2 1345 A1 1350 E31346 P11348 ap E31346 P11348 42 E31346 P11348 a2 E31346 P11348 a2 E41347
26. eeeeeeee 116 in automatic mode 122 i MCuDTI EE 112 Statemachine eeeeeeneeee 147 write peak eeeennneeeee 113 Stopwatch with analog output 119 Ww Storage nente e rocher a 7 Window comparator SUPEO cione divs ee nro ra ex v e DRY YT DR rey age cd 47 variables eeeeeeeeeeeen een 83 Switch data set seesseeeeee 71 Window Comparator Switching time eeseseeees 58 Constant Variable 84 T Word parameter Time aVy ra geni pisinisi den ata 106 Bele E AE ATT 117 Timer functions eeeeeeee 65 gcn EUN 114 Toggle Flip Flop Write index Master nete emen 55 Analog input buffer 135 S TUjers o ee 54 Digital input buffer 134 Transport estet ERR Deis 7 FT instructions eesesse 133 Triggering of an error 72 X U gt ttis cette eee ute A 99 Unite four bits to form a word 131 E 99 Up Down counter with analog output 118 XOR 1 3 operation 51 V XOR 1 operatios iscissi 51 Voltage parameter read eff oret 116 162 VPLC PLC 08 10 5 Bonfiglioli power control and green solutions Bonfiglioli has been designing and developing innovative and reliable power transmission and control solutions for
27. peak Write percent The input value is not changed and written as int parameter See 405 parameter chapter 5 7 1 5 Write position The input value is not changed and written as long parameter See 406 parameter chapter 5 7 1 6 The input value is put together from of low word and high word not Write long pa 407 rameter changed and output as long parameter For use for any long parame ter types See chapter 5 7 1 7 Write word The input value is not changed and written as int parameter See 408 parameter chapter 5 7 1 8 Read frequency The function reads the value of the parameter set up in P1 Parame 421 parameter ter number and P2 Data set index The value is converted to a frequency value See chapter5 7 2 1 Read current The function reads the value of the parameter set up in P1 Parame 422 parameter ter number and P2 Data set index The value is converted to a current value See chapter5 7 2 2 Read voltage The function reads the value of the parameter set up in P1 Parame 423 parameter ter number and P2 Data set index The value is converted to a eff voltage value See chapter5 7 2 3 Read voltage The function reads the value of the parameter set up in P1 Parame 424 parameter ter number and P2 Data set index The value is converted to a peak voltage value See chapter5 7 2 4 Read percent The function reads the value of the parameter set up in P1 Parame 425 parameter ter number and P2 Data set inde
28. w wor Die Y ues and offset Result Long 02 High word 334 Multiplication of input value by Gi s cqui 327 6796 a constant fraction P2 Multiplication of long input uds 335 value by percentage divided 01 02 7 0 27 1 by a constant WM SUN x P1 Division of an input value by WU 299 variable input values E T mc p i 327 67 Division of input value by con It P2 1 02 337 stant CRE 327 67 Division of a constant by the P1 P2 O1 02 3m input value reciprocal n 327 67 ate e P1 339 il multiplication and Olsen ne p2 IVISION 327 67 Average from 3 input values m 340 Multiplication by constant frac 01 02 3 3 327 67 tion as correction factor Absolute value of two ortho i 341 gonal components Multiplica O1 02 VI1 12 x 327 67 tion by constant fraction Absolute value of three ortho pi 342 gonal components Multiplica 01 02 VI1 I2 I3 x 5 327 67 tion by constant fraction 350 Integrator O1 02 5 rit 12 327 67 351 Differentiator D element Ol 02 x ES 327 67 360 Absolute value function O1 O2 I1 327 67 eia P2 361 Input value squared 01 02 11 327 6794 pce P2 362 Input value cubed 01 02 11 327 67 H u gt 01 f O1 02 JI1 zs P2 f lue Jn 363 Square root of input value Hs i bo i 4327 6794 Modulo multiplication and 01 02 xPxPi Ol Ergebnis H eet division result with remainder i I3xP2 Q2 Rest
29. 140 00 40 00 P1 4000 40 00 1 4000 0 4000 350 009 limit 327 6796 Note Percentages 96 have two decimals For example Value 12345m 123 45 1 2345 If P1 is set to value 0 the output has the value 327 67 The sign is applied from the input value 5 3 3 3 338 Division P1 by I1 reciprocal Input denomina tor P1 COE inverted output 1 Constant numerator upper and lower limit O1 Master Reset Description The parameter value P1 is divided by the input value at I1 reciprocal The result of the division is limited to P2 max to 327 67 As long as status TRUE is present at I4 Master Reset the output value O1 is 0 Example 11214000 140 00 O1 40 00 140 0096 P1 4000 240 0096 0 4000 1 4000 28 57 Note Percentages have two decimals For example Value 12345m 123 45 1 2345 If I1 has value 0 output O1 has value 327 67 or the value of P2 08 10 VPLC PLC 95 Bonfiglioli 5 3 4 339 Multiplication and division Input numerator 1 Input numerator 2 Input denomina tor Master Reset x2 O1 I3 inverted output 1 upper limit lower limit Description The input value at I1 is multiplied by the input value at I2 and the result is divided by the input value at I3 O1 02 I1 x12 I3 The result of the division is limited
30. 2410 FT Output buffer 10 FT Target Output 2 1351 2401 FT Output buffer 1 FT Commentary 1352 Z4 2410 1 Z4 gt Z5 FT instruction 1343 FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT Parameter 1 1348 FT Parameter 2 1349 FT Target Output 1 1350 FT Target Output 2 1351 FT Commentary 1352 FT instruction 1343 FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT Parameter 1 1348 FT Parameter 2 1349 FT Target Output 1 1350 FT Target Output 2 1351 FT Commentary 1352 Index 11 2 OR 6 TRUE 7 FALSE 7 FALSE 7 FALSE 2401 FT Output buffer 1 2411 FT Output buffer 11 Z5 2401 1 Index 13 100 Jump function 2006 Input buffer 6 6 TRUE 6 TRUE 6 TRUE 3 Index 12 80 Clock generator 2003 Input buffer 3 7 FALSE 7 FALSE 7 FALSE 100 100 2404 FT Output buffer 4 Z5a clock Index 14 100 Jump function 6 TRUE 2003 Input buffer 3 6 TRUE 6 TRUE 12 13 Z5 Z2 154 VPLC PLC 08 10 Bonfiglioli 9 List of parameters The parameter list is structured according to the menu branches of the control unit The para meters are listed in ascending numerical order A headline shaded can appear several times i e a subject area may be listed at different places in the table For better clarity the parame ters have been marked with pictograms The parameter is available in the
31. Bonfiglioli Vectron AGILE and ACTIVE Cube Application manual PLC I Bonfiglioli ontrol and gre Bonfiglioli Vectron General Information about the Documentation This application manual complements the Operating Instructions and the Quick Start Guide of the frequency inverter The application manual contains all information relevant to creating PLC functions using the graphical programming environment or the function table For better clarity the documentation is structured according to the customer specific require ments made on the frequency inverter Quick Start Guide The Quick Start Guide describes the basic steps required for mechanical and electrical installa tion of the frequency inverter The guided commissioning supports you in the selection of ne cessary parameters and the software configuration of the frequency inverter Operating instructions The operating instructions describe and document all functions of the frequency inverter The parameters required for adapting the frequency inverter to specific applications as well as the wide range of additional functions are described in detail Application Manual The application manual supplements the documentation for purposeful installation and commis sioning of the frequency inverter Information on various subjects connected with the use of the frequency inverter are described specific to the application Installation Instructions Complementing
32. Check state the output indicates if a motion block is running Note The Positioning user manual describes the positioning functions in configurations x40 08 10 VPLC PLC 121 Bonfiglioli Vectron 5 10 1 501 Start motion block as single motion Target position offset Pos Actual posi Low word tion High word EN Number of motion block Release index motion block ta ble b Wait until positioning is 3 finished Description The motion block selected with P1 is started Repetitions and next motion blocks are not ex ecuted If a motion block is still running it will be stopped The position value set at input I1 target position offset is added to the target position set in the motion block Instruction Motion Block P1 t Index Target Position I1 i Target Position Distance 1202 Input I1 can be combined with position values long The function is only executed if input I3 release is set If input I4 wait is set further instructions will only be processed when the target position has been reached The process cannot be stopped by other instructions or resetting I3 501 I1 Pos Offset O1 I3 Enable I4 Wait 02 P1 Index Motion blocks table I3 I4 Function 1 0 Start motion block P1 Stopping by other instruction is possible The target posi tion can be changed by other instructions even if the target position has not be
33. I1 lt I2 P1 O1 remains unchanged Range 3 I1 lt II2 P2 O1 FALSE 02 O1 The output value can be changed by means of the two Boolean inputs I3 and 14 Master Set sets output O1 to TRUE Master Reset sets output O1 to FALSE Master Reset has priority over Master Set 301 11 gt 12 P1 it 302 I1 gt 12 P1 O1 I2 I3 02 14 78 VPLC PLC 08 10 Bonfiglioli Vectron Note This function compares inputs I1 and I2 Percentages 96 have two decimals For example Value 12345m 123 4596 1 2345 5 2 2 303 304 Comparator comparison of constant to variable 9o Comparative value 1 Output I1 gt P1 ib O1 inverted upper threshold xxx xx lower threshold xxx xx Master Set Master Reset b b 303 Comp input with constant 304 Comp input with constant abs value 303 Comp Description This function compares input I1 to the switching thresholds P1 and P2 O1 is TRUE if I1 gt P1 upper threshold O1 is FALSE if I1 P2 lower threshold O1 remains unchanged if I1 is in the range between P2 and P1 The comparator has three working ranges Range 1 P1 Il O1 TRUE Range 2 P2 lt I1 P1 O1 remains unchanged Range 3 I1 lt P2 O1 FALSE 02 Ol Special case P2 lower threshold is set higher than P1 upper threshold thresholds exchanged O1 is TRUE if I1 gt P1 O1 will be reset if P1 is deceeded again and P2
34. P1 Amplification P1 Reset time s P2 Rate time ms Index n 1 Index n P1 I1 I2 01 02 PiQ4x Hu44 D44 4 m J I 4 124 4 dt P144 xP2n ina Pa n e Set amplification in P controller e Set integral time and derivative action time in PID controller Note If the amplification of the PID controller is to be 1 no P controller must be connected in series If a value of 100 0096 is applied to the input in the form of a jump the output value is the total of the three components P component 100 0096 constant I component Ramp reaching the value of 100 00 after integral time P1 D component Pulse of length of a sampling step and level FE 100 T1 Abtastzeit If the pulse level exceeds the limitation of the output value the pulse will be output longer The output value is limited to the value at input I3 The input can be combined with a fixed value for example As long as status TRUE is present at 14 Master Reset the output value O1 and the I compo nent are 0 Note Percentages have two decimals For example Value 12345 123 45 1 2345 106 VPLC PLC 08 10 Bonfiglioli Vectron 5 5 Filters 5 5 1 380 PT1 element t 96 Input value O1 I1x 1 e Pi Start value inverted output 1 Master Set Filter time constant in ms b Master Reset Description The input value at 11 is filtered t O1 02 Iix 1 e P
35. P21349 521351 E41347 P21349 921354 E41347 P21349 921351 E41347 P21349 921354 E11344 Al 11344 AL E11344 Al E1 1344 Al FT 1343 FT 1343 FT 1343 FT 1343 E2 1345 A1 1350 E2 1345 A1 1350 E2 1345 A1 1350 E2 1345 A1 1350 E31346 P11348 42 E31346 P11348 42 E31346 P11348 ap E31346 P11348 42 E41347 P21349 921351 E41347 P21349 9213514 E41347 P21349 921351 E41347 P21349 921354 E11344 Al E1 1344 Al E11344 A E1 1344 Al FT 1343 FT 1343 FT 1343 FT 1343 E2 1345 A1 1350 E2 1345 A1 1350 E2 1345 A1 1350 E2 1345 A1 1350 E31346 P11348 ap E31346 P11348 42 E31346 P11348 ap E31346 P11348 42 E41347 P21349 921351 E41347 P21349 921351 E41347 P21349 421351 E41347 P21349 421351 E11344 Al 11344 AL 11344 Al E1 1344 Al FT 1343 FT 1343 FT 1343 FT 1343 E2 1345 A1 1350 E2 1345 A1 1350 E2 1345 A1 1350 E2 1345 A1 1350 E31346 P11348 ap E31346 P11348 42 E31346 P11348 a2 E31346 P11348 a2 E41347 P21349 921351 E41347 P21349 921354 E41347 P21349 921351 E41347 P21349 921354 E11344 Al E1 1344 AL 11344 ____ A E1 1344 Al FT 1343 FT 1343 FT 1343 FT 1343 E2 1345 A1 1350 E2 1345 A1 1350 E2 1345 A1 1350 E2 1345 A1 1350 E31346 P11348 ap E31346 P11348 42 E31346 P11348 42 E31346 P11348 42 E41347 P21349 921351 E41347 P21349 921354 E41347 P21349 921351 E41347 P21349 921354 11344 Al 11344 AL 11344 ____ Al 11344 AL FT 1343 FT 1343 FT 1343 FT 1343 E2 1345 A1 1350 E2
36. Ramp limitation sseeseseeeeeennnee nennen nennen nnne 108 5 5 4 383 Spike filter average of three eeseeeeeeeneennnm mn 109 5 6 Analog switch eeesseseeeeeeeee ee neeeeee ennemi i nutari nn iaia 110 5 6 1 390 Analog multiplexer data set number eene 110 5 6 2 391 Analog changeover SWItCN eeeeeeee cece eee eeeeeeeeeeeeaeeaeaaaaaeeeeseeeeeaaea 110 5 6 3 392 MUX for position values data set number Multiplexer 111 5 6 4 393 Changeover switch for position values Long eeeeeeeess 111 5 7 Parameter access 1ensessesiesseen snae na saa ea ena u nau u aua uaa u Rad 4 agua R Rau RR Ra Run 112 5 7 l Writing parameters notieren teneri ree Dn ee ae seed ra Date r ed parturi naa 112 5 7 1 1 401 Write frequency parameter eeeeeeennnm m 112 5 7 1 2 402 Write current parameter eeeeeeeennnene mmm 113 5 7 1 3 403 Write voltage parameter eff eere 113 5 7 1 4 404 Write voltage parameter peak eee 114 5 7 1 5 405 Write percentage parameter eeeeeeenm mme 114 5 7 1 6 406 Write position parameter eeeeeeeennnenmmemmenn 114 5 7 1 7 407 Write long parameter eeeeeennnennnmmmm mnn 115 5 7 1 8 408 Write word parameter
37. The output value can be changed by means of the two Boolean inputs I3 and 14 Master Set sets output O1 to TRUE Master Reset sets output O1 to FALSE Master Reset has priority over Master Set 311 I2 P2 lt I1 lt I2 P1 I1 312 I2 P2 lt I1 lt 12 P1 O1 I2 I3 02 14 84 VPLC PLC 08 10 Bonfiglioli Vectron Note Percentages 96 have two decimals For example Value 12345 123 45 1 2345 5 2 7 313 314 Window comparator comparison of constant to variable Comparative value 1 Output I1 gt I2 ib O1 inverted positive window xxx xx negative window Xxxx xx Master Set Master Reset b 313 Window comparator V C comparison of variable to constant 314 Window comparator V C absolute value comparison of variable to constant 313 Window comparator V C Description Via P1 and P2 a value range window is adjusted and it is checked if I1 is within this constant range O1 is TRUE if T1 is in the range of from P2 to P1 O1 is FALSE if I1 is outside of this range The comparator has three working ranges Range 1 P1 I1 O1 FALSE Range 2 P2 I1 P1 O1 TRUE Range3 I1 lt P2 O1 FALSE 02 O1 Special case P2 negative window is greater than P1 positive window limits exchanged O1 is TRUE if I1 lt Pi or Ii gt P2 O1 is FALSE if I1 is in the range of from P1 to P2 window 08 10 VPLC PLC 85 Bonf
38. Update input buffer Update output buf fer Jump target index number of repetitions Description An instruction indicated as jump target in P1 is executed as often as indicated in P2 Via the inputs the loop can be stopped or restarted With P1 the jump target the instruction to be executed repeatedly is defined With P2 the number of repetitions is defined Die jump function can be at the end of a series of instructions to be processed repeatedly An internal counter is set to the value of P2 and counted down each time the instructions speci fied in P1 are called If input I1 is TRUE the loop is stopped before it is finished The jump is not executed and the internal counter is reset to the start value P2 If input I2 is TRUE the loop is restarted The jump is executed and the internal counter is reset to the start value P2 If input 3 is TRUE the input buffer is updated If input 4 is TRUE the output buffer is updated I1 I2 I3 14 Function 1 0 0 0 Stop reset to start value P2 0 1 0 O Restart reset to start value P2 0 0 1 0 Update input buffer 0 0 0 1 Update output buffer I2 restart has priority over I1 stop x P2 Counter 01010 FT instruction FT instruction FT instruction FT instruction FT instruction 1343 7 7 1343 1343 1343 101 Pi Jump target 1343 101 I1 Interrupt Al
39. s See chapter 4 6 5 Clock generator As in operation mode 80 the unit of the times set in P1 and P2 is 82 Superior min minutes min See chapter 4 6 5 Digital switches Digital functions Depending on the current data set the input values are forwarded to the output values Data set 1 Output 1 Input 1 90 Ded Mu Data set 2 Output 1 Input 2 Data set 3 Output 1 Input 3 Data set 4 Output 1 Input 4 See chapter 4 7 1 91 Dataset chan Switching over of data set depending on input signals See chapter geover 4 8 1 Error functions Digital functions _ Triggering of an error A user error is triggered via one of the inputs I1 I4 The behavior error cut off shut down emergency stop after triggering can be set up via P2 See chapter 4 9 1 Acknowledging an error Output 1 indicates if an acknowledgeable error message is present Via inputs I1 or I2 the error message can be acknowledged See chapter 4 9 2 Zero operation Digital functions 99 NOP Zero operation The function does not carry out an operation See chapter 4 11 1 08 10 VPLC PLC 29 Bonfiglioli Vectron Jump function Digital functions 100 Jump function Branching off to index table column See chapter 4 12 1 Jump function A function indicated as jump target in P1 is executed as often as 101 for loops indicated in P2 Via
40. the end of the cycle and is available in the global sources after that When the input buffer is updated the output buffer is updated and the cycle restarts By selective use of the jump function the input buffer and output buffer can be updated either separately or jointly This enables setting the output signals at certain times selected by the user during the processing 08 10 VPLC PLC 25 Bonfiglioli Vectron The output values of instructions can be saved in the following signal sources of the output buffer The signal sources 25xx can be used as input values by other instructions 2501 2504 Output frequency buffer number 1 4 2511 2514 Output current buffer number 1 4 2521 2524 Output percent buffer number 1 4 2531 2534 Output voltage buffer number 1 4 2551 2554 Output general value buffer number 1 4 2561 2564 Output flag buffer number 1 4 Input Settings analog Percent Voltage indicates index already in use 26 VPLC PLC 08 10 Bonfiglioli Vectron 2 8 1 Fixed analog values For the fixed values of the input buffer values for physical quantities can be entered 2601 2604 Fixed frequency values 2611 2614 2621 2624 2631 2644 2651 2654 r Input Settings analog PLC Signal 2601 Fixed val Freq 1 X Global Source Fixed val Freq 1 0 00
41. 1 or with negative clock edge at input 2 The time set in P1 is the On Time High and the time set in P2 is the ignore edge time Low The set on time starts again with each edge TRUE at the Superior Set input sets the output to TRUE TRUE at the Superior Reset input sets the output to FALSE Via the output buffer the output signal is globally available Inputs Superior Set and Superior Reset are connected in series with the function Levels on Monoflop inputs I1 and I2 As soon as the Superior Set or Superior Reset is reset the output is switched to the internally saved value I1 I2 I3 I4 O1 State o1 M M Ss SR Q x x x 1 O0 Off Superior x x 1 0 1 On Superior 021 x 0 0 L Pulse o1 x 021 0 0 L Pulse SR SS E Mjo E Mii lt gt lt gt 9 gt t1 t2 t t2 tl t2 Pi P2 on time ignore edge time 08 10 VPLC PLC 67 Bonfiglioli Vectron 4 6 4 170 171 172 Monoflop non retriggerable Master M Monoflop edge 1 b output O1 E M Monoflop edge 2 negated output O2 O1 2 Master Set input t On time High Master Reset input ignore edge time 170 ms 171 s or 172 min Description Output signal becomes TRUE with positive clock edge at input 1 or with negative clock edge at input 2 The time set in P1 is the On Time High and the time set in P2 is the ignore edge time Low The set on time starts again with each edge TRU
42. 120 Toggle Flip Flop Master Input Input Master Set Master Reset 130 D Flip Flop Master Clock input C Data inputD Master Set Master Reset 14x ius Master remigger Input Master Set Master Reset 15x Delay Master non Input Master Set Master Reset retriggerable 16x Fono nap Vester edu Input Input Master Set Master Reset gerable 17x Mononop Marter non Input Input Master Set Master Reset retriggerable 18x Clock generator Master Input Input Master Set Master Reset Note In instruction types 40 to 82 and 140 to 182 the x is used as a placeholder in the table The instruction types can be parameterized in three different time bases 0 milliseconds ms 1 seconds s 2 minutes min 08 10 VPLC PLC 35 Bonfiglioli Vectron 3 1 2 The analog functions use at least one analog input signal or output signal Depending on the instruction the inputs and outputs have different functions Inputs and outputs of analog functions 200 Bit NOT operation 9o b b 9o 9o 201 B AND NAND opera b b i 202 Bit OR NOR operation b b i MALLEM NE EE MERE NM 210 Bit shift right 96 b b 96 96 i _ Bit arithmetical shift I 211 right yo b b yo yo i 212 Bit shift left b b i 213 Bit roll right
43. 24 tir eren tte ein Exc ra i E Eoi tarea pea o s DR Ea reda en gna 14 2 2 13 Stopping the PLC ec eae e Assen ocak n AEO EO a araa ana ianei nainii 14 2 3 User CNViIrONnMe Nt cccceseceseeeeeeseeeeeeeeeeeeeeeaeeeaseeoeseeeeaseeneneeaeasesneseeaeaeananeeneneens 15 2 3 1 Tool bar and menu commands eects ee eee eee e eee ea nnne nnne nennen nn nnns 15 2 3 2 Other menu commands eeeeseeeeee eene nennen nenne nent nenne nen nnn ann nnn 16 piace 17 203 42 ODEA weet a a a E a a a a a aea A ANa 17 2 3 b Properties eee ATE OAOE ed OENE EEEE 17 2 3 6 Settings Inputs outputs and function bloOCK ssssssssssssssssssrrrssnrrirnsrrrrersrrrssnens 18 2 4 Starting the PLC functions sssssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn rn 21 2 5 Principle for digital functions input settings Boolean 21 2 6 Principle for analog functions eeeeeeeeseee esee 23 2 7 Input buffer and output buffer for digital signals 2 eeesss 25 2 8 Input buffer and output buffer for analog signals 25 28 1 FIXED ANALOG Valles iiti D ni eR e LE Gn ec E queda ta aX ea anaa Sani iaaii 27 3 1 Inputs and outputs 1neeesieeee seien eeeee nenne nane nnnm nnn nu annm nnam baup Runs EENT 35 3 1 1 Inputs of digital functions eee eee eee cece ee ee eee teeter reer esas saan eene 35 3 1 2 Inputs and ou
44. 4 Description Depending on the current data set the input values are forwarded to the outputs Parameter Active data set 249 shows the selected data set Active Dat c A1 clive Vata Ser249 2401 Ai 4 8 Switch 4 8 1 91 Switch Data Set Input 1 highest priority Ib Input 2 b Input3 Input 4 lowest priority Description A data set is selected via the input values Ii I2 I3 I4 Data Set 1 X X X 1 0 1 X X 2 0 0 1 X 3 0 0 0 1 4 0 0 0 0 Data set via contacts 08 10 VPLC PLC 71 Bonfiglioli Vectron 4 9 4 9 1 Error funct ions 95 Triggering of an error user error 1 user error 2 user error 3 Triggering user error 4 Shut down behavior Description If one of the inputs is TRUE the relevant user error is triggered The output stages are dis abled The error is not acknowledgeable as long the input remains TRUE The function can be used for example for stopping the drive by external events Via P1 the shut down behavior can be adjusted The error cut off can be effected immediately or the drive can be shut down first P1 0 No error cut off deactivated P1 1 Shut down and error cut off P1 2 Emergency stop and error cut off P1 3 Error cut off immediately Val Logic state Trig
45. 5a 10a restart timer t1 and t2 5a starts timer t1 9b is output after t1 referred to 9a 4b is output after time t2 6a to 8b repeated as from 2a Example 4 3 consecutive square pulse followed by positive edge On times and delays as in example 2 non retriggerable retriggerable da 036343 636303 da 03633 636279 ru ti t Processing as in example 3 Edge 5a Processing as in example 3 The last posi switches output High Edges 6a and tive edge 7a maintains the output sig 7a are filtered out due to the quick nals on High level succession 60 VPLC PLC 08 10 Bonfiglioli Vectron 4 5 1 40 41 42 Delay retriggerable Superior F edge b output O1 negated output O2 Ot Superior Set input On delay t1 Superior Reset input t Off delay t2 Description The positive edge at input 1 is transferred to the output after delay t1 the negative edge after delay t2 The delay time starts again with each edge TRUE at the Superior Set input sets the output to TRUE TRUE at the Superior Reset input sets the output to FALSE Via the output buffer the output signal is globally available Inputs Superior Set and Superior Reset are connected in series with the function Levels at in put I1 are processed internally As soon as the Superior Set or Superior Reset is reset the out put is switched to the internally saved value F I1 Ot r F SS s o State X x 1 0 Off Su
46. I2 Restart amp Reset to P2 P1 Jump target P2 Number of repetitions I3 Update input buffer Counter ONH A2 14 Update output buffer 76 VPLC PLC 08 10 Bonfiglioli Vectron 5 Description of analog functions In the following you will find explanations and examples of the individual analog functions The term analog function is defined as follows An analog function has at least one analog input or output value Other inputs are used as digi tal signal depending on the function If the function has an analog output value O1 the second output value O2 is the inverted negative value If the function has both analog and Boolean inputs the analog inputs are assigned the smaller ordinal numbers I1 analog I4 Boolean In the examples the standard links of the input buffer are used You can also parameterize other settings for the individual instructions Note In the case of some functions output O2 is not used as an inverted output but written with function specific values These functions are marked with Long for long variable In the descriptions the following abbreviations are used b Boolean TRUE FALSE 1 Bit Percentage with or without sign int unit 2 Byte 16 Bit L Long Variable of type long 4 byte 32 bits i Any number 0 Low state Representation of signal statuses in logic tables 1 High state Representation of signal statuses in logic tables
47. Installation eoeeeee eee eere nere nnne nennen nnnm nnn 8 1 6 Information on USC 1 ee seien eene aaa nnne nnne taara AaS annm ninaa anne annuus 9 1 6 1 Using external prOdUcts 1 cedere equipe vo ase eed ec eere ea eee IRE i ga 9 1 7 Maintenance and Service 1 ee ee eeeee esee nennen annnm annnm nhan nn nnn 9 EMEND LEODIIRME EIL 9 2 1 Chronological processing eeeeeesee esee 11 2 2 Creating a program with function blocks eere 12 pP EE Caddues E 12 2 2 2 Saving a flle eiecit toten ee e UR EE reap a ke Va Par eu uere a prva EOD TRIN ETE 12 2 2 3 Function block instruction eeeeeeeeeeeeennn nennen mnm nnne nnns 12 2 2 4 MEG idest oec eo sene exe IRE EE OE ERE REX UE EERSE e In p Oe Er ve Fre eO Era eO WENN SERVER TRY SET NERA 12 2 2 5 Digital input block eire rre agers irent tnn ta eren So rhe R eun ERR EIR 13 2 2 6 Analog input block sci cote nicer nea aret reet tere pere onera eia Fes a RR rH Rura edid 13 2 2 7 Digital output block erre rere tein n n nie na eaa re uin 13 2 2 8 A rialog Output block eon pene etai ed eere er aaa 14 2 2 9 AC ra a a a aa a aaa ead A a eaa ai taas 14 2 210 Syntax CHECK sissid annt neni te e tee ric ii pArA TAINA 14 2 2 11 Translation and download to frequency inverter eeeeeeeeeeeeee 14 2 2 12 Starting the PLC
48. OnE shifts P2 Left side is filled with zeroes See chapter 5 11 5 Bit arithmetical The input value at I1 is shifted to the right bitwise by the number of 211 shift right shifts P2 The most significant bit sign bit is maintained See chapter 5 11 6 212 Bit shift left The input value at I1 is shifted to the left bitwise by the number of shifts P2 Right side is filled with zeroes See chapter 5 11 7 The input value at I1 is shifted to the right bitwise by the number of 213 Bit roll right shifts P2 On the left side the bits leaving on the right side will be inserted See chapter 5 11 8 4 A selected bit of input value 1 is output at output 1 The bit is se 220 Output one bit jected via P1 See chapter 5 11 9 221 Unite four bits The state of input 1 is copied to the bit of the output specified via P1 to form a word the state of input 2 to the next bit etc See chapter5 11 10 222 Add two bits to The states at inputs I2 and I3 are inserted in certain bits of the input a word value 1 The bits are defined by P1 and P2 See chapter 5 11 11 Comparators Analog functions Comparator 2 Input values I1 and I2 are compared Via P1 and P2 a hysteresis can 301 inp be adjusted See chapter 5 2 1 COM iparator 2 Like operation mode 301 but the absolute values at inputs I1 and I2 302 inp absolute Value are compared See chapter 5 2 1 Comparator Two switching thresholds are adjusted If the upper threshold P1 is 303 inp
49. One of the values I1 I2 P1 or P2 is output Via I4 it is defined if an input value I1 I2 or a fixed value P1 P2 is output Via I3 it is defined if value 1 or 2 is output I3 14 I1 Ii O1 110 VPLC PLC 08 10 Bonfiglioli Vectron The input values and fixed values are selected according to the following table I3 14 O1 0 0 l 1 0 2 0 1 P1 1 1 P2 Note Percentages have two decimals For example Value 12345 123 45 1 2345 5 6 3 392 MUX for position values data set number Multiplexer Pos input value 1 Pos Low word input value 2 Pos Me leeta pr 14 High word input value 3 a Pos input value 4 E Description Depending on the active data set parameter active data set 249 one of the input values is output at the output Pos I1 Pos I2 O O2 Pos High word O1 Pos Low word Pos I3 Pos I4 Active data set 249 1 I1 2 I2 3 I3 4 I4 O 02 O1 High word Low word Note Output value O2 is not the inverted value of O1 The output can be combined with inputs for position values Long The function can also be used for ramp settings in configurations x40 The output has value 0 if an input combined with FALSE is selected by the active data set 5 6 4 393 Changeover switch for position values Long Pos input value 1 Low wo
50. SSDI 90 VPLC PLC 08 10 Bonfiglioli Vectron 5 3 1 Addition and subtraction 5 3 1 1 330 Add 01 02 11 12 I3 P1 P2 O1 11 12 I3 4 P1 P2 inverted output 1 positive offset negative offset positive input I1 positive input I2 ative input I3 Master Reset Description This function adds inputs I1 and I2 and subtracts input I3 In addition a positive and negative Offset can be defined via P1 and P2 respectively 0O1 0O2 11 12 I3 P1 P2 The result of the addition is limited to 327 67 Interim results are not limited As long as status TRUE is present at I4 Master Reset the output value at O1 is 0 Example 11 3240 32 40 O1 32 40 56 13 270 28 3 90 3 22 12 5613 56 13 181 07 I3 27028 270 28 P1 390 3 90 P2 322 3 22 Input for parameters e g 32 40 P2 390 Note Percentages have two decimals For example Value 12345m 123 45 1 2345 5 3 1 2 331 Addition position with offset positive input I1 Pos Low word rae 114 12 13 P positive input 12 Boe ie High word negative input I3 Pos T Low word Master Reset Pos postions SEP High word Description This function adds inputs T1 and I2 and subtracts input I3 In addition an offset can be speci fied 02 O1 I1 12 I3 P2 P1 O2 O1 High word Low word P2 P1 High word Low word
51. The filter time constant P1 indicates how long it takes in the case of a constant input value until the output value starting from zero reaches 63 of the input value Master Set TRUE sets the output to the start value The start value can be defined via input 12 Master Reset TRUE sets the output to 0 Master Reset has priority over Master Set O1 63 x I1 O1 Start value MS O1 I2 02 MR 01 0 P1 Filter time constant ms If the filter is to be stopped input 2 must be combined with the output and the Master Set in put I3 must be activated I2 01 I3 TRUE 380 Note Percentages 96 have two decimals For example Value 12345m 123 45 1 2345 5 5 2 381 Time average n Il Input value nu lioe Hasc Hs n n inverted output 1 Master Reset 08 10 VPLC PLC 107 Bonfiglioli Vectron Description The function determines the average value over a period of time The output value is up dated with each cycle Master Reset is FALSE The output value is the average of all input values since the last negative edge from Master Reset Master Reset is TRUE The output value is the same as the input value 01 02 n n I4 Ol 0 Average of I4 1 14 Note Percentages 96 have two decimals For example Value 12345m 123 45 1 2345 5 5 3 382 Ramp limitation Ili 2 _ Alet
52. VPLC PLC 65 Bonfiglioli Vectron 4 6 2 160 161 162 Monoflop retriggerable Master M Monoflop edge 1 b output O1 Sl M Monoflop edge 2 negated output O2 O1 ra Master Set input On time High Master Reset input ignore edge time 160 ms 161 s or 162 min Description Output signal becomes TRUE with positive clock edge at input 1 or with negative clock edge at input 2 The time set in P1 is the On Time High and the time set in P2 is the ignore edge time Low The set on time starts again with each edge TRUE at the Master Set input sets the output to TRUE TRUE at the Master Reset input sets the output to FALSE Via the output buffer the output signal is globally available Master Set and Master Reset are connected parallel with the function and change the state of the function as soon as the signal is present O1 01 M M Ms mR Q late x x X 1 0 Off Master X X 1 0 1 On Master 021 x 0 0 L Pulse o1 x 021 0 0 L Pulse on time ignore edge time 66 VPLC PLC 08 10 Bonfiglioli Vectron 4 6 3 70 71 72 Monoflop non retriggerable Superior M Monoflop edge 1 b output O1 ES M Monoflop edge 2 negated output O2 O1 ra Superior Set input On time High Superior Reset input ignore edge time 70 ms 71 s or 72 min Description Output signal becomes TRUE with positive clock edge at input
53. arithmetical shift right 129 Combination Bit NOT sirsenis 125 Digital inputs of device 137 Bit OR NOR eene 127 Instruction output with device function Bit roll right seessssesses 1305 AW egest Dern ra e reU RIEN 42 Bit Shift left eeeeeeeeess 129 Combination of instructions 138 Bit shift right 128 Parameterization logic diagram 141 Bit XOR XNOR enm 128 Signal source for digital output 44 Output one bit accen 130 F Unite four bits to form a word 131 Filter C PT1 element eee 106 Changeover switch for position values 110 Spike filter caer in 108 Clock generator esssss 48 Frequency parameter Master oeste iei 70 az PN 115 SUperlOF 2 eri ere temere ete Ead 69 TEE EA TE EEEE E E EE T 111 Combinations Function table Input buffer and inputs 41 PUT Aro ssceesiteess secesseetisensevassersdcatss 136 Inputs and outputs of instructions 38 l Instructions with one another 42 Information on Use ssssssssssssesesrsrrrrrrrreers 9 Output buffer and device function 42 Input buffer eee 41 output buffer and digital output 44 ANGIOG sss is eae E 25 Comparator c 25 Constant Variable 79 lic TM 35 38 Motion blocks
54. combine them with other functions no FT instructions e Output signals of FT instructions via a digital output Index 3 FT input 1 1344 lt 75 S6IND FT input 2 1345 lt 74 SSIND Index 1 FT input 3 1346 lt 71 S2IND FT input2 1345 lt 72 S3IND 1 FT input 1 1344 lt 73 S4IND Index 3 amp 2402 2201 E Buffer 2 2202 Start Clockwise 068 Index 1 Index 2 2101S 2401 FT Output Buffer 1 Y P R P Op Mode Digital Output 1 530 IDCM a 76 MFI1D FT input 2 1345 Function table input buffer Index 2 Index 3 Index 4 Index 5 Index6 Index9 FT input buffer 1362 71 S2IND 72 73 S3IND S4IND 74 SSIND 75 76 S6IND MFI1D Function table FT instruction 1343 FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT output 1 1350 FT output 2 1351 Start Clockwise 068 2402 FT Output Buffer 2 Index 1 Index 2 10 RS Flip Flop 2101 2009 Index 3 1 AND 2006 2005 2201 2202 Op Mode Digital Output 1 530 80 FT Output Buffer 1 140 VPLC PLC 08 10 Bonfiglioli Vectron Table of functions Index 1 Index 2 Index 3 Index 4 FT instruction 2 OR 10 RS Flip Flop 1 AND 0 Off last table 1343 Superior item FT input 1 1344 2004 FT input 2101 Outp 1 2006 FT in
55. delay Note The units of the set times is milliseconds ms seconds s or minutes min Internally the values for delays are limited to 24 days 58 VPLC PLC 08 10 Bonfiglioli Vectron Example 1 1 square pulse On time input F 500 ms Delay positive edge 1000 ms Delay negative edge 800 ms non retriggerable retriggerable da Input F Output A Edge 1a starts timer t1 Edge 2a starts timer t2 Edge 1b is output after a delay of t1 referred to 1a Edge 2b is output after a delay of t2 referred to 2a Example 2 1 square pulse followed by positive edge On time input F 500 ms Off time input F 350 ms Delay positive edge 1000 ms Delay negative edge 800 ms non retriggerable retriggerable da 28 3a da 2D A A Lu ti t a 1a starts timer t1 1a starts timer t1 2a starts timer t2 2a starts timer t2 1b is output after t1 3a starts timer t1 again retrigger 3a continuous signal stops execution of 3b is output after t1 referred to 3a 2a VPLC PLC 59 Bonfiglioli Vectron Example 3 4 consecutive square pulses On times and delays as in example 2 non retriggerable retriggerable da 036348 63627363 da 03833 636273 Ba 1a starts timer tl 1a starts timer t1 2a starts timer t2 2a starts timer t2 3a stops execution of 2a 3a starts timer t1 again retrigger 1b is output after time t1 4a starts timer t2 again retrigger 4a starts timer t2
56. fields P1 and P2 Via P1 and P2 the function block can be adjusted to the application Properties Instruction 330 Add with offset 01 11 2 B P1 P2 02 01 result limited to 327 6796 P1 pos offset P2 neg offset MR Reset 08 10 VPLC PLC 17 Bonfiglioli 2 3 6 Settings Inputs outputs and function block Input Settings boolean l J Input Sional Setti A digital signal of the frequency inverter shall PLC Signal 2001 Inputbuffer1 bea command Select an input biffer for PLC Signal Global Source 160 Ready Signal Select a global source for the input buffer ETE IEEE E N ERE ws wise Output Settings Digital ovputeufer 3 indicates index already in use Control functions of the frequency inverter with an output signal Example Output buffer 3 Parameter Start Clockwise 68 2403 PLC Output buffer 3 indicates index in use selection causes renumbering int float je WI Default 0 Max 65535 Double click Q int float Additional settings Default 0 irse Adapt the function to the application In example Delay time of an Edge Delay In the editor double click a block The dialog window will be opened Block Dialog window Eingangssignal Einstellungen cb ke Assign a digital signal at the control terminals of the frequency inverter or a control signal to an input of a digital function block e Sele
57. four data sets V The parameter value is set by the SETUP routine 69 This parameter cannot be written when the frequency inverter is in operation a m This parameter can only be written in setting F7 Runmode 1399 0 Stop Irun Urun Prun Nominal values of frequency inverter Overload capacity of frequency inverter Note In the KP500 control unit parameter numbers gt 999 are represented in hexadecimal form 999 A00 B54 C66 9 1 Actual values No Description Unit Display range Chapter 1356 PLC actual values function M T 7 1 X32 1 32 11 Il 1357 PLC actual values output buffer cra hg 7 1 LEM Se ee s c Tal 1400 PLC actual frequency value from P 1379 Hz 0 00 999 99 7 2 1401 PLC actual current value from P 1380 A 0 0 Ina 7 2 1402 PLC actual percentage from P 1381 96 200 200 7 2 1403 PLC actual voltage eff from P 1382 V 0 0 Uruu 7 2 1404 PLC actual voltage sp from P 1382 V 0 0 Uruu 7 2 1405 PLC actual value general from P 1383 32767 32767 7 2 1406 PLC actual output frequency 250x Hz 999 99 999 99 7 2 1407 PLC actual output current value 251x A eT rax ass Lra 7 2 1408 PLC actual output percentage 252x 200 200 7 2 1409 PLC actual output voltage eff 253x V 0 0 Urun 7 2 1410 PLC actual output voltage sp 253x V 0 0 Uruu 7 2 1411 PLC actual output general 25
58. function block In some instructions i e mathematical operations P1 and P2 can be display as Float or Int ernal Changing the display does not change the value For mathematical operations or Float is recommended For Times i e Monoflop the internal Notation Int is recommended Correlation Float Int 123 45 1 2345 12345 20 VPLC PLC 08 10 Bonfiglioli Vectron 2 4 Starting the PLC functions By default factory setting the PLC functions are stopped and must be started by clicking but ton Start PLC In stop mode no instructions are processed and the output buffer is not writ ten Run the following menu commands Syntax check Translation and download to frequency inverter Start PLC Note Instructions can only be edited in stop mode 2 5 Principle for digital functions input settings Boolean The digital function processing principle is shown in the following diagram The digital input buffer comprises 16 PLC signals which can be assigned to global sources The values in the input buffer are available to the instructions as sources The instructions can be combined with up to 4 input values The outputs of the instructions can be used as inputs of other instructions non negated outputs O1 and negated outputs O2 The instructions are processed one after the other starting with instruction 1 When the processing cycle jumps back to start the output
59. instruction block 1x 2x 3x In this connection an instruction block may also include a single instruction 08 10 VPLC PLC 137 Bonfiglioli Vectron For control of a PLC it is sufficient to select a mode and set it accordingly When the instruction block was processed the frequency inverter resets the operation mode to 0 Stop automatical ly The same mode can be selected again Note If a diagnosis via VPlus is to be performed both modes are required Execution of the instruc tion block must be started by the modes alternately because VPlus only updates parameters on ACU which have been changed Note If Single Step Single Part or Single Cycle are selected the selected mode is maintained The status of the function table is shown exactly in FT Actual Values Function 1356 6 2 1 Example Run Stop The following diagram shows a function block circuit which includes two jump functions J1 and J2 Depending on the settings of parameter F7 RunMode 1399 the procedure is as follows FT Runmode 1399 1 Run The sequence is processed continuously Jump functions are processed according to input sta tuses FT Runmode 1399 11 Single Step 12 Single Step The sequence is interrupted after each instruction Each time the sequence is stopped FT RunMode 1399 must be restarted with 11 Single Step or 12 Single Step Jump functions are processed according to input sta
60. r On delay ti 120 0 0 eg Off delay t2 P1 P2 positive delay negative delay 64 VPLC PLC 08 10 Bonfiglioli Vectron 4 6 Timer functions 4 6 1 60 61 62 Monoflop retriggerable Superior M Monoflop edge 1 b output O1 Cana M Monoflop edge 2 negated output O2 O1 ra Superior Set input On time High Superior Reset input ignore edge time 60 ms 61 s or 62 min Description Output signal becomes TRUE with positive clock edge at input 1 or with negative clock edge at input 2 The time set in P1 is the On Time High and the time set in P2 is the ignore edge time Low The set on time starts again with each edge TRUE at the Superior Set input sets the output to TRUE TRUE at the Superior Reset input sets the output to FALSE Via the output buffer the output signal is globally available Inputs Superior Set and Superior Reset are connected in series with the function Levels on Monoflop inputs I1 and I2 As soon as the Superior Set or Superior Reset is reset the output is switched to the internally saved value Digital Signal Function amp Logic table Input source output o1 State 01 M M SS R Q x X x 1 0 Off Superior xX X 1 0 1 On Superior Ol 021 X 0 0 L Pulse X 021 0 0 L Pulse SR SS Mii i Mii EAST Q 1 1 DER T K gt i ke Ly 3 gt ti t2 SH gt ti t2 ti t2 Pi P2 on time ignore edge time 08 10
61. selected bit of input value 1 is output at output 1 The bit is selected via P1 P1 0 The least significant bit LSB is selected P1 15 The most significant bit MSB is selected 08 10 VPLC PLC 131 Bonfiglioli Vectron Master Set sets all bits of the output value Output OxFFFF Master Reset deletes all bits of the output value Output 0x0000 Example P1 I1 O1 02 1 1 Bit 1 OxFOOF 1 0 2 4 Bit4 0x00FF 1 0 3 4 Bit 4 OxFFOO 0 1 In example 2 Bit 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 11 0 0 0 0 0 0 0 0 1 1 1 41 1 1 1 1 OxOOFF 01 1 gU P1 4 5 11 10 221 Unite four bits to form a word b input value 1 I1 I1 I3 I4 united to form a word input value 2 96 inverted output input value 3 Number of ist bit 0 15 input value 4 E Description The state of input 1 is copied to the bit of output O1 specified via P1 the state of input 2 to the next bit etc All other bits of the output value are zero If P1 gt 12 bits will be lost Master Set sets all bits of the output value Output OxFFFF Master Reset deletes all bits of the output value Output 0x0000 Exam P1 Copy I4 I3 I2 I1 O1 02 ple 1 0 I1 to bit 0 of O1 1 0 1 O 0x000A OxFFF5 I2 to bit 1 of O1 I3 to bit 2 of O1 I4 to bit 3 of O1 2 5 I1 to bit 5 of O1 1 0 1 0 0x0140
62. sets output to TRUE Superior Input 4 Superior Reset TRUE sets output to FALSE FALSE at Set and Reset Last output signal state is maintained See chapter 4 4 1 Output signal changes with the positive pulse edge at input 1 or with 20 Toggle Flip Flop the negative pulse edge at input 2 Superior TRUE at Superior Set input input 3 sets output TRUE TRUE at Superior Reset input input 4 sets output FALSE See chapter 4 4 3 If a positive edge is received at input 1 clock pulse input C Clock ae D Flip Flop Su m present at input 2 data input D is transferred to the out perior TRUE at Superior Set input input 3 sets output TRUE TRUE at Superior Reset input input 4 sets output FALSE See chapter 4 4 5 Delays Digital functions The positive edge at input 1 is delayed by the time set in P1 and the Delay Superior negative edge is delayed by the time set in P2 before switching them 40 ms retriggera through to the output The delay time starts again with each edge ble Times are indicated in milliseconds ms TRUE at Superior Set input input 3 sets output TRUE TRUE at Superior Reset input input 4 sets output FALSE See chapter 4 5 1 A1 Delay Superior s As in operation mode 40 the unit of the times set in P1 and P2 is retriggerable seconds s See chapter 4 5 1 42 ain eros As in operation mode 40 the unit of the times set in P1 and P2 is ble minutes min See chapter 4 5 1 The positive edge at input 1 is delayed by the
63. stopwatch to the start value P1 analog output With P2 a divisor can be set up to scale the output value See chap ter 5 9 2 Positioning functions Analog functions The availability of positioning functions depends on the device series Start motion The motion block selected with P1 is started Input I1 defines the 501 block as single target position Input I2 defines the reference speed See chapter motion 5 10 1 Start motion The motion block selected with P1 is started Input I1 defines the 502 block in auto target position Input I2 defines the reference speed See chapter matic mode 5 10 2 503 Stop motion The current motion block is stopped if the release at input I3 is set block See chapter 5 10 3 504 Continue mo The stopped motion block is continued if the release at input I3 is tion block set See chapter 5 10 4 505 Resume Motion A motion block stopped by an error cut off or mains off is continued Block if the release at input I3 is set See chapter 5 10 5 506 Start homing The homing operation defined in P1 is started if the release at input I3 is set See chapter 5 10 6 507 Check state While a motion block is running output O1 is set to TRUE See chap ter 5 10 7 34 VPLC PLC 08 10 9 Bonfiglioli Vectron 3 1 3 1 1 Inputs and outputs Inputs of digital functions The digital functions use digital input signals and digital output signals
64. the necessary covers improper use wrong installation or operation may result in serious injuries or material damage In order to avoid such injuries or damage only qualified technical staff may carry out the transport installation commissioning setup or maintenance work required The standards EN 50178 IEC 60364 Cenelec HD 384 or DIN VDE 0100 IEC 60664 1 Cenelec HD 625 or VDE 0110 1 as well as the applicable national regula tions must be complied with The term Qualified Staff refers to anybody who is familiar with the installation assembly commissioning and operation of the frequen cy inverter as well as the possible hazards and has the proper qualification for the job Persons who are not familiar with the operation of the frequency inverter and child ren must not have access to the device 1 2 Purpose of the Frequency Inverters Warning N The frequency inverters are electrical drive components intended for installation in industrial plants or machines Commissioning and start of operation is not allowed until it has been verified that the machine meets the requirements of the EC Machi nery Directive 2006 42 EEC and EN 60204 In accordance with the CE marking re quirements the frequency inverters comply with the Low Voltage Directive 2006 95 EC as well as EN 61800 5 1 The user shall be responsible for making sure that the requirements of the EMC Directive 2004 108 EEC are met Frequency inver ters are only available
65. value Window com A value range window is adjusted and it is checked if I1 is within 313 parator VC this constant range See chapter 5 2 7 a com Like operation mode 313 but the absolute value of input I1 varia 314 VC absolute ble is compared to window values P1 constant and P2 constant See chapter 5 2 7 value Based on variables I1 and I2 as well as the constants P1 and P2 the 320 Min Max minimum or maximum value is determined and output at O1 See chapter 5 2 8 Min Max for Based on variables I1 and I2 position values as well as constants P1 321 position values and P2 the minimum or maximum value is determined and output See chapter 5 2 9 One of the following values is output at output O1 the minimum input value at I1 determined over a certain period of f time 322 pan rex n the maximum input value at I1 determined over a certain period time window i of time the current input value at I1 See chapter 5 2 10 One of the following values is output the minimum position value at I1 determined over a certain period Min Max in of time 323 time window the maximum position value at I1 determined over a certain pe for positions riod of time the current position value at I1 See chapter 5 2 11 Mathematical functions Analog functions The input values at I1 and I2 are added up and the input value I3 is subtracted 330 io UM Via P1 and P2 you can sp
66. value O1 is 0 Example 11 14000 140 00 O1 140 0096 150 00 32 33 P1 15000 150 00 1 4000 1 5000 0 3233 6 4955 P2 3233 32 33 649 5590 limited to 327 67 Note Percentages 96 have two decimals For example Value 12345m 123 4596 1 2345 If P2 is set to value 0 the output has the value 327 6796 The sign is applied from the input value 5 3 2 4 335 Mult long percent input value 1 Pos E LP Low word input value 2 Pos P1 High word Denominator Master Reset Description The input value at I1 long is multiplied by the parameter value I2 percentage and divided by parameter value P1 O Ilx 12 P1 The output value comprises a High word O1 and a Low word O2 O2 O1 High word Low word 08 10 VPLC PLC 93 Bonfiglioli Vectron The result of the multiplication long is not limited As long as status TRUE is present at I4 Master Reset the output value is 0 The output value at O2 is not the inverted value of O1 The output can be combined with inputs for position values Long Note Percentages 96 have two decimals For example Value 12345m 123 45 1 2345 5 3 3 Division 5 3 3 1 336 Division I1 Input numerator 01 I2 xI3 Input denominator 1 Input denominator 2 Master Reset inverted output 1 upper limit lower limit Description Th
67. value is output if I3 is FALSE I3 FALSE O1 02 Minimum I1 I2 P1 P2 I3 TRUE O1 02 Maximum I1 I2 P1 P2 320 I1 lin Max I1 I2 P1 P2 O1 I2 P1 96 P2 96 D 02 I4 Note P1 and P2 are not evaluated when the maximum or minimum value is determined if they are set to 0 I2 is not evaluated when the maximum or minimum value is determined if I2 is connected to signal source 9 Zero As long as status TRUE is present at I4 Master Reset the output value is FALSE Note Percentages 96 have two decimals For example Value 12345m 123 45 1 2345 5 2 9 321 Min Max for position values Long Low word High word Low word High word Pos input value 1 input value 2 lb FALSE Min TRUE Max b Master Reset Description Based on variables T1 and I2 as well as constant P the minimum or maximum value is deter mined and output The maximum value is output if I3 is TRUE The minimum value is output if I3 is FALSE I3 FALSE O Minimum I1 I2 P I3 TRUE O Maximum I1 I2 P with O1 P1 Low word O2 P2 High word 08 10 VPLC PLC 87 Bonfiglioli Vectron Note P1 and P2 are not evaluated when the maximum or minimum value is determined if they are set to 0 I2 is not evaluated when the maximum or minimum value is determined if I2 is connected to signal source 9 Zero Note Output value O2 is not t
68. was not exceeded O1 is also reset if P2 is exceeded first and then deceeded again 304 Comp input with constant abs value Description This function compares the absolute value of input I1 to the switching thresholds P1 and P2 O1 is TRUE is I1 gt P1 upper threshold O1 is FALSE if I1 lt P2 lower threshold O1 remains unchanged if I1 is in the range between P2 and P1 08 10 VPLC PLC 79 Bonfiglioli Vectron The comparator has three working ranges Range 1 P1 lt I1 O1 TRUE Range 2 P2 lt I1 lt P1 O1 remains unchanged Range 3 Ii lt P2 Ol FALSE 02 O1 Special case P2 lower threshold is set higher than P1 upper threshold thresholds exchanged O1 is TRUE if I1 gt P1 O1 will be reset if P1 is deceeded again and P2 was not exceeded O1 is also reset if P2 is exceeded first and then deceeded again The output value can be changed by means of the two Boolean inputs I3 and 14 Master Set sets output O1 to TRUE Master Reset sets output O1 to FALSE Master Reset has priority over Master Set 303 I1 P1 304 I1 P1 I1 Note Percentages 96 have two decimals For example Value 12345 123 45 1 2345 80 VPLC PLC 08 10 Bonfiglioli Vectron 5 2 3 308 Comparator for motion blocks P1 current motion block P2 eS O1 inverted p Master Set ioo Motion block from Master Reset Motion block to Descri
69. with exceeded the output is switched on If the lower threshold P2 is const deceeded the output is switched off See chapter 5 2 2 Comparator Like operation mode 303 but the absolute value at input I1 varia 304 absolute value ble is compared to switching thresholds P1 and P2 constants See inp with const chapter 5 2 2 30 VPLC PLC 08 10 9 Bonfiglioli Vectron A motion block range is set up and it is checked if a motion block Comparator from this area is active in the case of table positioning 308 active motion O1 is TRUE if a motion block from range P1 to P2 motion block from block to is active See chapter 5 2 3 Not available for all device se ries 309 Comparator Input values I1 and I2 are compared Via P1 and P2 a hysteresis can Position be adjusted Suitable for position values See chapter 5 2 4 Signal at I3 saves actual value at I1 Via I2 variable and P1 con 310 Analog hystere stant a hysteresis can be set up If the value of I1 is within the sis hysteresis the saved value is output If the value of I1 is outside of the hysteresis the current value of I1 is output See chapter 5 2 5 311 Window com It is checked if I1 is in the adjusted range window around I2 See parator 2V chapter 5 2 6 Mndow SOR Like operation mode 311 but the absolute values of inputs I1 and I2 312 parator 2V are compared See chapter 5 2 6 absolute
70. 0 4 index Description The function reads the value of the parameter set up in P1 Parameter number and P2 Data set index The value is converted to a current value Via Input I3 read access is enabled I3 0 No read access I3 1 The parameter value is read The instruction is executed until the value is read 116 VPLC PLC 08 10 5 7 2 3 423 Read voltage parameter eff Parameter value V inverted output 1 Release read access Parameter number Bonfiglioli Data set 0 4 index Description The function reads the value of the parameter set up in P1 Parameter number and P2 Data set index The value is converted to a voltage value Via Input I3 read access is enabled I3 0 No read access I3 1 The parameter value is read The instruction is executed until the value is read 5 7 2 4 424 Read voltage parameter peak Parameter value V inverted output 1 Release read access Parameter number i Data set 0 4 index Description The function reads the value of the parameter set up in P1 Parameter number and P2 Data set index The value is converted to a voltage value Via Input I3 read access is enabled I320 No read access I321 The parameter value is read The instruction is executed until the value is read 5 7 2 5 425 Re
71. 00 6 16 67 3 One counting pulse down 100 00 P2 100 00 4 25 4 Four counting pulses up each 100 00 P1 100 00 6 16 67 5 Two counting pulses up limitation to 100 00 6 Three counting pulses down each 100 00 P2 100 00 4 25 7 One counting pulse up 100 00 P1 100 00 6 16 67 8 One counting pulse down 100 00 P2 100 00 4 25 9 Two counting pulses down limitation to zero 10 Master Set sets output O1 to 100 00 11 Two counting pulses down each 100 00 P2 100 00 4 25 Note P1 and P2 are limited internally to 100 00 If a greater value is entered this value is replaced by 100 0095 5 9 2 451 Stopwatch with analog output Release Counting value ms P2 lb _ Release inverted inverted output 1 ra Counting direction Start value Reset i Divisor 120 VPLC PLC 08 10 Bonfiglioli Vectron Description The stopwatch is running if I1 TRUE and I2 FALSE In all other cases the stopwatch is stopped Input 3 determines the direction I3 TRUE Stop watch runs forward I3 FALSE Stopwatch runs backward A positive edge at I4 sets the stopwatch output O1 to the start value P1 As from the next negative edge the stopwatch will be running if I1 TRUE and I2 FALSE P2 determines the divisor with which the internal value is converted in the output value The output value is limited to th
72. 01 PLC Output buffer 1 2416 PLC output buffer 16 must be selected If for exam ple output buffer 3 was selected for the digital output of the instruction signal source 2403 Output buffer 3 must be selected for a device function As a result the output is generally globally available to other device functions The selected signal source must also be assigned to the device function to be activated Up to 16 signal sources can be used for further processing of logic states of the instruction outputs A signal source can be assigned to several outputs of instructions Example 1 Combination of an instruction output with a device function The function Start anticlockwise is to be activated via the output of an instruction e Dialog window Settings for digital outputs Output buffer 1 other selection also possible As a result the output is generally globally available to other device functions e Start Anticlockwise 69 2401 PLC Output Buffer 1 according to above selection Example 2 Combination of an instruction output with a device function The output of an instruction is needed for combination with a device function This function is no PLC function The output of the instruction is to be defined as a general global signal source and activate the device function Switch data set 1 42 VPLC PLC 08 10 9 Bonfiglioli Vectron VPLC Instruction OR XOR AND O1 02 VPlus
73. 1 Settings for fixed parameterization Settings for non fixed parameterization non volatile volatile 0 all input buffers in EEPROM 5 all input buffers in RAM 1 4 individual input buffer in EEPROM 6 9 individual input buffer in RAM Note The settings 0 or 5 for FT Write Index FT input analog 1377 change all values of an in put buffer in the EEPROM or RAM In the case of non volatile storage 0 4 the changed values are still available when power supply is switched on again In the case of volatile storage 5 9 the data is only stored in RAM If the unit is switched off this data is lost and the data required are loaded from EEPROM 136 VPLC PLC 08 10 Bonfiglioli Vectron Caution Writing of the EEPROM is restricted to approx 1 million times If this number is exceeded the device may be damaged Definition Input buffer RAM input buffer EEPROM 5 Write index and read index for the Input buffer analog table VPlus i Parameter Data set 0 i FT write index FT input analog 1377 2 FT read index FT input analog 1378 2 1 i FT input buffer frequency 1379 62 Ref rescesaauency Channel i i FT input buffer current 1380 126 Active Curren i i l PVmbe WW Mp I E Input buffer analog Index1 Index 2 i FT input buffer frequency 1379 9 Zero 62 Reference Frequency Channel i FT input buffer current 1380 9 Zero 126 Active Current i 6 2 R
74. 1345 A1 1350 E2 1345 A1 1350 E2 1345 A1 1350 E31346 P11348 ap E31346 P11348 42 E31346 P11348 a2 E31346 P11348 42 E4 1347 P21349 421351 E4 1347 P21349 551351 E4 1347 P21349 451351 E4 1347 P21349 521351 FT Ausgangspuffer Indexi Index2 Index 3 Index 4 Index 5 Index 6 Index 7 Index 8 Index 9 Index 10 Indexi11 Index12 Indexi13 Indexi14 Index15 Index 16 Quelle 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 Digitaler Ausgang 158 VPLC PLC 08 10 Bonfiglioli Vectron 10 2 Mask Functions settings FT Instruction 1343 FT Input 1 134 FT Input 2 134 FT Input 3 134 FT Input 4 134 FT Parameter 1 134 FT Parameter 2 134 FT target output 1 135 FT target output 2 135 FT Commentary 1352 N eo FT Instruction 134 FT Input 1 134 FT Input 2 134 FT Input 3 134 FT Input 4 134 FT Parameter 1 1348 FT Parameter 2 134 FT target output 1 135 FT target output 2 135 FT Commentary 1352 FT Instruction 134 FT Input 1 134 FT Input 2 134 FT Input 3 134 FT Input 4 134 FT Parameter 1 1348 FT Parameter 2 1349 FT target output 1 135 FT target output 2 135 FT Commentary 1352 o1 i l FT Instruction 134 FT Input 1 134 FT Input 2 1345 FT Input 3 1346 FT Input 4 134 FT Parameter 1 134 FT Parameter 2 134 FT target output 1 135 FT target output 2 135 FT Commentary 1352 l 08 10 VPLC PLC 159 Bonfiglioli Vectron Index A Master A
75. 21 rete b Yo Yo i i 422 Read current parameter b i i Read voltage parameter _ i j 3 423 eff b Yo Yo i i Read voltage parameter _ i i 424 peak b Yo Yo i i 425 percent parame i b I 96 96 i i 426 ER position parame i b 96 i i 427 Read long parameter z b i i 428 Read word parameter 7 b i i 440 Limiter const b 441 Limiter variable b 450 Up Down counter b b b b i i 08 10 VPLC PLC 37 Bonfiglioli Vectron Counter with analog 451 b b b b 95 95 output sote sare motion DOR Pos b b Pos Pos single motion Boe ee natn Deen Pos b b Pos Pos automatic mode 503 Stop motion block b b Pos Pos 504 Continue motion block b b Pos Pos 505 Resume motion block b b Pos Pos 506 Start homing s b b Pos Pos 507 Check state b b b 3 2 Combination of inputs and outputs of instructions Inputs Each instruction has 4 inputs The inputs can be combined with outputs of other instructions or digital inputs or global signal sources Outputs Each instruction has 2 outputs The two outputs can be combined with inputs of other instructions combined with device functions output via digital or analog outputs of the device In the case of digital functions output 2 has the negated logic state of inpu
76. 4 2521 2524 Outp percent 1 4 2531 2534 Outp voltage 1 4 2551 2554 Outp user 1 4 2561 2564 Flag1 4 Combination with fixed analog value 2601 2604 Fixed frequ 1 4 2611 2614 Fixed current 1 4 2621 2624 Fixed perc 1 4 2631 2634 Fixed eff volt 1 4 2641 2644 Fixed peak volt 1 4 2651 2654 Fixed gen 1 4 2661 2664 Fixed position 1 4 2671 2674 Fixed speed pos 1 4 2681 2684 Fixed ramp pos 1 4 2380 2392 Auxiliary values constants and global flags status signals 2380 0 00 zero percent The auxiliary quantity has constant value 0 2381 100 00 one hundred percent The auxiliary quantity has constant value 100 2382 327 67 maximum value The auxiliary quantity has constant value 327 67 2383 OXFFF for bitwise combination The auxiliary quantity has constant hexadecimal value OxFFFF and can be used for bitwise com binations 2384 Fmax 100 Auxiliary quantity has constant value 100 of Fmax of parameter Maximum frequency 419 2385 Rated motor current in current data set The auxiliary quantity is referred to parameter value Rated current 371 in the current data set The constant value is applied to the input of the instruction 100 corresponds to the value of the rated motor current 2386 Short time overload current ILIMIT The auxili
77. 5x 32767 32767 7 2 1412 PLC actual value flag 256x 96 327 67 327 67 7 2 08 10 VPLC PLC 155 Bonfiglioli Vectron 9 2 The following parameters are needed only for parameterization using the function table Parameters of function table Description Unit Setting range Factory setting Chap ter PLC write index PLC table item 0 65 1 6 1 1 PLC read index PLC table item 0 65 1 6 1 1 PLC instruction Selection O Off last table item 6 3 PLC input 1 Selection 7 FALSE 6 3 PLC input 2 Selection 7 FALSE 6 3 PLC input 3 Selection 7 FALSE 6 3 PLC input 4 Selection 7 FALSE 6 3 PLC parameter 1 PLC parameter 2 Depend 0 65535 10 4 2 5 1 ing on instruction 0 65535 10 4 2 5 1 SPS target output 1 Selection 0 Output not usable globally 6 3 SPS target output 2 Selection 0 Output not usable globally 6 3 PLC commentary 16 characters 6 3 PLC write index PLC table item 0 33 PLC read index PLC input buffer 0 33 6 1 2 ol PLC input buffer Selection 6 1 2 PLC write index PLC input analog 0 9 6 1 3 PLC read index PLC input analog 0 9 PLC input buffer fre quency Selection
78. 6 1 2345 08 10 VPLC PLC 103 Bonfiglioli Vectron 5 4 4 373 PD T1 controller Input reference 9 amp O1 P1x 11 12 P1xP2x a t 12 value Input actual inverted output 1 value EIER LOT P amplification output values Master Reset i Derivative action time in ms Description The control deviation I1 I2 is multiplied by the amplification P1 The D component is added 01 02 P I1 12 p x p2 C I2 The output value is limited to the value at input I3 The input can be combined with a fixed value for example As long as status TRUE is present at I4 Master Reset the output value O1 is 0 The time constant T1 of the PD T1 controller corresponds to the sampling time Note Percentages 96 have two decimals For example Value 12345m 123 45 1 2345 5 4 5 374 PID T1 controller Tn in milliseconds Input reference value Input actual value Limitation of output values Master Reset i Derivative action time in ms 01 1 12 1 11 raja ez 01 22 inverted output 1 Integral time in ms Description The control deviation I1 12 is multiplied by the amplification 1 The I component and the D component are added 01 02 n 12 ti 12 at p 2 dt In instruction 374 PID T1 controller the integral time P1 I component and the derivative action time P2 D component can b
79. 7 7 6 Error messages of instruction 95 Triggering an error 147 08 10 VPLC PLC 5 Bonfiglioli Vectron 8 1 Example of a controller 111eeeeeeee serene nennen nn nnne nnns 148 9 1 Actual values 1 eeseeeeeeee seinen nenne nennen annua nana nana Uaa AEAN Aaaa SaRaNa 155 9 2 Parameters of function table esses esses ee 156 10 1 Mask Diagram for digital instructions of function table 158 10 2 Mask Functions settings c0se eee 159 6 VPLC PLC 08 10 Bonfiglioli Vectron 1 General Safety Instructions and Information on Use Warning N The specifications and instructions contained in the documentation must be complied with strictly during installation and commissioning Before starting the relevant ac tivity read the documentation carefully and comply with the safety instructions The term Qualified Staff refers to anybody who is familiar with the installation assem bly commissioning and operation of the frequency inverter and has the proper qua lification for the job 1 1 General Information Warning N The DC link circuit of the frequency inverter is charged during operation i e there is always the risk of contact with high voltage Frequency inverters are used for driving moving parts and they may become hot at the surface during operation Any unauthorized removal of
80. 72 170 Monoflop 80 82 180 182 Clock generator The units of Pi and P2 may be set to milliseconds ms seconds s or minutes min The unit of the entered value depends on the instruction Note Time set for P1 and P2 are limited internally to the maximum value of 24 days are not continued when the frequency is switched off and on again The sequence is res tarted from the beginning after re activation 4 2 2 Jump target The evaluation of P1 and P2 affects the following instruction 100 Jump function Description Min Max P2 4 2 3 Overview table The meaning of the settings for P1 and P2 depending on the selection of the application is summarized in the following table delay ms 140 retriggerable delay s 141 retriggerable delay min 142 retriggerable delay ms 150 non retriggerable delay s 151 non retriggerable delay min 152 non retriggerable Monoflop ms retriggerable Monoflop s retriggerable 162 70 Monoflop ms non retriggerable Monoflop s non retriggerable delay pos edge ms delay neg edge ms delay pos edge s delay neg edge s delay pos edge min delay neg edge min delay pos edge ms delay neg edge ms delay pos edge s delay neg edge s delay pos edge min delay neg edge min ON time ms ignore edge time ms ON time s ignore edge time s zZ onoflop min retriggerable ON time min ignor
81. Adjust the page size of the editor The changes made with VPLC are deleted in the frequency inverter and reset to the default set tings PLC gt Delete Apply the function block program to parameter values and download them to the frequency inver ter While edited in the editor the function block program is not changed in the frequency inverter Changes will only be applied to the frequency in verter by this command PLC gt Translate and download to fre quency inverter Note Working on the sheet doesn t change the program inside the frequency inverter Only via the Download Command the changes of the PLC program are loaded to the frequency inverter 16 VPLC PLC 08 10 9 Bonfiglioli Vectron 2 3 3 Editor In the editor PLC programs are displayed graphically 2 3 4 Library From the library the blocks for inputs and outputs and function blocks can be dragged to the editor window Alternatively you can click button Activate function block In this way the function block se lected in the library can be inserted in the editor window Library Libraries B Inputs Outputs Digital In Analog In Position In Digital Out Analog Out 5 Logic AND OR XOR 1 2 3 5 Properties The properties of the function block selected in the library will be displayed Number of instruction Function of inputs I and outputs O of instruction Function of input
82. Device functionality e Select an output buffer for the output of the instructions e g output buffer 5 DigOut Output buffer 5 output arbitrary from 2401 to 2416 Data set change over 1 70 2405 PLC Output buffer 5 As a result the signal source is generally globally available for processing by other device functions It is also possible to choose another signal source from signal sources 2401 to 2416 for the parameter e For parameter Switch Data Set 1 70 select signal source 2405 FT Output buffer 5 Example 3 The output value of instruction 1 is to be transmitted via system bus Depending on the device series an extension module with system bus must be installed VPLC Instruction analogue O1 02 VPlus Voltage buffer 1 Device functionality TxPDO 1 Word 1 950 2531 PLC Output Voltage 1 08 10 43 Bonfiglioli Vectron 3 2 5 Controlling a digital output via the output buffer The outputs of the instructions can be output via digital outputs once they have been defined as general global signal sources The following signal sources can be selected for the parameters of the digital outputs PLC output buffer 1 80 180 PLC output buffer 2 81 181 PLC output buffer 3 82 182 PLC output buffer 4 83 183 Example Selection of signal source for digital output The output signal of an instruction is to be output via a digit
83. E at the Master Set input sets the output to TRUE TRUE at the Master Reset input sets the output to FALSE Via the output buffer the output signal is globally available Master Set and Master Reset are connected parallel with the function and change the state of the function as soon as the signal is present M Q x x X 1 O0 Off Master x x 1 0 1 On Master 021 X 0 0 L Pulse 91 x 120 0 0 L Pulse MR i t ms 1 al LPL LAL as M deg ti tl t2 t ti t 2 YN P P1 P2 on time ignore edge time 68 VPLC PLC 08 10 Bonfiglioli Vectron 4 6 5 80 81 82 Clock generator Superior S clock generator 1 DEM S Clock generator 2 ra Superior Set input Superior Reset input b output O1 On time High t Off time Low 80 ms 81 s or 82 min Description negated output O2 Ot As long as input 1 is TRUE and input 2 is FALSE the set pulse pattern is output The pulse pat tern at the output always starts with TRUE The clock pattern is defined by the on time and the off time The time set in P1 is the on time High and the time set in P2 is the off time Low Via the output buffer the output signal is globally available Inputs Superior Set and Superior Reset are connected in series with the function Levels at Set input I1 and Reset input I2 are processed internally As soon as the Superior Set or Superior Reset is reset the o
84. F3 I2 to bit 0 of O1 I3 to Bit 1 of O1 Master Set sets all bits of the output value Output OxFFFF Master Reset deletes all bits of the output value Output 0x0000 In example 1 I2 o P1212 13 1 P2 11 n slale feelo eialo oloi tt oroo VY iV i i i Viii ix 01 1 1 1 0 1 00 0 0 00 0 1 11 1 OxE80F Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 08 10 VPLC PLC 133 Bonfiglioli Vectron 6 Examples of combinations in the function table The examples describe combinations of signals of the device series ACU The combination pro cedure is the same in the different device series The names of the signal sources may be dif ferent 6 1 Write index and read index 6 1 1 Write index and read index for FT instructions Via the write and read indices the index of the instruction the parameters of which are to be read or written is specified VTable uses the parameters automatically for writing and reading The write and read parameters are required for parameterization via the keypad of a control unit or via a bus system e g PROFIBUS Write index and read index for parameterization and reading of FT instructions via software VPlus The FT instructions can be parameterized in the user interface VPlus or in the function table VTable In the user interface VPlus an index of the function table can be creat
85. Hold O1 0 1 0 0O Q Hold 021 x 0 0 Q Toggle 1 0 0 0O Q Hold 1 1 0 0O Q Hold x 0 gt 1 0 0 Qum Toggle 54 VPLC PLC 08 10 Bonfiglioli Vectron 4 4 4 120 Toggle Flip Flop Master b Toggle 1 b output O1 b Toggle 2 negated output O2 O1 Ib Master Set input b Master Reset input Description Output signal changes with the positive pulse edge at input T1 or with the negative pulse edge at input T2 TRUE at the Master Set input sets the output to TRUE TRUE at the Master Reset input sets the output to FALSE Via the output buffer the output signal is globally available Master Set and Master Reset are connected parallel with the function and change the state of the function as soon as the signal is present State Off Master 1 On Master Q 4 Hold Qna Hold Qn1 Toggle Qna Hold Qna Hold Qn 1 Toggle Ol Ti T2 MS MR cOococococcococmun YVRrRoxrox x cOooooonu x 08 10 VPLC PLC 55 Bonfiglioli Vectron 4 4 5 30 D Flip Flop Superior C Clock b output O1 C D Data input negated output O2 O1 ra Superior Set input Superior Reset input Description If a positive edge is received at input 1 clock pulse input C Clock the signal is transferred from signal input 2 data input D to the output TRUE at the Superior Set input sets the output to TRUE TRUE at the Superior Reset input sets the outpu
86. MUX for position values 110 Purpose of the Frequency Inverters 7 N R NOB iii uini rentrer ED 74 Ramp limitation eeeeeeeee 107 O Read index OR operation eeennm 50 Analog input buffer sesers 135 Output buffer Digital input buffer srn 134 analog ir rnnt 25 FT instructions seeen 133 digitale viet crier ete 25 R CiDrOCal tette reset 94 Output one Ditis Potete baa 130 RS Flip Flop Output signals ssi eet eatis 142 Master oed i tiae We tectis 53 QUIDULS creen trt e eimi terne 36 Superior ee 52 Overview table RUN StOpss 3d er eterne 136 digitalz zero erret rt tuere 48 S P p 7 P CORUDIISE piii 101 Signal sources Parameter access analogis 52 nhi irt ent tre ds 24 current digital Ses cose eG a eser 22 i 115 for analog output see 145 lisi ED 112 for device function 146 frequency for digital output 145 iz EET 115 Single RIOLOrT sacos Coon een 121 WITE senri iade iieiea 111 Spike filter conser tetas 108 long Square 2 cete ona teneret eben 99 qo 117 Square TOOL iiit ae beer iki aepo 99 c HR 114 square root X cese 99 percent Start HOMING sessio ren o erus mk gasta ep 124 read sedentes 116 Start motion block 08 10 VPLC PLC 161 Bonfiglioli Vectron as single motion esee 121 read peak
87. OxFEBF I2 to bit 6 of O1 I3 to bit 7 of O1 I4 to bit 8 of O1 3 14 11 to bit 14 of O1 1 0 1 O 0x4000 OxBFFF P1212 I2 to bit 15 of O1 I3 not copied I4 not copied Re example 2 H lo P1 5 I2 1 I3 0 I4 01 0 0 00 0 00 1 0 10 00 0 0 0 0x0140 Bit 15 14 13 12 1110 98 7 6 5 4 3 2 1 0 132 VPLC PLC 08 10 Bonfiglioli Vectron 5 11 11 222 Add two bits to a word Input word 1 O1 I1 Bit P1 12 Bit P2 I3 lb Input Bit 1 inverted output b Input Bit 2 Number of ist bit 0 15 b Master Reset i Number of 2nd bit 0 15 Description The states at inputs I2 and I3 are inserted in certain bits of the input value 1 The bits are de fined by P1 and P2 The input value at I1 is copied to output O1 The state of input I2 is copied to the bit of output O1 specified via P1 The state of input I3 is copied to the bit of output O1 specified via P2 If a bit number outside of range 0 15 is specified the bit will not be written in the word Example P1 P2 Copy I1 I2 I3 O1 02 1 12 11 Ii to 01 OxFOOF 0 1 OxE80F Ox17F0 I2 to bit 12 of O1 I3 to Bit 11 of O1 2 4 5 I1 to O1 OxFOOF 1 1 OxFO3F OxOFCO I2 to bit 4 of O1 I3 to Bit 5 of O1 3 0 1 I1 to O1 OxFOOF 0 0 OxFOOC OxOF
88. Stator frequency Combination of a fixed value with the input of an instruction A fixed analog value e g fixed frequency value is to be applied to the input of an instruction e In dialog window Input settings analog select a PLC signal 2601 2654 e Enter a value Signal source 2601 2604 Fixed freq 1 4 2611 2614 Fixed current 1 4 2621 2624 Fixed perc 1 4 2631 2634 Fixed eff volt 1 4 2641 2644 Fixed peak volt 1 4 08 10 VPLC PLC 41 Bonfiglioli Vectron 2651 2654 Fixed gen 1 4 2661 2664 Fixed position 1 4 2671 2674 Fixed speed pos 1 4 2681 2684 Fixed ramp pos 1 4 Example Combination of an instruction input with a fixed value An adjusted current value is to be applied to an input of an instruction e In dialog window Input settings analog select a PLC signal 2611 Fixed current 1 2164 Fixed current 2 e Enter a current value A value 3 2 3 Combining instructions with one another The outputs of the instructions can be combined with inputs by instructions Use the wire tool 3 2 4 Activating device functions via the output buffer If the logic state of an output is to activate a device function an output buffer must be selected for the digital output of the instruction For the device function the corresponding signal source 24
89. Travel top Position up bottom Lower lamp off Lower lamp on Drive start Drive stopped up Initiator bottom Door open Initiator top Initializing reached Initiator bottom Initiator reached top Door open NoN Initiator Position Travel top gt down Upper lamp off Drive start down Upper lamp on Drive stopped Toggle switch bottom Representation as state machine step 2 The events and actions are assigned to the digital signals of the ACU At first the signals are linked to the input and output buffer An EM IO 03 extension module is available Function ACU Input buf Output fer buffer toggle switch top bottom SSIND 1 0 2005 top position initiator reached not S4IND 1 0 2004 reached bottom position initiator reached not S2IND 1 0 2002 reached door open open closed S3IND 1 0 2003 bottom LED on off S10UTD 1 0 2401 top LED on off S3OUTD 1 0 2402 bottom position door lamp on off MFO1D 1 0 2403 top position door lamp on off EM S10UTD 1 0 2404 start drive up Start Clockwise 2410 068 start drive down Start Anticlock 2411 wise 069 08 10 VPLC PLC 149 Bonfiglioli Vectron With the assignment of the digital ACU signals the following diagram is obtained Travel S5IND 1 Position up bottom lt lt S1OUTD 0 S1OUTD 1 Start CW Start CCW 068 1 S2IND 1 069 0 S4IND 1 Initializ
90. UE jump function is executed Input 1 FALSE jump function is not executed Jump target Input 2 defines the jump target of which parameter P1 or P2 is to be applied Input 2 TRUE Jump to instruction set in P1 Input 2 FALSE Jump to instruction set in P2 Updating of input buffer TRUE at input 3 results in the input buffer being updated The values of the digital inputs and signal sources in the input buffer are updated Updating of output buffer output buffer values TRUE at input 4 results in the values of the output values 2401 PLC output buffer 1 to 2416 PLC output buffer 16 being updated The updated values are available to digital outputs and functions linked to instruction outputs e g Start Clockwise Switch Data Set Jump function I1 Activation I2 Jump target I3 Update input buffer I4 Update output buffer Signal sources 2401 2416 I1 I2 I3 I4 Jump O0 x x x Jump to next instruction index I 1 1 1 x x Jump to instruction set in P1 1 0 x x Jump to instruction set in P2 I1 I2 I3 I4 Update X x 1 x j Update input buffer 2001 2016 X X x 1 Update output buffer 2401 2416 Note At first the output buffer is written and the input buffer is set Then the jump event is eva luated based on the updated buffers and executed 08 10 VPLC PLC 75 Bonfiglioli Vectron 4 12 2 101 Jump function for loops Finish loop b b Restart loop b
91. a date Te Input value Start value b Master Set b Master Reset I1 with limited ramp gradient inverted output 1 Ramp gradient 96 per time unit Time unit 1 ms 2 s 3 min Description The output value follows the input value at a limited ramp gradient P1 indicates the percentage by which the output value may change per unit of time P2 indicates the unit of P1 1 in percent per millisecond ms 2 in percent per second s 3 in percent per minute min Master Set TRUE sets the output to the start value The start value can be defined via input I2 Master Reset TRUE sets output O1 to 0 Master Reset has priority over Master Set 382 VA P1 time unit timeunit Start value 1 DE N P2 MS O1 I2 O1 ms s min 108 VPLC PLC 08 10 Bonfiglioli Vectron I3 I4 O1 0 0 I1 ramp gradient limited 021 0 I2 x 0 gt 1 0 If the ramp is to be stopped input 2 must be combined with the output and the Master Set input I3 must be activated I2201 I3Z TRUE 382 I3 Note Percentages 96 have two decimals For example Value 12345 123 4596 1 2345 5 5 4 383 Spike filter average of three Output average of Io 2 Ho D Ho Start value inverted output 1 Master Set Master Reset b b Descr
92. a short circuit Connect earth conductors Protect against nearby power sources and delimit the working zone 1 n plants with a nominal power up to 1 kV deviation from description may be possible When working at the frequency inverters comply with the relevant accident prevention regula tions the applicable standards standards governing work on systems with dangerous voltages e g EN 50178 directives for electrical and mechanical equipment erection and other national directives Comply with the electrical installation instructions given in the documentation as well as the relevant directives Responsibility for compliance with and examination of the limit values of the EMC product norm EN 61800 3 for variable speed electrical drive mechanisms is with the manu facturer of the industrial plant or machine The documentation contains information on EMC conforming instal lation The cables connected to the frequency inverters may not be subjected to high voltage insula tion tests unless appropriate circuitry measures are taken before Do not connect any capacitive loads 8 VPLC PLC 08 10 Bonfiglioli Vectron 1 6 Information on Use Warning AN The frequency inverter may be connected to power supply every 60 s This must be considered when operating a mains contactor in jog operation mode For commis sioning or after an emergency stop a non recurrent direct restart is permissible After a failure and restoratio
93. ad percent parameter 9o Parameter value 96 9o inverted output 1 lb Release read access Parameter number i Data set 0 4 index Description The function reads the value of the parameter set up in P1 Parameter number and P2 Data set index The value is converted to a percent value Via Input I3 read access is enabled I320 No read access I321 The parameter value is read The instruction is executed until the value is read 5 7 2 6 426 Read position parameter Position Low word A value High word Release read access Parameter number i Data set 0 4 index Description The function reads the value of the parameter set up in P1 Parameter number and P2 Data set index The value is converted to a position value Via Input I3 read access is enabled 0 No read access 1 I3 I3 The parameter value is read The instruction is executed until the value is read 08 10 VPLC PLC 117 Bonfiglioli Vectron 5 7 2 7 427 Read long parameter Long value Low word a High word Release read access Parameter number i Data set 0 4 index Description The function reads the value of the parameter set up in P1 Parameter number and P2 Data set index The value is converted to a long value Via Input I3 read access is enabled 0 No read access 1 The parameter value is read The instructio
94. aeo E e Lo Te nee 50 4 3 3 3 XOR i Operation eere eret rta eren Aa neu n RR ra ER ERR 51 4 3 4 4 XOR 1 3 operation eeeseeeeeeneneenn nnnm nnnm nnn nnn nnn 51 4 4 Flip Flop types 1neeerreeee rernm nennen nnn nnnm nnn nn nnn 52 4 4 1 10 RS Flip Flop Superior eeeeeeeeennenenmnmmmmmem nnn 52 4 4 2 110 RS Flip Flop Master ceeeeeeneenennnnnnnnnmenn nnne 53 4 4 3 20 Toggle Flip Flop Superior eseeeeenernnnnm mmm 54 4 4 4 120 Toggle Flip Flop Master ccccecccsseeeeeeeseeeeeeesaeeeeseaaaeeeeeaaaaeeeeasaaeeeeasaaes 55 4 4 5 30 D Flip Flop Superior e eerie nnn nnnm 56 4 4 6 130 D Flip Flop Master eeeeeeeneene nennen nnne nennen nnn 57 iS IDEVCEEEREMERPUHEEU DERE ETE 58 4 5 1 X 40 41 42 Delay retriggerable Superior eeenm 61 4 5 2 140 141 142 Delay retriggerable Master eeennm 62 4 5 3 50 51 52 Delay non retriggerable Superior eene 63 4 5 4 150 151 152 Delay non retriggerable Master eee 64 4 6 Timer functions eeieeee seiner eren nennen nnne nnne n ann nnnm n hana unu anam uana 65 4 6 1 60 61 62 Monoflop retriggerable Superior eeeenneen 65 4 6 2 160 161 162 Monoflop retriggerable Master
95. ages 96 have two decimals For example Value 12345m 123 45 1 2345 VPLC PLC 83 Bonfiglioli 5 2 6 311 312 Window comparator comparison of two variables 9o Comparative value 1 Comparative value 2 Master Set Master Reset Output I1 gt I2 O1 inverted positive window xxx xx9 o negative window xxx xx b b 311 W Comp 2 V Window comparator two variables 312 W Comp 2 V absolute value Window comparator two variables absolute value 311 W comp 2 V Description It is checked if I1 is in the adjusted range window around 12 O1 is TRUE if I1 is in the range of I2 The range is set up with P1 positive window and P2 negative window O1 is FALSE if I1 is outside of this range The comparator has three working ranges Range 1 I2 Pl lt I O1 FALSE Range 2 I2 P2 H I2 P1 O1 TRUE Range 3 I1 I2 P2 O1 FALSE 312 W comp 2 V absolute value Description It is checked if the absolute value I1 is in the adjusted range window around absolute value of I2 O1 is TRUE if I1 is in the range of I2 The range is set up with P1 positive window and P2 negative window O1 is FALSE if I1 is outside of this range The comparator has three working ranges Range 1 II2 P1 lt JIi O1 FALSE Range 2 II2 P2 lt I lt I2 P1 O1 TRUE Range 3 I1 lt I2 P2 O1 FALSE
96. al output VPLC Instruction OR XOR AND O1 DigOut Output buffer 4 output arbitrary from 2401 to 2404 02 VPlus Output of the output 1 of the instruction via digital output ACU i e Operation mode digital output 1 530 83 PLC Output buffer 4 AGL i e Operation mode OUTID X13 5 531 83 PLC Output buffer 4 The output of the instruction must be defined as a general global signal source e Select an output buffer for the output of the instructions e g 4 As a result the signal source is generally globally available for processing by other device functions and has the logic state of the output of the instruction You can also select another output buffer For a digital output choose the general global signal source which contains the output value of the instruction e For the parameter of a digital output choose the PLC output buffer signal e g 83 PLC output buffer 4 44 VPLC PLC 08 10 9 Bonfiglioli Vectron 3 2 6 Controlling an analog output via the output buffer The outputs of the analog instructions can be output via analog outputs once they have been defined as general global signal sources VPLC AnaOut VPlus Analog range 553 ACU Analog Source MF01A 553 AGL Buffer percent 61 Abs value PLC outp percent 1 Buffer number 1 161 PLC outp percent 1 Buffer percent ona 62 Abs value PLC outp percent 2 Buffer nu
97. alue at input I3 Input I3 can be combined with a fixed value for example As long as status TRUE is present at I4 Master Reset the output value O1 and the I compo nent are 0 Note Percentages 96 have two decimals For example Value 12345 123 4596 1 2345 5 4 6 375 PID T1 controller Tn in seconds 01 1 12 3 1 12 at po E inverted output 1 Limitation of output values Integral time in s Master Reset i Derivative action time in ms Description The control deviation I1 12 is multiplied by the amplification 21 The I component and the D component are added 01 o2 1 12 jq 12 dt p2x 201 22 dt 08 10 VPLC PLC 105 Bonfiglioli Vectron In instruction 375 PID T1 controller the integral time P1 I component and the derivative action time P2 D component can be adjusted The amplification P1 is set to the fixed value 1 In order to set up another amplification a P controller instruction 370 P controller must be connected to the input of the PID T1 controller Note In the P controller instruction 370 P1 is the amplification In the PID T1 controller P1 is the integral time PID controller and series connected P controller for setting up an amplification Index n 1 Index n P PID P 1 370 P Controller 375 PID T1 Controller Reference value O1 O1 Actual value I3 limit I4 MR 01 0 I4 MR 01 0
98. ar with two positions up and down is to be controlled by the function table The target position is defined via a toggle switch Each position is equipped with an initiator which informs the frequency inverter that the target has been reached As soon as the position is reached the frequency inverter is to stop and the respective LED top or bottom is to be switched on As soon as the drive starts again the LED is turned off Both positions are provided with a door which can be opened manually by the user As soon as one of the two doors is open the warning lamp top or bottom is pulsed on and off at an interval of 100 ms Note that the door open signals from the two doors are connected in series Hoist door Initiator top nig Upper platform door Initiator bottom Lower platform 148 VPLC PLC 08 10 Bonfiglioli Vectron Representation as state machine step 1 The requirements described above are shown in the following diagram as a state machine It must be considered that the state must be initialized first when the ACU is switched on or in the case of a reset In this example initialization is performed in order to switch to the correct state At first the initiators are evaluated If one of the initiators signals that the position has been reached the corresponding state is activated If no initiator signal is present the lower position is approached Toggle switch
99. ary quantity is referred to the type dependent overload current The constant value is applied to the input of the instruction 100 corresponds to the value of the overcurrent 08 10 VPLC PLC 39 Bonfiglioli Vectron 2387 INIT The status signal is TRUE for 64 ms after cut in of supply voltage or after start of the PLC functions Otherwise the signal status is FALSE The status signal cam be combined with Master Set and Master Reset inputs and is used for initializing the functions 2388 RESET The status signal is TRUE for 64 ms after cut in of supply voltage or after start of the PLC functions or after disabling of the output stages Otherwise the signal status is FALSE The status signal cam be combined with Master Set and Master Reset inputs and is used for initializing the functions 2389 IDLE The status signal is TRUE if the output stages are disabled 2390 Controller release The status signal is TRUE if the output stages are enabled and the magnetizing process has been completed flux forming finished drive working 2391 Controller release inverted Inverted status signal of Controller release 2392 Error acknowledgeable Status signal is TRUE if current error messages can be acknowledged 40 VPLC PLC 08 10 Bonfiglioli Vectron 3 2 2 Combining input buffer with inputs 3 2 2 1 Digital If the signal of a digital in
100. at specialized dealers and are exclusively intended for profes sional use as per EN 61000 3 2 Purposes other than intended may result in the exclusion of warranty The frequency inverters are also marked with the UL label according to UL508c which proves that they also meet the requirements of the CSA Standard C22 2 No 14 95 The technical data connection specifications and information on ambient conditions are indicated on the name plate and in the documentation and must be complied with in any case Anyone involved in any kind of work at the device must have read the instructions carefully and understood them before starting the work 1 3 Transport and Storage The frequency inverters must be transported and stored in an appropriate way During trans port and storage the devices must remain in their original packaging The units may only be stored in dry rooms which are protected against dust and moisture The units may be exposed to little temperature deviations only Observe the conditions according to EN 60721 3 1 for storage EN 60721 3 2 for transport and the marking on the packaging 08 10 VPLC PLC 7 Bonfiglioli Vectron The duration of storage without connection to the permissible nominal voltage may not exceed one year 1 4 Handling and Installation Warning Damaged or destroyed components must not be put into operation because they may i be a health hazard The frequency inverters are to be used in acc
101. bits of the output value Output OxFFFF Master Reset deletes all bits of the output value Output 0x0000 203 I4 4 MR Examples P2 I1 I2 P1 01 02 1 XOR 11 I2 OxFOOF OxOFOF OxFF00 OxOOFF 2 XOR I1 P1 OxFOOF i OxOOFF OxFOFO OxOFOF 3 XOR XOR I1 I2 P1 OxFOOF OxOFOF OxOOFF OxFFFF 0x0000 Re example 1 I4 1111 11 00 01 0 0 0 0 1 1 1 1 OxFOOF p o ololo i t1 10 0 0 0 1 1 1 1 OxOFOF I1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 O OxFFOO 5 11 5 210 Bit shift right input value 1 B b Master Set Master Reset I1 bitwise shifted by P2 inverted output Number of shifts Description The input value at I1 is shifted to the right bitwise by the number of shifts P2 Left side is filled with zeroes 08 10 VPLC PLC 129 Bonfiglioli Vectron Master Set sets all bits of the output value Output OxFFFF Master Reset deletes all bits of the output value Output 0x0000 Example P2 I1 O1 02 1 1 One shift OxFOOF 0x7807 Ox87F8 2 4 Four shifts OxOOFF OxOOOF OxFFFO 3 8 Eight shifts OxFFOO OxOOFF OxFFOO In example 1 I1 1 1 11 0 00 00 0 1 1 1 1 1x SHR b t O1 0 0 1 1 1 000 00 00 1 1 1 1 9o input value 1 Ih Master Set Master Reset
102. bsolute value non retriggerable 64 of three orthogonal components 96 retriggerable ssssss 62 of two orthogonal components 96 Superior Absolute value function 98 non retriggerable 63 Acknowledging an error 73 retriggerable eese 61 Actual value eeeeseeeeee 142 Description of system 10 atlalOg eire 144 D Flip Flop digita oe danean 142 Mastet 1 ose pen 57 Add two bits to a word 132 SUpDOGFiOE 1 eie dr Pega D p e reed 56 Addition eie tete 90 Differentiator eeeeeeeeneeeee 98 Kon 90 Digital Multiplexer Data Set Number 71 Analog hysteresis 82 Division Analog multiplexer 109 Constant variable 94 AND operation eene 50 Variable constant seses 94 Automatic mode sesesss 122 Matiables 1 anann 93 Average E OVEN Meara eee irren 106 Electrical Installation Average function sees 95 Salty 8 B Error messages eee 146 Bit functions for analog input values 125 Example Add two bits to a word 132 Ruri StOD itiiseste tii ete eiae 137 Bit AND NAND nennen 126 Examples Bit
103. buffer is written and the input buffer is up dated Jump functions enable branching off to certain instructions indices The instruction parame ters of the jump function additionally enable selective writing of the output buffer and updating of the input buffer 08 10 VPLC PLC 21 Bonfiglioli Vectron Digital signal sources for the inputs of digital instructions FT input buffer 1362 Digital inputs or Signal sources can be linked with inputs of functions within in the function table Indexi Index2 Index3 Index16 Global 70 71 72 7 Sources Fl release S2IND S3IND Off Factory setting P1343 I P1344 I P1345 I P1346 I P1347 I P1348 I P1349 I Function table P1350 I P1351 I Global 2401 2402 2403 2404 Sources for digital outputs global for further functions FT output buffer The Signal sources 2401 to 2416 are available generally global for further functions The Signal sources 2401 to 2404 are available generally global for digital outputs Selection of operation mode 80 83 for digital output gt The outputs of the logical functions can be linked with digital outputs or further functions Input buffer is updated Abbreviations used I Index of instruction 1 32 In Input of an instruction O1 O2 Outputs for combinations with other instructions or outputs for global combinations At first the output buffer is update
104. ct an input buffer for the PLC signal e Select a digital signal as the global source 18 VPLC PLC 08 10 9 Bonfiglioli Vectron Block Dialog window SPS Signal 2301 Frequency 1 Globale Quelle 10 Stator Frequency Y Assign an analog signal at the control terminals of the frequency inverter or an analog quantity frequency current voltage or percentage to an input of an analog function block e Select an analog quantity for the PLC signal e Select an analog signal of the frequency inverter as the global source SPS Signal 2621 Fixed val Perc 1 Globale Quelle Fixed val Perc 1 2 50 Enter a fixed analog value Block Dialog window Eingangssignal Einstellungen SPS Signal 2341 Actual Position m Festwert Assign the actual position value to an input of a function block e Select the position value for the PLC signal Eingangssignal Einstellungen SPS Signal 2661 Fixed val Position 1 z Fixed val Position 1 20 Assign a fixed position value to an input of a function block e Select a signal source for the fixed value for the PLC signal e Enter a fixed position value Block Dialog window lt DigOut Output Settings Digital cx Output Buffer 3 v indicates index already in use ox Abbrechen Write the output signal of a digital function block to the outp
105. d Then the input buffer is updated The values of the global sources are applied to the output buffer Then the global input values in the input buffer are updated 22 VPLC PLC 08 10 Bonfiglioli Vectron 2 6 Principle for analog functions The analog function processing principle is shown in the following diagram The analog input buffer comprises fixed values or PLC signals which can be assigned to global signal sources The values in the input buffer are available to the inputs of the instructions as sources Depending on the type of instructions two function block settings P1 and P2 are used for adjusting special instruction functions The outputs of the instructions can be used as inputs by other functions In addition the outputs can be used as a source for global variables The instructions are processed one after the other starting with instruction 1 When the processing cycle jumps back to start the output buffer is written and the input buffer is up dated Jump functions enable branching off to certain instructions indices The settings of the jump function additionally enable selective writing of the output buffer and updating of the input buffer Analog functions can process the following values Frequency Current Percent Voltage Position Positioning ramp gradient 08 10 VPLC PLC 23 Bonfiglioli Vectron Analog signal sources and fixed values for the
106. de 60 the unit of the times set in P1 and P2 is 62 rior min retrig f minutes min See chapter 4 6 1 gerable Output signal becomes TRUE with positive clock edge at input 1 or with negative clock edge at input 2 The time set in P1 is the On Monoflop Supe Time High and the time set in P2 is the ignore edge time Low 70 rior ms non The time is indicated in milliseconds ms Edges during the selected retriggerable ON time and the ignore edge time will be ignored TRUE at Superior Set input input 3 sets output TRUE TRUE at Superior Reset input input 4 sets output FALSE See chapter 4 6 3 Monoflop SUE As in operation mode 70 the unit of the times set in P1 and P2 is 71 rior s non seconds s See chapter 4 6 3 retriggerable Monoflop Supe As in operation mode 70 the unit of the times set in P1 and P2 is 72 rior min non f minutes min See chapter 4 6 3 retriggerable As long as input 1 is TRUE and input 2 is FALSE the set pulse pat tern is output The clock pattern is defined by the on time and the 80 Clock generator off time The time set in P1 is the on time High and the time set in Superior ms P2 is the off time Low The time is indicated in milliseconds ms TRUE at Superior Set input input 3 sets output TRUE TRUE at Superior Reset input input 4 sets output FALSE See chapter 4 6 5 Clock generator As in operation mode 80 the unit of the times set in P1 and P2 is 81 Superior s seconds
107. decimals For example Value 12345 123 45 1 2345 5 3 8 350 Integrator Integration quanti 1 0 0 2 Yo ty Yo O1 P1 tat 12 Start value inverted output 1 Integration time in ms denominator b Master Reset Master Set Description The input value at I1 is integrated The integration time constant P1 indicates how long it takes in the case of a constant input value until the output value reaches the input value 01 02 ridt 12 P1 If the integrator is to be stopped input 2 must be combined with the output and the Master Set input I3 must be activated Master Set TRUE sets the integrator to the start value I2 The start value can be defined via input I2 Master Reset TRUE sets the integrator to 0 Master Reset has priority over Master Set t I i 1 i 2 i 3 wa nd 1 1 0 0 0 1177 7 i 2 2 1 0 5 0 33 I I I 1 1 1 1 I I a a a Or 3 3 3 32 1 Biden 4 1 6 3 2 I I I 1 1 ee E S RIE s 1 Y 35 233 Oi I I I I 1 i i i i 6 0 8 4 2 67 Pisces ose I I I I 1 I I I I I I I I 1 1 t sot I I I I Note Percentages 96 have two decimals For example Value 12345 123 45 1 2345 98 VPLC PLC 08 10 Bonfiglioli Vectron 5 3 9 351 Differentiator D element dli Differentiation quan o o1 p1 x 9H bi dt tity 9o inverted output 1 Derivative action time in ms Master Reset
108. division The input value at I1 is multiplied by the input value at I2 and the result is divided by the input value at I3 See chapter 5 3 4 340 Average The average is calculated from the input values at I1 I2 and I3 See chapter 5 3 5 341 Absolute value The absolute value is formed from the orthogonal square angle 2D vector input values at I1 and I2 See chapter 5 3 6 342 Absolute value The absolute value is formed from the orthogonal square angle 3D vector input values at I1 I2 and I3 See chapter 5 3 7 350 Integrator The input value at I1 is integrated See chapter 5 3 8 351 Differentiator The input value at I1 is differentiated See chapter 5 3 9 Absolute value 360 function The absolute value of the input value at I1 is calculated See chapter 5 3 10 361 SQR 11 The input value at I1 is squared See chapter 5 3 11 362 Cube I1 The input value at I1 is cubed See chapter 5 3 12 363 Square root The square root is calculated from the input value at I1 See chapter 5 3 13 364 Modulo Multiplication and division O1 result O2 modulo See chapter 5 3 14 Controller Analog functions 370 P controller The control deviation I1 I2 is multiplied by the amplification P1 See chapter 5 4 1 PI Controller rS The control deviation I1 I2 is multiplied by the amplification P1 an the I component total of con
109. e 1 2401 Start Anticlockwise 69 2401 PLC Output buffer 1 4 2404 Error acknowledgment 103 2404 PLC Output buffer 4 Signal source for digital Example of digital output terminal output terminal 1 80 AgilE Operation mode OUTID X13 5 531 80 PLC Output buffer 1 4 83 ACU Operation mode digital output 1 530 83 PLC Output buffer 4 08 10 VPLC PLC 13 Bonfiglioli Vectron 2 2 8 Analog output block Combining an analog function block output with a device function or an analog output termin al Drag a block Analog Out from the library to the function block output Double click the block Analog Out Select an output buffer Example 2 2502 AgilE Reference frequency source 475 2502 PLC output frequency 2 Signal source for analog Example of analog output terminal output terminal 1 61 AgilE Analog Source MFOIA 553 61 Abs value PLC outp percent 1 2 2 9 Example Digital Analog Inputbuffer1 n Run Signal as Input Signal Analogue input MFI1A as input value Percentage 1 Output O1 via output buffer Bool1 Output O1 via buffer Percentage 1 Per centi 2 2 10 Syntax check Start the syntax check by clicking button Vl In the syntax check window click on the error message in bottom area The cause of the error is marked in the editor window 2 2 11 Translation and download to frequency inverter Click b
110. e adjusted The amplification P1 is set to the fixed value 1 In order to set up another amplification a P controller instruction 370 P controller must be connected to the input of the PID T1 controller Note In the P controller instruction 370 P1 is the amplification In the PID T1 controller P1 is the integral time 104 VPLC PLC 08 10 Bonfiglioli Vectron PID controller and series connected P controller for setting up an amplification Index n 1 Index n P PID P 1 370 P Controller 374 PID T1 Controller Reference value O1 O1 Actual value I3 limit I4 MR 01 0 I4 MR 01 0 P1 Amplification P1 Reset time ms P2 Rate time ms Index n 1 Index n 01 O02 Pi x 1 12 1 4 Pint JI 4 2 4 dt P144 xP2p ina na n e Set amplification in P controller e Set integral time and derivative action time in PID controller Note If the amplification of the PID controller is to be 1 no P controller must be connected in series If a value of 100 0096 is applied to the input in the form of a jump the output value is the total of the three components P component 100 00 constant I component Ramp reaching the value of 100 00 after integral time P1 D component Pulse of length of a sampling step and level TZ 100 T1 Abtastzeit If the pulse level exceeds the limitation of the output value the pulse will be output longer The output value is limited to the v
111. e edge time min ON time ms ignore edge time ms ON time s ignore edge time s 48 VPLC PLC 08 10 Bonfiglioli Vectron i i Monoflop min non retriggerable ON time min ignore edge time min im l Clock Generator ms ON time ms OFF time ms ai _ Clock Generator s ON time s OFF time s F i Clock Generator min ON time min OFF time min Jump function Jump target 1 Jump target 2 Note Operation modes lt 40 to 82 use Superior inputs operation modes lt 140 to 182 use Master inputs as overriding inputs Note In all other instructions not listed in the above table the setting of P1 and P2 does not affect the instruction 4 3 Boolean operations The following table shows the logic combinations of the implemented Boolean functions Logic Os are indicated as dots Output depending on logic function OR XOR1 XOR1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 i 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 08 10 VPLC PLC 49 Bonfiglioli Vectron 4 3 1 1 AND operation input value 1 b O1 AND 11 I2 I3 14 input value 2 negated output O2 O1 input value 3 input value 4 Description The inputs are AND combined with one another The inputs of the instruction are the assigned signal sources Output is TRUE if all inputs are TRUE As soon as one inpu
112. e input value at I1 is divided by the product from input values I2 and 13 n 1 025 CHATTE The result of the division is limited to P2 and P1 max to 327 6790 O1 327 67 6 5a ie Eon P1 SEETEREPPDUEEI EN 0 p2 L MMMII 327 67 eee P2 is the negative limit P2 even if only a positive value can be entered for P2 As long as status TRUE is present at I4 Master Reset the output value O1 is 0 Signal source 9 Zero or the value 0 at input I2 or I3 deactivates these inputs In this case no division by the input values at I2 and I3 is carried out The input values are processed as I2 1 and I3 1 Example 11 14000 140 00 O1 140 00 130 00 32 33 1223000 30 00 1 4000 0 3000 0 3233 13 3233 32 33 14434 47 limit 327 67 Note Percentages have two decimals For example Value 12345m 123 45 1 2345 If EI2 or I3 has value 0 output O1 has value I1 94 VPLC PLC 08 10 Bonfiglioli Vectron 5 3 3 2 337 Division by constant Input numera tor I PI inverted output 1 Constant denominator upper and lower limit O1 Master Reset Description The input value at I1 is divided by the parameter value P1 O1 02 a P1 The result of the division is limited to P2 max to 327 67 As long as status TRUE is present at 14 Master Reset the output value O1 is 0 Example I1 14000 140 00 O1
113. e range 0 00 327 6796 I1 I2 O1 02 13 I4 I1 I2 I3 I4 Function 1 0 1 X Stopwatch runs forward 1 0 0 X Stopwatch runs backward 1 0 x 021 Reset to start value P1 1 0 x 120 Start after reset Examples If 11 release TRUE I2 release inverted FALSE I3 counting direction TRUE I4 re set FALSE the internal counter long is increased by one every millisecond In order to calculate the output value this value is divided by P2 P2 1000 O1 is increased by 0 01 every second 1 P2 1 time one second 1000 ms t 1s 1000ms Output value O1 Fo RS x o giis 10 After one second the output reaches the value 10 2 P2 1000 time one hour 3600 s t 3600s 3600000ms Output value O1 36 P2 P2 1000x100 s 0 O1 is increased by 0 0196 every second After one hour the output reaches the value 36 5 10 Positioning functions The positioning can be controlled directly from the PLC functions Via the control operation mode of the positioning the control can be handed assigned to the PIC functions The position ing can be controlled in the settings for parameter Configuration 30 x40 In these configu rations parameter Operation mode 1221 must be set to 1000 Control via function table in order to control the positioning via the PLC functions Output O2 O1 High word Low word outputs the actual position In operation mode 507
114. ead of percentages this will be interpreted as follows 22000 u x FALSE x10 22 1200ux10 1 2 Ol 367 67 Begrenzung O2 0 33 18 3333 1833 33 Parameters P1 and P2 can also be used to scale the result O1 Result in front of decimal point scaling P1 division O2 Result behind decimal point scaling P2 multiplication 5 4 Controller Controllers can be built up from individual elements This can be used for limiting the output values of the individual elements 5 4 1 370 P controller Input reference value Input actual val ue P amplification x xx Master Reset Limitation of output value 99 O1 P1x 1 12 inverted output 1 Description The control deviation I1 12 is multiplied by the amplification P1 O1 02 P1 x 11 12 The output value is limited to P2 As long as status TRUE is present at I4 Master Reset the output value I1 is 0 Note Percentages 96 have two decimals For example Value 12345m 123 45 1 2345 The amplification is entered with two decimals displayed value 123 function value 1 23 102 VPLC PLC 08 10 Bonfiglioli Vectron 5 4 2 371 PI controller Tn in milliseconds Input reference value Input actual val ue Limitation of out put values Master Reset Integral time in ms _ Pl O1 P1x I 12 55 t 12 dt inverted output 1 P ampl
115. ecify a positive offset is added to the re sult and a negative offset is subtracted from the result respective ly See chapter 5 3 1 1 Addition The input values at I1 Long and I2 Long are added up and the 331 position with input value I3 Long is subtracted offset In addition an offset can be specified via P See chapter 5 3 1 2 332 Multiplication The input values at I1 and I2 as well as parameter value P1 are mul tiplied See chapter 5 3 2 1 The input values at I1 and I2 as well as parameter value P1 are mul 333 Multiplication tiplied by long result The result is divided into low word and high word and output at out puts O1 and O2 See chapter 5 3 2 2 08 10 VPLC PLC 31 Bonfiglioli Vectron 334 Multiplication The input value at I1 is multiplied by the parameter value P1 and by fraction divided by parameter value P2 See chapter 5 3 2 3 Multiplication The input value at I1 long is multiplied by the parameter value I2 335 long with per percentage and divided by parameter value P2 See chapter cent 5 3 2 4 vnd The input value at I1 is divided by the input value at I2 and the input 290 Division value at I3 See chapter 5 3 3 1 337 Division by The input value at I1 is divided by the parameter value P1 See chap const ter 0 338 Reciprocal The parameter value P1 is divided by the input value at I1 See chap ter 5 3 3 3 Multiplication 339 and
116. ed O1 02 11 Example I1 130 0096 O1 I1 169 00 The output value is limited to the adjusted value of P2 As long as status TRUE is present at 14 Master Reset the output value O1 is 0 Note Percentages have two decimals For example Value 12345m 123 45 1 2345 5 3 12 362 X Cube I1 Input value 01 11 inverted output 1 Master Reset Limitation of output value Description The input value at I1 is cubed 01 02 113 Example I1 130 0096 O1 I1 219 70 The output value is limited to P2 As long as status TRUE is present at I4 Master Reset the output value O1 is 0 Note Percentages 96 have two decimals For example Value 12345m 123 45 1 2345 5 3 13 363 VX square root of I1 Input value 996 O1 H inverted output 1 Master Reset Limitation of output value Description The square root is calculated from the input value at I1 O1 02 VIL 100 VPLC PLC 08 10 Bonfiglioli Vectron Note Since the square root of a negative number has no real result the square root of the absolute value of the input value is worked out and the sign is applied to the output value I1 gt 01 Jrr1 Example Positive input value I1 130 00 O1 114 02 Negative input value I1 130 00 O1 114 02 The output value is limited to P2 As long as status TRUE is present at 14 Ma
117. ed via parameter FT Write Index FT Table Item 1341 The chosen index corresponds to a column in the func tion table The settings of parameters 1343 to 1351 are applied to the selected index of the function table Via parameter FT7 Read Index FT Table Item 1342 the values of a selected index can be read from the function table No Description Min Max Fact sett 1341 FT write index FT table item L0 65 1 1342 FT read index FT table item 0 6 1 Settings for fixed parameterization Settings for non fixed parameterization non volatile volatile 0 all instructions in EEPROM 33 all instructions in RAM 1 32 individual instructions in EEPROM 34 65 individual instructions in RAM Note The settings 0 or 33 for FT Write Index FT table Item 1341 change all indices of a para meter in the EEPROM or RAM In the case of non volatile storage 0 32 the changed values are still available when power supply is switched on again In the case of volatile storage 33 65 the data is only stored in RAM If the unit is switched off this data is lost and the data required are loaded from EEPROM Caution Writing of the EEPROM is restricted to approx 1 million times If this number is exceeded the device may be damaged Definition Instruction RAM instruction EEPROM 33 134 VPLC PLC 08 10 Bonfiglioli Vectron Write index and read index for FT instructions in fu
118. en reached yet The motion block is restarted 1 1 Start motion block P1 and wait until positioning is finished 0 O The target position is not changed 0 1 The target position can be changed by other instructions if no positioning is ac tive 122 VPLC PLC 08 10 Bonfiglioli Vectron 5 10 2 502 Start motion block in automatic mode Target position offset Pos Actual posi Low word tion High word E Number of motion block Release index motion block ta ble b Wait until positioning is finished Description The motion block selected with P1 is started Repetitions and next motion blocks are executed If a motion block is still running it will be stopped The position value set at input I1 target position offset is added to the target position set in the motion block Configuration 30 x40 Instruction Motion Block P1 Index Target Position I1 Target Position Distance 1202 Input I1 can be combined with position values long The function is only executed if input I3 release is set If input I4 wait is set further instructions will only be processed when the target position has been reached The process cannot be stopped by other instructions or resetting I3 502 I1 Pos Offset O1 I3 Enable I4 Wait 02 P1 Index Motion blocks table I3 I4 Function 1 0 Start motion block P1 w
119. entage parameter b I1 int b inverted output 1 Parameter number i Data set 0 9 or index be used for any other int parameter types 405 I1 4 I2 Delete buffer O1 FT instruction 1343 I3 Write enable Parameter Parameter 02 I4 Wait 5 7 1 6 P1 406 Write position parameter Low word igh word Input value b Write enable Wait until writing is finished b O1 D2 I1 b inverted output 1 Parameter number i Data set 0 9 or index Description The input value is not changed and written as long parameter In this way this function can be used for any long parameter types O1 I2 I1 High word Low word 114 VPLC PLC Bonfiglioli Vectron ms un m m m m eo e e eo e e e o a a ms N m m Cx eo a mm eo eo e eo a e E NJ e e e a m eo eo e eo e e na a eo 0 0 0 0j 0 0 1 1 1 1 For the bits example values are entered here 406 I1 Pos Low word I2 Pos High word Ol FT instruction 1343 I3 Delete buffer Parameter Parameter 02 I4 4 Wait P1 5 7 1 7 407 Write long parameter Low word b O1 D2J I1 High word b inverted ou
120. equency inverter Stop the function block program Syntax check Stop PLC Start PLC Start the function block program File 2 New File gt open File 2 Save Edit 2 Undo Edit 2 Redo PLC gt Translate and down load to frequency inverter 08 10 VPLC PLC 15 Bonfiglioli Vectron 2 3 2 Other menu commands Save a VPLC file under a new file name File 2 Save as Export a VPLC file to a VCB file The VCB file con taining the parameter values created by the PLC functions can be edited in VPlus File gt Export to VCB Opens the print setup window Prints the editor area File gt Print Adjust the page size of the editor File gt Page setup View the page as it will be when printed File gt Print preview Select all objects in editor Edit gt Select all Opens the VPLC setup window Interface VPlus auto is displayed if VPLC was started in VPlus default setting COM The available in terfaces are displayed Only if VPLC is started without VPlus Language Select the language of the user environment and the menu com mands Apply texts from The language selected at inverter the frequency inverter is applied to the signal sources in VPLC Show parameter values The values of fields P1 and P2 of the function block settings will be displayed below the function block Edit gt VPLC setup Sheet size
121. f an instruction are indicated by parameter PLC Actual values function 1356 From left to right the following is displayed state of PLC or function table e g started stopped Index number of selected instruction vie PLC read index PLC input buffer 1361 Inputs of selected instruction Outputs of selected instruction index number of last processed instruction Inputs of last processed instruction Outputs of last processed instruction The states of the function table are R Running function table or PLC started S Stopped function table or PLC stopped U Updating input and output buffer are being updated E Empty function table or PLC is empty I Initialization Example i T RO1 Ostet al R State of function table 01 03 Index of instruction selected via last processed FT read index FT input buffer instruction 1361 1 ot 1234 1234 FT inputs FT inputs bs u 12 12 FT outputs FT outputs FALSE I TRUE Note For information on other actual values refer to the operating instructions of the frequency in verter 144 VPLC PLC 08 10 Bonfiglioli Vectron 7 2 Actual values of analog functions The following parameters indicate the actual values ofthe four indices of the analog input buffer ofthe four signal sources of the analog output buffer in the case of parameter
122. f the jump function the input buffer and output buffer can be updated either separately or jointly This enables setting the digital output signals at certain times selected by the user during the processing Note The input and output buffers are set and written during the return jump This is done in one processing cycle The output buffer is written first after that the input buffer is set 2 8 Input buffer and output buffer for analog signals The input buffer is updated and the output buffer is written at a defined point of time In this way it is ensured that the processing within a cycle in performed based on the same input data and inconsistent statuses are avoided Consistent values values of identical points of time are processed Clear arrangement thanks to limited number of signals Conversion to percent values functions process percent values Four indices In order to write an analog output you will have to select an output buffer first Then the sig nal must be assigned to the device function For analog outputs of the device the following operation modes are available 61 Abs value PLC outp percent 1 62 Abs value PLC outp percent 2 161 PLC outp percent 1 162 PLC outp percent 2 Based on these values the input buffer is read at the start of a cycle and kept in the memory until the end of the cycle Then the instructions are processed The output buffer is written at
123. figlioli Vectron The following diagram is obtained for the signals of the function table 2004 1 2004 1 2006 1 2005 0 2002 1 NoN Initiator In the first step the states and transitions are translated into instructions Setting state outputs The easiest way to set a digital signal independent of one or several input signals is using a Boolean operation In this application an OR instruction is used and an input is set to TRUE In this way FT target output 1 1350 is set to TRUE 1 and FT target output 2 1351 is set to FALSE 0 FT Instruction 1343 FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT target output 1 1350 FT target output 2 1351 2 OR 6 TRUE 7 FALSE 7 FALSE 7 FALSE 2411 FT Output buffer 11 2402 FT Output buffer 2 For states 3 to 5 instructions can be created in the same way Clock generator state 3a FT instruction 1343 FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT Parameter 1 1348 FT Parameter 2 1349 80 Clock generator 2003 Input buffer 3 7 FALSE 7 FALSE 7 FALSE 100 100 The clock generator of state 5a is created in the same way as 3a 08 10 VPLC PLC 151 Bonfiglioli Vectron Transition from state 2 t A o state 3 FT instruction 1343 FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT Parame
124. ger Function ue User error P1 I1 I2 I3 14 o 1 0 0 0 1 No error cut off 0 1 0 0 2 0 0 1 0 3 0 0 0 1 4 1 1 0 04 0 1 Shut down and error cut off 0 1 0 0 2 0 0 1 0 3 0 0 0 1 4 2 1 0 0 0 1 Emergency stop and error cut off 0 1 0 0 2 0 0 1 0 3 0 0 0 1 4 3 1 0 0 0 1 Error cut off immediately 0 1 0 0 2 0 0 1 0 3 0 0 0 1 4 One of the following error messages is displayed after a user error was triggered Error F3031 Description User error 1 PLC F3032 User error 2 PLC F3033 User error 3 PLC F3034 User error 4 PLC The inputs are evaluated with priority I1 I2 I3 I4 For example I1 has priority over I2 if both inputs are TRUE 72 VPLC PLC 08 10 Bonfiglioli Vectron 4 9 2 96 Acknowledging an error b Input error reset b Message can be acknowl edged b Input error reset b inverted output O1 Description Output 1 becomes TRUE if an acknowledgeable error message is present With each positive edge at input 1 or negative edge at input 2 an attempt is made to acknowl edge an present error message If the message cannot be acknowledged yet there is no reaction Reset Error canbe acknowledged LOFT LH Al 1 Te 12 A2 O1 11 I2 Function 1 DS x Acknowl edge fault 0 None 1 x 190 Acknowl edge fault 0 None I1 T Automatic Error Acknowledg ment
125. he inverted value of O1 The output can be combined with inputs for position values Long The function can also be used for ramp settings in configurations x40 5 2 10 322 Min Max in time window 9o input value 1 b FALSE Min TRUE Max b Master Reset Description The minimum input value at I1 determined over a certain period of time is output to Output O1 if I3 is TRUE and 14 is FALSE Or The maximum input value at I1 determined over a certain period of time is output to Output O1 if I3 is FALSE and 14 is FALSE Or The current input value at I1 is output to O1 if I4 is TRUE The signal status at I3 determines if the minimum or maximum input value is output FALSE must be present at I4 The period of time for the minimum or maximum value measurement is determined by a signal at I4 The measurement of the maximum or minimum value starts with a negative edge at I4 The measurement is restarted with each negative edge I3 I4 O1 0 0 Minimum 11 1 0 Maximum I1 X 1 Ol Note Percentages have two decimals For example Value 12345 123 45 1 2345 5 2 11 323 Min Max for positions Long in time window Pos input value 1 Low word b FALSE Min TRUE Max b Master Reset Description The minimum position value at I1 determined over a certain period of time is output if I3 is TRUE and I4 is FALSE Or The maximum position va
126. ification Description The control deviation I1 I2 is multiplied by the amplification P1 The I controller adds up the control deviation over time The I component is added When the integral time has elapsed the I component reaches the same value again so that the output value is doubled PL 01 02 PL I 2 55 f t1 12 dt The output value is limited to the value at input I3 As long as status TRUE is present at 14 Master Reset the output value I1 and the I compo nent are 0 Note Percentages have two decimals For example Value 12345m 123 45 1 2345 5 4 3 372 PI controller Tn in seconds Input reference Pi O1 P1 x I1 12 I1 I2 dt value i B E l u actual val 96 inverted output 1 Limitation of out P amplification put values Master Reset i Integral time in s Description The control deviation I1 I2 is multiplied by the amplification P1 The I controller adds up the control deviation over time The I component is added When the integral time has elapsed the I component reaches the same value again so that the output value is doubled PL O1 02 P1x Il 2 a I2 dt The output value is limited to the value at input I3 As long as status TRUE is present at I4 Master Reset the output value O1 and the I compo nent are 0 Note Percentages 96 have two decimals For example Value 12345m 123 459
127. iglioli Vectron 314 Window comparator V C absolute value comparison of variable to con stant Description Via P1 and P2 a value range window is adjusted and it is checked if the absolute value of I1 is within this range O1 is TRUE if I1 is in the range of from P2 to P1 O1 is FALSE if I1 is outside of this range The comparator has three working ranges Range 1 P1 lt I1 O1 FALSE Range 2 P2 lt IH lt P1 O1 TRUE Range3 Ii lt P2 O1 FALSE 02 Ol Special case P2 negative window is greater than P1 positive window limits exchanged O1 is TRUE if T1 lt P1 or Ii gt P2 O1 is FALSE if I1 is in the range of from P1 to P2 window The output value can be changed by means of the two Boolean inputs Master Set sets output O1 to TRUE Master Reset sets output O1 to FALSE Master Reset has priority over Master Set 313 P2 I1 P1 314 P2 I1 P1 Note Percentages 96 have two decimals For example Value 12345m 123 45 1 2345 86 VPLC PLC 08 10 Bonfiglioli Vectron 5 2 8 320 Min Max input value 1 Min or Max 11 12 P1 P2 input value 2 O1 inverted FALSE Min TRUE Max Constant value P1 Master Reset 96 Constant value P2 Description Based on variables I1 and I2 as well as the constants P1 and P2 the minimum or maximum value is determined and output at O1 The maximum value is output if I3 is TRUE The minimum
128. industry mobile machinery and renewable energy applications since 1956 www bonfiglioli com Bonfiglioli Riduttori S p A tel 39 051 647 3111 Via Giovanni XXIII 7 A fax 39 051 647 3126 40012 Lippo di Calderara di Reno bonfiglioli bonfiglioli com Bologna Italy www bonfiglioli com VEC 701 RO
129. ing S2IND 1 S4IND 1 S3IND 1 Warning signal Position top S3OUTD 1 Start CW 068 0 Solution NoN initiator Travel down S30UTD 0 Start CCW 069 1 S5IND 0 For assignment of the ACU signals and the input buffer of the function table the following pa rameterization is required 2002 FT Input Buffer 1362 Index 2 71 S2IND 2003 FT Input Buffer 1362 Index 3 72 S3IND 2004 FT Input Buffer 1362 Index 4 73 S4IND 2005 FT Input Buffer 1362 Index 5 74 S5IND 2006 FT Input Buffer 1362 Index 6 274 SSIND inverted Parameterization deviating from factory settings For assignment of the ACU signals and the output buffer of the function table the following parameterization is required Operation mode digital output 1 530 Operation mode digital output 3 532 Op Mode EM SIOUTD 533 MFO1 Operation mode 550 MFO1 Digital Operation 554 Start Clockwise 068 Start Anticlockwise 069 2401 FT Output buffer 1 2402 FT Output buffer 2 2404 FT Output buffer 4 1 Digital output 2403 FT Output buffer 3 2410 FT Output buffer 10 2411 FT Output buffer 11 To enable easy checking of the transition Top Position gt Down the inverted signal of signal S5IND in the input buffer is assigned For easier parameterization the names of the states used so far will be replaced by numerical values 150 VPLC PLC 08 10 Bon
130. inputs of analog instructions and the output signals of the instructions Input buffer PLC Signal Analogue global signal sources of the inverter Fixed values Instructions Output buffer 1 4 Output via an analogue output 61 Value PLC Output Percent 1 62 Value PLC Output Percent 2 161 or 162 signed 25xx Link with functions Abbreviations used I Index of instruction 1 32 In Input of an instruction O1 O2 Outputs for combinations with other instructions or for global combinations e g output via an analog output of the frequency inverter 24 VPLC PLC 08 10 Bonfiglioli Vectron 2 7 Input buffer and output buffer for digital signals Input buffer The input buffer is updated and the output buffer is written at a defined point of time In this way it is ensured that the processing within a cycle in performed based on the same input data and inconsistent statuses are avoided Output buffer For digital outputs control terminals of the device signal sources 2401 to 2404 are available corresponds to operation modes 80 83 for digital outputs Operation modes 2401 to 2416 are available to other functions e g comparators At the start of a cycle the input buffer is read and kept in the memory until the next return jump Then the instructions are processed The output buffer is written at the end of the cycle and is available in the global sources after that By selective use o
131. ions 1 ee eeeeeieee einen nenne nennen nnnm nn anna nnn nhan ann 90 5 3 1 Addition and subtraction eeessseeeseseeeeee nene nennen nennen nennen nnn nnn 91 5 3 1 1 330 Add O1 2 O2 211 1I2 I3 P1 P2 seeeeeeeeeeeeeeeeee nennen nnn nnn 91 5 3 1 2 331 Addition position with offset ccccceccseeeeeseseeeeesssaeeeesssaeeenenaaeeeeenes 91 5 3 2 Mu ltipliCatiOH spinining andreaaa ERE Re ev A D pCa antes paier E eee ee ed 92 5 3 2 1 332 Multiplication 5 1 eee e eerie a aa aa 92 5 3 2 2 333 Multiplication Long r SuUlt cccccssseeeeeeseeeesseseeeesasaeeeesesaaeeeeesaaaenes 92 5 3 2 3 334 Mult by TraGtlon iecore ee etenim teri tigen ER ER DURO 93 5 3 2 4 335 Mult long percent icon teer ceni eee e veuve snes Re ERE 93 5 3 3 BIE EAE EEN PTET TAT EIE 94 5 3 3 1 336 DIVISION si eoe etc oet oet eene Obed ror eee beat bested adh dais bnt SEE 94 5 3 3 2 337 Division by CONStANC is mrin ceres cede caen eo dhe euer D eo tee eio tacit 95 5 3 3 3 338 Division P1 by I1 reciprocal eeeeeeennm mnn 95 5 3 4 339 Multiplication and division eeseeeeeeennnmmnmn 96 5 3 5 340 Average function inienn naaraana aea aaraa Kaa nennen aA Aa nnn nnn nnn 96 5 3 6 341 Absolute value of two orthogonal components 2 D vector 97 5 3 7 342 Absolute value of three orthogonal components 3 D vector
132. iption The input value at I1 is filtered The average of the current input value and the two previous input values is output In this way individual input spikes are suppressed Master Set TRUE sets the output to the start value The start value can be defined via input I2 Master Reset TRUE sets the output to 0 Master Reset has priority over Master Set I3 I4 O1 0 0 I1 average of last 3 values 021 0 I2 X 021 0 SS Selection 12 SUDE VAG middle value t I1 O1 I3 MS O1 12 I4 MR 01 0 us Note Percentages 96 have two decimals For example Value 12345m 123 45 1 2345 08 10 VPLC PLC 109 Bonfiglioli Vectron 5 6 Analog switch 5 6 1 390 Analog multiplexer data set number input value 1 I1 I2 13 or I4 input value 2 inverted output 1 input value 3 input value 4 Description Depending on the active data set parameter active data set 249 one of the input values is output I1 I2 O1 I3 I4 Active data set 249 O1 1 I1 2 I2 3 I3 4 I4 Note Percentages 96 have two decimals For example Value 12345 123 4596 1 2345 5 6 2 391 Analog changeover switch input value 1 I1 I2 P1 or P2 input value 2 inverted output 1 Selection of value 1 or Fixed value 1 value 2 Selection of I or P Fixed value 2 Description
133. ith repetitions and next motion blocks Stopping by oth er instruction is possible The target position can be changed by other instruc tions even if the target position has not been reached yet The motion block is restarted 1 1 Start motion block P1 with repetitions and next motion blocks and wait until positioning is finished 0 O The target position is not changed 0 1 The target position can be changed by other instructions if no positioning is active 5 10 3 503 Stop motion block Pos Actual posi Low word Pos tion High word lb Release Wait until drive has stopped 08 10 VPLC PLC 123 Bonfiglioli Vectron Description The current motion block is stopped if the release at input I3 is set The drive is stopped If the release at I3 is reset the stopped motion block is continued and repetitions and next motion blocks are executed If input I4 wait is set further instructions will only be processed when the drive has come to a standstill The process cannot be stopped by other instructions or resetting I3 The instruction is only executed if input I3 release is set 503 O1 I3 Enable I4 1 Wait 02 w A Function Stop motion block and stop drive Wait until drive has stopped m OoOLmo Continue motion block 5 10 4 504 Continue motion block 5 Pos _ Actual posi Low word
134. ization using the function table the signal sources assigned to parameters PLC target output 1 1350 or PLC target output 2 1351 Parameters PLC actual frequency value from P 1379 PLC actual current value from P 1380 PLC actual percentage from P 1381 PLC actual voltage eff from P 1382 PLC actual voltage sp from P 1382 PLC actual value general from P 1383 PLC actual output frequency 250x 1401 1402 1403 1404 1405 1406 No Parameters No 1400 PLC actual output current value 251x PLC actual output percentage 252x PLC actual output voltage eff 253x 1407 1408 1409 PLC actual output voltage sp 253x 1410 PLC actual output general 255x 1411 PLC actual value flag 256x 1412 Example Actual value display parameterization using the function table Vtable Function Table Input Buffer analog FT input buffer frequency 1379 Function Table FT target output 1 1350 j Parameter FT Act Val Freq from P 1379 1400 FT Act Val Outp Freq 250x 1406 Index 2 i 10 Stator Frequency Index 1 2504 FT Output Frequency 41 0 00 Hz 115 00 Hz 0 00 Hz 0 00 Hz bee 0 00 Hz 0 00 Hz 0 00 Hz 5 00 Hz The parameter names may differ from the names shown depending on the device series The parameter numbers are identical 08 10 VPLC PLC 145 Bonfiglioli Vectron 7 3 Signals for digital outputs of device The following output signals of the can be as
135. ll parameters of the frequency inverter This is useful if the parameter is not connected to a source Since the read access is effected to the non realtime system of the frequency inverter an instruction may take longer than 1 ms The in struction is processed for the duration of the parameter access even if this takes longer than 1 ms If a non permissible data set or index is selected it will be replaced by one of the following data sets or indices Instead data set 1 is used i Instead index 1 is used Daa geru 1 4 Value of data set 1 4 1 max index Value from index 1 max Index Data seid Invalid value Instead data set 1 or index 1 is used Data set 0 All data sets are accessed from the RAM Internal access to the EEPROM and RAM is done in the same way 5 7 2 1 421 Read frequency parameter Parameter value Hz 9o inverted output 1 Release read access Parameter number i Data set 0 4 index Description The function reads the value of the parameter set up in P1 Parameter number and P2 Data set index The value is converted to a frequency value Via Input I3 read access is enabled 0 No read access 1 The parameter value is read The instruction is executed until the value is read 5 7 2 2 422 Read current parameter 9o Parameter value A inverted output 1 Release read access Parameter number i Data set
136. lue at I1 determined over a certain period of time is output if I3 is FALSE and 14 is FALSE Or The current position value at I1 is output if I4 is TRUE 88 VPLC PLC 08 10 Bonfiglioli Vectron The signal status at I3 determines if the minimum or maximum position value is output FALSE must be present at I4 The period of time for the minimum or maximum value measurement is determined by a signal at I4 The measurement of the maximum or minimum value starts with a negative edge at I4 The measurement is restarted with each negative edge at I4 I3 I4 O 0 0 Minimum 11 1 0 Maximum I1 X 1 IH Note Output value I2 is not the inverted value of O1 The output can be combined with inputs for position values Long The function can also be used for ramp settings in configurations x40 The availability of confi gurations x40 depends on the device series 08 10 VPLC PLC 89 Bonfiglioli Vectron 5 3 Mathematical functions 330 Addition and subtraction of 01 02 I1412 34 P1 P2 327 6796 input values and an offset Addition and subtraction of O I1 I2 I3 P 331 position values and offset O1 P1 Low word 0 27 1 Result Long O2 P2 High word 332 Multiplication of the input val O1 O2 I1xI2xP1 327 6796 ues and a factor 333 Multiplication of position val 02 O1 I1xT2 E T 0 2 1
137. lute value Signal source 2521 PLC output percent 1 is the output signal This sig nal source contains the output value of the instruction assigned to signal source 2521 Analog output signal of an instruction as an absolute value Signal source 2522 PLC output percent 2 is the output signal This sig nal source contains the output value of the instruction assigned to signal source 2522 Analog output signal of an instruction Signal source 2521 PLC output percent 1 is the output signal This signal source contains the output value of the instruction assigned to signal source 2521 Analog output signal of an instruction Signal source 2522 PLC output percent 2 is the output signal This signal source contains the output value of the instruction assigned to signal source 2522 146 VPLC PLC 08 10 Bonfiglioli Vectron 7 5 Signal sources for device function Signal sources of the instructions can be assigned to the device functions for further processing The values are updated when the output buffer is written Digital 2401 2416 PLC output buffer 1 16 Analog 2501 2504 PLC outp frequency 1 4 2511 2514 PLC outp current 1 4 2521 2524 PLC outp percent 1 4 2531 2534 PLC outp voltage 1 4 2551 2554 PLC outp user 1 4 2561 2564 PLC flag 1 4 7 6 Error messages of instruction 95 Triggering an e
138. mber 2 162 PLC outp percent 2 Example The output signal of an instruction is to be output via analog output MFO1A of the device VPLC Instruction analogue O1 Voltage buffer 1 02 VPlus Output via analogue output Analogue Mode 553 61 PLC Output Voltage 1 Operation Mode 550 2 Analogue Output via analogue output Analog Quelle MFO1A 553 61 PLC Output Voltage 1 Operation mode MFO A X13 6 550 10 Analog PWM MFO1A 08 10 VPLC PLC 45 Bonfiglioli Vectron 4 Description of digital functions In the following you will find explanations and examples of the individual digital functions The term digital function is defined as follows A digital function has at least one digital input value but not analog input value The output value is always digital The following symbols are used in the diagrams p C D i T2 FALSE TRUE 021 120 Qr P1 P2 Note edge evaluation level evaluation negated output Low state Representation of signal statuses in logic tables High state Representation of signal statuses in logic tables Low state Representation of signal statuses in function descriptions High state Representation of signal statuses in function descriptions any state Don t care 0 or 1 positive edge negative edge last state is maintained last state is negated toggle non nega
139. n is executed until the value is read 5 7 2 8 428 Read word parameter Parameter value inverted output 1 Release read access Parameter number i Data set 0 4 index Description The function reads the value of the parameter set up in P1 Parameter number and P2 Data set index The value is converted to a percent value Via Input I3 read access is enabled I3 0 No read access I3 1 The parameter value is read The instruction is executed until the value is read 5 8 Limiters 5 8 1 440 Limiter Const input value 1 O1 I1p 5 inverted output 1 upper limit Master Reset lower limit Description The input value at I1 is limited to P1 upper limit and P2 lower limit and output 01 15 As long as status TRUE is present at I4 Master Reset the output value O1 is 0 Note P2 can only be entered as a positive value O1 20 3 I P1 O1 P2 02 14 gt t 118 VPLC PLC 08 10 Bonfiglioli Vectron 5 8 2 441 Limiter variable input value 1 upper limit ra lower limit Master Reset Description The input value at I1 is limited to I1 upper limit and I2 lower limit and output I2 O1 114 As long as status TRUE is present at I4 Master Reset the output value O1 is 0 96 I2 piene inverted output 1 I1 I2 I3 I4
140. n of the power supply the motor may start unexpected ly if the auto start function is activated If staff is endangered a restart of the motor must be prevented by means of exter nal circuitry Before commissioning and the start of the operation make sure to fix all covers and check the terminals Check the additional monitoring and protective devices accord ing to EN 60204 and applicable the safety directives e g Working Machines Act Ac cident Prevention Directives etc No connection work may be performed while the system is in operation 1 6 1 Using external products Please note that Bonfiglioli Vectron does not take any responsibility for the compatibility of external products e g motors cables filters etc To ensure the best system compatibility Bonfiglioli Vectron offers components which simplify commissioning and provide the best tuning with each other during operation Using the device in combination with external products is carried out at your own risk 1 7 Maintenance and Service Warning VAN Unauthorized opening and improper interventions can lead to personal injury or material damage Repairs on the frequency inverters may only be carried out by the manu facturer or persons authorized by the manufacturer Check protective equipment regularly Any repair work must be carried out by qualified electricians 1 8 Disposal The dispose of frequency inverter components must be carried out in accordance
141. nction table for parameters 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 i Parameter i FT Write index FT table item 1341 i FT Read index FT table item 1342 i FT instruction 1343 i FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT Parameter 1 1348 Funktionentabelle Index1 Index 2 F T Parameter 2 1349 FT instruction 1343 2 OR 1 AND i FT target output 1 1350 FT input 1 1344 i FT target output 2 1351 FT input 21345 i FT actual values output buffer 1357 FT input 3 1346 FT actual values input buffer 1358 FT input 41347 pre E RC MU ME IPAE MCA E FT Parameter 1 1348 FT Parameter 2 1349 FT target output 1 1350 FT target output 2 1351 y EEP OA A E EEE E AEE EE EEE 6 1 2 Write index and read index for the digital input buffer Via the write and read indices the index of the Function table input buffer to be read or writ ten is specified Write index and read index for parameterization and reading of Function table input buffer via software VPlus The Function table input buffer can be parameterized in the user interface VPlus or in the function table VTable In the user interface VPlus an index of the input buffer can be created via parameter FT Write Index FT Input Buffer 1360 The chosen index corresponds to a col umn in the Function table Input buffer and thus an index of parameter FT Input Buffer 1362 The setting selec
142. nections of function blocks or inputs and outputs by arrang ing them on behind the other Correct connection Incorrect If the wire is shown in grey after the combination the combination must be checked 12 VPLC PLC 08 10 Bonfiglioli 2 2 5 Digital input block Combining a digital function block input with a digital input terminal or a frequency inverter control signal Drag a block DigIn from the library to the function block input Double click the block DigIn Select an input buffer for the PLC signal As the global source select the digital input or control signal to be applied to the functional module input 2 2 6 Analog input block Combining an analog function block input to a analog input terminal or a frequency inverter signal Drag a block Analog In from the library to the function block input Double click the block Analog In Select a physical quantity or percent for the PLC signal Select percent if a signal at the analog input terminal of the frequency inverter is to be applied to the function block input As the global source select the signal to be applied to the functional module input 2 2 7 Digital output block Combining a digital function block output with a device function or a digital output terminal Drag a block DigOut from the library to the function block output Double click the block DigOut Select an output buffer Exampl
143. ning yes 0 1 no x 0O yes 1 Wait 5 11 Bit functions for analog input values Each individual bit of input 1 is combined with the corresponding bits of input 2 and parame ter 1 if available to the selected function The result is saved in the corresponding bit of the output value For example bit 3 of the output value depends on bit 3 of input value 1 and bit 3 of input value 2 and Bit 3 of parameter 1 Parameter 2 indicates of input value I1 is to be combined with input value I2 or parameter P1 P2 1 Combination of input value I1 with input value I2 P2 2 Combination of input value I1 with parameter P1 P2 3 Combination of input value I1 with input value I2 and parameter P1 Master Set sets all bits of the output value Output OxFFFF Master Reset deletes all bits of the output value Output 0x0000 At output O2 the bitwise inverted value O1 is output Example O1 OxFF00 O2 OxOOFF 5 11 1 200 Bit NOT operation input value 1 I1 I1 bitwise inverted inverted output 11 b b Master Set Master Reset Description At output 1 O1 the bitwise inverted value of input I1 is output O1 I1 126 VPLC PLC 08 10 Bonfiglioli Vectron I3 MS I4 MR Example I1 OxFOOF gt O1 OxOFFO O2 OxFOOF Master Set sets all bits of the output value Output OxFFFF Master Reset deletes all bit
144. ning several FT instructions Note The FT instructions will be processed column by column according to the index in the table When designing application specific logic links in particular in the case of time critical applica tions Make sure to follow the correct order of the FT instructions Note the processing time 1 ms per FT instruction Example of parameterization of instructions in a function table Step 1 Task The drive may only start if both start signals Start 1 and Start 2 are present and no error is present As soon as one of the two start signals either Start 1 or Start 2 is no longer set the drive is to be stopped If one of three error messages error 1 error 2 or error 3 is present the drive is to be stopped The acknow input Ack is used for acknowledging the error messages Any error condition that may be present is to be signaled on digital output 1 Step 2 Logic plan start 1 aa amp Start Clockwise Fault 1 S Digital output 1 Fault 2 21 Faut3 ACK 08 10 VPLC PLC 139 Bonfiglioli Vectron Step 3 Combinations with and making entries in function table VTable e Combine FT instruction outputs to FT instruction inputs in function table VTable e Make FT instruction outputs generally globally available via signal sources 2401 FT Output buffer 1 to 2416 FT Output buffer 16 and
145. nput buffer 1360 3 iF T read index FT input buffer 1361 3 i FT input buffer 1362 75 S6IND 1 VTabe Function Table input buffer Index 1 Index2 Index3 i i FT input buffer 1362 75 S6IND 6 1 3 Write index and read index for the analog input buffer and FT fixed values Via the write and read indices the index of the Input buffer analog table the parameters of which are to be read or written is specified VTable uses the parameters automatically for writ ing and reading The write and read parameters are required for parameterization via the key pad of a control unit or via a bus system e g PROFIBUS Write index and read index for parameterization and reading of Input buffer ana log table via software VPlus The Input buffer analog table can be parameterized in the user interface VPlus or in the func tion table VTable In the user interface VPlus an index of the Input buffer analog table can be created via parameter FT Write Index FT Input analog 1377 The chosen index corresponds to a column in the Input buffer analog table The settings of parameters 1379 to 1397 are applied to the selected index of the Input buffer analog table Via parameter FT Read Index FT Input analog 1378 the values of a selected index can be read from the Input buffer analog table No Description Min Max Fact sett 1377 FT Write Index FT input analog L 9 g ee 1378 FT Read Index FT input analog o 9
146. nput buffer 4 Index 3 2 OR 6 TRUE 7 FALSE 7 FALSE 7 FALSE 2411 FT Output buffer 11 2402 FT Output buffer 2 Z2 2411 1 Index 2 100 Jump function 6 TRUE 2002 Input buffer 2 Index 4 100 Jump function 6 TRUE 2002 Input buffer 2 08 10 VPLC PLC 153 Bonfiglioli Vectron FT instruction 1343 FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT Parameter 1 1348 FT Parameter 2 1349 FT Target Output 1 1350 FT Target Output 2 1351 2401 FT Output buffer 1 2411 FT Output buffer 11 Index 6 80 Clock generator 2003 Input buffer 3 7 FALSE 7 FALSE 7 FALSE 100 100 2403 FT Output buffer 3 FT Commentary 1352 Z3 2401 1 Z3a clock Index 7 Index 8 FT instruction 1343 100 Jump function 100 Jump function FT input 1 1344 2005 Input buffer 5 6 TRUE FT input 2 1345 6 TRUE 2003 Input buffer 3 FT input 3 1346 6 TRUE 6 TRUE FT input 4 1347 6 TRUE 6 TRUE FT Parameter 1 1348 9 6 FT Parameter 2 1349 7 FT Target Output 1 1350 FT Target Output 2 1351 FT Commentary 1352 Z3 gt Z4 Z3 gt Z4 Index 9 Index 10 FT instruction 1343 2 OR 100 Jump function FT input 1 1344 6 TRUE 6 TRUE FT input 2 1345 7 FALSE 2002 Input buffer 2 FT input 3 1346 7 FALSE 6 TRUE FT input 4 1347 7 FALSE 6 TRUE FT Parameter 1 1348 11 FT Parameter 2 1349 FT Target Output 1 1350
147. nt denominator Description The absolute value is formed from the orthogonal square angle input values at I1 and I2 The absolute value is multiplied by the constant P O1 02 V11 12 x PL P2 As long as status TRUE is present at I4 Master Reset the output value O1 is 0 Example 11 14000 140 00 E T 5 00 13540 2200000 O1 4 140 0096 40 0096 x S0 0096 P1 500 5 00 5 00 2 4212 0096 x P2 10000 100 0096 V212 0096 x T0000 7 2896 Note Percentages 96 have two decimals For example Value 12345m 123 45 1 2345 5 3 7 342 Absolute value of three orthogonal components 3 D vector input value 1 O1 JT1 127 13 x B5 input value 2 inverted output 1 input value 3 Constant numerator Master Reset Constant denominator Description The absolute value is formed from the orthogonal square angle input values at I1 I2 and I3 The absolute value is multiplied by the constants x O1 02 JI I2 13 EE P2 As long as status TRUE is present at I4 Master Reset the output value O1 is 0 Example 08 10 VPLC PLC 97 Bonfiglioli Vectron gt 0 0 135400 400090 6 O1 4 140 0096 40 00 30 0096 x a o 13 3000 30 00 o P1 500 5 00 221 00 x 200 0 P2 10000 100 0096 100 00 7 43 Note Percentages have two
148. oO 4 3 4 4 XOR 1 3 operation input value 1 b O1 XOR3 11 I2 I3 I4 input value 2 negated output O2 O1 input value 3 input value 4 Description The inputs are XOR linked to one another The inputs of the instruction are the assigned signal sources The output is TRUE if TRUE is present on an odd number of inputs Via the output buffer the output signal is globally available O1 0 0 0 0 1 1 1 1 m ELOOrDn rmnOocGoco FOoOrOrFrOrFoO FOOrFOrFF oO 08 10 VPLC PLC 51 Bonfiglioli Vectron 4 4 Flip Flop types 4 4 1 10 RS Flip Flop Superior Set input b output O1 B Reset input b negated output O2 O1 ra Superior Set input Superior Reset input Description The inputs of the instruction are the assigned signal sources TRUE at the Set input sets the output to TRUE TRUE at the Reset input sets the output to FALSE If FALSE is present on both inputs the current status of the output signal is maintained TRUE at the Superior Set input sets the output to TRUE TRUE at the Superior Reset input sets the output to FALSE Priority Superior Reset highest priority Superior Set Reset Set lowest priority Via the output buffer the output signal is globally available Inputs Superior Set and Superior Reset are connected in series with the function Levels at Set input I1 and Reset input I2 are processed internally As soon as the S
149. ocessed internally If the Su perior Set Superior Reset Signal is no longer present the output will take the value which would result without the Set Reset Phase The processing sequence can be compared to a series connection of the function and a logic AND operation with the superior inputs Input 1 FlipFlop Delay Clock generator Input 2 s Superior Set Master The function sequence is interrupted The overriding inputs change the instruction output as from the time at which the overriding signal is present Set Reset signals are not evaluated as long as a Master Set Master Reset is present The processing sequence can be compared to a parallel connection of the function and the master inputs Inputi FlipFlop Delay Clock generator Input2 Master Set Master Reset Reset Timer Superior Master Superior Set Master Set TRUE at Superior Set Master Set switches instruction out put 1 to TRUE directly Superior Reset Master Reset TRUE at Superior Reset Master Reset switches instruction output 1 to FALSE directly Reset has a higher priority than set 4 2 P1 and P2 for chronological behavior and jump target The chronological behavior of the instructions or a jump target can be set up via P1 and P2 08 10 VPLC PLC 47 Bonfiglioli Vectron 4 2 1 Chronological behavior The setup of P1 and P2 affects the following instructions 42 140 52 150 62 160
150. or delaying edges for a certain time Two separate timers are available for the rising and the falling edge If the delay times are different this may result in an edge F1 at time T has a later switching time Ty than an edge F2 at the time T5 with switching time T22 In this case no edge is switched at the output as this would result in the input and output being inverted to on anoth er To gt Ti To lt Tu The delays are implemented both as retriggerable and as non retriggerable Retriggerable means that a new edge with the same direction during the processing will restart the delay the switching time for the edge will be recalculated last edge dominant The level of the input and output are not relevant to the calculation of the switching times Retriggerable should be selected if in the case of several consecutive signals with a short inter val between them only the last signal is to be executed or if in the case of continuous signals brief signal disturbances flickering are to be filtered out The level of the input and output are not relevant to the calculation of the switching times Non retriggerable means that a new edge with the same direction during the processing will not restart the delay the originally calculated switching time is maintained first edge do minant Non retriggerable should be used if an edge is to start a process and the process should not be stopped before the end of the
151. ordance with the documentation as well as the applicable directives and standards They must be handled carefully and protected against mechanical stress Do not bend any components or change the isolating distances Do not touch electronic components or contacts The devices are equipped with components which are sensitive to electrostatic energy and can be damaged if handled improperly Any use of damaged or destroyed components shall be considered as a non compliance with the appli cable standards Removal of seal marks may cause restrictions on warranty Do not remove any warning signs from the device 1 5 Electrical Installation Warning Before any assembly or connection work discharge the frequency inverter Verify that the frequency inverter is discharged Do not touch the terminals because the capacitors may still be charged Comply with the information given in the operating instructions and on the frequen cy inverter label Comply with the rules for working on electrical installations Rules for working on electrical installation Separate completely isolate the installation from all possible sources of electrical power Fix protect against reconnection Reconnection must be carried out by suitably qualified persons Verify there is no electrical power Verify that there is no voltage against earth on the plant component by measuring with measurement device or voltage tester Ground and connect in
152. ors during the write process will be ignored If input I4 Wait is TRUE zero operations NOP will be inserted if the write buffer is full until the write command can be entered in the buffer If input I4 Wait is FALSE write commands may be lost in the case of a buffer overflow If input I2 Delete buffer is TRUE the write buffer will be deleted first before the new write command is entered The target parameter of the write command is defined by P1 The target data set is defined by P2 5 7 1 1 401 Write frequency parameter input value 1 b I1 Hz b Delete buffer b inverted output 1 b Write release Parameter number Wait until writing is finished i Data set 0 9 or index Description The input value is converted from percent to Hz and written as long parameter I1 96 gt I1 Hz 123 45 123 45 Hz 112 VPLC PLC 08 10 Bonfiglioli Vectron 11 96 Hz xn I2 Delete buffer 01 FT instruction 1343 I3 Write enable Parameter Parameter 02 I4 Wait P1 5 7 1 2 402 Write current parameter input value 1 b I1 A lb Delete buffer b inverted output 1 b Write release Parameter number Wait until writing b is finished i Data set 0 9 or index Description The input value is converted from percent to A and written as int parameter I1 90 H A 123 4596 123 45 A
153. output values of instructions can also be used as input values in other instructions Values are interpreted as Percentage value internal Internal values of the frequency inverter are processed as percentage value Frequencies Cur rents and voltage are converted Also Input and Output buffer convert into percentage values Current Refers to the inverter nominal current The inverter nominal current refers to 100 00 96 10 VPLC PLC 08 10 Bonfiglioli Vectron Frequency Refers to Maximum Frequency 419 Maximum Frequency 419 refers to 100 00 96 Voltage Refers to 400 Ver bzw 400 V2 Vpeak The value refers to 100 00 96 Mathematical functions use percentage values as input and output values Internal conversions Internal values of the frequency inverter are processed as percentage value Frequencies Cur rents and voltage are converted Input Output conversion conversion f Hz f Hz I A 1 A PLC a A p Calculations Urea V Upeak V 0 5 0 5 Long inc Long inc Pos u Pos u 2 1 Chronological processing Instructions Write 24xx output buffer 25xx Update 20xx input buffer 23xx The instructions are processed cyclically In the first step the output buffer is written to the global variables then the input buffer is written to the sources Then the instructions are processed starting with Index 1 08 10 VPLC PLC 11 Bonfiglioli Vectron A c
154. p f trictiOn 7 2 cases ann dines Mtn chc e vore cent nee eee even i e voe 75 4 12 2 101 Jump function for loops eeeeeennneennnm menm 76 Buh BONAVIOR cs sicitscccicceahiadiacsascdazsabendeuctsucdssscansccaucdcaddaddsnssceetechaacstecteadiaddarssenaatenus 77 5 2 COMParators ecsseeeseeeeeeeeeeeeeeeaeeeaeeeaeeaeeeaeeeaeeeaeeeaeeeaeeeaeeeaeeeaeeeaecaeeeaeeeaeeaeeee 78 5 2 1 301 302 Comparator comparison of two variables esses 78 5 2 2 303 304 Comparator comparison of constant to variable 79 5 2 3 308 Comparator for motion blocks eeeeeeeeeennnen mmm 81 08 10 VPLC PLC 3 Bonfiglioli Vectron 5 2 4 309 Position comparator long eeeeeeeennnennnmem menn 82 5 2 5 310 Analog hysteresis eeeeeeeeeeeeeneeeene nennen nennen nennen nennen nnn nnn 83 5 2 6 311 312 Window comparator comparison of two variables 84 5 2 7 313 314 Window comparator comparison of constant to variable 85 5 2 8 320 Min M X355 oreet e eie e e eere re Ata eer Cra Eee ee ee 87 5 2 9 321 Min Max for position values Long eeeenenm m 87 5 2 10 322 Min Max in time window sseeeeeeeee nnnm nnne nnn 88 5 2 11 323 Min Max for positions Long in time window eeeeeeeeee 88 5 3 Mathematical funct
155. perior 55 x 1 0 1 On Superior BR O O1 021 0 O0 ae On delay ti 190 0 O eps Off delay t2 P1 P2 positive delay negative delay 08 10 VPLC PLC 61 Bonfiglioli Vectron 4 5 2 140 141 142 Delay retriggerable Master F edge b output O1 negated output O2 Ot Master Set input On delay t1 Master Reset input t Off delay t2 140 ms 141 s or 142 min Description The positive edge at input 1 is transferred to the output after delay ti P1 the negative edge after delay t2 P2 The delay time starts again with each edge TRUE at the Master Set input sets the output to TRUE TRUE at the Master Reset input sets the output to FALSE Via the output buffer the output signal is globally available Master Set and Master Reset are connected parallel with the function and change the state of the function as soon as the signal is present O1 F a m F MS MR Q State x X 1 0 Off Master MS x 1 0 1 On Master o 0i 021 0 O uer On delay ti 1250 0 0 eg Off delay t2 P1 P2 positive delay negative delay 62 VPLC PLC 08 10 Bonfiglioli Vectron 4 5 3 50 51 52 Delay non retriggerable Superior Off delay t2 50 ms 51 s or 52 min Description The positive edge at input 1 is transferred to the output after delay t1 P1 the negative edge after delay t2 P2 The delay time starts again with each edge TRUE at the Supe
156. ption This function compares the two parameters P1 and P2 to the current motion block of the table positioning If the current motion block is within the two defined parameters the output is set to TRUE The output of the comparator is TRUE if a motion block is active in the table positioning in the range P1 P2 The output value can be changed by means of the two Boolean inputs I3 and 14 Master Set sets output O1 to TRUE Master Reset sets output O1 to FALSE Master Reset has priority over Master Set Examples Pp1lp2 232a2586782m0m0 7295551075922222552525575757 P1 lt P2 5 7 Pi gt P2 20 10 O1 TRUE Special case P1 P2 O1 TRUE if a motion block from ranges 1 to P2 or P1 to 32 is active 08 10 VPLC PLC 81 Bonfiglioli Vectron 5 2 4 309 Position comparator long L Comparative val Output I1 gt 12 ue 1 Comparative val ue 2 Master Set Master Reset b b Description This function compares inputs I1 and I2 This function is intended for long variables positions ramps of table positioning O1 is TRUE if I1 gt I2 O1 is FALSE if I1 lt I2 If a hysteresis P1 and P2 is set up O1 is TRUE if T1 gt I2 P1 O1 is FALSE if I1 lt I2 P2 O1 remains unchanged if I1 is in the range of the hysteresis I2 P2 I1 I2 4 P1 The comparator has three working ranges Range 1 I2 Pl lt I1 O1 TRUE Range 2 I2 P2 H lt
157. put 7 FALSE buffer 4 instruction 1 buffer 6 FT input 2 1345 2003 FT input 2009 FT input 2005 FT input 7 FALSE buffer 3 buffer 9 buffer 5 FT input 3 1346 2002 FT input 7 FALSE 2201 Outp 1 7 FALSE buffer 2 instruction 1 FT input 4 1347 7 FALSE 7 FALSE 2202 Outp 1 7 FALSE instruction 2 FT Target Output 0 Output not 2402 FT 2401 FT 0 Output not 1 1350 usable globally Output buffer 2 Output buffer 1 usable globally FT Target Output 21351 0 Output not usable globally 0 Output not usable globally 0 Output not usable globally 0 Output not usable globally 1 Inverted output of function 1 in this example of OR function 2 Inverted output of function 2 in this example of RX Flip Flop The outputs of the FT instructions are available as sources and can be linked to the inputs of other functions or output via digital outputs Example Linking of AND function output with Start Clockwise Function parameter Start clockwise 068 2402 FT output buffer 2 Linking of RS Flip Flop output with digital output 1 Parameter Operation mode digital out put 1 530 80 FT Output buffer 1 08 10 VPLC PLC 141 Bonfiglioli Vectron 6 5 Example 3 Parameterization of logic diagram AND Index 2 Inverter Release amp XOR 1 b Index 3 OR Index 1 S1OUT 1 S2IND 4
158. put e g IN2D or a signal source e g 162 Error Signal is to be applied to the input of an instruction an input buffer must be set up on this digital input or signal source As a result the digital input or signal source is available for the inputs of the instructions ist example Combination of an instruction input with a digital input The signal at digital input I4ND is to be applied to input 3 of an instruction Input signal settings Boolean PLC signal e g 2003 Input buffer 3 Global source 74 IN4D 3 2 2 2 Analog Combination of a signal source with the input of an instruction The signal of an analog input e g MFI1A or and analog signal source e g 10 Stator fre quency is to be applied to the input of an instruction e In dialog window Input settings analog select a PLC signal 2301 2334 e Select a global source As a result the analog input or signal source is available for the inputs of the instructions PLC signal 2301 2304 Frequency 1 4 2311 2314 Current 1 4 2321 2324 Percent 1 4 2331 2334 Voltage 1 4 2351 2354 General source 1 4 Example Combination of an instruction input with a signal source The stator frequency is to be applied to the input of an instruction e In dialog window Input settings analog select a PLC signal 2301 Frequency 1 2304 Frequency 4 e Select global source 10
159. rd input value 2 HTSOFIRO PR High word Selection value 1 or 2 Fixed value P Low word Selection of I or P High word Description One of the values I1 I2 or P is output Via 14 it is defined if an input value or the fixed value is output Via I3 it is defined if value 1 or 2 is output 08 10 VPLC PLC 111 Bonfiglioli Vectron 13 14 I1 I2 O O2 Pos High word O1 Pos Low word The output value is determined according to the following table I3 I4 O 0 0 I1 1 0 I2 X 1 P2 P1 P2 P1 High word Low word Note Output value O2 is not the inverted value of O1 The output can be combined with inputs for position values Long The function can also be used for ramp settings in configurations x40 The availability of configuration x40 depends on the device series 5 7 Parameter access 5 7 1 Writing parameters Parameters can be written from the PLC functions This is done in two steps The PLC function puts the write request including all data on a list This list is processed in non realtime system In this process redundant write commands on the same parameter are deleted The list can contain a maximum of 8 write commands The output is TRUE if the list is full and cannot accept any more write commands If the parameter number is outside of the range 0 1599 only the status of the buffer is checked and the output is set if applicable Any err
160. rior Set input sets the output to TRUE TRUE at the Superior Reset input sets the output to FALSE Via the output buffer the output signal is globally available Inputs Superior Set and Superior Reset are connected in series with the function Levels at in put I1 are processed internally As soon as the Superior Set or Superior Reset is reset the out put is switched to the internally saved value Digital Signal Function amp Logic table Input source output F I1 o aa E sj sk g s E x x 1 O0 Off Superior _ 1 0 1 On Superior 0 Ol 021 0 O Juga On delay t1 0 0 eg Off delay t2 positive delay negative delay 08 10 VPLC PLC 63 Bonfiglioli Vectron 4 5 4 150 151 152 Delay non retriggerable Master Master Set input Master Reset input Off delay t2 150 ms 151 s or 152 min Description The positive edge at input 1 is transferred to the output after delay t1 P1 the negative edge after delay t2 P2 The delay time starts again with each edge TRUE at the Master Set input sets the output to TRUE TRUE at the Master Reset input sets the output to FALSE Via the output buffer the output signal is globally available Master Set and Master Reset are connected parallel with the function and change the state of the function as soon as the signal is present F I1 O1 a O1 F oms m 9 MS x x 1 0 Off Master x x 1 0 1 On Master MR P Ol 021 0 0 se
161. rror User error 1 In instruction 95 Triggering of an error shut down behavior P1 F3031 Nene was triggered via input I1 User error 2 In instruction 95 Triggering of an error shut down behavior P1 F3032 f dpa was triggered via input I2 User error 3 In instruction 95 Triggering of an error shut down behavior P1 F3033 e was triggered via input I3 User error 4 In instruction 95 Triggering of an error shut down behavior P1 F3034 Ere was triggered via input 14 08 10 VPLC PLC 147 Bonfiglioli Vectron 8 Obperation as state machine In the previous chapters the PLC functions were introduced as a sequence of various instruc tions In addition a state machine sequence also referred to as finite state machine can be integrated by the specified instruction types A state machine is often used for representing sequences schematically and for easier implementation of solutions In order to realize a state machine sequence the jump functions are of particular importance The jump functions are required for changing the state Inputs 1 and 2 of the jump function are used for checking the condition for the transition Inputs 3 and 4 set the input buffer and write the output buffer In the state machine inputs 3 and 4 are generally set to TRUE at the jump functions for this reason in order to update the changing signals for changing the state 8 1 Example of a controller Example A lifting ge
162. s of the output value Output 0x0000 Note Since output I2 output the bitwise inverted value of output O1 O2 I1 5 11 2 201 Bit AND NAND operation O1 AND I1 12 if P2 1 96 input value 1 96 O1 AND I1 P1 if P2 2 O1 AND I1 I2 P1 if P223 input value 2 inverted output NAND Ib _ Master Set Mask b Master Reset i Operation mode 1 2 or 3 Description The input value at I1 is AND combined Via P2 you can select P2 1 11 and I2 are AND combined P2 2 11 and P1 are AND combined P2 3 11 I2 and P1 are AND combined Master Set sets all bits of the output value Output OxFFFF Master Reset deletes all bits of the output value Output 0x0000 201 I3 MS I4 4 MR Examples P2 I1 I2 P1 O1 02 1 AND 11 12 OxFOOF OxOFOF 0x000F OxFFFO 2 AND 11 P1 OxFOOF OxOOFF 0x000F OxFFFO 3 AND I1 I2 P1 OxFOOF OxOFOF OxOOFF OxOOOF OxFFFO 08 10 VPLC PLC 127 Bonfiglioli Vectron In example 1 I1 1 1 1 10 0 00 00 0 0 1 1 1 I2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 m OxFOOF OxOFOF m 01 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0x000F O1 OR I1 I2 if P2 1 9o input value 1 O1 OR I1 P1 if P2 2 O1 OR I1 I2 P1 if P223 input value 2 inverted output NOR b Ma
163. signed to the digital outputs of the frequency in verter 80 PLC output buffer 1 81 PLC output buffer 2 82 PLC output buffer 3 83 PLC output buffer 4 100 to 183 Operation modes inverted LOW active Digital output is switched off Digital output signal of an instruction Signal source 2401 PLC output buffer 1 is the output signal This signal source contains the output value of the instruction assigned to signal source 2401 Digital output signal of an instruction Signal source 2402 PLC output buffer 2 is the output signal This signal source contains the output value of the instruction assigned to signal source 2402 Digital output signal of an instruction Signal source 2403 PLC output buffer 3 is the output signal This signal source contains the output value of the instruction assigned to signal source 2403 Digital output signal of an instruction Signal source 2404 PLC output buffer 4 is the output signal This signal source contains the output value of the instruction assigned to signal source 2404 7 4 Signals for analog outputs of device Via a multifunction output the values of analog instructions can be output The following output signals of the function table can be assigned to the analog outputs Abs value PLC outp percent 1 Abs value PLC outp percent 2 PLC outp per 161 cent 1 PLC outp per cent 2 162 Analog output signal of an instruction as an abso
164. ster Reset the output value O1 is 0 Note Percentages have two decimals For example Value 12345m 123 45 1 2345 5 3 14 364 Modulo Input numerator 1 I1 x I2 xP1 01 02 13 x P2 Input numerator 2 Input denomina tor 1 Master Reset Numerator 3 Denominator 2 Description The input value at I1 is multiplied by the input value at I2 and parameter value P1 and the re sult is divided by the input value at I3 and parameter value P2 01 02 I1xI2xP1 O1 Result in front of decimal point I3 x P2 O2 Result behind decimal point Example 1 I1 110 P1 100 0096 I2 100 P2 100 0096 I3 3296 0 0 0 110 00 x100 00 x100 00 11 _ 3 4375 343 75 32 00 x 100 00 0 32 01 343 00 O2 0 75 Example 2 I1 110 P1 1 00 I2 100 P2 100 00 I3 32 110 00 x 100 00 x 1 00 0 011 32 00 x 100 00 0 32 01 3 00 02 0 43 0 034375 3 43 Example 3 I1 220 P1 100 00 I2 100 P2 10 00 I3 12 08 10 VPLC PLC 101 Bonfiglioli Vectron 220 00 x 100 00 x 100 00 2 2 12 00 x 10 00 1 2 O1 183 02 0 33 1 8333 183 33 Example 4 I1 22000 P1 10 factory setting I2 FALSE P2 10 factory setting I3 1200 0 0 0 220 00 x 100 00 x 100 00 2 2 _ 1 8333 183 33 12 00 x 10 00 1 2 O1 183 O2 0 33 If position values are used as input quantities inst
165. ster Set Mask b Master Reset i Operation mode 1 2 or 3 Description The input value at I1 is OR combined Via P2 you can select P2 1 I1 I2 are OR combined P2 2 11 P1 are OR combined P2 3 I1 L2 P1 are OR combined Master Set sets all bits of the output value Output OxFFFF Master Reset deletes all bits of the output value Output 0x0000 202 I3 4 MS I4 4 MR Examples P2 I1 I2 P1 O1 02 1 OR 11 I2 OxFOOF OxOFOF OxFFOF 0x00F0 2 OR I1 P1 OxFOOF OxOOFF OxFOFF OxOFOO 3 OR I1 I2 P1 OxFOOF OxOFOF OxOOFF OxFFFF 0x0000 Re example 1 I1 1 1 11 00 000 0 00 1 1 1 1 OxFOOF I2 0 0 00 1 11 1 00 00 1 1 1 1 OxOFOF Ol 1 1 1 1 1 1 1 10 00 01 1 1 1 OxFFOF 128 VPLC PLC 08 10 Bonfiglioli Vectron 5 11 4 203 Bit XOR XNOR operation 9o input value 1 input value 2 Master Set Master Reset 96 9 6 O1 XOR 11 I2 if P271 O1 XOR 11 P1 if P2 2 O1 XOR XOR 11 12 P1 if P2 3 inverted output XNOR Mask Operation mode 1 2 or 3 Description The input value at I1 is Exclusive OR combined Via P2 you can select P2 1 I1 I2 are Exclusive OR combined P2 2 I1 P1 are Exclusive OR combined P2 3 I1 I2 P1 are Exclusive OR combined Master Set sets all
166. sult positive input I1 positive input I2 Master Reset Description Inputs T1 and I2 as well as Factor P1 are multiplied by one another The result at the output is divided in a High word O1 and a Low word O2 O2 O01 2I1xI2xP1 02 O1 High word Low word The result of the multiplication long is not limited As long as status TRUE is present at I4 Master Reset the output value is 0 If P1 is set to value 0 O I1 x I2 is calculated Note The output value at O2 is not the inverted value of O1 92 VPLC PLC 08 10 Bonfiglioli Vectron The output can be combined with inputs for position values Long The function can also be used for ramp settings in configurations x40 Example 11224000 240 00 O 240 00 310 00 630 00 I12 31000 310 00 2 4000 3 1000 6 3000 P1 63000 630 00 4687 20 726FOhex O1 26FOhex 9968 O2 0007 7 Note Percentages have two decimals For example Value 12345m 123 45 1 2345 5 3 2 3 334 Mult by fraction Ol 11xP P2 inverted output 1 Factor numerator Factor denominator Master Reset Description The input value at I1 is multiplied by the parameter value P1 and divided by parameter value P2 P1 O1 02 I1x po The result of the multiplication is limited to 327 6790 As long as status TRUE is present at I4 Master Reset the output
167. t The ramp gradient can be adjusted See chapter 5 5 3 383 Spike filter Input spikes are filtered out of the input value at I1 See chapter 5 5 4 32 VPLC PLC 08 10 9 Bonfiglioli Vectron Analog switch Analog functions Analog multip 390 exer One of the values I1 I2 P1 or P2 is output See chapter 5 6 2 391 Analog chan Depending on the active data set one of the input values I1 I4 is geover switch output See chapter 5 6 1 Analog multip lexer for posi 392 tion values One of the values I1 I2 or P P1 P2 is output See chapter 5 6 3 data set num ber Analog chan 393 geover switch Depending on the active data set one of the input values I1 I4 is for position output See chapter 5 6 4 values Parameter access reading and writing parameters Analog functions OTS The input value is converted from percent to Hz and written as long 401 quency para parameter See chapter 5 7 1 1 meters Write current The input value is converted from percent to A and written as int 402 parameter parameter See chapter 5 7 1 2 403 Write voltage The effective value at the input is converted from percent to V and parameter eff written as int parameter See chapter 5 7 1 3 WOES NON ade The peak value at the input is converted from percent to V and writ 404 parameter ten as int parameter See chapter 5 7 1 4
168. t 1 Note Instructions can only be edited in stop mode If you try to make any changes while the func tion table is not in stop mode an error will be displayed in VPlus and VPLC The attempted change will not be applied 3 2 1 The inputs can either be combined with the input buffer fixed values the outputs of other in structions normal or inverted or the global output variables digital output buffer or analog Inputs outp frequency outp current etc Note Note that the output buffer is updated only with a write operation e g during return jump The value used originates from the last write operation of the output buffer 6 TRUE 7 FALSE Combination with digital signal source of input buffer 2001 2016 Input buffer 1 16 Combination with analog signal source or actual value 2301 2304 Frequency 1 4 2311 2314 Current1 4 2321 2324 Percent 1 4 2331 2334 Voltage 1 4 38 VPLC PLC 08 10 Bonfiglioli Vectron 2341 Actual position of table positioning 2351 2354 General source 1 4 Combination with constants 2380 2392 Auxiliary values constants and global flags status signals Combination with digital global signal source of output buffer 2401 2416 Output buffer 1 16 Combination with analog output of an instruction 2501 2504 Outp frequency 1 4 2511 2514 Outp current 1
169. t buffer the output values of the instructions can be made generally globally available and used by other functions e g start clockwise data set change over or output via the digital outputs of the device Up to 16 signal sources can be used as digital output buffer 24 signal sources can be used as analog output buffer All output values of the instructions have defined values when the frequency inverter is in itialized They are FALSE digital instructions or have value 0 analog instructions for all in struction outputs and all output buffer values Inverted instruction outputs will be TRUE after initialization Processing of the instructions can be activated via button Start PLC and deactivated via button Stop PLC Consistent data The input buffer and output buffer guarantee consistent data during the run time Each instruction is described by Instruction digital AND OR etc analog addition absolute value function etc Inputs Inputs of the instructions digital analog or position Function block settings These parameters enable depending on the selected instruction setting of delay times factors or jumps between functions for example Outputs of instructions The value of an output can be moved to the output buffer and is now generally globally available to other device functions Each instruction has two outputs O1 and O2 O2 O1 inverted or O1 Low word and O2 High word The
170. t is FALSE the output will be FALSE Via the output buffer the output signal is globally available Note Unused inputs must be set to 6 TRUE For example I3 and I4 must be set to 6 TRUE if inputs I1 and I2 are to be combined by the AND operation I1 0 0 0 O1 0 1 0 I2 1 0 0 amp 1 1 1 13 o o1 I4 input value 1 b O1 OR I1 I2 13 14 input value 2 negated output O2 O1 input value 3 input value 4 Description The inputs are OR combined with one another The inputs of the instruction are the assigned signal sources Output is logic TRUE if at least one input is TRUE If all inputs are FALSE the output will be FALSE Via the output buffer the output signal is globally available Note Unused inputs must be set to 7 FALSE factory setting For example I3 and I4 must be set to 7 FALSE if inputs I1 and I2 are to be combined by the OR operation 0 0 0 Ol 9 1 1 12 1 0 1 21 1 1 1 I _ 3 o O1 14 50 VPLC PLC 08 10 Bonfiglioli Vectron 4 3 3 3 XOR 1 operation input value 1 b O1 XOR1 11 I2 13 14 input value 2 negated output O2 O1 input value 3 input value 4 Description The inputs are XOR linked to one another The inputs of the instruction are the assigned signal sources Output is logic TRUE if exactly one input is TRUE Via the output buffer the output signal is globally available O1 0 0 1 1 rFOrO Orr
171. t to FALSE Via the output buffer the output signal is globally available Inputs Superior Set and Superior Reset are connected in series with the function Levels on C input I1 and D input I2 are processed internally As soon as the Superior Set or Superior Reset is reset the output is switched to the internally saved value O1 PE oo c D ss s o St D X x x 1 0 Off Superior SS X x 1 0 1 On Superior x x 0 0 Q Hold s p e 0291 0 0 0 0 Sample 021 1 0 0 1 Sample 56 VPLC PLC 08 10 Bonfiglioli Vectron 4 4 6 130 D Flip Flop Master C Clock ES D Data input ra Master Set input Master Reset input output O1 negated output O2 Ot Description If a positive edge is received at input 1 clock pulse input C Clock the signal is transferred from signal input 2 data input D to the output TRUE at the Master Set input sets the output to TRUE TRUE at the Master Reset input sets the output to FALSE Via the output buffer the output signal is globally available Master Set and Master Reset are connected parallel with the function and change the state of the function as soon as the signal is present MR MS C D x x x X x 1 x x 0 0 gt 1 0 0 021 1 0 oooornr MS MR State Off Master On Master Hold Sample Sample 08 10 VPLC PLC 57 Bonfiglioli Vectron 4 5 Delays The delays can be used f
172. te of the function as soon as the signal is present O1 S R Ms m tate X x X 1 0 Off Master X X 1 0 1 On Master 0 0 0 O Q Hold 0 1 0 0 0 Reset 1 0 0 0 1 Set 1 1 0 0 0 Off MR MS j R o 9 D S o o 4 f 4 D Q 15r Set TRUE at the S input sets the output to TRUE Save If all inputs are FALSE the output remains unchanged Reset If R input is TRUE the output is set to logic FALSE Off If both inputs are set to TRUE the output is FALSE Master Set MS set output to TRUE Master Reset MR set output to FALSE CLR 08 10 VPLC PLC 53 Bonfiglioli Vectron 4 4 3 20 Toggle Flip Flop Superior b Toggle 1 b output O1 b Toggle 2 negated output O2 O1 ra Superior Set input Superior Reset input Description Output signal changes with the positive pulse edge at input T1 or with the negative pulse edge at input T2 TRUE at the Superior Set input sets the output to TRUE TRUE at the Superior Reset input sets the output to FALSE Via the output buffer the output signal is globally available Inputs Superior Set and Superior Reset are connected in series with the function Levels on T1 input I1 and T2 input I2 are processed internally As soon as the Superior Set or Superior Reset is reset the output is switched to the internally saved value O1 01 Ti 2 samo X X X 1 0 Off Superior X X 1 0 1 On Superior 0 0 0 Oj Q
173. ted output negated output VPLC Input field in function block setup Function table Parameter FT Parameter 1 1348 VPLC Input field in function block setup Function table Parameter FT Parameter 2 1349 For better clarity output On non negated is used in the descriptions The negated output O is available in each function and can be used For digital functions note Unused inputs must be set to 7 Off Exception Unused inputs of the instruction AND must be set to 6 On In all functions output 2 has the inverted logic state of input 1 Clock inputs T C evaluate signal edges Set Superior Set Master Set inputs and Reset Superior Reset Master Reset inputs evaluate logic states Reset has priority over Set Times set for P1 and P2 are limited internally to a max value of 24 days Via the library the logic function can be selected 46 VPLC PLC 08 10 Bonfiglioli Vectron 4 1 Superior Master Most instructions also enable setting of selective output statuses by overriding inputs This may be used for example for initialization of a plant status There are two variants of instructions with overriding inputs Superior The function sequence is processed further internally in the instruction The overriding in puts change the instruction output only for the time in which the overriding signal is present During the set reset phase edges will also be detected and pr
174. ter 1 1348 FT Parameter 2 1349 100 Jump function 6 TRUE 2002 Input buffer 2 6 TRUE 6 TRUE Index number ext state Index numberown state Items Next state and Own state are used as placeholders until the correct numbers of the indices can be entered The transition from state 4 to state 5 can be performed in the same way Transition from state 3 t o state 4 The transition from state 3 to state 4 requires a different method as two jump events have to be checked FT instruction 1343 FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT Parameter 1 1348 FT Parameter 2 1349 FT instruction 1343 FT input 1 1344 FT input 2 1345 FT input 3 1346 FT input 4 1347 FT Parameter 1 1348 FT Parameter 2 1349 100 Jump function 2005 Input buffer 5 6 TRUE 6 TRUE 6 TRUE next state No jump next step 100 Jump function 6 TRUE 2003 Input buffer 3 6 TRUE 6 TRUE Jump target clock generator Jump evaluation own state Items Next state and Jump target clock generator Jump evaluation own state are used as placeholders until the correct numbers of the indices can be entered Item No jump next step is a placeholder for any value The jump function is active only if 2005 Input buffer 2005 TRUE is fulfilled DI5 0 Otherwise the next step will be executed The transition from state 5 to state 2 can be performed again in the same way
175. the Brief Instructions and the Operating Instructions the Installation Instruc tions provide information on how to install and use the additional optional components If you need a copy of the documentation or additional information contact your local repre sentative of BONFIGLIOLI The following pictograms and signal words are used in the documentation Danger Danger refers to an immediate threat Non compliance with the precaution described may result in death serious injury or material damage Warning Warning refers to a possible threat Non compliance with the warning may result in death serious injury or material damage Caution Caution refers to an immediate hazard Non compliance may result in personal or material damage gt gt gt Attention Attention and the related text refer to a possible behavior or an undesired con dition which can occur during operation Note marks information which facilitates handling for you and supplements the cor responding part of the documentation 08 10 VPLC PLC 1 Bonfiglioli Vectron TABLE OF CONTENTS 1 1 General Information 1 eeoseeee eee nee lina ddi rna n ann saanane ndan nn annm annuas 7 1 2 Purpose of the Frequency Inverters eere rere nnn 7 1 3 Transport and Storage esses seeeeee nnne rase rere 7 1 4 Handling and Installation eeeeeeeee enini n 8 1 5 Electrical
176. the inputs the loop can be stopped or restarted See chapter 4 12 2 110 182 Like instruction types 10 82 Evaluation of Master Set Master Reset instead of Superior Set Superior Reset Analog functions Debouncer Analog functions The input value will be forwarded to the output only if it has had a 97 Debouncer constant value for the configured delay P1 pos edge P2 neg edge See chapter 4 10 1 Bit functions for analog input values Analog functions Bit NOT opera At output 1 O1 the bitwise inverted value of input I1 is output See 200 tion chapter 5 11 1 The input value at I1 is AND combined Via P2 you can select P2 1 Combination with input value 12 201 ee P2 2 Combination with a mask permanently set up in P1 P2 3 Combination with I2 and P1 See chapter 5 11 3 The input value at T1 is OR combined Via P2 you can select P2 1 Combination with input value 12 202 Mud da P222 Combination with a mask permanently set up in P1 P223 Combination with I2 and P1 See chapter 5 11 2 The input value at T1 is Exclusive OR combined Via P2 you can se lect 203 Bit XOR XNOR P221 Combination with input value I2 operation P222 Combination with a mask permanently set up in P1 P223 Combination with I2 and combination of result with P1 See chapter 5 11 4 Ur The input value at I1 is shifted to the right bitwise by the number of ALOA IEEE
177. time set in P1 and the Delay Superior negative edge is delayed by the time set in P2 before switching them 50 ms non through to the output During the delay time edges will be ignored retriggerable Times are indicated in milliseconds ms TRUE at Superior Set input input 3 sets output TRUE TRUE at Superior Reset input input 4 sets output FALSE See chapter 4 5 3 51 s SPELLS As in operation mode 50 the unit of the times set in P1 and P2 is retriggerable seconds s See chapter 4 5 3 28 VPLC PLC 08 10 Bonfiglioli Vectron 52 Delay Superior min non retriggerable As in operation mode 50 the unit of the times set in P1 and P2 is minutes min See chapter 4 5 3 Timer functions Digital functions Monoflop Supe Output signal becomes TRUE with positive clock edge at input 1 or with negative clock edge at input 2 The time set in P1 is the On Time High and the time set in P2 is the ignore edge time Low 60 rior ms retrig The time is indicated in milliseconds ms The set on time and the gerable ignore edge time start again with each edge TRUE at Superior Set input input 3 sets output TRUE TRUE at Superior Reset input input 4 sets output FALSE See chapter 4 6 1 Monoflop decl As in operation mode 60 the unit of the times set in P1 and P2 is 61 rior s retrigger d h 1 able seconds s See chapter 4 6 1 Monoflop Sure As in operation mo
178. tion of signal source or digital input of parameter FT Input Buffer 1362 is applied to the set index of Function table input buffer Via parameter FT Read In dex FT Input Buffer 1361 the values of a selected index can be read from the Function table input buffer Description Max Fact sett a FT Write Index FT input buffer E 33 1361 Fr ReadIndex FT mputbufe 0 33 Settings for fixed parameterization Settings for non fixed parameterization non volatile volatile 0 all input buffers in EEPROM 17 all input buffers in RAM 1 16 individual input buffer in EEPROM 18 33 individual input buffer in RAM Note The settings 0 or 17 for FT Write Index FT input buffer 1360 change all values of an input buffer in the EEPROM or RAM In the case of non volatile storage 0 16 the changed values are still available when power supply is switched on again In the case of volatile storage 17 33 the data is only stored in RAM If the unit is switched off this data is lost and the data required are loaded from EEPROM Caution Writing of the EEPROM is restricted to approx 1 million times If this number is exceeded the device may be damaged 08 10 VPLC PLC 135 Bonfiglioli Vectron Definition Input buffer RAM input buffer EEPROM 17 Write index and read index for the digital input buffer example i VPlus i Parameter Data set 0 iF T write index FT i
179. tions oneeee seien eere eren nennen nhanh nnn 121 5 10 1 501 Start motion block as single motion eeeennm n 122 5 10 2 502 Start motion block in automatic mode eem 123 5 10 3 503 Stop motion block a iisas esiisa a auand aviu a iadaa eiT 123 5 10 4 504 Continue motion block ccccseeeeessseeeeeesseeeeeessaeeeessaaeeessaaeeeessaaeeeesangs 124 5 10 5 505 Resume motion block eeeeeeeeeeeenennenmmen mener nnns 124 5 10 6 506 Start homilhg 5 2 rine ree er roce Pere Ere EE ena Ero Erin REOR pana o nah iere M iE 125 5 10 7 507 Check state 5 2 cnet teet em einer intact tee tla 125 5 11 Bit functions for analog input values 11 eere 126 5 11 1 200 Bit NOT operation eeeeeeeeeennenee nennen nnne nennen nnn nnn 126 5 11 2 201 Bit AND NAND operation eeseeeeeee nennen nnne nnn nnn nnns 127 5 11 3 202 Bit OR NOR operation eeeeeeeee nnne nnne nnne nennen nnn 128 5 11 4 203 Bit XOR XNOR operation eeeeeeeeenneneen nennen nnn nnns 129 5 11 5 210 Bit shift right iio ice teretes cei rete ree aes 129 5 11 6 211 Bit arithmetical shift right 130 511 7 212 Bit shift left iioi ete es lected dive delve exe exon ERR Ce MENS 130 SALS 213 Bit roll rights eiie ene ere here cr EHE aora Gas eter hn rac Enric eae TR 131 5 11 9
180. to P2 P1 max to 327 67 As long as status TRUE is present at I4 Master Reset the output value O1 is 0 Example 11 14000 140 00 O1 140 0096 40 00 20 00 I2 4000 40 00 1 4000 0 4000 0 2000 I3 2000 20 00 280 00 Note Percentages have two decimals For example Value 12345m 123 45 1 2345 5 3 5 340 Average function 114 12 13_ Pl Input 1 01 TU P2 Input 2 inverted output 1 Input 3 Factor numerator Master Reset i Factor denominator Description The average is calculated from the input values at I1 I2 and I3 Parameters P1 and P2 can be adjusted as correction factors Olz 02 12 D Pl 3 P2 As long as status TRUE is present at I4 Master Reset the output value O1 is 0 Example 11 14000 140 00 O1 140 0095 40 00 20 00 3 5 4 1I2 4000 40 00 200 3 5 4 I3 2000 20 00 83 33 P1 5 P2 4 If the average is to be calculated from two input values only I1 and I2 must be used and I3 must be set to FALSE H I2 P1 x 2 P2 O1 96 VPLC PLC 08 10 Bonfiglioli Vectron Note Percentages 96 have two decimals For example Value 12345m 123 45 1 2345 5 3 6 341 Absolute value of two orthogonal components 2 D vector i 2 Pl input value 1 O1 vI1 12 52 input value 2 inverted output 1 Constant numerator Master Reset Consta
181. tput 1 Parameter number i Data set 0 9 or index Input value Write enable Wait until writing is finished Description The input value is put together from of low word and high word not changed and output as long parameter In this way this function can be used for any long parameter types O1 I2 I1 High word Low word I1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 I2 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 2 O1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 For the bits example values are entered here uU Low word I2 High word Ol FT instruction 1343 13 Delete buffer Parameter Parameter 02 Wait 14 P1 5 7 1 8 408 Write word parameter int input value 1 b I1 int Ib Delete buffer b inverted output 1 lb iWrite release Parameter number b Wait until writing is finished i Data set 0 9 or index Description The input value is not changed and written as int parameter In this way this function can also be used for any other int parameter types 08 10 VPLC PLC 115 Bonfiglioli Vectron I1 int 408 I2 Delete buffer Ol FT instruction 1343 I3 Write enable Parameter Parameter 02 5 7 2 Reading parameters Read access enables direct reading of a
182. tputs of analog functions eeeesseeeeeneen mnn 36 3 2 Combination of inputs and outputs of instructions 38 3 2 1 Ig Uc ose aie ct ponds pate FD REM 38 3 2 2 Combining input buffer with inputs sseeeeeeeeee nennen nmn nnn 41 3 2 2 1 Digital E 41 CP MEND I EEE ET EET 41 3 2 3 Combining instructions with one another sse 42 VPLC PLC 08 10 Bonfiglioli Vectron 3 2 4 Activating device functions via the output buffer eeeeseseeeeeeeeees 42 3 2 5 Controlling a digital output via the output buffer eessseseeeseeeeees 44 3 2 6 Controlling an analog output via the output buffer sseeeenenenen 45 4 1 Superior Master ener ires eee eren nennen nnnm n hannah nnu nhan adn naue auae a annua 47 4 2 P1andP2 for chronological behavior and jump target 47 4 2 1 Chronological bebliaViIOr 2 0 iiie ii eere etn eta tonto eo bes Que aa E TERRE Fe ER dai aa ada 48 4 2 2 Jump target oie ee eet Eee reifen Pie peer iE ies 48 4 2 3 Overview table cerner net Poe Pol rn ep x enr erede vae red 48 4 3 Boolean operations 1 eerieeee eene rennen nennen nnne nn ann nnne RARA TAa ARAE Rai 49 4 3 1 L AND Operati n iioii e a sa aea ex ve Y wk RE RE CERES EERREP eid 50 4 3 2 2 OR operation cer rne t eter Soc Cen ned e dn
183. trol deviation over time is added The integral time is indicated in milliseconds ms See chapter 5 4 2 372 PI Controller s The control deviation I1 I2 is multiplied by the amplification P1 an the I component total of control deviation over time is added The integral time is indicated in seconds s See chapter 5 4 3 373 PD T1 The control deviation I1 I2 is multiplied by the amplification P1 Controller ms The D component is added See chapter 5 4 4 The control deviation I1 I2 is multiplied by the amplification 1 374 PID T1 con The I component and the D component are added To adjust another troller ms amplification a P controller must be connected in series The integral time is indicated in milliseconds ms See chapter 5 4 5 The control deviation I1 I2 is multiplied by the amplification 1 375 PID T1 con The I component and the D component are added To adjust another troller s amplification a P controller must be connected in series The integral time is indicated in seconds s See chapter5 4 6 Filters Analog functions 380 PT1 element The input value at I1 is filtered according to the set filter time con stant See chapter 5 5 1 381 Time average The average is calculated from the input values at I1 over a certain period of time See chapter 5 5 2 382 Ramp limitation The output value follows the input value at a limited ramp gradien
184. tuses Thus the sequence is I 1 Stop I2 Stop FT Runmode 1399 21 Single Part 22 Single Part The sequence is processed until a jump instruction is reached which writes the output buffer In this example the buffer is written by both jump instructions Thus the sequence is Block A Stop Block B Stop FT Runmode 1399 31 Single Cycle 32 Single Cycle The sequence is processed until the end is reached and the return jump to the start is effected to block C It may happen that Block B is processed repeatedly depending on the digital sig nals if the jump at J2 jumps to the beginning of Block B A cycle may be for example Block A Block B Block B Block B Block C return jump stop 6 3 Example 1 Combining two digital outputs Digital signals S2IND and S4IND are to control digital output S1OUT If both signals are present the output is TRUE If not the output is FALSE 138 VPLC PLC Bonfiglioli Vectron Settings in index 1 of function table FT Instruction 1343 1 AND FT input 1 1344 2002 FT input buffer 2 FT input 2 1345 2004 FT input buffer 4 FT input 3 1346 6 TRUE FT input 4 1347 6 TRUE FT target output 1 1350 2401 FT output buffer 1 2401 01 6 TRUE 1346 61 6 TRUE 1347 Settings in parameter group digital outputs Op Mode Digital Output 1 530 80 FT Output Buffer 1 6 4 Example 2 Combi
185. un Stop By default factory setting the function table is stopped and must be started by parameter FT RunMode 1399 In stop mode no instructions are processed and there is no writing of the output buffer Note Instructions can only be edited in stop mode If you try to make any changes while the func tion table is not in stop mode an error will be displayed in VPlus The attempted change will not be applied Further operation modes are available for processing individual instructions and instruction blocks If an operation mode 11 12 21 22 31 or 32 is selected the instruction block will be processed according to the function described Then Run mode will be set to 0 Stop auto matically In order to process another instruction block the operation mode must be set to the corresponding value again 0 Stop The function table is stopped and no longer processed The function table is started at index 1 and processed normally The function table is continued at the index where the processing was 2 Continue A stopped last time and the table is then processed normally i l Single Step One instruction is processed 2 l Single Part All instructions are processed until next writing of output buffer 31 All instructions are processed until return jump The return jump is 32 Single Cycle reached when the maximum number of logic functions is processed or the next FT Instruction 1343 0 Note Two modes are available to an
186. uperior Set or Superior Reset is reset the output is switched to the internally saved value s R 55 Rg X x X 1 0 Off Superior X X 1 0 1 On Superior O1 0 0 0 0 Q Hold 0 1 0 0 0 Reset 1 0 0 0 1 Set 1 1 0 0 0 Off SR SS R D D p S 0 0 1 0 1 Q m 1 Set TRUE at the S input sets the output to TRUE Save If all inputs are FALSE the output remains unchanged Reset If R input is TRUE the output is set to logic FALSE Off If both inputs are set to TRUE the output is FALSE Superior Set SS set output to TRUE Superior Reset SR set output to FALSE CLR 52 VPLC PLC 08 10 Bonfiglioli Vectron 4 4 2 110 RS Flip Flop Master Set input ERI Reset input ra Master Set input Master Reset input output O1 negated output O2 Ot Description The inputs of the instruction are the assigned signal sources TRUE at the Set input sets the output to TRUE TRUE at the Reset input sets the output to FALSE If FALSE is present on both inputs the current status of the output signal is maintained TRUE at the Master Set input sets the output to TRUE TRUE at the Master Reset input sets the output to FALSE Priority Master Reset highest priority Master Set Reset Set lowest priority Via the output buffer the output signal is globally available Master Set and Master Reset are connected parallel with the function and change the sta
187. ut buffer With the output signal of the function block this enables controlling device functions of the frequency inverter Output buffers 1 to 16 correspond to signal sources PLC output buffer 2401 to 2416 Select the corresponding signal source for a device function 08 10 VPLC PLC 19 Bonfiglioli Vectron Block Dialog window Percent Voltage Marker V indicates index Buffer Number i shendy in use Write the output signal of an analog function block to the output buffer Output buffers 1 to 4 correspond to signal sources 25xx The signal sources can be used for analog inputs of other function blocks or combined with device func tions Percent Buffer Number 1 and 2 can be output via analog control terminals of the frequency inverter Select Signal Source 61 Amount PLC output 1 Percent Buffer Number 1 or 62 Amount PLC output 2 Percent Buffer Number 2 for the parameter of the analog output Signal sources 161 and 162 have a sign Dialog window P2 0 550 T m indicates index in use x i Y selection causes renumbering on time 1 int float Min 0 Default 1 Max 65535 ignore edge time 0 Q int float Min 0 Default 0 Max 65535 Comment The index I determines the order in which the instructions are processed Adjust the function block to the application via input fields P1 and P2 The functions of P1 and P2 depend on the
188. utput is switched to the internally saved value SS PROX xk x IW O O x x x OoOooonnx d 31 _ 3 91 gt lt gt lt State Off Superior On Superior off off Clock On Clock Off lt gt tl t2 tl t2 ti t2 ti V P1 P2 on time off time 08 10 VPLC PLC 69 Bonfiglioli Vectron 4 6 6 180 181 182 Clock generator Master S clock generator 1 b output O1 p S Clock generator 2 LN Master Set input On time High Master Reset input t Off time Low 180 ms 181 s or 182 min Description As long as input 1 is TRUE and input 2 is FALSE the set pulse pattern is output The pulse pat tern at the output always starts with TRUE The clock pattern is defined by the on time and the off time The time set in P1 is the on time High and the time set in P2 is the off time Low Via the output buffer the output signal is globally available Master Set and Master Reset are connected parallel with the function and change the state of the function as soon as the signal is present State Off Master On Master Off Off Clock On Clock Off PROX xX xXI W O O x x x on time off time 70 VPLC PLC 08 10 Bonfiglioli Vectron 4 7 Digital multiplexer 4 7 1 90 Digital Multiplexer Data Set Number Input data set 1 b output O1 E Input data set 2 negated output O2 O1 rag Input data set 3 Input data set
189. utton to translate the function block program to parameter settings and download them to the frequency inverter Only if this function executed will the data in the frequency inverter be changed The syntax must be free from errors Before the translation and download stop the PLC by clicking button g 2 2 12 Starting the PLC Run the function block opened in the editor by clicking on button Q 2 2 13 Stopping the PLC Stop the started function block by clicking on button g 14 VPLC PLC 08 10 Bonfiglioli Vectron 2 3 2 3 1 User environment Tool bar and menu commands Se e 9 754 E N o Un Un Solel S 5 o d 9 g s alg 6 3 o g a 9 D P b gt zj Create a new VPLC file Open VPLC file Open an existing VPLC file Save the program created by means of function block as a VPLC file Select function blocks or wire in editor Place function block selected in the library in the editor Connect function block to one another or to inputs outputs Insert a text field for comments in the editor Undo the last action Up to 16 actions can be undone Redo a function undone before Place function Add comment Increase or reduce the view in the editor Check the function block pro gram for errors Click on the error message to mark the cause of the error in the editor Translate the function block pro gram to parameter values and download them to the fr
190. with the local and country specific regulations and standards 08 10 VPLC PLC 9 Bonfiglioli Vectron 2 Description of System VPLC With the PLC functions VPLC external digital signals and internal logic signals of the frequen cy inverter can be combined with one another Via analog and mathematical functions analog signals can be influenced or compared the results are available for output PLC functions are also referred to as instructions The results of the instructions can be used by other device functions e g comparator or out put via digital outputs The results can also be used as input values by other instructions The instructions can be configured via function blocks in VPLC The functions are processed from index to index I VPLC Up to 32 functions are possible Each function block describes an instruction The processing order corresponds to the order of indices 1 to max 32 Input settings digital Via a digital input buffer digital signal sources e g run signal error signal and digital inputs e g IN2D can be assigned to the instruction inputs The input buffer enables 16 en tries Input settings analog Via an analog input buffer analog signal sources e g frequencies can be assigned to the instruction inputs Via the input buffers 4 inputs each can be selected for frequencies per centages currents and voltages Analog output settings Via an outpu
191. x The value is converted to a percent value See chapter5 7 2 5 Read position The function reads the value of the parameter set up in P1 Parame 426 parameter ter number and P2 Data set index The value is converted to a position value See chapter5 7 2 6 Read lou The function reads the value of the parameter set up in P1 Parame 427 gP ter number and P2 Data set index The value is converted to a rameter So position value See chapter5 7 2 7 Read word The function reads the value of the parameter set up in P1 Parame 428 parameter ter number and P2 Data set index The value is converted to a percent value See chapter 5 7 2 8 08 10 VPLC PLC 33 Bonfiglioli Vectron Limiter Analog functions 440 Limitation Limitation to fixed values The input value at I1 is limited to P1 up const per limit and P2 lower limit and output See chapter 5 8 1 441 Limitation va Limitation to variable limits The input value at I1 is limited to I1 riable upper limit and I2 lower limit and output See chapter 5 8 2 Counters Analog functions 450 Up Down coun With each positive edge at I1 the output value of the counter is in creased by 100 00 P1 ter With each positive edge at I2 the output value of the counter is re duced by 100 00 P1 See chapter 5 9 1 The stopwatch is running if I1 TRUE and I2 FALSE I3 de 451 Counter with termines the direction I4 resets the
192. ycle is complete if all used and successive instructions have been processed Then the processing cycle is started again write output buffer update input buffer index 1 index 2 The processing time of each instruction is approx 1 ms Additionally 1 ms is required for writing the output signals 24xx 25xx and reading of input sig nals 20xx 23xx As a result the cycle time is the total of instructions 1 in milliseconds 2 2 Creating a program with function blocks 2 2 1 Starting VPLC In PC software VPlus click on button to start the editor for VPLC function blocks In menu Edit VPLC settings select the language for the user environment and the menu com mands 2 2 2 Saving a file Hi Click button to save the function block program as a VPLC file 2 2 3 Function block instruction Drag the required function blocks from the library into the editor window Double click the function block in order to set up an index for the function block The function blocks are processed in the order of the indices Wrong numbering will be reported by the syntax check ud Depending on the function block different settings are possible in fields P1 and P2 2 2 4 Wire Using the wire tool T to combine the blocks with one another in the editor Use wire to connect the blocks for inputs and outputs to function blocks Use wire to combine the function blocks with one another It is not possible to connect the con

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