Alex Milenkovich 1 CPE/EE 421 Microcomputers
Contents
1. Operating Modes C Examples C Examples C programming msp430x14x h _BIS_SR LPMO_bits GIE Enter LPMO w interrupt program stops here QQ Your program is in LPMO mode and it is woke up by an interrupt What should be done if you do not want to go back to LPMO after servicing the interrupt request but rather you would let the main program re enter LMPO based on current conditions the MSP430 CPE EE 421 521 Microcomputers CPE EE 421 521 Microcomputers Digital 1 0 all MSP430 Digital I O Introduction gt MSP430 family up to 6 digital I O ports implemented P1 P6 gt MSP430F 14x all 6 ports implemented Ports P1 and P2 have interrupt capability Each interrupt for the P1 and P2 I O lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input Signal a Ye ee Function Select Register PxSEL Direction Register PxDIR yes yes mamm SE Output Register PxOUT yes yes TREE m an e a r T WD J Input Register PxIN 7 The digital I O features include ji gt Independently programmable individual I Os LR gt Any combination of input or output 2 gt Individually configurable P1 and P2 interrupts Chapter 9 User s Manual gt Independent input and output data registers pages 9 1 to 9 7 The digital I O is configured with user software CPE EE 421 521 Microcomp2. Timer_A Counting Modes Timer_A5 MSP430x1xx Block Diagram Tew tok al a 7 j Page 11 3 User Manual 1 CPE EE 421 521 Microcomputers Timer_A 16 bit Counter Stop Halt Mode Timer is halted with the next CLK UP DOWN Mode OFFFFh CCRO Timer counts between 0 and CCRO and 0 UPIDOWN Mode UP Mode Timer counts between 0 and CCRO OFFFFh OFFFFh Continuous Mode Timer continuously counts up Continuous Mode Timer Clock Timer Block TASSELX 10x 16 bit Timer gt TAR Bi Choar R Input w w w 0 0 we 0 frae Ar CPE EE 421 521 Microcomputers Page 11 12 User s Manual CPE EE 421 521 Microcomputers Timer_A Capture Compare Blocks Capture Path Capture Compare Register CCR A Comparator x ISynchronize Capture Compare Path rw rw w rw 0 0 CAPTURE INBUT lun MQDE seect SCS SCCI useg CAP _OUTMODx w omw owe owe nwe owe nwe we we w rw rw 0 0 0 0 0 0 0 0 0 CPE EE 421 521 Microcomputers Timer_A Continuous Mode Example CCRO TAO Input input Capture Mode Positive Edge CCR1 TA1 Input Pxy Put Capture Mode Both Edges CCR2 TAZ Input pi Capture Mode Negative Edge CCRO CCR1 ICCR1 CCRIICCR
3. 1 Interrupts can be generated Oh ICCR2 Example shows three independent HW event captures CCRx stamps time of event Continuous Mode is ideal CPE EE 421 521 Microcomputers Timer_A Output Units OMx2 OMx1 OMx0 Function Operational Conditions Output Mode Outx signal is set according to Outx bit Set EQUx sets Outx signal clock synchronous with timer clock PWM Toggle Reset EQUx toggles Outx signal reset with EQUO clock syne with timer clock PWM Set Reset EQUx sets Out signal reset with EQUO clock synchronous with timer clock Toggle EQUx toggles Outx signal clock synchronous with timer clock Reset EQUx resets Outs signal clock synchronous with timer clock PWM Toggle Reset EQUx toggles Outx signal set with EQUO clock synchronous with timer clock PWM Set Reset EQUx resets Outx signal set with EQUO clock synchronous with timer clock CPE EE 421 521 Microcomputers Timer_A PWM Up Mode Example OFFFFH CCRO CCR1 CCR2 oh CCR1 PWM SetReset TA1 Output CCR2 PWM Reset Set C Mm PWM Toggle TAO Output COO Ta o ST Pxz o EQu2 Equ2 EQu2 EQuo EQUi Equo EQU1 EQUO Interrupts can be generated Output Mode 4 PWM Toggle Example shows three different asymmetric PWM Timings generated with the Up Mode CPE EE 421 521 Microcomputers Timer_A PWM Up Down Mode Example C Examples lt thipe gt include lt msp430x14x h gt ccro J1 MSP FET430P140 Deno Timer
4. CPE EE 421 Microcomputers Instructor Dr Aleksandar Milenkovic Lecture Note S18 Material used is in part developed by Dr D Raskovic and Dr E Jovanov CPE EE 421 521 Microcomputers Review Operating Modes for Basic Clock System SCG1 SCGO OSCOFF CPUOFF Mode CPU and Clocks Status 0 Active 1 LPMO CPU MCLK are SMCLK ACLK ai 1 LPM1 c are led OC ge CO is not used for CPU MCLK SMCLK DCO osc are disabled OC disabled LPM4 CPU and all clocks disabled CPE EE 421 521 Microcomputers MSP430 Documentation gt MSP430 home page TI www ti com msp430 gt User s manual http www ece uah edu milenka cpe421 04S manuals slau049c pdf gt Datasheet http www ece uah edu milenka cpe421 04S manuals slas272c pdf gt TI Workshop document http www ece uah edu milenka cpe421 04S manuals 430_ 2002 atc_workshop pdf gt IAR Workbench Tutorial http www ece uah edu milenka cpe421 04S manuals TUTOR pdf CPE EE 421 521 Microcomputers 2 Operating Modes for Basic Clock System Operating Modes General The MSP430 family was developed for ultralow power applications and uses different levels of operating modes The MSP430 operating modes give advanced support to various requirements for ultralow power and ultralow energy consumption This support is combined with an intelligent management of operations during the different module and CPU states An interrupt ev
5. PUOff and SCG1 in the status register are set Immediately after the bits are set CPU MCLK and SMCLK operations halt and all internal bus activities stop until an interrupt request or reset occurs Peripherals that operate with the MCLK or SMCLK signal are inactive because the clock signals are inactive Peripherals that operate with the ACLK signal are active or inactive according with the individual control registers and the module enable bits in the SFRs All I O port pins and the RAM registers are unchanged Wake up is possible by enabled interrupts coming from active peripherals or RST NMI CPE EE 421 521 Microcomputers Operating Modes Examples Q The following example describes ent nto low power mode 0 jain program flow with switch to CPUOff Mode BIS 18h SR Enter LPMO enable general int CPUOE GIE 1 The PC duri ution of this instr points to the consecutive pr The program continues here if bit is reset during the interrupt service routine Otherwise the PC retains its value and the processor returns to LPMO Q The following example describes clearing low power mode 0 nterrupt service routine CPU is act while handling interrupts BIC 10h 0 SP ic bit in the SR contents were stored on th the active state because the SR that are stored on jthe stack were manipulated Th curs because the SR is pushed onto the jupon an interrupt then restored jstack after the RETI instruction CPE EE 421 521 Microcomputers
6. _A Toggle P1 0 CCR2 CCRO Contmode ISR DCO SMCLK Description Toggle P1 0 using software and TA ISR Toggle rate is void main void set at 50000 DCO SHCLK cycles Default DCO frequency used for TACLK CCRI purring the TA_0 ISR P0 1 is toggled and 50000 clock cycles are perp WOTCTL WDTPW WDTHOLD Stop WDT CCR CCRO TAO ISR is triggered exactly 50000 cycles CPU is normally PIDIR 0x01 21 0 output oh off and cero ccr CCRO interrupt enabled MI onah only darting TAJM TA1 Output ACIK n a MCLK SMCLK TACLK DCO 800k CcRO 50000 oomey Li fo Fee 0 5xvmotor eee u TACTL TASSEL 2 MC_2 SMCLK contmode j u lt tpwi gt u mspa3or149 x gt TA2 Output F _BIS_SR LPMO_bits GIE Enter LPMO w interrupt 120 Degrees ee 3 n xmi 0 93xVmotor tpw2 iv n xour gt a 1 120 Degrees H ial m interrupt TIMERA0_VECTOR void TimerA void P1 01 gt 1ED 0 07xVmotor Pez u 1 m muccini P1OUT 0x01 Toggle P1 0 TIMOV Equo TIMOV EQUO TIMOV Interrupts can be generated f Waa SA H Biko S0000 r VA Aai orat eo Gone Timer AQ interrupt service routine 11 September 2003 Example shows Symmetric PWM Generation Built with IAR Embedded Workbench Version 1 268 1 December 2003 Digital Motor Control JI Updated for IAR Eabedded Workbench Version 2 218 sheusnevenensnenenesenesensuensuenanadenstenenenevesensdenauene
7. e Low power mode 0 LPMO SCG1 0 SCGO 0 OscOff 0 CPUOff 1 CPU is disabled MCLK is disabled SMCLK and ACLK remain active Low power mode 1 LPM1 SCG1 0 SCGO 1 OscOff 0 CPUOff 1 amp CPU is disabled MCLK is disabled DCO s dc generator is disabled if the DCO is not used for MCLK or SMCLK when in active mode Otherwise it remains enabled SMCLK and ACLK remain active Low power mode 2 LPM2 SCG1 1 SCGO 0 OscOff 0 CPUOff 1 CPU is disabled MCLK is disabled SMCLK is disabled DCO oscillator automatically disabled because it is not needed for MCLK or SMCLK DCO s de generator remains enabled ACLK remains active CPE EE 421 521 Microcomputers Operating Modes 2 Q Low power mode 3 LPM3 SCG1 1 SCGO 1 OscOff 0 CPUOff 1 CPU is disabled MCLK is disabled SMCLK is disabled DCO oscillator is disabled DCO s dce generator is disabled ACLK remains active Q Low power mode 4 LPM4 SCG1 X SCGO X OscOff 1 CPUOff 1 CPU is disabled ACLK is disabled MCLK is disabled SMCLK is disabled DCO oscillator is disabled DCO s dce generator is disabled Crystal oscillator is stopped CPE EE 421 521 Microcomputers Operating Modes Low Power Mode in details QLow Power Mode 4 LPM4 System Resets Interrupts and Operating Modes In low power mode 4 all activities cease only the RAM contents I O ports and registers are maintained Wake up is only possible by enabled exter
8. ent wakes the system from each of the various operating modes and the RETI instruction returns operation to the mode that was selected before the interrupt event The ultra low power system design which uses complementary metal oxide semiconductor CMOS technology takes into account three different needs O The desire for speed and data throughput despite conflicting needs for ultra low power Minimization of individual current consumption Q Limitation of the activity state to the minimum required by the use of low power modes CPE EE 421 521 Microcomputers Operating Modes General Another program flow may be selected by manipulating the data stored on the stack or the stack pointer Being able to access the stack and stack pointer with the instruction set allows the program structures to be individually optimized as illustrated in the following program flow O Enter interrupt routine The interrupt routine is entered and processed if an enabled interrupt awakens the MSP430 gt The SR and PC are stored on the stack with the content present at the interrupt event gt Subsequently the operation mode control bits OscOff SCG1 and CPUOff are cleared automatically in the status register Q Return from interrupt Two different modes are available to return from the interrupt service routine and continue the flow of operation Return with low power mode bits set When returning from the interrupt the program counter points
9. nal interrupts Before activating LPM4 the software should consider the system conditions during the low power mode period The two most important conditions are environmental that is temperature effect on the DCO and the clocked operation conditions The environment defines whether the value of the frequency integrator should be held or corrected A correction should be made when ambient conditions are anticipated to change drastically enough to increase or decrease the system frequency while the device is in LPM4 CPE EE 421 521 Microcomputers Operating Modes Low Power Mode in details QLow Power Mode 0 and 1 LPMO and LPM1 Low power mode 0 or 1 is selected if bit CPUOff in the status register is set Immediately after the bit is set the CPU stops operation and the normal operation of the system core stops The operation of the CPU halts and all internal bus activities stop until an interrupt request or reset occurs The system clock generator continues operation and the clock signals MCLK SMCLK and ACLK stay active depending on the state of the other three status register bits SCGO SCG1 and OscOff The peripherals are enabled or disabled with their individual control register settings and with the module enable registers in the SFRs All I O port pins and RAM registers are unchanged Wake up is possible through all enabled interrupts QLow Power Modes 2 and 3 LPM2 and LPM3 Low power mode 2 or 3 is selected if bits C
10. nenene CPE EE 421 521 Microcomputers CPE EE 421 521 Microcomputers
11. r the pin Bit 1 Peripheral module function is selected for the pin CPE EE 421 521 Microcomputers C Examples MSP FET430P140 Demo BasicClock Output buffered SMCLK ACIK and MCLK Description Output buffered MCLK SMCLK and ACLK ACLK LEXT1 32768 MCLK DCO Max SMCLK x72 XTAL s REQUIRED NOT INSTALLED ON FET MSP430F149 XT2IN1 XTAL 455k ehz xr20ur 1 P5 41 gt MCLK DCO Max P5 51 gt SMCLK x02 P5 6 gt ACLK 32kHz M Buceini Texas Instruments Inc January 2004 Updated for IAR Embedded Workbench Version 2 218 include lt msp430x14x h gt void main void WDTCTL WDTPW WDTHOLD Stop Watchdog Timer DCOCTL DCOO DCO1 DCO2 Max DCO BCSCTL1 RSELO RSEL1 RSEL2 XT2on max RSEL BCSCTL2 SELS SMCLK XT2 PSDIR 0x70 P5 6 5 4 outputs PSSEL 0x70 5 6 5 5 options while 1 y CPE EE 421 521 Microcomputers Timer_A MSP430x1xx 16 bit counter with 4 operating modes Selectable and configurable clock source Three or five independently configurable capture compare registers with configurable inputs Three or five individually configurable output modules with 8 output modes multiple simultaneous timings multiple capture compares multiple output waveforms such as PWM signals and any combination of these Interrupt capabilities each capture compare block individually configurable CPE EE 421 521 Microcomputers
12. to the next instruction The instruction pointed to is not executed since the restored low power mode stops CPU activity Return with low power mode bits reset When returning from the interrupt the program continues at the address following the instruction that set the OscOff or CPUOff bit in the status register To use this mode the interrupt service routine must reset the OscOff CPUOff SCGO and SCG1 bits on the stack Then when the SR contents are popped from the stack upon RETI the operating mode will be active mode AM CPE EE 421 521 Microcomputers Low power mode control There are four bits that control the CPU and the main parts of the operation of the system clock generator CPUOff OscOff SCGO and SCG1 These four bits support discontinuous active mode AM requests to limit the time period of the full operating mode and are located in the status register The major advantage of including the operating mode bits in the status register is that the present state of the operating condition is saved onto the stack during an interrupt service request As long as the stored status register information is not altered the processor continues after RETI with the same operating mode as before the interrupt event CPE EE 421 521 Microcomputers Operating Modes Software configurable There are six operating modes that the software can configure Q Active mode AM SCG1 0 SCGO 0 OscOff 0 CPUOff 0 CPU clocks are activ
13. uters CPE EE 421 521 Microcomputers Digital I O Registers Operation Input Register PniIN Each bit in each PnIN register reflects the value of the input signal at the corresponding I O pin when the pin is configured as I O function Do not write to PxIN It will result Bit 0 The input is low in increased current consumption Bit 1 The input is high Output Registers PhOUT Each bit in each PnOUT register is the value to be output on the corresponding I O pin when the pin is configured as I O function and output direction Bit 0 The output is low Bit 1 The output is high CPE EE 421 521 Microcomputers Digital I O Operation Interrupt Flag Registers P1IFG P2IFG only for P1 and P2 Bit 0 No interrupt is pending Bit 1 An interrupt is pending Only transitions not static levels cause interrupts Interrupt Edge Select Registers P1IES P2IES only for P1 and P2 Each PnIES bit selects the interrupt edge for the corresponding I O pin Bit 0 The PnIFGx flag is set with a low to high transition Bit 1 The PnIFGx flag is set with a high to low transition CPE EE 421 521 Microcomputers Digital I O Operation Direction Registers PnDIR Bit 0 The port pin is switched to input direction Bit 1 The port pin is switched to output direction Function Select Registers PnSEL Port pins are often multiplexed with other peripheral module functions Bit 0 I O Function is selected fo
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