Specification of Hazards, Stalls, Interrupts, and Exceptions in
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1. lt hazard_list gt lt hazard type gt lt hazard_detection_action_list gt lt hazard_list gt NULL lt hazard type gt RAW WAR WAW lt hazard_detection_action_list gt lt function_unit_name gt lt operation_name gt lt action gt lt hazard_detection_action_list gt lt function_unit_name gt The unit which handles that hazard lt operation_name gt The operation during which the hazard occurs lt action gt NO ACTION OPERATION STALL UNIT STALL PIPE STALL GLOBAL STALL Following example shows the hazard specification for a typical architecture using the above grammar Each type of hazard RAW WAR WAW may occur in more than one place in the architecture RAW happens in three issue units ALU1 and LDST in the example shown below We specify during which operation operation read operation issue operation graduation execution etc does this hazard occur The last field specifies the necessary action need to be taken when this hazard is detected Unit Control HAZARDS RAW INTISSUE OPREAD NO ACTION FLTISSUE OPREAD OPERATION STALL MEMISSUE OPREAD UNIT STALL ALU1 OPREAD PIPE STALL LDST OPREAD GLOBAL STALL WAR DECODE OPISSUE GLOBAL STALL WAW COMPLETION GRADUATE UNIT STALL 2 2 Control Hazards Control hazards due to branches can have different outcome depending on how the branch is handled for that architecture The actions2. BC7 ID BC8 RE BC9 EX lt else gt k NOP IF BC10 AC w pc BC11 PF BC12 1D BC13 RE k NOP ID BC14 EX k NOP ID k NOP AC k NOP AC k NOP RE k NOP RB k NOP EX k NOP EX lt operate gt BC1 control ebus_addr pc BC2 control ir mem ebus_addr pc BC10 control pc SOPCODE2 LISA and RADL have similar mechanism for hazard detection and pipeline flushing These are very much tied to the architecture For example in LISA the L chart for each operation e g BC describes which operations to be killed at which particular pipeline stage During design space ex ploration where designers want to change pipeline stages parallelism etc these techniques are not useful since for every change in the architecture all the operations needs to be re written More over the specification technique is not general enough to model hazards or pipeline flushes in contemporary DSP VLIW and Superscalar architectures nML has very primitive interrupt speci fication mechanism which is not powerful enough to model the the interrupts exceptions and their complex interactions e g handling multiple exceptions available in contemporary architectures In other words existing hazards and interrupts specification techniques are not good candidates for design space exploration of wide spectrum of processor memory architectures Section 2 describes how we specify hazards and stalls in EX
3. Publishers Inc San Mateo CA 1990 9 V Rajesh and R Moona Processor modeling for hardware software codesign In International Conference on VLSI Design Jan 1999 10 C Siska A processor description language supporting retargetable multi pipeline dsp program development tools In Proc ISSS Dec 1998 11 Tensilica Incorporated http www tensilica com 12 Trimaran Release http www trimaran org The MDES User Manual 1997 16 Table 1 Interrupts and exceptions for the family of PowerPC architecture Interrupt Exception pe Async Sync Sync Critical AAA A A ee Es o AS E Wie access control fx _ o Byte ordering fi x Cd Cache Tocking fi x fd J Siorage synchronization x _ Oo Tnsruction Storage Execute access control x id O Be orden x External Input_ _Extemaf inp x _ oo C Aime _Alignment__ x _ Program Enabled x x i iegatinstruction ff x FF Privitegedinstruction fx _ ee o YP Unimmplemmented operation x i Oo FP Unavailable FP unavailable x _ C Systemi ___SystemCall AP Unavailable AP unavailable a RO Fxediniervaltimer A C Wachdogimer x D lt Data TER error TB MS Jx E Tage address error a instruction TLB eror TB Ms x _ PS Tage address error x bg x l ast Rae Compare A e Bata Addr compare x x x struction complete x x Brant iP x Cd x S Retr From interrupt E irte
4. due to branch mis prediction can be specified either in the branch opcode or in the functional unit which handles branch operation It appears more appro priate to specify the actions in the functional unit which handles branch operation The following piece of code shows the actions taken during branch mis prediction for a typical processor If misprediction updatePC updateBTB selectiveFlush UpdatePC and updateBTB are self explanatory We consider two kinds of flushing here viz selective flushing and complete flushing In selective flushing all the instructions ahead in se quential order of mis predicted branch are allowed to graduate and all the instructions came to pipeline after the mis predicted branch are flushed In complete flushing all the instructions in the pipeline are flushed 2 3 Structural Hazards Structural information are provided using reservation tables During static scheduling compile time this resource information is used In execution time structural hazards leads to different kinds of stalls viz pipe stall unit stall global stall etc depending on the architecture 6 3 Specification of Interrupts and Exceptions We classify interrupts into three categories This classification is motivated from the ease of specification point of view e External interrupts reset power on etc e Software Hardware interrupts related to functional unit illegal slot exception etc e Software exceptions rel
5. step trap TI C6x interrupts Reset highest priority NMI INT4 INTS INT6 13 6 INT7 7 INTS 8 INTO 9 INTIO 10 INT11 11 INT12 12 INT13 13 INT14 14 INT15 lowest priority Reset is used to halt the CPU and return it to a known state Non maskable interrupt NMI is used to alert the CPU of a serious hardware problem such as imminent power failure The remaining twelve interrupts viz INT4 to INT15 can be associated with external devices on chip peripherals software control or not be available C6x programmer guide explains how to interrupt a function always or a particular number of times by using the pragma in C program as shown below pragma FUNC_INTERRUPT_THRESHOLD func 1 Always pragma FUNC_INTERRUPT_THRESHOLD func threshold To generate interrupt service routine ISR the Interrupt keyword should be used Alternatively to define a existing function as an ISR pragma can be used as shown below Interrupt void int_handler OR pragma INTERRUPT func unsigned int flags Enabling and disabling interrupts is done through control status register CSR 3 6 4 R10K interrupts The priority of the exceptions are shown below Each exception is handled processed by hard ware and then serviced by software 1 Cold reset highest priority 2 Soft reset 3 Non maskable interrupt NMI 14 4 Cache error instruction cache 5 Cache error data cache 6 Cache error s
6. using the resource descriptor w and it performs the write during the IE operation specified by the w descriptor Instruction 2 shown shifted attempts to read register RO during the decode operation the r descriptor is used Using the supplied information the data hazard on register RO can be easily detected and resolved using interlocking as shown below The same mechanism is used to describe control hazards and effects of short circuiting IF ID w RO IA IE w RO IF nop nop ID r RO IA IE In order to describe pipeline flushing LISA permits some of the control instructions to explicitly change the sequencing mechanism of the generic machine model It introduced the k descriptor for operations e g k 03 The kill descriptor is described in the example given below The example is the LISA machine description of TMS320C54x branch conditional BC instruction The kill descriptor simply overloads the operation in the specified stage with its own operation in this case NOP In this way operation cancellation takes place to stop further propagation issuing of the instructions which are supposed to be flushed due to branch mis prediction lt insn gt BC lt decode gt SID 0x7495 0x0493 Scond_code SOPCODE1 amp Ox7F Sdest_address SOPCODE2 lt schedule gt BC1 PF w ebus_addr w pc BC2 PF w pc BC3 IF BC4 ID lt if gt condition cond_code BC5 AC BC6 PF
7. PRESSION 7 The explicit spec ification of interrupts and exceptions in EXPRESSION is described in Section 3 Section 3 also includes the examples of interrupts and exceptions for contemporary VLIW and superscalar archi tectures 2 Specification of Hazards and Stalls There are three classes of hazards 1 Structural hazards arise from resource conflicts when the hardware cannot support all pos sible combinations of instruction in simultaneous overlapped execution 2 Data hazards arise when instructions depend on one another in a way that is exposed by the overlapping of instructions in the pipeline 3 Control hazards arise from dependencies on branches and other instructions that changes the PC 2 1 Data Hazards We capture the data hazard information of the processor by specifying the functional unit which detects the hazard It also captures whenever possible the operation which causes the hazard We consider three classes of data dependent hazards according to various data update patterns write after read WAR hazards read after write RAW hazards and write after write WAW hazards Note that read after read RAR does not pose a problem because nothing is changed The hazard problem can be solved by data forwarding also called bypassing and sometimes short circuiting whenever possible In general pipeline gets stalled when a hazard is detected Stall can be local where only the instruction is stalled Now this has diffe
8. Specification of Hazards Stalls Interrupts and Exceptions in EXPRESSION Prabhat Mishra Nikil Dutt Alex Nicolau pmishra ics uci edu dutt ics uci edu nicolau ics uci edu Architectures and Compilers for Embedded Systems ACES Laboratory Center for Embedded Computer Systems University of California Irvine CA USA http www cecs uci edu aces Technical Report 01 05 Dept of Information and Computer Science University of California Irvine CA 92697 USA January 2001 1 Introduction Recent work on language driven Design Space Exploration DSE 1 2 3 4 6 7 9 11 12 uses Architectural Description Languages ADL to capture the processor architecture generate automatically a software toolkit including compiler simulator and assembler for that processor and provide feedback to the designer on the quality of the architecture However none of these ADLs have explicit way of describing hazards and interrupts for wide variety of processors and memory architectures The nML 6 LISA 5 and RADL 10 proces sor description languages are closet to our work We describe in detail the hazard and interrupt specification techniques for these languages The RADL 10 processor description language supports interrupts and hazards specification Hazard Stall specification is closely tied to the architecture and hence not good candidate for ar chitectural exploration Moreover the paper does not demonstrate how to ap
9. ated to opcodes like divide by zero TLB miss etc v a Unit related Opcode related Figure 1 Different types of interrupts 3 1 Opcode related interrupts It is appropriate to describe opcode related interrupts and it s actions inside the opcode specifica tion For example modified DIV opcode is shown below after adding the exception information Please note that the last line is newly added the remaining three lines exist in the original EX PRESSION description OPCODE DIVW OP_TYPE DATA_OP OPERANDS _SOURCE1_ gpr _SOURCE_2_ gpr _DEST_ gpr BEHAVIOR _DEST_ SRC1 SRC2 if SRC2 0 throw D exception 3 2 Interrupts Related to Functional Units Functional unit related interrupts should be defined in functional unit specification For example illegal slot instruction can be described in decode unit Unit Decode CAPACITY 2 TIMING all 1 OPCODES all PORTS Obj3 Obj5 Obj36 Obj2 if SLOT4 opcode LDST_type throw illegal slot instruction 3 3 External Interrupts External interrupts can be specified in the control unit 3 4 Interrupt Handler Interrupt handler will have a priority table and will be able to accept n number of excep tion interrupt requests and generate only one interrupt per cycle There may not be one interrupt associated with each exception A class of exceptions may give rise to one interrupt in that case architecture implementation should ensure only one excep
10. econdary cache 7 Cache error system interface 8 Address error instruction fetch 9 TLB refill instruction fetch 10 TLB invalid instruction fetch 11 Bus error instruction fetch 12 Integer overflow trap system call breakpoint reserved instruction 13 unusable floating point exception 14 Address error data access 15 TLB refill data access 16 TLB invalid Data access 17 TLB modified data write 18 Watch 19 Bus error data access 20 Interrupt lowest priority References 1 ARC Cores http www arccores com 2 G G et al CHESS Retargetable code generation for embedded DSP processors In Code Generation for Embedded Processors Kluwer 1997 3 G H etal ISDL An instruction set description language for retargetability In Proc DAC 1997 4 R L et al Retargetable generation of code selectors from HDL processor models In Proc EDTC 1997 5 V Z et al LISA machine description language and generic machine model for HW SW co design In IEEE Workshop on VLSI Signal Processing 1996 6 M Freericks The nML machine description formalism Technical Report TR SM IMP DIST 08 TU Berlin CS Dept 1993 7 A Halambi P Grun V Ganesh A Khare N Dutt and A Nicolau EXPRESSION A language for architecture exploration through compiler simulator retargetability In Proc DATE Mar 1999 15 8 J Hennessy and D Patterson Computer Architecture A quantitative approach Morgan Kaufmann
11. iP i xd S YF Toma debug event x x ttt EHH CLE 17
12. imer 8 Debug e HW SW exceptions describe in functional unit Data Storage Instruction Storage Program FP Unavailable System Call AP Unavailable Data TLB error o Ny DD Nn ho Nel Instruction TLB error 3 6 2 IA 64 interrupts 1 2 10 11 12 Machine reset Machine check Initialization interrupt Platform management interrupt External interrupt IR unimplemented data address fault IR data nested TLB fault IR alternate data TLB fault IR VHPT data fault IR data TLB fault IR data page not present fault IR data NaT page consumption fault 10 13 14 15 16 17 18 19 20 212 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 IR data key miss fault IR data key permission fault IR data access rights fault IR data access bit fault IR data debug fault IA 32 instruction breakpoint fault IA 32 code fetch fault Alternate instruction TLB fault VHPT instruction fault Instruction TLB fault Instruction page not present fault Instruction NaT page consumption fault Instruction key miss fault Instruction key permission fault Instruction access rights fault Instruction access bit fault Instruction debug fault IA 32 instruction length 15 bytes IA 32 invalid opcode fault IA 32 instruction intercept fault Ilegal operation fault Illegal dependency fault Break instruction fault Privileged operation fault Disabled floating p
13. oint register fault 11 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Disabled instruction set transition fault IA 32 device not available fault IA 32 FP error fault Register NaT consumption fault Reserved register field fault Unimplemented data address fault Privileged register fault Speculative operation fault IA 32 stack exception IA 32 general protection fault Data nested TLB fault Alternate data TLB fault VHPT data fault Data TLB fault Data page not present fault Data NaT page consumption fault Data key miss fault Data key permission fault Data access rights fault Data dirty bit fault Data access bit fault Data debug fault Unaligned data reference fault IA 32 alignment check fault TA 32 locked data reference fault 12 63 64 65 66 67 68 69 70 71 T2 73 74 75 76 T1 78 79 80 81 3 6 3 IA 32 segment not present fault IA 32 divide y zero fault IA 32 bound fault IA 32 streaming SIMD extension numeric error fault Unsupported data reference fault Floating point fault Unimplemented instruction address trap Floating point trap Lower privilege transfer trap Taken branch trap Single step trap IA 32 system flag intercept trap IA 32 gate intercept trap IA 32 INTO trap IA 32 breakpoint trap IA 32 software interrupt trap IA 32 data breakpoint trap IA 32 taken branch trap IA 32 single
14. ply this technique for VLIW and Superscalar processors RADL has one declarative part for interrupt handling It allows multiple program counters and could specify the program counter in the pipe line control section declaratively On a given signal which indicates an interrupt it fetches using an alternative PC However register file save and restore along with interrupt disable and re enable was left to be procedural Moreover this language mechanism does not correspond to any hardware implemen tation So while it leads to cycle and phase accurate instruction behavior it may not accurately reflect internal hardware state The paper does not give any examples of interrupt specification It provides example for hazard detection and stalling using the simple DLX pipeline as described in Hennessey and Patterson 8 figure 3 4 It detects hazard using its load interlock detection logic and sets the appropriate control signal load_raw say The strategy to perform the stall using load_raw is as follows load_raw ID stall NOP load_raw signal decides whether the above strategy is applicable The second element ID indicates the pipeline stage involved The third element stall NOP indicates that NOP in struction will be inserted into the stage just after the ID stage The ID stage and all other upstream stages are stalled The rest of the stages MEM and WB will continue to flow smoothly In RADL sometimes kill construct is u
15. rent implications in different scenarios In case of in order execution semantics stalling a operation means stalling everything if the architec ture does not have reservation station anywhere If it has reservation station in units which have space to accommodate incoming operations then the above scenario would mean stalling that par ticular functional unit which detected the hazard If it has out of order execution semantics then it means only operation stalling Some hazards may not happen for particular architectural style For example WAW and WAR is not possible when architecture has register renaming Detection of a hazard does not mean it would stall operation functional unit that particular pipe or the complete architecture It may not do anything at all and issue the operation For example if a architecture supports snooping reading operands using bypass logic in execution unit then issue unit can issue the operation evenif one or both of its operands are not ready RAW hazard Based on this discussion we classify the stall due to data hazard into the following five cate gories First four of them belongs to local stall category e NO ACTION e OPERATION STALL e UNIT STALL e PIPE STALL Stalls only that particular pipe in case of fragmented pipeline e GLOBAL STALL We specify the hazard and stall information in control unit The syntax of this specification is shown below Unit Control HAZARDS lt hazard_list gt
16. rupt service register ISR in interrupt handler unit Inter rupt handler decides the highest priority interrupt using interrupt priority table Now the question 8 remains how do we specify explicitly what happens to the remaining interrupts This is system specific In general external interrupts are serviced one after the other in the priority order unless masked by earlier one before resuming the program execution The software interrupts caused due to program execution which got flushed can be ignored since they will be generated again once execution is resumed Masking information for each interrupt need to be captured explicitly In general interrupts are not allowed to interrupt an interrupt service routine However NMI in c6x is allowed to interrupt the execution of lower priority interrupts NMI saves the state completes execution and then earlier interrupt execution is resumed The family of PowerPC architectures execute all the interrupts based on priority and gurranted to report in program order Only excep tion is in the case of multiple synchronous imprecise interrupts where synchronizing event ensures all previously unreported exceptions are reported An interrupt of an exception class masks the interrupts of the classes having equal or lower priority This may not mean an exception which might have caused an interrupt otherwise is lost It could be stored in temporary register and later when that particular type of interrupt i
17. s enabled might be serviced In our scheme we can mask all the equal or lower priority interrupts Service all the external interrupts not generated due to program execution Enable all the pending interrupts Now these pending interrupts were generated due to program execution which are expected to generate while execution resumes If they don t get generated again have two possibilities viz e The program code segment which generated this interrupt have been completed successfully e The exception is not valid any more For example TLB miss processing for one load oper ation can suppress the TLB miss exception for the other one An synchronizing event should ensure if necessary that all the pending interrupts are enabled 3 6 Example architectures interrupts and exceptions 3 6 1 PowerPC Family Table 1 shows all the interrupt and exception category possible in the family of PowerPC architec tures It also shows what category does each exception belong to viz asynchronous synchronous precise synchronous imprecise Table also shows the critical interrupts We can classify the the exceptions shown in Table in the three major categories mentioned earlier depending on where we want to capture them in EXPRESSION It does not have exception for the opcode category e External describe in Control unit 1 Critical Input 2 Machine Check 3 External Input 4 Alignment 5 Decrementer 6 Fixed interval timer 7 Watchdog t
18. sed to replace an instruction with stalling upstream stages The nML processor description language 6 has explicit way of describing interrupts The example shown below is given in the paper The example assumes an interrupt register that may hold a value of O or an interrupt number that serves as index into some vector array stored at address 256 mem interrupt_register 1 card 4 volatile irq op instruction i rest_instruction action i action if interrupt_register 0 then STORED_PC PC PC M interrupt_register lt lt 2 0x100 interrupt_register 0 endif The interrupt register is marked as volatile i e changing its value If some non zero value appears the PC is stored in some intermediate location or put on the stack or whatever and changed to the address found at the index Of course on a real machine much more happens the current CPU state is stored special mode bits are set interrupts may be masked etc LISA 5 Gnatt chart based models to detect structural hazards In order to detect data and control hazards and perform pipeline flushes it uses extended Gnatt charts by introducing L charts and operation descriptors The following example shows two instructions producing a hazard IF ID w RO IA IE w RO instruction 1 IF ID r RO IA TE instruction 2 Instruction 1 reserves register RO for writing already during the ID operation by announcing the write access to register RO
19. tion from that class happens at a time If each exception corresponds to a particular interrupt then actions for each interrupt can be described where exception is described viz in opcode or in unit In general one interrupt corresponds to more than one exception We specify the interrupts and exceptions in control unit The syntax of this specification is shown below Unit Control INTERRUPTS lt interrupt_list gt lt interrupt_list gt lt Interrupt gt lt interrupt_list gt NULL lt Interrupt gt INTERRUPT lt interrupt_name gt EXCEPTIONS lt exception_list gt OPERANDS lt operand_list gt BEHAVIOR lt behavior of ISR gt lt interrupt_name gt name of the interrupt lt exception_list gt The list of exceptions which give rise to that particular interrupt lt behavior of ISR gt Behavioral description of the interrupt service routine for the interrupt lt interrupt_name gt For example interrupt INT1 is described below INT1 gets generated due to any memory failure during memory operation e g ITLB miss DTLB miss etc Interrupt INT1 EXCEPTIONS ITLB_MISS DTLB_MISS OPERANDS BEHAVIOR SelectiveStall Save state SetPC INT1 address ExecuteISR1 Updates TLB Restore state 3 5 Multiple Exceptions As we discussed earlier interrupt handler is responsible for handling multiple exceptions Each exception sets one particular bit of inter
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