AD481 User Manual - 4DSP LLC
Contents
1. AD481 user manual 3 2 FPGA devices configuration 3 2 1 Flash storage The FPGA firmware is stored on board in a flash device The 128Mbit device is partly used to store the configuration for both FPGAs In the default CPLD firmware configuration the Virtex 4 devices A and B are directly configured from flash if a valid bitstream is stored in the flash for each FPGA The flash is pre programmed in factory with the default firmware example for both FPGAs 128Mbit Flash l 929GL126M amp bit parallel configuration CoolRunner ll CPLD Virtex 4 device A XC2C256 CP132 Figure 3 Configuration circuit 3 2 2 CPLD device As shown on Figure 2 a CPLD is present on board to interface between the flash device and the FPGA devices It is of type CoolRunner ll The CPLD is used to program and read the flash The data stored in the flash are transferred from the host motherboard via the PCI bus to the Virtex 4 device A and then to the CPLD that writes the required bit stream to the storage device A 31 25 MHz clock connects to the CPLD and is used to generate the configuration clock sent to the FPGA devices At power up if the CPLD detects that an FPGA configuration bitstream is stored in the flash for both FPGA devices it will start programming the devices in SelectMap mode Do NOT reprogram the CPLD without 4DSP approval The CPLD configuration is achieved by loading with a Xilinx download2. 4a Pn4to4ofacit m4 Pna toa 42 43 Pn4to42 na_ T9 Pmios 44 45 Pn4io4s4 t8s P5 Prd 045 46 47 Png to4e R5 Aamo Pn4i047 48 49 Pn4 1048 AaB1o P4 Pn4io49g 50 51 Pn4 io50 R3 wio Pn4io51 52 53 Pn4 1052 10 Na Pn i053 54 55 Pn41054 Pp3 uUe Pn4i055 56 57 Pn4io56 u5s T4 Pn4i057 58 59 Pn4 i058 T3 u7 Pn i059 6o 61 Pn4io60 ve u4 Prd tet 62 63 Pn4ios2 v4 u9 Pn4ios3s 64 Table 2 Pn4 pin assignment AD481 User manual november 2008 www 4dsp com 8 HOS AD481 user manual 3 1 2 Virtex 4 device B 3 1 2 1 Virtex 4 device B family and package The Virtex 4 device B is dedicated to interfacing to the A D circuitry and can also perform Digital Signal Processing algorithms It is available in the Virtex 4 SX or LX family devices and is packaged in a 1148 ball Fineline Ball Grid array In terms of logic and dedicated DSP resources The FPGA B can be chosen in 5 different sizes SX55 LX40 LX60 LX80 LX100 and LX160 3 1 2 2 Virtex 4 device B external memory interfaces The Virtex 4 device B interfaces to four 8Mbytes QDR2 SRAM devices with 32 bit data bus Please note that the four QDR2 SRAM devices are only available with the LX80 LX100 and LX160 devices For smaller Virtex 4 FPGAs LX40 LX60 and SX55 only three QDR2 SRAM devices are connected to the FPGA AD481 User manual november 2008 www 4dsp com 9 HOS
3. AD481 user manual p External External x 2 5Gb s optical transceivers triggers Analog outputs clock iad a Gigabit Ethernet iomon FE D A D A Ciocks 14 bit 14 bit generation and 1000MHz ff 1000MHz distribution Low jitter local oscillator QDR2 SRAM a Bre ODR2 SRAM E l Not on LX40 60 or SX5 QDR2 SRAM XC4VSX55 Configuration circuit XC4VLX40 60 and JTAG XC4VLX80 100 160 FPGA A XC4VEX20 60 DDR Local PCI bus Sp N interface 32 or 6 4 yyy User VO PCI X PCI 66 33MHz 6 4 32 bit Power supply DC DC converters Figure 1 AD481 block diagram The AD481 converts 2 14 bit digital data streams into two analogue signals The digital to Analogue conversion is performed by the MB86064 Device with a conversion rate up to 1000 MSPS per channel The clock source can be set to external or internal using the software and firmware settings available to users Please note that the clock generation is using low jitter clock synthesizers AD481 User manual november 2008 www 4dsp com 5 HOS AD481 user manual 2 Installation 2 1 Requirements and handling instructions e The AD481 must be installed on a motherboard compliant to the IEEE Std 1386 2001 standard for 3 3V PMC e Do not flex the board e Observe SSD precautions when handling the board to prevent electrostatic discharges
4. DAC Output Analog Signal Signal on inside of connector GND on outside of connector Channel pos AC Coupling single ended and pos side of DC coupling differential Poe Poe DAC Output Analog Signal Signal on inside of connector GND on outside of connector Channel neg DC Coupling only differential signal split over both connectors E DAC Output Analog Signal Signal on inside of connector GND on outside of connector Channel pos AC Coupling single ended and pos side of DC coupling differential DAC Test Clock LVPECL output test clock Copy of clock going to DAC Postive on inside of Output connector negative on outside of connector Used for verification of the clock going to the DAC External RF clock External Analog input Clock to DAC Clock on inside of connector DGND on the input outside of connector External ECL clock External ECL input Clock to DAC Positive on inside of connector negative on input the outside of connector Table 8 DAC281 component locations Diagram Pcb Description Ref RefDes J J8 FPGA MSP FPGA MSP430 on SMT338 VP JTAG routed down to SMT338 VP Use for JTAG Connector without having to remove the SMT381 an a TRANS2 M A Com TP101 By default the SMT381 analog input through a twisted pair balum transformer Transformer single ended It is possible to change this to DC coupled by taking out the transformer and installing some resistors on the board TRANS1 M A Com T
5. 9 DAC281 clock tree The clock synthesizer does not offer a clock as good as the VCO does Therefore the performances of the module degrade when using the clock synthesizer and it is recommended to use the VCO whenever possible The FPGA controls the LVPECL multiplexers that drive the clock fed to the ADC device clock synthesizer PLL VCO or external The selected clock is distributed to the DAC and the FPGA on the host module for synchronization purposes The digital interface works in a Dual data rate mode which means that the clock from the DAC to the FPGA runs at half the conversion frequency 3 8 Front Panel optical transceivers Four 2 5Gb s optical transceivers LTP ST11M are available on the AD481 in the front panel area They are connected to the MGT I Os of the Virtex 4 device A Infiniband protocols as well as Gigabit Ethernet and Fibre channel SFPDP can be implemented over the transceivers Lower rate optical transceivers 2 125Gb s and 1 0625Gb s are available in the same form factor AD481 User manual november 2008 www 4dsp com 16 HOS Two low jitter clocks 106 25MHz and 125MHz are directly connected to the MGT clock inputs so multi rate applications can be implemented on the AD481 The MGT banks have power supplies independent from the digital supply provided to the FPGAs in order to insure low noise and data integrity The LT1963 device will be used to generate the 1 2V 1 5V and 2 5V necessary for the MGT
6. ON o Flash is busy writing or erasing OFF No CRC error detected Table 4 LED board status AD481 User manual november 2008 www 4dsp com 11 HOS AD481 user manual CPLD LEC3 CPLD LEC2 CPLD LEC CPLD LECO SITIES EEE GJ PELI a 411114314 Sf Figure 5 CPLD LED locations 3 2 3 JTAG A JTAG connector is available on the AD481 for configuration purposes The JTAG can also be used to debug the FPGA design with the Xilinx Chipscope The JTAG connector is located on side 1 of the PCB in front see Figure 6 P TE a JTAG connector biter Iogan r bi E 4 p E p Wg kei Me H Eig JT ome bis Figure 6 JTAG connector J6 location The JTAG connector pinout is as follows Signal Signal Pin TCK TDO 6 Table 5 JTAG pin assignment AD481 User manual november 2008 www 4dsp com 12 HOS AD481 user manual 3 3 Clock tree The AD481 clock architecture offers an efficient distribution of low jitter clocks In addition to the PCI Express bus the MGT reference clocks of 106 25MHz and 125MHz Epson EG2121CA make it possible to implement several standards over the MGT I Os connected to the optical transceivers Both FPGAs receive a low jitter 125MHz clock A low jitter programmable clock able to generate frequencies from 62 5MHz to 255 5MHz in steps of 0 5MHz is also available This clock management approach ensures maximum flex
7. can serve as data buffer AD481 User manual november 2008 www 4dsp com 6 HOS AD481 user manual 3 1 1 4 PCI interface The Virtex 4 device A interfaces directly to the PCI bus via the PMC Pni Pn2 and Pn3 connectors or to the PCl e bus via the Pn5 An embedded PCI core from Xilinx is used to communicate over the PCI bus with the host system on the motherboard PCl e 4 lanes PCI X 64 bit 66MHz2 133MHz PCI 64 bit 66MHz and PCI 32 bit 33MHz are supported on the AD481 The bus type must be communicated at the time of the order so the right Virtex 4 device A firmware can be loaded into the flash prior to delivery The following performances have been recorded with the AD481 transferring data on the bus gt PCI X 64 bit 133MHz 750Mbytes s sustained gt PCI X 64 bit 66MHz 425Mbytes s sustained gt PCI 32 bit 33MHz 112Mbytes s sustained Without any data reduction it is therefore possible to transfer over a PCI X bus two digitized signals with a 12 bit resolution each The resulting bandwidth would be 630Mbytes s The PCl express 4 lane is using the MGT I Os on the Virtex 4 device A Power filtering low jitter clock and special routing are used to achieve the performances required by this standard Please refer to the Front Panel Optical transceivers section of this document for more details 3 6 3 1 1 5 LED Four LEDs are connected to the Virtex 4 device A In the default FPGA firmware the LEDs are driven by the Virte
8. mode An external power connector J2 is available on side 2 of the PMC next to the PMC connectors lt is used to power the board when it is in stand alone mode This is a right angled connector and it will be mounted on board only if the card is ordered in its stand alone version AD481 SA The height and placement of this connector on the PCB breaches the PMC specifications and the module should not be used in an enclosed chassis compliant to PMC specifications if the external power connector is present on board Do not connect an external power source to J2 if the board is powered via the PMC connectors Doing so will result in damaging the board The external power connector is of type Molex 43045 1021 Each circuit can carry a maximum current of 5A The connector pin assignment is as follows 2 3 5 GND GND 6 7 GND GND 8 9 tav i2v 10 Table 10 External power connector pin assignment AD481 User manual november 2008 www 4dsp com 19 HOS AD481 user manual 5 System Side view The following diagram shows a side view of the AD481 mounted a motherboard RF Daughtercard PCB Inter PCB Connector ADC Tei mm Loo 12 i a a aaa u a a S C7 O On enna A U 4 OSOE SE Stand off Figure 12 System side view 6 Environment 6 1 Temperature Operating temperature e 0C to 60 C Commercial e 40C to 85 C Industrial Storage temperature e 40C to 120C 6 2 Convecti
9. External sampling clock inputs LVPECL Clock Signal format LVPECL Frequency range 25MHz to 1000 MHz RF Clock Signal format Sinus wave 25MHz to 1000 MHz OdBm Typ Frequency range Amplitude External trigger inputs Signal format LVPECL DC to 100 MHz ADC Performance Single tone at 1dBFS 800MSa s DC to 400MHz From DAC datasheet Spurious Free Dynamic Range SFDR 20MHz 75dBc Frequency range Spurious Free Dynamic Range SFDR 300MHz 58dBc Cross talk 4 tone test each tone at 15dBFS centred at 276MHz 67dBc 3 6 DAC connector locations The following diagram indicates the location of all the important connectors and components on the DAC281 PCB in Gea T TEETE A ga SIERE pain lame y Tmi ss ix pu TE FE I Tpi ae ee h i a tin ae TE LELELLEELELEL ELS v ral EIK i j ma Ha D ue Figure 8 DAC281 top view AD481 User manual november 2008 www 4dsp com 14 HOS AD481 user manual Table 7 DAC281 connector locations Diagram Pcb Description Ref RefDes External Trigger B LVPECL Signal Positive on inside of connector Negative on outside of Channel connector External Trigger A LVPECL Signal Positive on inside of connector Negative on outside of Channel connector DAC Output Analog Signal Signal on inside of connector GND on outside of connector Channel neg DC Coupling only differential signal split over both connectors
10. HOS AD481 user manual AD481 User Manual 4DSP Inc 955 S Virginia Street Suite 214 Reno NV 89502 USA 4DSP bv Crown Business Centre Leidse Schouw 2 2408 AE Alphen a d Rijn Netherlands Email support 4dsp com This document is the property of 4DSP Inc and may not be copied nor communicated to a third party without the written permission of 4DSP Inc 4DSP 2008 HOS AD481 user manual Revision History Date Revision Version 02 09 07 09 07 First release 8 release Ea 11 08 Updated the document to reflect the latest state of the Fae ae RY TT HW p totus PO AD481 User manual november 2008 www 4dsp com AD481 user manual V1 1 Table of Contents 1 Acronyms and related documents cccceeseseeseeeeseseeneeseeseeeeneeeeneeoeeseseeneeeeaeeneneees 4 1 1 PTO OY FNS ce E E EEA 4 1 2 Related Documents ccccscccceeeeceeeceseeeeceececeusecsueeeceusecsueecsseeceusesseeeesueeessesessass 4 1 3 General AESCIIPtION ccccceeecccceeeeeceeeeeeceeeeeeaeeeeeeeeeeeeseaeeeseeeeesaeeeesaeeeeesaeeessaaeees 4 2 VST AN ATION scssi a venta mace vesuawonedescaneeedcenieueveceseece 6 2 1 Requirements and handling instructions ccceccceeeeeeeeeeeeeeeeeeeeseseeeeeueenseeseeenes 6 2 2 Firmware and SOPWANE ccccceececeeecceeeeceeeeceeeeeseeeseueeseeeeeaueeesaueesseeeeseeesaneensees 6 SN e EE E ce eewoaasence veces caeeeexessatacess 6 3 1 fg A 0 210 6 2S eee ee ce eee e
11. P101 By default the SMT381 analog input through a twisted pair balum transformer Transformer single ended It is possible to change this to DC coupled by taking out the transformer and installing some resistors on the board VCO1 UMC 600 System Clock for the DAC VCO Requires with air flow cooling in a system 1200MHz VCO setup U9 Fujitsu DAC DAC Requires heat sink with air flow system setup U31 Clock Synthesizer Test Clock for DAC The range of this than the operating range of the DAC 50 950MHz AD481 User manual november 2008 www 4dsp com 15 HOS AD481 user manual 3 7 DAC Clock tree The main clock source of the module is an UMC 600MHz to 1200MHz voltage controlled oscillator The frequency range of the VCO is adjustable with a frequency synthesizer The output of the VCO Synthesizer combination is passed through a Maxim high frequency comparator with an LVPECL output to form the main system clock In addition to this clock there is a clock synthesizer on the module that can generate a 50 to 950 MHz clock This clock is ideal for testing purposes Alternatively the user can provide the module with an external LVPECL clock Comperator max9601 Lmx2330 E VCO 1p 00Mhz Frequency 600 1200 2 Fpga_clkO Oscilator synthesizer MHz Divide by 8 amp 1 2 buffer FPga_clkt Clock synthesizer 16 00Mhz 50 950 MHz SY89430 Oscilator DAC clk Ext DAC clk out Figure
12. PGA A and B The maximum current rating given in the table below is the maximum current that can be drawn from each voltage rail in the case where resources are used to their maximum level Device Interface Voltage Maximum current rating DCI and memory reference 0 9V 5A voltage QDR2 DDR2 SDRAM core and 1 8V V O banks Virtex 4 devices I O banks 10A Virtex 4 device B I O bank 1 8V 2 5 3 3V 1 5A connected to the front panel daughter card Virtex 4 device A I O bank 3 3V 4A connected to the PCI bus Flash CPLD front Panel I O daughter card A D circuitry MGT power supply 1 2V 1 5V 2 5V 1 7A 0 5A 0 01A respectively Table 9 Power supply AD481 User manual november 2008 www 4dsp com 18 HOS AD481 user manual PMC XMC connectors 12V 12V 5V 3 3V E Low noise 2 5V regulator Switching 1 8V regulator Switching 1 2V regulator Switching 0 9V m7 regulator 12V 5V 3 3V 12V External Power connector Figure 11 Power supply An ADT7411 device is used to monitor the power on the different voltage rails as well as the temperature The ADT7411 data are constantly passed to the Virtex 4 device A Measurements can be accessed from the host computer via the PCI bus A software utility delivered with the board allows the monitoring of the voltage on the 2 5V 1 8V 1 2V and 0 9V rails It also displays the Virtex 4 device B junction temperature 4 1 External power connector for stand alone
13. cable a bitstream from a host computer via the JTAG connector The FPGA devices configuration can also be performed using the JTAG 3 2 2 1 DIP Switch A switch J1 is located next to the JTAG programming connector J6 see Figure 4 The switch positions are defined as follows AD481 User manual november 2008 www 4dsp com 10 AD481 user manual Figure 4 switch J1 location Default setting The Virtex 4 device A configuration is loaded from the flash at power up Virtex 4 device A safety configuration loaded from the flash at power up To be used only if the Virtex 4 device A cannot be configured or does not perform properly with the switch in the OFF position Sw2 Reservea a Reserved Reserved Table 3 Switch description 3 2 2 2 LED and board status Four LEDs connect to the CPLD and give information about the board status FPGA A or B bitstream or user_ROM_register is currently being written to the flash ON FPGA A not configured OFF FPGA A configured FPGA A or B bitstream or user_ROM_register is currently being written to the flash FPGA B not configured FPGA B configured The Virtex 4 device A has been configured with the safety configuration bitstream programmed in the flash at factory Please write a valid Virtex 4 device A bitstream to the flash Flash device is not busy CRC error Presumably a wrong or corrupted FPGA bitstream has been written to the flash Once on this LED remains on
14. e Do not install the AD481 while the motherboard is powered up 2 2 Firmware and software Drivers API libraries and a program example working in combination with a pre programmed firmware for both FPGAs are provided The AD481 is delivered with an interface to the Xilinx PCI core in the Virtex 4 device A and an example VHDL design in the Virtex 4 device B so users can start digitizing and performing data manipulation right out of the box For more information about software installation and FPGA firmware please refer the AD481 Get Started Guide and to the Programmer s guide available online 3 Design 3 1 FPGA devices The Virtex 4 FPGA devices interface to the various resources on the AD481 as shown on Figure 1 They also interconnect to each other via 86 general purpose pins and 2 clock pins 3 1 1 Virtex 4 device A 3 1 1 1 Virtex 4 device A family and package The Virtex 4 device A is from the Virtex 4 FX family It can be either an XC4VFX20 or XC4VFX6O0 in a Fineline Ball Grid array with 672 balls FF672 3 1 1 2 Power PC embedded processor Up to two IBM PowerPC RISC processor cores are available in the Virtex 4 device A This core can be used to execute C based algorithms and control the logic resources implemented in the FPGA 3 1 1 3 Virtex 4 device A external memory interfaces The Virtex 4 device A is connected to a 128Mbytes SDRAM bank with a 32 bit data bus width This memory resource can be used by the PowerPC core or
15. ee eee eee eee 6 3 1 1 Virtex 4 device cto sie eereeessapse dace g atest nes ice cass Gebiemense de deebSeaseeuerasatecucenteaeeeeniooe 6 3 1 2 NO CC B seasgan ee eee aac gamepad r E 9 3 2 FPGA devices COMMOUIATION sc vcnsnscsececaccensersnedodecncesincectewnnnd Ghedoeceesvannetaedodedeactesheebes 10 3 2 1 IAS SLO AS coear E EE E EE E E 10 3 2 2 OPED OVI CO eee en renee nee ee eee ee eee 10 3 2 3 UP eos sso E deena ee ET T E S E E AT 12 3 3 ROC I OO r otto pets eter 2s eeepc cee eec eels ems cece E 13 3 4 MIE TION YTS OUI CCS wa taconcsstsntsnassonen stettentseaunendonsantesanseh osuenostancqunnstesscsenananseaseatioseaa ies 13 3 4 1 DT SRAN errr EE e R EE scenes 13 3 4 2 DOR ORAND e EAE 13 3 5 DAC inputs and outputs main characteristics cceceeseeeeceeeeeeeeeeeeeeeseeeeseeesseees 14 3 6 DAG Connector OCAS eei a deat a aeiia 14 3 7 DAG OCK IEC eae a O E E E E EN 16 3 8 Front Panel optical transceivers c ccccsecssseceeeeceeeeseeeeeeeeceeeesueeseeeaeeeseeeeaeeeneeees 16 A WPOWOR FO CUI CIC N S sipsien N A 18 4 1 External power connector for stand alone mode ccceceeeeeeeeeeeeeeeeeeeeeeeeeeaeees 19 De SOT SIGS VOW A E EN scoot T N ON A 20 6 ENVIT ONMDMEN nae a E 20 6 1 pieier iti s eE E E E E 20 02 GONVECHON COOMO oases assesses etice E EE EEEa eNi 20 63 COnduUCON COGINIO ssriressirrrene aA ERE 20 E DIE i E O E r 20 9 EMO coionnan aE EASA EAE Ea 21 NY osc e E E sccenemaeneeemaeecmcstnecevewesatennd 21 AD481 U
16. ibility to efficiently implement multi clock domains algorithms and use the memory devices at different frequencies Both clock buffer devices CDM1804 and the frequency synthesizer I1CS8430 61 are controlled by the Virtex 4 device A 16MHzZ PCI PCIax Tel Low jitter 66 1 S3SMHz T E eae DDR A TOL ow jir T MGT clocks Virtex 4 f fr device B device A 106 25MHz LVPECL LVEMOS 31o HE CPLD synthesizer Virtex 4 Figure 7 Clock tree 3 4 Memory resources 3 4 1 QDR2 SRAM Four independent QDR2 SRAM devices are connected to the Virtex 4 device B The QDR2 SRAM devices available on the AD481 are 2M words deep 8Mbytes per memory device Please note that only three QDR SRAM devices are available to the user if the XC4VLX40 XC4VLX60 or XC4VSX55 FPGA device is mounted on board In this case the mounted banks are A 0 C 2 and D 3 3 4 2 DDR2 SDRAM Two 16 bit DDR2 SDRAM devices of 128MBytes each are connected to Virtex 4 device A The two memories share the same address and control bus and have their own data bus This memory resource can be accessed by the PowerPC processor in the Virtex 4 device A or can be used as a data buffer for custom user logic AD481 User manual november 2008 www 4dsp com 13 HOS 3 5 DAC inputs and outputs main characteristics Table 6 AD481 A D characteristics AD481 user manual Output current range Analogue outputs 20mA Data Format Analogue current
17. on cooling 600LFM minimum 6 3 Conduction cooling The AD481 can optionally be delivered as conduction cooled PMC The AD481 is compliant to ANSI VITA 20 2001 standard for conduction cooled PMC 7 Safety This module presents no hazard to the user AD481 User manual november 2008 www 4dsp com 20 HOS AD481 user manual 8 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system 9 Warranty Basic Warranty included 1 Year from Date of Shipment 90 Days from Date of Shipment Extended Warranty optional 2 Years from Date of Shipment l1 Year from Date of Shipment AD481 User manual november 2008 www 4dsp com 21
18. ser manual november 2008 www 4dsp com 3 45S n AD481 user manual 1 Acronyms and related documents 1 1 1 2 1 3 Acronyms ADC Analog to Digital Converter DAC Digital to Analog Converter DCI Digitally Controlled Impedance DDR___ Double Data Rate o Join Test Action Group PCB Printed Circuit Board QDR __ Quadruple Data rate Table 1 Glossary Related Documents IEEE Std 1386 1 2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC ANSI VITA 32 2003 Processor PMC ANSI VITA 39 2003 PCI X for PMC and Processor PMC IEEE Std 1386 2001 IEEE Standard for a Common Mezzanine Card CMC Family Xilinx Virtex 4 user guide Xilinx PCI X core datasheet Xilinx Virtex 4 Rocket I O guide General description AD481 User manual november 2008 www 4dsp com 4 HOS The AD481 is a high performance PMC module with two analogue outputs dedicated to digital signal processing applications with high bandwidth and complex algorithms requirements The AD481 can interface to a PCl express PCI X and or PCI bus In addition to two 1000MSPS DAC channels the AD481 offers fast on board memory resources and two Virtex 4 FPGAs Up to 4x 2 5Gbps optical transceivers for serial FPDP or gigabit Ethernet applications are available for communication with external systems The AD481 is mechanically and electrically compliant to the standard and specifications listed in section 1 2 of this document
19. to operate The power filtering network includes a 220nF decoupling capacitor and ferrite bead MP21608S221A per power pin The signal differential pairs are routed on a specific inner layer with one reference GND plane on each side of the layer stack up AD481 user manual The optical transceivers are an ideal communication link to transfer digitized and processed data to a remote system eg storage system by offering an aggregate bandwidth of 1 25GBytes s PMC edge Front Panel Power supply for MGT 1 2V 15V and 2 5V Low jitter MGT clocks Opikeal Virtex 4 Virtex t 125MHz Optical device Tranceiver device B PCl exprass Optical Tramceiver Optical Tranceiver Y h Figure 10 Optical transceivers AD481 User manual november 2008 www 4dsp com 17 HOS AD481 user manual 4 Power requirements The power is supplied to the AD481 via the PMC connectors Several DC DC converters generate the appropriate voltage rails for the different devices and interfaces present on board The AD481 power consumption depends mainly on the FPGA devices work load By using high efficiency power converters all care has been taken to ensure that power consumption will remain as low as possible for any given algorithm After power up the AD481 typically consumes 5W of power For precise power measurements it is recommended to use the Xilinx power estimation tools for both F
20. x 4 device B via the Virtex 4 device A Virtex 4 device B interface The LEDs are located on side 2 of the PCB in the front panel area D ad 5 25 3 FPGA LEDS Me eb E FPGA LED2 Sate Pe a wae FPGA LED Oto thers FPGA LEDO Figure 2 FPGA LED locations AD481 User manual november 2008 www 4dsp com 7 45S n AD481 user manual 3 1 1 6 Pn4 user I O connector The Pn4 connector is wired to the Virtex 4 device A The 32 lower bits are available only if an XC4VFX60 device is mounted on board The 32 higher bits are available only if PCI 32 bit is used and only if specified at the time of order All signals are user defined 3 3V LVTLL LVCMOS on rane fen _ an mame on a name pin pin name ee ee 5 Pngioa4 N7_ Na PQ 105 6 7 Pn4io6 No Pe Pamio 8 9 Pmios pio Pim Pm iog 10 11 Pn4toto po9 ng Paion 12 13 Pn io Re Pa Pra 013 14 15 Pn ioi4 Re R7 Pmi015 16 17 Pa ioie na m Pn4i017 18 19 Pn4i018 m20 m9 Pn i019 20 21 Pn4tozo Pi9 N19 Pn tat 22 23 Png to22 nia_ Miz Pn4i0o23 24 25 Pn41024 p16 Nie Pn4i0235 26 27 Pn4 i026 R18 P18 Pn4 1027 28 29 Pn4 1028 p21 P2o Pn4i029 30 31 Pn4io30 R17 Rie Pn4i031 32 33 Pn4io32 L9 m5 Pn4i033 34 35 Pn4 1034 15 AD11 Pn4 1035 36 37 Pn4 1036 AaD10 L4 Pn41037 38 39 Pn4 i038 13 AB11 Pn4 1039 40
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