Evaluation Board User Guide
Contents
1. ey 10593 026 Figure 26 Ground Plane Layer 2 Rev 0 Page 20 of 28 Figure 27 Power Plane Layer 3 Figure 28 Power Plane Layer 4 Rev 0 Page 21 of 28 10593 027 10593 028 Figure 30 Bottom Side Rev 0 Page 22 of 28 10593 029 10593 030 ORDERING INFORMATION BILL OF MATERIALS Table 1 AD9642 AD9634 AD6672 Bill of Materials Item Qty Reference Designator Description Manufacturer Part No 1 1 N A 2 13 C101 C103 C105 C109 to C113 C514 to C516 C520 C521 3 6 C107 C117 C118 C121 C122 C212 5 10 C204 C206 C207 C209 C225 C227 C228 C230 C241 C243 6 6 C210 C211 C220 C221 C223 C224 7 1 C213 8 2 C214 C216 9 1 C215 10 4 C217 C218 C226 C229 11 36 C231 C233 C235 C239 C301 C305 C306 C401 to C404 C501 C502 C504 to C507 C517 to C519 C535 to C548 C601 C604 12 3 C302 to C304 13 2 C503 C508 14 2 C509 C510 15 3 C511 to C513 16 3 C523 C532 C533 17 6 C524 to C527 C530 C534 18 1 C531 19 1 CR201 20 1 CR202 21 3 CR204 to CR206 22 2 CR501 CR502 23 1 CR503 24 13 E202 E204 E205 E207 to E214 E216 E217 25 2 E501 E502 26 1 F201 27 1 FL201 28 2 J301 J506 29 2 JP201 JP203 30 6 L501 to L506 31 1 L507 32 8 P104 to P110 P401 33 1 P201 34 1 P202 35 1 P203 6 C201 C232 C234 C236 C240 C405 Printed circuit board AD9642 engineering board 0 1 uF capaci2. WHWHLNHO OL ALNO STIN dadovid CINOHS S VNS L OAV I INOT NI Ig 2 IT z w o ag ING e o 6 6v 5 665 RI 6 Je Jz A stead ores sSuvHS 0 0 o 3010 000000 6S81 00 V8VWi vw Ina 3 0 90 SocA NIA nie T ZOEL coer de 90 2 TOEL 9 pie alor 16 0048 5 ANT O 3nl 0 o 6 L2 Sieg E N 2 OS RDA 1 a us S ING nd _ 8 2E B i D ING 5 ETEN 6 68 v THIS AAA AAA Je Jz SEES MSS S0 2 000000 6S1 00 V8VIl jon AA NIV x 6 6P 0 Sava 0 8 toer T LIEN HLVd WHAISSVd ES wo Po LOdNI 2O IVNV 1NO NI dWV Rev 0 Page 16 of 28 220 6901 WOA da 5O INNV Vd HAT LOY NI NI ING 5OTVNV AEdEt ze TNA 4010 HNOZT HNOZT 0 5 2 0 TONAN 14 EOT z Bs WITSUd 9 ING ZOvT ING 1092 90 8 sees HNZ8 INA SaNa 0 ING a vy 901 ae ING 4010 gj 99 TENS Oy WON d ees A 000000 6STL00 YaYW L aas L aas 4 5 ANTA OTHO 6079 Y ziyu IN 8050 aia 6 Ur
3. uo A S32 2050 6152 eso ofe 4nr o MOT AOT 1092 NIOXTO mir MS AUF 8 LISA AALINOYID MIO __ HIVd MOOTO HAILIOV ANTO 001 19 N ZIno ire Teg me 520 iS TESI LOST 0 1n0 XT 0252 Figure 23 Default and Optional Clock Input Circuits Rev 0 Page 18 of 28 FAST_SPI_EN DRVDD a 2 4 R603 1 1K So DNI a 0603 t I G73 xb 1 TP_DUT_SDIO ADG734BRUZ a LAE 5 0601 7 GT NC7WZ07P6X Yar 1 6 alx 3ja2 M x24 596 233 elu 35 2 DNI 229 2 TP SDIO LAYOUT PLACE V V 3 NOTE THIS SYMBOL 2 m 58 a 25 ni s z 615 DRVDD n 10K o T 55 Sr a SPI amp 8 TP_DUT_CSB L c604 DNI DNI E T 0 1UF TP DUT SCLK x 8 555 955 po m 2 9 m s 0602 med E V 11 1 6 T 3 a2 v2 4 4 4 olx GND als 225 Nc7WZ16P 6x7 S3s e 229 V LAYOUT ROUTE I ALL TRACE TYCO CONN ON TOP OF BOAR I H O H am P601 P601 AL b A2 B2 DNI a3 5 Ba TP605 ba Bl as Bs ad Bs Al 3 B7 AS amp
4. 0220 LZ 60Td z ZHWOOT 0 60 Es Q java 2 S Sue 2 1 ETS 44001 z100 otza o ie 7 1 35 3 3 LTZ 9124 TR Loza 240022 8 RUM gota soza X001 m sozu aanw iE Ed N z pe 5 S SNIHOLIMS orzo ZHWOOT zn 8 TWNOILdO z i 9 Y if ches 5 E dl VZS 41 d Qe er 560 5 1 9078 0 LH 8l ZqNV90LLddV HOZAN E a E S g 5 N a E 7 zHWOOT 8 8 2 de E 4 4 o 5 E TTA i toza goza 0 SZbE TES GZ Sl Sota M 5 SE 5 e 3 8S ele 5 5 5 N 5 P NEC E 3 E 5 S Ng E i TEST A T A f NIA 4 z T i Liza p MATT 1 5 LA 8 T ZCNYOSTAQY 202 Lozn LH E ZCNYOS Taw 3Kh S zozn ZHWOOT i E 2 07529812562 5 o 8 HOP E sn SR5STS 2 T 9 9 S E sole amp 9 elo 3 3 d ols gt v ae 5 41 1 I g AAM d am oh AT S S B 9 2 Y loz1 TVII9IQ Figure 20 Board Power Input and Supply Rev 0 Page 15 of 28 120 66501
5. priate part type should be listed in the status bar of the VisualAnalog New Canvas window Select the template that corresponds to the type of testing to be performed see Figure 4 where the AD9642 is shown as an example The AD9642 is given as an example in this user guide Similar settings are used for the AD9634 For the AD6672 the differences are noted where necessary in the steps that follow VisualAnalog New Canvas New Existing Recent Categories Templates AD9444 C AD9445 B C 09446 FFT C3 AD9447 AD9460 C 9461 58 C AD9467 27 27 AD9480 Samples Logic ADS484 C AD9601 C3 9609 C AD9626 AD9629 C AD9634 C AD9641 AD9642 T LJ Two Tone Average Two Tone AD9642 14 170 210 250 MSPS Single device found 10593 004 _ Figure 4 VisualAnalog New Canvas Window 2 After the template is selected a message appears asking if the default configuration can be used to program the FPGA see Figure 5 Click Yes and the window closes i VisualAnalog will now attempt to program the on board FPGA with a default file for AD9642 Please click Yes to program the FPGA If you prefer to use the current FPGA configuration click No Before clicking Yes please make sure t
6. Ch A FFT E 15M 30M 45M 60M 75M 90M 105M 120M Date 1 30 2012 Time 3 31 12 PM Sample Frequency 250 MHz Samples 16384 0 SNR 69 394 dB SNRFS 70 374 dB SINAD 69 29 dBc DC Frequency 0 MHz DC Power 43 789 dBFS 45 Fund Frequency 79 78 MHz Fund Power 0 98 dBFS Fund Bins 21 Harm 2 Power 88 523 dBc Ham 3 Power 89 725 dBc 30 Ham 4 Power 98 75 dBc Ham 5 Power 100 078 dBc Ham 6 Power 100 078 dBc Worst Other Frequency 15 82 MHz Worst Other Power 89 136 dBFS 45 Noise Hz 151 343 dBFS Hz Average Bin Noise 109 508 dBFS THD 85 528 dBc SFDR 88 156 dBc 50 75 2 90 3 4 5 TET Ji m dala M M x alld itl mm url mum AW me 1 15 Figure 15 Graph Window of VisualAnalog AD9642 Rev 0 Page 11 of 28 10593 014 10593 015 4 the AD6672 with NSR enabled certain options in the FFT Analysis box see Figure 16 in VisualAnalog to in VisualAnalog must be enabled Click the button circled bring up the options for setting the NSR E gt Visualanalog Canvas AD6672 Eile Edit View Canvas Tools Window Help 2 osar 5 Components E Board Interfaces 7798 ADC Data Capture Data Router Window Routine FFT Analysis FIFO4x Interface DEBUG ONLY int Window 5 3 308 Debug Graphics Process u Filter Process Ej M
7. FIFO4x Interface LL G DEBUG ONLY iB Debug Graphics Process i ie Fiter Process E Miscellaneous Comment 51 8 Models i48 ADC Model iii Generic Model Ej Processes f Aray Math Average 121 Bit Processor Bit Shifter Lue CCDF IW CFR i Complex Waveform Merger tI Complex Waveform Splitter Data Router offi DNL INL Analysis EVM FFT t FFT Analysis oof Hilbert Transform 55 Histogram ill Histogram Analysis 3 1vs Q 3 Input Formatter fA Inverse FFT cH Inverse Sine Z3 Output Formatter PAR iM Peak Hold AB Power Phase Resampler cx Resolution Formatter Scalar Math Stop cof Subset cola Vector Receiver Waveform Analysis Window Routine X DC Cor Zy X QEC E Python 42 Python Process 1 8 Results 5 Data Grid E Graph 10593 007 Setting Up the SPI Controller Software After the ADC data capture board setup is complete set up the SPI controller software using the following procedure 1 Open the SPI controller software by going to the Start menu or by double clicking the SPIController software desktop icon If prompted for a configuration file select the appropriate one If not check the title bar of the window to determine which configuration is loaded If necessary choose Cfg Open from the File menu and select the appropriate file based on your part type
8. EMT mount 78 L201 L202 2 2 uH inductor SM Toko FDV0630 2R2M 79 L301 L405 L406 82 nH inductor SM Murata LOW18AN82NGOOD 80 L401 to L404 120 nH inductor SM Panasonic ELJ RER12JF3 81 R204 R216 R218 R221 R305 R306 0 resistor film SMD 0402 Panasonic ERJ 2GEOROOX R308 to R312 R403 R406 R408 R409 R412 R508 R533 R534 R538 R541 R542 R608 82 R215 R220 TBD0603 do not install TBD_R0603 TBD0603 83 R301 R304 R520 R521 R529 R530 49 9 resistor PREC thick film chip R0402 Panasonic ERJ 2RKF49R9X 84 R410 R411 1 00 resistor PREC thick film chip R0402 Panasonic ERJ 2RKF1001X 85 R512 R633 R635 to R637 R643 to 100 resistor PREC thick film chip R0201 Panasonic ERJ 1GEF 1000C R646 86 R543 100 resistor film SMD 0402 Venkel CR0402 16W 1000FPT 87 627 629 10 resistor PREC thick film chip R0402 Panasonic ERJ 2RKF1002X 88 T301 T502 ADT1 1WT XFMR RF Mini Circuits ADT1 1WT 89 U603 Quad SPDT switches IC CMOS Analog Devices ADG734BRUZ 90 Y501 60 MHz to 800 MHz IC oscillator voltage Epson Toyocom TCO 2111 controlled OSC Do not install RELATED LINKS Resource Description AD6672 Product Page 11 Bit 250 MSPS 1 8 V IF Diversity Receiver AD9634 Product Page 12 bit 170 MSPS 210 MSPS 250 MSPS 1 8 V Analog to Digital Converter ADC AD9642 Product Page 14 Bit 170 MSPS 210 MSPS 250 MSPS 1 8 V Analog to Digital Converter ADC ADP2114 Product Page Configurable Dual 2 A Single 4 A Synchronous Step Down
9. FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS 100 00 EXPORT Customer agrees that it will not directly or indirectly export the Evaluation Board to another country and that it will comply with all applicable United States federal laws and regulations relating to exports GOVERNING LAW This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts excluding conflict of law rules Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County Massachusetts and Customer hereby submits to the personal jurisdiction and venue of such courts The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed 2012 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners UG10593 0 4 12 0 DEVICES www analo g com Rev 0 Page 28 of 28
10. Note that the CHIP ID 1 section should be filled to indicate whether the correct SPI controller configuration file is loaded see Figure 8 10593 008 Figure 8 SPI Controller CHIP ID 1 Section Rev 0 Page 7 of 28 2 Click the New DUT button in the SPIController window see Figure 9 Ta TODA ISTO Ne ak ti NEW DUT BUTTON E Figure 9 SPI Controller New DUT Button 3 Inthe ADCBase 0 tab of the SPIController window find the CLK DIV B section see Figure 11 If using the clock divider use the drop down box to select the correct clock divide ratio if necessary See the appropriate part data sheet the AN 878 Application Note High Speed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Speed ADCs via SPI for additional information Rev 0 Page 8 of 28 In the ADCBase 0 tab of the SPIController window find the OUTPUT DELAY 17 box Select the DCO Clk Delay Enable checkbox to enable this feature In the drop down box select 600 ps additional delay on DCO pin These settings align the output timing with the input timing on the capture FPGA Note that other settings can be changed on the ADCBase 0 tab see Figure 11 See the appropriate part data sheet the AN 878 Application Note High Speed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Speed ADCs via SPI for additional information on the available s
11. P602 respectively to the FPGA on the data capture board DEFAULT OPERATION AND JUMPER SELECTION SETTINGS This section explains the default and optional settings or modes allowed on the AD9642 AD9634 AD6672 evaluation board Power Circuitry Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P201 Analog Input The A and B channel inputs on the evaluation board are set up for a double balun coupled analog input with a 50 Q impedance This input network is optimized to support a wide frequency band See the AD9642 AD9634 and AD6672 data sheets for additional information on the recommended networks for different input frequency ranges The nominal input drive level is 10 dBm to achieve 2 V p p full scale into 50 At higher input frequencies slightly higher input drive levels are required due to losses in the front end network Optionally Channel A and Channel B inputs on the board can be configured to use the ADL5201 digitally controlled variable gain wide bandwidth amplifier The ADL5201 component is 2V p p 0 1 ene ene Oar 360 included on the evaluation board at 0401 However the path into and out of the ADL5201 can be configured in many different ways depending on the application therefore the parts in the input and output path are left unpopulated See the ADL5201 data sheet for additional information on t
12. 081 08 m AAA H E 315 atos 5 292 9055 EP LOO A 8 000000 661 00 ING TIT aeae m anro I ATO 000000 6STL00 vaw v vOST HOST 001 z A MEAT VS INTO 2 uu epsa oss ma GA fo ANTO 0 9 5i z L162 8162 Bi boues B 5 S osu oot 3 bs v Jz E wn TIS 2006 i I B 2292 sose INACE b ING ING I 1 z HAT 555 E 1 07100748 1 9 32012 Ag aT S H HlVd MOOTO XAIIOV SQVd LINOAVT OL 1 STIW OFS Ad GINOHS S WWS LNOAWT MOOTO HAISSVd 2 w A ezseay Han 8 d i ad a H amp A E 5 e 4 4 N 6100 6100 NI 6 81n0 t C C VA VV T Pe 4 8055 5 9058 gino 02A e a Q gt 5 2150 6 59 sae anLb 0 5 2 LI 35 ETS ETS n H ido 5 ag UM 2 1 NTNI79SO 4 4 NI 058 THIO 250 dO 1X3 Naama 8059 ES 2010 Twas e E aca 959 E Tra eaaa PAE 00027 5 3 vas osi z 3 ZHW008 09 I ic 0 1nO At 9 A d 3 05441 o X9 d9 UMN 088 2 ii 7 o 74570511915 THI1270X2A j WM an 20804 anl 0 amp
13. ANALOG DEVICES Evaluation Board User Guide UG 386 One Technology Way Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 Fax 781 461 3113 www analog com Evaluating the AD9642 AD9634 AD6672 Analog to Digital Converters FEATURES Full featured evaluation board for the AD9642 AD9634 AD6672 5 interface for setup and control External or AD9523 clocking option Balun transformer or amplifier input drive option LDO regulator power supply VisualAnalog and SPI controller software interfaces EQUIPMENT NEEDED Analog signal source and antialiasing filter Sample clock source if not using the on board oscillator 2 switching power supplies 6 0 V 2 5 A CUI EPS060250UH PHP SZ provided PC running Windows 98 2nd ed Windows 2000 Windows ME or Windows XP USB 2 0 port recommended USB 1 1 compatible AD9642 AD9634 or AD6672 evaluation board HSC ADC EVALCZ FPGA based data capture kit SOFTWARE NEEDED VisualAnalog SPI controller DOCUMENTS NEEDED AD9642 AD9634 or AD6672 data sheet HSC ADC EVALCZ data sheet AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual AN 878 Application Note High Speed ADC SPI Control Software AN 877 Application Note Interfacing to High Speed ADCs via SPI AN 835 Application Note Understanding ADC Testing and Evaluation GENERAL DESCRIPTION This user guide describes the AD9642 AD9634 and AD6672 evaluation b
14. ATOS ra Z ATO A y x pu 5 1 TIS SOTdL orota gt LNOAVT ALIINVOO L00AV T d e P EE 4 t T 40170 1 GOTO svigdIdW dli E x SNIMVHGQ AHL LSNIVOV HH OI SAJAN 4 1205 SIHI HO4 INIYdLOOd FHL Lad 11109059 vrE96Q0V ZV96QV Figure 19 Device Under Test and Related Circuits Rev 0 Page 14 of 28 5 8 ING 5 L T Ina anzz anzz i 09008L ozz ZHWOOT HDZ Z 4 z T Iza eo A es 61 8 2x 34001 q cates _ cogoaaz 1 e E erzo T 9129 6023 zug 340081 yoy gt Mosen 090451 2 um anzz anzz
15. Agreement This Agreement is made by and between you Customer and Analog Devices Inc ADI with its principal place of business at One Technology Way Norwood MA 02062 USA Subject to the terms and conditions of the Agreement ADI hereby grants to Customer a free limited personal temporary non exclusive non sublicensable non transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above and agrees not to use the Evaluation Board for any other purpose Furthermore the license granted is expressly made subject to the following additional limitations Customer shall not i rent lease display sell transfer assign sublicense or distribute the Evaluation Board and ii permit any Third Party to access the Evaluation Board As used herein the term Third Party includes any entity other than ADI Customer their employees affiliates and in house consultants The Evaluation Board is NOT sold to Customer all rights not expressly granted herein including ownership of the Evaluation Board are reserved by ADI CONFIDENTIALITY This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason Upon discontinuation of use of the Evaluation Board or termin
16. Analog Devices ADP1706ARDZ 1 8 R7 linear regulator 61 1 U206 ADP2114 IC dual configurable synchronous Analog Devices ADP2114 PWM step down regulator 62 1 U207 ADP150AUJZ 1 8 R7 IC CMOS linear Analog Devices ADP150AUJZ 1 8 R7 regulator LDO 1 8 V 63 2 U300 U602 NC7WZ16P6X IC tiny logic UHS dual buffer Fairchild NC7WZ16P6X 64 1 U401 ADL5562 IC 2 6 GHZ ultralow distortion Analog Devices ADL5562 DIFF IF RF amp 65 1 U601 NC7WZO7P6X IC tiny logic UHS dual buffer Fairchild NC7WZ07P6X 66 1 C602 0 1 uF capacitor ceramic X7R 0402 Murata GRM155R71C104KA88D 67 1 CR203 LNJ314G8TRA green LED green surface Panasonic LNJ314G8TRA mount 68 1 R502 1 resistor ultraprecision ultrareliability SUSUMU RG1005P 102 B T5 MF chip 69 2 R539 R540 33 O resistor high PRES high stability Yageo RT0402DRE0733RL 70 1 U501 AD9523 IC Analog Devices AD9523 71 C205 C208 C242 0 01 pF capacitor ceramic X7R 0402 Murata GRM155R71H103KA01D 72 C219 C222 TBD0603 do not install TBD_C0603 TBD0603 Rev 0 Page 24 of 28 Item Qty Reference Designator Description Manufacturer Part No 73 C314 C406 to C408 C529 C603 0 1 uF capacitor ceramic X7R 0402 Murata GRM155R71C104KA88D 74 6409 C410 5 pF capacitor Panasonic ECU E1HO50CCQ 75 C522 390 pF capacitor ceramic COG 0402 Murata GRM1555C1H391JA01D 76 E203 E206 100 MHZ inductor ferrite bead Panasonic EXC ML20A390U 77 J302 J502 J503 J505 SMA J P X ST EM1 CONN PCB SMA ST edge Samtec SMA J P X ST
17. Bo 10 B10 P601 P601 Sis os cil bi m C2 2 cg amp 8 cd 7 3 3 D7 ca fla bs c9 bo 10 b10 P601 P601 BG2 2 Bc3 amp BGA Q 5 8 H 565 Bes 2 5 BGs amp pes BGO bao BG10 6469169 1 D2 D3 pe D7 10 11 D4 D5 12 1 9 3P3V DIGITAL R608 KP VbDIO t MM DNI 0 9602 C602 NEAR DUT 0 1UF V DNI IS DRAWN GIVEN INPUT 1 LOGIC FPGA CONN 0603 DNI D PINS R E MOVE R633 Dco P602 P602 100 pur Bi nco DO D1 R643 B2 a3 B 1 E3 100 pur ae Aj 8 Ba pen 2 03 R635 02 03 A5 B Bs Di0 D11 100 pur Ad o 86 5 R644 D4 D5 3 S B A8 m B8 100 AY B9 D6 D7 R636 D6 D7 10 B10 100 pur P602 P602 D8 D9 R645 m 100 EE DNI a Q 8 T m D10 D11 R637 p10 p11 eg 100 pur a da D12 D13 R646 D12 D 100 pur P602 P602 BGI 4 a E E I5 mom o o 2 2 a d amp Figure 24 SPI Configuration Circuit and FIFO Board Connector Circuit Rev 0 Page 19 of 28 ADG734BRUZ C603 0 1UF DNI 10593 024
18. DC to DC Regulator AD9523 Product Page 14 Output Low Jitter Clock generator ADG734 Product Page CMOS 2 5 O Low Voltage Quad SPDT Switch AN 878 Application Note High Speed ADC SPI Control Software AN 877 Application Note Interfacing to High Speed ADCs via SPI AN 835 Application Note Understanding High Speed ADC Testing and Evaluation AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual Rev 0 Page 25 of 28 NOTES Rev 0 Page 26 of 28 NOTES Rev 0 Page 27 of 28 NOTES ESD Caution ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Legal Terms and Conditions By using the evaluation board discussed herein together with any tools components documentation or support materials the Evaluation Board you are agreeing to be bound by the terms and conditions set forth below Agreement unless you have purchased the Evaluation Board in which case the Analog Devices Standard Terms and Conditions of Sale shall govern Do not use the Evaluation Board until you have read and agreed to the Agreement Your use of the Evaluation Board shall signify your acceptance of the
19. F3 45 1 R214 10 5 resistor precision thick film chip Panasonic ERJ 2RKF1052X R0402 46 14 R217 R219 R302 R303 R307 R319 0 resistor film SMD 0402 Panasonic ERJ 2GEOROOX R320 R404 R405 R506 R522 R523 R528 R537 47 2 R313 R314 36 resistor film SMD 0402 Panasonic ERJ 2GEJ360X 48 2 R315 R316 15 resistor film SMD 0402 Panasonic ERJ 2RFK15ROX 49 6 R317 R318 R501 R503 R505 R604 49 9 resistor precision thick film chip Panasonic ERJ 2RKF49R9X R0402 50 2 R401 R402 40 2 resistor precision thick film chip Panasonic ERJ 2RKF40R2X R0402 51 4 R407 R603 R605 R626 1 1 resistor film SMD 0402 Panasonic ERJ 2GEJ112X 52 1 R507 TBD0402 do not install TBD_R0402 TBD0402 53 10 R509 R515 to R519 R601 R609 10 kQ resistor precision thick film chip Panasonic ERJ 2RKF1002X R610 R615 R0402 54 13 R510 R511 R524 to R527 R531 100 Q resistor precision thick film chip Panasonic ERJ 1GEF1000C R532 R535 R536 R544 to R546 R0201 55 2 R513 R514 200 resistor precision thick film chip Panasonic ERJ 2RKF2000X R0402 56 4 R606 R613 R616 R628 0 resistor thick film chip Multicomp 0402WGF0000TCE 57 5 T302 T303 T401 T501 T503 MABA 007159 000000 XFMR RF 1 1 MACOM MABA 007159 000000 58 1 U1010 SG MLF32A 7004 socket 32P MLF direct Ironwood Electronics SG MLF32A 7004 mount 59 2 U202 U203 ADP150AUJZ 3 3 R7 IC CMOS linear Analog Devices ADP150AUJZ 3 3 R7 regulator LDO 3 3 V 60 2 U204 U205 ADP1706ARDZ 1 8 R7 IC low dropout CMOS
20. NOA INIA HNZ8 300 0 LA kel ANA ZaIA 1 z Ob ous IJa Sort ING ING 40770 TOPA HNOZT HNOZI topa T S FINO JOT O 90 2 ANOT N ANT 0 copy TO O 3 lOWHHOO FOVId lt JOVTd JUU SOTH ASHHL e0570 d Figure 22 Optional Active Input Circuits Rev 0 Page 17 of 28 8 A A S z 8 530 A Sens bold NIONTO T ede 9 9 inowio n T w ope 5 in zo o 2 So T I LS ATE S ose 2082 E j E b Je Jz 8 goer gosi aaoec 2406 et amp ets et amp 55509 t ING 1
21. after Run see Figure 13 is clicked do the following Make sure that the evaluation board is securely connected to the HSC ADC EVALCZ board Make sure that the FPGA has been programmed by verifying that the DONE LED is illuminated on the HSC ADC EVALCZ board If this LED is not illuminated make sure that the U4 switch on the board is in the correct position for USB CONFIG Make sure that the correct FPGA program was installed by clicking the Settings button in the ADC Data Capture block in VisualAnalog Then select the FPGA tab and verify that the proper FPGA bin file is selected for the part If VisualAnalog indicates that the data capture timed out do the following Make sure that all power and USB connections are secure Probe the DCO signal at the ADC on the evaluation board and confirm that a clock signal is present at the ADC sampling rate EVALUATION BOARD SCHEMATICS AND ARTWORK e l i SB RBRBAARE ANTO ANTO ANTO ANTO 0 L BEPRR REE BTID ees ETTO OTTO 60TO nn NId ING LV ant QGAV A A vOOL W2EaIN OS o o ps ols o A T vOTdL L T GGAHd EL 8 daaua 4 cordi zotai Wet etl NEL ES 9 td zd 05T 02 5 ANT ANTO ANT O ANT 00d IZ rd o0d TETO 0I2 TOTO LOTO ords ind Zz
22. ation of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board including but not limited to soldering or any other activity that affects the material content of the Evaluation Board Modifications to the Evaluation Board must comply with applicable law including but not limited to the RoHS Directive TERMINATION ADI may terminate this Agreement at any time upon giving written notice to Customer Customer agrees to return to ADI the Evaluation Board at that time LIMITATION OF LIABILITY THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED AS IS AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS ENDORSEMENTS GUARANTEES OR WARRANTIES EXPRESS OR IMPLIED RELATED TO THE EVALUATION BOARD INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY TITLE FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER S POSSESSION OR USE OF THE EVALUATION BOARD INCLUDING BUT NOT LIMITED TO LOST PROFITS DELAY COSTS LABOR COSTS OR LOSS OF GOODWILL ADI S TOTAL LIABILITY
23. ettings 2 5 103635 TAB 20 03 250450 Ser 10593 009 bw ISIM D SUN Tw DedieADC Dig Oupa 7 PN Long Gen PH Short Gen punes pariaicw roast est Ure Mode p y Brey Mode i mme C2 Comment up Teu Moda ir OW Comer PATE Oe M iseen OO Maig DIST heks n seset Ds x AE wc wisis TAUTA ce f Pot OCO Ch Imt Quer tiptoe Mode Un Cheval A 5 ee 79 DCO Ch Delay CD Ck Dl 10593 010 Figure 10 SPI Controller Example ADCBase 0 Tab Evaluation Board User Guide Contin ous Output Mode 0 Off Normal Operation MSB 00000000 00 4 3 2012 9 56 42 AM 10593 011 Figure 11 SPI Controller CLK DIV B Section Rev 0 Page 9 of 28 Evaluation Board User Guide Figure 12 SPI Controller Example ADCBase 0 Tab NSR Settings for the AD6672 10593 012 5 Ifusing the noise shaping requantizer NSR feature of the 6 Clickthe Run button in the VisualAnalog toolbar see AD6672 the settings in the ADCBase 0 tab must be Figure 13 changed see Figure 12 The NSR Enable checkbox must be selected under the NOISE SHAPED REQUANTIZER Seen Muere eus Ee oL 1 3C section This enab
24. he HSC ADC EVALC is powered with the correct supply and that the board is connected to the computer Also make sure the dipswitch U4 on the HSC ADC EVALC is set to the following configuration MO0 ON M1 OFF M2 OFF If the configuration is successful you will see the DONE light Do not show this message again Ye te 10593 005 e 1 Figure 5 VisualAnalog Default Configuration Message To change features to settings other than the default settings click the Expand Display button located on the bottom right corner of the window see Figure 6 to see what is shown in Figure 7 Detailed instructions for changing the features and capture settings can be found in the AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual After the changes are made to the capture settings click the Collapse Display button VisualAnalog 09642 A F gt isualAnalog Canvas fe File Edit View Canvas Tools Window amp x E 092 Average FFT Res dy EXPAND DISPLAY BUTTON Rev 0 Page 6 of 28 Figure 6 VisualAnalog Window Toolbar Collapsed Display gt VisualAnalog Canvas AD9642 Average FFT REEL eee X File Edit View Canvas Tools Window Help ub E Components x E Board Interfaces ADC Data Capture ADC Data Capire Window Routine
25. his part and for configuring the inputs and outputs The ADL5201 by default is held in power down mode but can be enabled by adding 1 resistors at RA27 and R428 to enable Channel A and Channel B respectively Clock Circuitry The default clock input circuit that is populated on the AD9642 AD9634 AD6672 evaluation board uses a simple transformer coupled circuit with a high bandwidth 1 1 impedance ratio transformer T503 that adds a very low amount of jitter to the clock path The clock input is 50 terminated and ac coupled to handle single ended sine wave types of inputs The trans former converts the single ended input to a differential signal that is clipped by CR503 before entering the ADC clock inputs The board is set by default to use an external clock generator An external clock source capable of driving a 50 terminated input should be connected to J506 A differential LVPECL clock driver output can also be used to clock the ADC input using the AD9523 U501 To place the AD9523 into the clock path populate R541 and R542 with 0 O resistors and remove C532 and C533 to disconnect the default clock path inputs In addition populate R533 and R534 with 0 resistors remove R522 and R523 to disconnect the default clock path outputs and insert AD9523 LVPECL Output 2 The AD9523 must be configured through the SPI controller software to set up the PLL and other operation modes Consult the AD9523 data sheet for more infor
26. iscellaneous Comment Models e FFT 1 30 2012 3 41 30 PM M ADC Model Generic Model E Processes 2 Math Average 5 45M 60M 75M 30M 105M 120M 121 Bit Processor Bit Shifter Pur CCDF N X Complex Waveform Merger 1 Complex Waveform Splitter Data Router 6 DNL INL Analysis EVM FFT iM FFT Analysis W Hilbert Transform LJ Histogram Histogram Analysis Ivs Q 4x Input Formatter TA Inverse FFT H Inverse Sinc 3 Logic Analysis 0 Mixer 13 Output Formatter PAR Peak Hold 984 Power Phase Resampler X Resolution Formatter 9 Scalar Math Stop i gt Subset Tia Vector Receiver Waveform Analysis a Window Routine 9 X DC Cor Python 5 Python Process gt Results zz Data FE Graph m 10593 016 Ready Figure 16 VisualAnalog Main Window Showing FFT Analysis for AD6672 Rev 0 Page 12 of 28 5 Configure the settings in the FFT analysis to match the settings selected for the NSR in the SPI controller see Figure 17 FFT Analysis Settings mS User Delined Preset Analyses See Tore Anaya Advanced Calculations Standard Measurements Average Din Nowe ex Figure 17 VisualAnalog FFT Ana
27. les the circuitry in the AD6672 To select the bandwidth mode use the NSR Mode drop y AD9642 Average FFT down box in the NOISE SHAPED REQUANTIZER 1 3C section Upon selecting the bandwidth mode select the desired tuning word in the NSR Tuning drop down menu Figure 13 Run Button Encircled in Red in VisualAnalog Toolbar 10593 013 under the NOISE SHAPED REQUANTIZER TUNING 3E Collapsed Display section Rev 0 Page 10 of 28 Adjusting the Amplitude of the Input Signal 250 5 5 90 1MHz 1dBFS The next step is to adjust the amplitude of the input signal for 20 SNR 714 724 each channel as follows EE 40 1 Adjust the amplitude of the input signal so that the fundamen tal is at the desired level Examine the Fund Power reading S 60 THIRD HARMONIC in the left panel of the VisualAnalog Graph window See 8 Ei E SECOND HARMONIC gure 15 d 2 Repeat this procedure for Channel B if desired E 3 Click the Save disk icon within the Graph window to save E URP the performance plot data as a csv formatted file See dh Figure 14 for an example aud ada ad d LU 0 25 50 75 100 125 FREQUENCY MHz Figure 14 Typical FFT AD9642 gt Graph AD9642 Average FFT 1 30 2012 33 12 TTE mM EXE e File Eus ela Fr
28. lysis Settings for AD6672 6 The result should show an FFT plot that looks similar to Figure 18 Figure 18 Graph Window of VisualAnalog NSR Enabled AD6672 7 The amplitude shows approximately 0 6 dB lower than when the NSR is disabled The NSR circuitry introduces this loss An amplitude of 1 6 dBFS with NSR enabled is analogous to an amplitude of 1 0 dBFS with NSR disabled 8 Repeat Step 3 to save the graph in a csv file format Rev 0 Page 13 of 28 10593 017 10593 018 Troubleshooting Tips If the FFT plot appears abnormal do the following If you see a normal noise floor when you disconnect the signal generator from the analog input be sure that you are not overdriving the ADC Reduce the input level if necessary In VisualAnalog click the Settings button in the Input Formatter block see Figure 7 Check that Number Format in the settings of the Input Formatter block is set to the correct encoding offset binary by default Repeat for the other channel If the FFT appears normal but the performance is poor check the following Make sure that an appropriate filter is used on the analog input Make sure that the signal generators for the clock and the analog input are clean low phase noise Change the analog input frequency slightly if noncoherent sampling is being used Make sure that the SPI configuration file matches the product being evaluated If the FFT window remains blank
29. mation about these and other options PDWN To enable the power down feature Bits 1 0 of Register 0x08 must be written for the desired power down mode OEB To disable the digital output pins and place them in a high imped ance state Bit 4 of Register Ox14 must be written AD9642 AD9634 AD6672 VCM Q VIN o_O 3 9pF 10593 003 Y Figure 3 Default Analog Input Configuration of the AD9642 AD9634 AD6672 Rev 0 Page 4 of 28 Switching Power Supply Optionally the ADC on the board can be configured to use the ADP2114 dual switching power supply to provide power to the DRVDD and AVDD rails of the ADC To configure the board to operate from the ADP2114 the following changes must be incorporated see the Evaluation Board Schematics and Artwork and the Bill of Materials sections for specific recommendations for part values 1 Install R204 and R221 to enable the ADP2114 2 Install R216 and R218 3 Install L201 and L202 Remove JP201 and JP203 5 Remove jumpers from across Pin 1 and Pin 2 on P107 and P108 respectively 6 Place jumpers across Pin 1 and Pin 2 of P106 and P109 respectively Making these changes enables the switching converter to power the ADC Using the switching converter as the ADC power source is more efficient than using the default LDOs Rev 0 Page 5 of 28 EVALUATION BOARD SOFTWARE QUICK START PROCEDURES This section provides quick start procedures for usi
30. ng the AD9642 AD9634 AD6672 evaluation board Both the default and optional settings are described CONFIGURING THE BOARD Before using the software for testing configure the evaluation board as follows 1 Connect the evaluation board to the data capture board as shown in Figure 1 and Figure 2 Connect one 6 V 2 5 A switching power supply such as the CUI Inc EPS060250UH PHP SZ that is supplied to the AD9642 AD9634 AD6672 board Connect another 6 V 2 5 A switching power supply such as the CUI EPS060250UH PHP SZ that is supplied to the HSC ADC EVALCZ board Connect the HSC ADC EVALCZ board J6 to the PC with a USB cable On the ADC evaluation board confirm that jumpers are installed on the P105 P108 P104 P107 and P110 headers Connect a low jitter sample clock to Connector J506 Use a clean signal generator with low phase noise to provide an input signal to the desired channel s at Connector J301 Channel A and or Connector J303 Channel B Use a 1 m shielded RG 58 50 coaxial cable to connect the signal generator For best results use a narrow band band pass filter with 50 terminations and an appropriate center frequency Analog Devices uses TTE Allen Avionics and K amp L band pass filters USING THE SOFTWARE FOR TESTING Setting Up the ADC Data Capture After configuring the board set up the ADC data capture using the following steps 1 Open VisualAnalog on the connected PC The appro
31. oard which provides all of the support circuitry required to operate the AD9642 AD9634 and AD6672 in their various modes and configurations The application software used to interface with the devices is also described The AD9642 AD9634 and AD6672 data sheets provide additional information and should be consulted when using the evaluation board All documents and software tools are available at http www analog com fifo For additional information or questions send an email to highspeed converters analog com TYPICAL MEASUREMENT SETUP 10593 001 Figure 1 AD9642 AD9634 or AD6672 Evaluation Board on Left and HSC ADC EVALCZ Data Capture Board on Right PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS Rev 0 Page 1 of 28 TABLE OF CONTENTS Fedtur ss M Equipment Needed e dne netta eR Software Needed eere eimi entes Documents Needed ssepe n General Description a IERI eet Typical Measurement Setup seen Revision History ee Evaluation Board Hardware eere Power Suppliesu Input ur ait REVISION HISTORY 4 12 Revision 0 Initial Version Output Signals ERU 4 Default Operation and Jumper Selection Settings 4 Evaluation Board Software Quick Start Procedures 6 Configuring the Board sse 6 U
32. outlet at 47 Hz to 63 Hz The output from the supply is provided through a 2 1 mm inner diameter jack that connects to the printed circuit board PCB at P201 The 6 V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators default configuration that supply the proper bias to each of the various sections on the board WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz SWITCHING POWER SUPPLY SWITCHING POWER SUPPLY SIGNAL SYNTHESIZER OPTIONAL CLOCK SOURCE Figure 2 Evaluation Board Connection The evaluation board can be powered in a nondefault condition using external bench power supplies To do this remove the jumpers on the P104 P107 P108 and P105 header pins to disconnect the outputs from the on board LDOs This enables the user to bias each section of the board individually Use P202 and P203 to connect a different supply for each section A 1 8 V supply is needed with a 1 A current capability for DUT_AVDD and DRVDD however it is recommended that separate supplies be used for both analog and digital domains An additional supply is also required to supply 1 8 V for digital support circuitry on the board DVDD This should also have a 1 A current capability and can be combined with DRVDD with little or no degradation in performance To operate the evaluation board using the SPI and alternate clock options a separate 3 3 V analog supply is needed in addition to the other supplie
33. s This 3 3 V supply or 3P3V_ANALOG should have a 1 A current capability This 3 3 V supply is also used to support the optional input path amplifier ADL5201 on Channel A and Channel B INPUT SIGNALS When connecting the clock and analog source use clean signal generators with low phase noise such as the Rohde amp Schwarz SMA or HP 8644B signal generators or an equivalent Use a 1 m shielded RG 58 50 coaxial cable for connecting to the evalua tion board Enter the desired frequency and amplitude see the Specifications section in the data sheet of the respective part 6V DC 2 5A MAX PC RUNNING ADC ANALYZER OR VISUAL ANALOG USER SOFTWARE 10593 002 Rev 0 Page 3 of 28 When connecting the analog input source use of a multipole narrow band band pass filter with 50 terminations is recom mended Analog Devices Inc uses TTE and K amp L Microwave Inc band pass filters The filters should be connected directly to the evaluation board If an external clock source is used it should also be supplied with a clean signal generator as previously specified Typically most Analog Devices evaluation boards can accept 2 8 V p p or 13 dBm sine wave input for the clock OUTPUT SIGNALS The default setup uses the Analog Devices high speed converter evaluation platform HSC ADC EVALCZ for data capture The output signals from Channel A and Channel B for the AD9642 AD9634 and AD6672 are routed through P601 and
34. sing the Software for Testing sse 6 Evaluation Board Schematics and Artwork 14 Ordering 23 Bill Of Materials cs orte 23 Related Einks ioci EROR DER RN ORE 25 Rev 0 Page 2 of 28 EVALUATION BOARD HARDWARE The AD9642 AD9634 and AD6672 evaluation board provides all of the support circuitry required to operate these parts in their various modes and configurations Figure 2 shows the typical bench characterization setup used to evaluate the ac performance of the AD9642 AD9634 or AD6672 It is critical that the signal sources used for the analog input and the clock have very low phase noise lt 1 ps rms jitter to realize the opti mum performance of the signal chain Proper filtering of the analog input signal to remove harmonics and lower the inte grated or broadband noise at the input is necessary to achieve the specified noise performance See the Evaluation Board Software Quick Start Procedures section to get started and see Figure 19 to Figure 30 for the complete schematics and layout diagrams These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters POWER SUPPLIES This evaluation board comes with a wall mountable switching power supply that provides a 6 V 2 5 A maximum output Connect the supply to a rated 100 V ac to 240 V ac wall
35. ta GRM155R71H103KA01D Murata GRM155R71C104KA88D Murata GRM1555C1H3R9CZO1D Murata GRM155R61A334KE15D Murata GRM155R71H102KA01D Murata GCM188R71C474KA55D Murata GRM1555C1H391JA01D Murata GRM21BR61C106KE15L Murata GRM1555C1H120JZ01D Diode Incorp S1AB 13 MCC SK33A TP MICRO Commercial Components CORP S2A TP Panasonic LNJ314G8TRA Avago HSMS 2812BLK Panasonic EXC ML20A390U Panasonic EXCCL3225U1 TYCO Electronics NANOSMDC110F 2 Murata BNX016 01 Samtec SMA J P X ST EM1 Panasonic ERJ 6GEYJO O Coil Craft ME3220 102MLB Murata LQG15HN3N9S02D Samtec TSW 102 08 G S CUI Stack PJ 202A Wieland 5 531 3625 0 Wieland Z5 531 3425 0 Rev 0 Page 23 of 28 Item Qty Reference Designator Description Manufacturer Part No 36 2 P601 P602 6469169 1 CONN 60 RA connector TYCO 6469169 1 37 1 R201 261 resistor film chip thick NIC COMP CORP NRCO6F2610TRF 38 2 R205 R222 1 00 resistor precision thick film chip Panasonic ERJ 2RKF1001X R0402 39 1 R206 10 O resistor precision thick film chip 402 Panasonic ERJ 2RKF10ROX 40 5 R207 R208 R602 R611 R612 100 resistor precision thick film chip Panasonic ERJ 2RKF1003X R0402 41 1 R209 27 resistor chip SMD 0402 Panasonic ERJ 2RKF2702X 42 1 R210 4 64 Q resistor precision thick film chip Panasonic ERJ 2RKF4641X R0402 43 2 R211 R212 15 kQ resistor chip SMD 0402 Panasonic ERJ 2RKF1502X 44 1 R213 13 resistor film SMD 0402 Yageo 9C04021A1302FLH
36. tor ceramic X5R 0201 1 uF capacitor mono ceramic 0402 10 capacitor tantalum 4 7 uF capacitor monolithic ceramic X5R 22 capacitor ceramic chip 2200 pF capacitor ceramic X7R 0402 100 pF capacitor chip mono ceramic COG 0402 1500 pF capacitor ceramic X7R 0402 0 01 pF capacitor ceramic X7R 0402 0 1 pF capacitor ceramic X7R 0402 3 9 pF capacitor ceramic NPO 0402 0 33 pF capacitor ceramic X5R 0 001 uF capacitor ceramic monolithic 0 47 pF capacitor chip CER X7R 0603 390 pF capacitor ceramic COG 0402 10 capacitor ceramic monolithic 12 pF capacitor ceramic COG 0402 S1AB 13 diode rectifier GPP SMD SK33A TP diode Schottky 3 amp rectifier S2A TP diode recovery rectifier LNJ314G8TRA green LED green surface mount HSMS 2812BLK diode Schottky dual series 100 MHZ inductor ferrite bead 45 chip bead core 1 1 A fuse poly switch PTC device 1812 BNX016 01 FLTR noise suppression LC combined type SMA J P X ST EM1 CONN PCB SMA ST edge mount OQ resistor JMPR SMD 0805 SHRT 1 uH inductor SMT power 3 9 nH inductor SM TSW 102 08 G S CONN PCB header 2 POS PJ 202A CONN PCB DC power jack SM Z5 531 3625 0 CONN PCB header 6 position 25 531 3425 0 CONN PCB pluggable header AD9642EE01A Murata GRMO33R60J104KE19D Murata GRM155R60J105KE19D AVX TAJA106K010RNJ Murata GRM188R60J475KE19 Murata GRM21BR60J226ME39L Phycomp YAGEO CC0402KRX7R9BB222 Murata GRM1555C1H101JD01D Murata GRM155R71H152KA01D Mura
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