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1. 14 SIGNALA 2 SIGNALB 55 SIGNALn1 Implicit assignment pins SIGNALA nodes SIGNALAI SIGNALB SIGNALB1 SIGNALn SIGNALn1 External pin signals Internal node signals 4 18 Flash PLD memm ees 1S PLD 5 Bit Counter Example Design This design example illustrates implementing a 5 bit counter with a state machine into the ATV750 PLCC de vice Change to the TUTOR design Use the Design Management Tools to change to the TU TOR design Display the Programmable Logic tools screen Adjust the Tool Set Configuration 1 Set Compile Source and Configure PLD Tools The Configure PLD screen appears 2 Pan down to the Processing Options Select Create er ror message file with line and column numbers 3 Pan back up to the top select OK to save the change Capture the design 1 The source OHDL for the counter is shown in the Figure 3 5COUNT PLD OHDL Sample Use the Edit File editor to key in the source file Select Edit File and Execute Type in 5COUNT PLD as the File to Edit Select OK Type in the source file Save the file Exit the text editor Note to save time you only have to key in source lines that begin with a vertical bar p any other line is regarded as a comment by the logic compiler Compile the Design 1 Select Compile Source Local Configuration and Con figure LOGIC The Configure Compile Source screen displays 2 In the File area select 5CO2. i JEDEC DOC Fusemap r 1 i Documentation High Performance Flash PLD OrCAD Support 0718A 4 17 AIMEL PLD 386 with Atmel ABEL Software Continued Related documents Atmel SmartPart ATMEL 750 2500 Device Fitter Intelligent Device Fitting Software User Manual DATA VO Programmable Logic Design Tools Language Guide Programmable Logic Design Tools 386 User s Guide ATF1500 CPLD Device Fitter Manual Setting up Atmel ABEL This section describes the Atmel ABEL software system requirements that should be satisfied before running the Fit Logic processor These notes reflect the installation and setup information described in Atmel s ATMEL ABEL De sign Software Installation Guide document Note To generate a JEDEC file for an Atmel PLD family device with PLD 386 requires a complete installation of the Atmel ABEL Device Fitter 1 The following environment variables must be set The following lines should be added to the AUTO EXEC BAT SET ABEL4DEV path ib4 SET ABEL5DEV path lib5 where path is the subdirectory preceding the Atmel ABEL environment 2 The Atmel software node must be added to the PATH of the AUTOEXEC BAT An example path is shown below PATH C DOS C ORCADEXE C ATMEL 3 The CONFIG SYS should contain the following parameters files 20 buffers 20 shell c command com p e 102 4 Attach the DATA I O software security key to the parallel port Note The Atmel ABEL insta
3. G test log can be viewed by the Edit File editor Fit the Logic 1 Select Fit Logic Local Configuration and Configure FITLOGIC The Configure Fit Logic screen displays In the File area select 5COUNT PLA from the list box The Source entry box displays the name of the selected file The information message Target De vice ATV750c PLCC appears 2 Select OK to save the configuration 3 Select Fit Logic and Execute As it processes the de sign environment displays in full screen mode the activity of the Atmel ABEL software 4 The Programmable Logic Tools screen reappears when Fit Logic is complete The Open ABEL logic in terchange 5COUNT TT3 and reports about the fitter process 5COUNT TT3 and 5COUNT RPT can be viewed by the Edit File editor 5 Assemble the fuse map Run from the DOS command line fuseasm 5count 0 5count jed To append test vectors to the JEDEC file rerun Test Logic Expressing the logic as a schematic A similar process is used the capture the design in sche matics Use the Edit Schematic Logic editor to draft the logic and Convert Schematic Logic to Source to gener ate an OHDL source file 4 19 Figure 3 SCOUNT PLD OHDI Sample FILE 5COUNT PLD This test case was translated from the ABEL design file COUNT5 ABL NCLUDE FILES None ATV750C 16 Q2 Output signals 17 QO Pins Q1 CLOCK Input signals CLEAR OUTEN Title count to five counter Conditioning OUTEN D
4. UNT PLD from the list box The Source entry box displays the name of the se lected file 3 Select OK to save the configuration 4 Select Compile Source and Execute As it processes a view window appears near the bottom of the screen If any errors or warnings are encountered by the compiler the design environment will allow you to View Source View Output or ignore the messages OK If you View Source your text editor will appear with the 5COUNT PLD file If you are using the Stony Brook M2EDIT Text Editor the function key will display any syntax errors that may have been generated by the source file Edit and recompile until the logic compiler returns to the Programmable Logic Tools screen without errors or warn ings The logic interchange file 5COUNT PLA and a re port about the design compilation 5COUNT LST can be viewed by the Edit File editor AMEL Test the Logic 1 Select Test Logic Logic Configuration and Config ure VECTORS The Configure Test Logic screen displays 2 Inthe File area select 5COUNT PLD from the list box The Source entry box displays the name of the selected file 3 Select Initialize internal registers to Low 4 Select OK to save the configuration 5 Select Test Logic and Execute As it processes the design environment displays in full screen mode the activity of the logic tester 6 The Programmable Logic Tools screen reappears when Test Logic is complete The 5COUNT LO
5. ees lash PLD OrCAD Support for Atmel PLDs Atmel Device Support for OrCAD PLD 386 ATV750 ATV750B Device Family ATV2500 ATV2500B Device Family For ATF1500 support please contact Atmel PLD applications For 16V8 20V8 and 22V10 use the standard OrCAD PLD library OrCAD s Programmable Logic Design Tools 386 is used to create compile test and fit logic for programmable devices This application note describes how to use OrCAD PLD 386 to create an object file to program the Atmel PLD and CPLD de vices Overview OrCAD PLD 386 can be used in conjunction with Atmel ABEL Fitter software avail able from Atmel to create JEDEC files Figure 1 illustrates the programs that are involved PLD 386 with Atmel ABEL Software The OrCAD Hardware Description Language OHDL allows you to express your design using indexed boolean equations numerical maps state machines etc When used in conjunction with SDT 386 PLD 386 also allows you to design with schematics or a mix to schematics and OHDL Fit Logic with the Atmel ABEL Device Fitter translates your OHDL design into an Open ABEL tt2 logic interchange file The JEDEC writer FUSEASM creates a programming file continued Figure 1 Atmel OrCAD Interface CSchematic gt OHDL OrCAD Compile v Atmel ABEL Fitter Interface i y Fuseasm FIT LOG Fitter Report Fitter Log 5 f v i
6. ff Q 2 0 CLOCK Procedure Q 2 0 States s0 0 S1 Ly S2 2 3 3 S4 4 SO CLEAR gt sl If CLEAR then S1 else SO gt SO S1 CLEAR 62 If CLEAR then S2 else SO gt S0 S2 CLEAR gt 3 If CLEAR then S3 else SO gt SO S3 CLEAR gt S4 If CLEAR then S4 else SO gt SO S4 gt SO So gt 80 Decode illegal states S6 gt S0 S7 gt S0 Vectors d CLOCK c CLEAR OUTEN gt Q 2 0 OUTEN CLEAR CLOCK CLEAR CLOCK 10 0 1 tatunun 4 20 Flash PLD memm
7. llation software automatically implements the modifications to your AUTOEXEC BAT and CONFIG SYS files Figure 2 Implicit and Explicit Signal Assignment Example How to target an Atmel Device To generate the proper logic interchange file identify the device architecture in your OHDL source file If you are us ing the source composition technique the sample source lines below demonstrate how to target any device of the Atmel Device Family ATV750 DIP ATV750C PLCC ATV750B DIP ATV750BC PLCC ATV2500 DIP ATV2500C PLCC ATV2500B DIP ATV2500BC PLCC If you are using the schematic capture technique use the a PLACE Text command in Edit Schematic Logic then use one of the type keywords below Type ATV750 Type ATV750C Type ATV750B Type ATV750BC Type ATV2500 Type ATV2500C Type ATV2500B Type ATV2500BC How to assign signals You can assign signals explicitly in the design pld OHDL source file or allow them to float If a signal floats the At mel ABEL Device Fitter will assign the signal to a specific pins or nodes To identify floating signals to the logic compiler use the pins and nodes keywords The source lines in Figure 2 demonstrate how to assign signals to pins and nodes explicitly or allow them to float If you are using the schematic capture technique use the Get PINPAD or NODEPAD command in Edit Schematic Logic Explicit assignment
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