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Lab 3: Xilinx PicoBlaze Flow Lab

1. The following allows you to see the status of the source files being added to the project and allows you to specify the Design View association for sources which are successfully added to the project lem uclock low level definition all None Implementation Simulation LA Il m cmn 1 Click Open and then OK to add uclock vhd as a VHDL Design File to the project Select the top level design file uart clock vhd in the Sources in Project window Inthe Processes for Source window expand the Implement Design process expand Place amp Route expand Back Annotate Pin Locations and double click View Locked Pin Constraints The Project Navigator automatically determines which processes must be run and it will open the report once the Place amp Route process is completed Scroll down in the report and confirm that the pin numbers for the I O signals match the assignments you made You can also view the pin assignments by clicking on Pinout Report under Design Overview section of the Design Summary window Double click on Generate Programming File to generate bitstream file Error IBUF CLK Configure de FPGA Step 11 Configure and start a hyperterminal session Connect and power the board Generate the bitstream and configure the FPGA Verify operation of the real time UART clock in hardware Open a hyperterminal session by going to Start gt All Programs gt Accessories gt
2. Start of test architecture architecture Behavioral of uart clock is COMPONENT my dem PORT CLKIN IN IN std logic CLKFX OUT OUT std logic CLKO OUT OUT std logic LOCKED OUT OUT std logic END COMPONENT Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 18 MH 2 From the HDL Instantiation Template my dcm vhi copy the component instantiation begin at Inst my dcm my dcm until the end of the file and paste into uart clock vhd under begin of Architecture Inst my dem my dem PORT MAPI Cie Le ey CLKFX OUT gt CLKO OUT gt LOCKED OUT gt Complete the instantiation by filling in the port connections as follows Inst my dem my dem PORT MAP CLKIN IN gt clk CLKFX OUT gt c1KSSMHz CLKO OUT gt open LOCKED OUT gt lock Note The clkin_ibufg_out port is an output that is present to support designs that use the RocketIO transceivers Because the Spartan 3E device does not contain transceivers this port will be connected to a dummy signal Adda signal declaration for the 55 MHz output of the DCM under the comment Signals for DCM as follows sagnat ClKOOMEZ sed logic note the uart clock vhd design need to be updated so all design instances and processes are clocked using the clk55MHz signal Add an output pin for lock in the entity as follows entity uart clock is Port tx out std logic rx in std_logic alarm out std_logic clk in st
3. ha kcuart rx low_level_definition fAll F C9 E 4demo_xilinx_ISE_3E labsource KCPSM3 VHDL kcuart_ts vhd ag kcuart tx low_level_definition JAll v E demo_sxilinx_ISE_3E labsource KCPSM3 HDL uart_clock vhd en uart clock Behavioral All v E demo_xilinx_ISE_3E labsource KCPSM3 HDL uart_rx vhd aa uart re macro level definition JAII X p E demo_xilinx_ISE_3E labsource KCPSM3 VHDL uart_tx vhd lem uart tx macro level definition JA Click OK accepting the default setting of All for both source files In the Sources in Project window select Implementation in the Sources pane and select the top TN level design file uart clockt vhd Make sure that Jerat symbol appears in front of uut instance If not right click on the uut instance and select Set as Top Module Click OK on the message Sources for Implementation 8 lab S 9 xc3s500e 4ft256 ag kepsm3_int_test Behavioral kcpsm3_int_test vhd j lem processor kcpsm3 low level definition kcpsm3 hd ha lem program int test low level definition INT TEST YHD ii Ha k Behavioral fuart clock shd pe i processor kcpsm3 low_level_definition kcpsm3 hd j program_rom uclock i i transmit uart tx macro level definition uart_ts vhd lem receive Uart rx macro level definition uart rx shd E Sources ps Snapshots f Libraries The design requires a 55 MHz clock Since the Spartan 3E board in
4. program provided with the distribution is able to interpret upper and lower case characters by converting commands see documentation for details to upper case before analyzing them Incorrect commands will result in a syntax error message and incorrect time values will be indicated by an Invalid Time message Although it is unlikely to occur when using hyperterminal an overflow error message will be generated if commands are transmitted faster than the design can process them ie UART receiver buffer becomes full Click Add Source and browse to the c KCPSM3 VHDL Select the VHDL files uart clock uart_tx uart_rx kcuart_tx kcuart rx bbfifo 16x8 and kcpsm3 files and click Open Click Next leaving a check mark in each box for the copy to project option Click Finish The dialogue below should appear which allows you to select a flow none implementation simulation or both associated with each source file Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 13 R Adding Source Files The following allows you to see the status of the source files being added to the project and allows you to specify the Design View association for sources which are successfully added to the project Design Unit Association C9 E demo_xiliny_ISE_3E labsource KCPSM3 VHDL bbfifo_16x8 vhd i bbe 16 8 fw level deft E demo_xilinx_ISE_3E labsource KCPSM3 YHDL kcuart rx vhd
5. Communications gt HyperTerminal Give the session a name click OK and specify COM port connection ie COM 1 Click the Configure button and specify the following parameters for the port settings Click OK when finished e Baud rate of 38400 8 data bits No parity bits 1 stop bit No flow control Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 27 COM1 Properties Port Settings Bits per second Data bits Parity Stop bits Flow control EEE v Restore Defaults Figure 1 32 Settings for Serial Port Communications Click the Settings tab the ASCII Setup tab and then click so that a check mark appears next to the Append line feeds to incoming line ends option and then click OK Click OK again to exit the properties dialogue arwz_pace Properties Connect To Settings Function arrow and ctrl keys act as Terminal k Terminal keys O ASCII Setup Backspace key sends ASCII Sending CikH O Dea O C Send line ends with line feeds Emulation _ Echo typed characters locally Auto detect Line delay 0 miliseconds Character delay 0 miliseconds Telnet terminal ID Backscroll buffer lines 500 ASCII Receiving Play sound when connecti Append line feeds to incoming line ends Force incoming data to 7 bit ASCII Input Translation Wrap lines that exceed terminal width Figure 1 33 ASCII Settings f
6. File Edit View Call Transfer Help KCPSM3 time 99 06 53 KCPSH3 gt lt gt Connected 0 13 51 Auto detect 38400 8 N 1 NUM Figure 1 36 Display of Current Time Enter the command alarm at the command prompt to display the current alarm time in the form of hh mm ss Note the alarm is inactive fpga_flow Hyper Terminal File Edit View Call Transfer Help KCPSH3 gt time 00 06 53 KCPSH3 gt alarm 60 06 60 Figure 1 37 Display of alarm time and status Enter the command alarm on for the alarm to become active Enter the command alarm 00 00 30 to set the alarm to 30 seconds Enter the command time 00 00 00 to set the time Note You should notice that led1 on the Digilent Spartan 3E board will light up once the alarm goes off Enter the command alarm off to shut off the alarm Note You should notice that the led1 turns on indicating that the alarm has been disarmed Close iMPACT program without saving the project and close ISE Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 30 MH s You will extend the lab design by adding a ChipScope ILA core to the PicoBlaze output bus Next you will setup the trigger to capture data when text is entered via hyperterminal You should see the resulting text displayed in ChipScope when the buffer is full Create a New ChipScope Pro Source Step 13 Create anew ChipScope Definition and Connection source by
7. Lab 3 Xilinx PicoBlaze Flow Lab Targeting Spartan 3E Starter Kit berapaan e f je Platform Flas in TEXAS INSTRUMENTS X XILINX DIGILENT SPARTAN 3E Lvditatatatutatatatatabubudatatatatatababubudidit Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 1 7 XILINX MH s Create a New Project Step 1 Create a new project targeting the Spartan 3E device that is on the Spartan 3E kit Specify your language of choice VHDL or Verilog to complete the lab Launch ISE Select Start All Programs Xilinx ISE Design Suite ISE Project Navigator New Project Inthe Project Navigator select File gt New Project or click on New Project The New Project Wizard opens For Project Location use the button to browse to one of the following directories and then click OK e VHDL users c labs lab3 The Working Directory path will also be set to the same directory automatically For Project Name type Flow lab leaving Top level source type as HDL se New Project Wizard Create New Project E x Enter a name and location for the project Project name Project location flab3 C Mabs lab3 aoe Select the type of top level source for the project Top level source type HDL More Info Figure 1 1 New Project Wizard Click Next Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 2 mi Select t
8. The steps below are for illustrative purposes only and show how to analyze the internal signals of the design The first step shows how to add internal signals to the waveform The second step shows how to analyze the interrupt process The third step shows how to analyze the output waveform process You may optionally complete these steps if you have additional time at the end of the lab Monitor internal signals by adding them to the design You need to expand the design hierarchy and select the desired module entry uut in Instance and Process Name window and then select the desired signal address in Simulation Objects window Right click on it and select Add to Wave Configuration Similarly add interrupt interrupt_ack and instruction signals Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 9 Design Unit testbench testbench behavior Suut kepsm3_int_test behavioral B proce kepsm3 low level definition progr int test low level definition Brg Sources Files les Snapshots D Libraries Sim Instance rx Type All v counter 7 0 Output Port JUJUUUUU waveforms 7 0 Output Port UUUUUUUU interrupt_event Input Port O 0 0000000101 011100000000000001 gnal 00000001 onal 00000010 Input Port Show Driver Add To Waveform in_port 7 0 Internal Signal oo000000 write_ strobe Internal Signal O read strobe Internal Signal O interrupt Internal Signal O
9. interrupt_ack Internal Signal O reset Internal Signal O Sf Processes Sim Objects Figure 1 13 Accessing Internal Signals 1 00us v Change radix of address and instructions to hexadecimal Enter 25 00us in in the tool buttons bar where 1 00us is displayed click Simulation gt Restart followed by Simulation gt PAKA Run for Specified Time to re simulate the design Using buttons from toolbar you can zoom into any area of the simulator waveform window Analyze the waveform for Interrupt Service Routine process Figure 1 14 1 900 ns 2 000 ns 2 200 ns 4 counter 7 0 d waveforms 7 0 interrupt event clk period address 9 0 004 X 005 D06 005 3FF X PBO X 2B1 interrupt interrupt_ack SM instruction 17 0 l 1C001 35405 X 10001 35405 X 10001 34280 15A01 X2CA04 x 36001 Figure 1 14 Interrupt Service routine Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 10 MH s Add write _ stribe signal and re simulate the design Analyze the output waveform process Figure 1 15 2 000 ns 2 500 ns b Sd counter 7 0 00009010 p Bd waveforms 7 0 interrupt event clk period a address 9 0 interrupt interrupt_ack p Sd instruction 17 0 1co01 write_strobe Figure 1 15 Output Waveform Note The int_test log file in the Assembly directory shows the address and code for each instruction Close the simulator windows Click No to quit the simulator without saving the run Implem
10. Automotive amp Industrial Basic Elements 9 Communication amp Networking Debug amp Verification J Digital Signal Processing FPGA Features and Design i E ChipSync a Clocking i S Spartan 3E Spartan 34 N Board Deskew with an Internal Deskew DCM SP v9 1i Pe N Cascading in Series with Two DCM SP v3 11 Pe N Clock Forwarding 4 Board Deskew DCM SP v9 1 Pe X Clock Switching with Two DCM SPs v9 1i ae 2 Single DCM SP v3 11 al Virtex 4 More Info Back new Cancel Figure 1 19b Architecture Wizard Selection Box E Fl sevens Jose t El Click Next and click Finish Xilinx PicoBlaze Flow Demo Lab www xilinx com XILINX In the Xilinx Clocking Wizard General Setup window set the following options as shown in Figure 1 20 and click Next to continue o CLKO CLKFX and LOCKED boxes Checked o RST box Unchecked o Input Clock Frequency 50 MHz A Xilinx Clocking Wizard General Setup l x Phase Shift Type NONE Value jo Input Clock Frequency so e MHz C ns CLKIN Source External Internal Single Feedback Source C External Internal C None Single C Differential Differential Divide By Value Feedback Value 2 r f 1K OX Ik Use Duty Cycle Correction i Advanced Back Next gt Cancel Figure 1 20 Xilinx Clocking Wizard Genera
11. L Pinout Repon Design Goat Bameed Timing Constraints Al Corsairs He a L H Clock Report Design Strategy Xiinx Default unlocked Final Timing Score 0 Timing Report and Warnings l ha p Synthesis Messages Be D Translation Messages D Map Messages fee D Place and Route Messages ag p Timing Messages Ben D Bitgen Messages Pa D All Current Messages El ana Reports ba E Synthesis Report a Bee B Translation Report i E Map Report Tj Number of Slices 103 4 656 a c Ts Ba Ke NN MEN 130 1 Project Properties H Enable Enhanced Design Summary O Enable Message Filtering i C Display Incremental Messages Enhanced Design Summary Contents H M Show Partition Data O Show Errors O Show Warnings O Show Failing Constraints i CJ Show Clock Report Figure 1 18 Design Summary The design implements a real time clock maintaining time in hours minutes and seconds together with the ability to set an alarm The unusual feature of the design is that a UART serial communication is used to set and observe the time alarm sending simple text commands and messages via a utility such as hyperterminal The design understands some simple ASCII commands and even supports some editing during their entry using the backspace key on your keyboard A command is only completed when a carriage return is entered The design is ready to accept a command when the KCPSM3 gt prompt is displayed The uclock
12. Simulation v B lem testbench behavior E demo xilins ISE 3E labsource KCPSM H Pal uut kepsm3 int test Behavioral kcpsm3_int_test vhd Erg Sources fp Snapshots Figure 1 10 Hierarchical View Including Test Bench Expand the Xilinx ISE Simulator toolbox in the Processes window right click on Simulate Behavioral Model and select Properties Enter the value of 25000 for the Simulation Run Time and click OK E Process Properties ISE Simulator Properties Use Custom Simulation Command File Custom Simulation Command File l Run for Specified Time Vv Simulation Run Time 25000 ns Property display level Standard Default Cancel Apply Help 4 Figure 1 11 ISIM Behavioral Simulation Properties Double click Simulate Behavioral Model to simulate the design Figure 1 12 Click on Zoom to Full View button Click close to us time in the waveform window Click Zoom In couple of times to see the activity happening between 0 and 2 us Change radix of waveforms signal by selecting it in the Name column of the waveform window right click select Radix followed by Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 8 2 Hexadecimal You should see three input interrupt pulses and the displayed interrupt count value You should also see an alternating inverted pattern displayed gt interrupt event clk period Figure 1 12 iSIM Behavioral Simulation Results
13. allows you to specify which data will be stored in the internal buffer Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 33 3 Trigger Parameters Capture Parameters Net Connections Trigger Input and Match Unit Settings Number of Input Trigger Ports 3 wi Number of Match Units Used 3 TRIGO Trigger Width 1 Match Type Basic sv Match Units KN Ed Bit Values 0 1 X Counter Width Disabled w Functions lt gt gt TRIG1 Trigger Vvidth Match Type Match Units il Bit Values 0 1 X Counter Width Disabled Functions lt gt TRIG2 Trigger Width 1 Match Type Match Units a4 wi Bit Values Trigger Condition Settings Enable Trigger Sequencer Max Number of Sequencer Levels 2 v E Storage Qualification Condition Settings Enable Storage Qualification Figure 1 42 Specify the Trigger Parameters The maximum number of data sample words that the ILA core can store in the sample buffer is called the data depth The data depth determines the number of data width bits contributed by each block RAM unit used by the ILA unit The maximum number of data sample words that can be captured depends on the number and size of block RAM which varies according to device family and density Set the following capture parameters and click Next Data Depth 512 Sample On Rising clock edge Data Same as Trigger Port unchecked Data Width 8 Xilinx PicoBlaze Flow Demo Lab www xili
14. cdc uart c loc Ko es cdec hae Ia uart clock ucf uart clock ucf E Sources Figure 1 39 ChipScope Definition and Connection cdc added to VHDL Project Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 31 MH 2 Configure and Connect an ILA Core Step 14 gt Connect the ILA core to the PicoBlaze output Double click the uart clock cs cdc file in the sources in project window to open the core inserter project amp ChipScope Pro Core Inserter uart_clock_cs cdc O x File Edit Help Hee gt DEVICE Select Device Options ICON Design Files Input Design Netlist Output Design Netlist Core Utilization Output Directory Device Settings Device Fame v LUT Count 97 Use SRL16s FF Count 28 Use RPMs BRAM Count 0 essages Loading CDC project C labsilab1uartclock_cs cde Successfully read project Clabsilabliuart clock cs cdc gt 4 Figure 1 40 ChipScope Pro Core Inserter Note Projects saved in the Core Inserter hold all relevant information about source files destination files core parameters and core settings Click Next and then click New ILA Unit Notice in the left hand window how an instance of the ILA core UO ILA is added to the system ICON Parameters No ICON parameters Figure 1 41 Insert a new integrated logic analyzer ILA Unit Click Next to
15. ERCODE O MyDeviced XC 35500E 6 01c22093 3 1 MyDevicet 5 05045033 2 MyDevice CoolRunner ll 06c5e033 Figure 1 50 Impact Detects Devices in JTAG Chain Right Click on the xc3s500e device and select configure Click Select New File and select the uart clock bit bitstream file from the project directory Note that the import cdc file field shows the cdc file located in the project directory The user will need to create a bus out_port Right click OK Double click on Trigger Setup and Waveform entries in Project Tree to open the respective windows The ChipScope Pro Analyzer interface consists of four parts New Project Rr JTAG Chain Project Tree Tri DEV 0 M Deva C3S500E Match Unit Function UNIT O MyILAO ILA gt MO TriggerPortO Trigger Setup Waveform M1 TriggerPort1 9 M2 TriggerPort2 Listing Data Port fout_port Windows 1 Trigger Ports All Data TriggerPortO TriggerPort1 TriggerPort2 Data and Trigger Bus Signal Ports f gt fout port Figure 1 51 ChipScope Analyzer Window Each ChipScope Pro ILA ILA ATC and IBA core has its own Trigger setup window which provides a graphical interface for the user to setup triggers The trigger mechanism inside each ChipScope Pro core can be modified at run time without having to recompile the design There are three components to the trigger mechanism Xilinx Pi
16. P BUFGP BUFGP aa 4 Move Nets Up en_16_x_baud en_16_x_baud en 18 x haus In 18 x baud burg tg Lena gt Figure 1 45 Net Connections The Select Net dialog provides an easy interface to choose nets to connect to the ILA ILA ATC or ATC2 cores The hierarchical structure of the design can be traversed using the Structure Nets pane All the design s nets of the selected structure hierarchy appear in the table at the lower left pane The Clock Signals and Trigger Data Signals tabs illustrate the net connections between the design and the ILA core With the Clock Signals tab under Net Selections selected highlight the entry for cIkSSMHz in the listing of nets and click the Make Connections button to connect the clock signal in the design to the clock port of the ILA core Net Selections Trigger Signals Data Signals Clock Signals Channel CHO fclk55MHz Figure 1 46 Connect the clock Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 36 MH s Click the Trigger Signals tab and connect the three trigger ports as follows e TPO rx data present this signal indicates that data is present in the uart rx module e TPI read from uart input to uart_rx that indicates that a read operation will occur e TP2 write to uart input to uart tx that indicates that a write operation will occur Click the Data Signals tab and connect the output port of the PicoBlaze controller to the data port of the ILA
17. R Help TIMESPEC Name Clock Net Name clk Clock Signal Definition e Specify Time Time 20 Units ns Y e Start HIGH C Start LOW Time HIGH 50 Units E C Relative to other PERIOD TIMESPEC Reference IIMESPEL v f Multiply by C Divide by Factors fic PHASE Plus C Mmus Value Units ns r Input Jitter Time Units ns Priority Comment Figure 1 28 Clock Period dialogue Accept the default settings of 20ns since we have 50 MHz clock source and 50 duty cycle by clicking OK Select Ports in Constraint Type window and double click the white space under the Pad to setup column in the right side window to invoke the Offset In Wizard Leave the default settings System synchronous SDR and Rising edge and click Next after reviewing the description Note Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 24 2 that the PicoBlaze design is using a single clock for the entire design where all registers are clocked on the rising edge ES OffsetIn Wizard x Interface type System Synchronous SDR Rising System synchronous PERIOD ns HIGH re ONY re Clock F8ING OFFSET IN we C Source synchronous Data rate Single data rate SDR Double data rate DDR Data Clock edge 515 VALID Center aligned Edge aligned Rising edge Falling
18. cel Figure 1 3 Create New Source Dialog Click Next The Add Existing Sources dialog appears Figure 1 4 New Project Wizard Add Existing Sources x Add existing sources o Eoo ou Iira Add Source Remove Adding existing sources is optional Additional sources can be added after the project is created using the Project gt Add Source or Project gt 4dd Copy of Source commands More Info Back New Cancel Figure 1 4 Add Existing Sources Dialog Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 4 MH 2 Add an Existing Design to the Project Step 2 Add HDL source files for an example PicoBlaze design You may review the PicoBlaze documentation to become familiar with the 8 bit microcontroller architecture and assembler Refer to KCPSM3 manual pdf in the KCPSM3 docs directory Click Add Source and browse to the c KCPSM3 VHDL Select the VHDL files kcpsm3 int test and kcpsm3 files and click Open Click Next leaving a check mark in each box for the copy to project option Click Finish The dialogue below should appear which allows you to select a flow none implementation simulation or both associated with each source file E New Project Wizard Add Existing Sources x Add existing sources Add Source kepsm3_int_test vhd Remove kepsm3 vhd Adding existing sources is optional Additional sources can be added after the pro
19. cludes a 50 MHz oscillator you will use the Architecture Wizard to generate a DCM with a 55 MHz output and instantiate it into the design Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 14 MH s Configure a DCM Step 6 This version of the design is missing a DCM component Use the Architecture Wizard to configure a DCM component to output a clock at 55 MHz Inthe Processes for Source window double click Create New Source If you do not see the Create New Source process ensure that an HDL source file is selected in the Sources in Project window Inthe New Source window select IP CoreGen amp Architecture Wizard and enter my dcm as the file name and click Next Figure 1 19a E New Source Wizard Select Source Type x IP CORE Generator amp Architecture Wizard D Schematic el Implementation Constraints File A State Diagram File name Test Bench Waveform OS User Document Verilog Module Location Wh Verilog Test Fixture Cabs OOOOC lt CS si S Ti VHDL Module C Vabs lab1 a A VHDL Library P VHDL Package tal VHDL Test Bench Embedded Processor Ik Add to project More Info Back oo Cancel Figure 1 19a New Source Wizard Selection Box Inthe Select IP window expand FPGA Features and Design gt Clocking gt Spartan 3E Spartan 3A and select Single DCM SP v9 1i Figure 1 19b ES New Source Wizard Select IP x J
20. coBlaze Flow Demo Lab www xilinx com 1 38 2 e Match Functions Defines the match or comparison value of each match unit e Trigger Conditions Defines the overall trigger condition based on a binary equation or sequence of one or more match functions e Capture Settings Defines how many samples to capture how many capture windows and the position of the trigger in those windows In this design you will setup the triggers to capture text at the PicoBlaze output port after being entered via hyperterminal Specify the Match Units as follows e M0 TriggerPort0 rx data present Value 1 e Ml TriggerPortl read from uart Value 1 e M2 TriggerPortl write to uart Value 1 E Trigger Setup DEV 0 MyDeviced XC3S500E UNIT O MyiLAG ILA coccinea nanan nanan o a Bd Match Unit Function o C MO TriggerPortO gt EI M1 TriggerPortt o CJ M2TriggerPort2 Figure 1 52 Setup the Match Units Click the field under Trigger Condition Equation set the equation M0 M1 in the Sequencer tab and then click OK Trigger Condition TriggerConditionO Boolean Sequencer Number of Levels v Use Contiguous Match Events Only Level Match Unit Negate 1 MO E E 2 L KI Trigger Condition Eguation MO gt M1 Figure 1 53 Trigger Condition Equation Check the field next to Storage Qualification select the AND E
21. core see Figure 1 50 and click OK Trigger Signals Data Signals Clock Signals Channel CH 0 Yout port 0 out_port lt 1 gt CH 2 jout portx2 Ca jou ponas out_port lt 4 gt CH 5 jout_port lt 5 gt H 7 out_port lt 7 gt Figure 1 47 Connect the PicoBlaze output port You will notice that the Clock Trigger and Data ports under Net Connections are highlighted in black indicating valid connections Click Return to Project Navigator and save the file DEVICE LA ICON UO ILA Trigger Parameters Car et Connections UNIT CLOCK PORT TRIGGER PORTS DATA PORT Figure 1 48 Connection between Design and ILA core Established Specify ChipScope Analyzer Options Step 15 You will download the bitstream using ChipScope and configure the ILA core to trigger when the UART reads text from hyperterminal With the top level file uart clock vhd selected double click on Analyze Design Using ChipScope in the Processes window Click the Open Cable Search JTAG Chain button Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 37 Ni Open Cablefsearch JTAG Chain JTAG Chain Figure 1 49 Establish JTAG Connection Click OK noting that the Spartan 3E device is the first device in the chain of three devices ChipScope Pro Analyzer xi JTAG Chain Device Order Index Name Device Name IR Length Device IDCODE US
22. d logic lock out std_logic end uart clock Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 19 2 note this lock output pin will drive the ledO on the Spartan 3E board and is driven by the lock signal on the DCM This will indicate to the user that the DCM has successfully locked onto the 50 MHz clock signal from the on board oscillator Click File Save to save the file Notice that the source file my_dcm xaw is now inserted into the correct place in the design hierarchy Sources for Implementation hd 4ft256 kepsm3_int_test Behavioral kcpsm3 int test vhd i E processor kcpsm3 low_level_definition kepsm3 vhd Fe hg program int test low_level_definition INT_TEST VHD ashe es uart_clock Behavioral uart_clock yhd j processor kcpsm3 low level definition kcpsm3 shd je program_rom uclock f X Inst mp dem my dem my_dem saw transmit uart_tx macro_level_definition uart_ts vhd E hl receive uart_rx macro level definition uart_rx vhd E Sources Ps Snapshots IP Libraries Assign Pin Locations Step 8 In this step you will use PinAhead to assign locations to the pins in the design You will then verify in the Pad report that the pins have actually been assigned after running place amp route 2 In the Sources in Project window select the top level design file uart_clock vhd In the Processes window expand User Constraints a
23. e top level design file uart clock vhd Inthe Processes for Source window expand User Constraints and double click Create Timing Constraints Figure 1 26 Processes for uart_clock Behavioral a m Add Existing Source ba PI Create New Source te E View Design Summary S Design Utilities 1g User Constraints z Is Create Timing Constraints 23 Floorplan I0 Pre Synthesis 73 Floorplan Area 10 4 Logic Post Synthesis DO Synthesize XST CO Implement Design i amp WEA anar ate Pres sramina File ja ap Processes Figure 1 26 Processes for Source Window In the constraint Type under Timing Constraints window select Global see Figure 1 27 to list the clock domains in the design Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 22 Constraint Files uart_clock uct C Show Constraints from Specified File only Show Constraints from All Files Constraint Type Timing Constraints as Global Advanced H Group Constraints H Miscellaneous Erg Sources Files Snapshd IP Libraries Timing Constra Figure 1 27 Timing Constraints Editor Double click Period entry under the Clock net name window on right to open the Clock Period dialogue Clock Net Name Period Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 23 Bul LT x Initial active edge used for OFFSET value is set to HIGH k PERIOD EE N Cancel k INPUTITTE
24. edge All edges Figure 1 29 OFFSET IN Wizard Clock Edge Page Enter the value of 7 ns for OFFSET IN see Figure 1 30 and click Finish Note that this design does not have stringent timing reguirements for clocking in external data so a random value of 7 ns was chosen ES OffsetIn Wizard Data Page Kn xi Capturing clock pad net clk Create Edit Capturing clock information System Synchronous SDR Rising hb PERIOD 8 __________j HIGH rs ONY D36 ww i r RISING OFFSET IN Clock Name clk Period 20 ns Duty Cycle 50 Data COO Aoo RisingData Data a RISING VALID _________ gt Input pad group net clk v Create Rising edge External setup time offset in 1 Data valid duration 20 Clock Information The capturing clock Pad Net is the clock net used to capture the incoming data Information from the selected clock is shown in the Clock Information area A new clock PERIOD can be defined by selecting the Create New Clock Period button Input register group v Create mom row wa Input Pad Group Figure 1 30 OFFSET IN Wizard Data Page Similarly select Outputs in Constraint Type window and double click the white space under Clock to pad to invoke the Offset Out Wizard and enter a value of 7 5 ns see Figure 3 8 for the Offset Out constraint Click OK when finished Xilinx P
25. eing added to the project and allows you to specify the Design View association for sources which are successfully added to the project C9 INT_TEST VHD ra int test low_level_definition All Figure 1 8 VHDL ROM Definition Files Click Open and then OK to add INT TEST as a VHDL Design File to the project Figure 1 9 Sources for Implementation lai F xc3s500e 4ft256 lem processor kcpsm3 low level definition kcpsm3 shd lem program int test low level definition INT_TEST VHD Erg Sources pa Snapshots IP Libraries Figure 1 9 Hierarchical view of PicoBlaze design Note The top level kepsm3_int_test file contains an instantiation of the int test ROM definition file After adding this source code for the int_test to the design the red question mark in the module view will disappear as it is no longer seen as a black box Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 7 MH s Simulate the Design Step 4 gt Add the testbench and review the code Run a behavioral simulation using the Xilinx ISIM simulator and analyze the results Goto Project gt Add Copy of Source or click on de and browse to c KCPSM3 vhdl or verilog Select the testbench file test bench vhd and click Open Set the association to Simulation and click OK to add the test bench to the project Click on Sources for and select Behavioral Simulation Sources for Behavioral
26. ent the Design Step 5 gt Implement the design During implementation some reports will be created You will look more closely at some of these reports in a later module Inthe Sources in Project window select Implementation in the Sources pane and select the top level design file Acpsm3_int_test vhd Figure 1 16 Make sure that symbol appears in front of uut instance If not right click on the uut instance and select Set as Top Module Click OK on the message Sources for f Implementation eba Ef xc3s500e 4ft256 aah kepsm3_int_test Behavioral kcpsm3_int_test vhd processor kcpsm3 low level definition kcpsm3 shd ba program int test low level definition INT_TEST YHD Er Sources Files Snapshots Libraries Figure 1 16 Sources Window Pane Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 11 MH 2 Inthe Processes for Source window double click Implement Design Figure 1 17 Notice that the tools run all of the processes required to implement the design In this case the tools run Synthesis before going into Implementation Sources for Implementation hd 9 xc3s500e 4ft256 E pis kcpsm3 int test Behavioral kcpsm3 int test vhd te lem processor kcpsm3 low level defirition kcpsm3 shd a lem program int test low level definition INT TEST YHD Er Sources ps Snapshots A Libraries Add Existing Source P Create Ne
27. er and template files to your project directory For the workshop we will keep the files in the current location int_test psm II F Archivo PSM KCPSM3 EXE 2 KB ROM Form coe Archivo COE 1 KB ROM Form Documento de texto 15 KB ROM form vhd Documento de textc 13 KB uclock psm Archivo PSM S0 KB El Figure 1 7 PicoBlaze Assembler Files Open the int test psm file using a standard text editor such as Wordpad and review the code referring to the PicoBlaze 8 bit Embedded Microcontroller User Guide or KCPSM3 manual for technical guidance These documents are provided in the docs sub directory Open a command window by going to Start gt All Programs gt Accessories gt Command Prompt Browse to the Assembler directory using the cd command gt cd c KCPSM3 Assembler Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 6 MH s Generate the ROM definition files by assembling the example assembly application Enter the following command at the command prompt gt kcpsm3 int_test psm Note You should now see several files in the Assembler sub directory starting with init test including VHDL int_test vhd ROM definition files Add VHDL ROM definition file to the project Go to Project gt Add Copy of Source or click on from the side button window and select either int_test vhd file Figure 1 8 E Adding Source Files x The following allows you to see the status of the source files b
28. he following options and click Next Device Family Spartan3E Device xc3s500E Package fg320 Speed Grade 4 Synthesis Tool XST VHDL Verilog Simulator ISE Simulator VHDL Verilog Preferred Language VHDL E New Project Wizard Device Properties Select the device and design flow for the project Property Name Product Category gt Fem Spatense SC SS Device C3S500E Package G320 2 TopLevel Source Type mooo S S Synthesis Tool ST VHDL erilog v ISE Simulator YHDL Verilog Speed Preferred Language Enable Enhanced Design Summary Enable Message Filtering More Info Back new Cancel Figure 1 2 Device and Design Flow Dialog The Create New Source dialog will appear Figure 1 3 You can use this dialog to create a new HDL source file by defining the module name and ports All of the source files have been created for you in this project so you will not create a new source file here Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 3 E New Project Wizard Create New Source x Create a new source New Source Remove Creating 4 new source to add to the project is optional Only one new source can be created with the New Project Wizard Additional sources can be created and added to the project by using the Project gt New Source command Existing sources can be added on the next page More Info lt Back New gt Can
29. icoBlaze Flow Demo Lab www xilinx com 1 25 MH Output interface detail Single datarate Dual data rate Dutput clock pad net clk v Output pad timegroup net counter Os Create TxData Rising edge constraints Offset out Units 7 5 ns A TxClk eee ee Output skew reference pin lt Default gt gt v Create Output register timegroup Rising edge comment Figure 1 31 OFFSET OUT constraints dialogue Save the constraints and close the timing constraints editor Test the Design in Hardware Step 10 Open the uclock psm file using a standard text editor such as Wordpad and review the code refering to the PicoBlaze 8 bit Embedded Microcontroller User Guide or KCPSM3 manual for technical guidance These documents are provided in the docs sub directory Open acommand window by going to Start gt All Programs gt Accessories gt Command Prompt Browse to the Assembler directory using the cd command gt cd c KCPSM3 Assembler Generate the ROM definition files by assembling the example assembly application Enter the following command at the command prompt gt kcpsm3 uclock psm Add VHDL ROM definition file to the project Go to Project gt Add Copy of Source or click on a from the side button window and select either uclock vhd file Figure 1 8 Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 26 ES Adding Source Files
30. ject is created using the Project gt Add Source or Project gt Add Copy of Source commands More Info Back New gt Cancel Figure 1 5 Choose Source Type Click OK accepting the default setting of All for both source files Note You should see a module called int_test listed in the hierarchy view with an orange question mark This module is a BlockRAM that will contain the instructions for the PicoBlaze controller which will be added in a later step Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 5 Sources for Implementation hd Slab 5 gA xc3s500e 4ft256 DE kepsm3_int_test Behavioral kcpsm3 int test vhd processor kcpsm3 low level definition kcpsm3 shd i 9 program int test Gre Sources es Snapshots Figure 1 6 Design Hierarchy in Sources Window Complete the Design Step 3 gt An example assembly psm file called init_test psm is included with the PicoBlaze distribution You will assemble this file to generate the instruction ROM and add it to the design Open up Windows Explorer and browse to the Assembler provided in the KCPSM3 sub directory c KCPSM3 Assembler Note The KCPSM3 exe assembler and ROM form template files along with two example PSM files should reside in this directory Keep in mind that the assembled output files will be generated in the directory containing the assembler and template files It may be beneficial to copy the assembl
31. l Setup Window In the Xilinx Clocking Wizard Clock Buffers window Figure 1 21 keep the defaults and click Next Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 16 fA xilinx Clocking Wizard Clock Buffers Clock Buffer Settings LEE E EEE EEE EEE EERE EERE EEE EEE REESE EEEEE EEE EEE EEEEEEEE EEE EEE EERE EEE EEE EEEEEEEEEEEEEEEEE EEE EEE EEE EE EEE EE Global Buffer Global Buffer Figure 1 21 Xilinx Clocking Wizard Clock Buffers Window In the Xilinx Clocking Wizard Clocking Frequency Synthesizer dialog enter 55 MHz as the output frequency and click Calculate to determine the M multiply and D divide values that are used to calculate the output frequency A Xilinx Clocking Wizard Clock Frequency Synthesizer Valid Ranges for Speed Grade 4 DFS Mode Fin MHz Fout MHz Low 0 200 333 000 5 000 311 000 High 0 200 333 000 5 000 311 000 Inputs for Jitter Calculations Input Clock Frequency 50 MHz Use output frequency 55 MHz ns C Use Multiply M and Divide D values M 4 DH Calculate Generated Output Output Period Jitter unit Period Jitter Freq MHz interval pk to pk ns Figure 1 22 Specifying the DCM output frequency Click Next and then Finish Notice that a new file my_dcm xaw is added as a Source in the project Figure 1 23 This source file will not be included in the design hierarchy until the com
32. nd double click Floorplan I O Pre Synthesis to open PinAhead Click yes when asked to add a UCF file to the project Click Close to close the introductory window 1f it shows up You can uncheck the box if you do not want to see this introductory window every time you invoke PinAhead from ISE In the I O Ports window select tx signal In the I O Port Properties window type m14 in the site field and click Apply Select configure tab and select LVTTL as the I O standard and select 8 mA as the drive strength Click Apply button to assign these properties Similarly enter the pin constraints for other pins in the design as shown in the I O Ports list window Figure 1 24 Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 20 ki Design Object List I O Pins clk Input c9 BANKO LYVCMOS33 NZA 3 30 lock Output fl2 BANKO LYTTL N A 3 30 rx Input i BANK2 LYTTL NZA 3 30 alarm Output el2 BANKO LYTTL N A 3 30 tx m4 SANKTILVTTI NA 13 30 18 Figure 1 24 Enter Pin Location Constraints Listed below are descriptions for the I O signals that you have just assigned The complete pinout for the Spartan 3E starter kit can be found in the user manual clk connected to 50 MHz oscillator lock connected to ledO alarm connected to led1 rx connected to pin that receives serial data from Maxim MAX3232 tx connected to pin that transmits serial data to Maxim MAX3232 O O O00 0 View your pin assignments in relation to the in
33. nx com 1 34 Select Integrated Logic Analyzer Option Trigger Parameters Capture Parameters Net Connections Capture Settings Data Width Sample On Rising v Clock Edge Data Depth 512 v samples _ Data Same As Trigger Trigger Ports Used As Data Include TRIGO Port width 1 Include TRIG1 Port width 1 Include IRIG2 Port width 1 Figure 1 43 Specify Trigger Parameters The net connections tab allows you to choose the signals to connect to the ILA core If trigger is separate from data then clock trigger and data must be specified Connections that have not been made will appear in red ILA Trigger Parameters Capture Parame Net Connections UNIT CLOCK PORT TRIGGER PORTS DATA PORT Figure 1 44 Unconnected Net Connections Click the Modify Connections tab Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 35 amp Select Net xj Structure Nets Net Selections Iuart clock Trigger Signals Data Signals ChipScope ILA Clock Signals ports avaiable ies ooo for connection List of design nets ae alarm_not0001 alarm notoooni torz LT baud_count lt 0 gt baud count s baud_count_5 FDR FDR baud_count lt 6 gt baud_count 6 FDR baud count cmp eg0 baud count cmp eg0 LUT4 LUT4 cIkSSMHz CIK55MHz_BUFG BUFG BUFG RN P1 TP2 clkSSMHz1 Inst_my_dem clk_BUFGP clk_BUFG
34. or Serial Port Connection Connect the cables power USB and rs232 and power the board Select uart_clock vhd expand Configure Target Device and double click on Manage Configuration Project IMPACT Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 28 2 When the iMPACT opens double click on Boundary Scan in iMPACT Flow window Click on Initialize Chain button Click YES and then browse to the project directory Select uart_clock bit file for the xc3s500e first device in JTAG chain Next click NO as we do not want to attach the PROM files and click bypass for the remaining devices and then click OK TDI xc3s500e xcfO4s xc2cb4a uart clock bit bypass bypass TDO Figure 1 34 JTAG Chain with assigned configuration files Right click on the xc3s500e in the iMPACT window and select Program Note You should now see the KCPSM3 gt prompt in the hyperterminal window If not then hit Enter key fpga_flow HyperTerminal Fie Edit View Call Transfer Help KCPSH3 gt _ Figure 1 35 Serial Communication with PicoBlaze Operate the UART Real Time Clock Step 12 gt You will issue commands to operate the UART real time clock as specified in the UART real time clock pdf file Enter the command time at the command prompt to display the current time in the form of hh mm ss Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 29 2 fpga_flow Hyper Terminal Ck
35. ponent has been instantiated into one of the HDL source files You will do this in the next step Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 17 Sources for Implementation hd kepsm3_int_test Behavioral kcpsm3_int_test vhd je processor kcpsm3 low level definition kepsm3 vhd p program int test low level definition INT_TEST VHD pi uart clock Behavioral uart_clock vhd H Taj processor kcpsm3 low level definition kcpsm3 shd Pe 2 program_rom uclock EI transmit uart tx macro level definition fuart tx vhd Pl receive uart rx macro level definition uart rx shd foe 3 mp dem my dem xaw ER Sources TP Libraries Figure 1 23 DCM listed in design hierarchy Instantiate the DCM into a VHDL Design Step 7 Now that you have created the necessary files you can instantiate the DCM component into your design Copy and paste the text from the Instantiation Template into uart clock vhd and connect the signals In the Sources in Project window double click uart clock vhd to open the source code in the text editor Select my dcm xaw in the Sources in Project window In the Processes for Source window double click View HDL Instantiation Template to open the instantiation template in the text editor From the Instantiation Template my dcm vhi copy the component declaration begins at COMPONENT my dcm and end after END COMPONENT and paste into uart clock vhd
36. quation and check M2 Click OK This will enable the ILA core to capture data in the buffer only when data is present and not on every single clock edge Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 39 Storage Condition O All Data AND Equation OR Equation C Negate Whole Equation Match Unit Enable Negate MO z o M o i L UI M2 fa L KI Storage Condition Eguation Figure 1 54 Storage Qualification Equation Perform an On Chip Verification Step 16 Start Hyper Terminal program Set baud rate to 38400 Arm the trigger and view the waveforms of the captured data Set the buffer depth to 16 r Type Window v Windows 1 Dept Storage Qualification M2 16 v i Position 0 ainjdes 4 Figure 1 55 Select Buffer Depth Cick the Apply Settings and Arm Trigger button jed Figure 1 56 Apply Settings and Arm Trigger Type alarm on in hyperterminal and view the message in ChipScope Analyzer Si Waveform DEV 0 MyDevice0 XC3S500E UNIT 0 MyiLAO ILA o a Right click and set Radix to ASCII Buffer setup to capture 16 samples Figure 1 57 Output in Waveform Window Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 40
37. selecting Project gt New Source and entering the name uart clock cs Click Next to continue New Source Wizard Select Source Type x ChipScope Definition and Connection File d IP CORE Generator amp Architecture Wizard MEM File el Implementation Constraints File D Schematic File name A State Diagram fuatcockes Test Bench Waveform uart clock cs User Document Location Verilog Module Wh Verilog Test Fixture JC Mabe lab E Hal VHDL Module IP VHDL Library VHDL Package a VHDL Test Bench Embedded Processor Ik Add to project More Info lt Back oke Cancel Figure 1 38 New Source Dialog Box Select uart_clock as the source Click Next and then Finish A ChipScope Pro source will be added to the Sources in Project window Sources for Implementation E lab1 S 9 xc3s500e 4fg320 lem kcpsm3 int test Behavioral kcpsm3 int test vhd pe lem processor kcpsm3 low level definition kcpsm3 vhd Le al program int test low level definition INT_TEST VHD Maleh uart_clock Behavioral E demo_xilins_ISE_3E labsource KI a processor kcpsm3 low_level_definition kcpsm3 vhd he em program rom uclock low level defirition E demo_sxilinx_ Ha transmit uart tx macro level definition E demo xilins ISE E H hal receive uart rx macro level definition E demo_silins_ISE amp uart c loc kK es
38. setup the trigger parameters Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 32 2 Each ILA or ILA ATC core can have up to 16 separate trigger ports that can be setup independently The individual trigger ports are buses that are made up of individual signals or bits that can range from 1 to 256 bits Each trigger port can be connected to 1 to 16 match units A match unit is a comparator that is connected to a trigger port and is used to detect events on that trigger port The results of one or more match units are combined together to form the overall trigger condition event that is used to control the capturing of data The different comparisons or match functions that can be performed by the trigger port match units depend on the type of match unit The ILA and ILA ITC cores support six types of match units In this lab you will setup the ILA core to trigger via some UART control signals Set the following ILA trigger parameters as follows and then click Next Trigger Input and Match Unit Settings e Number of input trigger ports 3 Trigger Port Trigger Width Match Units Counter Width Match Type TRIGO Disabled TRIG do o JE Disabled TRIG2 Disabled Trigger Condition Settings e Enable Trigger Sequencer Checked This allows you to specify a sequence of events to enable triggering e Max Number of Sequencer Levels 2 Storage Qualification Condition Settings e Enable Storage Qualification Checked This
39. ternal logic Inthe I O Ports window select a pin e g rx and click on Fit Selection button Notice that the FloorPlan window shows the selected I O and the Device Package window shows the Figure 1 25 Top View 123 4 5 6 8 9 1011 12 13 14 15 16 17 18 lt c Hodvywvz2 2FrTFr Acro a 1MOO0O0r lt cCApPU0zZEr rx TO 1mMOO0rL g POOR OOOO BOOED BOOO JOR SOU 1 2 3 4 5 6 8 9 1011 12 13 14 15 16 1 16 Figure 1 25 Device and Package Windows Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 21 2 The colored bar alongside the I O pins indicates which pins are in the same I O bank You can easily see which pins have been assigned to the same bank Click each I O pin in the I O port and observe the corresponding pin in the Device and Package windows when click on Fit Selection button Click File Save to save these pin placements Click File Exit to close PinAhead Click OK Highlight the UCF file in the Project Navigator expand User Constraints and double click Edit Constraints Text to view the constraints created in the uart clock ucf file through PlanAhead View the text version of the UCF file to confirm that the constraints were written to the file Enter the Global Timing Constraints Step 9 In this step you will use a graphical tool called the constraints editor to enter PERIOD 20 ns and OFFSET IN OUT 7 ns and 7 5 ns constraints Inthe Sources in Project window select th
40. w Source 5 View Design Summary SB Design Utilities Sy User Constraints C Synthesize XST i Implement Design H Translate H A Map H 2 Place amp Route gt Generate Programming File gt Configure Target Device IP Update Bitstream with Processor Data Figure 1 17 Processes for Source Window While the implementation is running click the next to Implement Design to expand the implementation step and view the progress We refer to this as expanding a process After each stage is completed a symbol will appear next to each stage Check mark for successful Exclamation point for warnings X for errors For this particular design there may be an exclamation point warnings for some steps The warnings here are okay to ignore Read some of the messages in the message window located across the bottom of the Project Navigator window When implementation is complete double click on E Design Summary Reports in Processes window to review the design utilization in the Design Summary window Figure 1 18 Xilinx PicoBlaze Flow Demo Lab www xilinx com 1 12 7 XILINX a Io Nabi Project Status 02 23 2013 18 35 29 i ummary BOB Pepe Module Name Tepmdnttat Ew L EModieleveiUilesion Target Device wasmemss swam z E Timing Constraints Product Version ISE 10 1 03 Foundation Simulator Routing Results All Signals Completely Routed

Lab 3: Xilinx PicoBlaze Flow Lab

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