Home

Crossbar Switch

1. gt Rx ID Mask 0 29 S Rx ID Mask 63 29 Each buffer has its own receive ID mask For backwards compatibility Global mask Mask 14 amp 15 register are used out of reset Buffers 0 7 can be used to implement an 8 frame Rx FIFO Ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 83 f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e FlexcAN Message Buffer Structure FlexCAN Message Buffer Structure 0x0 CODE SRR LENGTH TIME STAMP IDE RTR 0x4 Extended Standard Extended ID ID 0x8 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 0xC Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Receive Buffer Codes Transmit Buffer Codes Booe ater eserpion Betore ater OO esor 0000 pm Buffer not active 4000 Buffer not ready to transmit 0010 0010 0110 Buffer is Full Overrun 1100 1000 Tx buffer ready to transmit once Buffer Active amp Empty Remote frame will transfer and msg buf becomes Rx buf Data frame t
2. DEx Peripheral Set x Divider Enable DIVx Peripheral Set x Divider x Division Value 1 16 Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 47 f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e M CGM Output Clock gt Clock output on the GPIO O pin osca clk irc fast CLKOUT div 1 2 4 8 CLOCK OUT fmplla cik Selector GPIO 0 as dutput Clock Division Select facie CGM_OCDS_ SC SELDIV division by 1 2 4 8 SELCTL clock source OscA Irc fast pll selection e Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 48 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc K freescale CGM Source Clock Main Feature Summary Division Trimble Signaling Switching Bypass C
3. Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 202 f E pem Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesCca e K ADC a Daa aaa Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor i Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 203 7 fre es C a e Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo ADC overview 10 bit ADC resolution on MPC5605 6 7B additional 12 Bit ADC e Supports conversions time down to 650ns starrer lines e internal clock will be system clock 2 e ADC is specified from 6MHz to 32MHz e Up to 36 single ended inputs channels expandable to 64 channels with external multiplexers e Internally multiplexed channels 10 bit 2 counts accuracy TUE available for 16ch 10 bit 3 counts accuracy TUE available for up to 20ch e Externally
4. e MCB e OPWMT e OPWMB e OPWFMB e OPWMCB e IPWM IPM e DAOC e SAIC SAOC e GPIO e MC MCB e OPWMT e OPWMB e OPWFMB e SAIC SAOC e GPIO e OPWMT e OPWMB e IPWM IPM e DAOC e SAIC SAOC e GPIO C e OPWMT e OPWMB e SAIC SAOC e GPIO e SAIC SAOC e GPIO g sng 193 unoo g sng 13 unoo Global PreScaler 8 Bit Counter Bus Global Clk PreScaler 8 Bit Counter J sng 193 unop J sng sejunoy y sng sequnoy N q sng seyunoy O O C D s U C oe UO Counter Bus A eMIOS1 eMIOSO J sng sejunoy lt lt __ gt lt _ lt _ _ _ lt _ _ 4 lt __ _ O Cc r OD mS d am ee m Ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 24 1 f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e M eMIOS Channel Type Channel Type e General Purpose Input Output cs a a Single Action Input Capture Single Action Output Compare Modulus Counter Modulus Counter Buffered Up Down Input Pulse Width Measurement Input Peri
5. Freescale and the A a ogo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qor s a trademark of Freescale Semiconductor se Inc a Power Architec and Power o ses rks and the Power and Power PA and related marks H aa e a fo f u Power org Al other pro co cen e the property of their respec ective o 5 2008 2010 2011 Freesca le Semiconductor Inc 147 eo reesca e LLL LL ae Interrupts 200Z0 Interrupt Vectors IVOR Interrupt Type Enables State Examples Saved In IVORO Critical Input CE CSRRO 1 Non maskable interrupt pins PD 10 PD 11 IVOR1 Machine Check ME CSRRO 1 ISI ITLB error on 1 instr n of exception handler IVOR2 Data Storage SRRO 1 Incorrect privilege mode for R W access IVOR3 Instruction Storage SRRO 1 Incorrect privilege mode for instruction IVOR4 External Input EE src SRRO 1_ Peripherals IRQ pins software IVORS Alignment SRRO 1 Load or store operand not word aligned IVOR6 Program SRRO 1 Illegal instruction trap IVOR72 FP Unavailable SRRO 1 FP instruction attempt with MSR FP 0 IVOR8 System Call SRRO 1 System call sc instruction IVOR102 Decrementer EE DIE SRRO 1 Decrementer timeout IVOR112 Fixed Interval Timer EE FIE SRRO 1 Fixed interval timer timeout IVOR122 Watchdog Timer CE WIE CSRRO 1 Watchdog timeout when ENW 1 WIS 0 IVOR132 Data TLB Error SRRO 1 Data TLB miss in MMU IVOR142 Instruct n TLB Error SRRO 1 Instruction TLB miss in MMU IVOR15 Debug
6. eMIOS 2 4 3 2 24ch FlexCAN LINFlex SPI 12C t t F 4 Family Differences Note block diagram represents the MPC5606S 40x4 MPC5606S 1 MB 48K SRAM 160K Display Control Unit DCU with QuadSPI 2xFexCAN 2xSCl Nexus 176 144 Graphics RAM Parallel Data Interface PDI 3xDSPI 4xlIC MPC5604S 512 KB 48K SRAM No 64x6 No 2xFexCAN 2xSCl 28KB 144 100 2xDSPI 2xlIC MPC5602S 256 KB 24K SRAM 64x6 No 1xFexCAN 2xSCl 24KB 144 100 3xDSPI 2xIIC The MPC5606S Hybrid Cluster SoC LEDs 2x CAN 2x LIN RTC 48K SRAM 4x16k 160K EEPROM Graphics 64MHz RAM sound Power TM 1MB by E200z0h core FLASH Display QuadSPI 40x4 LCD Control Serial Flash segment Unit Controller driver apeage m DOA eT Low cost Quad Serial Flash eMIOS 6 Stepper Motor Drivers PWMs with patented stall detection MPC5606S NANA D AQA Lr TA i ji UUU P lol KN TFT DISPLAY DCU on MPC5606S can drive up to 480x272 LCD with no external RAM e Cost efficient e Low memory requirement e Optimized for GUI and advanced OSD e Safety feature to enable safety related display content Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 1 6 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks an
7. Notes On a comparator A match FLAG is set and the internal counter is set to value 0 A change of the A2 register makes the A1 register be updated at the next clock e Caution If when entering MC mode the internal counter value is upper than register UCA n value then it will wrap at the maximum counter value FFFFFF before matching A1 NY Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 21 8 f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e N E eMIOS Modes Modulus Counter Buffer Mode UP Counter Generates a time base which can be shared with other channels through the internal counter bases Can use Internal or External input channel pin counter Internal Counter UCCNTn 0x001000 0x000800 0x000001 FLAG pin t t f register A1 value 001000 000800 A2 value 001000 write tt update A1 match into A2 A1 match of A1 A1 match Notes On a comparator A match FLAG is set and the internal counter is set to value 1 Allowing smooth transitions a change of the A2 register makes the A1 register be updated when the
8. June 8 2011 Qorivva 32 bit Power Architecture MCU DwF Hangzhou Hands on Training Johnny Chen PARE Automotive Field Application Engineer j Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by f J u Ireescaie Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc KY i 69 I Oorivva Device Overview 6 Interrupt Control Bolero Pictus Spectrum Monaco Hardware vector mode Development Tools and Support Software vector mode Hands on SW Interrupt 2 I O Modules SIUL 7 Communication Modules Hands On EVB intro GPIO DSPI LINFlex FlexCAN CAN Sampler Hands On RappID amp FlexCAN 3 System Clock Module Timer 8 System Related FIRC FXOSC SIRC SXOSC PLL Peripheral Bridge STM RTC SWT PIT Crossbar Switch Hands On System_Clk BAM 4 Power Mode Control 9 ADC CTU EMIOS Mode Entry Module ADC Power Control Unit CTU Voltage Regulator EMIOS Wakeup Unit Hands on ADC EMIOS Hands on Mode Transition Standby 5 Memor 10 Hands on Workshop Memory Map Starter TRAK Flash SRAM Lab Demo 1 2 3 4 5 6 7 MPU Fr
9. 2011 Freescale Semiconductor Inc reesca e ECC Interrupt Interrupt CARRE CIC we ECC_DBD PFlattormFlash Plattform ECC Double Bit Detection ECC DBD_PlatformRAM ECC SBC_PlatiormFlash Platiorm ECC Single Bit Correction ECC SBC_PlatiormRAM Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by N Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc 1 45 M freescale 6 Interrupt Control gt Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 46 pP f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc gt reesca e LL Overview of Instruction Control e200Z0 Interrupt control mechanism Is defined by a Power Architecture Book E ISA The implementation of the mechanism is called INTC module in MPC560x MCU
10. Enables the input buffer of the pad gt ODE Open Drain Output Enable Selects either open drain or push pull driver configurations for the pad This feature applies to output pads only gt SRC Slew Rate Control Controls the slew rate of the output signals gt WPE Weak Pull Up Down Enable Enables Disables the weak pull up down on the pad gt WPS Weak Pull Up Down Select Selects weak pull up down if enabled Reset 0 N cale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se k Frees Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 35 Ps f ii a J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e Peripherals SIUL Pad Control and lOMux configuration 1 5 Alternate functions are chosen by PCR PA bitfields PCR PA 00 gt AFO PCR PA 01 gt AF1 PCR PA gt 10 gt AF2 PCR PA 11 gt AF3 This is intended o select the outpt functions For input functions PCR IBE bit must be written to 1 regardless of the values selected in PCR PA bitfields For this reason the value 2 7 Functional ports A B C D E F G H The functional port pins are listed in Table 2 3 Table 2 3
11. FMPLL clocked by FXOSC e Optional output clock frequency modulation for current consumption spreading e Optionally monitored by CMU e can be used as system clock Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 4 4 eF f i Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e CGM Clocking Structure system_clk osca clk div div 1 to 32 System irc_fast_div Clock div 1 to 32 Selector ME div 1 to 15 EMPL div 1 to 15 irc_fast RESET osca _clck SAFE div 1 to 15 oscb_clck INT irc_slow irc_fact_div _ gt b clk_d div 1 to 32 aoa irc_slow_div div 1 to 32 osca_clk irc_fast CLKOUT fmplla clk Selector gt div 1 2 4 8 freescale Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 4 5 Power org All other product or service n
12. M freescale Notes gt When power is removed from a domain all of the status and contents of memories and registers is lost gt Typically RAM Is split across two domains with a small block preserved even in STANDBYO mode gt The primary domain 0 is always powered even in STANDBYO mode as wakeup unit Is located in this domain Ky Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm tal s a trademark of Freescale Semiconductor rks r l Inc ne Powe r Ar Hiie aa and Power T T rks and the toed and Power bee and related marks Ni a and service marks licensed by f J Power org All other produ Ba vice n e the property of their respective own O2 2010 2011 a reesca le Semiconductor Inc 107 reesca e KA Voltage Regulator and Power Supply Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 0 8 e fr e e S C a e Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo err VREG Supply Pin gt VDD_HV VSS_HV 4x pairs Digital Supply Voltage e Range 5V or 3 3V e Supply modules I O clock sources flash HV part gt VD
13. Pae Pore Wateup_ rar wuria Pas Pemon waret ma 2 Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 1 7 eF f i Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e External Wakeups Interrupts The Wakeup Unit supports up to 18 external wakeup interrupts which can be allocated to any pad necessary at the SoC level This allocation 1s fixed per SoC IRGQ_17_16 Interrupt Controller IE MIIE H Wakeup enable WREA 17 0 Ff Ff fF i fg of f Ff fF i Interrupt enable IRER 17 0 WIFER 17 0 Edge Detection E_ T_T T_T eT eT eT eT eT Tg ft ft Analog Glitch Filter Glitch Filter enable T MM LX Pads oe ae oe ALAA A Figure 28 4 External Interrupt Pad Diagram Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by Power org All other product or service names are the property of t
14. e S DFLA data flash status S SYSCLK system clock status Ky Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off oe is a trademark of Freescale Semiconductor Inc The Powe r Ar Hiie aa and Power pee a rks and the and Power or and related marks are tr a rks and service marks licensed by 86 le Semiconductor Inc a gos elat Power org All other produ pa vice n e the property of their respective own S 2008 2010 2011 Er reesca freescale SW and HW Transition gt Software handled transition A transition is requested writing a key protected sequence in ME_MCTL e Mode Entry configures the modules according to the ME xxx MC register of the target mode e Once all modules are ready the new mode is entered e Transition completion signaling status bit interrupt e Note Modification of a ME_xxx_ MC register even the current one is taken into account on next mode xxx entry gt Hardware triggered transition Exit from low power mode e SAFE transition caused by HW failure Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 87 PF f u Power org All other product or service names are the p
15. internal counter reaches the value 1 e Caution If when entering MCB mode the internal counter value is upper than register UCA n value then it will wrap at the maximum counter value FFFFFF before matching A1 freescale Ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 21 9 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M eMIOS Modes Modulus Counter Buffer Mode UP DOWN Counter Generates a time base which can be shared with other channels through the internal counter bases Can use Internal or External input channel pin counter Internal Counter UCCNTn 0x001000 0x000800 0x000001 FLAG pin register A1 value 001000 000800 A2 value 001000 write tt update A1 match into A2 A1 match of A1 A1 match Notes On a comparator A match FLAG is set and the internal counter is set to value 1 Allowing smooth transitions a change of the A2 register makes the A1 register be updated when the internal counter reaches the value 1 Caution If when entering MCB mode the internal counter value is upper than register UCA n value then it wi
16. of which WKUP2 can cause non maskable interrupt requests The Wakeup Unit supports these distinctive features Non maskable interrupt support with NMI source with bypassable glitch filter Independent interrupt destination non maskable interrupt critical interrupt or machine check request Edge detection External wakeup interrupt support with 3 system interrupt vectors for up to 18 interrupt sources Analog glitch filter per each wakeup line Independent interrupt mask Edge detection Configurable system wakeup triggering from all interrupt sources Configurable pullup On chip wakeup support 2 wakeup sources Wakeup status mapped to same register as external wakeup interrupt status N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Ps Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 1 6 eF f i Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc Yd reesca e Wakeup Line Mapping MPCS60x6 aI PCR Wakeup IRQ muo ae na WaleUp RO x A PCR1 WakeUp_IRQ_O WakeUp Ra 0 weurs Port Pones watema o weure Peo Pones wakeup imao roer Peo Poma wareup rao kuro
17. only be written in INIT mode Normal mode e Main user mode Ri INITIALIZATION SLEEP e Configuration registers protection in RUN mode sleep mode e low power mode entered on SW request NORMAL LINRX DOMINANT e LINFlex clock stopped e exit possible by SW or HW i Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 73 oF f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e LSAT LINFLEX Test modes Loopback LINFlex e Self test mode e LINFlex treats transmitted messages as received messages to be independent of external events LINTX LINRX LINFlex Selftest e hot self test mode e like loopback mode but without affecting the running system LINTX LINRX sp Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 2 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 7 4 esf f Power org All other produc
18. 0x07FFFF 128 Kbyte Mid Address Space Ox080000 0x1F FFFF High Address Space OOO AEF 8 Kee Shadow Ales Ss 0x204000 0x3FFFFF 2032 Kbyte Shadow Address Space OF 0x404000 0x7FFFFF Test Address Space N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 27 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc K freescale ST Flash in Different Modes Reset Mode v Reset is highest priority for Flash module and will terminates all other operations v Reset will terminates all other operations and forces Flash into the user mode to receive access v MCR DONE may be polled to determine if the Flash module has complete the transition out of Reset and the registers can not be written until MCR DONE is set Power down mode Disabled mode v All DC current can be turned off in power down mode so the power dissipation is due only to the leakage of circuitry v Read and write is not supported in this mode v Ifthe Flash is disabled during erase operation it could be suspended and resumed when power down mode is exited v Ifthe Flash is disable during the program opera
19. 1 TCTRL R Ox000000003 Enable PIT1 inte gge IHTC PSR 60 R Ox01 PIT 1 interrupt LAB1 into the ISR TEE T E T Modify PIT period to Fold initsylrgq4 vo1 INTC PSR 4 R 2 Software interrupt 4 IF check the result on board void aoar a d INTL LPR B PRI Single Core Lower I asni wrteel a Enable external inte y Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 2 4 5 f mi Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e N Lab Target Through this lab customer will learn how to use RAppID to generate FlexCAN loopback code compile with Codewarrior and debug on EVB Section e Getting Started with FlexCAN e Overview of the steps e RAppIDJDP GUI Setup e Code e Application Execution e Debugger Window HILFE Detail steps please refer to RAppID MPC5604B FlexCAN Tutorial located under RAppID install folder Xxx 560xB Help Tutorials FlexCAN Tu torial pdt EEI HEHH 3 eee Tera EEN saa eee kee Veena F oo eee ei ei m i e a o aooo uL a sc eee e ee fol eee Pop Wie PET ree poor REZ IC
20. All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e K Lab Target LAB3 Mode Transition Demo Through this lab customer will learn how to put Bolero ina specific mode by either software trigger or hardware trigger SYSTEM MODES USER MODES RECOVERABLE HW FAILURE SW REQUEST oe gJ AJ C NON RECOVERABLE HW FAILURE CRS E gt HW triggered transition gt SW triggered transition Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a tra LOW POWER MODES jJ demark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 2 43 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc Hints 1 DRUN to RUNO then to switch between RUNO and RUNS Configure the registers ME RUN 0 3 ME RUNPC 0 7 ME LPPC 0 7 Configure peripheral ME PCTLIn Wait for the mode stable before to do the mode transition ry freescale K LAB4 Low Power Mode Lab Target Through this lab customer will learn how to put Bolero into Standby and then exit the Standby by Wakeup pin or API USER MODE
21. Controls configuration of the static electrical and functional characteristics associated with I O pads gt One PCR Register per PAD gt Depending on the usage of each pad on the device we may have e PAD with GPIO and digital alternate function e PAD with Slew Rate Control e PAD with GPIO and analog functionality PAD dedicated to Precise ADC Channels gt This impact the availability of certains bits in the PCR registers as described in the following Ky Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm sl raed s a trademark of Freescale Semiconductor rks r l Inc ne Powe r Ar Hiie aa and Power T T rks and the toed and Power bee and related marks Ni a and service marks licensed by f J Power org All other produ Ba vice n e the property of their respective own O2 2010 2011 a reesca le Semiconductor Inc 34 reesca e 2 i ne Pad Configuration Register PCR Bitfields description 1 2 3 4 5 6 7 8 9 10 13 14 15 0 0 0 0 0 1 0 0 0 0 0 0 0 0 gt SMC Safe Mode Control Override automatic deactivation of the output buffer upon entering SAFE mode of the SoC gt APC Analog Pad Control Enables the usage of the pad as analog input gt PA Pad Output Assignment Select the function that is allowed to drive the output of a multiplexed pad gt OBE Output Buffer Enable Enables the output buffer of the pad when in GPIO mode gt IBE Input Buffer Enable
22. DE IDM CSSRO 1 ROM Debugger when HIDO DAPUEN 0 DE IDM DSRRO 1 ROM Debugger when HIDO DAPUEN 1 1 CE ME EE DE are in MSR DIE FIE WIE are in TCR src is individual enable for each INTC source Debug interrupt VOR15 also requires EDM 0 EDM and IDM are in DBCRO 2 Unused on e200z0 Ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 148 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M freescale TE Interrupts Hardware and Software Vector Mode Software Vector Mode The CPU branches to one of the 16 core interrupt vectors IVOR s which contains a branch to an exception handler eg IVOR4 handler The exception handler is common for the majority of exceptions Prologue Identification of specific interrupt by reading a register Location of ISR is read from a jump table Branch to ISR Common epilogue Hardware Vector Mode The IVOR4 vector is not used instead each interrupt has a unique vector entry containing the jump address of the ISR The ISR contains Unique Prologue ISR Unique Epilogue HW and SW Vector Modes are configurable by cor
23. FlexCAN Pins 64 100 144 te R v4 freescale Ce Bolero Family Product Offering Entry Level BCM Mid Range BCM 16 32bit MCU 1 x 16 32bit MCU lt 512k Flash lt 1 5MB Flash Feature Needs 1 2 CAN 2 4 CAN 1 2 LIN 7 LIN lt 112 LQFP 144 176 LQFP MPC5604 3 2B C MPC5607 6 5B z0 64MHz z0 64MHz Freescale Solution Up to 512KB Flash 48KB RAM Up to 1 5M Flash 96KB RAM Up to 6 CAN 4 LIN 3 SPI Up to 6 CAN 10 LIN 6 SPI 100 144 Pin 100 176 Pin re The oy Acer and Poer ora wo nats adhe Po and Poner ora aoe rad na tans ana Sondee matched freescale Door Lock oe Example of Body Control Module Block Diagram Door Lock H bridge ican Warning LEDs S08 Door Lock te Door Lock H bridge CAN System Basis vinci Various sensor inputs Chip Multiplexor Various sensor inputs CAN CAN Transceiver Multiplexor Various sensor inputs CAN CAN Transceiver MPC560xB LIN Transceiver c UHF Amplifier C transceiver LI N LIN Transceiver Antenna LI N LE LIN Transceiver Internal Lighting High side Horn switches External lighting Multiplexor E gt LED control Seat control LED Drivers Various Outputs se 9 2 fre le Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off
24. Functional Port Pin LET w Alternat T a PCR e 2 o8 j BREE register function gt o jy i 5 144 1 gt E s amp LQFP ea pi I PCA AFo GPIO 0 SIUL I O i AF1 EOUC 0 eMIOS 0 H AF2 CLKOUT CGM AF3 EOUC 13 eMIOS 0 rf WKUPI19 KPU PCR 1 AFO I O Tristat AF1 EOUC 1 eMlOSo 1 0 e AF2 AF3 WKUP 2 9 WKPU NMI4 WKPU PCR 2 AFO GPIO 2 SIUL I O k AF1 EOUC 2 eMIOSO 1 0 ie WKUP 3 WKPU corresponding ae etd otoS ic i m LINSTX LINFlex 5 to an input only function is reported as k ma om i Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 36 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc N K freescale Eo S E SIUL Pad Control and IOMux config PSMI Registers Choosing the input pad O 1 2 3 4 8 9 10 11 12 15 16 17 18 19 20 23 24 25 26 27 28 31 R FD TO pasen A A posen f fF fF _0 oo oo PADSELn PADSEL n 1 PADSEL n 2 PADSEL n 3 w E O T Ce D 1 2 rr ne gt Different pads can be chosen as possible inputs for a certain peripheral function gt Each PADSEL selects the pad currentl
25. Provides a series of enhanced Enabled by a proven ecosystem of control peripherals with industry features for accurate reliable and development tools software benchmark architecture robust control and design resources High performance 64 MHz 32 bit Hardware Error Correction Coding A full suite of 3 party software and tool e200z0 Power Architecture core with ECC on RAM and auto grade flash vendors peripheral drivers compilers variable length encoding VLE memory allows memory error detection debuggers and RTOS s Up to 512KB flash and additional 64KB and correction One click solution development kit data flash allows for flexible cost includes a Getting Started DVD with efficient memory configurations Fault collection unit FCU eases one click access to documentation depending on application needs abil a cid nik application notes software examples A cross triggering unit significantly Se ene ie ee ee ase and training reduces interrupt load due to hardware Freescale market leading Automotive synchronization of the PWM cycle MCU quality and reliability with low timers and the ADCs failure rates and 15 years product Rich set of peripherals for complex longevity field oriented control algorithms improves electric motor efficiency and reliability Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 14 In
26. a FLAG event On Comparator A1 match Output pin is set to value of EDPOL On comparator A2 match FLAG is set and can allow to synchronize with other events ie AD conversion On Comparator B1 match Output pin is set to complement of EDPOL The transfers from register B2 n to B1 n is performed at every match of register A1 N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor oa Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 225 eF Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc freescale o M eMIOS Modes OPWMT Generates a PWM signal with a fixed offset and a trigger signal Intended to be used with other channels in the same mode with shared common time base This mode is particularly useful in the generation of lighting PWM control signals output flip flop i i FLAG pin i E S S i i register Selected counter bus 0x001000 0x000600 0x000400 0x000200 B2 value 000200 i i 000200 l l I l r d d S I I I A1 value 000200 000200 000200 l l A2 value 000400 0040 000400 i i e A1 amp B1 write into Update A24 write no No B1 a match maici B2 of B1 Imatch match of B1 ae a
27. amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by Caution A2 n value is not readable A1 n value is not writable and therefore cannot be configured in this mode use GPIO mode for example Caution A2 n is not buffered its update is immediate Caution Registers loaded with 0 will not produce matches if the time base is driven by a channel in MCB mode A 4 KO Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc 227 freescale eMIOS OPWMT Trigger event The trigger event generated by an OPWMT channel allows to synchronize ADC conversion w r t PWM signal The CTU Cross Triggering Unit can be configured to define the ADC channel to be converted on OPWMT channel trigger Each ADC conversion result is stored in a dedicated result register refer to ADC slides eMIOS A ChO Trig eMIOS A Ch1 Trig Event Configuration Reg 0 P gt Event Configuration Reg 1 eMIOS B Ch n Trig gt Event Configuration Reg 63 ADC Control ADC Trigger csl ADC Conversion Done N Freescale and the Fre PO e trademarks of Freescale Semiconductor Inc a a pi rivva is a trademark of Freescale Semiconductor Inc re Powe ea and Power ee or mars a and the id and Power oe an
28. be converted by hardware po ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 20 5 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc freescale C a Peripherals ADC Sampling and Conversion Timings Sampling and conversion sequence 0 5 cycles I I 10 cycles 1 l k 2 5 cycles gt k 1 l l l 1 1 l 4 Sampling phase oee Successive approximation evaluation phase gt l l l Latching phase The capacitors field input switch is opened Example Operating conditions INPLATCH 0 INPSAMP 3 INPCMP 1 and Fiac ak 20 MHz sample INPSAMP ndelay Tx e INPSAMP 2 3 ndelay 0 5 if INPSAMP lt OGh otherwise 1 eva 10 INPCMP Tay e INPCMP 2 1 and INPLATCH lt INPCMP T Tava ndelay Top End of conversion 7 7 conv sample eval N Freescale and the Fre E ogo are trademarks of Freescale Semiconductor Inc U S Pat amp Tm irae s a trademark of Freescale Semiconductor rks i Inc e Powe Adhie aa and Power a eri and the tad and Power abe and relate
29. bit EDPOL 1 for HIGH input signal selected counter bus FLAG pin register A2 captured value XXXXXX B1 value xxxxxx B2 captured SXXXXXX value A1 value xxxxxx Width A2 B1 Width A2 B1 idth A2 B1 2 Notes idt idt Width A2 B1 Leading edge is captured into B2 n EDPOL Determines if leading edge is high or low Trailing edge is captured into A2 n and Flag is set Pulse width is calculated by subtracting UCBn B1 from UCAn A2 Caution If pulse has spanned a counter bus period then need to take care to modify calculation Width UCAn Counter Bus Period UCBn Ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 21 6 f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e M Input Period Measurement Determines the period in counter bus clock ticks of an input pulse width Can use Internal or Modulus counter Can be configured to measure between 2 HIGH or 2 LOW edges determined by the state of the EDPOL bit input signal selected counter bus FLAG pin register A2 captured value XX
30. hr with 1s resolution RTC compare value changeable while counter is running RTC status and control register are reset only by POR Autonomous periodic interrupt API 10 bit compare value to support wakeup intervals of 1 0 ms to 1s compare value changeable while counter is running Configurable interrupt for RTC match API match and RTC rollover Configurable wakeup event for RTC match API match and RTC rollover N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor PS Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 71 esf f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e PIT timer Module Periodic Interrupt Timer PIT features 32 bit counter resolution clocked by system clock timer can generate interrupt independent timeout periods for each timer Channel outputs can trigger ADC conversion MPC5602 3 4 gt 6 PITs 4 G islo w Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Psd Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are tradema
31. is set to complement of EDPOL and internal counter set to 1 N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor oa Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 223 eF f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc P reesca eMIOS Modes OPWMCB Generates a center aligned PWM output signal with dead time insertion MODE 6 bit selects between trailing and leading dead time insertion respectively EDPOL allows selection between active HIGH or active LOW duty cycle Requires MCB UP DOWN MODE 5 1 l l l l output flip flop ae i EDPOL 1 MoDEIe 1 1 i FLAG pin f t i i register i 0x000800 0X000300 a l 0x000001 000800 000800 l l l I l l l l l l l Internal Counter 0x000020 0x000001 B1 value 000020 000020 i p00020 i B2 value 000020 oi i i i A 4 write update A 4 Notes A1 match fB1 match into A2 fai match Ta A1 A1 match 1 match tat match FLAGS can be generated only on B1 matches or on both A1 and B1 matches depending on MODE 5 bit The transfers from register B2 n to B1 n and from register A2 n to A1 n are performed at the first clock of the next cyc
32. multiplexed channels 10 bit 3 counts accuracy TUE available for up to 32ch Internal control to support generation of external analog multiplexer selection e Dedicated result register available for every internally and externally muxed channel e 3 independently configurable sample and conversion times for high occurrence channels internally muxed channels and externally muxed channels e Support for one shot scan injection and triggered injected CTU conversion modes e Independently configurable parameters for channels Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 20 4 p f m ITreescaie Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M eee Peripherals ADC Block Diagram AINO AIN1 i ADC data registers hte 10 bit l HOLD Converter l l l End of SUCCESSIVE APPROXIMATION A D CONVERTER conversion AINx End of injection ANALOG MUX Threshold Violation Interrupts EMIOS Cross triggering Timer channels Unit ADC_INTERRUPT Trigger event for injected conversion ADC CONTROL The CTU will automatically signal the channel to
33. names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc P lt reesca e Wo LL ae acca MPC563xM Key Benefits cont gt Helps Save Cost e Requires only one linear power supply SV e Compatibility with existing MPC5500 family allows code sharing and cost reduction of existing solutions into these new markets e No active external components are required for the on chip knock system because variable gain and sensor bias are on chip e QFP option has visible pins making it cheaper to assemble and inspect since infrared and X ray technology is not required gt Mitigates Supply Risk e The MPC563xM family of devices are dual sourced products enabling our customers to design applications with confidence that the supply will be there Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 20 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by f J Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc e reesca e M al Development Tools and Support 1 5MB Sample Part Numbers 512KB Sample Part Numbers e PPC5607BEMMGA 208 MAPBGA e PPC5604BEF1MMG 208 MAPBGA e PPC5607BEMLUA 176 LQFP PPC5604BEF1MLQ
34. names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc Yd reesca e Lan SRAM ECC Mechanism The SRAM ECC detects the following conditions and produces the following results Detects and corrects all 1 bit errors Detects and flags all 2 bit errors as non correctable errors Detects 39 bit reads 32 bit data bus plus the 7 bit ECC that return all zeros or all ones asserts an error indicator on the bus cycle and sets the error flag SRAM does not detect all errors greater than 2 bits ECC checks are performed during the read portion of an SRAM ECC read write R W operation and ECC calculations are performed durmg the write portion of a R W operation Because the ECC bits can contain random data after the device is powered on the SRAM must be initialized by executing 32 bit write operations prior to any read accesses This 1s also true for implicit read accesses caused by any write accesses of less than 32 bits as discussed in Section 17 4 SRAM ECC mechanism Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 4 4 eF f Power org All other product or service names are the property of their respective owners 2005 2010
35. owners 2005 2010 2011 Freescale Semiconductor Inc LLL a a Concept of ECC ECC is the abbreviation of Error Correction Code The objective of ECC is to enhance the reliability of data retention in the memory either Flash or SRAM ECC is a code corresponding to a set of data store in memory which contains the information relevant to that data Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor eo Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 142 Pr f a Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e N ae Flash ECC Mechanism For Flash memory the 8 bit ECC code are always applied to a fixed size of 64 bit data The 8 bit ECC code is capable of Single Error Correction and Double Error Detection which in short is SEC DED N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Ps Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 143 eF f i Power org All other product or service
36. produ ee vice n e the property of their respective own ects 2010 2011 aes reesca le Semiconductor Inc 161 reesca e CO INTC Benefits of Software Interrupts scheduling lower priority portions of an ISR High Without High Priority SWIRQ Priority e Setting software interrupt in ISR higher priority portion requests lower priority portion to complete Low at a later time Priority ISR e ISR partitioned into two ISRs ISR e Interorocessor Communication Shared Memory e Core 1 tells Core2 there is new data in shared memory N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 2 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 62 Pr f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc rd reesca e 7 Communication Modules ty Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 64 freescale Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Power org All other product or service
37. reesca le Semiconductor Inc 103 reesca e CO O Power Domain 2 Examples LLI l D V PD2 powered in uy LL e X gt OQ Y All modes except STNDBYO 0010000101101111 Allmodes except STOPO RUN3 amp RUNO 0000000010001011 OnlyRUN3 DRUN amp TEST RESET bit read only Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 04 Pr f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca E LS Reset Generation Module gt There are two classes of reset handled by the RGM Destructive resets completely restart the MCU after a critical event Register and memory contents are not guaranteed Functional resets restart digital modules but preserve analog flash and debugging module settings gt The RGM contains various registers that reflect the status of the MCU and allow users to configure certain reset behaviours gt There are four phases of reset that the RGM provides to ensure correct behaviour gt The RGM handles selection of the boot mode gt Resets can optionally drive the reset pin on an event Ky Freescale and t
38. slow IRC_ SLOW 128 kHz PLL Clock Monitor XOSC_ 32k CSC_32k_CLK 32 kHz Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 63 f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e M Timer STM RTC API SWT PIT Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor p Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 69 f m Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e K Timer Attributes Clock Timer SGUICE Features Functions Application 8 bit prescaler 1 256 32 bit wide 1 up counter 4 cmp channels with separate interrupt source for each Common system and system clock ren age application timing no internal prescaler 6 channel with 32 bit width generate periodic interrupt generate DMA
39. trigger pulse can trigger ADC conversion Common system and system clock i ee application timing 3 selectable clock source SIRC mn lz Free running counter for SXOSC 32 kHz time keeping FIRC 16 MHz applications System clock optional 512 and 32 prescaler Runs in all modes of autonomous periodical interrupt operation RTC status control register are reset only by POR no internal prescaler 32 bit counter optionally run in debug and stop mode but watchdog not available in standby mode SIRC 128kHz regular or window mode serive Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor ze Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by _ ts Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc 70 mi freescale RTC amp API Real Time Counter RTC 3 selectable counter clock sources SIRC128K SXOSC32K FIRC16M Optional 512 prescaler and optional 32 prescaler 32 bit counter e supports times up to 1 5 months with 1 ms resolution runs in all modes of operation e reset when disabled by software and by POR 2 bit compare value to support interrupt intervals of 1s up to greater than 1
40. 144 LQFP PPC5607BEMLQA 144 LQFP PPC5604BEF1MLL 100 LQFP PPC5607BEMLLA 100 LQFP _ Low Cost Demo Board Price 99 Full Evaluation Kit a7 O Evaluation system main module mini module and P amp E Multilink allov access to the CPU all of the CPU s I O signals and the motherboai peripherals such as CAN SCI LIN VB Kit VB Kit VB Kit VB Motherboard XPCS6xXMB BH VB Daughter Card XDC560B208SC512K O8MAPBGA 120 VB Daughter Card XDC560B144SC512K 120 VB Daughter Card XDC560B100SC512K OOLQFP 120 rack Board Low Cost Starter Kit TRK MPC5604B P amp E Hardware Interface Cable e USB ML PPCNEXUS gt 249 y Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 24 f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e K Evaluation Kit and Daughter Card Info Evaluation Board Summary and Features The evaluation system motherboard and daughter card allows full access to the CPU all of CPU s I O signals and motherboard peripherals such as CAN SCI LIN 12VDC power supply input barrel connector e 2 CAN channels with jumper enabl
41. 2 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by A Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc 222 eo freescale 4 N eMIOS Modes OPWMCB Generates a center aligned PWM output signal with dead time insertion MODE 6 bit selects between trailing and leading dead time insertion respectively EDPOL allows selection between active HIGH or active LOW duty cycle Requires MCB UP DOWN MODE 5 1 l l l l output flip flop ae i EDPOL 1 MoDEIe 1 1 FLAG pin i t t t register Sel Counter Bu i EV SCONE CO E E A E O E E O A T E anieeeet a 0x000 300 OEE T aia E E AT Pees ea E E E T 0x000001 A1 value 000300 000300 000300 000300 A2 value 000300 oi Internal Counter 0x000020 0x000001 Bi value 000020 000020 i 000020 B2 value 000020 oi i to i Notes A1 match 1 match tat match A1 match fB match fai match Period MCB Period Dead Time B1 n Duty Cycle 2 Period A1 n Dead Time On the selected dead time insertion edge On Comparator A1 match Selected Counter Bus the internal counter is set to 1 On Comparator B1 match Internal Counter Output pin is set to the value of EDPOL On the non selected dead time insertion edge On Comparator A1 match Output pin
42. D BV 1x pair Ballast Voltage e Range 5V or 3 3V e Supply the ballast transistors of all internal voltage regulators gt VDD_LV 3x pairs Internal Digital Low Voltage Internal 1 2V decoupling pins e 330nF capacitor must be placed between VDD_LV and VSS LV gt VDD HV ADC VSS_HV_ADC 1x pair e Range SV or 3 3V e Supply ADC module only v Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S P trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 09 f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e CEOTTO VREG Regulator Main Features gt 3 Regulators e High power or main regulator Low power regulator e Ultra low power regulator gt 4 Low Voltage Detectors e Low voltage detector for 5 0v on the main supply e Low voltage detector for 3 3v on the main supply Low voltage detector for 1 2v on main digital domain Low voltage detector for 1 2v on standby domain gt Power On Reset Ny Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and rela
43. Data Flash for EEPROM emulation 512K Flash 512K Flash 512K Flash Array 0 Array 1 Array 2 Array 0 L ees ee es es ee ee ees aM BankO CFlash Figure 20 1 Flash memory architecture W Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 30 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc freescale COO Flash Prog Erase Operations continued In general each modify operation is started through a sequence of three steps l The first instruction is used to select the desired operation by setting its corresponding selection bit in MCR PGM or ERS or UTO MRE or EIE 2 The second step is the definition of the operands the Address and the Data for programming or the Sectors for erase or margin read 3 The third instruction is used to start the modify operation by setting EHV in MCR or AIE in UTO Table 20 62 Flash modify operations Double word program MCR PGM Address and data by interlock writes Margin read UTO MRE UTO MRV LMS HBS ECC logic check ITO EIE UT0 DS1 UT1 UT In general each modify operation is completed through a sequence of four st
44. EE y g Standard OH HFE Pir amp Ble E m amp aligned PWM aE Z 4 mae 3 counts ail CHO Duty Cycle CH1 x g Duty cycle2 100 4 4 4 ADC 10 bit ANX uxed 4 RIS amp 4 q S NORMAL conversion 64 channel mE E TUE i 3 counts ere Hanz HAJA i are CEEE CORE ware BEN WEM W ee Fy Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor oa Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by Y f 247 Ireescaie Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc lt a freescale semiconductor
45. Each INTC interrupt has a unique 4 byte vector entry in the vector table at IVPR 2KB The table entry is calculated by adding the 4 byte vector to the IVPR There is no common handler and each interrupt ISR has it s own prologue and epilogue WPR 0 19 20 31 T Hardware Vector Mode Offset 0 19 20 21 oo 30 31 N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 2 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 156 eF f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e TTT intc Hardware Interrupt Example MAIN with return handler _0 Program T Prologue Interrupt_n Epilogue VECTOR Table Base Address b handler 0 IVPR 2KB b handler 1 b handler 2 b handler 3 handler_n Prologue b handler 293 Jump to address vector calculated as IVPR 0x800 Vector x 4 Epilogue handler_293 Prologue Epilogue Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor g Inc The Power Architecture and Power org word marks
46. Form Error Detected by a receiver if a fixed form bit field contains one or more illegal bits Acknowleage Error Detected by a transmitter if it does not receive a dominant bit during the ACK Slot A KO Freescale and the Fre a pee e trademarks of Freescale Semiconductor Inc pie U S Pat amp Tm sand s a trademark of Freescale Semiconductor Inc The Power Architectur and Power E als and the Pouer and Power or and related marks far arks emarks and service marks license 185 e Semiconduc tor Inc gos elat Power org All other produ pe vice n e the property of their respective own 5 2005 2010 2011 Fre reesca freescale a FlexcAN FLEXCAN Interrupts 20 unique INTC vectors per FLEXCAN2 module e 18 channel vectors 16 unique for buffers 0 15 1 for buffers 16 31 OR d together 1 for buffers 32 63 OR d together e 1 bus off vector e 1 error vector Each buffer has its own e Interrupt enable bit mask Q Interrupt is disabled 1 Interrupt is enabled e Status flag bit Ry Freescale and the Fre mais ogo are trademarks of Freescale Semiconductor Inc pie U S Pat amp Tm irae s a trademark of Freescale Semiconductor rks i Inc e Powe Adhie aa and Power a eri and the tad and Power abe and related marks hetero ite and service marks licensed by f Power org All other produ ee vice n e the property of their respective own ects 2010 2011 aes reesca le Semiconductor Inc 186
47. MD DSP amp loating point VLE Nexus IEEE ISTO MMU 5001 2003 3 x 4 Crossbar Switch I O Boot Bridge Assist Module Y v T ry O D Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 1 7 se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by PF f freescaie Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc Monaco Target Applications gt Up to 4 cylinder gasoline direct injection engines gt Entry level diesel engines gt Entry level transmission Images Dreamstime com N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 1 8 Ps Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by eF f J i Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e CO gt Go Green by Reducing Knock MPC563xM Key Benefits e On chip knock system makes tight emissions con
48. O 1 x FlexCAN with 32MB 1 x Safety port can be used as additional FlexCAN 32MB 1 x FlexRay Dual Channel with 32MB Y 2 x LinFlex CROSSBAR SWITCH 4 x DSPI 4 independent chip selects each 1 x FlexPWM 4x3 channels with 4 Fault Inputs 1 x eTimer 6 channels incl quad decode 1 x eTimer 6 channels for general purpose 2x ADC 2x13 Ch 4 shared channels 10bit conversion time lt 1usec 2x8ch 4shared on 100 pin package e1 x Cross triggering unit for motor control FlexRay Controller Boot Assist Crossbar Slaves Module BAM System 2 x PLL one FM PLL one for FlexRay 16Ch eDMA Fault Collection Unit 16MHz internal RC OSC Junction Temperature Sensor JTAG Nexus Class 2 3 3V single supply or 5V supply with external ballast transistor 100 and 144 pins TQFP package Communications I O System Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 1 oF f i Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e E Pictus Target Applications gt Electronic power steering gt Suspension gt Braking gt Brushless DC motor gt Electric hybrid
49. PC5604B C Microcontroller Reference Manual Automotive Software and Tools Brochure E200ZORM e200Z0 Core Reference Manual Freescale and the Fre age e trademarks of Freescale Semiconductor Inc Ses tiga tea cedar rivva is a trademark o reescale Semiconductor Inc The Nee ARIE ur and Power eee ord marks a andthe and Power ac and related marks are tadema and service marks a f J cal onductor Inc 28 reesca e a ogos Power org All other produ Sa vice nam e the property of their respective own 5 2005 2010 2011 Fre V T b Wo 2 SIUL of Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by f J i 29 reescaie Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc SIUL gt Introduction gt Pad Control and OMux configuration gt GPIO ports with data control gt External interrupt management gt MCU Identification sp Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Ps Inc The Power Architecture and Power org word marks and the Power and Po
50. Power Architec and Power T T rks and the Power and Power les and related marks ns ion ard A AA SA icensed by f J Power org A other pro ae cen e the property of their respec ective o O2 2010 2011 Freesca le Semiconductor Inc 81 reesca Ky D User Modes Description gt RUN O 3 e Full performance available Support WAIT instruction to stop the core with the capability to restart with very short latency lt 4 system clocks gt HALT Core stopped but system clock can remain the same as in RUN mode Selective peripheral clock gating Flash can be put in low power mode Useful to reduce device consumption during a slow serial communication e g LIN frame transmission or reception gt STOP e Core stopped limited clock sources e g no PLL available e Selective peripheral clock gating gt STANDBY e Mode providing the lowest possible consumption e Most functions digital and analog of the device are not powered Remains only the back up logic e g RTC API Wake up lines RAM 4 N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor p lt Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 82 PF f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale
51. Power and Power org logos and related marks are trademarks and service marks licensed by 61 7 fr e es C a e Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo DOO CGM Clock Monitoring Unit CMU gt PLL clock monitoring Detect if PLL leaves an upper or lower frequency boundary in turn can then switch to a SAFE mode gt Crystal clock monitoring Monitor the external crystal oscillator clock which must be greater than the internal RC clock divided by a division factor given by RCDIV 1 0 of CMU_CSR register Also in turn can then switch to a SAFE mode gt Frequency meter measure the frequency of a internal RC versus a Known reference clock XOSC Ky Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm sl raed s a trademark of Freescale Semiconductor rks Inc ne Powe Archie aa and Power T T rks and the toed and Power bee and related marks Ni a and service marks licensed by f J Power org All other produ Ba vice n e the property of their respective own O2 2010 ee ae reesca le Semiconductor Inc 62 reesca CGM CMU Block Diagram IRC fast IRC_FAST 16 MHz XOSC_ 4M FXOSC_CLK Frequency meter PLL stable unstable 4 16 MHz XOSC_4M stable unstable Mode Entry PLL_CLK FMPLL OSC supervisor FXOSC Failure Module Fosc 4M lt Firc_ fast 2 PLL Failure IRC
52. Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by OEM s and tier 1 s continually strive to integrate more features and functionality in to Body control Modules and gateways In future customers will want a bigger portfolio of Powerful microcontrollers Customers want to use the devices for a range of body controller and gateway applications Power efficiency is key for body controllers and gateways Customers need maximum reuse and easy to use development tools Customer demand ease of use MPC560xB C Value Proposition MPC560xB C Family ranges from 256KB up to 1 5MB Flash and uses the same core across the product range this enables customers to develop the application once and then reuse across a range of products platforms The MPC560xB C is part of a bigger range of products that go from low to high end Compatible Scalable products will be offered in the near future that offer lower and higher memory sizes and feature sets than the MPC560xB C Sophisticated peripherals FlexCAN for CAN networking LINFlex for LIN networking Cross triggering units CTU and eMIOS provide automated buffering cross triggering hence putting less constraints on software design e g Lighting Diagnostics EMC Power consumption of modules increases in each generation but environmental con
53. Qorivva is a trademark of Freescale Semiconductor oa Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 40 PF Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc freescale D SIUL MCU Identification Registers MDIR gt SIUL includes two registers that can be read by users and tools manufactures to determine what device is present which part number pkg flash size etc and to take the corresponding actions These registers are called MIDR1 Bt 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PartNo SPY PKG J 0 0 Mask_No_Major_ Mask_No_ Minor vv a e MIDR2 Bit O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RI S F Flash_Size_1 Flash_Size 2 Part_No x D 0 0 0 0 0 0 0 0 0 O EE O 0 0 FR wO OOOO OOO OOOO E ECOC ECC ECO O I IIUM ee ECEE FR bitis at 0 for Bolero Freescale and the Fre P ogo are trademarks of Freescale Semiconductor Inc Reg U S Pat ak ia mi s a trademark of Freescale Semiconductor se Inc e Powe Nchi aa and Power pee a rks and the and Power aie and relat arks Ni sone arks and service marks licensed by fo f J u Power org All other produ Sa vice n e the property of their respective own 5 2008 2010 2011 Fre re
54. Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 84 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc y CONFIGURABLE NORMAL NOT CONFIGURABLE LOW POWER aL al Ve A YY freescale System Clock Configuration RESET test sare Hat stop stBy IRC_DIV NO CLK HAUGK Hh d pi E V CONFIGURABLE NOT CONFIGURABLE Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 85 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc X freescale Global Status Register gt Global Status register ME_GS gives the status of the current mode S CURRENT MODE S e S MTRANS transition status e S_CFLA code flash status e S_DC current consumption e S PLL PLL status e S_ PDO control pad status e S_OSC XOSC status e S MVR VREG status e S_IRC IRC16M status
55. Register CR 1 2 Offset Oso000 Access User read write Cen Bitname Bit description O N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor p lt Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 53 PF f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc e reesca e CGM FMPLL Control Register CR 2 2 B p This bit is used to enable progressive clock switching 24 moe This bit is used to activate the 1 1 Mode unlock _once This bit is a sticky indication of PLL loss of lock condition Unlock_once is set when the PLL loses lock Whenever the PLL reacquires lock unlock_once remains set Only por_rst_b can clear this bit i_ lock This bit is set by hardware whenever there is a lock unlock event It is cleared aka a software writing 1 This bit is an indication of whether the PLL has This bit is an indication of whether the PLL has acquired lock lock a tak mask This bit is used to mask the pll_ fail output 30 pll_fail_ flag This bit is asynchronously set by hardware whenever a loss of lock event occurs while PLL is switched on It is cleared by software writing 1 Ky Freescale and the Freescale logo are tradema
56. S SYSTEM MODES _ECOVERABLE Hints we FAILU REI LOW POWER MODES RUNO to Standby Configure Wakeup pin before transfer to standby SW REQUEST reser om NON RECOVERABLE HW FAILURE gt HW triggered transition gt SW triggered transition Try to use Button4 to enter standby Wakeup by API Modes_LowPower sample code ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 2 4 4 f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e K 2 LABS Interrupt and PIT Lab Target Through this lab customer will learn how to configure a PIT and implement the interrupt service routine void initINTCf voidi Hints INTC MCR B HVEH UC Single core initializ INTC MCR BYTES Q Single core Use detfar INTC IACKR R uint32_t amp IntcIsrVectorTable 0 1 Reuse the sample code of CW INTC wdd sorter ionidi SWvector VLE NOTE DIVIDER FROM SYE PIT PITHCR R 0x00000001 7s nable PIT and c Integrate the LED PIT CH 1 LDVAL RF 64000 PITL timeout toaale code from PIT CH
57. SCLK bit field is allowed only for STOPO and TEST modes 0 1 a 4 5 T E E 10 14 12 13 14 15 R o o ofo o oo wo oo fo to foe fo o foe foe fa Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 94 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M freescale E invalid Mode Transition gt _ICONF bit in the Interrupt Status register ar WEEE E gt Five causes revealed by Inva v s m sa a _ a R a 0 ee JE A 2 gt Mode Transition Status regist Eee ft ete i w en er e a e Mode Transition Illegal ee i i i a Mode requested when a transitior ME_IS register is active i ToT Poe Te PsP tof fo stot Toto Mode Request Illegal oe a S E Target mode not valid respect to P o N Si oo ao 6 0 o o o current Disable Mode Access HEHE Target mode is disabled in Mode rnea TE ila aar a ar Enable Register E ME IMTS reaister Non Existing Mode Access arget mode doesn t exist SAFE Event Active Status Transition is requested when bit is pending Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc R
58. Semiconductor Inc reesca E Mode Configuration Register gt Each mode has a Mode Configuration register ME_XXX_MC where XXX is the mode e g RUNO HALT STOP etc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MVR reserved reserved ON DFLAON CFLAON 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PLL OSC IRC e PDO control pad driver output e MVRON control VREG on off e OSCON control XOSC on off e CFLAON DFLAON e IRCON control IRC16M on off control code data flash module e SYSCLK select system clock Normal Low Power Power Down e PLLON control PLL on off Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc v 83 N freescale Configuration Parameter MV DATA CODE R FLASH FLASH NORMAL NORMAL NORMAL OSC IRC vest oF on USER RESET on USER OFF RESET on m NORMAL NORMAL NORMAL 7 Z NORMAL NORMAL LOW POWER K E STOP mo POWER POWER DOWN DOWN oP on USER POWER POWER Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc
59. TEM MODES USER MODES RECOVERABLE HW FAILURE LOW POWER MODES SW REQUEST NON RECOVERABLE HW FAILURE feos a ae eee HW triggered transition gt SW triggered transition N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Ps Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 80 p freescale Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc oe LL System Modes Description gt RESET Virtual mode completely managed by HW e The flash initialization is executed while device in RESET gt DRUN Default RUN Mode automatically entered out of RESET or STANDBY This mode is used by the application to configure the device out of RESET or out of STANDBY gt SAFE e Mode automatically entered on recoverable HW failure detection like oscillator PLL or voltage failure e Device in a SAFE configuration with IRC output high impedance if configured so gt TEST Allow device self tests like flash checksum RAM BIST xy Freescale and the A a ogo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qor s a trademark of Freescale iconductor k l icond Inc ne
60. XXXX B1 value xxxxxx B2 captured SXXXXXX value A1 value xxxxxx Notes When the edge of the selected polarity is detected counter value is captured into A2 n and B2 n the data previously held in B2 n is captured into A1 n and B1 n and Flag is set Period is calculated by subtracting UCBn B1 from UCAn A2 Caution If period of input signal has spanned a counter bus period then need to take care to modify calculation Width UCAn Counter Bus Period UCBn Width A2 B1 Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 21 7 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M freescale E eMIOS Modes Modulus Counter Mode UP Counter Generates a time base which can be shared with other channels through the internal counter bases Can use Internal or External input channel pin counter Internal Counter UCCNTn 0x001000 0x000800 0x000000 FLAG pin f f f register i i pe A1 value 001000 001000 Of 000800 000800 A2 value 001000 i 000800 i t write update f A1 match into A2 of A1 A1 match A1 match
61. ad new code restore and save it into default SRAM configuration Figure 5 4 BAM logic flow Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor g Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 4 f 198 2 freescale Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc a E ES Serial Protocol From a high level perspective the download protocol follows these steps l Send 64 bit password 2 Send start address size of downloaded code in bytes and VLE bit 3 Download data 4 Execute code from start address Each step must be completed before the next step starts The communication is done in half duplex manner any transmission from the hostis followed by the MCU transmission Host sends data to MCU and starts waiting MCU echoes to host the data received Host verifies if echoes is correct If data is correct host can continue to send data If data is not correct host stops to transmit and MCU need to be reset Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org wo
62. aed s a trademark of Freescale Semiconductor Inc The Power Architectur and Power ales and the Pouer and Power n and related marks et arks a ogos elat emarks and service marks licensed by we f J i Power org All other produ vice n e the property of their respective own S 2005 2010 2011 Fre reescale Semiconductor Inc 4 f reesca e V Co Why 32bit Evolving software development methodologies e More structured software architectures engineered for reuse creating overhead Example AUTOSAR standardization adding about 10 15 performance overhead e Linear paged architecture and 32bit data handling allows for easier implementation of model based designs and autocoding e Scalability upwards allowing platform designs from low to high end systems e More affordable as technology shrinks the cost delta between 32bit and 16bit architectures reduces RY Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm sl raed s a trademark of Freescale Semiconductor rks r l Inc ne Powe r Ar Hiie aa and Power T T rks and the toed and Power bee and related marks Ni a and service marks licensed by gt f J Power org All other produ Ba vice n e the property of their respective own O2 2010 2011 a reesca le Semiconductor Inc 5 eo reesca V Cross Family Compatibility MPC563xM MPC560xP MPC560xB C MPC560xS Powertrain Airbag Steering Body Instrume
63. ames are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc K CGM System Clock Description gt Provides the clock divided or not to the Core Peripherals gt Selected by ME_XXX_MC register system_clk osca_clk osca_clk_div System irc_fast Clock div 1 to 15 Selector _irc_fast_div_ ME div 1 to 15 fmplla_clk div 1 to 15 Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 46 eF Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc freescale Peripheral Set Divider Configuration Register gt Peripheral Set 1 Peripheral Set 2 Peripheral Set 3 gt All LINFlex module PAIFIeXCAN SAI eMIOS modules modules gt All 12C modules gt All DSPI modules gt CTU O i gt c i z I oo CE OO T 0 0 E 0 0 i Oo i i F l Reset 9 0 o 0 a i DI 0 0 0 0 s x 1 a 24 25 26 27 26 29 30 Ji i fae EARN Dive of of o of o o o fo R Saeed en e OE Reset g 0 p 0 0 0 0 0 0 0 o 0 0 0 E 0 System Clock Divider Configuration Registers CGM_SC_DC0 2
64. and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 57 oF f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e NTC MPC560xB Software amp Hardware Vector Modes Address Instructions Address ISR Vector Table IVPRo 49 prolog Pere including using IACKR 2 Software to get vector then bl ISR n Vector Mode a Handler Branch Table Address Instructions Notes Hardware IVPRo 49 0x800 b handler_0 1 b handler_n instruction is technically part of the handlers Vector Mode b handler_1 2 ISR Vector Table alignment in software vector mode assu IVPRo 19 0x804 b handler_2 INTC_MCRIVTES 0 b handler_n IVPRo 19 OxOC8C Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 2 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 58 eF f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc P reesca e ee inte SW vs HW Vector Mode Handler Software Vector Mode jven o Hardware Vector Mode aven 1 HW HW Backs up machine state to SRRO 1 Backs up
65. are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc ry freescale K DOU LINFLEX Master mode bit error idle on bit error disable DRIE Pele Reception IOBE 0 DTIE 1 Completed Transmission Bit Error Reception Get Data l ERR Q l X RX wear baa fem r i E DRIE 1 BEIE 1 BEIE 1 Reception IOBE 0 DTIE 1 IOBE 0 Completed Trans Bit Error Rec Bit Error Get Data em X Aer RAX O oa oh header Doaa To Header Software can take appropriate action on bit error interrupt y Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 178 f E Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e N ae LINFLEX Overview Protocol Handler Slave mode only LINFlexO on Bolero Header and response E handling with minimum alia CPU intervention HEADER TxDATA oR Slave as publisher TRANSMIT RESPONSE Indication after reception of a correct identifier Boe RX Indication Indication Response Latency V N O RXDATA Response RARER bail RECEIVE RESPONSE TX Confirmation Transmissi
66. bee and related marks Ni a and service marks licensed by f J Power org All other produ Ba vice n e the property of their respective own O2 2010 2011 a reesca le Semiconductor Inc 113 reesca e cE VREG Power On Reset Main functions gt Works only on the rising edge of the main supply gt Used to mask all 1 2v controls signals during supply ramp gt POR levels 1 5v to 2 7v N Freescale and the Fre O e trademarks of Freescale Semiconductor Inc Sie E a a a rivva is a trademark of Freescale Semiconductor rks Inc ne Power Archilectur and Power T leis and the toed and Power bee and related marks Ap Ara and service marks licensed by f Power org All other produ Ba vice n e the property of their respective own O2 2010 GFE reesca le Semiconductor Inc 114 reesca e K Wakeup Unit Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 1 5 fre es C a e Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo Wakeup Unit The Wakeup Unit supports 2 internal sources WKUP 0 1 and up to 18 external sources WKUP 2 19 that can generate interrupts or wakeup events
67. c The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by f m Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e 4 M PC560xS S pect ru m System Crossbar Debug Integration Masters Family Overview we gt Auto and Industrial Target Applications i Instrument cluster and central display applications Oscillator Power i Architecture exus IDisplay control Puh e200z0h Display gt Display Control Unit as 16ch paves Control Enables direct drive of Quarter VGA and DOR Unit RGB Control WQVGA Interrupt __ ee Works independently of CPU to fetch process enie 1 and display graphics data directly from multiple t a sources Not just from Graphics RAM RCI Eels oh ATIC Don t need huge expensive graphics RAM Memory Protection Unit MPU Can move graphics data from external serial i via QuadSPI directly into RAM for DCU nee vs gt SSD is key for cluster Mgmt Bridge Graphics jj Serial Flash SRAM Needles calibrate themselves automatically eae L Low Power Design Module 4x 16EEE Crossbar Slaves Designed for dynamic power management of BAM core and peripherals Software controlled clock gating of peripherals Multiple power domains to minimize leakage in low power modes Communications 1 O System
68. car engine gt Airbag Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 2 ef f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e D Electric Power Steering Reference Design in Shanghai Auto Lab sp Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 3 e fre e S C a e Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M LSS Qorivva MPC560xP offers integration performance and reliability For industrial motor control AC drives and safety critical applications Supported by an extensive proven ecosystem of development tools software and design resources Exceptional performance with high Tea pga level of integration Ideal for safety critical applications Faster time to market Offers a rich set of real time
69. ck diagram Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc 129 2 Key Features of PCF Dual array interfaces support up to a total of 16Mbytes of Flash memory partitioned as two separate 8 Mbytes backs Single AHB port interface supports a 32 bit data bus All AHB aligned and unaligned reads within the 32 bit container are supported Only aligned word writes are supported Array interfaces support a 128 bit read data bus and a 64 bit write data bus for each bank Several prefetch control algorithms are available for controlling page read buffer fills Access protections may be applied on a per master basis for both reads and writes to support security and privilege mechanisms A KO freescale O Flash Prog Erase Operations AHB Crossbar Switch AHB ports 32 N otes 4128 Page Buffer 1x128 Page Buffer RWW is not supported in same Bank memory however supported in PFlash Controller different Ban ks All prog erase operations of Flash module are managed through the Flash User Registers Interface
70. d marks hetero ite and service marks licensed by f J u Power org All other produ a vice n e the property of their respective own E 2010 2011 na reesca le Semiconductor Inc 206 reesca e K Peripherals ADC conversion modes Normal conversion mode one shot mode or scan mode possible lt Sample Boo Convert B Sample Co Convert C gt lt Sample D _ Convert D lt Sample E Injected conversion mode lt Sample B gt lt Convert B 4 Sample C gt lt Convert C gt e Sample D 1 Conert D f 1 I Injected conversion of channels arr J Comet A e Convert J gt Hormal conversion resumes fran the last aborted channel The ongoing channel corversion is a and the injected conversion chain is processed first After the inched chain is converted the ronreil cameron resumes from the channel at which mamal conversion was abk t ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 207 f ra Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e K E Peripherals ADC analog watchdogs e The ADC support
71. d related marks Sie arks ogos emarks and service marks licensed by p f s Power org All other produ ie vice nam e the property of their respective own S 2005 2010 2011 Fre reesca le Semiconductor Inc 228 eo reesca e P CTU Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor i Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 229 fre es C a e Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo i Peripherals CTU Lite Purpose The Cross Triggering Unit Lite on the Bolero family is a link between timers eMIOS or PIT and the ADC The CTU Lite automatically transforms timer events into ADC conversions without main CPU intervention The real time behavior synchronization between timer events and ADC conversions is guaranteed N Freescale and the Fre PO e trademarks of Freescale Semiconductor Inc ie a olde rivva is a trademark o reescale Semiconductor Inc The Powe ee and Power o or marks a a eel and Power ces and related marks are tadema and service marks ns cal onductor Inc 230 freescale ee ogos Power org All other produ a vice nam e the property of their respective own 5 2008 2010 2011 Fre 4 OO P
72. d service marks licensed by Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc freescale Core e 40 60 and 80MHz options ON prenilecluicri2s e200z3 Core e Binary User mode compatible with RCPU MPC500 and e200z6 e New SIMD module for DSP and floating point features Memory 1 5M byte RWW Flash with ECC e 81k SRAM e 64k Data RAM also has 32K for standby with ECC e 17k for eTPU2 14k code amp 3k parameters I O Timed I O Channels e 32 channel eTPU2 8 additional reaction channels e 16 channel eMIOS with unified channels e 2 x FlexCAN compatible with TouCAN 64 32 buffers e 2x esCl e 2x DSPI 16 bits wide up to 6 chip selects each e Supporting Micro Second Bus e 34 channel Dual ADC up to 12 bit and less than 1us conversions 6 queues with triggering and DMA support e Variable Gain Amplifier X1 X2 X4 e Decimation Filter 4th order IIR or 8th order FIR with prog coeff e 4 pairs differentials inputs System e FM PLL e Junction temperature sensor e 32 Channel DMA Controller e 196 source Interrupt Controller plus NMI e Nexus IEEE ISTO 5001 2003 Class 2 eTPU2 Class 1 e Single 5V Power supply e EBI for calibration 16bit not pinned out of QFP e 144 LQFP package 32ADC e 176 LQFP package e 208 MAPBGA no bus 34ADC e 496 CSP Vertical Calibration Bus MPC5634M Powertrain e200Z3 core SI
73. d service marks licensed by Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc E E Code Flash Module Structure Code Flash composed of single blank with 912K Flash memory RWW is not supported Addressable double words 64bits for programming and page 128bits for reading 16 KB TestFlash is exists out side the normal address space and is programmed and read independently of other blocks The TestFlash is reserved to store the non volatile information about redundancy configuration and protection The 16 KB shadow section is presented to store user defined functions possibly to store boot code other configuration words or factory process codes The Flash module supports fault tolerance through Error Correction Code ECC or error detection or both The ECC implemented within the Flash module will correct single bit failures and detect double bit failure WO 125 freescale E Data Flash Module Structure High Read parallelism 128 bits Error Correction Code SEC DED to enhance Data Retention Double Word Program 64 bits HV generator e Sector erase Single bank Read While Write RWW not a available Program Erase Flash Bank 1 Controller Erase Suspend available Program Kbyte Suspend not available 16 KB TestFlash Flash Registers Software programmable program erase protect
74. duc e the property o fe espective own ects 2010 2011 Freesca le Semiconductor Inc 152 reesca a intc SOftware Vector Mode Interrupt Acknowledge Each core has an Interrupt Acknowledge Register IACKR valid for IVOR4 INTC exceptions in software vector mode e INCT IACKR PCRO INCT IACKR_PCRI1 e Reading this register acknowledges the interrupt has taken place and prevents the same interrupt occurring again e Reading IACKR also calculates and returns the address of the relevant Interrupt Service Routine based on reading the 32 bit address at VIBA ISR Offset Vector Table Base Address VTBA IACKR Contents of VTBA Interrupt ISR293 Ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 53 f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e M ntc Software INTC Interrupt Example MAIN Program IVOR4 Handler ISR VECTOR Table IVOR4 Interrupt i MSR updated ti from INTC 4 AI Prologue ISR293 Base Address IVPR Jump to ISR IACKR Contents of VTBA Interrupt Epilogue Jump to address in Prefix Reg
75. e Notes To achieve 0 duty cycle both registers A1 and B1 must be set to the same value To achieve 100 duty cycle the register B1 must be set to a value greater than the maximum value of the selected time base N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor PS Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by eF Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc 226 P freescale nn eMIOS Modes OPWMT Generates a PWM signal with a fixed offset and a trigger signal Intended to be used with other channels in the same mode with shared common time base This mode is particularly useful in the generation of lighting PWM control signals output flip flop i i Selected counter FLAG pin f t i t register i 0x001000 0x000600 0x000400 0x000200 bus B1 value 000200 000800 B2 value 000200 i i 000200 A1 value 000200 000200 000200 l l A2 value 000400 0040 000400 i i e A1 amp B1 write into Update A24 write no No B1 a e Notes match aie B2 of B1 Imatch match of B1 mac is Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat
76. e ae oon a e Checksum calculated automatically RECEIVE RESPONSE Master as subscriber Software configures ID Data length HEADER direction and request transmission Reception indication IGNORE RESPONSE ry Freescale and the Fre PO e trademarks of Freescale Semiconductor Inc a a pi rivva is a trademark of Freescale Semiconductor rks Inc a Powe eis a and Power pas ses i and the eel and Power o and related marks eas and service marks licensed by f m Power org All other produ ie vice nam e the property of their respective own S 2005 2010 2011 Fre reesca le Semiconductor Inc 176 reesca e K LINFLEX Master mode bit error idle on bit error enable value read back from the bus differs from the from the transmitted value DRIE BEIE 1 Reception IOBE 1 Completed Transmission Bit Error Get Data l Qax poate paar ch Reception Header BEIE 1 BEIE 1 IOBE 1 IOBE Trans Bit Error Rec Bit Error N ERR l X ERR Header 7 f i Header Communication stopped immediately Interrupt to notify bit error E Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 77 Power org All other product or service names
77. e in INTC MCR so one core can use SW Vector Mode and the other HW Vector Mode Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 149 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M freescale Interrupts SOftware Interrupt Vector Mode Structure Interrupt Requests from Interrupt Controller INTC Interrupt Requests from elected n 7 INTC in Software Vector Mode External Input CPU Core Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor ze Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 50 F f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc e reesca e ee interrupts Hardware Interrupt Vector Mode Structure The interrupt vectors are located on a 4KByte boundary Hardware vector mode has IVPR Interrupt Vector Prefix Register at a 2Kbyte offset f
78. e purpose of the FMPLL is to generate a 64 MHz max system clock from the FXOSC gt The FMPLL operating modes Power down Progressive clock switching e Normal e Normal with frequency modulation to reduce EMC gt These modes are controlled by two registers e Control Register CR e Modulation Register MR Ky Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm sl raed s a trademark of Freescale Semiconductor rks Inc ne Powe Archie aa and Power T T rks and the toed and Power bee and related marks Ni a and service marks licensed by f J Power org All other produ Ba vice n e the property of their respective own O2 2010 2011 a reesca le Semiconductor Inc 51 reesca e KA Ce CGM FMPLL Normal mode gt The PLL output clock frequency derives from the relation gt P gt Input Output divider divider FXOSC Phase CRF MIPLLL detector loop divider N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 52 f m Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e 9 CGM FMPLL Control
79. e trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 2 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 221 PF f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc e reesca e o M eMIOS Modes OPWMB Generates a simple output PWM signal Can use Internal or Modulus counter EDPOL allows selection between active HIGH or active LOW duty cycle output flip flop l EDPOL 1 Doo y e Selected coun ter B1 value 000800 B2 value 000800 A1 value 000200 000200 i A2 value 000200 i update of docs pe tat match B1 match A1 amp B1 e Write UCA n A1 with Leading Edge Write UCB n B1 with trailing edge e On Comparator A1 match Output pin is set to value of EDPOL e On Comparator B1 match Output pin is set to complement of EDPOL The transfers from register B2 n to B1 n and from register A2 n to A1 n are performed at the first clock of the next cycle FLAGS can be generated only on B1 matches or on both A1 and B1 matches depending on MODE 5 bit A1 match B1 match Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor
80. eMIOS_0 MCUPort SUPCR 1 Channel20 PES 68 2 Channel21 PES 6 SWITCH MCU Port SIU_PCR KEY 4 C57 C38 CSS CGO 0 1uF O 1uF ey 1 Configure SIU PCR n OluF li 4 INPUT SWITCHES ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 2 41 f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e K LAB2 System Clock Generation Lab Target Through this lab customer will learn how to generate the system Clock by FMPLL sourcing from external high frequency oscillator Hints 1 Configure the div 110 15 Peripheral ett ME RUN O Try these 3 sources OSC 8M PLL 64M Add the LED toggle code to easy check wT ia y div 1 to 32 div 1 to 32 CLKOUT ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 2 42 f m Power org
81. eescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 2 eF f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e 1 Qorivva MPC56xx Device Overview ty Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 3 freescale Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor P Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc SL What s a Power Architecture MCU An industry benchmark architecture very successful in embedded systems from automotive powertrain navigation systems to netcom applications A long term partnership between FSL and IBM The 32bit architecture of choice for FSL in automotive applications single issue multiple execution unit 32 bit RISC CPU Ww Freescale and the Fre een ie e trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm sl r
82. eg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by P f J u 95 Ireescaie Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc a Peripheral Clock Gating gt The Mode Entry Module manages the clock gating of each peripheral gt Define peripherals state active frozen in each mode 8 different types of peripheral behavior during running modes 8 different types of peripheral behavior during low power modes Ky Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm tal s a trademark of Freescale Semiconductor rks 3 Inc ne Powe Archie aa and Power T leis and the toed and Power bee and related marks one and service marks licensed by f Power org All other produ Ba vice n e the property of their respective own O2 2010 2011 a reesca le Semiconductor Inc 96 reesca e KA a RUN LP Configuration Registers gt ME RUN PC O 7 eee oe oe oe registers configure the behavior of peripherals during RUN Modes gt ME LP PC O 7 registers configure the behavior of peripherals during Low Power Modes gt Configuration bits RESET i o o ofo0 o o ofo o o 0 0 0 e ri p h e ral iS fro zen Low Power Peripheral Conf
83. eneration of Peripheral and Register settings Efficient C and Assembly code generation for a multitude of compilers like CodeWarrior Diab WindRiver and GreenHills e On line documentation and built in tool tips for MPC5500 Functional Settings ease of use i e Performs consistency checks to eliminate mistakes and inconsistencies e C code and Documentation templates customizable as a service e Supports multiple initialization strategy code generation iepr wa RA pp ID Compiler Linker o N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 27 f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e P Pr A MPC56xx Resources MPC560xB Product Page MPC5604BC XPCS60BEVBUM MPC5604B C Data Sheet XPC560BEVB User Manual AN2865 MPCs60XBCPB Example code MPC560xB C Family Product Brief AN3753 EB696 MPC551x to MPC560xB C SPC560Bx Cx New VLE Instructions for Improving Interrupt Migration Handler Efficiency AN3836 MPCS60XBFAMFS Advanced Headlights Control and Diagnostics MPC560xB Family Fact Sheet MPCs604BCRM BRFSLSFWTLAUTO M
84. eps Wait for operation completion wait for bit MCR DONE or UTO AID to go high 2 Check operation result check bit MCR PEG or compare UMISRO 4 with expected value 3 Switch off FPEC by resetting MCR EHY or UTO AIE 4 Deselect current operation by clearing MCR PGM ERS or UTO MRE EIE N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 31 j Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e K Static RAM Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 32 fre es C a e Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo ee SRAM Features The SRAM provides the following features SRAM can be read written from any bus master Byte halfword and word addressable ECC error correction code p
85. er response gt This mode is enabled by setting bit PLL _CR en_pll_ sw and then enabling the PLL by setting the bit ME_x MC PLLON mode mode FXOSC fe PLL ck PLL Ky Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm sl raed s a trademark of Freescale Semiconductor rks Inc ne Powe Archie aa and Power T T rks and the toed and Power bee and related marks Ni a and service marks licensed by f J Power org All other produ Ba vice n e the property of their respective own O2 2010 2011 a reesca le Semiconductor Inc 56 reesca CEET FMPLL Normal mode frequency modulation 1 3 Frequency ke i ae ee Center Spread FO Timo 27 pot Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 57 oF f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e Clock Monitor Unit CMU Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the
86. eripherals CTU Lite Features CTU features details 64 timer events Each timer event can be assigned corresponding ADC channel e Only one ADC conversion can be triggered at a time e HW arbitration when simultaneous event occur Event priorities are HW defined e Single cycle delayed trigger output The trigger output is a combination of 64 generic value input flags events connected to different timers in the system e Maskable interrupt generation whenever a trigger output is generated e One event configuration register dedicated to each timer event allows to define the corresponding ADC channel e Acknowledgment signal to eMIOS PIT for clearing the flag e Synchronization with ADC to avoid collision N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 231 f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e 9 Peripherals CTU Lite Block Diagram Channel valc Channel Value Select Hasana tae Trig63 TRGO oe TRG INT NEAT CMD Figure 252 Cross Triggering Unit block diagram ty freescale Freescale and the Freescale l
87. ernal safe clock 128KHz oscillator no other clock source can be selected The Watchdog can be configured to generate a reset or interrupt on an initial time out it will always generate a reset on consecutive time outs Programmable selection of window mode or regular servicing Hard lock by reset and soft lock by software of configuration y Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 74 f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e 3 Power Mode Control gt Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 75 p P f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc gt reesca e LN Power Control Overview e Mode Entry Control e Power Control Unit and Reset Generation Module e Wakeup Uni
88. es e One channel with High Speed transceiver e One channel with Low Speed Fault Tolerant and High Speed transceiver selectable with jumpers e 2 LIN channels with jumper enables e One with transceiver and pin header connector populated e One channel with footprints only e 1 SCI channel with jumper enables e 2 FlexRay channels with jumper enables e One channel with transceiver and DB9 male connector e One channel with footprint only e 4 user push buttons with jumper enables and polarity selection e 4 user LED s with jumper enables Daughter Card features potentiometer for analog voltage Input Can be used as a stand alone board by providing external 5V power supply input Evaluation Kit Contents e ON OFF Power Switch w LED indicator e One Motherboard e Reset button with filter and LED indicator e One Daughter Card e Debug ports 38 pin Mictor Nexus port and or e One XPC56xx Resources CD 14 pin JTAG port ROM e Direct clock input through SMA connector e Freescale Warranty Card footprint only e Jumpers for boot configuration C Low Cost Evaluation Kit Info Evaluation Board Summary and Features The evaluation system allows full access to the CPU all of CPU s I O signals and peripherals such as CAN SCI LIN eMPC5604B C Microcontroller in a 144LQFP package On board JTAG connection via open source OSBDM circuit using the MPC9S08JM microcontroller eMCZ3390S5EK system basis chip with advanced power management and integ
89. esca le Semiconductor Inc 41 eo reesca 3 System Clock Module Timer gt Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by p f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc gt reesca e ST CGM Clock sources gt Main Clock e 4 16 MHz External Crystal Oscillator gt FXOSC e 16 MHz Internal RC Oscillator gt IRC Default system clock at reset output DRUN mode Trimble gt Low Power Clock e 32 kHz External Crystal Oscillator gt OSC_ 32k Low power oscillator Dedicated for RTC API e 128 kHz Internal RC Oscillator Dedicated for RTC API and watchdog Optional clock for LCD driver in STANDBY modes Trimble Ky Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm sl raed s a trademark of Freescale Semiconductor rks 3 Inc ne Powe Archie aa and Power T leis and the toed and Power bee and related marks one and service marks licensed by f J Power org All other produ Ba vice n e the property of their respective own O2 2010 2011 a reesca le Semiconductor Inc 43 reesca e KA CE CGM PLLs gt
90. escale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 21 3 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc N CO eMIOS Modes Single Action Output Compare Generates an output on a counter bus match Can use Internal or Modulus counter Can set output to go HIGH LOW or TOGGLE based on the state of EDPOL and EDSEL output flip flop EDSEL 0 EDPOL 1 output flip flop EDSEL 1 EDPOL x selected ennnenn TS counter bus 000500 eee FLAG pin register 001000 write update GS W_ A into A2 of A1 tat match tat match tat match Notes Write the desired counter bus value to create a match into UCA n A2n which is buffered into A1 A comparator match of A1 results in an output event defined by status of EDPOL and EDSEL Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor 2 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by f u 214 freescaie N Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Se
91. fied in DSPI_MCR DCONF es ee CMD TX data Shift register gt lt SOUT_x x SIN_x S SCK_x SPI baud rate x CSO delay and transfer 4 A CS0 control oO C51 4x x CS5_x Figure 20 1 DSP block diagram N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor P lt Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 69 eF f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e al pspi Configuration of Master Slave Mode Selection of Master or Slave Mode Is made in the DSPIMCRIMSTR bitfield 0 Slave default 1 Master DSPI Master DSPI Slave SOUT SIN Shift Register gt Shift Register SCK SCK Baud Rate Generator Note PCSx to SS signal must be configured active low for slave mode operation N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor P lt Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 70 eF f J A Power org All other product or service names are the
92. gital 3 3v to 1 2v minimum PMOS Power power in 5 0v 10 up of 3 x STOP 10 to 15mA 330nF cap mode Ultral Low 1 2v digital 3 3v to 1 2v No NMOS Power power in 5 0v 10 up externally Regulator STANDBY 10 to 5mA capacitanc mode e needed W Freescale and the Fre O e trademarks of Freescale Semiconductor Inc Ses tiga tea A A rivva is a trademark of Freescale T uctor Inc The Powe ae ii and Power a ord marks a andthe and Power ac and related marks are trademarks and se ice marks sed by f m cale Semiconductor Inc 112 Treescaie a ogos Power org All other produ Sa vice nam e the property of their respective own 5 2005 2010 2011 Fre CETT oo oO VREG Low Voltage Detectors Main functions gt Low voltage detector for 5 0v operations on the main supply e Upper level 4 3 v max Lower level 4 2v min gt Low voltage detector for 3 3v operations on the main supply e Upper level 2 8v typ Lower level 2 7v typ gt Low voltage detector for 1 2v on the digital core supplies e Monitor 1 2v on main amp low power regulator in run or stop mode e Monitor 1 2v on ultra low power regulator in standby mode e Upper level 1 185v max e Lower level 1 095v min Ky Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm sl raed s a trademark of Freescale Semiconductor rks Inc ne Powe Archie aa and Power T T rks and the toed and Power
93. guration e Providing a SAFE mode to manage HW failure reescale and the Fre een ie e trademarks of Fre Inc The Powe arn eer cale Semiconductor Inc ape ery basalt apa s a trademark of Freescale Semicon arks Power org All other produ ne or and Power pee a rks and the and Power aie and relat arks emarks and service marks license 78 vice n e the property of their respective own 5 2008 2010 2011 Fre reescale Semiconductor Inc E A KO freescale LS Mode Overview gt Provide SYSTEM modes and USER modes e SYSTEM RESET DRUN Default RUN SAFE and TEST e USER RUN O 3 HALT STOP and STANDBY gt For each mode the following parameters are configured controlled e System clock sources ON OFF e System clock source selection Memory flash and RAM power mode ON low power power down Pad output driver state e Peripherals clock gated clocked e Power domains gt Control without CPU intervention the target mode s parameters and mode transition RY Freescale and the A a ogo are trademarks of Freescale Semic pim ctor Inc Reg U S Pat amp Tm Off mi s a trademark of Freescale Semiconductor Inc EN er Architectur and Power a E and the Pow and Power pees elated m et arks i gos andr arks emarks and service marks licensed by ae f J s Power org All other produc e the property o of tial espective o S 2005 2010 2011 Fre reescale Semiconductor Inc 19 f reesca e V Mode Flow Chart SYS
94. he Fre eae ee e trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm sl raed s a trademark of Freescale Semiconductor rks 3 Inc ne Powe Archie aa and Power T T rks and the toed and Power bee and related marks one and service marks licensed by f J Power org All other produ Ba vice n e the property of their respective own O2 2010 ee ae reesca le Semiconductor Inc 105 reesca TTT Reset functionality gt Destructive resets Power on reset e 1 2V low voltage detected power domain 0 or 1 e 2 V low voltage detected e Software watchdog timer gt Functional resets gt External reset Can optionally create an interrupt request or a e JTAG initiated reset t safe mode request Core reset t t Can optionally choose a short reset sequence Software resett e Checkstop resett e PLLO fail t e Oscillator frequency lower than reference t e CMUO clock frequency higher lower than reference t e 4 5V low voltage detected T e Code or data flash fatal error T Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 06 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc
95. heir respective owners 2005 2010 2011 Freescale Semiconductor Inc 118 WISA IT 0 Aising WIREEA I7 0 Falling WIFEER I7 0 Interrupt Edge Enable N A x 2 fre escale Non Maskable Interrupts External pin PA 1 GPIO 1 E0UC 1 NMI 0 WKUP 2 CPU The Wakeup Unit supports the generation of three types of mode interrupts from the NMI The Wakeup Unit supports the g 3 capturing of a second event per NMI input before the interrupt e F is cleared thus reducing the chance of losing an NMI event pan Each NMI passes through a bypassable analog glitch filter RL NMI Configuration Register NCR NWDSS px NMI Destination Source Select x Flag 00 Non maskable interrupt 01 Critical interrupt 10 Machine check request 11 Reserved no NMI critical interrupt or machine check request generated MWR E x NMI Wakeup Request Enable x Glitch Filter 1 A set NIF x bit or set NOVF x bit causes a system wakeup request O System wakeup requests from the corresponding NIF x bit are disabled x NMI Rising edge Events Enable x NWAEE x 1 Rising edge event is enabled 0 Rising edge event is disabled NMI Falling edge Events Enable x WrFEE x 1 Falling edge event is enabled O Falling edge event is disabled NMI Filter Enable x NFE X Enable analog glitch filter on the NMI pad input 1 Filter is enabled MI Configuration Register NCR O Filter is disabled NMI pad diagram NFE N Free
96. iconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 234 f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e STARTER TRAK MPC5604B MPC4S6048 LIN Connectors LEDs USB Connector Power Supply Sw itches Potentiometer MCZ3300S5EK System Basis Chip All Available Pins CAN RS232 Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 235 P f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e Starter TRAK TRK MPC5604B TI TTI Overview nee E i Lowe EH Sig ESB O z Power Jack 9 12V LED USB On Boaro PD 4 7 Push Button PD 0 4 CAN Connector FA ADC PE 0 MCU FOO als 4 MPC5604E us CO jet cee wasn O Oe T omaso FO ole oal O CULE TETL CE ONAIN AI DIANANI Lt GST_EM Jat Solon O z EITA RS232 Connector pf N Freescale and the Freescale logo are trade
97. iconductor Ps Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 38 p freescale Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc oo COON SIUL GPIO Functionality gt SIUL manages accesses GPIO pads both e On individual base R W access to a single GPIO Access is done on a byte basis e On port base parallel access gt Ports accesses can be Data Read 32 bit 16 bit or 8 bit accesses e Data Write 32 bit only if not masked access 16 bit or 8 bit Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 39 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc WO freescale SIUL External Interrupt Management PAD Control PCR Regs PSMI Regs GPIO functionality Data Pad Inputs Ext Interrupt Mgmt Interrupt e Interrupt config Controller e Glitch filter N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off
98. iguration Registers ME LP PC0 7 with clock gated e 1 peripheral is active Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 97 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc X freescale COO o Peripheral Control Registers gt ME PCTLI O 143 registers select the Running Low Power Mode configurations for each peripheral WE a Peripheral Control Registers ME_PCTLO 143 gt DBG F bit controls the state of the peripheral in Debug Mode 0 peripheral status depends on LP_ CFG RUN CFG 1 peripheral is frozen gt LP CFG bits specify a Low Power Mode configuration as defined in ME_LP PCs 000 select the ME LP PC O configuration 111 select the ME_LP_PC 7 configuration gt RUN CFG bits specify a Running Mode configuration as defined in ME_ RUN PCs 000 select the ME_ RUN_PC O configuration 111 select the ME RUN_PC 7 configuration Ky Freescale and the A a ogo T ademarks of Freescale Semic pim ctor is Reg U S Pat amp Tm Off Qor s a trademark of Freescale Semiconductor k r l Inc ne Power Architectur Ha Po owe T T marks and the Po
99. ion to avoid unwanted writings Censored Mode against piracy Not usable as main Code Memory of the Matrix gl i Interface Nite Ms device Shadow Sector not available Fi 20 26 Flash module struct aiak e a One Time Programmable OTP area in Test Flash block Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor oS Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 6 P freescale Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc oo nee Code Flash Sectorization Bank 0 of the Flash module 1s divided in 10 sectors including a reserved sector named TestF lash in which some One Time Programmable OTP user data are stored as well as a Shadow Sector in which user erasable configuration values can be stored The matrix module sectorization 1s shown in Table 19 1 Table 19 1 Flash module sectorization ce ae meem Ys ne 22 eor wonton aa au os Sas BO BOF1 OOKOO0 Ox0t 16 Low Address Space BO BOF O0x00C000 0x00FFFF Low Address Space BO BOFS 0x010000 0x017FFF Low Address Space POTEO DDN FEFA Cow Aase Sac BOFS 0x020000 0x03FFFF 128 lt Low Address Space 0x040000 0x05FFFF 128 Kbyte Mid Address Space BOF7 0x060000
100. ister IVPR offset of 0x40 for IVOR4 Note MSR is updated based on current exception For CE ME and EE are also disabled EE External Exceptions All IVOR4 are EE ME Machine Exceptions CE Critical Exceptions Incl Watchdog Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 5 4 oF f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e i _ i s intc SOftware INTC Interrupt Example MAIN Program IVOR4 Handler Prologue Jump to ISR ISRn Context Save Context Restore Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor g Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by Y f 155 2 freescale Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc E intc Hardware Vector Mode Details In hardware vector mode IVOR4 is not used
101. itch a aa Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor p Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 91 f l ra Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e K D Crossbar Switch XBAR The purpose of the XBAR is to concurrently support up to eight Simultaneous connections between master ports and slave ports Each slave port can support multiple master priority schemes Each slave port has a hardware input which selects the maser priority scheme so dynamically change master priority levels on slave port by slave port basis FUTE teh ARAR DIOTE OEN XBAR supports a 32 bit address bus width and a 32 bit data bus width at all master and slave ports Crossbar Switch Slave modules Internal Peripheral SRAM bridges Table 15 1 Master Slave mappings Physical master ID Internal SRA Peripheral bridge N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 2 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are
102. j BoC BEL ei Fi knh ch Mha Freen es raam ee arg Received CANO LE SET Uo FFE New r i kT ufe ata i HA Bh FERE Bid 77 H ee Fou G5 s FF i ru EIR eB B ri D H ar EIT ce Lo ETENN Ene FEA ela ETETA wI Ho HIMNE FFF DARAN th FFFGI in ujaj FFFE P FE ae u FRG IK aed s x EE ee 3 is oe E PATAWA Besa TA a BI z E BERUSRRIIRIEZ F i Eg FF FERE T FEFEFE CA E Bai dil ial a ae Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 2 46 esf f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e LLL Lo LAB7 ADC EMIOS Lab Target Through this lab customer will learn how to capture ADC input and generate PWM signal with EMIOS Hints 1 Configure ADC for ft de SOON E scarey j Connect J30 2 ADC channel to P2 5 Toggle LED1 according to ANP for variable voltage ADC input 0 0x3FF Precise J30 2 is pin nearest W1 TUE ANALOG INPUT Watch EMIOS PWM output 2 counts signal on LED2 LED3 Tr to enerate center ANS SH AM AE MA EFO AR Bie EPO BR sau eH
103. l other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo a Power Control unit gt The MCU peripherals are allocated to various power domains gt The PCU allows users to remove or apply power to a power domain depending on the operating mode This is used to optimise power saving gt Each time the MCU changes mode the PCU Evaluates the required status of each power domain e Provides controlled power up or power down of the power domain if required gt Only one power domain 2 can be controlled by the PCU Power domains 0 amp 1 are not controllable gt A status register indicates the current state of each power domain Ky Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm sl raed s a trademark of Freescale Semiconductor rks r l Inc ne Powe r Ar Hiie aa and Power T T rks and the toed and Power bee and related marks Ni a and service marks licensed by f J Power org All other produ Ba vice n e the property of their respective own O2 2010 2011 a reesca le Semiconductor Inc 101 reesca VREG Supply and Regulator Diagram VDD_HV E k i HEBE 330nF T 330nF E 330nF HEE _ AVDD_HV _ AVDD _REF L _VDD_HV DOMAIN 2 STBY _ _ PA O Pa KACER aA A 24KRAM j J Px y Low Volt Detector DOMAIN 0 STBY eV DD LAV Pcjo 8KRAM RGM IRC PC 1 Wake
104. le To achieve 100 duty cycle A1 n must be set to 1 To achieve 0 duty cycle A1 n must be set to a value greater than the maximum value of the selected time base e Caution The internal counter should not reach 0 as consequence of a rollover N Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 224 f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc e reesca Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor px o M eMIOS Modes OPWMT Generates a PWM signal with a fixed offset and a trigger signal Intended to be used with other channels in the same mode with shared common time base output flip flop Selected counter This mode is particularly useful in the generation of lighting PWM control signals I EDPOL 1 i FLAG pin i f i register B1 value 000800 000800 ma 000200 B2 value 000800 _ A1 value 000200 000200 000200_ A2 value ee i o0p400 i 00 400 000400 oe Be B1 A24 write Update A2 B1 Notes match seule match ee match ied of B2 match Imatch A1 n defines the Leading Edge B1 n the trailing edge A2 n the generation of
105. le Semiconductor g Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by Y f 181 lt 2 freescale Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc FlexcAN Features FlexCAN Module Features e CAN module which supports both CAN A and CAN B specifications 64 message buffers per module Filters for receive message buffers Message buffers and errors can cause interrupts Programmable loop back for self test operation e Can wakeup on bus activity using FlexCAN input pins through CRP Wakeup internal to FlexCAN is not supported Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 82 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M freescale FlexcAN Architecture with FlexCAN 20 64 Transmit Receive Message Buffers fa Tx Shifter BUFFER 13 Rx Shifter gt ae CANRx Transparent to user ie BUFFER 14 l BUFFER 15
106. ll wrap at the maximum counter value FFFFFF before matching A1 NY Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 220 f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesCca e Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor N eMIOS Modes OPWMFEMB Generates a simple output PWM signal Requires INTERNAL Counter EDPOL allows selection between active HIGH or active LOW duty cycle output flip flop EDPOL 0 output flip flop EDPOL 1 Selected counter bus 0x001000 0x000800 0x000200 B1 value 001000 A1 value 000200 000200 A2 value 000200 i A update tat match B1 match of A1 A1 match 181 match Notes e Duty Cycle UCA n A1 1 Period UCB n B1 1 e On Comparator A1 match Output pin is set to value of EDPOL e On Comparator B1 match Output pin is set to complement of EDPOL and Internal counter is reset The transfers from register B2 n to B1 n and from register A2 n to A1 n are performed at the first clock of the next cycle FLAGS can be generated only on B1 matches or on both A1 and B1 matches depending on MODE 5 bit N Freescale and the Freescale logo ar
107. lock Configura factors status in on off available ble start range from STANDBY controlled interrupt up time 1 2 3 32 Mode by Mode Entry FXOSC Yes N A Yes Yes Yes Yes Yes 4 16MHz SXOSC Yes N A Yes Yes Yes Yes Yes 32K FIRC Yes 1 Yes Yes No No No 16MHz SIRC Yes 1 Yes No No No 128K Note Control SIRC_128K state ON OFF in only availabel in STANDBY Mode In all other modes e g RUN HALT the SIRC is always ON 3 N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 49 f ra Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e K Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 50 f a Ireescaie Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc a CGM Frequency Modulated PLL FMPLL gt Th
108. machine state to SRRO 1 Disables interrupts except CE ME DE Disables interrupts except CE ME DE Takes External Input Interrupt based on Takes unique IRQ vector based on IVPR IVPR and offset 0x40 for IVOR4 and offset which matches INTVEC SW Prolog SW Prolog Saves SRRO 1 Saves SRRO 1 Reads INTC_IACKR INTVEC Re enables MSR EE Re enables MSR EE Saves other registers Saves other registers SW SW ISR clears interrupt flag SW ISR clears interrupt flag SW Epilog SW Epilog Executes mbar to ensure IRQ flag cleared Executes mbar to ensure IRQ flag cleared Restores most registers Restores most registers Disables EE and writes to INTC _ EOIR Disables EE and writes to INTC_EOIR Restores remaining registers and returns rfi Restores remaining registers and returns rfi V Freescale and the Fre a pee e trademarks of Freescale Semiconductor Inc pie U S Pat amp Tm sand s a trademark of Freescale Semiconductor rks Inc ie Powe Adhie aa and Power pas ses rks and the eel and Power o and related marks hetero ite and service marks licensed by f i u Power org All other produ pe vice n e the property of their respective own 5 2005 2010 2011 Fre reesca le Semiconductor Inc 159 gt reesca E M LL Interrupts Hardware Vs Software What are the advantages disadvantages of HW and SW interrupts Software Conforms to Power Architecture minor poin
109. marks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 236 f ra Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e D Hardware Setup USB Qorivva Multilink gt If the USB Qorivva Multilink is used eee rn ara d Batteries ES Bluetooth Devices P Computer E8 ControMault Device Sg Disk dives i B Display adapters lk DYDYCD AOM drives Fig Human Interface Devices nS IDE ATAZATAPI controllers Fl IEEE 1394 Bus host controllers ER Jungo 2 BB USE Multilink 2 0 Win Driver Hip Keyboards E t Mice and other pointing devices oe Monitors E Network adapters ee PCMCIA adapters T is ph ae F C s aS a The USB Multilink 2 0 device can be found in your computer device list H Ports COM amp LPT ee Processors rE SCSI and RAID controllers E Smart card readers H Sound video and game controllers Universal Serial Bue controllers fe System devices Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor ao Inc The Powe
110. miconductor Inc eMIOS Modes Double Action Output Compare Generates an output pulse Can use Internal or Modulus counter Polarity of pulse is determined by value of EDPOL output flip flop MODE 0 1 EDSEL 0 EDPOL 1 selected annncn V counter bus 000500 FLAG pin register A1 value xxxxxx B2 value 001100 write into update of A2 amp B2 A1 amp B1 tat match t B1 match tat match t B1 match tat match Notes Write the desired pulse leading edge into UCA n A2n and the falling edge into UCB n B2n which are buffered into A1 and B1 On a comparator A match the output is set to the value of EDPOL FLAG is set if MODEO 1 On a comparator B match the output is set to the inverse of EDPOL FLAG is set Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 2 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 21 5 P Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc freescale N i O O Input Pulse Width Measurement Determines the width in counter bus clock ticks of an input pulse width Can use Internal or Modulus counter Can be configured to measure HIGH or LOW pulses by state of EDPOL
111. names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc LT Communication Modules DSPI LINFlex FlexCAN IIC o e o e o e Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 6 5 e fr e e S C a e Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo DSPI Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor i Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 66 fre es C a e Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo To psp Features High speed full duplex three wire synchronous interface Master and slave modes supported Six Peripheral Chip Selects e Expandable to 64 with external demultiplexer e Deglitching support of up to 32 chip selects when external mux used SPI Queue support Buffered t
112. nt Cluster System Crossbar Masters Debug System Crossbar Masters System Crossbar Masters Debug System Crossbar Masters i mae Integration Integration Integration ie FMPLL e E Ready A ba CROSSBAR SWITCH CROSSBAR SWITCH CROSSBAR SWITCH CROSSBAR SWITCH Fy Crossbar Slaves Gieesballslanes Crossbar Slaves Crossbar Slaves ee Communications I O System Communications I O System Communications O System eT l 32 bit standard architecture adopted across all product families gt Maximum IP reuse gt Faster time to market gt Reduced risk gt Leverage software and tools investments Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc _ freescale O A K gt Family Overview gt Targeted at mid range complex control and diagnostic applications such as central body gateway and comfort gt FlexCAN module supporting both FIFO and mailbox data storage ideal for Controller Area Network CAN gateways to manage event driven vs periodic bus traffic gt LINFlex module provides a fully automated Local I
113. nterconnect Network LIN message management reducing CPU load intervention and message latencies gt eMIOS timer combines multiple counter sources to input capture output compare and PWM capabilities in one very flexible module PWM function supports shifted signal output to improve EMC gt Cross Triggering Unit CTU synchronizes PWM output signals with analog to digital conversions gt Enables very accurate diagnostic and control capabilities Family Differences Device MPC5604B MPC5603B MPC5602B Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 7 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc MPC560xB C Body Electronics System Integration Crossbar Masters Debug VReg MCM JTAG muse Power Mgt pee Oscillator Core Nexus 2 FMPLL Interrupt Controller i CROSSBAR SWITCH Memory Protection Unit MPU a a l Standby RAM Boot 32K SRAM Module Crossbar Slaves Communications I O System eMIOSLite 36 Ch CTU ch IC OC ADC 50ch PWM 10bit t 7 t 4 3 4 3 1 FlexCAN LINFlex DSPI I2C Note block diagram represents the MPC5606B Flash SRAM SCI LINFl GAN
114. o transfer once then only as a response to frame always Overrun 2nd frame rec d before CPU read 1 frame Data frame will transfer only as a response to remote frame 0101 0010 An empty buffer was filled mo f oo A full overrun buf was filled Before buffer codes Host CPU writes commands After buffer codes Reflects the status of that buffer Fields ignored when using standard frames IDE 0 N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor oa Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 84 eF f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc e reesca FlexcAN CAN Error Detection Bit Error Detected by a transmitter if the bit value received is different from the bit value transmitted Exceptions sending a recessive bit and receiving a dominant bit during the Arbitration Field or the Ack Slot or during a Passive Error flag Stuff Error Detected by a receiver if 6 consecutive bit values are received during a message field that should be encoded by bit stuffing CAC Error Detected by a receiver if the CRC calculated by the receiver is different from the CRC received in the CRC Sequence field
115. od Measurement Double Action Output Compare Output Pulse Width and Frequency Modulation Buffered Genter aligned Output PWM Buffered with dead time Output Pulse Width Modulation Buttered Output Pulse Width Modulation Trigger Ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 21 2 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc KA freescale E eMIOS Modes Single Action Input Capture Returns the value of the counter bus on an edge match of an input signal Can use Internal or Modulus counter Can match on Rising Falling or Toggle determined by state of EDPOL EDSEL Edge Edge Edge detect detect Input signal counter bus 8000500 FLAG pin register A2 captured es value Notes Example with detection on rising edge When edge is detected flag is set and counter bus value is captured in register A2 User reads this value from UCA n register e UCB n Cleared and cannot be written freescale iy Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Fre
116. ogo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 932 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc K aaa MPC5602 3 4B eMlIOS260 OPWMT Trigger event eMIOS AO ChO Trig ADC Control eMIOS A23 Ch23 Trig ADC Trigger eMIOS BO Ch29 Trig i ADC Done eMIOS B23 Ch52 Trig PIT3 Ch28 Trig Ss Injection trigger PIT2 _ A Aai6aq A N xcvwmei gt wwwwwwre Scum oo 4 gt uquouooH _ _ _ Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor i Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 933 oF f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e 10 Hands on Workshop Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Sem
117. omotive Platform Product Package Code 56 PPC in 90nm B Body LL 100 LOFP iaka anand eae lel 57 PPC in 65nm C Gateway LO 144 LOFP 57 PFC in 65nm C Gateway LQ 144 LQFP MG 208 MAPBaa LU 176 LQFP Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 2 4 p fr e e S C a e Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo 55xx 56xx Power Architecture Tools Support Evaluation es Boards os af le aXiom Reference freescale Designs semiconductor MANUFACTURING SERVICES cul MCAL F lt p imal A ese i Green Hills SOFTWARE INC LAUTERBACH 7N Compilers Qe M q DEVELOPMENT TOOLS te Simulators wl lh P bca fre e SC a e Debuggers Sree Ta PER WIND RIVER L semiconductor will i f F Stacks ao reen Hills l KA Als Drivers ot SOFTWARE INC Translators z fr eescale Init Tools semiconductor WIND RIVER r P eTPU pes n Tools freescale semiconductor a eC Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of F
118. on confirmation Reception indication Indication e 8 optional identifier filters for automatic reception HEADER IGNORE RESPONSE Ry Freescale and the Fre mais ogo are trademarks of Freescale Semiconductor Inc pie U S Pat amp Tm sand s a trademark of Freescale Semiconductor rks i Inc e Powe eis a and Power a eae rks ardire tad and Power abe and related marks a and service marks licensed by f Power org All other produ ee vice n e the property of their respective own ects 2010 2011 aes reesca le Semiconductor Inc 179 reesca e a ae LINFLEX Overview UART mode Mode e Full Duplex e 8 bit 9 bit e Even Odd parity Transmit Buffer eee Ta Receive Buffer e Depth configurable from 1 to 4 Error e Parity e Overrun LIN TX LIN RX ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 80 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc freescale K LT Communication Modules FlexCAN Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freesca
119. operty of their respective owners 2005 2010 2011 Freescale Semiconductor Inc KA freescale Hands on Demos Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 239 f E pem Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesCca e K LS Hands on Demos SIUL GPIO System Clock Generation a Mode Transition Demo 0 Low Power Mode o A Interrupt and PIT FlexCAN Lookback RAppID ADC EMIOS N amp Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 240 eF f E pram Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e LAB1 SIUL GPIO Lab Target Through this lab customer will learn how to configure a PIN to GPIO and to read write the I O status Base of the rest labs LED
120. or Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Boot from FlexCAN Table 5 8 FlexC AN boot mode download protocol Host sent message nam TR message CAN ID 0x011 CAN ID 0x001 Password checked for validity and compared against stored amp l bit password 64 bit password password CAN ID 0x012 CAN ID 0x002 Load address is stored for future use 32 bit store 32 bit store size of download are stored for future use address VLE address VLE Verify if VLE bit is set to 1 bit 31 bit number of bt 31 bit number of bytes bytes CAN ID 0x013 CAN ID 0x003 6 bit data are packed into 32 bit words These words are 6to 64 bits of raw amp to 64 bits of raw saved into SRAM starting from the Load address binary data binary data Load address increments until the number of data received and stored matches the size as specified in the previous step Branch to downloaded code Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 201 eF f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e 9 ADC CTU EMIOS
121. p platform rpp_z0h_ref Features MPU provides hardware access control for all memory references generated in the device Core z0hn1 or zOhn2p Support for 8 program visible 128 bit region descriptors Support for 3 AHB slave port connections flash controller system RAM controller and IPS peripherals bus Global MPU enable disable control bit provides a mechanism to easily load region descriptors during system startup or allow complete access rights during debug with the module disable Figure 14 1 MPU block diagram q Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 135 PF f J Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e ECC Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 41 T f a Ireescaie Power org All other product or service names are the property of their respective
122. produ Ba vice n e the property of their respective own O2 2010 2011 a reesca le Semiconductor Inc 92 reesca e KA TT Interrupt Management gt The mode entry can generate interrupts on the following events Invalid mode event Mode configuration Mode transition e SAFE Mode transition event on HW request e Mode transition event complete gt Each interrupt flag can be masked independently Ny Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm tal s a trademark of Freescale Semiconductor rks 3 Inc ne Powe Archie aa and Power T leis and the toed and Power bee and related marks one and service marks licensed by f Power org All other produ Ba vice n e the property of their respective own O2 2010 2011 a reesca le Semiconductor Inc 93 reesca e KA E Invalid Mode Configuration gt Caused by writing ME_ lt mode gt _MC registers with invalid mode configuration gt ICONF bit in the Interrupt Status register ME_IS gt To avoid invalid mode configuration event IRC should be ON if sysclk rc_clk or sysclk rc_clk_div XOSC should be ON if sysclk osc_clk or sysclk osc_clk_div PLL should be ON if sysclk pll_clk Configuration 00 for the CFLAON and DFLAON bit fields should not be used MVR must be ON if any of the following is active PLL CFLASH DFLASH system clock configurations marked as reserved may not be selected Configuration 1111 for the SY
123. property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e LINFlex Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 71 TY fre es C a e Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo LINFlex Features e Supports LIN protocol version 1 3 2 0 2 1 and J2602 UART mode 7 8 bit data parity no parity 1 or 2 stop bit eae SCI LIN LSB first LIN Management Transnver Shit Register Recener anm Regine e initialisation Normal and Sleep e Maskable interrupts Wake up event on dominant bit detection e 8 bit counter for time out management al Receive Software efficient data buffer interface mapping at a unique address cane space s LIN Master Mode Autonomous message handling Once the software has triggered the header transmission no further intervention needed until the next header transmission request in transmission mode l until the checksum reception in reception mode Ei loentiner LIN Slave Mode only LINFlex0 on Bolero is capable of slave mode poate fay Om h E Software intervention needed only
124. property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e ee Memory Map Table 1 4 shows the memory map for the MPC5604B All addresses on the MPC5604B including those that are reserved are identified in the table The addresses represent the physical addresses assigned to each IP block Table 1 4 Memory map 2 a 6 2 Oxo 28 0x00060000 Code Flash Sector N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Ps Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 22 eF f i Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc Yd reesca e Flash Memory Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 23 fre es C a e Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo COO O Flash Memory Architecture The Flash memory comprise
125. r Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 237 esf f na Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e Le Hardware Setup TRK MPC5604B File gt If the TRK MPC5604B board is used Acton Wiew Help E ir Batteries HEJ Bluetooth Devices w Computer H E ControWault Device S Disk drives B Display adapters H 5 OYOACO AOM drives E Human Interface Devices H IDE ATAZATAPI controllers The BDM JM60 LibUSB Win32 ee device can be found in your computer e i i a Open source BOM JMBO LIBUSB W 32 device list Mice and other pointing devices i E 3 Monitors gt The on board Embedded OSJTAG is E8 Network adapter l H E PCMCI4 adapters H Ports COM amp LPT available tan H SCSI and RAID controllers il AA Smart card readers E Sound video and game controllers El l System devices re Universal Seral Bus controllers Ry Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 238 Power org All other product or service names are the pr
126. r org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e BAM a Daa aaa Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor i Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 9 4 fre es C a e Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo ey Boot Mode Selection Notes Two boot modes are supported POR The gray modules are done by hardware automatically Single Chip boot from the first a a aera bootable section of the Flash main array Sarnal Boot SBL LIN Flax Serial Boot download boot code from either LINFlex or FlexCAN oe interface and then execute it Sarial Boot SBL FlexCAN Flash Boat ID Jin any boot sector Table 5 2 Hardware configuration to select boot mode no Boot ID i Standby RAM boot flag T a a a E e Boot ID Boot mode Static Mode N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Po
127. r service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e K Peripheral Bridge PBRIDGE is a interface between system BUS and on chip peripherals PBRIDGE on MPC560xB is a hard wired implementation not software configurable System Bus Crossbar Switch ABAR Peripheral The PBRIDGE generates module Bridge enables the module address transfer PBRIDGE1 attributes byte enables and write data as inputs to the slave peripherals The PBRIDGE captures read data from the slave interface and drives it on the system bus The PBRIDGE occupies a 64 MB portion of address space The register maps of the slave peripherals are located on 16 KB boundaries Fiqure 13 1 PBRIDGE Interface et The PBRIDGE is responsible for indicating to slave peripherals if an access is in Supervisor or user mode Peripheral Bridge PBRRIDGEDO system Bus stem Bus NPC5607B N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 2 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 190 PF f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e Crossbar Sw
128. ransfers using 4 deep Tx FIFO and 4 deep Rx FIFO e FIFO visibility for debugging 6 Interrupt conditions Ry scale and the Fre mais ogo are trademarks of Freescale Semiconductor Inc pie U S Pat amp Tm sand s a trademark of Freescale Semiconductor rks Free l Inc ne Powe r Ar Hiie aa and Power a eae rks and the tad and Power abe and related marks ot a and service marks licensed by f Power org All other produ ee vice n e the property of their respective own ects 2010 2011 aes reesca le Semiconductor Inc 167 reesca e KA COON o DSPI Configurations Serial Peripheral Interface SPI Configuration Operation as basic SPI or Queued SPI using internal FIFOs Programmable transfer attributes on a per frame basis Serial clock baud rate polarity and phase Frame size 4 to 16 bits Various programmable delays Chip Select Up to 6 and continuous hold capability Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 68 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M freescale O psPi Confiaurations Block Diagram INTC DSPI Configuration of SPlis speci
129. rated CAN transceiver eCAN amp LIN Interface eAnalog Interface with potentiometer eHigh efficiency LEDs eSCI serial communication interface pane i ag 9 Evaluation Kit Contents u a eT RK MPC5604B Board TRK MPC5604B DVD ROM a mat eter A includes CodeWarrior software See ol ja e eUSB A to B Cable po Freescale Warranty Card IA SNC Hh 8 O n E WS gt A A arti sa 1 N a ote CE oN ray MPCBOOd n an MPC560xB Part Number Information MPC5604B Part Diagram MPC5607B Part Diagram Example code M PO 56 0 4 B E M LL AR Example code PC 56 0 7 B M LL R Qualification Status l Qualification Status PowerPC Core PowerPC Core Automotive Platform Automotive Platform Core Version Core Version Flash Size core dependenti Flash Size core dependent Product Product Optional fields Optional fields Tamperature spec Temperature spec Package Code Package Code A Tape amp Reel blank if Tray R Tape amp Reel blank if Tray Qualification Status Flash Size z0 core Temperature spec Qualification Status Flash Size z0 core Temperature spec M MC status 2 256 KB C 40 to 85 C M MC status 3 768 KB C 40 C to 85 C 5 Auto qualified 3 984 KB V 40 to 105 C 5 Auto qualified 6 1024 KB V 40 C to 105 C P PC status 4 519 KB M 40 to 125 C F PC status 7 1 5 MB M 40 C to 125 C Automotive Platform Product Package Code Aut
130. rd marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 99 f l i ra Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e K Boot from UART Table 5 7 UART boot mode download protocol nn BAM response Host sent message ae message 64 bit password 64 bit password Password checked for validity and compared against MSB first stored password 32 bit store address 32 bit store address Load address is stored for future use VLE bit 31 bit VLE bit 31 bit Size of download are stored for future use number of bytes number of bytes Verify if VLE bitis set to 1 MSB first MSB first 6 bits of raw binary 6 bits of raw binary amp bit data are packed into a 32 bit word This word is data saved into SRAM starting from the Load address Load address increments until the number of data received and stored matches the size as specified in the previous step Branch to downloaded code fep Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by oe Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc 200 eo freescale Freescale and the Freescale logo are trademarks of Freescale Semiconduct
131. reesca e KA 8 System Related Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 87 f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e K LL System Related Peripheral Bridge Crossbar Switch BAM Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 8 8 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc freescale K Peripheral Bridge a aa Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor p Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 89 f l ra Power org All other product o
132. reescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 2 5 oF f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e 55xx 56xx Power Architecture Tools Support ts ap Tae Z freescale CodeWarrior XATA Ses acon LAUTERBACH AM ry lt n DEVELOPMENT TOOLS H l F Professional WIND RIVER ST _ Gree AUT OOSAR sorrware ince WW aShWare com semiconductor Zz CodeWarrior 2 freescale Special Edition semiconductor gt N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 26 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc freescale RAppID Time to Market Improvement for the MPC560xB C P M S Family RAppID application initialization and m documentation software e Comprehensive Initialization of MPC560xB C e GUI based tool for easy and fast development of initialization code e Automatic report g
133. rks and service marks licensed by 72 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor freescale Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor TID Watchdog Introduction Watchdog is used to provide a system error recovery function e g from software loop traps or failing bus transaction Software must periodically write a servicing sequence prior to the next expiration of the watchdog timer interval to avoid reset or interrupt by watchdog Writing the sequence resets the timer to the specified time out period Programmable selection of window mode or regular servicing The MPC560xB watchdog resides in the Safety Module Watchdog is default enabled e Default Watchdog is enabled e Can be disabled by default by programming WATCHDOG EN Bit in NVUSRO Register Bit 31in Shadow Flash N Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 73 P freescale Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc Ct Watchdog Feature List 32 bit time out register to set the time out period The SWT counter clock is the undivided clock provided by int
134. rks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 54 f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca CGM FMPLL Power down mode gt The power down mode is controlled by the PLLON bit in every Mode Entry mode configuration registers ME x MC In this mode the PLL reach its lowest current consumption and of course does not provide any clock mode mode FXOSC fe PLL ck PLL Lf d ME_x MC PLLON Ky Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm sl raed s a trademark of Freescale Semiconductor rks Inc ne Powe Archie aa and Power T T rks and the toed and Power wee ogos and related marks Ni a s and service marks licensed by f J Power org All other produ Ba vice nam e the property of their respective own O2 2010 2011 a reesca le Semiconductor Inc 55 reesca e KA CONN CGM FMPLL Progressive clock switching mode gt Progressive clock switching allows to switch FXOSC input clock to PLL output clock stepping through different division factors This means that the current consumption gradually increases and so the voltage regulator has a bett
135. rom the software mode IVPR IVPR 4 KB boundary IVPR 2 KB Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 51 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M freescale interrupts SOftware Vector Mode Interrupt Handler The IVOR4 Interrupt handler consists of 3 main parts Prologue e Save SRR s to stack Read IACKR to determine which INTC interrupt occurred See next slide e Re enable interrupts in MSR e Save GPR s to stack Jump to ISR e Branch with link to IACKR sa Execute mbar to ensure all pending data operations are complete before restoring any registers e Write to EOIR Sets CPR back to previous value e Restore GPR s e Disable Interrupts in MSR e Restore SRR s Execute RFI Return to address in SRRO and restore MSR Ky Freescale and the Fre e logo are trademarks of Freescale Semic pia ctor Inc pie U S Pat amp Tm Off Qor s a trademark of Freescale Semiconductor k r l Inc ne Power Ar Hiie aa and Power a eae rks and the Pow and Power abe and related marks ies poner donee icensed by f Power org i other pro
136. roperty of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e LL ene Mode Control Register gt Mode transition is controlled by writing twice ME_MCTL register 1st write TARGET MODE KEY 2nd write TARGET MODE INVERTED KEY TARGET 0000 RESET MODE 0001 TEST 0010 SAFE 0011 DRUN 0100 RUNO 0101 RUN1 0110 RUN2 0111 RUN3 i O i q o 1 q i D G q i i i i 1000 HALTO ME _MCTL register 1010 STOPO 1101 STANDBYO others configuration are reserved KEY OxSAFO INVERTED KEY OxA50F 4 5 a T g 10 i 12 13 14 16 peo fa fo fe to etot o o fo ato D 0 a i 0 0 E 0 0 a 0 N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor p lt Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 88 PF f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc e reesca e Status and Interrupt gt he complete transition could be triggered by e S MTRANS bit of Global Statu Register ME _ GS S_MTRANS 0 Transition noa active S _MTRANS 1 Transition on e MTC bit of Interrupt Status Register ME_IS MTC 0 No transition comp MTC 1 Transition complet gt Note bit MTC is no
137. rotected with single bit correction and double bit detection e Except in standby mode all SRAM is powered on While in standby mode user can decide to either power on all 48k or just 8k SRAM for power saving purpose Table 18 1 Low power configuration Configuration RUN TEST SAFE and The entire SRAM is powered and operational STANDBY Either all or just 8 KB of the SRAM remains powered This option is software selectable Fy Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Ps Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 33 eF f i Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc Yd reesca e MPU Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 3 4 f ra Ireescaie Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc MPU Block Diagram and Features sp
138. rty of their respective owners 2005 2010 2011 Freescale Semiconductor Inc P reesca ST BAM Overview BAM is only executed in either one of the following two cases 30002 0000 Kbytes Serial boot mode is selected by FAB pin 001 2000 TT Hardware has not found any valid ID in boot sectors 2 Kbytes s If one of above case is true the device s0001 0000 Boat information fetches code at address Oxffff _c000 and 16 Kbytes execute the BAM software 0000 Coua Beatinfarmation 16 Kbytes 0000 8000 Table 5 1 BAM memory organization BAM entry point OxFFFF_COO0 Downloaded code base address Ox4000_0700 0000 0000 Boat information Internal Flash N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 2 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 197 eF f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e BAM Logic Flow BAM entry OxXFFFF_COOO Save default configuration Which boot mode is selected is verified by reading the SSCM_STATUS register BMODE and ABD check boot mode i mode NO estore ge 7 default 1 STATIC mode configuration downlo
139. s 4 analog watchdogs with Interrupt capability Allow continuous hardware monitoring of 4 analog input channels The analog watchdogs are used for determining whether the result of a channel conversion lies within a given guarded area specified by an upper and a lower threshold value named THRH and THRL respectively Figure 25 6 Guarded area Analog voltage A Upper threshold Lower threshold After the conversion of the selected channel a comparison is performed between the converted value and the threshold values If the converted value lies outside that guarded area then corresponding threshold violation interrupts are generated N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 208 f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e 9 C I O Module eMIOS Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor g Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and ser
140. s a platform Flash controller PFlash interface and two Flash memory arrays one array of 512 Kbyte for code CFlash and one array of 64 Kbyte for data DFlash The Flash architecture of this device 1s illustrated in Figure 19 1 AHB Crossbar Switch AHB ports 32 A 4x128 Page Buffer 1x128 Page Buffer PFlash Controller Data Flash for EEPROM emulation 512 KB Flash Array 0 Array 0 L G S ee Se es es SS Se BankO CFlash ron Bank1 DFlash Figure 19 1 Flash memory architecture Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor se Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 124 pT f m ITreescaie Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M Flash saad Program Erase Sieh Bank 0 ee 512 Kbyte 16 KB TestFlash 16 KB Shadow Registers Interface Figure 19 2 Flash module structure Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks an
141. scale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor p lt Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 1 9 PF f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc e reesca e 5 Memory gt Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 20 Y f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc gt reesca e a Memory Topics e Memory Map e Flash Memory Code Flash Data Flash SRAM e MPU ECC Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 21 esf f Power org All other product or service names are the
142. straints dictate that the power actually consumed must reduce The MPC560xB C has a number of different modes which help to save power and enable our customers to meet all known low power requirements This further enables platform designs The reuse of modules peripherals and even the core means that the full tools ecosystem available has a huge amount of reuse across the entire MPC560xB C family Future family members will also be able to reuse the tools This ensures that our customers have to expend minimizes effort required to create platform designs Nexus2 debug and JTAG are included on the MPC560xB C No cumbersome emulators in application code tracing can save potential costly redesigns Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 0 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc N Y freescale MPC5604P Chassis amp Safety Core System Crossbar Masters up to 64 MHz PowerPC ISA e200 zenOh core Integration PowerPC Memory e200 Core 512k byte Program Flash with ECC 4x16k byte Data Flash with ECC 40k byte SRAM with ECC V
143. t e Common IVOR handler for 294 ISR s saves code e More convoluted than hardware Hardware Faster than software to execute e Inherently simpler to code understand than software Less code efficient with prologue and epilogue in each handler Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 60 f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e N D NTC Software Interrupts Eight interrupt vectors are assigned to software interrupts e Software interrupts 0 7 have interrupt vectors 0 7 A software interrupt request is triggered by software writing a 1 toa SETX bit in INTC Software Set Clear Interrupt Registers INTC SSCIR O 7 A software interrupt request is cleared by software writing a 1 toa CLRx bit in INTC Software Set Clear Interrupt Registers Ky Freescale and the Fre mais ogo are trademarks of Freescale Semiconductor Inc pie U S Pat amp Tm sand s a trademark of Freescale Semiconductor rks Inc ne Powe Adhie aa and Power a eae rks and the tad and Power abe and related marks ot a and service marks licensed by f Power org All other
144. t e Voltage Regulator and Power Supply N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Ps Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 76 eF f E pmm Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e Mode Entry Control Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor p Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 77 f m Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M reesca e K Mode Entry Purpose gt The purpose of the Mode Entry ME is to centralize the control of all device modes and related modules parameters within a unique module gt The ME simplify the implementation of mode management and so increase Its robustness e Avoiding to manage the power modes on a module by module basis e g peripherals FLASH mode voltage regulator e Defining the available modes and their related confi
145. t or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc _ reesca e OOS ae LINFLEX Enhanced error detection circuit Bit error e Slave response timeout Detection on all bits e Dedicated timer programmable by transmitted including men header delimiters e LINRX stuck dominant Identifier Parity Buffer overrun Break Delimiter Error signalling in LINESR register e 9 error sources Inconsistent Synch Field e Each error source can be independently Framing error enabled disabled Checksum Error e Classic Enhanced 4 N Freescale and the Fre PO e trademarks of Freescale Semiconductor Inc ie a olde rivva is a trademark of Freescale Semiconductor l Inc The Powe r Ar Hile ii and Power eto oe a and the tad and Power org logos and related marks are trade arks and service marks li eed by f w cal onductor Inc 175 reesca e M ogos Power org All other produ a vice nam e the property of their respective own 2005 2010 2011 Fre K _ __ _ L L LL LINFLEX Overview Protocol handler Master mode Header and response handling TX Confirmation without CPU intervention Master as publisher HEADER TXDATA CRC e Software configures ID Data length Sa E E Buffer and request TRANSMIT RESPONSE e Transmission without dead time RX Indication Synch Break length configurable from SIAVE RESPONSE CALENCY 10 to 36 bit times COOLING i
146. t set in case of transition to low pov modes HALT STOP STANDBY0O Reset a a E ME_IS register Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 89 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc X freescale Ln Example 1 of 3 DRUN Mode gt RUNO Mode transition gt Current Mode DRUN with system clock IRC default gt Target Mode RUNO Mode with system clock XOSC oteps gt Configuration of RUNO Mode ME _RUNO_MC OSCON 1 ME RUNO_MC SYSCLK XOSC gt Transition request ME _MCTL RUNO KEY ME MCTL RUNO INVERTED VECE sysclk XOSC KEY gt Waiting for the transition complete through the ME IS I MTC bit KO Freescale and the Fre E e logo are trademarks of Fre K i pim ctor Inc eae ne Off Qorivva is a trademark of Freescale icondu Inc ute as peer and Power Bete ka and the Pow and Power la elated m trad k i gos andr arks are trademarks and service marks license f J _ Power org All other produc e the property o of tial espective own S 2005 2010 2011 Freesca le Semiconductor Inc reesca e 2 o 2 lt O Ky Exit Lo
147. ted marks are trademarks and service marks licensed by 1 1 0 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M freescale VREG Supply and Regulator Diagram VDD_HV E k i HEBE 330nF T 330nF E 330nF HEE _ AVDD_HV _ AVDD _REF L _VDD_HV DOMAIN 2 STBY _ _ PA O Pa KACER aA A 24KRAM j J Px y Low Volt Detector DOMAIN 0 STBY eV DD LAV Pcjo 8KRAM RGM IRC PC 1 Wake up Unit etc REGULATOR co Pn m Main supply 5v or 3 3v Ballast supply 5v or 3 3v Digital supply 1 2v N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 1 1 f m Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e 4 N VREG Regulator Different Mode Main Functions Summary VREG Power Input Output Externally Control Regulator Domain Voltage Supply and regulation integrated into the chip High 1 2v digital 3 3v to 1 2v minimum PMOS Power power 5 0v 10 up of 3 x Regulator 10 to100mA 330nF cap Low 1 2v di
148. tion the power down mode will not entered until the program operation completed Low power mode sleep mode v Most of DC current can be turned off in low power mode v Read and write is not supported in this mode v Ifthe Flash is disabled during erase operation it could be suspended and resumed when power down mode is exited v Ifthe Flash is disable during the program operation the power down mode will not entered until the program operation completed Normal Mode The operational mode of Flash module Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor oS Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by P f J u 128 Ireescaie Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc Platform Flash Controller PCF e200z0h Core D Dispatch Debug Load Sto re Dispatch ee n nit AHBBU BIU eo p_i_h RPP_Z0H_REF 28 bit read data bus 64 bit write data bus 24 bit address bus MemArray Banki PFlash J MemArray L Banko IPS 4PB IPFS APB Bus Slave Modules IPS Bus On platform IRQs e ane aa Off Platform IRQs Figure 20 42 Power Architecture e200z0h RPP reference platform blo
149. to Seer Trigger transmission reception or discard depending on the aS identifier aam Fill the buffer transmission or get data from buffer reception Gae me Soe In Filter mode Software intervention needed only to Fill the buffer in transmission Get data from buffer in reception f Filter mode is combined with DMA one channel per filter no software intervention required Ph mak EIT A J peuri znr cuma ones cht oura cana fo onre TEO i UART mode a es Full duplex Character length 7 amp 8 bits opt parity 1 or 2 stop bits ee ooe ome cor se 4 byte Tx and Rx buffers Le MI A y aka AICA 3 interrupt sources error Rx Tx jm LSB first N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 72 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc K freescale LINFLEX Operating modes Initialization mode RESET e all transfers to and from the LIN bus are stopped e LIN TX Pin is recessive high e Entering INIT mode does not change the configuration registers d SLEEP e LIN and UART configuration registers can
150. trademarks and service marks licensed by 1 92 o 7 f u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc gt reesca e SE Arbitration The XBAR supports two arbitration schemes a simple fixed priority comparison algorithm and a simple e200z0 round robin fairness algorithm Instruction The arbitration scheme is independently programmable for each slave port When operating in fixed priority mode each master is assigned a unique priority level in the MPR and AMPR If two masters both request access to a salve lport the master with the highest priority in the selected priority register will gain control over the slave port Crossbar When operating in round robin mode each master is assigned a relative priority based on the master number This relative priority is compared to the ID of the last master to perform a Flash PBridge Seo transfer on the slave bus The highest priority requesting master will become owner of the slae bus as the next XBAR Structure of MPC5605B transfer boundary Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qoriwa is a trademark of Freescale Semiconductor ey Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 93 oe f J u Powe
151. trols affordable bringing 3 5 improvement of economy and power e Knock system helps reduce global warming by lowering CO emissions by 3 5 for same amount of fuel Power and memory size allow fast development of clean sheet solutions to meet emissions legislation e No active external components required for on chip knock system because of variable on chip gain and sensor bias e Same integrated components can be used for a patented sensor diagnostics scheme that meets on board diagnostics gt Improves Performance e Combination of hardware decimator and DMA can lead to a savings of up to 5 of the CPU load e eT PU and I O configured to handle electronic manual transmissions paddle flap applications where up to four brushless DC motors are used e Offers 32 eTPU2 channels to handle complex timer applications and offload the CPU gt Ease of Use Offers a 144 pin quad flat package QFP option QFP has visible pins making it easier to assemble and inspect since infrared and X ray technology is not required e Microsecond bus enabled for connecting ASIC with MPC563xM family Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 1 9 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by f J u Power org All other product or service
152. up Unit etc REGULATOR A Pn m Main supply 5v or 3 3v Ballast supply 5v or 3 3v Digital supply 1 2v N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 02 f l ra Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e 4 N LL Operating modes supported gt The PCU has individual control bits for the following operating modes in the appropriate Configuration Register e RESET DRUN SAFE TEST RUNO RUN1 RUN2 RUN3 HALTO STOPO and STANDBYO gt These bits are available for all power domains but only domain 2 is configurable To enable a power domain set the bit corresponding to each mode e By default the power domain is enabled in all modes except STANDBYO mode Ky Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm sl raed s a trademark of Freescale Semiconductor rks r l Inc ne Powe r Ar Hiie aa and Power T T rks and the toed and Power bee and related marks Ni a and service marks licensed by f J Power org All other produ Ba vice n e the property of their respective own O2 2010 2011 a
153. vice marks licensed by 209 4 fre es C a e Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eo BOLERO family offers up to two eMIOS modules 0 and 1 with 28 channels each Each eMIOS features input capture output compare PWM and GPIO modes Not all modes on all channels 5 x 16 bit counter busses independent time bases A counter bus can be shared between different channels Programmable clock prescalers for channels 0 8 16 23 amp 24 Programmable input filter Channels can be individually disabled to assist with power saving The two eMIOS modules start stop synchronously System Global Clock Prescaler Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc eMIOS H uca X emiost2a Counter Bus A eMIOS 23 UC 23 kX X eMIOS 22 i l UC 16 eMIOS 16 SX emlos 15 Counter Bus C X emlosis X emiosi7 r gt emosio 210 Le Ky freescale eMIOS Channel Configuration
154. w Power Mode HW triggered transition SW triggered transition gt Automatically managed by rarer a ar DEER hardware MODES gt Came back to the previous 3 mode from which entered in if exit from Stop mode N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Px Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 91 eF f E pmm Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e Example 2 of 3 RUNO Mode gt STOP Mode gt RUNO Mode transition gt Configuration of STOP Mode ae ene eee ME STOP MC SYSCLK NO CLK gt Software Transition request e ME MCTL STOP KEY ME_MCTL STOP INVERTED KEY ea Device put in STOP Mode by SW aaa gt Force an interrupt wakeup event gt Device exited from STOP Mode to RUNO Mode by HW gt Waiting for the transition complete through the ME_IS I MTC bit Ky Freescale and the Fre aie ogo are trademarks of Freescale Semiconductor Inc oie U S Pat amp Tm sl raed s a trademark of Freescale Semiconductor rks Inc ne Powe Archie aa and Power T T rks and the toed and Power bee and related marks Ni a and service marks licensed by f J Power org All other
155. wer org logos and related marks are trademarks and service marks licensed by 30 esf f Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e Introduction gt SIUL features the following gt Pad Control and OMux configuration Intended to configure the electrical parameters and mux ing of each pad gt GPIO ports Manages up to 123 GPIO pads organized as ports that can be accessed for data reads and writes as 32 16 or 8 bit PAD Control PCR age PSMI Regs GPIO functionality gt External interrupt management Allows the enabling and configuration such as filtering window edge and mask setting of digital glitch filters on each ext irq gt MCU Identification Recognition of the exact MCU a rtorrupt cenfig Glitch filter Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 31 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc M freescale SIUL Pad Control and IOMux configuration gt Pad Control is managed through PCR registers gt OMu
156. wer and Power org logos and related marks are trademarks and service marks licensed by 1 95 f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e K COO Boot from Single Chip Mode Figure 5 2 Reset Configuration Half Word RCHW 128 Kbytes 0002 0000 s0001 8000 Boot information MMPC560xB Flash is partitioned into boot sectors as shown in the left diagram Each boot sector contains at offset Ox00 the Reset Configuration Half Word RCHW s0001 0000 Bast infermaten In single chip boot mode the hardware searches a flash boot sector for a valid boot ID As soon the device 0000 cooo ieee detects a bootable sector it jumps within this sector and reads the 32 bit word at offset 0x4 The word is the OS address where the startup code is located If a valid RCHW is not found the BAM code is executed in this case BAM just put MPCS560xB into soono oaao Beatinfarmatian static mode low power SAFE mode Internal Flash T Kbytes N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 2 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 96 eF f u Power org All other product or service names are the prope
157. wer and p owe a gos and related marks HN a emarks and service marks licensed by f J Power org A other produc e the property o An espective own O2 2010 2011 Freesca le Semiconductor Inc 98 reesca e Example 3 of 3 EMIOSO Clock Gating gt Configure EMIOS in the following way Active in DRUN RUNO STOP Mode Clock gated in the others mode gt Steps gt Configuration of Running Mode ME_RUN_PC 1 DRUN 1 ME_RUN_PC 1 RUNO 1 gt Configuration of Low Power EMIOG active Mode ME_LP_PC 2 STOP 1 gt Configuration of EMIOS peripheral number 72 ME_PCTL 72 RUN_CFG 1 ME_PCTL 72 LP_CFG 2 Ky Freescale and the Fre e logo are trademarks of Freescale Semic pim ctor Inc oie U S Pat amp Tm Off Qor s a trademark of Freescale Semiconductor k l icond Inc ne Power Ar Hiie aa and Power T T rks and the Pow and Power bee and related marks ns sone s and service marks licensed by f Power org A other produc e the property o An espective own O2 2010 2011 Freesca le Semiconductor Inc 99 reesca e KA Power Control Unit and Reset Generation Module sp Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor 2 Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 1 00 e fr e e S C a e Power org Al
158. x configuration is managed through PAD Control PCR Registers output ae functionalities PSMI Regs PSMI Registers input functionalities Ext Interrupt Mgmt Interrupt config Glitch filter Ky Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 39 f J u Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc reesca e M SIUL Pad Control and lOMux config PCRn SMC ode L al AP ok ns PCRn WPE SoC Safe Mode A v PCRn WPS 5 PCRn OBE PGRn ODE 5 SA Le _ PCRn SRC _ PCRn APC PCRn PA Reset O Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivwva is a trademark of Freescale Semiconductor Psd Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by p f 33 treescaie Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc D Pad Control Register PCR General gt
159. y used for a certain input function Table 15 13 Peripheral inpul pin selection PSMI registers PSMI registers PADSEL fields PADSEL fields fields SIUL address offsot address offset Function Poripheral Mapping PSMIO_3 PADSELO CANIRX FlexGAN 1 00 PCA 35 01 PCR 43 10 PCR as PADSEL1 0x501 CAN2RX FlexCAN 2 0 PCR 73 i aih PADSEL2 0x502 CANSRX FlexCAN3 00 PCA 36 01 PCA 3 10 PCRs PADSEL3 0x503 CAN4RX FlexCAN 4 00 PCA 35 01 PCR 43 10 FCR 95 A KO Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by 37 Power org All other product or service names are the property of their respective owners 2005 2010 2011 Freescale Semiconductor Inc freescale Usage of PSMI Registers Graphic representation 1 PAD l l l l a on one a PA t i T TT 1 PAD Mm i i nS Z gt i 0 1 2 3 4 8 9 10 11 12 15 16 17 18 19 20 23 24 25 26 27 28 31 PADSEL n 2 O O O O PADSEL n 3 N Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Qorivva is a trademark of Freescale Sem

Crossbar Switch

Contents

Download Pdf Manuals

Related Search

Related Contents