Home

User Manual MIC-5603 - Advantech

1. Y 54 5 5 1 AMC connector Interfaces and E Keying channels 54 Table 5 7 AMC port vs E Keying channel 54 5 5 2 E keying channel 55 5 5 3 Clock E keying 2 cien eene Ra 55 commands sse nennen nennen sn trennen sinn 56 Table 5 8 OEM command overview 56 5 6 1 IPMItool raw emen 56 5 6 2 Configuration setting OEM commands 56 5 6 3 LAN controller interface selection 57 5 6 4 FPGA COM port UART MUX sse 58 Table 5 9 OEM 4 58 Table 5 10 COM1 UART MUX 58 Table 5 11 COM2 UART MUX 58 5 6 5 Read Port 80 BIOS POST Code OEM command 59 5 6 6 Clear NVRAM data OEM command 59 5 6 7 MAC address mirroring OEM 59 Table 5 12 address mapping table 59 5 6 8 Load default configuration OEM 60 UART and UART Multiplexer een 60 5 7 1
2. 444222212 42 viii Chapter 5 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 5 10 MMC Firmware Operation 43 Module Management 44 PMI Iriterfaces iiit tertie titre ete 44 Figure 5 1 IPMI 44 524 44 522 ec 45 523 45 Sri 46 MEETS E 46 Table 5 1 Sensor 1 5 88 46 5 3 2 Threshold based 47 Table 5 2 Threshold descriptions 47 Table 5 3 Voltage sensor 47 Table 5 4 Temperature sensor 48 5 3 3 Discrete Sensors eese teen etit e e re 48 5 3 4 Example sensor data 49 5 3 5 Integrity Sensor ss deed terne dette qne ied aae Pbi 49 Table 5 5 Integrity sensor event definitions 50 Table 5 6 Integrity sensor s event data table 51 FRU Information 53 5 4 1 PICMG FRU 53 5 4 2 FRU Information access 53 5 4 3 Example FRU 0 1121111 53 E KOYING e
3. H H H EA S 4 5603 0 02 s 003 hir aaa 02 31 4000c Component requires Payload Cold Reset Firmware upgrade procedure successful Activate NVRAM image Following two actions are needed to boot BIOS with the new NVRAM image and BIOS settings OEM NVRAM section activate command Since there are more than one NVRAM sections provided by the MMC another IPMI OEM command is used to activate a selected NVRAM section default 0 root localhost ipmitool raw 0x2E 0x40 0x39 0x28 0x00 0x03 0x02 lt section gt Payload cold reset A payload cold reset is required to activate the new NVRAM image Component requires Payload Cold Reset The payload reset can be performed through different ways W If the user is working on the local OS KCS a linux reboot poweroff or halt W If the user accesses the MMC through the other interfaces LAN IPMB a deac tivation and activation cycle is needed to load the new NVRAM image 75 MIC 5603 User Manual 6 6 Verify successful upgrades To verify successful updates the IPMItool hom check command can be used root localhost ipmitool hpm check PICMG HPM 1 Upgrade Agent 1 0 2 Device Id 0x21 Device Revision 0x81 Product Id 0x5603 anufacturer Id 0x2839 Unknown 0x2839 ID Name Versions Active Backup 0 5603 BLL 0 22 1 5603 MMC 0 24 0 22 2 5603 FPGAA 241
4. 5603 Advanced Mezzanine Processor AMC AD ANTECH Enabling an Intelligent Planet Copyright The documentation and the software included with this product are copyrighted 2013 by Advantech Co Ltd All rights are reserved Advantech Co Ltd reserves the right to make improvements in the products described in this manual at any time without notice No part of this manual may be reproduced copied translated or transmitted in any form or by any means without the prior written permission of Advantech Co Ltd Information provided in this manual is intended to be accurate and reliable How ever Advantech Co Ltd assumes no responsibility for its use nor for any infringe ments of the rights of third parties which may result from its use Acknowledgements All other product names or trademarks are properties of their respective owners Product Warranty 2 years Advantech warrants to you the original purchaser that each of its products will be free from defects in materials and workmanship for two years from the date of pur chase This warranty does not apply to any products which have been repaired or altered by persons other than repair personnel authorized by Advantech or which have been subject to misuse abuse accident or improper installation Advantech assumes no liability under the terms of this warranty as a consequence of such events Because of Advantech s high quality control standards and rigo
5. Temperature Threshold PCH temperature 17 INTEGRITY OEM Advantech Integrity sensor 18 WATCHDOG Watchdog 2 Discrete IPMI BMC Watchdog sensor 19 FW PROGRESS oo Progress PMI FW Progress sensor 20 VERSION_CHANGE Version Change Discrete IPMI Version Change sensor MIC 5603 User Manual 46 5 3 2 5 3 2 1 Threshold based sensors According to the IPMI specification sensor event thresholds are classified as Non critical Critical or Non recoverable When different thresholds are reached different actions may be executed by carrier or shelf manager e g fan speed adjustment for temperature sensor events Below table list the six sensor thresholds specified for threshold based sensors in the following subchapters Table 5 2 Threshold descriptions Threshold Description UNR Upper Non recoverable UC Upper Critical UNC Upper Non critical LNC Lower Non critical LC Lower Critical LNR Lower Non recoverable Voltage sensors All listed voltages listed below are monitored by the MMC and readable via IPMI Table 5 3 Voltage sensor list Sensor Name Nominal IINR cR lunc Value MP VOL 3 30 290 315 345 360 1370 V12 VOL 12 0 9 90 102 10 8 13 2 13 8 14 1 V5 0 VOL 5 00 440 450 475 525 550 5 0 VO 75 VOL 0 75 0 60 10 675 0 71 079 0825 0 90 V1 8 VOL 1 8 158 162 1 71 1 89 1 98 202 V1 5 VOL 1 5 1 26 135 142
6. 5 5 3 Clock E keying The AMC 0 R2 0 Specification defines additional Clock E Keying for the AMC Clock Interfaces These AMC clocks are comprised of four Telecom clocks TCLKA TCLKB TCLKC and TCLKD plus one fabric clock FCLKA 5 5 3 1 Fabric PCI Express clock The MIC 5603 AMC module connects FCLKA with a PCI Express reference clock from its PCH chipset Root Complex This means the PCIE reference clock is gen erated locally and the AMC acts as clock source to connected PCI Express End points The FRU data describes the AMC s PCIE clock details in a PICMG Clock Configuration Record according to AMC 1 R2 0 PCI Express on AdvancedMC Spec ification To establish PCIE connections from the MIC 5603 Root Complex to PCIE Endpoints on other AMC modules or on Carrier devices the clock signal need to be connected to this PCIE device This implicate that the Carrier Manager and Backplane must support clock routing in HW and SW Clock E Keying 55 MIC 5603 User Manual 5 6 5 6 1 5 6 2 OEM commands Advantech management solutions support extended OEM IPMI command sets based on the IPMI defined OEM Group Network Function NetFn Codes 2Eh 2Fh The first three data bytes of IPMI requests and responses under the OEM Group Net work Function explicitly identify the OEM vendor that specifies the command func tionality To be more precise the vendor IANA Enterprise Number for the defining body occupies the first three data byt
7. Backlight Control PWM Inverted Back Light Control Setting BIA Auto Spread Spectrum clock Chip Off TV1 Standard VBIOS Default Select the ability to configure a TV Format MIC 5603 User Manual 34 TV2 Standard VBIOS Default Select the ability to configure a TV Minor Format ALS Support ALS Support Enable Legacy ALS Support through the IGD INT10 function ACPI ALS support through an ACPI ALS driver Active Int LVDS Select the Active LFP Configuration No LVDS VBIOS does not enable LVDS Int LVDS VBIOS enables LVDS driver by integrated encoder SDVO LVDS VBIOS enables LVDS driver by SDVO encoder eDP Port A LFP Driven by Int DisplayPort encoder from Port A Panel Color Depth 18 Bit Select the LFP Panel Color Depth The Option 18 Bit 24 Bit 4 5 1 6 j 4 4 Figure 4 20 configuration menu DMI Vc1 Control Enabled DMI Vcp Control Enabled DMI Vcm Control Enabled DMI Link ASPM Control LOsL 1 Enable or disable the control of Active State Power Management on SA side of the DMI Link 35 MIC 5603 User Manual Jojdeuy dnies Sold IINV m DMI Extended Synch Control Disabled Enable DMI Extended Synchronization m Gen 2 Enabled Enable or disable DMI Gen 2 4 5 1 7 NB PCle Configuration 1 COMA Pu TY Auto Auto ato Figure 4 21 NB PCI Express configuration men
8. Declaration of Conformity CE This product has passed the CE test for environmental specifications when shielded cables are used for external wiring We recommend the use of shielded cables FCC Class B Note This equipment without HDMI cable connected to the front panel I O interface has been tested and found to comply with the limits for a Class B digital device pur suant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commer cial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense FM This equipment has passed the FM certification According to the National Fire Pro tection Association work sites are classified into different classes divisions and groups based on hazard considerations This equipment is compliant with the speci fications of Class l Division 2 Groups A B C and D indoor hazards Technical Support and Assistance 1 the Advantech web site at www advantech com support where you can find the latest information about the product 2 Contact your distributor sales re
9. Figure 4 10SATA configuration menu 26 4 4 7 Intel Trusted Execution Technology 27 Figure 4 11Intel Trusted Execution Technology configuration MONU 27 4 4 8 Intel FW 28 Figure 4 12Intel Management Engine firmware configuration prc 28 4 4 9 USB 28 Figure 4 13USB configuration menu 28 4 4 10 Serial Port Console 29 Figure 4 14Console redirection configuration menu 29 4 4 11 Sandy Bridge DTS 30 Figure 4 15Processor Digital Thermal Sensor setting 30 4 4 12 Sandybridge PPM Configuration sese 31 Figure 4 16Processor PPM configuration menu 31 eei 32 4 5 1 System Agent SA 32 Figure 4 17System Agent configuration menu 32 Figure 4 18Intel graphics engine configuration 33 Figure 4 191 CD control configuration 34 Figure 4 20DMI configuration 35 Figure 4 21NB PCI Express configuration menu 36
10. Figure 4 22System memory configuration 37 4 5 2 IO Configuration essen 38 Figure 4 23Intel PCH configuration menu 38 Boot Configuration essssssssssessseeeee eene 39 Figure 4 24Boot configuration menu 39 4 6 1 Setup Prompt 39 4 6 2 Boot up NumLock State 39 4 6 8 Quick Boot 39 4 6 4 5 16 Module Version 07 64 39 4 6 5 Boot option priorities Built in EFI Shell 39 SII ce E 40 Figure 4 25Security setup menu sess 40 4 7 1 Administrator 4 en 40 4 7 2 User Password usse eere tdeo desert e E dee 40 SUCI asse c 41 Figure 4 26Save and Exit 41 4 8 1 Save changes and 41 4 8 2 Discard changes and Exit 41 4 8 3 Save changes and Reset sss 41 4 8 4 Discard changes and 41 4 8 5 Save changes a ainak 42 4 8 6 Discard changes eee ten Pobre 42 4 8 7 Restore Deftaults iisdem 42 4 8 8 Save as User 42 4 8 9 Restore User
11. fied in IPMI v1 5 request response manner for communication IPMI v1 5 LAN messages are encapsulated in RMCP packets while IPMI v2 0 specification added an enhanced protocol RMCP for transferring IPMI messages and other types of payloads RMCP uses RMCP overall packet format but defines exten sions such as encryption and the ability to carry additional traffic types e g serial data in addition to IPMI messages refer to Chapter 5 12 Serial over LAN Three of MIC 5603 s Ethernet interfaces can be used for IPMI over LAN Both AMC fabric interfaces AMC Port 0 and 1 W The front panel LAN2 RJ 45 connector Note The LAN controller used for PMI communication is connected to the payload power domain Thus the payload needs to be powered to be 5 able to use IPMI over LAN Following IPMItool parameters are needed to connect to the MMC vial LAN ipmitool I lan H IP Address U User P Password Command 45 MIC 5603 User Manual Command Line Syntax lan Specifies Ethernet interface H lt IP Address gt IP address assigned to the MMC U User User account default administrator Password used with specified user account default password for user administrator is advantech 5 3 Sensors Monitoring board voltages and temperatures in one of the main tasks of the MMC populated on the MIC 5603 Processor AMC All important voltages and temperatures ar
12. Address ICMB 09h Mandatory Optional No Get ICMB Connector Bridg Optional info ICMB OAh Mandatory Optional No Get ICMB Connection Bridg Optional ID ICMB e OBh Mandatory Optional No 2 ICMB Connection ICMB ene OCh eddie Optional No Discovery Commands ICMB IPMI Advantech Command v2 0 NetFn CMD ES BMG MOD MMC Ref a 9 Bridg Optional Prepare For Discovery ICMB 10h Mandatory Optional No Bridg Optional Get Addresses ICMB m 11h Mandatory Optional No Bridg Optional Set Discovered ICMB e 12h Mandatory Optional No Bridg Optional Get Chassis Device ID ICMB a 13h Mandatory Optional No Set Chassis Device ID ICMB Bridg 44h Optional Optional N e Mandatory prona o Bridging Commands ICMB IPMI Advantech Command v2 0 CMD ES BMC MC MMC Ref 9 9 Bridg Optional Bridge Request ICMB 20 Optional No Bridge Message IcMB 8 99 ath MERERI Optional No 85 MIC 5603 User Manual Event Commands ICMB IPMI Advantech Command v2 0 CMD ES ENS MEC MMC Ref q 4 support Get Event Count ICMB eu 30h Optional No Set Event Destination ICMB Seg 31h rae Optional No Set Event Reception Bridg Optional State ICMB 32h Mandatory Optional No Send ICMB Event Bridg Optional Message ICMB B 3
13. odis Inventory 34 1 Storage 10h Mandatory Mandatory Yes Read FRU Data 34 2 Storage 11h Mandatory Mandatory Yes Write FRU Data 34 3 Storage 12h Mandatory Mandatory Yes SDR Device Commands IPMI Advantech Command v2 0 NetFn CMD E BME MEC MMC Ref 9 support m SDR Repository 33 9 Storage 20h Mandatory Optional Yes DRR i 4 1 Storage 21h Optional Optional No Reserve SDR 33 1 Repository 1 Storage 22h Mandatory Optional Yes Get SDR 2 Storage 23h Mandatory Optional Yes Add SDR dh Storage 24h Mandatory Optional No Partial Add SDR ria Storage 25h Mandatory Optional No Delete SDR gen Storage 26h Optional Optional No Clear SDR Repository EM Storage 27h Mandatory Optional Yes Get SDR Repository 33 1 Optional Time 7 Storage 28h Mandatory Optional Yes Set SDR Repository 33 1 Optional Time 8 Storage 29h Mandatory Optional Yes Enter SDR Repository 33 1 Update Mode 9 Storage 2Ah Optional Optional No Exit SDR Repository 33 2 Update Mode 0 Storage 2Bh Mandatory Optional No Run Initialization Agent que Storage 2Ch Optional Optional No MIC 5603 User Manual 82 SEL Device Commands IPMI Advantech Command v2 0 PMIBMC Module Req MMC Ref support Get SEL Info 31 2 Storage 40h Mandatory Optional Yes Get SEL A
14. Base interface AMC Ports 0 amp 1 These commands be used to read out the actual selected IPMI over LAN Serial over LAN interface and to change the selection LAN controller interface selection settings 00h Front panel LAN IO 01h AMC connector LAN BI default Read LAN Interface selection ipmitool raw 0 2 0x41 0x39 0x28 0x00 0x04 0x00 Response 39 28 00 setting Change LAN Interface selection ipmitool raw 0x2e 0x40 0x39 0x28 0x00 0x04 0x00 setting Response 39 28 00 LAN controller channel selection and priority In addition to the selected LAN controller interface users may need to configure each single LAN controller channel port as dedicated NC SI interface to the MMC Addi tional OEM commands for the configuration of the NC SI LAN controller channel selection and priority are provided to allow a flexible configuration LAN channel selection priority setting list 0 The first channel that links up gets the NC SI connection to the MMC 1 Channel 1 is the preferred port if it is up otherwise use channel 2 if it is up 2 Channel 2 is the preferred port if it is up otherwise use channel 1 if it is up 3 Channel 1 is the only allowed port always use it never change to channel 2 4 2 Channel 2 is the only allowed port always use it never change to channel 1 The NC SI LAN controller channel setting will be stored permanently non volatile EEPROM The defa
15. Hot Plug Disabled 1 External SATA Disab led gt lt Select Screen 1 Hard Disk Driver v Select Item 1 Spin Up Device Disabled Enter Select Serial ATA Port 1 Empty Change Opt 1 Software Preserve Unknown F1 General Help Port 1 Enabled F2 Previous Values Hot Plug Disabled 3 Optimized Defaults 1 External SATA Disabled sc Save amp Exit 1 Hard Disk Driver SC Exit Figure 4 10 SATA configuration menu 4 4 6 1 SATA Mode Selection AHCI AHCI Mode Use this setting to attach all SATA channel to one ACHI compati ble PCI mass storage controller m IDE mode When this setting is used the following applies The SATA channels 0 to 1 are logically attached to one legacy ATA compatible PCI device where channel 0 forms the primary master channel 1 the primary slave channel 2 the secondary master and RAID mode Use this setting to specify that e2 channels are attached to one RAID PCI controller 4 4 6 2 SATA Test Mode Test Mode 4 4 6 3 Aggressive LPM Support Enable Aggressive Link Power Management ALPM is a power saving Technique that helps the disk save power by setting a SATA Link to the disk to a low Power setting during idle time that is when there is no MIC 5603 User Manual 26 4 4 6 4 Software Feature Mask Configuration 77777200 RAD eweDiaeRAD Rau _ EwMeDiabe
16. Setup screen You can select any of the items in the left frame of the screen such as CPU Configuration to go to the sub menu for that item You can display an Advanced BIOS Setup option by highlighting it using the Arrow keys All Advanced BIOS Setup options are described in this section The Advanced BIOS Setup screen is shown below The sub menus are described on the following pages COMI3 Pal TY Trusted Computing TPM Legacy OpROM Support settings Launch PXE OpROM Disabled 1 PCI Subsystem Settings ACPI Settings CPU Configuration SATA Configuration Intel TXT LT Configuation PCH FW Configuration gt lt Select Screen USB Configuration v Select Item Serial Port Console Redirection Enter Select Sandybridge DTS Configuration Change Opt Sandybridge PPM Configuration F1 General Help F2 Previous Values F3 Optimized Defaults F4 Save amp Exit ESC Exit Figure 4 4 Advanced BIOS Features Setup Screen 4 4 4 Launch PXE OpROM Disabled i COMI3 PuTTY Enable or Disable Boot Legacy OpROM Support Option for Legacy Network Devices 1 PCI Subsystem Settings 1 ACPI Settings 1 Trusted Computing 1 CPU Configuration 1 SATA Configuration 1 Intel TXT LT Configuation PCH FW Configuration gt lt Select Screen USB Configuration 1 Select Item Serial Port Console Redirection Enter Select Sandybridge DTS Conf
17. UART block diagram eerie erento 60 Figure 5 2 UART functional block overview 60 5 7 2 UART implementation 60 5 7 9 61 Table 5 13 COM port usage 5 61 Hot SWap AG Plas E 61 5 8 1 ACPI featured graceful shutdown 222 2 2 27 2 61 5 8 2 Graceful shutdown 1 61 BIOS failover redundanoy sse 62 NER T UII 62 5 9 2 BIOS 62 5923 MMC ziii tied ecd e daanin 62 5 9 4 BIOS 62 Supported 63 5 10 1 Firmware watchdog eene enne 63 5 10 2 BMC 63 ix MIC 5603 User Manual Chapter 6 6 1 6 2 6 3 6 4 6 5 6 6 Appendix A A 1 Appendix B B 1 B 2 MIC 5603 User Manual roc 9 63 5 11 1 Module management controller resets 63 5 11 2 Payload reset cce eere eee tee eps 64 io MT o 64 5 12 1 Preconditions for SOL sse 64 5 12 2 LAN configuration with IPMItool eeee 65 5 12 3 SOL session with 4 66 HPM 1 Update 69 precondlitlo
18. a checksum error 49 MIC 5603 User Manual 5 3 5 3 Event data byte definition The following list provides the exact Integrity sensor event bytes definition Table 5 5 Integrity sensor event definitions Data Byte Bit Description Value Event Data Event data 2 amp event data 3 used 1 7 0 IPMI Header OxAO as OEM data HPM 1 component FW FPGA 0x00 0x07 BIOS 2 7 0 Component 0x08 OxFE Logical component FRU OxFF RTC Board specific event b00000 Update b00001 Recovery Rollback b00010 Manual Rollback b00011 Automatic Rollback b00100 Activation b00101 Flash 0 Boot b00110 Flash 1 Boot Action b00111 Common Header 3 7 3 Subcomponent b01000 Internal Area b01001 Chassis Info Area b01010 Board Info Area b01011 Product Info Area b01100 Multi Record Area b01101 Time synchronization b01110 Graceful Shutdown 001111 Not defined yet b11111 Not defined yet b000 Successful b001 Failed b010 Aborted b011 Checksum Error 3 2 0 Resul b100 Timeout b101 Initiated b110 Finished b111 Unspecified Error 5 3 5 4 Event data translation The structured definition allows simple translation of each Integrity Sensor event message Below is an example Integrity Sensor SEL event 0x0A0100 The three event data bytes could be translated in following manner Data 1 OxOA Header Data 2 0x01 logical Component MMC FW Data 3 0x00 50200000000 Update Successful The example In
19. configuration menu Graphics Turbo IMON Current 31 Graphics turbo IMON current values supported 14 31 Primary Display Auto Select which of IGFX PEG PCI Graphics device should be Primary Display or select SG for Switchable Gfx Internal Graphics Auto Keep IGD enabled based on the setup options WB GTT Size 2MB Select the GTT Size Aperture Size 256MB Select the Aperture Size m DVMT Pre Allocated 64MB Select DVMT 5 0 Pre Allocated Fixed Graphics Memory size used by the Internal Graphics Device DVMT Total Gfx Mem 256M Select DVMT 5 0 Total Graphic Memory size used by the Internal Graphics Device m Gfx Low power Mode Enabled 33 MIC 5603 User Manual y Jajdeuy dnies 5019 INY B LCD Control 1 1 1 1 1 1 1 S 1 1 1 1 1 1 Figure 4 19 LCD control configuration menu Primacy IGFX Boot Display VBIOS Default Select the video Device which will be activated during POST Secondary boot dis play selection will appear based on selection VGA modes will be supported only on primary display LCD Panel Type VBIOS Default Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item SDVO LFP Panel Type VBIOS Default Select SDVO panel used by Internal Graphics Device by selecting the appropriate setup item Panel Scaling Auto Select the LCD panel scaling option used by the Internal Graphics Device
20. definitions in the IPMI specification Its main purpose is to monitor inter nal firmware states and report events to the operator that would otherwise go unno ticed hence integrity sensor Examples for those events are checksum errors firmware update success failure firmware rollbacks Sensor characteristics The Integrity sensor does not support sensor reading but generates event messages only These events are stored in the local System Event Log SEL and sent to the default event receiver The event message contains three bytes of event data The first byte defines how the event is supposed to be treated the value of 0 0 defines that event data 2 and 3 contain OEM data please verify the IPMI specification for details on OEM sensors Event data 2 is used to identify which component the event relates to This can either be a HPM 1 component a logical component feature on the board for example FRU RTO or simply a board specific event Event data 3 7 3 identifies the action or a subcomponent For example If the com ponent in byte 2 was a HPM 1 component it might report if this was an update a roll back or boot failure If the component in byte 2 was FRU it might indicate the subcomponent area within the FRU that the event relates to Event data 3 2 0 holds the result code For the HPM 1 example above it might report that an update or rollback either succeeded or failed For the FRU example it might indicate
21. tion to remove the need for any mechanic keying It defines the process in which a Carrier determines a matching configuration of channel and clock connections to an AMC Module Main purpose is to prevent board damage and miss operation Further more it helps to verify the Carrier to AMC module compatibility The MIC 5603 FRU data includes an important PICMG AMC point to point connec tivity record for E Keying refer to Chapter 5 4 FRU Information This record describes the AMC port connectivity gold finger connector and is parsed by the Car rier Manager during AMC initialization The Carrier Manager will only enable match ing interfaces with identical AMC port protocols per channel between Carrier and AMC Module when the CM powers and activate the AMC module 5 5 1 AMC connector Interfaces and E Keying channels The table below lists the MIC 5603 AMC gold finger connector protocols per AMC port and where the ports are connected The last column relates the AMC ports to the used E keying channel numbers Table 5 7 AMC port vs E Keying channel AMC Port Region Protocol Connected Resource E Keying channel No 0 GbE 1000Base BX LAN Controller 0 1 Common GbE 1000Base BX LAN Controller 1 2 Options SATA PCH 2 3 SATA PCH 3 4 PCIE PCH 5 PCIE PCH 4 6 PCIE PCH 7 PCIE PCH 8 Fat Pipes LVDS AMM optional 9 1 LVDS A
22. x64 Compliency UEFI 2 1 Project Version mic 5603V120 Build Date and Time 04 05 2012 16 58 05 System Date Thu 01 01 2009 System Time 00 00 191 gt lt Select Screen v Select Item Access Level Administrator Enter Select Change Opt F1 General Help F2 Previous Values F3 Optimized Defaults F4 Save amp Exit ESC Exit Figure 4 3 Main Setup Screen The main BIOS setup menu screen has two main frames The left frame displays all the options that can be configured Grayed out options cannot be configured while options in blue can The right frame displays the key legend Above the key legend is an area reserved for a text message When an option is selected in the left frame it is highlighted in white Often a text message will accompany it System Time and System Date Use this option to change the system time and date Highlight System Time or Sys tem Date using the Arrow keys Enter new values through the keyboard Press the Tab key or the Arrow keys to move between fields The date must be entered in MM DD YY format The time is entered in HH MM SS format Note There is no battery backed RTC on the MIC 5603 standard model E therefore the system time and date will not be updated continuously 5 when the power to the processor is off MIC 5603 User Manual 20 4 4 Advanced BIOS Feature Setup Select the Advanced tab from the MIC 5603 setup screen to enter the Advanced BIOS
23. 03 User Manual y Joideuy dnies 5019 INY 4 8 5 Save changes Save changes done so for to any of the setup option 4 8 6 Discard changes Discard changes done so for to any of the setup option 4 8 7 Restore Defaults Restore Load default values for all the setup option 4 8 8 Save as User Defaults Save the changes done so far as User Defaults 4 8 9 Restore User Defaults Restore the user defaults to all the setup options MIC 5603 User Manual 42 MMC Firmware Operation This chapter describes the MMC firmware features 5 1 5 2 5 2 1 Module Management The term Module Management Controller MMC describes an IPMI Baseboard Management Controller BMC located on a PICMG compliant AMC module The MMC is the essential part of the MIC 5603 AMC module It is implemented on NXP s ARM Cortex M3 LPC1768 controller and acts as standard IPMI management control ler with additional AMC functionality extensions Main tasks are the module healthy monitoring voltage and temperature sensors hot swap state management partici pation AMC information data storage and providing several IPMI communication interfaces IPMI Interfaces The MIC 5603 provides three main IPMI messaging interfaces to connect to the mod ules MMC These are the local IPMB bus IPMB L for basic communication with the Carrier Manager the LAN side band interface RMCP RMCP and the on board payload interface to x86 5 Figure 5 1 IPMI int
24. 2 5 12 1 5 12 1 1 In addition to the management controller reset types the AMC module also support payload resets The x86 system represents the payload of the MIC 5603 processor AMC module Payload cold reset A payload cold reset means hardware reset to the modules payload part similar to a power on reset Following events cause AMC payload cold resets Payload power activation after hot swap state change W The front panel reset button is pressed for a short period less than five sec onds The mandatory PICMG FRU Control Cold Reset IPMI command is send to the MMC IPMI BMC Watchdog events Control Alt Delete also known as the three finger salute a connected keyStandard operating system reset commands e g Linux reboot SOL setup Serial over LAN SOL is an extension to IPMI over LAN IOL and allows to transmit serial data via LAN in addition to IPMI commands verify Chapter 5 1 IPMI Inter faces LAN It s defined in the IPMI v2 0 specification and based on the pro tocol to encapsulate serial data in network packets and exchange them via LAN With the help of SOL user can connect to a virtual serial console e g payload x86 system from remote SOL can be used on MIC 5603 for serial based OS and pre OS communication over LAN e g OS command line interface and serial redirected BIOS menu Preconditions for SOL Supported LAN interfaces Three of MIC 5603 s Ethernet inte
25. 2 2410 3 5603 BIOSS 0 10 0 08 4 5603 NVRAMM 0 03 um n Component requires Payload Cold Reset After a successful upgrade the new backup version should be the former active ver sion if Backup versions are supported And the new Active version should be the version of the used upload file MIC 5603 User Manual 76 IPMI PICMG Command Subset Supported by MMC IPM Device Global Commands A 1 Standard IPMI Commands v2 0 IPMI Advantech Command v2 0 cmp Module Req MMC Req Ref support Get Device ID 20 1 App Oih Mandatory Mandatory Yes Cold Reset 20 2 App 02h Optional Optional Yes Warm Reset 20 3 App 03h Optional Optional Yes Get Self Test Results 20 4 App 04h Mandatory Optional Yes Manufacturing Test On 20 5 App 05h Optional Optional No Set ACPI Power State 20 6 App 06h Optional Optional Get ACPI Power State 20 7 App 07h Optional Optional No Get Device GUID 20 8 App 08h Optional Optional Yes Broadcast Get Device Optional ID 20 9 App 01h Mandatory Mandatory Yes BMC Watchdog Timer Commands IPMI Advantech Command v2 0 cmp PMIBMC Module R Req MMC Req ef support Reset Watchdog Timer 27 5 App 22h Mandatory Optional Yes Set Watchdog Timer 27 6 App 24h Manda
26. 2 PUTTY 15 Figure 3 3 MIC 5603 BIOS POST Shown on PuTTY Screen 16 AMI BIOS 5 17 EET 18 Figure 4 1 Setup Program Initial 18 isi 19 Figure 4 2 Press DEL to Run Setup 19 I 20 Figure 4 3 Main Setup 20 4 3 1 System Time and System Date 20 Advanced BIOS Feature 21 vii MIC 5603 User Manual 4 5 4 6 4 7 4 8 MIC 5603 User Manual Figure 4 4 Advanced BIOS Features Setup Screen 21 4 4 1 Launch PXE OpROM 0 21 Figure 4 5 Launch PXE 21 4 4 2 PCI Subsystem Setting sse 22 Figure 4 6 PCI Express subsystem settings 22 4 4 8 23 Figure 4 7 ACPI 23 4 4 4 Trust Computing sssssssesseseeeneeee nennen 24 Figure 4 8 Trust 24 4 4 5 CPU 25 Figure 4 9 CPU Configuration see 25 4 4 6 SATA Configuration 26
27. 3h Mandatory Optional No Bridg Optional Get Event Destination ICMB 8 34h Mandatory Optional No Get Event Reception Bridg Optional State ICMB 35h Mandatory Optional No OEM Commands for Bridge NetFn IPMI Advantech Command v2 0 CMD ES MEC MMC Ref q q support OEM Commands 8199 Coh MERI ON Optional No Other Bridge Commands IPMI Advantech Command v2 0 NetFn CMD in BME 2 MMC Ref q 9 Error Report ICMB 2 Optional No 86 MIC 5603 User Manual IPMI Commands AdvancedTCA PICMG 3 0 R3 0 AdvancedTCA Base Specification PICMG Advantech Command 3 0 NetFn CMD Table a 9 f PICM Get PICMG Properties 3 11 G 00h Mandatory Yes Get Address Info oi N A No Get Shelf Address Info 3 16 GM 2 N A No Set Shelf Address Info 3 17 EUM 03h N A No FRU Control 3 27 04h Mandatory Yes Get FRU LED PICM Properties 3 29 G 05h Mandatory Yes Get LED Color PICM Capabilities 3 30 G 06h Mandatory Yes Set FRU LED State 3 31 a 07h Mandatory Yes PICM Get FRU LED State 3 32 G 08h Mandatory Yes Set IPMB State ooh N A No Set FRU Activation PICM Policy 3 20 G OAh N A No Get FRU Activation PICM Policy 3 21 G OBh N A No Set FRU Activation aia och N A No Ge
28. 75 1 575 1 65 1 74 V1 0 VOL 1 0 0 88 090 093 1 07 110 1 12 VO 85 VOL 0 85 0 71 0 765 080 00 0935 0 99 V1 05 VOL 1 05 0 88 0945 0 99 1 11 1 455 1 22 V3 3 VOL 3 30 290 315 345 360 1370 VCC RTC VOL 3 30 290 315 345 360 1370 47 MIC 5603 User Manual 5 3 2 2 5 3 3 5 3 3 1 5 3 3 2 5 3 3 3 5 3 3 4 5 3 3 5 Temperature sensors The MIC 5603 Processor AMC supports some temperature sensors either via board populated IC s e g TMP75 or readings from CPU Chipset interfaces PECI SMBus Table 5 4 Temperature sensor list Sensor Name Value LNR LCR LNC UNC UCR UNR REAR AMC TMP 25 15 10 5 65 75 85 OUTLET TMP 25 15 10 5 65 75 85 CPU TMP 40 15 10 5 80 90 105 PCH TMP 40 15 10 5 85 95 112 Note The PCH temperature sensors can only measure values greater equal 1044 degrees Discrete sensors MMC device locator Each MMC provides a PICMG compliant FRU device locator for the subsystem This record is used to hold location and type information of the MMC FRU hotswap sensor The MMC contains a PICMG compliant Hot Swap sensor inside it s sensor data repository BMC watchdog sensor The BMC Watchdog sensor is supported according to the Watchdog 2 sensor type listed in the IPMI specification FW progress sensor The MMC SDR contains a FW Progress sensor in order to support logging of the OS boot process Th
29. Get Chassis Status 28 2 Chassis 01 Mandatory Optional No i Optional Chassis Control 28 3 Chassis 02h Mandatory Optional Chassis Reset 28 4 Chassis 03h Optional Optional Chassis Identify 28 5 Chassis 04h Optional Optional No Set Front Panel Button Enables 28 6 Chassis No 2 28 7 Chassis 05h Optional Optional No 2 Mostara 28 8 Chassis 06h Optional Optional No Set Power Cycle Interval 28 9 Chassis OBh No mesian Chassis 07h Optional Optional No 2 Boot 24 Chassis 08h Optional Optional Bont cun Chassis 091 Optional Optional No Get POH Counter 2 Chassis OFh Optional Optional No Event Commands IPMI Advantech Command v2 0 Module MMC Req MMC Req Ref support Set Event Receiver 29 1 S E 00h Mandatory Mandatory Yes Get Event Receiver 29 2 S E Oih Mandatory Mandatory Yes Platform Event a k a Event Menon E 23 3 S E 02h Mandatory Mandatory Yes 80 MIC 5603 User Manual and Alerting Commands IPMI Advantech Command v2 0 PMIBMC Module Req MMC Ref support Get PEF Capabilities 30 1 S E 10h Mandatory Optional No S er Postpone 30 2 S E 11h Mandatory Optional No Set PEF Confi ti SS 30 3 S E 12h Man
30. H includes a four channel Enhanced Direct Memory Access EDMA controller offering low latency and high throughput data transfer capability with no CPU intervention for higher overall system performance It also integrates con troller features such as Serial ATA PCI and USB saving board real estate and power by removing the need for a separate legacy I O bridge chip For demanding 1 O and networking applications the PCle interfaces support for up to eight ports with transfers up to 5 GT s Refer to the following figure for the interfaces 7 MIC 5603 User Manual 2 2 4 2 2 5 2 2 6 Figure 2 1 INTEL QM67 Chipset Memory The 2nd Generation Intel Core Processor provides two channels of system memory with nine DDR3 SDRAMs per channel amp supports memory DDR3 data transfer rates of 1333MT S with ECC The 2nd Generation Intel Core Processor supports 1 Gbit and 2 Gbit and 4Gbit memory technologies However according to product options the MIC 5603 uses 18 pieces of either 2 Gbit 256 Mb x 8 or 4Gbit 512Mb x 8 SDRAMs with total capacity of 4GB or 8GB respectively Ethernet Controller The MIC 5603 uses one Intel 82580EB LAN controller connected to the 2nd Genera tion Intel Core Processor through a PCle x4 interface to provide two GbE connec tions 1000BX to Port 0 amp Port 1 amp one GbE accessible on the AMC front panel via RJ45 port SATA Interface The QM67 PCH has two integrated SATA host cont
31. ITool source code can be downloaded from the official project page http ipmitool sourceforge net Built binaries and executable for Windows and Linux can be downloaded from the Advantech page in 2012 Q3 Additional drivers and tools which are useful on with MIC 5603 will be ready 2013 Q1 BSP Board Support Packag will be ready in 2013 Q1 MIC 5603 User Manual 92 93 MIC 5603 User Manual AD ANTECH Enabling an Intelligent Planet www advantech com Please verify specifications before quoting This guide is intended for reference purposes only All product specifications are subject to change without notice No part of this publication may be reproduced in any form or by any means electronic photocopying recording or otherwise without prior written permis sion of the publisher All brand and product names are trademarks or registered trademarks of their respective companies Copyright 2013 Advantech Co Ltd
32. MI FRU data areas the FRU stores 0 speci fication defined PICMG records These FRU records e g Module Current Require ments or E Keying information are mandatory for the AMC module functionality Please note that the PICMG FRU data records are essential for any AMC module Improper record data or wrong modifications can influence the correct activation and behavior of the AMC through the carrier manager FRU Information access commands The FRU device IPMI commands are supported by the MMC to read and write the AMC module FRU information Correct and board specific FRU data is programmed to each single module in factory Please be very careful using the regular IPMI FRU write command avoid if possible Wrong FRU data content could destroy the AMC payload functionality Example FRU data Below example shows a default MIC 5603 FRU data excerpt Board and Product Info areas using the Linux IPMItool root localhost ipmitool fru FRU Device Description Builtin FRU Device ID 0 Board Mfg Date Mon Jan 1 07 00 00 1996 Board Mfg Advantech Board Product 5603 Board Serial 1234567 Board Part Number MIC 5603 Product Manufacturer Advantech Product Name MIC 5603 Product Part Number MIC 5603 Product Version Al 03 Product Serial 1234567 53 MIC 5603 User Manual 5 5 E Keying Electronic Keying E Keying has been added to the PICMG 0 R2 0 Specifica
33. MM optional 10 LVDS AMM optional 11 LVDS AMM optional 12 LVDS FPGA 13 Extended LVDS FPGA 14 Options LVDS FPGA 15 UART FPGA UART MUX 5 17 FI2 LVDS AMM optional 18 Extended FI2 LVDS AMM optional 19 Options 2 LVDS AMM optional 20 FI2 LVDS AMM optional TCLKA Telecom Clock FPGA TCLKB Telecom Clock FPGA 1 Clocks Telecom Clock FPGA dem Telecom Clock FPGA FCLKA Fabric Clock PCH PCIe ref clock E Keying MIC 5603 User Manual 54 5 5 2 E keying channel states Users can read out the AMC E Keying channel states via IPMI Get AMC Port State command Below printout shows MIC 5603 channels with the open IPMItool device Grouping ID Type Extension Type Link Designator Channel Number Port Flag STATE Link Link Link Link device Grouping ID Type Extension Type Designator Channel Number Port Flag STATE Link Link Link Link Link device Grouping ID Type Extension Type Link Designator Channel Number Port Flag STATE Link Link Link Link Link device root localhost ipmitool picmg amcportstate getall AMC 0x00 1000BASE BX ETHERNET SerDES Gigabit 0x00 0x01 enabled AMC 0x00 1000BASE BX ETHERNET SerDES Gigabit 0x01 0x01 disabled AMC 0x00 Serial ATA STORAGE 0x02 0x01 disabled AMC
34. MTBF Mean Time Between Failures NCSI Network Controller Sideband Interface NVRAM Non Volatile Random Access Memory OOS Out Of Service PATA Parallel Advanced Technology Interface PCH Platform Controller Hub PCle PCI Express PICMG PCI Industrial Computer Manufacturers Group PXE Pre boot Execution Environment RX Receive RMCP Remote Management Control Protocol SATA Serial Advanced Technology Attachment SDR Sensor Data Record SerDes Serializer Deserializer SOL Serial Over LAN SPI Serial Peripheral Interface TPM Trusted Platform Module TX Transmit UART Universal Asynchronous Receiver Transmitter MIC 5603 User Manual vi Contents Chapter Chapter Chapter Chapter 1 N gt 2 2 1 2 2 3 3 1 3 2 3 3 4 1 4 2 4 3 4 4 Product Overview PITOCUCTION p 2 APDIICAUIONS m et 2 Functional Block 2 2224 000 3 Figure 1 1 5603 Block Diagram 3 Board Specification 5 Technical Data RE 6 Table 2 1 Advantech MIC 5603 Processor AMC Technical 6 Prod ct Features es 7 ius a eee 7 Table 2 2 Intel Processor Selec
35. NLY be used if the COM1 MUX is set to SOL 0x01 If the COM1 MUX has any other settings than SOL is permanently fixed to SOL and the COM2 MUX OEM command setting is ignored Read COM port UART MUX setting ipmitool raw 0x2e 0x41 0x39 0x28 0x00 0x08 port Response 39 28 00 setting Change COM port UART MUX setting ipmitool raw 0x2e 0x40 0x39 0x28 0x00 0x08 port setting Response 39 28 00 MIC 5603 User Manual 58 5 6 5 Read Port 80 BIOS POST Code OEM command 5 6 6 5 6 7 To be able to read out the actual BIOS boot state via IPMI the MMC provides an Advantech OEM command to reflect the actual BIOS POST Port 80 code ipmitool raw 0 2 0x80 0x39 0x28 0x00 Response 39 28 00 POST Code Clear NVRAM data OEM command The MMC implements an OEM command to be able to clear the BIOS settings in NVRAM from SW side without the need of extracting the AMC module and perform ing any jumper plug and re plug This command can be used to load the default BIOS settings ipmitool raw 0 2 0x81 0x39 0x28 0x00 Response 39 29 00 MAC address mirroring OEM command The AMC module LAN Controller MAC addresses will also be stored in the FRU EEPROM making the MAC s available even if the payload is not powered This helps to relate the MAC address and the physical logical AMC module location The MIC 5603 board is equipped wit
36. RADIue _ _ IRRT Only on eSATA IRRT volume can span internal SATA drives and external SATA drives 4 4 7 Intel Trusted Execution Technology Display Intel Trusted Execution Technology configuration COM4 21061 Figure 4 11 Intel Trusted Execution Technology configuration menu 27 MIC 5603 User Manual Jadeuy dnies Sold IINV 4 4 8 Intel FW configuration Display Intel FW configuration PuTTY Setup hy 10 Aptic Advanced Utility Copyright 7 1 14 1107 Normal Mode Full Sku Firmware 5MB ME FW Version ME Firmware Mode ME Firmvare Type ME Firmware SKU 2010 American Megatrends Configure Management Engine Technology Parameters 1 gt lt Select Screen v Select Item Enter Select Change Opt F1 General Help F2 Previous Values F3 Optimized Defaults F4 Save amp Exit ESC Exit Figure 4 12 Intel Management Engine firmware configuration menu 4 4 9 USB Configuration This is a display only function providing general information about the USB module and the USB devices detected COMA PuTTY USB Configuration USB Devices 2 Hubs EHCI Hand off Disabled USB hardvare delays a USB transfer time out Device reset time out Device power up delay 20 sec 20 sec Auto Enables Legacy USB Support AUTO option disables legacy support 112 no USB devices a
37. T implementation The MIC 5603 FPGA implements two different kinds of UART s The real UART isa 16550 compatible UART with complete RS232 serial interface support An UART multiplexer MUX is used to connect the main serial interfaces front panel microUSB connector and AMC connector Port15 to the real UART The virtual UART is only used for Serial over LAN SOL and not fully 16550 com patible Means it only has a 16550 compatible register interface for x86 but a reduced FIFO interface for the MMC access only An access multiplexer is used to avoid that SOL and the serial interface is fixed to a specific COM port IO address range It allows to swap the COM port functionality with help of IPMI commands verify Chapter 5 6 OEM Commands for details MIC 5603 User Manual 60 5 7 3 5 8 5 8 1 5 8 2 Limitation Because there s only one real UART to x86 available users can only connect to one physical serial interface at the same time Below table gives a quick overview about the supported UART MUX combinations Table 5 13 port usage combinations Serial Interface COM1 COM2 MicroUSB SOL Supported Function eae uL SOL MicroUSB SOL AMC Port15 Caution COM is the serial interface with higher priority COM2 can ONLY be routed to the real UART serial interfaces front panel microUSB A AMC Port15 if COMI is set to SOL If COM1 has access to the real UART any other setting t
38. ame Versions Upload Progress Upload Image Active Backup File 10 50 100 Time Size H F H ee 1 5603 MMC 0 222 9 20 90 24 02 16 39d60 Firmware upgrade procedure successful MIC 5603 User Manual 70 6 2 2 Activate MMC firmware 6 3 6 3 1 Although the new MMC FW is successfully downloaded to the board called deferred version it needs to be activated before it will be functional Use following HPM 1 command root localhost ipmitool hpm activate PICMG HPM 1 Upgrade Agent 1 0 2 Waiting firmware activation OK The front panel FRU LED s 1 and 2 red OOS and green payload LED are flashing during the FW update activation This procedure needs around 60 seconds to finalize the update FPGA configuration upgrade Load new FPGA image Type IPMItool HPM 1 upgrade command and select the new FPGA image root localhost ipmitool hpm upgrade mic5603_standard_hpm_fpga_02_12 img PICMG HPM 1 Upgrade Agent 1 0 2 Validating firmware image integrity OK Performing preparation stage Services may be affected during upgrade Do you wish to continue y ny OK Performing upgrade stage ID Name Versions Upload Progress Upload Image Active Backup File 10 50 100 Time Size H H H 2 5603 FPGAA 2 10 2 08 2 12 3bf70 Component requires Pay
39. annel 0 IPMB O default interface parameter can be skipped Remote target address MMC IPMB L address to which requests should be bridged by the Carrier Manager b 7 Remote target channel 7 IPMB L lt Auth type gt T lt CM IPMB Address gt 0 t lt MMC IPMB Address gt KCS The Keyboard Controller Style KCS protocol is used as IPMI system interface con nection to the x86 part on MIC 5603 It is based on the Low Pin Count LPC bus And it is used as the local MMC interface to BIOS and the Operating System OS on the Processor AMC KCS is a fast IPMI interface compared to IPMB but requires active payload IPMI driver support is needed to be able to use the IPMItool from OS level via the KCS MMC interface refer to Appendix B Driver and Tools With working IPMI driver the MMC can be accessed easily from OS via KCS No interface parameters are needed at all to use the local onboard IPMI connection ipmitool lt Command gt LAN The IPMI LAN Interface on MIC 5603 is accomplished by using a shared LAN Con troller together with the x86 system In addition to systems PCI Express link a LAN controller side band interface Network Controller Sideband Interface short NC SI is connected to the MMC This NC SI channel is used by the MMC to receive and trans mit IPMI management traffic from and to network with help of the LAN controller IPMI over LAN IOL uses the Remote Management Control Protocol RMCP speci
40. apter helps to clar ify the used naming and the differences between the available resets Module management controller resets The MIC 5603 MMC support two different resets types cold and warm resets accord ing to the IPMI specification MMC cold reset The cold MMC reset causes default setting of all internal and external data states e g message buffers interrupt settings sensor and event configurations E keying port states and FRU LED states and power up defaults to be restored Following events lead to MMC cold resets m When the MMC is powered on a cold MMC reset is performed W Incase management power drops below some critical value the MMC is cold reset When the management power returns to its normal value the MMC is brought out of reset 63 5603 User Manual W Another example for the cold reset scenario is if the internal watchdog timer of the MMC expires and reset the MMC m User can force a MMC cold reset by pressing the front panel reset button for more than five seconds W Finally a cold reset can also be executed by software with help of the standard IPMI Cold Reset command 5 11 1 2 MMC warm reset The warm MMC reset is similar to cold reset but with additional preserved data states e g addresses enables and E keying port states On a warm reset which can be executed by a standard IPMI command the MMC firmware recovers its state from local memory 5 11 2 Payload reset 5 11 2 1 5 1
41. ated into many industrial and embed ded motherboards for over a decade This section describes the BIOS which has been specifically adapted to the MIC 5603 With the AMI BIOS Setup program you can modify BIOS settings and control the special features of the MIC 5603 The Setup program uses a number of menus for making changes and turning the special features on or off This chapter describes the basic navigation of the MIC 5603 setup Screens 1 PuTTY Aptio Setup Utility Copyrigt System Language Engiish Figure 4 1 Setup Program Initial Screen The BIOS ROM has a built in Setup program that allows users to modify the basic system configuration MIC 5603 User Manual 18 4 2 Entering Setup To run the BIOS setup menu simply press the DEL or F2 key on the USB key board when the boot up screen see Figure 4 2 appears following system power up x COM4 PuTIY Figure 4 2 Press lt DEL gt to Run Setup 19 MIC 5603 User Manual 4 3 4 3 1 Main Setup When you first enter the BIOS Setup Utility you will enter the Main setup screen You can always return to the Main setup screen by selecting the Main tab Two main setup options are described in this section The main BIOS setup screen is shown below Paul TY Aptio Setup Utility Copyright C 2010 American Megatrends BIOS Information Choose the system BIOS Vendor American Megatrends default language Core Version 4 6 4 0 0 10
42. ation menu 4 4 10 1 COMO Console Redirection Enabled 4 4 10 2 Pci Dev22 Func3 Console Redirection Enabled 29 MIC 5603 User Manual y Jajdeuy dnies 5019 INY 4 4 10 3 Serial Port for out of Band Management Windows Emergency Management 4 4 11 Services EMS Console Redirection Enabled Use this setting to add the SPCR table to the ACPI tables The OS can further use the information provided for serial redirection services m Out of Band Management COMO Microsoft Windows Emergency management Services EMS allows for remote man agement of a Windows Server OS though a serial port Data Bits This is a display only function providing information about the frame width for the Out of Band Management Parity This is a display only function providing information about the parity for Out of Band Management Stop Bits This is a display only function providing information about the number of stop bits for Out of Band Management Terminal Type VT UTF8 Use one of following settings to select the terminal type for out of band management VT100 VT100 VT UTF8 ANSI Sandy Bridge DTS Configuration This is a display only function providing information about Sandybridge DTS configu ration 27 COMA PuTTY TRY Disabled 1 Figure 4 15 Processor Digital Thermal Sensor setting MIC 5603 User Manual 30 4 4 12 Sandybridge PPM Configurat
43. configuration parameters for a given channel root localhost ipmitool lan print Set in Progress Set Complete Auth Type Support NONE MD5 PASSWORD Auth Type Enable Callback NONE MD5 PASSWORD User NONE MD5 PASSWORD Operator NONE MD5 PASSWORD Admin NONE MD5 PASSWORD OEM IP Address Source Static Address IP Address 192 168 21 1 Subnet Mask 2 255 255 255 0 MAC Address 00 0b ab 3e 45 87 Default Gateway IP 0 0 0 0 RMCP Cipher Suites e Or 125 lr oy LL12 Cipher Suite Priv Max aaaaaaaaaXXXXXX X Cipher Suite Unused C CALLBACK u USER a ADMIN 65 MIC 5603 User Manual lan set channel command option This command can be used to change several MMC LAN parameters e g IP address netmask gateway IP address Below example demonstrates how to change the MMC IP address root localhost ipmitool lan set 5 ipaddr 172 21 35 104 Setting LAN IP Address to 172 21 35 104 5 12 2 2 User commands user list Get the list of all supported users root localhost ipmitool user list ID Name Callin Link Auth IPMI Msg Channel Priv Limit 1 true true true NO ACCESS 2 callback true true true NO ACCESS 3 user true true true NO ACCESS 4 operator true true true NO ACCESS user set name user id username This command can be used to change the user name root localhost ipmitool u
44. ctions include B MMC Firmware FPGA Configuration E BIOS Image E NVRAM Image BIOS Settings 6 1 1 preconditions 6 1 1 IPMItool Before upgrading users need to prepare a HPM 1 capable update utility Advantech recommends to use the open and verified IPMItool gt version 1 8 10 In general any tool compliant to the PICMG HPM 1 R1 0 specification can be used 6 1 2 Interfaces HPM 1 provides a way to upgrade firmware via different interfaces verify Chapter 5 1 IPMI interfaces The MIC 5603 Processor AMC supports following IPMI interfaces m KCS local payload interface active payload and OS support needed m IPMB L remote bridged via Carrier Shelf Manager independent of payload W LAN interface remote active payload required The upgrade procedures in the following chapters are described with the help of KCS since this is the easiest method Using LAN or IPMB is similar only the IPMI tool interface parameters which need to be used are different 6 2 MMC firmware upgrade 6 2 1 Load new MMC firmware image Type IPMItool HPM 1 upgrade command and select the new MMC firmware image root localhost 1 ipmitool upgrade mic5603 standard hpm fw 00 24 img PICMG HPM 1 Upgrade Agent 1 0 2 Validating firmware image integrity OK Performing preparation stage Services may be affected during upgrade Do you wish to continue y n y OK Performing upgrade stage ID N
45. datory Optional No Get PEF Confi ti BER guration 304 S E 13h Mandatory Optional No 2 Processed 30 5 S E 14h Mandatory Optional No EE Processed 30 6 S E 15h Mandatory Optional No Alert Immediate 30 7 S E 16h Optional Optional No PET Acknowledge 30 8 S E 17h Optional Optional No Sensor Device Commands IPMI Advantech Command v2 0 cmp PMIBMC Module Req MMC Req Ref support Get Device SDR Info 35 2 S E 20h Optional Mandatory Yes Get Device SDR 35 3 S E 21h Optional Mandatory Yes R Device SDR Hepusllo 35 4 S E 22h Optional Mandatory Yes Sd Reading 35 5 S E 23h Optional Optional No Set Sensor Hysteresis 35 6 S E 24h Optional Optional No Get Sensor Hysteresis 35 7 S E 25h Optional Optional No Set Sensor Threshold 35 8 S E 26h Optional Optional Yes Get Sensor Threshold 35 9 S E 27h Optional Optional Yes Event oH S E 28h Optional Optional Yes ee Event 5 29h Optional Optional Yes Re arm Sensor Events ae S E 2Ah Optional Optional Yes Event gt S E 2Bh Optional Optional Yes Get Sensor Reading S E 2Dh Mandatory Mandatory Yes Set Sensor Type 2i S E 2Eh Optional Optional No Get Sensor Type en S E 2Fh Optional Optional No 81 MIC 5603 User Manual FRU Device Commands Advantech Command E V20 NetFn E BM ans MMC i support
46. dware Prefetcher Enable The Processor has a hardware prefetcher that automatically analyzes its require ments a prefetched data amp instructions from the memory into the Level 2 cache This reduces the latency associated with memory reads 4 4 5 7 Adjacent cache line P Enable The processor has a hard ware adjacent cache line prefetch mechanism that auto matically fetched an extra 64 byte cache line whenever the processor requests for a 64 byte cache line this reduces cache latency by making the next cache line immedi ately available if the processor requires it as well 25 MIC 5603 User Manual Joydeuy dnies SOIG INY 4 4 5 8 Intel Virtualization This function is used to enable a Virtual Machine Manager VMM to utilize the addi tional hardware capabilities provided by the Vanderpool Technology To change the state of this function a hardware reset is necessary 4 4 6 SATA Configuration This is a display only function indicating if a device is connected to the corresponding port If no device is connected the functions indicate Not Present Otherwise they show the device s built in reference name followed by the device s size if the device is a hard drive Enable or disable SATA SATA Mode Selection AHCI Device SATA Test Mode Disabled Aggressive LPM Suppor Enabled gt Softvare Feature Mask Configuration 1 1 1 1 Serial Port 0 Empty Software Preserve Unknown Port 0 Enabled 1
47. e MMC supports adding and forwarding of SEL entries from the BIOS OS system firmware progress events by sending Add sel entry commands with the matching sensor type to the MMC through the KCS interface Version change sensor A Version Change sensor is supported according to the IPMI specification MIC 5603 User Manual 48 5 3 4 5 3 5 5 3 5 1 5 3 5 2 Example sensor data Below example shows a MIC 5603 sensor reading list printed with the open source IPMItool root localhost ipmitool sdr elist all MIC 5603 00h ok 193 98 Dynamic MC 20h HOTSWAP 01 193 98 Module Handle Closed MP VOL 02h ok 193 98 3 24 Volts V12 VOL 03h ok 193 98 12 22 Volts V5 0 VOL 04h 193 98 4 98 Volts V0 75 VOL 05h ok 193 98 0 74 Volts V1 8 VOL 06h 193 98 1 79 Volts V1 5 VOL 07h ok 193 98 1 50 Volts V1 0 VOL 08h 193 98 1 01 Volts V0 85 VOL 09h ok 193 98 0 87 Volts V1 05 VOL OAh ok 193 98 1 03 Volts V3_3 VOL OBh ok 193 98 3 26 Volts VCC RTC VOL OCh ok 193 98 3 22 Volts REAR AMC TMP ODh ok 193 98 30 degrees C OUTLET TMP OEh 193 98 32 degrees CPU TMP 193 98 45 degrees PCH TMP 10h 193 98 44 degrees C INTEGRITY 11h ns 193 98 Disabled BMC WATCHDOG 12h ok 193 98 FW PROGRESS 13h ok 193 98 VERSION CHANGE 14h ok 193 998 Integrity sensor Overview The Advantech Integrity Sensor is an OEM sensor according to the SDR Sensor Data Record
48. e connected to the MMC sensor part Moreover the MMC Management Subsystem also registers below logical sensors m PICMG Hot Swap sensor m BMC Watchdog sensor m FW Progress sensor m Version change sensor m Advantech OEM Sensor Integrity Sensor 5 3 1 Sensor list All sensors available on the MIC 5603 Processor AMC are listed in the table below inclusive FRU Device Locator record Table 5 1 Sensor list No Sensor ID Description 0 MIC 5603 IPMI FRU Device Locator 1 HOTSWAP Hot Swap Discrete Module Hot Swap sensor 2 MP VOL Voltage Threshold AMC Management Power 3 3V 3 V12 VOL Voltage Threshold AMC Payload Power 12V 4 V5 0 VOL Voltage Threshold AMC Board 5 0V voltage 5 VO 75 VOL Voltage Threshold AMC Board DDR3 VTT voltage 6 V1_8 VOL Voltage Threshold AMC Board 1 8V voltage 7 V1_5 VOL Voltage Threshold AMC Board 1 5V voltage 8 V1 0 VOL Voltage Threshold AMC Board 1 0V voltage 9 VO 85 VOL Voltage Threshold AMC CPU 0 85V voltage 10 1 05 VOL Voltage Threshold AMC Board 1 05V voltage 11 V3_3 VOL Voltage Threshold AMC Board 3 3V voltage 12 VCC RTC VOL Voltage Threshold AMC RTC supply voltage 13 REAR AMC TMP Temperature Threshold 8081 temperature close to 14 OUTLET TMP Temperature Threshold Board Outlet temperature 15 Temperature Threshold temperature 16
49. ea leve above sea level MIC 5603 User Manual 2 2 2 2 1 2 2 2 2 2 3 UL94V0 FCC Class CE RoHS amp WEEE Ready PER NEBSLevel3 Designed for GR 63 CORE and GR 1089 CORE PICMG 0 1 2 AMC 3 2 0 Compliance Standards HPM 1 Product Features CPU The MIC 5603 supports the low wattage Intel 2nd Generation Core i7 mobile pro cessors on 32nm technology with core frequencies up to 2 2 GHz and 5 0 GT s point to point DMI interface to PCH These processors are validated with the integrated Intel QM67 PCH This chipset provides greater flexibility for developers of embedded applications by integrating the memory and l O control functions into a single compo nent addressing the needs for high performance high reliability and low power con sumption within a small form factor such as the MIC 5603 Current supported processors are listed in the table below Table 2 2 Intel Processor Selection for the MIC 5603 Model Core Speed DMISpeed Intel Smart Cache Intel Core i7 2655LE 2 2 GHz 5 GT s 4 25 W FCBGA1023 Intel Core i7 2610UE 1 5 GHz 5 GT s 4 MB 17W FCBGA1023 BIOS Two 8 MB SPI Flashes contain board specific BIOS from AMI designed to meet telecom and embedded system requirements The BIOS boot sector contains the early start up code Chipset The 67 PC
50. enipmi sourceforge net The Open IPMI Linux device driver is designed as a full function IPMI device driver with the following features Allows multiple users Allows multiple interfaces Allows both kernel and userland things to use the interface Fully supports the watchdog timer It works like IPMI drivers are supposed to It tracks outgoing messages and matches up their responses automatically It automatically fetches events received messages etc It supports interrupts 1 have tested them now It has backwards compatability modules for supporting the Radisys driver and the Intel IMB driver It s modular You don t have to have the standard userland interface You don t have to have the watchdog Etc It supports generating an event on a panic More information regarding the IPMI driver can be found on the OpenIPMI Project page http openipmi sourceforge net The KCS register interfaces are at OxCA2 OxCA3 and used by the OpenIPMI driver as default B 2 IPMITool The IPMITool provides an easy to use set of functions and commands to access the MMC via the KCS interface within the Operating System of the MIC 5603 or via Ethernet through NC SI from external The IPMI Tool also supports bridged IPMI commands to access the MMC if the carrier manager provides an IPMl over LAN interface See Chapter 5 for a more detailed description of different access methods and IPMITool calls The IPM
51. erfaces IPMB L Basic IPMI connection of an AMC MMC is the I2C based serial IPMB L interface routed to the AMC edge connector Once plugged in an AMC carrier bay and sup plied with management power the MMC discovers the slot connector Geographic Address GA The GA is used to assign a unique IPMB address according to the AMC site number With this IPMB L address the MMC is able to communicate with the connected AMC Carrier Manager The main benefit of the IPMB L interface is the independence from payload state means it can be used at any time The open source IPMItool can be used to access the MMC via IPMB L Access to the local MMC to CM connection can only be achieved with help of Carrier Manager Shelf Manager interfaces IPMItool supports bridge commands to bypass the Car rier and Shelf Managers environments Below example shows double bridged access to IPMB L ipmitool I lan H ShMC IP Address A Auth type T CM IPMB Address B 0 t MMC IPMB Address b 7 Command MIC 5603 User Manual 44 5 2 2 5 2 3 Command Line Syntax lan Specifies that Ethernet is used as Shelf Manager interface H ShMC IP Address address assigned to the Shelf Manager Authentication type depending on supported types by the Shelf Manager default NONE Remote transit address IPMB 0 address of Carrier Manager to which requests should be bridged by the Shelf Manager Remote transit ch
52. es not support other USB devices except bootable devices like CD ROM E drives and floppy disk drives 2 2 11 On board Storage Flash Chip An on board 8GB storage chip located on the CFast expansion mezzanine module is the single device solid state drives supports standard SATA protocol The built in microcontroller and file management firmware communicates with SATA standard interfaces It provides complete SATA Hard Disk Drive functionality and compatibility in a BGA package Note 16GB storage option is available for the NAND flash s capacity 2 2 12 CFast Expansion Module CFast expansion mezzanine module is a standard feature on the AMC The CFast card provides high capacity data storage that electrically complies with the Serial ATA International Organization standard amp Applications that demand low power Flash based CF consumes less than 5 percent the power of 1 8 and 2 inch disk drives And as the disk drive industry ends the manufacturing of PATA drives CFast becomes an attractive and less expensive alternative to SATA hard drives 2 2 13 Trusted Platform Module Optional As an option a Trusted Platform Module can be available on the board It provides single chip turnkey solution enabling high levels of hardware security and interoper ability while maintaining exceptional user convenience and privacy for embedded application It implements version 1 2 of the Trusted Computing Group specification for Trusted Platfo
53. es in a request and the first three data bytes fol lowing the completion code position in a response Advantech s IANA Enterprise Number used for OEM commands is 002839h The MIC 5603 MMC supports Advantech IPMI OEM commands listed in below table Table 5 8 command overview Command LUN NetFn CMD Store Configuration Settings 00h 2Eh 2Fh 40h Read Configuration Settings 00h 2Eh 2Fh 41h Read Port 80 BIOS POST Code 00h 2Eh 2Fh 80h Clear NVRAM data 00h 2Eh 2Fh 81h Read MAC Address 00h 2Eh 2Fh E2h Load Default Configuration 00h 2Eh 2Fh F2h IPMItool raw command To be able to use the Advantech OEM commands with the open source IPMItool users have to employ the raw command of IPMItool Please find below command structure details of the IPMItool raw command General raw request ipmitool raw netfn cmd data Response if raw lt netfn gt is 2Eh OEM Group lt IANA Enterprise Number data Configuration setting OEM commands The Read and Store Configuration OEM commands can be used to read and change several important board settings The following sub chapters describe the needed command details MIC 5603 User Manual 56 5 6 3 5 6 3 1 LAN controller interface selection The MMC firmware provides an OEM IPMI command to allow users to switch the MMC connected NC SI interface between one front panel LAN IO RJ 45 connector and the AMC connector
54. fety Instructions gt D Read these safety instructions carefully Keep this User Manual for later reference Keep this equipment away from humidity Put this equipment on a reliable surface during installation Dropping it or letting it fall may cause damage All cautions and warnings on the equipment should be noted Never pour any liquid into an opening This may cause fire or electrical shock Never open the equipment For safety reasons the equipment should be opened only by qualified service personnel If one of the following situations arises get the equipment checked by service personnel The power cord or plug is damaged Liquid has penetrated into the equipment The equipment has been exposed to moisture The equipment does not work well or you cannot get it to work according to the user s manual The equipment has been dropped and damaged The equipment has obvious signs of breakage DO NOT LEAVE THIS EQUIPMENT IN AN ENVIRONMENT WHERE THE STORAGE TEMPERATURE MAY GO BELOW 20 C 4 F OR ABOVE 60 C 140 F THIS COULD DAMAGE THE EQUIPMENT THE EQUIPMENT SHOULD BE IN A CONTROLLED ENVIRONMENT The sound pressure level at the operator s position according to IEC 704 1 1982 is no more than 70 dB A DISCLAIMER This set of instructions is given according to IEC 704 1 Advantech disclaims all responsibility for the accuracy of any statements contained herein Product C
55. ge Compact Flash On CF Module Module with CFast socket 8 default or 16 GB industrial grade internal flash disk optional SATA Interface AMC Edge Con nector Two SATA interfaces 6Gbps to common option ports 2 3 Other One SATA routed to CF daughter board Routed to front panel as USB Slave interface through Senalinienace onboard USB to Serial converter USB Interface lO One USB 2 0 compliant host port standard USB Con nector on front panel Watchdog Timer Supervision One MMC watchdog One payload watchdog Management Controller NXP LPC 1768 Controller Compliancy 2 0 Source Code Advantech IPMI Core Firmware Update Standard HPM 1 compliant Operating Sys WindRiver PNE LE 3 0 RHEL CentOS Windows tem Server 2008 Windows 7 Enterprise Mid size or Full size Interface AMC 0 compliant Miscellaneous LEDs blue for hot swap x1 red for failure and OOS x1 green for general purpose Intel Core i7 2610UE QM67 8GB on board DDR Power Require Configuration memory ment Consumption 40 watts Physical Dimension 180 6 mm x 73 5 mm Operating Non operating Temperature S9 les USA 40 140 F Note Humidity 60068 2 78 95 RH 40 C Environment Vibration 5 500Hz 60068 2 6 0 002 G2 Hz 1 Grms Shock IEC60068 2 27 10 G 11 ms Altitude Sea level tO QUDIR 10 000m above s
56. h 5 MAC addresses in total Please find below the used order in the FRU EEPROM Internal Use Area Table 5 12 address mapping table MAC Number LAN Interface 0 AMC port 0 0 82580 MAC 0 1 AMC port 1 1 82580 MAC 1 2 FP LAN 1 IO 0 82579 MAC 3 FP LAN 2 IO 1 82580 MAC 3 4 MMC MAC Read MAC Address OEM command ipmitool raw 0 2 0xe2 0x39 0x28 0x00 MAC Number gt Response 39 28 00 MAC Address 59 MIC 5603 User Manual 5 6 8 5 7 5 7 1 5 7 2 Load default configuration OEM command Several configurations settings are provided by the MMC To reset all of them to their default values a single OEM command is available to perform this with only one IPMI command ipmitool raw 0 2 OxF2 0x39 0x28 0x00 Response 39 28 00 UART and UART Multiplexer The x86 subsystem of MIC 5603 has access to 2 UARTs implemented insight the FPGA These UARTS are 16550 compatible and mapped to the standard address ranges Ox2F8 0x2FF and 0x3F8 0x3FF This chapter gives an overview of the imple mentation details and the resulting use cases UART block diagram UART SWAP PORT SELECT Micro r USB COM1 Lo de und an See Portts l 2 Virtual Data for SoL COM default routing 2 default routing Figure 5 2 UART functional block overview UAR
57. han SOL COM2 is permanently fixed to SOL Hot swap ACPI Hot swapping the MIC 5603 means to plug and remove the AMC Module from a sys tem AMC Carrier while the power is still on and the system is still operating If the MIC 5603 will be removed from a powered system the MMC need to interact with the payload to safely shut down the payloads operating system OS This chapter describes the supported ACPI mechanism to achieve this on the Processor AMC ACPI featured graceful shutdown Note payload OS used with MIC 5603 need to support ACPI to benefit from the module graceful shutdown feature If there s shutdown request e g hot swap front panel handle open event or IPMI FRU Deactivate command the MMC will initiate the OS shutdown with help of the ACPI Power Button signal routed to the x86 system The ACPI daemon running on the payload OS start to shutdown the system once it detects the ACPI event At the time the OS shutdown is finished the payload will indicate the achieved sleep state to the MMC Last step for the MMC is to forward this information to the Carrier Manager quiesced hot swap event who will power off the AMC payload subse quently Graceful shutdown timeout A Graceful Shutdown timeout is implemented for payload operating systems without ACPI support or in case the shutdown process is not finished no active x86 sleep state If the MMC does not get the activated sleep state signal w
58. iguration Change Opt Sandybridge PPM Configurationll F1 General Help F2 Previous Values F3 Optimized Defaults F4 Save amp Exit ESC Exit Figure 4 5 Launch OpROM Disabled Use this setting to ignore all PXE Option ROMs Enabled Use this setting to load PXE Option ROMs To limit the PXE support to par ticular devices 21 MIC 5603 User Manual 4 4 2 4 4 2 1 4 4 2 2 4 4 2 3 4 4 2 4 4 4 2 5 PCI Subsystem Setting This screen provides functions for specifying the PCI Express device settings i M iar sh oa eee as Figure 4 6 PCI Express subsystem settings Relaxed Ordering Relaxed ordering allows certain transactions to violate the strict ordering rules of PCI that is a transaction may be completed prior to other transactions that were already enqueued Extended Tag When set this bit enables a Function to use an 8 bit Tag field as a Requester If the bit is Clear the Function is restricted to a 5 bit Tag field No Snoop If this bit is set the function is permitted to set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency Maximal Payload Packet size from 128Bytes to 4092Bytes Minimal Read Request Packet size from 128Bytes to 4092Bytes ASPM Support This feature allows power
59. image is not directly written to any of the BIOS SPI flashes The BIOS settings are stored in the external SPI flash of the MMC to support deferred activation For extended flexibility the external SPI flash supports different sections to store up to four BIOS setting images at the same time Each of these four NVRAM images can be set to active at any time and will be copied to the active BIOS flash at the next OS boot Select NVRAM upgrade section optional As described above the MMC provides multiple upgrade sections for different NVRAM images An IPMI OEM command verify Chapter 5 6 OEM Commands for details can be used to select the one of the BIOS setting sections in the external flash root localhost ipmitool raw 0x2E 0x40 0x39 0x28 0x00 0x03 0x01 section Default section for a NVRAM update is section zero if the OEM command is not used MIC 5603 User Manual 74 6 5 2 6 5 3 6 5 3 1 6 5 3 2 Load new NVRAM image Type IPMItool HPM 1 upgrade command and select the new NVRAM image root localhost ipmitool hpm upgrade mic5603 standard hpm nvram 00 03 img PICMG HPM 1 Upgrade Agent 1 0 2 Validating firmware image integrity OK Performing preparation stage Services may be affected during upgrade Do you wish to continue y n y OK Performing upgrade stage ID Name Versions Upload Progress Upload Image Active Backup File 10 50 100 Time Size
60. ion Figure 4 16 Processor PPM configuration menu 4 4 12 1 EIST Enabled Enable or Disable Intel Speedstep 4 4 12 2 Turbo Mode Enabled Enable or Disable Intel Turbo Mode 4 4 12 3 CPU C3 Report Enabled Enable or Disable CPU C3 report to SO 4 4 12 4 CPU C6 Report Enabled Enable or Disable CPU C6 report to SO 4 4 12 5 CPU C7 Report Enabled Enable or Disable CPU C7 report to SO 4 4 12 6 Long Duration power limit 0 Long duration power limit in watts 0 means use factory default 4 4 12 7 Long Duration power maintained 28 Time window which long duration power is maintained 4 4 12 8 Short Duration power limit 0 Short duration power limit in watts 0 means use factory default 4 4 12 9 TCC active offset 0 Offset from the factory TCC activation temperature y Jaydeuy dnies 5019 INY 31 MIC 5603 User Manual 4 5 Chipset 4 5 1 System Agent SA Configuration Figure 4 17 System Agent configuration menu 4 5 1 1 VT d Enabled Check to enable VT d function on CPU 4 5 1 2 CHAP Device BO D7 F0 Disabled Enable or disable SA CHAP Device 4 5 1 3 Thermal Device B0 D4 Disabled Enable or disable SA Thermal Device 4 5 1 4 Enable NB CRID Disabled Enable or disable NB CRID Work Around MIC 5603 User Manual 32 4 5 1 5 Graphics Configuration COMA 7997 Setup I M Figure 4 18 Intel graphics engine
61. irmware image integrity OK Performing preparation stage Services may be affected during upgrade Do you wish to continue y n y OK Performing upgrade stage ID Name Versions Upload Progress Upload Image Active Backup File 10 50 100 Time Size H 3 156503 BIOSS 0208 90 09 0210 1 5 Rm 25 22 7 000 Component requires Payload Cold Reset Firmware upgrade procedure successful Activate BIOS image Although the new BIOS image is successfully loaded deferred version it needs to be activated before users can boot the new BIOS Following two actions are needed to finish the upgrade HPM 1 activate command Schedule the BIOS load with the HPM 1 Activate command root localhost ipmitool hpm activate PICMG HPM 1 Upgrade Agent 1 0 2 73 MIC 5603 User Manual 6 4 2 2 Payload cold reset 6 5 6 5 1 A payload cold reset is required to activate the new BIOS image Component requires Payload Cold Reset The payload reset can be performed through different ways W If the user is working on the local OS KCS a linux reboot poweroff or halt W If the user accesses the MMC through the other interfaces LAN IPMB a deac tivation and activation cycle is needed to load the new BIOS image NVRAM upgrade In contrast to the BIOS image update a BIOS setting NVRAM update
62. is hot swappable which allows it to be replaced by operators or service organizations in the field without bringing down an entire AdvancedTCA blade or system MIC 5603 User Manual 2 Chapter 1 1 3 Functional Block Diagram The hardware concept can be illustrated by the following functional block diagram Refer to table 2 1 for the product s detailed technical specification Product Overview Common options 3rd or 2nd Generation Intel Core Processor Intel QM67 Chipset UART MONITOR Sensor FRU E PROM Figure 1 1 MIC 5603 Block Diagram MIC 5603 User Manual MIC 5603 User Manual Board Specification This chapter describes the hard ware features of the MIC 5603 2 1 Technical Data Table 2 1 Advantech 5603 Processor Technical Data Intel 2nd Generation Core i7 mobile processors up to 2 2 GHz 4 L2 cache Processor Sys Chipset Intel QM67 tem AMI 1 Dual images with update rollback 2 NVRAM BIOS settings can be changed over IPMI and 3 CMOS backup works without battery Bus DMI 5 0 GT s point to point DMI interface to PCH Technology Dual channel DDR3 1066MT s and 1333MT s Memory SDRAM with ECC Max Capacity 8 GB RAM soldered on board memory Controller IntelR 82580EB Quad port Gigabit Ethernet controller Ethernet One GbE accessible on front panel via RJ 45 and two SerDes links to AMC ports 0 and 1 Mass Stora
63. item set the minimum assertion width of the SLP S4 signal to guarantee the DRAM has been safely power cycled Restore AC Power Loss Power On Select AC power state when power is re applied after a power failure MIC 5603 User Manual 38 4 6 Boot Configuration gt QD COMA Pal TY nen m D gt 02 O e c Figure 4 24 Boot configuration menu 4 6 1 Setup Prompt Timeout 1 Number of seconds to wait for setup activation key 65535 OxFFFF means indefinite waiting 4 6 2 Boot up NumLock State On Select the keyboard NumLock state 4 6 3 Quick Boot Disabled 4 6 4 CSM16 Module Version 07 64 Display CSM16 Module Version 4 6 5 Boot option priorities Built in EFI Shell 39 MIC 5603 User Manual 4 7 Security Administrator Password Figure 4 25 Security setup menu 4 7 1 Administrator Password Set setup Administrator Password 4 7 2 User Password Set User Password MIC 5603 User Manual 40 4 8 4 8 1 4 8 2 4 8 3 4 8 4 Save amp Exit 17 PuTTY Figure 4 26 Save and Exit menu Save changes and Exit Exit system setup after saving the changes Discard changes and Exit Exit system setup without saving the changes Save changes and Reset Reset the system after saving the changes Discard changes and Reset Reset the system without saving the changes 41 MIC 56
64. ithin the timeout value of 60 seconds it will report the quiesced hot swap event to the Carrier Manager anyway 61 MIC 5603 User Manual 5 9 5 9 1 5 9 2 5 9 3 5 9 4 BIOS failover redundancy Overview The MIC 5603 Processor AMC supports BIOS redundancy handled by the MMC Two BIOS SPI flashes are populated on the AMC module and BIOS redundancy is responsible to manage the flash failover if the actual selected BIOS fail to boot An example of use is a BIOS update over HPM 1 verify chapter x x x HPM 1 Updates If the BIOS HPM 1 update was done and the new BIOS version does not boot the MMC will switch back to the previous used BIOS version BIOS boot watchdog An IPMI compliant BMC Watchdog verify Chapter 5 10 Support watchdogs imple mented in the MMC is used to monitor the BIOS boot progress The MMC will initiate the BIOS SPI flash swap in case of a BMC Watchdog bite during BIOS execution e g selected BIOS corrupt MMC part The BMC Watchdog is programmed by MMC with a predefined timeout and started when payload power for the x86 subsystem is turned on payload reset detected The watchdog timeout action is configured to do a hardware reset and the timer use is set to BIOS If a BMC Watchdog timeout occurs with this configuration the BIOS flash failover is initiated by MMC It s followed by a x86 system reset and the watchdog timer restart BMC Watchdog timeout events are logged in the MMC System Eve
65. llocation Info 31 3 Storage 41h Optional Optional No Reserve SEL 31 4 Storage 42h Optional Optional Yes Get SEL Entry 31 5 Storage 43h Mandatory Optional Yes Add SEL Entry 31 6 Storage 44h Mandatory Optional Yes Partial Add SEL Entry 31 7 Storage 45h Mandatory Optional No Delete SEL Entry 31 8 Storage 46h Optional Optional No Clear SEL 31 9 Storage 47h Mandatory Optional Yes Get SEL Time 5 d Storage 48h Mandatory Optional Yes Set SEL Time a Storage 49h Mandatory Optional Yes See Log A d Storage 5Ah Optional Optional No Enn Ma Log a x Storage 5Bh Optional Optional No LAN Device Commands IPMI Advantech Command v2 0 PMIBMC Module Req MMC Ref support Set LAN Configuration Transp Optional Parameters 23 1 ort oth Mandatory Optional Yes Get LAN Configuration Transp Optional Parameters UE ort zen Mandatory Optional Yes Transp Optional Suspend BMC ARPs 23 3 ort 03h Mandatory Optional No Get IP UDP RMCP Transp Statistics 23 4 rt 04h Optional Optional No 83 MIC 5603 User Manual Serial Modem Device Commands Command 0 NetFn CMD E ENS MMC Esa MC Ten Ref support Set SeriaiModem Transp igh Optional optional No ase ee aah Pome Set Serial Modem Mux 25 3 ae 12h Optional Optional No oed Respon
66. load Cold Reset Firmware upgrade procedure successful 71 MIC 5603 User Manual 6 3 2 6 3 2 1 6 3 2 2 Activate FPGA configuration Although the new FPGA configuration is successfully stored on the board deferred version it needs to be activated before it s loaded into the FPGA chip Following two actions are needed to finish the upgrade HPM 1 activate command Schedule the FPGA load with the HPM 1 Activate command root localhost ipmitool hpm activate PICMG HPM 1 Upgrade Agent 1 0 2 Payload cold reset In order to activate the new FPGA image a payload cold reset is required Component requires Payload Cold Reset The payload reset can be performed through different ways W If the user is working on the local OS KCS a linux reboot poweroff or halt W If the user accesses the MMC through the other interfaces LAN IPMB a deac tivation and activation cycle is needed in order to update the FPGA The front panel FRU LED s 1 and 2 red OOS and green payload LED are flashing during the FW update activation This procedure needs around 200 seconds to final ize the update MIC 5603 User Manual 72 6 4 6 4 1 6 4 2 6 4 2 1 BIOS upgrade Load new BIOS image Type IPMItool HPM 1 upgrade command and select the new BIOS image root localhost ipmitool hpm upgrade mic5603 standard hpm bios 00 10 img PICMG HPM 1 Upgrade Agent 1 0 2 Validating f
67. nel Info ale App 42h Optional Optional Yes Set User Access 43h Optional Optional Yes Get User Access erie App 44h Optional Optional Yes Set User Name 875 45h Optional Optional Yes Get User Name 46h Optional Optional Yes Set User Password gs App 47h Optional Optional Yes Activate Payload 24 1 App 48h Optional Yes Deactivate Payload 24 2 App 49h Optional Yes Get Payload Activati 2 oac ACUVAUON laa UE App 4Ah Optional No n Payload Instance 24 5 App 4Bh Optional No Set User Payload 22 246 4Ch Optional Yes Get User Payload 2 247 4Dh Optional Yes Get Ch Payload SUDO ayoa 24 8 App 4Eh Optional No Get Ch Payload ayn 24 9 App 4Fh Optional No Get Channel OEM 24 1 Payload Info 0 App 50h Optional No Master Write Read aen App 52h Mandatory Optional Yes Get Ch Ciph 22 1 UGG SOUPE 5 App 54h Optional Yes Suspend Resume Payload Encryption 24 3 App 55h Optional No Set Ch IS it 22 2 Keys 56h Optional Yes Get System Interface Capabilities 22 9 App 57h Optional No 79 MIC 5603 User Manual Chassis Device Commands IPMI Advantech Command v2 0 CMD Module MMC Req MMC Req Ref support CDM 28 1 Chassis 00h Mandatory Optional No i Optional
68. nt Log SEL and BIOS failover details are stored in SEL via the Advantech Integrity Sensor verify Chapter 5 3 5 Integrity sensor BIOS participation Active involvement of BIOS in the redundancy mechanism is limited but necessary The BMC Watchdog status is changed by BIOS at the end of its execution transition to OS and if users enter the BIOS setup menu MIC 5603 User Manual 62 5 10 5 10 1 Supported watchdogs Firmware watchdog The FW Watchdog monitors the MMC functionality If the MMC hangs and stops exe cution the watchdog will not be restarted The watchdog bites after a timeout and resets the MMC to recover the controller from current error state Strobe Watchdog If the Watchdog is triggered the IPMB L is isolated from the controller The AMC Payload is not affected and the FRUs operational state stays untouched 5 10 2 BMC watchdog 5 11 5 11 1 5 11 1 1 The BMC Watchdog is full IPMI v2 0 Specification compliant It supports the following IPMI commands W Reset Watchdog Timer IPMI 2 0 Specification 27 5 Wm Set Watchdog Timer 2 0 Specification 27 6 Get Watchdog Timer 2 0 Specification 27 7 To ensure a high reliability of the MIC 5603 Payload the BMC Watchdog is enabled by default for BIOS monitoring The details are described in BIOS failover chapter Chapter 5 9 BIOS failover redundancy Resets Several different reset types are support by AMC modules This ch
69. oll back Automatic roll back if update failed W 1 for in field updates supporting MMC Firmware FPGA BIOS NVDATA BIOS settings Proven interoperability with different and ATCA vendors Specification compliance tested with Polaris Compliance Tester Automatic UART muxing between all serial interfaces for easy console access Additional sensors for hardware monitoring Integrated Clock Controller The PCH contains a Fully Integrated Clock Controller ICC generating various plat form clocks from a 25 MHz crystal source The ICC contains up to eight PLLs and four Spread Modulators for generating various clocks suited to the platform needs The ICC supplies up to ten 100 MHz PCI Express 2 0 Specification compliant clocks one 100 MHz BCLK DMI to the processor four 33 MHz clocks for SIO LPC TPM devices and four Flex Clocks that can be configured to various frequencies that include 14 318 MHz 33 MHz and 24 48 MHz for use with SIO LPC and discrete Graphics devices 9 MIC 5603 User Manual 2 2 10 Legacy USB Support The legacy USB support enables USB devices such as keyboards mice and hubs to be used even when the operating system s USB drivers are not yet available The legacy USB support allows the user to access the BIOS setup menu and install an operating system that supports USB The legacy USB support is set to Enabled by default Note legacy USB support is for keyboards mice and hubs only It do
70. onfigurations Model Number On Board Option MIC 5603AFZ M4E Full size front panel 4GB DDR3 with ECC AMC Mezzanine Mod ule with optional on board flash MIC 5603AFZ M8E Full size front panel 8GB DDR3 with ECC AMC Mezzanine Mod ule with optional on board flash MIC 5603AM M4E Mid size front panel 4GB DDR3 with ECC CFast module with optional on board flash MIC 5603AM M8E Mid size front panel DDR3 with ECC CFast module with optional on board flash We Appreciate Your Input Note E 1 CFast module is available as an option 2 Full size front panel design will be available upon request Please let us know of any aspect of this product including the manual which could use improvement or correction We appreciate your valuable input in helping make our products better V MIC 5603 User Manual Glossary AMC Advanced Mezzanine Card ATCA Advanced Telecommunications Computing Architecture BMC Baseboard Management Controller DMI Direct Media Interface ECC Error Checking and Correction EHCI Enhanced Host Controller Interface FRU Field Replaceable Unit FPGA Field Programmable Gate Arrays GbE Gigabit Ethernet HPM Hardware Platform Management IOL IPMI Over LAN IPMB Intelligent Platform Management Bus IPMC Intelligent Platform Management Controller IPMI Intelligent Platform Management Interface KCS Keyboard Controller Style MCH MicroTCA Carrier Hub MMC Module Management Controller
71. ormats This chip includes a complete USB 2 0 full speed function controller bridge control logic and a UART interface with transmit receive buffers and modem handshake signals For a terminal PC to bridge successfully to the console function on the MIC 5603 the CP2102 driver available for download from Silicon Laboratories website hyperlink below must be installed on the terminal PC for example running on Linux 2 4 or 2 6 Kernel or Windows XP https www silabs com products interface usbtouart Pages default aspx Terminal Emulator A terminal emulator application must be available on the terminal PC in order to access the console screen If your terminal PC runs on Microsoft Windows a com mon application that can act as a client for the SSH Telnet rlogin and raw TCP pro tocols called PuTTY can be installed and used It was originally written for Microsoft Windows however it has also been ported to various Unix like operating systems And it is free and open source software available for download from the internet PuTTY Configuration Assuming both CP2102 driver and PuTTY have been installed successfully in the ter minal PC with Microsoft Windows you can check the COM port UART number under COM and LPT in the Device Manager which can be accessed by entering the Control Panel followed by opening up System and then Hardware Let us assume the CP210x USB to UART Bridge Controller has been assigned with 5
72. presentative or Advantech s customer service center for technical support if you need additional assistance Please have the following information ready before you call Product name and serial number Description of your peripheral attachments Description of your software operating system version application software etc Acomplete description of the problem The exact wording of any error messages iii MIC 5603 User Manual Warnings Cautions and Notes Warning Warnings indicate conditions which if not observed can cause personal injury Caution Cautions are included to help you avoid damaging hardware or losing data e g A There is a danger of a new battery exploding if it is incorrectly installed Do not attempt to recharge force open or heat the battery Replace the battery only with the same or equivalent type recommended by the man ufacturer Discard used batteries according to the manufacturer s instructions Note Notes provide optional additional information B Document Feedback To assist us in making improvements to this manual we would welcome comments and constructive criticism Please send all such in writing to support advan tech com Packing List B MIC 5603 Processor Advanced Mezzanine Card B Warranty certificate document If any of these items are missing or damaged contact your distributor or sales repre sentative immediately MIC 5603 User Manual iv Sa
73. q MMC Req support Set AMC Port State 3 27 19h 2 Yes Get AMC Port State 328 RICM ian 2 Yes Set Clock State 3 44 2Ch ee ry Yes Get Clock State 3 45 oN 2Dh ee ry Yes MIC 5603 User Manual 88 HPM 1 R1 0 Command did NetFn CMD Hed PME MMC Bed MM aon Table support ume eue 3 3 d 2Eh Mandatory Yes 1 3 5 a 2Fh Mandatory Yes 3 15 CM 30h Optional Yes Initiate upgrade action 3 8 2 31h Mandatory Yes Upload firmware block 3 9 cM 32h Mandatory Yes Finish firmware upload 3 10 GM 33h Mandatory Yes Get upgrade status 3 2 d 34h 1 Yes Activate firmware 3 11 35h Mandatory Yes Query Self test Results 3 12 36h Menu Yes Query Rollback status 3 13 aoe 37h 5 Yes ave BO om Reheat vs OEM Group IPMI Commands Advantech OEM Commands Command NetFn CMD bu BMG ace 4 MNC Tm support uM 40h l 7 Yes rM Ah l Yes Read Port 80 cn 80h Yes Clear CMOS 1 81h Yes Read MAC Address 1 E2h Yes Load Default Configuration cip F2h Yes 89 MIC 5603 User Manual MIC 5603 User Manual 90 Appendix B Driver Tools B 1 The project provides an Kernel driver which is available in most of the Linux distributions Source OpenIPMI Page http op
74. re connected DISABLE loption vill keep USB devices available only EFI applications gt lt Select Screen v Select Item Enter Select Change Opt Fi General Help F2 Previous Values F3 Optimized Defaults F4 Save 6 Exit ESC Exit Figure 4 13 USB configuration menu MIC 5603 User Manual 28 4 4 9 1 4 4 9 2 4 4 9 3 4 4 9 4 4 4 9 5 Legacy USB Support Enable This function is required for booting from USB devices and for operating systems which do not support USB themselves mainly DOS and some BootLoaders EHCI Hands Off Disabled Enabled Enables the support for OS without an EHCI hand off feature Disabled Disables the function USB Transfer Time Out 20sec This setting specifies the timeout in seconds for Control Bulk and Interrupt transfers The default is 20 seconds Device Reset Timeout 20sec This setting specifies the number of seconds the Power On Self Test will wait for a USB mass storage device to 20 seconds Device Power Up Delay Auto Maximum time the device will take before it properly reports itself to the Host Control 4 4 10 Serial Port Console Redirection This screen provides information about functions for specifying the Serial Port Con sole Redirection configuration settings Pal TY Console Redirection gt Console Redirect ion Set 1 iR TT M d 45 1 1 1 1 5 Figure 4 14 Console redirection configur
75. rfaces can be used for Serial over LAN B Both AMC base interfaces AMC Port 0 and 1 W Thefront panel LAN2 RJ 45 connector Note LAN controller used for SOL is connected to the payload power domain To be able to use Serial over LAN the payload needs to be E powered MIC 5603 User Manual 64 5 12 1 2 LAN controller and UART MUX configuration The LAN and UART configuration of the Processor AMC is flexible and allows differ ent configurations To avoid wrong setups users should always verify the actual LAN and UART configuration settings Chapter 5 6 2 Configuration setting OEM commands before working with SOL W Select the LAN interface to be used front panel or AMC base interface Make sure the LAN channel priority is appropriate W Select UART interface to be used COM1 or COM2 5 12 1 3 Default parameter Following default parameters are good to know for the initial MIC 5603 LAN setup IP Address 192 168 1 1 LAN Channel Number 5 Username administrator Password advantech 5 12 2 LAN configuration with IPMItool The open source IPMItool utility is used in this chapter for the MIC 5603 SOL and LAN parameter configuration Any other utility based on standard IPMI commands can be used as well To get an overview of all possible commands within an IPMItool command group please use the single keywords e g lan user or sol only 5 12 2 1 LAN commands lan print channel number Get the LAN
76. ris ette PERF 70 6 1 1 IPMIEOOl tr titre tei eoe ven inus 70 6 102 Interfaces iei ten eben teet pee ek 70 MMC firmware 70 6 2 1 Load new MMC firmware 70 6 2 2 Activate MMC firmware ssssssseeeen ns 71 FPGA configuration 71 6 3 1 Load new FPGA 71 6 3 2 Activate FPGA 2 72 BIOS 73 6 41 Load new 2 8 73 6 4 2 Activate 800 73 NVRAMIY upgrade 74 6 5 1 Select NVRAM upgrade section optional 74 6 5 2 Load new NVRAM image eee 75 6 5 3 Activate NVRAM 75 Verify successful 76 IPMI PICMG Command Subset Supported by MMC 77 Standard IPMI Commands 2 0 78 Driver amp Tools 91 OPEMIPM 92 92 Product Overview This chapter describes briefly the product technology of the MIC 5603 1 1 Introduction The MIC 5603 is a highly integrated single width Full mid size processor AMC Its design is ba
77. rm Modules The chip communicates with the system through the LPC interface 2 2 14 Handle Switch A handle switch is implemented to facilitate the insertion locking and extraction of the AMC module from the carrier board in addition to the state change of the hot swap micro switch When the handle is pushed towards the front panel by the user the switch is toggled to confirm AMC insertion On the other hand when the handle is pulled away from the front panel the micro switch will resume its original position to indicate a request for AMC extraction to the Module Management Controller MMC The MMC sends a Module Hot Swap event message to the Carrier IPMC when the hot swap micro switch changes state The handle switch type and location are designed according to the PICMG 0 Rev2 0 specification MIC 5603 User Manual 10 2 2 15 Front Panel Ports and Indicators HDMI Type D Reset Button ue Gigabit Ethernet USB2 0 Handle Switch Serial Port LED O Figure 2 2 MIC 5603 Front Panel 2 2 15 1 Reset Button The reset button on the front panel is controlled by the MMC Two different reset but ton modes are supported When the reset button is pressed and released within 1 second the payload x86 system will reset m When the reset button is pressed for more than 5 seconds the MMC will cold reset Note As long as the reset button is active pressed the red LED will light in order indicate a s
78. rollers that support independent DMA operation on up to six ports and supports data transfer rates of up to 6 0 Gb s 600 MB s on up to two ports while all ports support rates up to 3 0 Gb s 300 MB s and up to 1 5 Gb s 150 MB s Two of these six ports namely SATA 0 and SATA 1 are routed to AMC edge connector SATA 3 to the Compact Flash expansion board connector for SATA PATA interface conversion amp SATA 2 for on board Flash MIC 5603 User Manual 8 2 2 7 2 2 8 2 2 8 1 2 2 9 USB Host Interface The QM67 PCH also has USB host interface with two EHCI high speed USB 2 0 Host controllers and two rate matching hubs provide support for up to fourteen USB 2 0 ports MMC The management firmware of the MIC 5603 is implemented on NXP s LPC1768 which is based on a 32 bit ARM Cortex M3 core It contains 512 kB internal Flash a total of 64 kB SRAM and operates with up to 100MHz An external SPI EEPROM is used for storing FRU inventory data and non volatile configurations The deferred firmware image is stored in an external SPI flash Key Features Advantech Integrity Sensor Based on Advantech IPMI Core designed for and IPMI 1 5 and IPMI 2 0 Specification compliant IPMI over LAN Serial over LAN KCS interface for direct IPMI communication between Operating System and MMC BIOS fail over including BIOS watchdog Full BMC Watchdog support as defined in IPMI specification Ful MMC Firmware redundancy Manual r
79. rous testing most of our customers never need to use our repair service If an Advantech product is defec tive it will be repaired or replaced at no charge during the warranty period For out of warranty repairs you will be billed according to the cost of replacement materials service time and freight Please consult your dealer for more details If you think you have a defective product follow these steps 1 Collect all the information about the problem encountered For example CPU speed Advantech products used other hardware and software used etc Note anything abnormal and list any onscreen messages you get when the problem occurs 2 Call your Advantech sales representative and describe the problem Please have your manual product and any helpful information readily available 3 If your product is diagnosed as defective obtain an RMA return merchandise authorization number from your Advantech sales representative This allows us to process your return more quickly 4 Carefully pack the defective product a fully completed Repair and Replacement Order Card and a photocopy proof of purchase date such as your sales receipt in a shippable container A product returned without proof of the purchase date is not eligible for warranty service 5 Write the RMA number visibly on the outside of the package and ship it prepaid to your dealer Part No 2002560300 Edition 1 Printed in Taiwan February 2013 MIC 5603 User Manual ii
80. s 5019 INY 4 4 4 Trust Computing This screen provides functions for specifying the TPM configuration settings and TPM displaying status information lt 4 COM4 PuTTY TPH SUPPORT Disable Figure 4 8 Trust Computing The hardware support for TPM on the MIC 5603 series is available by request there fore the default setting for this feature is No in BIOS MIC 5603 User Manual 24 4 4 5 CPU Configuration 27 PuTTY j a as as am as am as an as am am e l 1 l Enabled ee Figure 4 9 CPU Configuration 4 4 5 1 CPU Configuration This is a display only function indicating general information about the installed CPU 4 4 5 2 Hyper threading Enabled Intel s proprietary HT Technology is used to improve parallelization of computations doing multiple tasks at once performed on PC microprocessors 4 4 5 3 Active Processor Core AIl Select the numbers of cores in each processor package Configuration options All 1 It depends on each CPU type 4 4 5 4 Limit CPUID Maximum Disabled This function is used to limit the return value for the maximum CPUID input value to 03 when queried 4 4 5 5 Execute Disable Bit Enabled Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system 4 4 5 6 Har
81. sed on the low power high performance Intel 2nd Generation Core i7 mobile processors combined with the high performance Intel QM67 PCH The board includes 4 or 8 GB of soldered DDR3 1333 MHz memory with ECC for higher MTBF and optimum cooling To facilitate development test and integration whilst offering typical network connectivity once deployed the front panel provides two gigabit Ethernet connector a serial port and a USB 2 0 host port The MIC 5603 maximizes AMC edge connector connectivity for the best design flexi bility Two gigabit Ethernet ports provide AMC 2 compliance and offer control and data plane connectivity to facilitate the migration of existing applications Both ports connect to the Intel 82850 data throughput Dual SATA interfaces provide AMC 3 compliant storage One SATA routed to CFast daughter board for optional and One USB ports offer further connectivity opportunities A dedicated Module Management Controller MMC monitors onboard conditions and manages hot swap operation for field upgrades or module replacement without the need to power down the underlying system 1 2 Applications It is designed to allow communication equipment manufacturers to add modular and upgradeable computing functionality to their AdvancedTCA or MicroTCA proprietary baseboards and provide the localized capability necessary for applications such as protocol processing packet processing data management and I O management This AMC module
82. ser set name 2 newuser User set password user id password This command can be is used change the user password root localhost ipmitool user set password 2 newpassword 5 12 3 SOL session with IPMItool Advantech recommends using IPMItool to successful open a SOL session with MIC 5603 The lanplus interface RMCP of IPMItool must be used to be able to change SOL parameters and establish SOL sessions Following general IPMItool parameters are needed for RMCP and IPMItool sol commands ipmitool I lanplus H IP Address U User P Password sol SOL Command Command Line Syntax lanplus Specifies RMCP as desired protocol H lt IP Address gt IP address assigned to the MMC U User User account default administrator Password used with specified user account default password for d SPOSSWOIde user administrator is advantech MIC 5603 User Manual 66 5 12 3 1 SOL parameter commands sol info channel number Read out the SOL configuration parameters for a given channel ipmitool I lanplus IP Address U User P Password sol info Set in progress set complete Enabled false Force Encryption true Force Authentication true Privilege Level ADMINISTRATOR Character Accumulate Level ms 250 Character Send Threshold 32 Retry Count 2 Retry Interval ms 1000 Volatile Bit Rate kbps 115 2 Non Volatile Bit Ra
83. ses 25 4 13h Optional Optional No 2 Den Proxy 25 5 ap 14h Optional Optional No S PUER Da ISI 25 6 15h Optional Optional No En ia UDP TOY 287 a 16h Optional Optional No Receive Data 258 or 17n Optional Optional No C ius 25 9 18 Optional No Callback 25 1 TransP 195 Optional Optional No 5 m 1Ah Optional Optional No 20 251 Transp 1Bh Optional Optional No SOL Activating 26 1 Hs 20h an Ge SOL m _ 84 MIC 5603 User Manual Bridge Management Commands ICMB IPMI Advantech Command v2 0 NetFn CMD ii EM 1 MMC Ret q support Bridg Optional Get Bridge State ICMB m 00h Mandatory Optional No Bridg Optional Set Bridge State ICMB 01h Mandatory Optional No Bridg Optional Get ICMB Address ICMB 5 02h Mandatory Optional No Bridg Optional Set ICMB Address ICMB B 03h Mandatory Optional No Set Bridge Proxy Bridg Optional Address ICMB E 04h Mandatory Optional No m Bridg Optional Get Bridge Statistics ICMB 5 05h Mandatory Optional No ai Bridg Optional Get ICMB Capabilities ICMB E 06h Mandatory Optional No Bridg Optional Clear Bridge Statistics ICMB 5 08h Mandatory Optional No Get Bridge Proxy Bridg Optional
84. t Device Locator PICM Record ID 3 39 G ODh Mandatory Yes Set Port State 3 59 PCM och N A No Get Port State 360 oFn N A No Compute Power PICM Properties 3 82 G 10h N A No Set Power Level 3 84 ae 11h N A No Get Power Level 3 83 ae 12h N A No Renegotiate Power 3 91 2 13h l Get Fan Speed PICM Properties 3 86 G 14h N A No Set Fan Level 3 88 ish No Get Fan Level 287 FICM fieh N A No Bused Resource 3 62 a 17h N A No Get IPMB Link Info 3 68 ae 18h l N A No 87 MIC 5603 User Manual Get Shelf Manager PICM IPMB Address 938 G 2 Set Fan Policy 3 89 ich N A No Get Fan Policy 90 FICM tbh N A No FRU Control PICM Capabilities 3 26 G 1Eh Mandatory Yes FRU Inventory Device PICM Lock 3 42 G 1Fh l Optional No Control FRU tory Devi PICM Write ees G 20h Optional No Get Shelf Manager IP PICM Addresses 3 36 G 21h Optional No Get Shelf Power PICM Allocation 3 85 G 22h N A No Get Telco Alarm PICM Capability 3 93 G 29h 7 No Set Telco Alarm State 3 94 ae 2Ah No Get Telco Alarm State 3 95 a 2Bh Get Alarm PICM Location 3 96 G 39h 7 Set FRU Extracted 225 sah No 0 R2 0 Advantech Command 0 NetEn CMD Module MMC Table Re
85. te kbps 115 2 Payload Channel 7 0x07 Payload Port 623 sol set parameter value channel This command allows modifying special SOL configuration parameters ipmitool I lanplus IP Address U User P Password sol set SOL set parameters and values set in progress set complete set in progress com mit write enabled true false force encryption true false force authentication true false privilege level user operator admin oem character accumulate level in 5 ms increments character send threshold N retry count N retry interval in 10 ms increments non volatile bit rate serial 9 6 19 2 38 4 57 6 115 2 volatile bit rate serial 9 6 19 2 38 4 57 6 115 2 5 12 3 2 SOL session activation Finally the IPMItool sol activate command need to be issued to establish the SOL session to MIC 5603 from remote ipmitool I vate SOL Session operational terminated ipmitool lanplus IP Address U User P Password sol acti Use for help To terminate an active IPMItool SOL session please use the key tilde and dot Note There can only be one Serial over LAN session active at once 67 MIC 5603 User Manual MIC 5603 User Manual 68 HPM 1 Update This chapter describes the update of following software firmware components Se
86. tegrity Sensor event reports a successful MMC Firmware update MIC 5603 User Manual 50 5 3 5 5 Event data table All event data combinations supported by the MMC Integrity Sensor can be found in following list Component Subcomponent Result Byte 1 Byte2 Update Successful 0x01 0x00 Update Timeout 0x01 0x04 Update Aborted 0x01 0x02 Activation Failed 0x01 0x21 MMC FW Manual Rollback Initiated 0x01 0x15 Automatic Rollback Initiated 0x01 0x1D Rollback Finished 0x01 OxOE Rollback Failed 0x01 0x09 Graceful Shutdown Timeout 0x01 0x74 Update Successful 0x02 0x00 FPGA Update Timeout 0x02 0x04 Update Aborted 0x02 0x02 Recovery Finished 0x02 OxOE Update Successful 0x03 0x00 Update Timeout 0x03 0x04 BIOS Update Aborted 0x03 0x02 Flash 0 Boot Failed 0x03 0x29 Flash 1 Boot Failed 0x03 0x31 Update Successful 0x04 0x00 NVRAM Update Timeout 0x04 0x04 Update Aborted 0x04 0x02 RTC Time sync Successful 0x09 0x68 Time sync Failed 0x09 0x69 51 MIC 5603 User Manual 5 3 5 6 Example event identification The Integrity Sensor is listed as last MIC 5603 sensor verify below IPMItool exam ple root localhost ipmitool sdr elist HOTSWAP Olh 193 100 Module Handle Closed INTEGRITY 10h ns 193 100 Disabled As mentioned before the Integrity Sensor does not provide a sensor reading dis abled but supports event genera
87. tion at any time Occurred events are stored as records in the System Event Log and can be read out with following IPMItool command root localhost ipmitool sel elist 1 04 23 2012 10 04 46 Module Hot Swap 0 01 Module Han dle Closed Asserted e 04 23 2012 10 13 31 OEM OEM Specific Asserted Detailed information to single system events event data bytes in the SEL can be displayed with IPMItool sel get lt entry gt root localhost ipmitool sel get 0 0 SEL Record ID 000e Record Type 02 Timestamp 04 23 2012 10 13 31 Generator ID 0074 EvM Revision 04 Sensor Type OEM Sensor Number s 10 Event Type Sensor specific Discrete Event Direction Assertion Event Event Data a00100 Description OEM Specific The Event Data field reflects the three needed bytes to identify the occurred Integ rity Sensor event MIC 5603 User Manual 52 5 4 5 4 1 5 4 2 5 4 3 FRU Information The MMC provides IPMI defined Field Replaceable Unit FRU information about the AMC module The MIC 5603 FRU data include general board information s such as product name HW version or serial number A total of 2 kB non volatile storage space is reserved for the FRU data The boards IPMI FRU information can be made accessible via all MMC interfaces and the information can be retrieved at any time PICMG FRU records In addition to the standard IP
88. tion for the MIC 5603 7 222 BlOS P MOX 7 2 2 9 ene eec tea ebd 7 Figure 2 1 INTEL QM67 Chipset 8 2 214 A 8 2 2 5 Ethernet Controller cesses 8 22 6 SATA InterfaCe iniecit tati eni taa ERES ERES 8 2 2 7 USB Host Interface cccccsssesesssssssdssccacecavarsveseneasacecascuasanasauaanes 9 2 2 0 aa eaaa aK 9 2 2 9 Integrated Clock 9 2 2 10 Legacy USB 2 04 44 000 10 2 2 11 On board Storage Flash 10 2 2 12 CFast Expansion Module sse 10 2 2 13 Trusted Platform Module 10 2 2 14 Handle SWIICh trit erection sa th a aaa 10 2 2 15 Front Panel Ports and Indicators 11 Figure 2 2 MIC 5603 Front 11 Table 2 3 LAN LEDS nette 11 Table 2 4 Front Panel 12 Console Terminal Setup 13 USB to VART Bridge 14 Terminal Emulator 14 PUTTY Configuration esssssssssssseseeeeeeeeen 14 Figure 3 1 PuTTY 15 Figure 3
89. to individual serial Links in a PCI Express fabric to be incrementally reduced as a Link becomes less active The default setting is Dis abled Warning Enable ASPM may cause some PCle device to Fail A MIC 5603 User Manual 22 4 4 2 6 4 4 3 4 4 3 1 4 4 3 2 4 4 3 3 Extended Synch This bit when set forces the transmission of additional ordered sets when exiting the LOs state amp when in the Recovery state ACPI Configuration ACPI is the newer power management in the hands of the operating system APM is controlled by the BIOS In addition it is available by default when ACPI is disabled 27 PuTIY Figure 4 7 ACPI settings Note If ACPI is disabled the functionality of graceful OS shutdown becomes unavailable Enable Hibernation Enabled All is powered off but the memory was saved like temporary file on the hard drive This mode is called Save to disk ACPI Sleep State S3 Suspend to RAM S1 Sleep The CPU is stopped The RAM is regenerated the system functions in reduced power 53 Standby The CPU does not have any power The RAM regenerates at mini mum the power supply unit is in mode of reduced power This mode is also called Suspend to RAM Lock Legacy Resources Disabled When enabled locked this option prevents the operating system from modifying assignments for legacy resources serial parallel and PS 2 ports 23 MIC 5603 User Manual y Jajdeuy dnie
90. tory Optional Yes Get Watchdog Timer 27 7 App 25h Mandatory Optional Yes BMC Device and Messaging Commands IPMI Advantech Command v2 0 cup Module Req MMC Req Ret support Et Global 22 1 App 2Eh Mandatory Optional Yes ER Global 22 2 App 2Fh Mandatory Optional Yes Clear Message Flags 22 3 App 30h Mandatory Optional Yes Get Message Flags 22 4 App 31h Mandatory Optional Yes Enable Message Channel Receive 22 5 App 32h Optional Optional No Get Message 22 6 App 33h Mandatory Optional Yes Send Message 22 7 App 34h Mandatory Optional Yes Message 22 8 App 35h Optional Optional Yes Get BT Interf 22 1 Capabilities 0 36h Mandatory Optional No Get System GUID 37h Optional Optional Yes Get Channel 221 Authentication 3 App 38h Optional Optional Yes Capabilities Get Session Challenge App 39h Optional Optional Yes MIC 5603 User Manual 78 Activate Session zen App Optional Optional Yes 2 Privilege App 3Bh Optional Optional Yes Close Session App 3Ch Optional Optional Yes 22 2 Get Session Info 0 App 3Dh Optional Optional Yes Get AuthCode que App 3Fh Optional Optional No Set Channel Access App 40h Optional Optional Yes Get Channel Access ce App 41h Optional Optional Yes Get Chan
91. u m PEGO Gen X Configure PEGO B0 D1 F0 Gen1 Gen2 m PEG1 Gen X Configure PEG1 B0 D1 F1 Gen1 Gen2 PEG2 GenX Configure PEG2 B0 D1 F2 Gen1 Gen2 MIC 5603 User Manual 36 4 5 1 8 Memory Configuration COMA Pal TY Aptio Setup DEN Si ct DIMM profile Default DIAM profile Figure 4 22 System memory configuration menu DIMM profile Default DIMM Profile Select DIMM timing profile that should be used m Memory Frequency Auto Maximum Memory Frequency Selections in Mhz m Max TOLUD Dynamic Maximum Value of TOLUD Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller m NMode Support Auto NMode Support Option 37 MIC 5603 User Manual y Jaydeuy dnies 5019 INY 4 5 2 4 5 2 1 4 5 2 2 4 5 2 3 4 5 2 4 4 5 2 5 4 5 2 6 4 5 2 7 4 5 2 8 PCH IO Configuration Figure 4 23 Intel PCH configuration menu PCH LAN Controller Enabled Enable Disable LAN1 Controller Wake on LAN1 from S5 Disabled Disabled Enabled Wake on Lan1 from S5 Azalia internal HDMI codec Enabled Enable or Disable Azalia internal HDMI codec Azalia Docking Supp Enabled Enable or disable Azalia Docking Support of Audio Controller Azalia PME Disabled Enable or disable Power Management Capability of Audio Controller High Precision Timer Enabled Enable or Disable the High Precision Timer 54 Assertion Width 4 5 Seconds This
92. uccessful reset contact 2 2 15 2 Micro USB Console Port A micro USB 2 0 compliant slave port is used for debugging diagnostic information and implementation of a serial console interface This function is derived from the on board USB to Serial converter 2 2 15 3 USB 2 0 Port There is a USB 2 0 compliant host port on the front panel for USB 2 0 device connec tion 2 2 15 4 RJ 45 LAN Port Two RJ45 are available on the front panel for 10 100 1000 Base T Ethernet connec tion which come through PCle based Intel 82580 amp 82579 MAC PHY Table 2 3 LAN LEDs LED Color Description Solid Link 0 Green Flashing Activity Off 10 Mbps 1 Green Orange Green 100 Mbps Orange 1000 Mbps 11 MIC 5603 User Manual 2 2 15 5 MMC LED Indicators The MIC 5603 supports three front panel LEDs Table 2 4 Front Panel LEDs LED Color Description 0 Blue Hot swap indicator 1 Red Out of service indicator 2 Gr e Flashing FW application active payload x86 in sleep Solid FW application active payload x86 active MIC 5603 User Manual 12 Console Terminal Setup This chapter describes through example how setup con sole for the MIC 5603 3 1 3 2 3 3 USB to UART Bridge TThe MIC 5603 contains a console port micro USB on the front panel The MIC 5603 uses a USB to UART bridge called CP2102 from Silicon Laboratories to con vert data traffic between USB and UART f
93. ult value is 0 Read LAN channel selection priority ipmitool raw 0 2 0x41 0x39 0x28 0x00 0x04 0x01 Response 39 28 00 setting Change LAN channel selection priority ipmitool raw 0x2e 0x40 0x39 0x28 0x00 0x04 0x01 setting Response 39 28 00 57 MIC 5603 User Manual 5 6 4 FPGA COM port UART MUX MIC 5603 implements several serial interfaces which can be configured in some ways This is done inside the FPGA with the help of an UART MUX refer to Chapter 5 6 UART and UART Multiplexer The MMC provides OEM commands to config ure these UARTS via IPMI Following COM1 COM2 port settings are available Cau tion Verify note below about the UART dependency COM interfaces 5 9 Interface 0x00 1 0x01 COM2 COM1 MUX Table 5 10 COM1 UART MUX settings Setting Connection 0x00 no interface connected open 0x01 Serial over LAN SOL 0x02 Front panel Micro USB default 0x03 AMC connector port 15 COM2 Table 5 11 COM2 UART MUX settings Setting Connection 0x00 no interface connected open 0x01 Serial over LAN SOL default 0x02 Front panel Micro USB 0x03 AMC connector port 15 Note The COM1 UART is the main interface with higher priority There is an 7 important dependency between COM1 and 2 UARTs users should 5 know aware of The COM2 MUX can O
94. you can open up PuTTY and begin the configuration as shown below MIC 5603 User Manual 14 PuTTY Confipnration Category Session Basic options for your PuTTY session Logging Specify the destination you want to connect to Terminal Keyboard 21205 Speed Bell COM5 115200 Features Connection type Window Raw Rlogn SSH Appearance i3 Load save or delete a stored session Behaviour Translation Saved Sessions Selection mii Let ol AM RES Load Connection Proxy Rloain x SSH i Seria Close window on exit Always Never 9 Only clean exit Figure 3 1 PuTTY configuration E Specify COM5 under serial line and 115200 for speed W Check Serial for connection type W Click the Open button and a PuTTY terminal screen as shown below will appear 5 PuTTY Figure 3 2 PuTTY screen 15 MIC 5603 User Manual If the connection is successful upon boot up the MIC 5603 s BIOS POST will be dis played on the PuTTY screen 5 PuTTY Jj 0 14 0 Intel R itium R M p r 1 40GHz Speed 1 40 GHz Press DEL to run Setup on Remote Keyboard Initializing USB Controllers Done 1024MB OK nn 0075 Figure 3 3 MIC 5603 BIOS POST Shown PuTTY Screen MIC 5603 User Manual 16 AMI BIOS Setup This chapter describes how to configure the AMI BIOS 4 1 Introduction The AMI BIOS has been customized and integr

User Manual MIC-5603 - Advantech

Contents

Download Pdf Manuals

Related Search

Related Contents