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M68332EVK EVALUATION KIT USER`S MANUAL

1. 1 5 2 1 Socket to Memory Device Compatibility ss 2 11 2 2 BCGC PFB Compatibilty us eet eiie dtr Sen A aede 2 24 3 1 EVK Control SWItSh Su us Ne uae eaa ARS ee 3 3 3 2 BCC Rev Chip Selection Summatry 3 4 3 3 BCC Rev B Chip Selection Summary nitrate 3 5 3 4 Rev C Chip Selection Summary 3 5 3 9 CC PLZ Bus EXCEPUON SS S Tamu am pA BE cL a 3 6 5 1 EVK Connector Descriptions VER net cn 5 1 5 2 Expansion Connector Pin Assignments 5 2 5 3 P2 Expansion Connector Pin Assignments 5 5 5 4 and P10 Background Mode Connector Pin Assignments 5 8 5 5 BCC P4 Connector Pin 5 9 5 6 P1 Logic Analyzer Connector Pin Assignments 5 9 5 7 P2 Logic Analyzer Connector Pin Assignments 5 10 5 8 P3 Logic Analyzer Connector Pin Assignments 5 10 5 9 P4 Logic Analyzer Connector Pin Assignments 5 11 5 10 PFB P5 Logic Analyzer Conn
2. RS 232C CONNECTOR U2 RAM EPROM FOR DI SELECT HEADER LOGIC ANALYZER CONNECTORS POWER SUPPLY RS 232C U2 EPROM U4 RAM EPROM COPROCESSOR P1 P6 CONNECTOR CONNECTOR SELECT HEADER SELECT HEADER SOCKET FOR BCC te J4 J5 J7 J6 1 E P7 U1 amp U3 ENABLE HEADER fie 1 p2 U4 EPROM Ji SELECT HEADER co U2 J2 L 14 ENABLE HEADER P8 r 1J3 BCC P1 BCC P2 BCCDI P1 U4 4 ENABLE HEADER BCCDI P2 REVISION LEVEL P9 SELECT HEADERS J8 J13 P5 P6 sw 11 swe J14 C P10 VOLTAGE STANDBY 64 PIN EXPANSION 64 PIN EXPANSION IFETCH SELECT VSTBY CONNECTOR HEADER CONNECTOR HEADER CONNECTOR HEADER FOR THE BCC FOR THE DI BACKGROUND MODE CONNECTOR Figure 2 3 PFB Jumper Header and Connector Location Diagram M68332EVK D 2 12 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 2 1 U1 and U3 Enable Header J1 Sockets U1 and U3 are for user supplied 32k x 16 bit RAM Use jumper header J1 to enable this additional memory The PFB is shipped from the factory with a jumper installed on pins 1 and 2 U1 and U3 disabled shown below To enable RAM in sockets U1 and U3 move the fabricated jumper to pins 2 and 3 Refer to the PFB schematic diagram for more detail on RAM enable select signal wiring A23 CS10 21 58 A22 CS9 U1 U3 2 27 G le FABRICATED 20 E 2016 JUMPER 60L256 60L256 2 6 0 e
3. 510 50 SFFFCOC L 5024 FFFA22 Modify memory at location 500C Change PIT time out speed Go to address 5000 and begin execution Periodic interrupt timer time out message Press the ABORT switch on the PFB to terminate the loop program Exception ABORT PC 200005018 SR SFC 5 SD DFC 5 SD DO 00000000 21 0000 24 00000000 25 0000 0 0000510 Al 0000 A4 00000000 5 0000 00005018 6000FFF8 CPU32Bug gt T 1 lt CR gt PC 00005018 SR 2500 SFC 5 SD DFC 5 SD DO 00000000 21 0000 4 00000000 25 0000 AO 0000510E Al 0000 4 00000000 5 0000 00005012 F80001C0 2500 CPU32Bug gt BR 5034 lt CR gt BREAKPOINTS 00005034 CPU32Bug gt g 5000 lt CR gt Effective address 00005018 At Breakpoint PC 00005034 SR SFC 5 SD DFC 5 SD DO 00000000 21 0000 24 00000000 25 0000 0 00005101 1 0000 4 00000000 5 0000 00005034 2 8 M68332EVK D REV 1 2500 TR OFF_S_5_ USP 0000 00 0000 2 00000000 0000 D6 00000000 510E A2 00000000 0000 6 00000000 BRA W W 5012 Trace one instruction TR OFF S 5 USP 0000 00 0000 2 00000000 0000 D6 00000000 510E A2 00000000 0000 6 00000000 LPSTOP W 52500 Set breakpoint at 5034 VBR 00000000 SSP 00010000 D3 00000000 D7 00000000 A3 00000000 A7 00010000 VBR 00000000 SSP 00010000 D3 00000000 D7 00000000 A3 00000000 A7 00010000 Go to a
4. and DCD be shorted together before they will function properly with the EVK Make this modification to the PC side of the cable Figure 2 6 Terminal PC Cable Diagram for PFB P9 M68332EVK D 2 30 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 4 5 Terminal Connection The BCC has a 4 pin serial port P4 for connection to a terminal or host computer with terminal emulation Use P4 to communicate with the BCC from a terminal or host computer To connect an RS 232C compatible terminal or host computer use a user supplied cable assembly as shown in Figure 2 7 Connect one end of the cable assembly to BCC connector P4 shown below Connect the other end of the cable assembly to a user supplied terminal or host computer Refer to Chapter 5 for connector pin assignments and signal descriptions of BCC connector P4 4 10V 3 RCV 2 GND 1 BCC J8 Terminal PC Port M68332EVK D 2 31 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION BCC J8 TERMINAL SERIAL PORT NOTE Some serial communication cards require CTS DSR DTR and DCD be shorted together before they will function properly with the EVK Make this modification to the PC side of the cable DB 25 Figure 2 7 Terminal PC Cable Diagram for BCC J8 M68332EVK D 2 32 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 4 6 Logic Analyzer EVK Connection logic analyzer can be connected to the as an a
5. 50 microamps min 2 25 x 3 875 in 5 7 x 9 84 cm 1 An optional high frequency clock source as high as 16 77 MHz may be used if MODCK P2 pin 28 is pulled to a logic low level A hybrid oscillator is recommended as the external clock M68332EVK D REV 1 1 2 MOTOROLA GENERAL INFORMATION Table 1 2 PFB Specifications CHARACTERISTICS SPECIFICATIONS External Clock 25 kHz to 50 kHz Expanded Memory Sockets U1 U4 32k x 16 RAM U1 U2 U3 amp U4 32k x 16 EPROM U2 amp U4 64k x 16 EPROM U2 amp U4 25 2 clock bus cycle access 16 7 MHz or 85ns 3 clock bus cycle access 16 7 MHz 200ns 5 clock bus cycle access 16 7 MHz 200ns 5 clock bus cycle access 16 7 MHz Terminal Host Ports RS 232C compatible Temperature Operating Storage Relative humidity 25 40 to 85 0 to 90 non condensing Power Requirements Power Supply Battery Backup 5 500 milliamps min 3 50 microamps min Dimensions 6 25 x 10 in 15 88 25 4 cm M68332EVK D REV 1 MOTOROLA GENERAL INFORMATION 1 4 GENERAL DESCRIPTION Using the EVK the user can design debug and evaluate MC68332 MCU based target systems The BCC simplifies user evaluation of prototype hardware software products The EVK requires a user supplied power supply and an RS 232C compatible terminal for functional operation The E
6. 3 Vpp GND 1 23 510 A21 CS8 and A22 CS9 are default signals Jumpers J8 J12 and 713 respectively can select the alternates M68332EVK D 2 13 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 2 2 U2 Enable Header J2 The user may install a user supplied 32k byte RAM 32k byte EPROM or 64k byte in socket U2 Use jumper header J2 to select between CS6 and CSBOOT chip selects for the memory device installed in U2 The PFB is shipped from the factory with a jumper installed on pins 1 and 2 shown below If you install an EPROM in U2 and desire a program to execute during reset or power up place the fabricated jumper across pins 2 and 3 and disable the EPROM on the BCC refer to paragraph 2 3 1 4 Jumper headers J2 and J3 must be configured the same for EPROMs installed in locations U2 and U4 Refer to schematic diagram for more detail on chip enable signal wiring FABRICATED JUMPER 60L256 1 R W and CS6 are default signals Jumpers J4 and J11 respectively can select the alternates M68332EVK D 2 14 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 2 3 U4 Enable Header J3 The user may install a user supplied 32k byte RAM 32k byte or 64k byte EPROM in socket U4 Use jumper header J3 to select between CS7 and CSBOOT selects for the memory device installed in U4 The PFB is shipped from the factory with a jumper installed on pins 1 and 2 shown below
7. REV 1 Signal Name And Description Not connected DATA AND SIZE ACKNOWLEDGE Active low input signals that allow asynchronous data transfers and dynamic bus sizing between the MC68332 and external devices ADDRESS BUS Three state output address bus GROUND 5 10 MOTOROLA SUPPORT INFORMATION Table 5 9 PFB P4 Logic Analyzer Connector Pin Assignments Signal Mnemonic Pin Number Signal Name And Description NC Not connected DSACKO DATA AND SIZE ACKNOWLEDGE Active low input signals that allow asynchronous data transfers and dynamic bus sizing between the MC68332 and external devices 1 2 an automatic vector during an interrupt acknowledge cycle RMC READ MODIFY WRITE CYCLE Active low output signal that identifies the bus cycle as part of an 4 x AVEC AUTOVECTOR Active low input signal that requests x indivisible read modify write operation 6 AS ADDRESS STROBE Active low output signal that indicates that a valid address is on the address bus DS DATA STROBE Active low output signal that during a read cycle indicates that an external device should place valid data on the data bus During the write cycle DS indicates that valid data is on the data bus that an external device requires bus master ship CS0 CHIP SELECT 0 Output signal that selects peripheral memory devices at programmed addresses BG BUS GRANT Active low output signal that
8. BCC Block Diagram M68332EVK D 4 3 MOTOROLA REV 1 4 3 1 FUNCTIONAL DESCRIPTION Summary The resident MC68332 Microcontroller Unit MCU of the provides resources for designing debugging and evaluating MC68332 MCU based target systems and simplifies user evaluation of prototype hardware software products The MCU device is 32 bit integrated microcontroller combining high performance data manipulation capabilities with powerful peripheral subsystems The MCU includes 4 3 1 1 32 bit central processor unit CPU32 Time processor unit TPU Queued serial module QSM Random access memory RAM External bus interface Chip selects System clock Test module 32 Bit Central Processor Unit The CPU32 is the central processor for the MC68332 MCU device The CPU32 is source and object code compatible with the MC68000 and MC68010 user programs can be executed unchanged The CPU32 features are 32 Bit internal data path and arithmetic hardware 16 bit external data bus 32 Bit internal address bus 24 bit external address bus Powerful instruction set Eight 32 bit general purpose data registers Seven 32 bit general purpose address registers Separate user and supervisor stack pointers and address spaces Separate program and data address spaces Flexible addressing modes Full interrupt processing M68332EVK D 4 4 MOTOROLA REV 1 FUNCTIONAL DESCRIPTION 4 3 1 2 Time Processor Unit The Time Pr
9. each or to transmit a stream of data as long as 256 bits without CPU intervention A special wrap around mode lets the user continuously sample a serial peripheral automatically updating the QSPI RAM for efficient interfacing to serial peripheral devices such as analog to digital converters The serial communications interface SCI port provides a standard non return to zero NRZ mark space format Advanced error detection circuitry catches noise glitches to 1 16 of a bit time in duration Word length is software selectable between 8 or 9 bits and the SCI modulus type baud rate generator provides baud rates from 64 to 524k baud based on a 16 77 MHz system clock The SCI features full or half duplex operation with separate transmitter and receiver enable bits and double buffering of data Optional parity generation and detection provide either even or odd parity check capability Wake up functions let the CPU run uninterrupted until either a true idle line is detected or a new address byte is received 4 3 1 4 Random Access Memory 2k bytes of static RAM are contained within the MC68332 MCU device The RAM is used for storage of variable and temporary data RAM data size may be 8 bits byte 16 bits word or 32 bits longword The RAM can be mapped to any 2k byte boundary in the address map M68332EVK D 4 5 MOTOROLA REV 1 FUNCTIONAL DESCRIPTION 4 3 1 5 External Bus Interface The external bus consists of 24 address lines and a
10. into memory code data 0 From 0 to n bytes of executable code memory loadable data or descriptive information For compatibility with teletypewriters some programs may limit the number of bytes to as few as 28 56 printable characters in the S record checksum 2 The least significant byte of the one s complement of the sum of the values represented by the pairs of characters making up the records length address and the code data fields M68332EVK D 1 MOTOROLA REV 1 APPENDIX A Each record may be terminated with a CR LF NULL Additionally an S record may have an initial field to accommodate other data such as line numbers generated by some time sharing systems An S record file is a normal ASCII text file in the operating system of origin Accuracy of transmission 1s ensured by the record length byte count and checksum fields S RECORD TYPES Eight types of S records have been defined to accommodate the several needs of the encoding transportation and decoding functions The various Motorola upload download and other records transportation control programs as well as cross assemblers linkers and other file creating or debugging programs utilize only those S records which serve the purpose of the program For specific information on which S records are supported by a particular program the user s manual for the program must be consulted 332Bug supports SO 51 52 S3 57 58 and S9 records S record format mod
11. operating procedure and monitor description for the EVK debug monitor CPU32Bug MCU assembling disassembling and EVK downloading procedures are also provided This information is in this order General information Control switch descriptions Limitations Operating procedure Monitor description Assembling disassembling procedures Downloading procedures The EVK is factory tested for target system evaluation The monitor is the resident firmware CPU32Bug for the EVK which provides a self contained operating environment The monitor interacts with the user through commands entered at a terminal These commands perform functions such as memory display or modification MCU internal register display or modification program execution under various levels of control and control access to various I O peripherals connected to the EVK 3 2 GENERAL INFORMATION The EPROMs the BCC contain the M68CPU32BUG debug monitor program hereafter referred to as CPU32Bug CPU32Bug is a software tool for evaluating and debugging systems built around the MC68332 MCU CPU32Bug allows loading debugging and executing of user programs Various CPU32Bug routines that handle I O data conversion timer and string functions are available to user programs through system calls For a detailed description of the CPU32Bug functions refer to M68CPU32BUG Debug Monitor User s Manual M68CPU32BUG ADI M68332EVK D 3 1 MOTOROLA REV 1 OPERAT
12. that indicates an on line in service active status 7 RTS REQUEST TO SEND Not connected 8 CTS CLEAR TO SEND An output signal that indicates a ready to transfer data status 9 NC Not connected M68332EVK D 5 17 MOTOROLA REV 1 SUPPORT INFORMATION M68332EVK D 5 18 MOTOROLA REV 1 APPENDIX A APPENDIX A S RECORD INFORMATION S record format for output modules was devised for the purpose of encoding programs or data files in a printable format for transportation between computer systems transportation process can thus be visually monitored and the S records can be more easily edited S RECORD CONTENT When viewed by the user S records are essentially character strings made of several fields which identify the record type record length memory address code data and checksum Each byte of binary data is encoded as a 2 character hexadecimal number the first character representing the high order 4 bits and the second the low order 4 bits of the byte The five fields which comprise an S record are shown below TYPE RECORD LENGTH ADDRESS CODE DATA CHECKSUM Where the fields are composed as follows Printable Field Characters Contents 2 S records type SO 51 etc record 2 The count of the character pairs in the record excluding type and length record length address 4 6 8 2 3 or 4 byte address at which the data field is to be loaded
13. 03 enable for MSB LSB BOTH 59 U1 write enable for LSB LOWER ODD RAM CS10 U3 write enable for MSB UPPER EVEN RAM Table 3 4 BCC Rev C Chip Selection Summary Signal Board Chip Description Memory Type CSBOOT BCC U3 CPU32Bug EPROM for MSB UPPER EVEN CSBOOT U4 CPU32Bug EPROM for LSB LOWER ODD cso BCC Ut write enable for MSB UPPER EVEN RAM CS1 BCC U2 write enable for LSB LOWER ODD RAM CS2 BCCUS3 Ut read enable for MSB LSB BOTH RAM CS3 lcunused gt CS4 push button autovector CS5 PFB U5 chip enable for MC68881 882 cut jump U5 J3 from 652 to CS5 required CS6 U2 read enable for LSB LOWER ODD RAM EPROM CS7 _ 04 read enable for MSB UPPER EVEN RAM EPROM 58 01 03 read enable for MSB LSB BOTH RAM CS9 U1 write enable for LSB LOWER ODD RAM CS10 U3 write enable for MSB UPPER EVEN RAM M68332EVK D 3 5 REV 1 OPERATING INSTRUCTIONS 3 4 2 Other Resources Used CPU32Bug Avoid writing the value zero to bit 7 of the port F pin assignment register PFPAR such a value disables the ABORT switch The software watchdog timer is disabled via a write once register SYPCR during power up or reset so the software watchdog timer cannot be used or re enabled by the user unless the user modifies the SYPCR_OR and SYPCR_AND parameters Modification of the SYPCR_OR and SYPCR AND parameters is detailed in Appendix C of th
14. 4 IBM PC with PROCOMMD to EVK Re ne st ne 3 23 CHAPTER 4 FUNCTIONAL DESCRIPTION 4 1 cii 4 1 4 1 AS TCO 4 3 Summary ose a 4 4 4 3 1 1 32 Bit Central Processor Unit 4 4 43 1 2 Time Processor Unit nement 4 5 4 3 1 3 Queued Serial Module 4 5 4 3 1 4 Random Access d eter tg ade Rt Md 4 5 43 1 External Bus Interface eei d itt EE 4 6 4 3 L 6 C hipoSeleets RT pe ko epu neta ores 4 6 GO System p ad een 4 6 423445 cat eee ee 4 6 BSD User Memory au sl nt ua Suwa 4 6 4 323 GonnectorSs uu aaa dei 4 8 4 3 3 1 64 Expansion Connectors oe e ive Eae pe 4 8 4 3 3 2 Serial Communication Connectors ss 4 8 4 3 3 3 Background Mode Interface Connector 4 8 44 PEB DesenpHOLbis 4 8 4 4 1 Floating Point Coprocessor Socket US 4 8 44 2 Logic Analyzer Cone ctODSo u a ne ne Dui
15. 5020 5024 502C 502E 5034 5036 503A Enter the ASCII code for the output message P MOVE L 501C 78 lt CR gt MOVE L 061E0120 FFFA22 lt CR gt LPSTOP 2500 lt CR gt BRA W 5012 lt CR gt MOVEA W 5100 A0 lt CR gt MOVEA W 510E A1 lt CR gt BTST B 4 0 FFFCOC CR BEQ B 5024 lt CR gt MOVE B 0 FFFCOF lt CR gt 1 lt gt BNE W 5024 lt CR gt RTE lt CR gt PROGRAM DESCRIPTION Memory modify at location 5000 with disassembly option Set up level six vector table Initialize PIT Execute LPSTOP Instruction Loop Beginning of message End of message Check for SCI not busy Branch until free Send message byte Check for end of message Branch until done Return from print routine LE ME OUT Each time this message appears when running the program indicates the program has completed a loop Enter the following ASCII code at memory location 5100 CPU32Bug gt MS 5100 M68332EVK D REV 1 PIT TIME OUT ODOA lt CR gt 3 15 Memory modify at location 5100 MOTOROLA OPERATING INSTRUCTIONS After entering the PIT time out program display the instructions at location 5000 EXAMPLE PROGRAM PROGRAM DESCRIPTION CPU32Bug gt MD 5000 DI lt CR gt Display memory at location 5000 with disassembly option 5000 21FC0000 501C0078 MOVE L 501 78 W 5008 23FCO61E 012000FF FA
16. Expand Blank Lines Yes Pace Character 0 Character pacing 15 milliseconds Line Pacing 10 CR Translation None LF Translation None Save above settings to disk for future use d Apply power to the EVK e Press the keyboard carriage return CR key to display the applicable EVK monitor prompt f Enter the EVK monitor download command CPU32Bug gt LO Press lt CR gt after entering LO g Press the PC Pg Up key to instruct PROCOMM to send the S record file Then follow PROCOMM instructions on the screen to select the S record file using an ASCII protocol The file transfer 15 done when the beeper sounds and the underline cursor flashes Press the carriage return twice to return to the CPU32Bug prompt lt CR gt lt CR gt CPU32Bug gt M68332EVK D 3 23 MOTOROLA REV 1 OPERATING INSTRUCTIONS M68332EVK D 3 24 MOTOROLA REV 1 FUNCTIONAL DESCRIPTION CHAPTER 4 FUNCTIONAL DESCRIPTION 4 1 INTRODUCTION This chapter is a functional description of the EVK and its components 4 2 EVK DESCRIPTION The EVK may be configured in either of two ways the BCC mounted on the PFB or the BCC mounted on the target system Figure 4 1 is the EVK block diagram When the BCC is mounted on the PFB you may evaluate the MCU and debug user developed code To do this connect a terminal or host computer to PFB connector P9 and run the CPU32Bug debug monitor program Logic analyzer connection may be made to connectors P1
17. P6 M68332EVK D 4 9 MOTOROLA REV 1 FUNCTIONAL DESCRIPTION M68332EVK D 4 10 MOTOROLA REV 1 SUPPORT INFORMATION CHAPTER 5 SUPPORT INFORMATION 5 1 INTRODUCTION This chapter provides the connector signal descriptions parts lists and associated parts location diagrams and schematic diagrams of the M68332EVK Evaluation Kit EVK components BCC and 5 2 CONNECTOR SIGNAL DESCRIPTIONS EVK connector pin assignments are defined in Tables 5 1 through 5 12 Connector signals are identified by pin number signal mnemonic and signal name and description Table 5 1 15 the EVK connector descriptions for the BCC and PFB Table 5 1 EVK Connector Descriptions Connector Description Table BCC P1 Interconnect the BCC and 5 1 BCC P2 Interconnect the BCC and 5 2 BCC J8 Background mode connector 5 3 BCC J9 Serial communication between a PC and the BCC 5 4 PFB BCC P1 Interconnect the PFB and BCC 5 1 PFB BCC P2 Interconnect the PFB and BCC 5 2 PFB BCCDI P1 Interconnect the and 5 1 BCCDI P2 Interconnect the and 5 2 1 6 Logic analyzer connections 5 5 5 10 PFB P7 Supplies power to the EVK None PFB P8 Serial communication between a PC and the DI 5 11 PFB P9 Serial communication between a PC and the BCC 5 12 PFB P10 Battery b
18. Refresh Test MT H Random Byte Test MT I Program Test MT J TAS Test Bus error test BERR tests for internal bus access time out and internal to external bus access time out error conditions including M68332EVK D REV 1 Bus errors when accessing the BCC RAM Bus errors when reading the BCC EPROM Bus errors when accessing the PFB optional memory Internal bus access time outs when reading and writing from an undefined function code memory location internal to the MCU Internal to external bus access time outs reading or writing to an undefined function code memory location external to the MCU 3 13 MOTOROLA OPERATING INSTRUCTIONS 3 7 ASSEMBLING DISASSEMBLING PROCEDURES The assembler disassembler is an interactive one line assembler editor in which the source program is not saved Each source line is converted into machine language code and is stored in memory on a line by line basis at the time of entry In order to display an instruction the machine code is disassembled and the instruction mnemonic and operands are displayed AII valid opcodes are converted to assembly language mnemonic All invalid opcodes return a Declare Constant Word DC W conversion The memory modify mm di command lets the user create modify and debug MC68332 MCU code Assembler input must have exactly one space between the mnemonic and the operand There must be no space inside the operand field Assembler input must be terminated by a
19. Select Header Se 2 6 2 3 1 4 TxD Select Header J4 2 7 2 3 1 5 RD Select H ider 15 dette hie Ras esses 2 8 2 3 1 6 Clock Input Select Header I6 ee diua 2 9 232 UPDBBACODIPEUEAEHOTEGO cy a tutae dau gatum Nr u M EUREN E 2 11 2 3 2 1 Ul and U3 Enable Header J1 enn 2 13 2 552 2 AZ Biiable Header 72 niet e at bee ed 2 14 2 3 2 3 Wa Enable Header 73 none tit erit Peste ee ISU 2 15 2 3 2 4 2 RAM EPROM Select Header J4 2 16 2 3 2 5 2 EPROM Select Header J5 2 17 2 3 2 6 U4 EPROM Select Header J6 eene 2 18 2 3 2 71 U4RAM EPROM Select Header J7 2 19 2 3 2 8 Revision Level Select Headers J8 J13 2 20 2 3 2 9 IFETCH Select Header le ea Re 2 21 2 3 2 10 VSTBY Battery Backup Connector P10 2 23 232 11 C aprocessor Socket US 2 23 24 Installation INSHUCHONS 2 24 2A BCC PEB I Btereoniectieu u uu u Ge Reems 2 24 2 4 2 Target System BCC ss 2 25 24 3 Power Supply EVK Connection s
20. carriage return No comments are allowed after the instruction input and no line labels are permitted After each new assembler input line the new line is disassembled for the user before stepping to the new instruction The new line may assemble to a different number of bytes than the previous one For Branch if Higher or Same BHS Branch if Carry Clear BCC mnemonics disassembly displays the BCC mnemonic For Branch if Lower BLO Branch if Carry Set BCS mnemonics disassembly displays the BCS mnemonic Branch address offsets are automatically calculated by the assembler so the user should input the destination address rather than an offset value The assembler is terminated by entering a period followed by a carriage return as the only entry on the command input line Entering a carriage return alone on an input line steps to the next instruction The following pages describe how to operate the assembler disassembler by creating a typical program loop and debugging the program using CPU32Bug monitor commands A typical program loop is first assembled Routine examples then illustrate how to set a breakpoint proceed from a breakpoint display and modify registers and initiate user program execution M68332EVK D 3 14 MOTOROLA REV 1 OPERATING INSTRUCTIONS Enter the periodic interrupt timer PIT time out program starting at address 5000 EXAMPLE PROGRAM CPU32Bug gt MM 5000 DI lt CR gt 5000 5008 5012 5018 501C
21. diagnostic monitor commands HE help displays a menu of the top level directory ST self test executes self test diagnostics SD switch directories toggles between the CPU32Bug directory and the CPU32Diag directory LE loop on error loops a test at the point where an error is detected SE Stop On Error halts a test at the point where an error is detected LC loop continue loops a test or series of tests NV non verbose suppresses all error messages except PASSED or FAILED DE display error counters displays the results of a particular test ZE clear error counters resets all error counters to zero DP display pass count displays the number of passes in loop continue mode At the conclusion of each pass this command also displays other information ZP zero pass count resets the pass counter to zero Available utilities are WL Write Loop RL Read Loop WR Read Write Loop CPU tests are diagnostics tests on the CPU portion of the MC68332 MCU CPUA Register Test CPU B Instruction Test CPU C Address Mode Test CPU D Exception Processing Test M68332EVK D 3 12 MOTOROLA REV 1 OPERATING INSTRUCTIONS Memory tests verify random access memory that may reside on the BCC or the PFB A Set Function Code Set Start Address MT C Set Stop Address D Set Bus Data Width MT E March Address Test MT F Walk a Bit Test MT G
22. is the default signal Jumpers J3 and J10 can select the alternate M68332EVK D 2 18 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 2 7 U4 RAM EPROM Select Header J7 Use jumper header J7 to select RAM or EPROM as the memory device type The 15 shipped from the factory with fabricated jumpers installed on pins 1 and 2 and pins 4 and 5 shown below This is correct if RAM is installed in U4 When an EPROM is installed U4 place the jumpers on pins 2 and 3 and pins 5 and 6 refer to paragraph 2 3 2 6 Refer to the PFB schematic diagram for more detail on RAM EPROM type select signal wiring FABRICATED JUMPERS 60L256 A15 1 CS7 is the default signal Jumpers J3 and J10 can select the alternate M68332EVK D 2 19 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 2 8 Revision Level Select Headers J8 J13 Use Jumpers J8 through J13 shown below to configure the for either a revision or BCC The is shipped from the factory configured for operation with a or revision of the BCC via cut trace shorts between pins 2 and 3 of J8 J13 To configure the to function with a revision cut the traces between pins 2 and 3 of J8 J13 and place fabricated jumpers between pins 1 and 2 of J8 713 fabricated jumpers or traces J8 J13 must be in the same state either between pins 1 and 2 or 2 and 3 Refer to the PFB schematic diagram for more detail
23. output string in pointer pointer format outputs a string of characters to the default output port OUTLN output line in pointer pointer format outputs a character strings followed by a carriage return CR and a line feed lt LF gt sequence WRITE output string in pointer count format formats character strings with a count byte and outputs the string to the default output port After formatting the count byte is the first byte in the string WRITELN output line in pointer count format formats character strings with a count byte and outputs the string to the default output port After formatting the count byte is the first byte in the string PCRLF output carriage return and line feed sends a CR and a lt LF gt sequence to the default output port ERASLN erase line erases the line at the present cursor position WRITD output string with data in pointer count format uses the monitor I O routine which outputs a user string containing embedded variable fields The user passes the starting address of the string and the data stack address containing the data which 15 inserted into the string The output goes to the default output port M68332EVK D 3 10 MOTOROLA REV 1 OPERATING INSTRUCTIONS WRITDLN output line with data in pointer count format uses the monitor I O routine which outputs a user string containing embedded variable fields The user passes the starting address of the string and the data stack
24. through P6 of the PFB Mount the BCC on the target system to verify hardware design With the BCC mounted on the target system MC68332 MCU device emulation with hardware breakpoints is possible by connecting a PC to BCC connector P4 and running CPU32Bug debug monitor Logic analyzer connection may be made to connectors P1 and P2 of the BCC M68332EVK D 4 1 MOTOROLA REV 1 FUNCTIONAL DESCRIPTION LOGIC ANALYZER TERMINAL HOST LOGIC TERMINAL COMPUTER BCC ANALYZER HOST CONNECTORS COMPUTER P1 P6 TERMINAL HOST COMPUTER DI EXPANSION CONNECTORS BCC BACKGROUND MODE CONNECTOR POWER SUPPLY BACKGROUND CONNECTOR MODE CONNECTOR Figure 4 1 EVK Block Diagram M68332EVK D 4 2 MOTOROLA REV 1 FUNCTIONAL DESCRIPTION 4 3 BCC DESCRIPTION The is a tool for designing debugging and evaluating MC68332 MCU based target systems The BCC simplifies user evaluation of prototype hardware software products The BCC may be used by itself as part of the EVK or as part of the M68300EVS Evaluation System EVS Figure 4 2 is the BCC block diagram The BCC consists of these functional circuits Microcontroller unit User memory T O connectors TIMER CHANNELS TERMINAL HOST INTERFACE 1 COMPUTER 3 gt UE ADDRESS AND CONTROL LINES P4 BACKGROUND MODE P3 64K x 8 64K x8 32K x8 32Kx8 EPROM EPROM RAM RAM U1 U2 U3 U4 INTERRUPT SIGNALS P2 DATA AND CONTROL LINES Figure 4 2
25. 16 bit data bus The data bus allows dynamic sizing between 8 and 16 bit data accesses A read modify write cycle RMC signal prevents bus cycle interruption External bus arbitration is accomplished by a three line handshaking interface 4 3 1 6 Chip Selects Twelve independently programmable chip selects provide fast two cycle external memory or peripheral access Block size is programmable from 2 kilobytes through 1 megabyte Accesses can be selected for either 8 or 16 bit transfers As many as 13 wait states can be programmed for insertion during the access bus interface signals are automatically handled by the chip select logic 4 3 1 7 System Clock An on chip phase locked loop circuit generates the system clock signal to run the device up to 16 78 MHz from a 32 768 kHz watch crystal The system speed can be changed dynamically providing either high performance or low power consumption under software control The system clock is a fully static CMOS design so it is possible to completely stop the system clock via a low power stop instruction while still retaining the contents of the registers and on board RAM 4 3 1 8 Test Module The test module consolidates the microcontroller test logic into a single block to facilitate production testing user self test and system diagnostics Scan paths throughout the MC68332 provide signature analysis checks on internal logic User self test is initiated by asserting the test pin to ente
26. 22 MOVE L 5061 0120 SFFFA22 L 5012 F80001CO 2500 LPSTOP W 2500 5018 6000FFF8 BRA W 5012 501C 307C5100 MOVEA W 5100 A0 5020 327C510E MOVEA W 510E A1 5024 08390000 00FFFCOC BTST B 0 SFFFCOC L 502C 67 6 55024 CPU32Bug gt lt CR gt Display next eight instructions 502 13D800FF AO FFFCOF L 5034 B2C8 5036 6600FFEC 503A 4 73 CMPA W 503 0000FFFF ORI O O O W 5024 B SFF DO 5040 0000FFFF RI B SFF DO 5044 0000FFFF RI B SFF DO 5048 0000FFFF RI B SFF DO The message displayed on the terminal CPU32Bug MD 5100 CR 00005100 5049 5420 5449 4045 2D4F 5554 FFFF PIT TIME OUT M68332EVK D 3 16 MOTOROLA REV 1 OPERATING INSTRUCTIONS The following routines are performed on the preceding program loop TERMINAL CPU32Bug gt MD 5000 DI lt CR gt 00005000 21FC0000 501C0078 MOVE L 00005008 23FC061E 012000FF FA22 MOVE L 00005012 80001 0 2500 LPSTOP 00005018 6000FFF8 BRA W 0000501C 307C5100 MOVEA W 00005020 327C510E MOVEA W 00005024 08390000 00 BTST B 0000502C 67F6 BEQ B CPU32Bug MM 500C lt CR gt 0000500C 0120 OOFF CPU32Bug g 5000 lt CR gt Effective address 00005000 PIT TIME OU IME OU PIT IME OU ROUTINE DESCRIPTION Display memory at address 5000 5501 78 W 5061 0120 52500 55012 55100
27. EV 1 GND 5V DTROUT 1 5 7 9 11 1 15 17 13 24V DI 13 24V DI 15 TP13 11 TP9 TP7 TP5 TP3 1 MOSI 50 55 PCS2 TXD BKPT DSCLK RESET IPIPE DSO 5V GND M68332EVK D REV 1 Figure 2 4 GND 5V 4 A6 A8 10 A12 A14 A16 A18 NC VSTBY T2CLK TP14 TP12 TP10 TP8 TP6 4 2 5 SCK PCS1 PCS3 RXD FREEZE QUOT 1FETCH DSI 5V GND Expansion Connector Pin Assignments HARDWARE PREPARATION AND INSTALLATION GND 5V D1 D3 D5 D7 D9 011 013 015 RXD D MODB D CSBOOT RW TSTME TSC A22 CS9 A20 CS7 FC2 CS5 0 53 BG CS1 IRQ1 TRQ3 1RQ5 TRQ7 DSACKO AVEC DS 5120 11 5 EXTAL 5V GND 2 26 GND 5V DO D2 D4 D6 D8 D10 D12 D14 TXD XMT 232 RCV 232 MODCK A23 CS10 A21 CS8 A19 CS6 1 54 BGACK CS2 BR CSO 1 2 IRQ4 IRQ6 BERR DSACK1 RMC AS SIZ1 CLKOUT HALT 45V GND MOTOROLA HARDWARE PREPARATION AND INSTALLATION P1 P2 3 lin 7 87 cm 2 5 08 Figure 2 5 Target System Connector Dimension Requirements M68332EVK D 2 27 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 4 3 Power Supply EVK Connection The EVK requires a 5 Vdc 200 milliamps power supply for operation Use connector P7 to connect power to the EVK Contact 1 1 ground black lever Contac
28. EVK functionality Refer to Figure 2 2 for the location of the jumper headers CAUTION Depending on the application it may be necessary to cut wiring trace shorts cut trace shorts on the PCB Be careful not to cut adjacent PCB wiring traces 64 Pin Expansion Connector Background Mode VSTBY Connector J1 Select DNE RxD RAM Chip Select J2 Select Clock Input Select 47 RS 232C Serial _ EPROM Chip Communication us Select J8 64 Pin Expansion Connector Figure 2 2 BCC Jumper Header and Connector Location Diagram M68332EVK D 2 3 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 1 1 VSTBY Select Header J1 Use the two pin jumper header J1 shown below to select a voltage standby VSTBY power supply source VSTB Y provides battery backup to the RAM contained in the MC68332 MCU device 1 shipped from the factory with VSTBY connected to ground GND via cut trace short To power VSTBY with an external supply cut the trace on the bottom of the PCB and connect an external power supply between P1 pin 28 and any BCC ground pin Refer to the BCC schematic diagram for more detail on VSTBY signal wiring 64 Pin Expansion Connector Fabricated Jumper VSTBY MC68332 MCU NOTE If the cut trace short on jumper header is cut a user supplied fabricated jumper must be installed on J1 to return the to its default setting M68332EVK D 2 4 MOTORO
29. ING INSTRUCTIONS CPU32Bug consists of Memory and register display and modification commands e Breakpoint capabilities System calls e Diagnostic commands Asingle line assembler disassembler parameter area for user customization There are two modes of operation in the CPU32Bug monitor the debugger mode and the diagnostic mode When the user is in the debugger directory the prompt CPU32Bug gt appears and the user has access to the debugger commands refer to paragraph 3 5 When the user is in the diagnostic mode the prompt CPU32Diag gt appears and the user has access to the diagnostic commands refer to paragraph 3 5 4 These modes are also called directories CPU32Bug is command driven and performs various operations in response to user commands entered at the keyboard CPU32Bug executes entered commands upon completion the prompt reappears However if a command is entered which causes execution of user target code 1 GO control may or may not return to CPU32Bug This depends upon the user program function Entering the help HE command provides a list of all possible commands and their structure M68332EVK D 3 2 MOTOROLA REV 1 3 3 CONTROL SWITCHES OPERATING INSTRUCTIONS The two EVK switches switches SW1 and SW2 control the reset and abort functions Table 3 1 lists these switches by name description and function Name PFB SW1 ABORT Switch PFB SW2 3 4 LIMITATIONS BCC
30. If you install an EPROM in U4 and desire a program to execute during reset or power up place the fabricated jumper across pins 2 and 3 and disable the EPROM on the BCC refer to paragraph 2 3 1 4 Jumper headers J2 and J3 must be configured the same for EPROMs installed in locations U2 and U4 Refer to the schematic diagram for more detail on chip enable signal wiring FABRICATED JUMPER 60L256 1 R W CS7 are default signals Jumpers 77 and 710 respectively can select the alternates M68332EVK D 2 15 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 2 4 U2 RAM EPROM Select Header J4 Use jumper header J4 to select RAM or EPROM as the memory device type The 15 shipped from the factory with fabricated jumpers installed on pins 1 and 2 and pins 4 and 5 shown below This is correct if RAM is installed U2 When EPROM is installed U2 place the jumpers on pins 2 and 3 and pins 5 and 6 refer to paragraph 2 3 2 5 Refer to the PFB schematic diagram for more detail on RAM EPROM type select signal wiring FABRICATED F JUMPERS 60L256 A15 1 CS6 is the default signal Jumpers J2 and J11 can select the alternate M68332EVK D 2 16 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 2 5 U2 EPROM Select Header J5 Use jumper header 75 shown below when 15 to be installed in U2 Two types of EPROM can be used 27 256 and 27 512 For 27C256 instal
31. L When TSC is 10 volts 2 X this input signal forces all output drivers to a high impedance state 30 34 23 510 ADDRESS BUS 19 23 Three state output address A22 CS9 bus A21 CS8 A20 CS7 CHIP SELECTS 6 10 Output signals that select 1 9 CS6 peripheral memory devices at programmed addresses M68332EVK D 5 5 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 3 P2 Expansion Connector Pin Assignments continued Signal Mnemonic Pin Number Signal Name And Description 35 37 2 5 FUNCTION CODES Three state output signals that FC1 CS4 identify the processor state and address space of the FCo CS3 current bus cycle CHIP SELECTS 3 5 Output signals that select peripheral memory devices at programmed addresses 38 BGACK BUS GRANT ACKNOWLEDGE Active low input signal that indicates that an external device has assumed control of the bus CS2 CHIP SELECT 2 Output signal that selects peripheral memory devices at programmed addresses 39 BG BUS GRANT Active low output signal that indicates that the current bus cycle is complete and the MC68332 has relinquished the bus CS1 CHIP SELECT 1 Output signal that selects peripheral memory devices at programmed addresses 40 BR BUS REQUEST Active low input signal that indicates that an external device requests bus master ship CSO CHIP SELECT 0 Output signal that selects peripheral memory devices at programmed addresse
32. LA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 1 2 RAM Chip Enable Select Header J2 Use the three pin jumper header J2 shown below to enable disable selection of the on board RAM The BCC is shipped from the factory with the RAM chip select connected to GND via a cut trace short on the bottom of the BCC PCB between pins 1 and 2 A fabricated jumper is also installed between pins 1 and 2 The cut trace short or a fabricated jumper between pins 1 and 2 enables the BCC on board RAM BR CSO 52 BG CS1 U4 U3 27 WE 27 WE 5V 3 OE 22 2 20 20 GND 1 t CS CS 6206 MCM6206 Fabricated Jumper To disable the RAM from the BCC memory map cut the trace on the solder side of the board on J2 between pins 1 and 2 and move the fabricated jumper to pins 2 and 3 This jumper disables selection of the on board RAM by connecting chip enable to 5V The chip selects are now free for other uses Refer to the BCC schematic diagram for more detail on RAM chip select signal wiring CAUTION Do not connect the jumper between pins 2 and 3 before removing the cut trace short between pins 1 and 2 Installing the jumper before the cut trace short is removed connects 5Vdc to ground If 5Vdc is shorted to ground or power supply may be damaged NOTE If the cut trace short on jumper header J2 is cut the fabricated jumper must be reinstalled on J2 pins 1 and 2 to return the BCC to its default setting
33. M68332EVK D REV 1 October 1993 M68332EVK EVALUATION KIT USER S MANUAL MOTOROLA INC 1991 1993 Rights Reserved Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part CPU32Bug is a trademark of Motorola Inc White Knight is a trademark of FreeSoft Company MacTerminal Apple and Macintosh ar
34. M68332EVK D 2 5 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 1 3 EPROM Chip Select Header J3 When power 1 applied or reset occurs the MC68332 MCU device resets itself and downloads the program in U1 amp U2 The EPROM contains the boot program Use the three pin jumper header J3 shown below to disable the BCC on board EPROM The BCC is shipped from the factory with the EPROM connected to the MCU bootstrap chip select pin CSBOOT via a cut trace short on the bottom of the BCC PCB between pins 1 and 2 A fabricated jumper is also installed between pins 1 and 2 To boot from a program stored in memory located in the target system cut this trace move the jumper to pins 2 and 3 and connect CSBOOT to the target system via P2 pin 25 Cutting the cut trace short and moving the fabricated jumper to pins 2 and 3 removes U1 amp U2 from the BCC memory map Refer to the BCC schematic diagram for more detail on CSBOOT signal wiring GND Fabricated Jumper U5 CSBOOT MC68332 MCU 64 Pin Expansion Connector CAUTION Do not connect the jumper between pins 2 and 3 before removing the cut trace short between pins 1 and 2 Installing the jumper before the cut trace short is removed connects 5Vdc to CSBOOT If 5Vdc is shorted to CSBOOT the MCU may be damaged NOTE If the cut trace short on jumper header J3 is cut the fabricated jumper must be reinstalled on J3 pins 1 and 2 to return
35. N 4 3 3 I O Connectors There are two 64 pin expansion connectors on the and 2 Through these connectors the BCC communicates with the PFB or target system Background mode operation is available through P3 and serial communication through P4 Chapter 5 contains a description of the interface connectors pin assignments 4 3 3 1 64 Expansion Connectors The expansion connectors interconnect the BCC to the or target system The pin outs of the 68332 MCU device serial communication and background mode interface are available on the expansion connectors 4 3 3 2 Serial Communication Connectors A terminal or host computer with terminal emulation PCKERMIT EXE etc can be connected to the BCC or to the PFB Terminal connections are provided through the serial communication connectors BCC P4 or to PFB P9 4 3 3 3 Background Mode Interface Connector The background debug mode is implemented MCU microcode In background mode registers can be viewed or altered memory can be read or written and test features can be executed Background mode is initiated by one of several sources externally generated breakpoints internal peripherally generated breakpoints software and catastrophic exception conditions Instruction execution is suspended for the duration of background mode Background mode communications between the BCC and the development system are via a serial link P3 4 4 PFB DESC
36. Pin Assignments continued Signal Mnemonic Pin Number Signal Name And Description 18 5 MASTER IN SLAVE OUT Serial input to the QSPI in master mode and serial output from the QSPI in slave mode 19 MOSI MASTER OUT SLAVE IN Serial output from the OSPI in master mode and serial input to the QSPI in slave mode 20 GND GROUND Table 5 12 PFB P8 Connector Pin Assignments Signal Mnemonic Pin Number Signal Name And Description 1 DCD DATA CARRIER DETECT Not connected 2 RXD RECEIVE DATA RS 232C serial input signal 3 TXD TRANSMIT RS 232C serial output signal 4 DTR DATA TERMINAL READY Not connected 5 GND GROUND 6 DSR DATA SET READY An output signal held high that indicates an on line in service active status 7 RTS REQUEST TO SEND Not connected 8 CTS CLEAR TO SEND An output signal that indicates a ready to transfer data status 9 NC Not connected M68332EVK D 5 16 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 13 PFB P9 Connector Pin Assignments Signal Mnemonic Pin Number Signal Name And Description 1 DATA CARRIER DETECT Not connected 2 RXD RECEIVE DATA RS 232C serial input signal 3 TXD TRANSMIT RS 232C serial output signal 4 DTR DATA TERMINAL READY An output line that indicates an on line in service active status 5 GND GROUND 6 DSR DATA SET READY An output signal held high
37. RESET Switch Table 3 1 EVK Control Switches Description And Function The PFB reset switch returns the BCC to a known state Reset causes a total BCC initialization equivalent to the power up sequence All static variables are restored to their default states The serial ports are reset to their default state The breakpoint table is cleared The offset registers are cleared The target registers are invalidated Input and output character queues are cleared On board devices timer serial ports etc are reset Use reset if the MC68332 MCU halts for example after a halt monitor fault or if the user program environment is lost vector table is destroyed etc The PFB abort switch terminates all in process instructions When the abort switch is pressed while running target code a snapshot of the processor state is captured and stored in the target registers For this reason abort is appropriate when terminating a user program that is being debugged Use abort to regain control if the program gets caught in a loop etc The target PC stack pointers etc help pinpoint malfunctions Abort generates a non maskable level seven interrupt The target registers reflect the MC68332 MCU device state at the time of an abort and are displayed on the terminal screen Any breakpoints installed in the user code are removed and the breakpoint table remains intact Control is then returned to the user CPU32Bug requires these system r
38. RIPTION The PFB is the physical location for installing the BCC The user may expand the user accessible memory I O connectors are available for communication power and a logic analyzer 441 Floating Point Coprocessor Socket U5 Socket US on accommodates an optional coprocessor for the EVK Either an MC68881 or an MC68882 coprocessor can be used in socket U5 The coprocessor software interface is not part of the EVK so must be provided by the user For developing the coprocessor software interface see the application note MC68881 Floating Point Coprocessor as a Peripheral in an M68000 System AN947 The coprocessor interface is a transparent logical extension of the MC68332 MCU device registers and instructions To the external environment the CPU and coprocessor execution model appear to be on the same chip M68332EVK D 4 8 MOTOROLA REV 1 FUNCTIONAL DESCRIPTION coprocessor interface is an execution model based on sequential instruction execution by the CPU and coprocessor For optimum performance the coprocessor interface lets floating point instructions execute concurrently with CPU integer instructions Concurrent instruction execution 1s further extended by the coprocessor which executes multiple floating point instructions simultaneously 44 2 Logic Analyzer Connectors To debug hardware and software developed for the 68331 MCU device connect a logic analyzer to the desired pins of connectors P1
39. VK consists of two printed circuit boards the BCC and the PFB The BCC operates as a single board computer or as a well defined core in larger applications Mounted on the BCC are a microcontroller on board memory and serial level converter circuitry The BCC also has a 4 pin connector for serial communication The 64 pin expansion connectors provide access to most of the MC68332 MCU pins The is the physical location for installing the BCC and Development Interface DI The user may also expand the BCC user accessible memory by installing RAM or EPROM in sockets on the PFB PFB RAM EPROM sockets may be configured for autoboot The PFB has two DB 9 terminal I O ports for communicating with the BCC from a host computer or terminal The PFB also has the BCC power connector See Chapter 2 for I O connector pin outs and Chapter 5 for interface connector pin assignments and signal descriptions The M68CPU32BUG Debug Monitor CPU32Bug is stored in EPROMs CPU32Bug is a software evaluation and debug tool that may be used to develop systems built around the MCU Using the debug monitor the user interacts with the EVK through monitor commands that are entered at the terminal host computer keyboard These commands perform functions such as modification of memory modification of MCU internal registers program execution under various levels of control and access to various I O peripherals in the MCU itself User programs may be downl
40. ackup for MC68332 MCU internal None 11 Background mode connector 5 3 M68332EVK D 5 1 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 2 P1 Expansion Connector Pin Assignments Signal Mnemonic Pin Number Signal Name And Description 1 2 GND GROUND 3 4 VDD SYSTEM POWER SUPPLY 5 volt power source 5 DTROUT DATA TERMINAL READY OUT RS 232C handshake signal from the 6 24 AO A18 ADDRESS BUS Three state output address bus 25 EPROM W EPROM WRITE Active low input write strobe that enables the on board EPROM 26 EPROM VPP EPROM PROGRAMMING VOLTAGE 12 5 Vdc input programming voltage 27 13 24 DI 13 24 VOLTS DEVELOPMENT Power converter voltage 15 volts 28 VSTBY VOLTAGE STANDBY Input standby voltage source for MCU on chip RAM 29 13 24V DI 13 24 VOLTS DEVELOPMENT INTER FACE Power converter voltage 15 volts 30 T2CLK TPU CLOCK External input clock source to the TPU 31 46 15 TIME PROCESSOR UNIT CHANNELS Input output channels 47 MOSI MASTER OUT SLAVE IN Serial output from the OSPI in master mode and serial input to the QSPI in slave mode 48 MISO MASTER IN SLAVE OUT Serial input to the QSPI in master mode and serial output from the QSPI in slave mode M68332EVK D 5 2 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 2 P1 Expansion Connector Pin Assi
41. address containing the data which is inserted into the string The output goes to the default output port SNDBRK send break sends a break to the default output port TM INI timer initialization initializes the MC68331 MCU device periodic interrupt timer TM STRO start timer at T 0 resets the timer to zero and starts it TM RD read timer reads the timer count DELAY timer delay generates timing delays RETURN return to CPU32Bug returns control to CPU32Bug from the target program BINDEC convert binary to Binary Coded Decimal calculates the BCD equivalent of a specified binary number CHANGEYV parse value parses value in user specified buffer STRCMP compare two strings in pointer count format compares equality and returns a Boolean flag to the caller MULU32 multiply two 32 bit unsigned integers multiplies two 32 bit unsigned integers and returns the product on the stack as a 32 bit unsigned integer DIVU32 divide two 32 bit unsigned integers divides two 32 bit unsigned integers and returns the quotient on the stack as a 32 bit unsigned integer M68332EVK D 3 11 MOTOROLA REV 1 OPERATING INSTRUCTIONS 3 6 4 Diagnostic Monitor The diagnostic monitor 1s a series of self tests for the MC68332 MCU device The diagnostic monitor is programmed into the EPROM For more information on the diagnostic monitor refer to Chapter 6 of the M68CPU32BUG Debug Monitor Users Manual M68CPU32BUG ADI The
42. ading operations To perform IBM PC to EVK downloading procedure EXAMPLE DESCRIPTION C gt KERMIT lt CR gt IBM PC prompt Enter Kermit program Kermit MS VX XX Type for help Kermit MS gt SET BAUD 9600 lt CR gt Set IBM PC baud rate Kermit MS gt CONNECT lt CR gt Connect IBM PC to Connecting to host type Control to return to lt CR gt CPU32Bug gt LO lt CR gt EVK download command via terminal port entered CTRL Kermit MS gt PUSH lt CR gt The IBM Personal Computer DOS Version X XX C Copyright IBM Corp 1981 1982 1983 C gt TYPE File Name gt COM1 lt CR gt Motorola S record file name C gt EXIT lt CR gt S record downloading completed Kermit MS gt CONNECT lt CR gt Return to EVK monitor program The underline cursor flashes and the beeper sounds when the 5 finishes downloading Press the carriage return twice to return to the CPU32Bug prompt lt CR gt lt CR gt CPU32Bug gt Q PU32Bug gt CTRL C ERMIT MS gt EXIT lt CR gt Exit Kermit program N M68332EVK D 3 22 MOTOROLA REV 1 OPERATING INSTRUCTIONS 3 8 4 IBM PC with PROCOMM to EVK Execute program b Set up PROCOMM to match the EVK baud rate and protocol type Alt P then the number 11 as follows 9600 baud no parity 8 bits 1 stop bit full duplex Setup ASCII transfer parameters type Alt S then the number 6 as follows Echo Local No
43. ating that 19 character pairs representing 19 bytes of binary data follow 00 Four character 2 byte address field hexadecimal address 0000 where the data which 00 follows is to be loaded M68332EVK D A 3 MOTOROLA REV 1 APPENDIX A The next 16 character pairs of the first S1 record are the ASCII bytes of the actual program code data In this assembly language example the hexadecimal opcodes of the program are written sequence the code data fields of the 51 records OPCODE INSTRUCTION 285 MOVE L A7 A4 245F MOVE L A7 A2 2212 MOVE L A2 DI 226A0004 MOVE L 4 2 1 24290008 MOVE L FUNCTION A1 D2 237C MOVE L FORCEFUNC FUNCTION A1 The balance of this code is continued in the code data fields of the remaining 51 records and stored in memory 2A The checksum of the first S1 record The second and third S1 records also each contain 13 19 character pairs and are ended with checksums 13 and 52 respectively The fourth 51 record contains 07 character pairs and has a checksum of 92 The S9 record is explained as follows S9 S record type S9 indicating that it is a termination record 03 Hexadecimal 03 indicating that three character pairs 3 bytes follow 00 00 The address field zeros FC The checksum of the S9 record Each printable character in an S record is encoded in a hexadecimal ASCII in this example representation of the binary bits which are actually transmitted For example th
44. ble 3 2 BCC Rev A Chip Selection Summary Signal Board Chip Description Memory Type CSBOOT BCCU ICPU32Bug EPROM cso BCCU lread write enable for MSB UPPER EVEN CS BCC U3 read write enable for LSB LOWER ODD RAM CS2 01 03 ead enable for MSB LSB BOTH RAM CS3 U1 write enable for LSB LOWER ODD RAM CS4 14 ead enable for MSB UPPER EVEN RAM EPROM 5 02 ead enable for LSB LOWER ODD 6 chip enable for 68881 882 CS7 unused CS8 ABORT push button autovector 59 cunused gt CS10 U3 write enable for MSB UPPER EVEN RAM cut jump U3 27 from CS4 to CS10 required M68332EVK D 3 4 MOTOROLA REV 1 Table 3 3 Rev Chip Selection Summary OPERATING INSTRUCTIONS Signal Board Chip Description Memory Type CSBOOT U2 ICPU32Bug EPROM cso BCC Ut write enable for MSB UPPER EVEN RAM CS1 BCCUS write enable for LSB LOWER ODD RAM CS2 034 read enable for MSB LSB BOTH CS3 gt 54 ABORT push button autovector CS5 PFB U5 Ichip enable for MC68881 882 cut jump U5 J3 from CS2 to CS5 required cse PFB u2 lead enable for LSB LOWER ODD RAM EPROM CS7 PFBU4 ead enable for MSB UPPER EVEN RAM EPROM CS8 1
45. continues in one of two basic modes If the command causes execution of a user program the monitor may or may not be reentered depending upon the desire of the user For the alternate case the command is executed under the control of the monitor and the system returns to a waiting condition after the command is completed During command execution additional user input may be required depending on the command function The user can use any of the commands supported by the monitor A standard input routine controls the BCC operation while the user types a command line Command processing begins only after the command line has been terminated by pressing the keyboard carriage return CR key M68332EVK D 3 7 MOTOROLA REV 1 OPERATING INSTRUCTIONS 3 6 MONITOR DESCRIPTION CPU32Bug performs various operations in response to user commands entered at the keyboard When the debugger prompt CPU32Bug gt appears on the terminal screen the debugger is ready to accept commands As the command line is entered it is stored in an internal buffer Execution begins only after the carriage return is entered This lets the user correct entry errors using the control characters described the M68CPU32BUG Debug Monitor User s Manual M68CPU32BUG ADI After the debugger executes a command it returns with the CPU32Bug gt prompt However if the entered command causes execution of user target code i e GO then control may or may not return to the d
46. d jumper 15 also installed on pins 1 and 2 To disconnect the RxD pin of the cut this trace and remove the jumper 64 Pin Expansion Connector Fabricated Jumper MC68332 MCU 64 Pin Expansion Connector NOTE If the cut trace short on jumper header J5 is cut the fabricated jumper must be reinstalled on J5 to return the BCC to its default setting Refer to the BCC schematic diagram for more detail on RxD signal wiring M68332EVK D 2 8 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 1 6 Clock Input Select Header J6 Use the three pin jumper header J6 shown below to select the on board clock source or an external clock source The BCC on board clock source is a 32 kHz crystal which is frequency multiplied by the MC68332 to a programmable operating frequency The BCC is shipped with the on board crystal selected as the clock source J6 has a cut trace short on the bottom of the BCC PCB between pins 2 and 3 A fabricated jumper is also supplied but is not required when the user uses the on board clock source Refer to the BCC schematic diagram for more detail on EXTAL signal wiring BCC On Board Oscillator MC68332 MCU 64 Pin Expansion Connector M68332EVK D 2 9 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION An optional high frequency oscillator 0 to 16 77 MHz may be used if MODCK connector P2 pin 28 is pulled to a logic low level To use the target system external
47. d rate typically 9600 baud no parity 8 bits 1 stop bit full duplex Apply power to the EVK d Press the computer keyboard carriage return CR key to display the applicable EVK monitor prompt e Enter the EVK monitor download command CPU32Bug gt LO Press lt CR gt after entering f Operate the pull down File menu and select choose Send File ASCII g Use the dialog box to select the applicable S record object file Click on Send Motorola S record file is now transferred to the EVK NOTE The S record file is not displayed during the file transfer to the EVK The underline cursor flashes and the beeper sounds when the S record finishes downloading Press the carriage return twice to return to the CPU32Bug prompt CR CR CPU32Bug M68332EVK D 3 21 MOTOROLA REV 1 OPERATING INSTRUCTIONS 3 8 3 IBM PC with KERMIT to EVK Before performing any IBM PC operation ensure that both IBM PC and EVK baud rates are 9600 and that the IBM PC asynchronous port is configured for terminal mode of operation If the asynchronous port is hard wired for host mode of operation and cannot be re configured for a terminal mode of operation the use a null modem cross coupled transmit TxD and receive RxD and associated handshake lines is required NOTE IBM PC to EVK connection requires one serial communication cable assembly This cable is connected to the EVK terminal I O port connector P9 for downlo
48. ddress 5000 and begin execution 2600 TR OFF_S_6_ USP 0000 D2 0000 D6 510E A2 0000 6 CMPA W 3 17 0000FC00 00000000 00000000 00000000 00000000 0 1 VBR 00000000 SSP 0000FFF8 D3 00000000 D7 00000000 A3 00000000 A7 0000 8 MOTOROLA OPERATING INSTRUCTIONS 3 8 DOWNLOADING PROCEDURES Downloading transfers information from a host computer to the EVK via the load LO command The procedure described below lets the user download with an IBM personal computer PC or Apple Macintosh host computer The LO command moves data in S record format see Appendix A from an external host computer to the EVK user pseudo ROM Subsections 3 8 1 through 3 8 4 list instructions for downloading to the EVK from an Apple Macintosh with MacTerminal or Red Ryder or from an IBM PC with Kermit or PROCOMM M68332EVK D 3 18 MOTOROLA REV 1 OPERATING INSTRUCTIONS 3 8 1 Apple Macintosh with MacTerminal to EVK The MacTerminal downloading program serves as a terminal emulator for the Apple Macintosh computer To download a Motorola S record file from the Apple Macintosh computer to the EVK follow these steps a Select these menu terminal settings Terminal VT100 Mode ANSI Cursor Shape Underline Line Width 80 Columns Select On Line Auto Repeat Click on OK b Select these menu compatibility settings Baud rate 9600 Bits per Character 8 Bits Parity None Handshake XOn XOff Connection Anot
49. der Uae Qu 4 9 M68332EVK D ii MOTOROLA REV 1 TABLE 5 5 SUPPORT INFORMATION Sel esi io E 5 1 5 2 Connector Signal Descriptions 5 1 APPENDIX A S RECORD INFORMATION LIST OF ILLUSTRATIONS Figure Page 2 1 Mb658332bBEVK Eval ation Kit oie He o 2 2 2 2 Jumper Header and Connector Location 2 3 2 3 Jumper Header and Connector Location Diagram 2 12 2 4 Expansion Connector Pin 2 26 2 5 Target System Connector Dimension Requirements eee 2 27 2 6 Terminal PC Cable Diagram for PFB P9 2 30 2 7 Terminal PC Cable Diagram for BCC J8 isi ette ettet erue aerae e 2 32 Al EB WK Block 4 2 2 2 aodio 4 3 4 3 EVK Memory 4 7 M68332EVK D iii MOTOROLA REV 1 TABLE 5 LIST TABLES Table Page CC SDECHICAHONS ds D I EE 1 2 1227 2 5 NS nd nn 1 3 1 3 External Equipment
50. e M68CPU32BUG Debug Monitor User s Manual M68CPU32BUG ADI The monitor uses the system exception vectors so they are unavailable to the BCC user The monitor debug exception vectors are listed in Table 3 5 The associated debugger facilities breakpoints trace mode etc will not operate if the vector offsets in the target program vector table are changed Table 3 5 CPU32Bug Exception Vectors Vector Number Offset Exception CPU32Bug Commands 4 10 Illegal Instruction breakpoints Used by GO GN GT 9 24 Trace 31 7C Level 7 interrupt ABORT switch 47 15 System calls see Chapter 5 the M68CPU32BUG Debug Monitor User s Manual M68CPU32BUG AD1 66 108 User Defined Timer Trap 15 Calls 4X Any change in the 68332 MCU device clock speed causes corresponding change the SCI baud rate The operational speed of the MCU is determined by the clock and the synthesizer control register value SYNCR or by an external clock signal applied to the EXTAL pin of the MCU The SCI baud rate is then set based on this system clock frequency If changes are made to the MCU system clock frequency changes must be made to the customization parameter area FCRYSTAL FEXTAL so the correct baud rate be calculated for SCI communications by CPU32Bug See M68CPU32BUG Debug Monitor Users Manual M68CPU32BUG ADI Appendix C for details Additional
51. e first 51 record above is sent as ore LENGTH ADDRESS CODE DATA CHECKSUM 0101 0011 0011100011 0011 0001 0011 0011 0011 0000 0011 0000 0011 0000 00111 0000 0011 0010 0011 1000 0011 T 0011 0010 0100 0001 M68332EVK D A 4 MOTOROLA REV 1
52. e instruction pipeline DSO DEVELOPMENT SERIAL OUT Serial output for background debug mode indicates when the CPU is performing an instruction word pre fetch and when the instruction pipeline has been flushed DSI DEVELOPMENT SERIAL IN Serial data input for background debug mode VDD 5 VOLT INPUT POWER 60 IFETCH INSTRUCTION Active low output signal that 61 62 63 64 GND GROUND M68332EVK D 5 4 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 3 P2 Expansion Connector Pin Assignments Signal Mnemonic Pin Number Signal Name And Description 1 2 GND GROUND 3 4 VDD 5 VOLT INPUT POWER 5 20 DO 015 DATA BUS 16 bi directional data pins 21 DI RECEIVE DATA DEVELOPMENT INTER FACE DI receive data 22 TXD DI TRANSMIT DATA DEVELOPMENT INTER FACE DI transmit data 23 MODB DI MODE B DEVELOPMENT INTERFACE MC68HC1 1 mode B pin on the DI 24 XMT 232 TRANSMIT DATA Serial data output signal 25 CSBOOT BOOT CHIP SELECT An active low output chip select 26 RCV 232 RECEIVE DATA Serial data input signal 27 R W READ WRITE Active high output signal that indicates the direction of data transfer on the bus 28 MODCK CLOCK MODE SELECT Input signal that selects the source of the internal system clock 29 TSTME TEST MODE ENABLE Active low input signal that enables hardware for test mode TSC THREE STATE CONTRO
53. e trademarks of Apple Computer Inc IBM PC is a registered trademark of International Business Machines Corporation ProComm is a trademark of Datastorm Technologies Inc The computer program stored in the Read Only Memory of the device contains material copyrighted by Motorola Inc first published 1991 and may be used only under a license such as the License For Computer Programs Article 14 contained in Motorola s Terms and Conditions of Sale Rev 1 79 TABLE 5 TABLE OF CONTENTS CHAPTER 1 GENERAL INFORMATION Le Introduction utes bio 1 1 I SD CS ones Ud 1 1 1 3 SpecifiCatiOns sius eiie p e RUE EAR CES EN LUN S dA ER 1 2 General Descriptio 1 4 152 Required iG e ien t 1 5 2 HARDWARE PREPARATION AND INSTALLATION 2 1 IntOd etionu un uuu ASS a tisane tentes 2 1 2 2 Unpacking Instr cttoDs nnn nn SUN CERE 2 1 23 Hardware Preparation oses ooe pad vet atu ose Md SS Sq a aqu ia au 2 1 231 lt Ga eee ies ee Su GQ emn 2 3 Zac NSTBY Select Header TL idiot ed 2 4 2 3 1 2 Chip Enable Select Header J2 2 5 2341 EPROM Chip
54. ebugger This depends on the user program function For example if a breakpoint is specified control returns to the debugger when the breakpoint is encountered during user program execution The user program also returns control to the debugger by means of the TRAP 15 system call function RETURN Included as part of the CPU32Bug firmware is a single line assembler disassembler function The assembler is an interactive assembler editor in which source programs are not saved Each source line is translated into MC68332 MCU machine language code and stored line by line into memory as it is entered In order to display an instruction the machine code is disassembled and the instruction mnemonic and operands are displayed All valid MC68332 MCU instructions are supported The CPU32Bug assembler is effectively a subset of the M68000 Family Structured Assembler M68MASM It has some limitations as compared with the M68MASM assembler such as not allowing line numbers and labels however it is a useful tool for creating modifying and debugging MC68332 MCU code M68332EVK D 3 8 MOTOROLA REV 1 3 6 1 OPERATING INSTRUCTIONS Memory and Register Display and Modification Commands Various commands are available to the user for displaying and modifying memory For more information refer to Chapter 3 of the M68CPU32BUG Debug Monitor Users Manual M68CPU32BUG ADI The memory display and modification commands BF block of memory fill fil
55. ector Pin Assignments eee 5 13 5 11 Logic Analyzer Connector Pin Assignments eee 5 15 5 12 PFB P8 Connector Pm Assignments 5 16 5 13 PFB P9 Connector Pm Assignments nts ine 5 17 M68332EVK D iv MOTOROLA REV 1 GENERAL INFORMATION CHAPTER 1 GENERAL INFORMATION 1 1 INTRODUCTION This manual provides general information hardware preparation installation instructions functional description and support information for the M68332EVK Evaluation hereafter referred as EVK Appendix contains EVK downloading S record information The EVK consists of two printed circuit boards and one software program e M68332BCC Business Card Computer BCC M68300PFB Platform Board CPU32BUG Debug Monitor CPU32Bug 1 2 FEATURES The BCC consists of e MC68332 Microcontroller Unit MCU 64k x 16 bit two erasable programmable read only memories EPROMs Programmed into the BCC EPROMs is the M68CPU32BUG Debug Monitor Refer to the M68CPU32BUG Debug Monitor User s Manual M68CPU32BUG ADI 32k x 16 bit byte addressable random access memory RAM RS 232C compatible terminal host computer input output I O port Background mode interface port BCC expansion connectors The PFB consists of BCC expansion connectors for the BCC and M68300DI Developmen
56. esources to operate properly several chip selects level 7 interrupt periodic interrupt timer for timer system calls SYSCALL and system exception vectors M68332EVK D 3 3 REV 1 MOTOROLA OPERATING INSTRUCTIONS 3 4 1 Chip Select Usage The MC68332 MCU has chip select signals that enable peripheral devices The BCC requires some of these chip selects for operation making them unavailable to the user Do not remove the chip selects used by the BCC or CPU32Bug will not operate In addition to the chip selects employed on the BCC other chip selects are used elsewhere in the M68332EVK refer to Tables 3 2 through 3 4 Depending on the user s environment any or all of the chip selects may be re configured for an alternate function i e as I O or address lines Chip select pins used by the BCC and EVK cannot be used in their alternate capacities Although a chip select CS8 on Rev and CS4 on Rev and Rev BCCs is dedicated for the ABORT switch the pin is not used Instead the chip select decodes the interrupt acknowledge IACK cycle in response to a level 7 interrupt generated by the ABORT switch Refer the System Integration Module User s Manual SIM32UM AD for more information When the BCC is not mounted on the PFB these chip selects are available to the user Also if the RAM EPROM socket pairs U1 U3 U2 U4 and coprocessor socket US are not populated the chip selects are available to the user Ta
57. gnments continued Signal Mnemonic Pin Number Signal Name And Description 49 50 PERIPHERAL CHIP SELECT 0 Active low output QSPI peripheral chip select signal SS SLAVE SELECT Bi directional active low signal that places the QSPI in slave mode 50 SCK QSPI SERIAL CLOCK Input output QSPI clock Source 51 PCS2 PERIPHERAL CHIP SELECT 2 Active low output QSPI peripheral chip select 52 PCS1 PERIPHERAL CHIP SELECT 1 Active low output QSPI peripheral chip select 53 TXD TRANSMIT DATA Serial data output line 54 PCS3 PERIPHERAL CHIP SELECT 3 Active low output QSPI peripheral chip select 55 BKPT BREAKPOINT An active low input signal that places the CPU32 in background debug mode DSCLK DEVELOPMENT SYSTEM CLOCK Serial input clock for background debug mode 56 RXD RECEIVE DATA Serial data input line 57 RESET RESET Active low input output signal for initiating a system reset 58 FREEZE FREEZE Output signal that indicates that the CPU32 has entered background debug mode QUOT QUOTIENT OUT Output signal that furnishes the quotient bit of the polynomial divider for test purposes M68332EVK D 5 8 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 2 Expansion Connector Pin Assignments continued Signal Mnemonic Pin Number Signal Name And Description 59 IPIPE INSTRUCTION Active low output signal that tracks movement of words through th
58. grammed addresses 20 GND GROUND M68332EVK D 5 14 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 11 PFB P6 Logic Analyzer Connector Pin Assignments Signal Mnemonic Pin Number Signal Name And Description 1 2 NC Not connected that an external device should place valid data on the data bus During the write cycle DS indicates that valid data is on the data bus MODCK CLOCK MODE SELECT Active high input signal that DATA STROBE During a read cycle DS indicates selects the source of the internal system clock IRQ1 IRQ7 INTERRUPT REQUEST 1 7 Seven prioritized active low input lines that requests MCU synchronous interrupts IRQ7 has the highest priority 5 11 12 TXD TRANSMIT DATA Serial data output line QSPI peripheral chip select signal SS SLAVE SELECT Bi directional active low signal that places the QSPI in slave mode PCS1 PERIPHERAL CHIP SELECT 1 Active low output QSPI peripheral chip select 14 15 PCS2 PERIPHERAL CHIP SELECT 2 Active low output QSPI peripheral chip select 16 PCS3 PERIPHERAL CHIP SELECT Active low output QSPI peripheral chip select 17 SCK QSPI SERIAL CLOCK Furnishes the clock from the QSPI in master mode or to the QSPI in slave mode 13 PCSO PERIPHERAL CHIP SELECT 0 Active low output M68332EVK D 5 15 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 11 PFB P6 Logic Analyzer Connector
59. her Computer Connection Port Modem Click on OK c Select these menu file transfer settings Settings for Pasting or Sending Text Word Wrap Outgoing Text File Transfer Protocol Text Settings for Saving Lines Off Top Retain Line Breaks Click on OK M68332EVK D 3 19 MOTOROLA REV 1 OPERATING INSTRUCTIONS d Apply power to the EVK e Press the carriage return lt CR gt key to display the applicable EVK monitor prompt f computer displays the CPU32Bug gt prompt g Enter the EVK monitor download command CPU32Bug gt LO Press CR after entering LO h Operate the pull down File menu and select choose Send File i Usethe dialog box to select applicable S record object file Click on Send Motorola S record file is now transferred to the EVK NOTE The S record file is not displayed during the file transfer to the EVK The underline cursor flashes and the beeper sounds when the S record finishes downloading Press the carriage return twice to return to the CPU32Bug prompt CR CR CPU32Bug M68332EVK D 3 20 MOTOROLA REV 1 OPERATING INSTRUCTIONS 3 8 2 Apple Macintosh with White Knight to EVK The White Knight downloading program serves as a terminal emulator for the Apple Macintosh computer To download a Motorola S record file from the Apple Macintosh computer to the EVK follow these steps Execute the White Knight program b Setup the computer program to match the EVK bau
60. id to debugging target system hardware and software Logic analyzer connector pin assignments are shown below For EVK connectors P6 signal descriptions refer to Chapter 5 NC AS D14 D12 D10 D8 D6 D4 D2 DO NC DSACK1 A14 A12 A10 A8 A6 A4 A2 BKPT DSCLK RESET IPIPE DSO DSACK1 FC2 CS5 FC0 CS3 SIZ0 BGACK CS2 M68332EVK D REV 1 11 13 15 17 19 Noo 11 13 15 17 19 Noo NC D15 D13 011 09 07 05 03 01 GND NC 15 1 11 9 5 1 GND NC BERR FREEZE QUOT HALT NEW IFETCH DSACKO FC1 CS4 SIZ1 R W GND 2 33 NC T2CLK TP14 TP12 TP10 TP8 TP6 4 2 DSACKO RMC DS 51 CLKOUT A22 CS9 EB1 NC CLKOUT NC DS IRQ1 IRQ3 IRQ5 IRQ7 50 55 PCS2 SCK MOSI Now 11 13 15 17 19 Noo 11 13 15 17 19 Noo 11 13 15 17 19 OAN 12 14 16 18 20 OAN 12 14 16 18 20 NC TP15 TP13 TP11 7 5 TP3 1 GND NC AVEC AS BR CSO CSBOOT A23 CS10 A21 CS8 19 56 17 GND NC MODCK IRQ2 IRQ4 IRQ6 TXD PCS1 PCS3 MISO GND MOTOROLA HARDWARE PREPARATION AND INSTALLATION M68332EVK D 2 34 MOTOROLA REV 1 OPERATING INSTRUCTIONS CHAPTER 3 OPERATING INSTRUCTIONS 3 1 INTRODUCTION This chapter provides general information control switch descriptions limitations
61. indicates that the current bus cycle is complete and the 68332 has relinquished the bus CS1 CHIP SELECT 1 Output signal that selects peripheral memory devices at programmed addresses 8 BR BUS REQUEST Active low input signal that indicates M68332EVK D 5 11 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 9 PFB P4 Logic Analyzer Connector Pin Assignments continued Signal Mnemonic Pin Number Signal Name And Description 10 CSBOOT BOOT CHIP SELECT An active low output chip select 11 CLKOUT SYSTEM CLOCK OUTPUT internal clock output signal 12 16 23 510 ADDRESS BUS 19 23 5 bits of the 24 bit address A22 CS9 bus A21 CS8 A20 CS7 CHIP SELECTS 6 10 Enables peripherals at A19 CS6 programmed addresses 17 19 A16 A18 ADDRESS BUS 16 18 Three bits of the 24 bit address bus 20 GND GROUND M68332EVK D 5 12 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 10 PFB PS Logic Analyzer Connector Pin Assignments Signal Mnemonic Pin Number Signal Name And Description 1 2 NC Not connected 3 CLKOUT SYSTEM CLOCK OUTPUT internal clock output signal 4 BUS ERROR Active low input signal that indicates that an erroneous bus operation is being attempted 5 BKPT BREAKPOINT Active low input signal that places the CPUS2 in background debug mode DSCLK DEVELOPMENT SYSTEM CLOCK Serial input cloc
62. k for background debug mode 6 FREEZE FREEZE Indicates that the CPU has acknowledged a breakpoint or has entered background mode QUOT QUOTIENT OUT Furnishes the quotient bit of the polynomial divider for test purposes 7 RESET RESET System reset 8 HALT HALT Suspend external bus activity 9 IPIPE INSTRUCTION PIPE Tracks movement of words through the instruction pipeline DSO DEVELOPMENT SERIAL OUT Serial output for background debug mode 10 NEW IFETCH NEW INSTRUCTION FETCH NEW IFETCH is either normal IFETCH or latched IFETCH per the configuration of jumper header J14 M68332bEVK D 5 13 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 10 P5 Logic Analyzer Connector Pin Assignments continued Signal Mnemonic Pin Number Signal Name And Description 11 12 DSACK1 DATA AND SIZE ACKNOWLEDGE Terminates DSACKO asynchronous data transfers and dynamic bus sizing 13 15 FC2 CS5 FUNCTION CODES Identify the processor state and FC1 CS4 address space of the current bus cycle FC0 CS3 CHIP SELECTS 3 5 Enable peripherals at programmed addresses 16 17 SIZ1 SIZO SIZE Indicates the number of bytes remaining to be transferred during this cycle 18 R W READ WRITE Indicates the direction of data transfer on the bus 19 BGACK BUS GRANT ACKNOWLEDGE Indicates that an external device has assumed control of the bus CS2 CHIP SELECT 2 Enables peripherals at pro
63. l fabricated jumper between pins 1 and 2 for 27C512 install jumper between pins 2 and 3 Paragraph 2 3 2 4 explains jumper header J4 configuration to match memory device in location U2 Locations U2 and U4 must have the same type of memory devices either both RAM or both EPROM Refer to the PFB schematic diagram for more detail on EPROM type selection signal wiring FABRICATED JUMPERS 1 60L256 A15 JUMPER EPROM J5 1 amp 2 27C256 45 2 3 276512 1 Above diagram shows J4 in the EPROM select mode 2 56 is the default signal Jumpers J2 and J11 can select the alternate M68332EVK D 2 17 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 2 6 U4 EPROM Select Header J6 Use jumper header J6 shown below when an 15 to be installed in U4 Two types of can be used 27 256 and 27 512 For 27C256 install fabricated jumper between pins 1 and 2 for 27 512 install fabricated jumper between pins 2 and 3 Paragraph 2 3 2 7 explains jumper header J7 configuration to match memory device in location U4 Locations U4 and U2 must have the same type of memory devices either both RAM or both EPROM Refer to the schematic diagram for more detail on EPROM type selection signal wiring FABRICATED JUMPERS 1 60L256 15 16 JUMPER EPROM J6 1 amp 2 27C256 46 2 3 27C512 1 Above diagram shows J7 in the EPROM select mode 2 CST
64. ls the specified range of memory with a data pattern BM block of memory move copies the contents of the memory addresses defined by RANGE to another place in memory beginning at lt ADDR gt BS block of memory search searches the specified range of memory for a match with a user entered data pattern BV block of memory verify compares the specified range of memory against a data pattern MD memory display displays the contents of multiple memory locations MM memory modify examines and changes memory locations MS memory set writes data to memory starting at a specified address RD register display displays the contents of the MCU registers RM register modify examines and changes register contents RS register set writes data to specified register 3 6 2 Breakpoint Capabilities A breakpoint lets the user set a target code instruction address stopping point for debugging purposes Target code execution halts when a breakpoint is encountered For more information on breakpoints refer to Chapter 3 of the M68CPU32BUG Debug Monitor User s Manual M68CPU32BUG ADI The breakpoint commands BR NOBR breakpoint insert delete lets the user set a target code instruction address as a breakpoint address for debugging purposes GD go direct starts target code execution and ignores breakpoints GN go to temporary breakpoint sets a temporary breakpoint at the address of the next instruction that is the one f
65. ly CPU32Bug writes a one 1 to the module mapping MM bit of the module control register MCR This configures the register block to start at address FFFOOO As the MM bit is a write once bit the user cannot clear it to move the register block to low memory 7FF000 The user can move the register block by modifying the AND parameter detailed in Appendix C of the M68CPU32BUG Debug Monitor Users Manual M68CPU32BUG ADI M68332EVK D 3 6 MOTOROLA REV 1 OPERATING INSTRUCTIONS 3 5 OPERATING PROCEDURE A Power On Reset occurs when the user applies power to the EVK This POR resets the MCU and user I O port circuitry and passes processing control to the monitor program MC68332 MCU registers are set to their reset state during monitor power up The input serial format for the BCC terminal I O port must be configured for 8 data bits 1 stop bit no parity and 9600 baud The terminal then displays this message CPU32Bug Debugger Diagnostics Version X XX C Copyright 1991 by Motorola Inc CPU32Bug where X XX is the software revision level After initialization or return of control to the monitor the terminal displays the prompt CPU32Bug gt and waits for a response If an incorrect response is entered the terminal displays Invalid command followed by the prompt CPU32Bug gt CPU32Bug waits for a command line input from the user terminal When a proper command is entered the operation
66. nals is 50 51 52 53 54 55 MCU IFETCH LATCHED M68332EVK D 2 22 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 210 VSTBY Battery Backup Connector P10 To maintain memory the MCU during power down cut the trace on the solder side of jumper header J1 on the per paragraph 2 3 1 1 Then attach a user supplied battery or external power supply 5 Vdc at 50 pA to P10 on the PFB This provides the required voltage to preserve data in the static RAM portion of the MCU Refer to the PFB schematic diagram for more detail on VSTBY signal wiring 5 Volt Battery Backup 64 Pin Expansion Connector MC68332 2 3 2 11 Coprocessor Socket 05 Use the 68 pin gate array PGA socket U5 for installing a user supplied MC68881 or MC68882 floating point coprocessor so floating point instructions execute concurrently with MPU integer instructions Execution of floating point instructions requires user supplied interface routines Addition of the floating point coprocessor substantially decreases processor instruction execution time for floating point arithmetic M68332EVK D 2 23 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 4 INSTALLATION INSTRUCTIONS The following paragraphs describe EVK interconnections expansion connector pin assignments target system dimensions
67. oaded into RAM on the BCC or PFB For a detailed description of the CPU32Bug refer to the M68CPU32BUG Debug Monitor Users Manual M68CPU32BUG ADI To program the EPROMs you must remove the EPROMs and use an EPROM programmer M68332EVK D 1 4 MOTOROLA REV 1 GENERAL INFORMATION 1 5 EQUIPMENT REQUIRED Table 1 3 lists the external equipment requirements for EVK operation Table 1 3 External Equipment Requirements EXTERNAL EQUIPMENT terminal or host computer RS 232C compatible with a terminal emulation package PCKERMIT PROCOMM MacTerminal White Knight 1 Serial communication cable for the terminal or host computer 2 5 Vdc at 500 mA power supply 2 1 Refer to Chapter 3 for details on downloading using a host computer with terminal emulation package 2 Refer to Chapter 2 for details M68332EVK D 1 5 MOTOROLA REV 1 GENERAL INFORMATION M68332EVK D 1 6 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION 2 1 INTRODUCTION This chapter provides unpacking instructions hardware preparation and installation instructions for the EVK This description ensures the EVK is properly configured for target system operation 2 2 UNPACKING INSTRUCTIONS Unpack the BCC from shipping carton Refer to the packing list and verify that all items are present Save packing material for storing and shipping the BCC NOTE If the prod
68. ocessor Unit TPU optimizes performance of time related activities The TPU has dedicated execution unit tri level prioritized scheduler data storage RAM dual time bases and microcode ROM which drastically reduces the need for CPU intervention The TPU controls sixteen independent orthogonal channels each channel has an associated pin and perform any time function Each channel also contains a dedicated event register for both match and input capture functions Each channel can be synchronized to either of two 16 bit free running counters with a pre scaler One counter based on the system clock provides resolution of TPU system clock divided by 4 The second counter based on an external reference also provides resolution of TPU system clock divided by 8 Channels may also be linked together allowing the user to reference operations on one channel to the occurrence of a specified action on another channel providing inter task control 4 31 3 Queued Serial Module The QSM contains two serial ports The queued serial peripheral interface QSPI port provides easy peripheral expansion or inter processor communications via a full duplex synchronous three line bus data in data out and a serial clock Four programmable peripheral select pins provide address ability for as many as 16 peripheral devices A QSPI enhancement is an added queue in a small RAM This lets the QSPI handle as many as 16 serial transfers of 8 to 16 bits
69. ollowing the current instruction GT go to temporary breakpoint sets a temporary breakpoint at the current instruction and starts target code execution TT trace to temporary breakpoint sets a temporary breakpoint at a specified address and traces until encountering a breakpoint M68332EVK D 3 9 MOTOROLA REV 1 3 6 3 OPERATING INSTRUCTIONS System Calls The CPU32Bug TRAP 15 handler allows system calls from user programs A system call accesses selected functional routines contained in CPU32Bug including input and output routines TRAP 15 also transfers control to CPU32Bug at the end of a user program For more information on system calls refer to Chapter 5 of the M68CPU32BUG Debug Monitor User s Manual M68CPU32BUG ADI System calls include INCHR input character reads a character from the default input port INSTAT input serial port status checks for characters in the default input port buffer INEN input line pointer pointer format reads a line from the default input port READSTR input string pointer count format reads a string of characters from the default input port into a buffer READLN input line pointer count format reads a string of characters from the default input port CHKBRK check for break returns zero 0 status in condition code register if break status is detected at the default input port OUTCHR output character outputs a character to the default output port OUTSTR
70. on revision level signal wiring 1 2 3 owe e ee NOTE If the cut trace shorts on jumper headers J8 through J13 are cut user supplied fabricated jumpers must be installed on J8 through J13 pins 2 and 3 to return the BCC to its factory setting M68332EVK D 2 20 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 2 9 IFETCH Select Header J14 Use jumper header J14 shown below to select the latched IFETCH or MCU IFETCH signal The 15 shipped from the factory with fabricated jumpers installed between pins 1 and 2 of 114 this routes IFETCH directly from the MC68332 MCU to the logic analyzer connector P5 pin 10 When the jumper is installed on pins 2 and 3 a latched IFETCH signal is routed to the logic analyzer connector P5 pin 10 Refer to the PFB schematic diagram for more detail on IFETCH signal wiring 9 74AC10 IFETCH DSI FABRICATED JUMPER EN 74 10 10 NEW IFETCH LOGIC ANALYZER ps CONNECTOR M68332EVK D 2 21 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION Latched IFETCH is an active high signal opposite of IFETCH that signals the logic analyzer to decode an instruction from the data bus The signal characteristics are When MCU IFETCH goes low latched IFETCH goes high on the rising edge of CLKOUT beginning of S2 Latched IFETCH goes low inactive 2 10 nanoseconds after address strobe AS goes high The timing diagram for these sig
71. power supply interconnections the serial communication connector and cable and logic analyzer connectors 2 4 1 Interconnection For BCC to interconnection the BCC mounts on the shown below This configuration is the EVS standalone configuration The EVK may be used to evaluate the MCU and verify functionality of user developed code For this configuration match BCC P1 to and BCC P2 to PFB BCC P2 Figure 2 4 illustrates the expansion header pin assignments for the BCC and PFB Table 2 2 shows revision level compatibility between the BCC and PFB M68300PFB M68332BCC BCC to PFB Interconnection Table 2 2 BCC PFB Compatibility BCC REV Level PFB REV Level c M68332EVK D 2 24 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 4 2 Target System Interconnection For target system to BCC interconnection the BCC mounts on the target system as shown below Use this configuration to evaluate your hardware design The 64 pin expansion connectors provide access to most of the MC68332 MCU device pins Figure 2 4 illustrates the expansion header pin assignments for the BCC Figure 2 5 shows physical dimension requirements for installing the BCC on a target system M68332BCC SP CA Ss Connectors for BCC Target System TS Target System to BCC Interconnection M68332EVK D 2 25 MOTOROLA R
72. put signal that tracks movement of words through the instruction pipeline DSO DEVELOPMENT SERIAL OUT Serial output for background debug mode M68332EVK D 5 8 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 5 BCC P4 Connector Pin Assignments Signal Mnemonic Pin Number Signal Name And Description 1 TRANSMIT DATA RS 232C serial output data 2 GND GROUND 3 ROV RECEIVE DATA RS 232C serial input data 4 10V 10 VOLTS DC Output voltage that may be used to drive RS 232C handshake lines Table 5 6 PFB P1 Logic Analyzer Connector Pin Assignments Signal Mnemonic Pin Number 1 2 NC 3 AS 4 19 00 015 20 GND M68332EVK D REV 1 Signal Name And Description Not connected ADDRESS STROBE Active low output signal that indicates a valid address is on the address bus DATA BUS 16 bi directional data pins GROUND 5 9 MOTOROLA SUPPORT INFORMATION Table 5 7 PFB P2 Logic Analyzer Connector Pin Assignments Signal Mnemonic Pin Number Signal Name And Description 1 2 NC Not connected 3 T2CLK CLOCK External input clock source to the TPU 4 19 TPO TP15 TIME PROCESSOR UNIT CHANNELS input output channels 20 GND GROUND Table 5 8 PFB P3 Logic Analyzer Connector Pin Assignments Signal Mnemonic Pin Number 1 2 NC 3 DSACK1 4 19 AO A15 20 GND M68332EVK D
73. r test mode This test provides a pass fail response to various externally supplied test vectors 4 3 2 User Memory On board the BCC is 32k x 16 bits of RAM and 64k x 16 bits of EPROM The RAM is the debug monitor storage area and user accessible memory space the M68CPU32BUG Debug Monitor is stored in the BCC EPROMs For debug monitor functionality see the M68CPU32BUG Debug Monitor User s Manual M68CPU32BUG AD1 Figure 4 3 is the EVK memory map The PFB has sockets for 32k x 16 or 64k x 16 bit RAM or 64k x 16 bit EPROM The RAM and or EPROM supplied by the user is user accessible memory space M68332EVK D 4 6 MOTOROLA REV 1 FUNCTIONAL DESCRIPTION XXX7FF INTERNAL XXX000 FFFFFF MCU INTERNAL MODULES LUE p 120000 9 INTERNAL 5 020000 OPTIONAL RA LE U1 amp U3 2 010000 VARIABLES 2 20d CPU32BUG VECTOR 003000 TABLE SYSTEM RAM TARGET VECTOR BCC U3 amp U4 TABLE 000000 1 Consult the MCU device user s manual 2 XXbase address i programmable Internal modules such as i figured on power up reset by using the covered in Appendix C of the M68CPU32BUG Debug Monitor User s Manual M68CPU32BUG AD1 3 Floating point coprocessor MC68881 MC68882 4 See Appendix C of the M68CPU32BUG Debug Monitor User s Manual M68CPU32BUG AD1 5 Depends on the memory device type used Figure 4 3 EVK Memory Map M68332EVK D 4 7 MOTOROLA REV 1 FUNCTIONAL DESCRIPTIO
74. rmination record is used for each block of S records 57 and S8 records are usually used only when control is to be passed to a 3 or 4 byte address Normally only one header record is used although it is possible for multiple header records to occur M68332EVK D A 2 MOTOROLA REV 1 APPENDIX A S RECORDS CREATION S record format files may be produced by dump utilities debuggers linkage editors cross assemblers or cross linkers Several pro grams are available for downloading a file in S record format from a host system to microprocessor based system EXAMPLE Shown below is a typical S record format module as printed or displayed 500600004844521 51130000285 245 22122264000424290008237 2 511300100002000800082629001853812341001813 S113002041E900084E42234300182342000824A952 S113003000144ED492 S9030000FC The module consists of 50 record four 51 records and S9 record The 50 record is comprised of the following character pairs 50 06 00 00 48 44 52 1 S record type 50 indicating that it is a header record Hexadecimal 06 decimal 6 indicating that six character pairs or ASCII bytes follow Four character 2 byte address field zeros in this example ASCII H D and HDR The checksum The first S1 record is explained as follows 51 S record type S1 indicating that it is code data record to be loaded verified at a 2 byte address 13 Hexadecimal 13 decimal 19 indic
75. rs to customize EVK functionality There are several connectors associated with the PFB Through these connectors you power communicate with and access the available BCC features Figure 2 3 shows the locations of switches jumpers and connectors on the The 15 shipped from the factory with the M68332BCC Business Card Computer BCC installed in its expansion connectors Configure the the desired mode of operation per paragraphs 2 4 1 and 2 4 2 If you remove the BCC take care to fully reinsert it when installing it back on the PFB The PFB contains ABORT and RESET switches a power connector a battery backup connector and 14 jumpers see Figure 2 1 The has two pairs of LC sockets U1 U2 and U3 U4 for user supplied memory devices RAM or See table below for RAM EPROM capabilities If EPROM is installed on the PFB it may be used instead of the BCC on board EPROM PFB RAM expands BCC on board RAM The PFB jumper headers must be configured to utilize the user installed RAM or EPROM To configure these jumpers follow the instructions in the paragraphs that follow Table 2 1 Socket to Memory Device Compatibility PFB SOCKET MEMORY DEVICE U1 U3 32k bytes of RAM per socket 02 04 32k bytes of RAM per socket 32k bytes of EPROM per socket 64k bytes of EPROM per socket M68332EVK D 2 11 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION
76. s 41 47 IRQ1 IRQ7 INTERRUPT REQUEST 1 7 Seven prioritized active low input lines that request MCU synchronous interrupts IRQ7 has the highest priority 48 BERR BUS ERROR Active low input signal that indicates an erroneous bus operation attempt M68332EVK D 5 6 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 3 P2 Expansion Connector Pin Assignments continued Signal Mnemonic Pin Number Signal Name And Description 49 50 DSACKO DATA AND SIZE ACKNOWLEDGE Active low input DSACK1 signals that allow asynchronous data transfers and dynamic bus sizing between the MC68332 and external devices 51 AVEC AUTOVECTOR Active low input signal that requests an automatic vector during an interrupt acknowledge cycle 52 RMC READ MODIFY WRITE CYCLE Active low output signal that identifies the bus cycle as part of an indivisible read modify write operation 53 DS DATA STROBE Active low output signal that during a read cycle indicates that an external device should place valid data on the data bus During the write cycle DS indicates that valid data is on the data bus 54 AS ADDRESS STROBE Active low output signal that indicates that a valid address is on the address bus 55 56 SIZO 6121 TRANSFER SIZE Active high output signals that indicate the number of bytes remaining to be transferred during this cycle 57 11RESET MC68HC11 RESET Active low input signal that rese
77. s 2 28 ZA E me aa Naqa ne 2 29 245 Terminal BCC Connection 2 31 2 4 6 Logic Analyzer EVK Connection ss 2 33 M68332EVK D i MOTOROLA REV 1 TABLE 5 3 OPERATING INSTRUCTIONS Sol cS 3 1 32 General geet cee 3 1 3 3 Montrol Switthes 3 3 Sm MEI 3 3 34 1 Chip Select USAGES nd 3 4 3 4 2 Other MCU Resources Used by 2 3 6 So Mie Re LE Ad qu CL UE 3 7 3 6 Monitor Descriptio 3 8 3 6 1 Memory and Register Display and Modification Commands 3 9 3 62 Breakpoint C apabilitte Ss dpi nne SU e Mu 3 9 or E NEN Iu Calls Pn 3 10 3 6 4 Diagnostic Monitor arises sinistres 3 12 3 7 Assembling Disassembling 3 14 3 8 Downloading PrOCedUt ese eus 3 18 3 8 1 Apple Macintosh with MacTerminal to EVK 3 19 3 8 2 Apple Macintosh with White Knight to EVK 3 2 3 83 IBM PC with KERMIT to EVK ee ascent SE ARAS 3 22 3 8
78. source CMOS clock follow these steps 7 gt M68332EVK D REV 1 Turn off power to the BCC Move the fabricated jumper between pins 2 and 3 to pins 1 and 2 Supply an external oscillator to connector P2 pin 59 EXTAL Ground connector P2 pin 28 MODCK Apply power to the start the external oscillator and drive connector pin 57 RESET low NOTES If the cut trace short on jumper header J6 is cut the fabricated jumper must be reinstalled on J6 pins 2 and 3 to return the BCC to its default setting Use a hybrid oscillator when driving the MCU from an external source Any change in the MC68332 MCU device clock speed causes a corresponding change in the SCI baud rate The operational speed of the MCU is determined by the clock and the synthesizer control register value SYNCR The SCI baud rate is then set based on this system clock frequency If changes are made to the MCU speed and the terminal baud rate is not changed appropriately terminal communication will fail Refer to Appendix C of the M68CPU32BUG Debug Monitor User s Manual M68CPU32BUG ADI 2 10 Cut the printed circuit trace on the bottom of the BCC between pins 2 and 3 MOTOROLA HARDWARE PREPARATION AND INSTALLATION 2 3 2 Configuration This section of the manual describes the inspection and preparation of the PFB The PFB was factory tested and shipped with installed jumpers The user may reposition these jumpe
79. t 2 1 VDD 5 volts red lever Use 20 or 22 AWG wire for power connections For each wire trim back the insulation 1 4 in 635 cm lift the appropriate lever of P7 to release tension on the contacts then insert the bare wire into P7 and close the lever CAUTION Do not use wire larger than 20 AWG in connector P7 Such wire could damage the connector Turn off PFB power when installing the BCC or removing the BCC from the PFB Sudden power surges could damage EVK integrated circuits M68332EVK D 2 28 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 4 4 Terminal EVK Connection The has two 9 pin serial ports P8 and P9 for connection to a terminal or host computer with terminal emulation Use P9 to communicate with the BCC from a terminal or host computer P8 is not used with the EVK To connect an RS 232C compatible terminal or host computer use a user supplied cable assembly as shown in Figure 2 6 Connect one end of the cable assembly to PFB connector P9 shown below Connect the other end of the cable assembly to a user supplied terminal or host computer Refer to Chapter 5 for connector pin assignments and signal descriptions of PFB connector P9 NC DSR RXD NC TXD CTR DTR NC GND PFB P9 Terminal PC Port M68332EVK D 2 29 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION IBM PC TERMINAL DP 9 MALE SERIAL PORT NOTE Some serial communication cards require CTS DSR
80. t Interface External power supply connector Two RS 232C compatible terminal host computer I O ports Background mode interface port Memory expansion sockets Socket for MC68881 or MC68882 Coprocessor Logic analyzer interface M68332EVK D 1 1 MOTOROLA REV 1 GENERAL INFORMATION CPU32Bug includes Commands for display and modification of memory Breakpoint capabilities Anassembler disassembler useful for patching programs power up self test feature which verifies system integrity Acommand driven user interactive software debugger the debugger Auser interface which accepts commands from the system console terminal parameter area for user customization CPU32Bug is described in detail in the M68CPU32BUG Debug Monitor Users Manual M68CPU32BUG ADI 1 3 SPECIFICATIONS Tables 1 1 and 1 2 list BCC and PFB specifications Table 1 1 BCC Specifications CHARACTERISTICS SPECIFICATIONS Internal Clock External Clock Memory 32k x 16 RAM 64k x 16 EPROM Terminal Host Port Temperature Operating Storage Relative humidity Power Requirements Power Supply Battery Backup Dimensions 32 768 kHz 25 kHz to 50 1 85ns 3 clock bus cycle access 16 7 MHz 200ns 5 clock bus cycle access 16 7 MHz RS 232C compatible with internal DC DC converters for 10 volts 10 mA 25 40 to 85 0 to 90 non condensing 5 Vdc 200 milliamps min 3
81. the BCC to its default setting M68332EVK D 2 6 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 1 4 TxD Select Header J4 Jumper header J4 allows the user to disconnect the transmit TxD serial data pin of the MC68332 MCU device U5 from the RS 232C receiver driver U6 and use a target system receiver driver The 15 shipped from the factory with the receiver driver connected MCU TxD 52 via cut trace short on the bottom of the between 14 pins 1 and 2 shown below fabricated jumper 18 also installed on pins 1 and 2 To disconnect the serial pin of the cut this trace and remove the jumper 64 Pin Expansion Connector Fabricated Jumper MC68332 MCU 64 Pin Expansion Connector NOTE If the cut trace short on jumper header J4 15 cut the fabricated jumper must be reinstalled on J4 to return the BCC to its default setting Refer to the schematic diagram for more detail on TxD signal wiring M68332EVK D 2 7 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 1 5 RxD Select Header J5 Jumper header allows the user to disconnect the receive RxD serial data pin of the MC68332 MCU device U5 from the RS 232C receiver driver U6 and use a target system receiver driver The 1 shipped from the factory with receiver driver connected to RxD via cut trace short on the bottom of the BCC PCB between JS pins 1 and 2 shown below fabricate
82. ts the DI HC11 58 CLKOUT SYSTEM CLOCK OUT Output signal that is the MC68332 internal system clock 59 EXTAL EXTERNAL CLOCK INPUT External clock input for the MC68332 MCU device 60 HALT HALT Active low input output signal that suspends external bus activity to request a retry when used with BERR or for single step operation 61 62 VDD 5 VOLT INPUT POWER 63 64 GND GROUND M68332EVK D 5 7 MOTOROLA REV 1 SUPPORT INFORMATION Table 5 4 BCC P3 and PFB P10 Background Mode Connector Pin Assignments Signal Mnemonic Pin Number Signal Name And Description 1 GND GROUND 2 BKPT BREAKPOINT An active low input signal that places the CPU32 in background debug mode DSCLK DEVELOPMENT SYSTEM CLOCK Serial input clock for background debug mode 3 GND GROUND 4 FREEZE FREEZE Indicates that the CPU has acknowledged a breakpoint or has entered background mode QUOT QUOTIENT OUT Output signal that furnishes the quotient bit of the polynomial divider for test purposes 5 RESET RESET Active low input output signal for initiating a system reset 6 IFETCH INSTRUCTION Active low output signal that indicates when the CPU is performing an instruction word pre fetch and when the instruction pipeline has been flushed DSI DEVELOPMENT SERIAL IN Serial data input for background debug mode 7 VDD 5 VOLT INPUT POWER 8 IPIPE INSTRUCTION PIPE Active low out
83. uct arrives damaged save all packing material and contact the carrier s agent 2 5 HARDWARE PREPARATION The EVK has been factory tested and is shipped with installed jumpers The user may reposition these jumpers when the application requires customization of EVK functionality There are also several connectors on the EVK These connectors provide power communication and access to EVK features Figure 2 1 shows the BCC installation on the via the expansion connectors Figures 2 2 and 2 3 show the locations of switches jumpers and connectors on the EVK boards CAUTION Use caution when handling the EVK the signals are not buffered so the EVK is sensitive to static discharge M68332EVK D 2 1 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION MC68332 MCU EPROM RS 232C Connector M68332BCC Background Mode Optional Connector RAM or Connectors for DI Connectors 5 232 for BCC DI Connector RS 232C BCC Connector M68300PFB Figure 2 1 M68332EVK Evaluation Kit 1 There is RAM and EPROM on the The RAM U3 amp U4 is located under the EPROM UI amp U2 To access RAM remove the EPROM from the sockets Use caution when removing or installing the EPROM M68332EVK D 2 2 MOTOROLA REV 1 HARDWARE PREPARATION AND INSTALLATION 2 3 1 Configuration The BCC was factory tested and shipped with installed jumpers The user may reposition these jumpers to customize
84. ule may contain S records of the following types Type Description The header record for each block of S records The code data field may contain any descriptive information identifying the following block of S records The address field is normally zeros 51 record containing code data and the 2 byte address at which the code data is to reside S2 A record containing code data and the 3 byte address at which the code data is to reside S3 record containing code data and the 4 byte address at which the code data is to reside record containing the number of 51 52 63 records transmitted in particular block This count appears in the address field There is no code data field S7 A termination record for a block of S3 records The address field may optionally contain the 4 byte address of the instruction to which control is passed There is no code data field 58 A termination record for a block of S2 records The address field may optionally contain the 3 byte address of the instruction to which control is passed There is no code data field 59 A termination record for a block of S1 records The address field may optionally contain the 2 byte address of the instruction to which control is passed If not specified the first entry point specification encountered in the object module input will be used There is no code data field Only one te

M68332EVK EVALUATION KIT USER`S MANUAL

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