SystemCrafter SC User Manual
Contents
1. wwmeennnennn 33 CALL OOD ay VB II 33 POI ROSS US UGC GY NT 34 Input and Output TV DOS ccrseavuscvedstvaauans deeswersersesonsessausessbueecdasseiprsguecensanenass 34 3 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 6 3 Verilog Synthesis and SimulationN eemmnnenmn 34 crait gatelibrary AA 34 Xilinx Reset Strategy eescseessressreessecesrersesresseresrersseresserssseeseereseeesseeeee 34 Input and Output WI Ia 34 6 4 SystemC Synthesis and Simulation eese 34 eii inia oz Rd Sus AAA 35 Input and Output TY DCS ii 35 6 5 Differences Between System Level and Gate Level Simulation 35 UA Ul AUC IA 35 Tionde ve IIIA 3D Uninitialized VariaDbleSs wmeennnennnnennnennnnes 35 Duo IN GEM IVI DS Aaa 36 VEIDE Fe NS IA 36 Verlgg BD ca een E ee er es nnn ii 36 Internally Generated NAaMe cccccccecececcececencecescesecessecessecessesecensesens 36 Teg PIII Sa Na AAA AAA AAA E E E E EEE EEES 37 Deak PUNS aAA Eb IA 37 7 2 Using Your Existing C Compiler s GUI 38 Basic EEIBCIDIOS IA 38 Setup F r Vis al 38 O 40 4 www systemcrafter com User Manual 3 0 02. 34 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 5 Language Reference Block Rams Some Xilinx FPGAs also implement rams called block rams which have different timing conditions and are even more efficient See the Xilinx literature for more details SystemCrafter supports these They can be declared as follows ram blookesc uint 325 8 a this and used as normal ram Note that the data of a block ram is read according to the address on the previous clock cycle Here is an example ram bloockesc tint lt 32 gt 512 gt bD Chzs s b wrrirte 5 7 s wait b write 8 9 wait out b read 5 will be 9 ie b 8 8 from last cycle walt out b read 8 will be 7 ie b 5 5 from last cycle wait out b read 3 will be 9 ie b 8 8 from last cycle wait 35 www systemcrafter com User Manual 3 0 0 SystemCrafter g Hardware And Software Together 6 Synthesis And Simulation Guide This chapter discusses the output from SystemCrafter SC and contains the following sections e Introduction e VHDL Synthesis and Simulation e Verilog Synthesis and Simulation e SystemC Synthesis and Simulation e Differences Between System Level and Gate Level Simulation e Name Mappings 6 1 Introduction oystemCrafter compiles the input SystemC description to an RTL description in either VHDL or Verilog This can be used for simulation an
3. SystemCrafter Bringing Hardware And Software Together SystemCrafter SC User Manual Version 3 0 0 SystemCrafter Bringing Hardware And Software Together SystemCrafter Bringing Hardware And Software Together SystemCrafter SystemCrafter SC Bringing Hardware And Software Together and the logos shown above are trademarks of SystemCrafter Ltd All other trademarks are the property of their respective owners SystemCrafter Ltd does not assume any responsibility arising out of the use of any information described in this document nor does it convey any license of its rights or the rights of others SystemCrafter Ltd reserves the right to make changes to its products at any time SystemCrafter Ltd will not assume any responsibility for information described in this document SystemCrafter Ltd provides all information as is By providing information SystemCrafter Ltd makes no representation that its use is free from any claims of infringement You are responsible for obtaining any rights you may require SystemCrafter Ltd expressly disclaims any warranty whatsoever with respect to information used from this document including but not limited to any warranties or representations that the information is free from infringement as well as any implied warranties of merchantability or fitness for a particular purpose SystemCrafter Ltd assumes no obligations to correct any errors contained in this document or to advise any use
4. SystemCrafter Bringing Hardware And Software Together We can define a test bench with outputs supplying the inputs to circuit and an input which reads the output of circuit This is placed in tester h ifndef TESTER_H define TESTER_H include lt systemc h gt class tester public sc_module public SG outesc UInNt lt 2 gt gt inl inz SC OUL lt bOOl gt start sc In booli Inish lock Sc in sc uint 32 gt result void do it SC CTOR tester SC THREAD dO ILC sensitive_pos lt lt clock bi endif TESTER H In file tester cpp we can supply the inputs to circuit and read the outputs Note that we have to wait a cycle at the beginning of the test process for the circuit to be reset 16 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 3 Using SystemCrafter SC In Your Design Flow Tinclude tester Hh void tester do it start 0 wait wait for system reset walt start 1 inl 9753 in2 45 wait start 0 while finish read walt cout lt lt result is x lt result read lt lt Tin wait Main In file main cpp we can connect the circuit and the test bench together include tester LH ifdef SC GATELEVEL include GateLevel circuit h else T1nolude circurt h endif int Sc malin rint argc char argv 4 ClYCOUIL TOLIPOCUFLI tester thete
5. class circuit public sc_module public sc_in lt sc_uint lt 3 gt gt a Sc oUL so UNE gt g OULt2 Oout3 sc 3m bool clk sc IINGIE urnts3 I sc srgnal amp sc uint lt 3 gt gt 2 void do it DC OIOR GITOULL 4 SC THREAD do it Sensitive pos lt lt clk 28 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 5 Language Reference beginning of contents cIIOUIlLl el e new CIP circuit 6G TOUILA CZ new IFC UZI GITOUItz2 5 circuiti c new circuitl circeurit3 circuiti o4 new cirouitl circurbk4 s JJ end or Conten Fi beginning of connections Clini ta cl Soucth ei cl gt clkl clk C2 F 112 31 62 gt S02 SZ c2 gt c1k2 clk c3 inlisz s ISSUE c3 gt clk1 clk ed 517 1 Ca c4 gt out1 oucZ gt c4 gt cl1k1 clk end of connections bi 29 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 5 Language Reference 5 6 Separate Compilation and Black Boxes A design may be split into compilation units each of which can be compiled separately Alternatively you may wish to use another tool for part of your design and link its output with the output of SystemCrafter These related concepts are both supported If a class does not have all of its methods defined or has no constructor then it is treated as a black box which may be
6. VHDL Output From The SystemCrafter SC GUI This is the default output from SystemCrafter SC Load your SystemC source and header files into the tree view of your project Set up the Build options for your C compiler and the SystemC library and header then select Build HDL and SystemCrafter SC will generate an RTL VHDL description of your design Verilog Output From The SystemCrafter SC GUI oystemCrafter SC can output an RTL Verilog description of your design Load the source and header files into the tree view of your project Set up the Build options for your C compiler and the SystemC library and header In the Build options select the SystemCrafter options folder and enter vlog as a command line option Now select Build HDL and a Verilog description of the input design will be generated 3 3 Example Simple GCD Calculator This example calculates the greatest common divisor GCD of two 32 bit unsigned numbers SystemC class circuit public sc module Dubie po 11050 int lt 32 gt gt inl inz Ssc_out lt sc_uint lt 32 gt gt result soc in lt bool gt start clock SC o t lt pool gt Tinish void do woo 1 SC CTOR circuit 13 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 3 Using SystemCrafter SC In Your Design Flow SC THREAD do gcd sensitive pos lt lt clock void Gxrocurbrsdo godt SC uint 32 xreg yreg while 1
7. functional style constructors e g sc_uint lt 3 gt 5 references typedef templates 24 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 5 Language Reference 5 2 Expressions Unary expressions Supported Binary expressions lt lt gt gt lt gt Supported Assignment expressions Supported Conditional expression x y z Supported Postincrement postdecrement preincrement Supported and predecrement or_reduce xor_reduce Supported and reduce range x 1 x y concatenation a x where a is an array single dimensional Supported array access a x where a is variable of an appropriate Supported datatype bit selection x read x write where x is a port Supported multidimensional arrays Not supported part select range Not supported Casting is not supported but datatypes are automatically converted when required For instance sco uintse4 a SC queso Is so Uine lt D Sc unnbe l ds d a dla is permitted and it is not necessary to cast the results as in some other tools 29 www systemcrafter com User Manual 3 0 0 5 Language Reference SystemCrafter Bringing Hardware And Software Together 5 3 Statements Labeled statements case default Supported Selection statements if if else Supported Switch Iteration sta
8. gt Slare Stare ed gt inl ta c4 gt outl out2Z e4 gt cLki clk c4 gt start start 65 Fi1n1 5 cb outl out4 CSS clki elk c5 gt start start 17 end Or Connect ons circuit1 h class circuiti public so Ana urntess gt aml public sc module sc out sc BIHtse2 gt outi Sc in bool olkl ac gqmnebool start int rznstance void do it SC CTOR crirocurti SC THREAD do it sensitive pos lt lt clkl b circuit2 h SystemCrafter Bringing Hardware And Software Together 31 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 5 Language Reference class circuit2 public sc module public Sc 1n lt SCc mBinte 3 gt anZz so gu t lt so UlntL lt 3 gt gt OULZ sc ian lt bool gt olk sc_in lt bool gt start ond do Xt1 5 SC CTOR circuit 4 SC THREAD do it sensitive pos lt lt clk2 bi circuit Cpp Tinolude oircouit h void clilrcult do it while start wait while 1 out3 a read 5 walt circuit1 cpp include oircuitl h VOXd Ireo itti while start wait while 1 outl instance instance inl read walt circuit2 Cpp T1melude cirewit 1 void clfOult2 00 12814 while start wait while 1 4 32 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardw
9. used in the current compilation unit but whose definition appears elsewhere This definition may be generated by SystemCrafter or by another tool Separate Compilation The example in Section 5 5 can be used to illustrate separate compilation The files circuit h circuit cpp circuit1 h circuitl cpp circuit2 h and circuit2 cpp will look like this circuit h include ei regi tlh include oei9600it2 h class circuit public sc_module publio sc i1n lt sc mrpmtes gt a SC 3n 90 uint gt gt Di BO outs Uinl lt 3 gt gt gj SC WUTASA uint lt gt gt gt OUEZS Sc out sc W1nt lt 3 gt gt out3 Sc ocut sc ninte3 gt outi ac mepoool clk SC qnebool start sc Srgnalssc uinte gt si sc srgnaleso urnte35 gt SZ void do rxti0 OC CIOR GLECULIL 4 SC THREAD do it Sensitive pos lt lt clk beginning of contents circuitl cl new Circuiti circuit C3 rOCUILZ 702 new OiP001It24 circuri y cIlfyOCunbl cso New GLrouiltIi Circuit T circuit ce new Ccircurxtl cnirounit4 s CcIrcUltl ch new circurtli circult5 5 end of contents beginning of connections 30 www systemcrafter com User Manual 3 0 0 5 Language Reference Cl gt in a cl gt outlisl gt cGl 5clkL telk s cl gt start start g2 1n2091 5 Ca OoULZ 0925 Gz oOGLDkZ clk gt c2 gt start start c3 1mbtos2 s c3o ooULlTg s Co gt CIKI CLK C3
10. which behave somewhat like arrays The major difference is that they are enormously more efficient to implement in hardware but can only access one address index in each clock cycle oystemCrafter provides both simulation and synthesis support for rams craft systemlibrary h contains definitions for modules to aid simulation To use these you must declare your class as a subclass of sc module ram craft include craft systemlibrary h for system level simulation and only use your ram in a method of that class not a function As an example the following description declares a ram aram of length 512 which stores data of type sc uint 32 The thread writes 7 to a 5 and then reads from a 5 into the output ifndef SC SYNTHESIS include systemc h include craft systemlibrary h endif class orrocurt public se module ram crat p ublic SC Inesc urpnte2 gt Im Sc out sc uints52 gt out sc insbool clock vola do 3t YA SC CTOR CLIEOHILEb SC THREAD do it sensitive pos clock bi yord CrrOcultitdo ret fam lt sc uint lt 32 gt 512 gt aram this Brom wrriteio 33 wait out aram read 5 wait The simulation methods supplied in craft systemlibrary h will give an error during simulation if you attempt to use two different addresses in one clock cycle SystemCrafter does not give any errors or warnings Multi port rams are not supported in this version of SystemCrafter
11. 3 Example Simple GCD Calculator ccccccececcsccsssccaceccsccccrcceacscsecs 13 ccnl M 13 TSC IIIA 14 SOUT OC and Header KU vo nint aeo tidem titu DU HE EE 14 TCU DETTI O C 14 MST CC MR ETE 15 MO A E AA AAA 16 A an OC ned TERR EE TT 18 4 1 The SystemCrafter SC GUL i eiue eeesu se ses tebes eos erpx P PROUVEC OE PIIPa ad Sa PPAR 18 2 Conimand NA III 18 aS Odi 19 brun eee 19 VADE EXD IA 20 NOTOG EKIDI II E EE E E 20 Output LO SHDETEOCLOT UH 20 5 Language ReferenCe esssssesreessreessecesrerssoeesrerseseessereseersesreseereseeeseereseeesees 21 SM IOAN APY e AI 22 WA P 5 clo WI 2 Jo DALO TNNT TU TU 24 5 4 Classes Structs and PUNCTIONS cccceccccececescececeeeeceneeceeeceseneeeeneeees 29 5 5 Interconnected Classes eessessssressrsesrersereesreresrersseresrerseseessereseeeseres 26 5 6 Separate Compilation and Black BOX S sccsssssessssscrreessrrerssreeesrreeesees 27 separate COM AI defen Ted eie E Res 27 Black BOO II 30 Dig PROMI Ia 31 BO CR AA III 31 6 Synthesis and Simulation Guide mmeennnennnnennn 33 Cek INUA 0 5116 IAA eee 33 PUI TROSCE SEL aU CGY cxsecacaidawasnesasequeeadsesiasameweauaseneneonedis IM EI eda ESI IMPRIME E 33 6 2 VHDL Synthesis and Simulation
12. Language Reference 9 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 3 Using SystemCrafter SC In Your Design Flow This chapter explains how you can fit SystemCrafter SC into a design flow First the design flow is discussed in greater detail followed by a description of how this can be managed using the SystemCrafter SC graphical user interface GUI Finally a very simple design example is introduced The chapter includes the following sections e Detailed Design Flow e Using The SystemCrafter SC GUI e Example Simple GCD Calculator 3 1 Detailed Design Flow There are two flows that are used to synthesize and verify a SystemC design the first system level flow directly simulates the SystemC files you have written the second gate level flow runs SystemCrafter SC and then simulates the synthesized circuit In the following description we will assume that your SystemC description has been written in files circuit h and circuit cpp The test bench is in files tester h and tester cpp and both design and test bench are combined in main cpp 10 User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 3 Using SystemCrafter SC In Your Design Flow System Level Flow The system level flow is quite straightforward Circuit cpp main cpp and tester cpp are compiled using your C compiler and then linked together with your SystemC library to pr
13. SystemCrafter Bringing Hardware And Software Together 1 About SystemCrafter SC SystemCrafter SC is a SystemC synthesis tool This edition of SystemCrafter targets Xilinx FPGAs systemCrafter can be used either This in a hardware design flow to provide a SystemC design entry tool to be used as a front end to the Xilinx synthesis tools or in a hardware software co design flow to automatically produce hardware from selected parts of a system level model written in systemC manual describes how to use SystemCrafter to compile SystemC descriptions to hardware It assumes that the reader has already obtained and used the SystemC simulator and is familiar with the SystemC documentation These can be obtained from www systemc org systemCrafter SC version 3 0 0 has been tested using Xilinx ISE version 9 21 SystemC version 2 1 v1 Visual C net version 7 1 and gcc version 3 2 3 The manual includes the following chapters Chapter 2 Introduction shows how SystemCrafter fits into a typical design flow from a SystemC description of a circuit to a Xilinx FPGA Chapter 3 Using SystemCrafter SC In Your Design Flow describes the design process in greater detail and illustrates this using the simple GCD example provided with your SystemCrafter SC installation Chapter 4 Invocation explains how you can work with SystemCrafter SC using the graphical user interface or via the command line Alternatively you
14. ad of synchronous oa outputarchitecturename use outputarchitecturename as the name of the architecture in the VHDL output Eg oa RTL will name the architecture RIL If you use a 96s in the outputarchitecturename it will be replaced with the name of the entity Eg oa s will name the architecture circuit for an entity circuit and oa s RTL will name the architecture circuit RTL Options may start with a leading or E g crait ovH vhdl OCrrcocult cpp and craft ovh vhdl Circuit cpop are both permitted 20 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 4 Invocation 4 3 Output Files VHDL Output VHDL is the default output from SystemCrafter SC It can be generated from the SystemCrafter GUI by selecting Build VHDL after having loaded a project and setting up the build options Alternatively it can be generated from the command line using the following command craft vhdl options inputfilename See the previous section Command Line for available options Verilog Output Verilog can be generated from SystemCrafter SC from the GUI Load your oystemC project files and set up the Build options for your C compiler and the SystemC library and header file Select the SystemCrafter Options folder and enter vlog in the command line field Now if you select Build HDL SystemCrafter SC will generate a Verilog description of your design Altern
15. ardware And Software Together 7 Appendices VHDL Output Follow the previous instructions for the custom build step and enter the command line given in step 10d shown below o Program Files SystemCrafter SystemCrafter SC bin craft oh S TargetDir InputName h oc S TargetDir InputFileName InputPath When you set the gcd configuration to be GateLevel and select Build gcd systemCrafter SC will generate a set of VHDL files Verilog Output Follow the previous instructions but add the verilog output option to the command line for the custom build step c Program Files SystemCrafter SystemCrafter SC bin craft vlog oh S TargetDir S InputName h oc S TargetDir InputFileName InputPath When you set the gcd configuration to be GateLevel and select Build gcd systemCrafter SC will generate a set of Verilog files 45 www systemcrafter com User Manual 3 0 0
16. are And Software Together 5 Language Reference out2 in2 read 2 walt circuit cpp can be compiled using SystemCrafter to produce GateLevel circuit h and GateLevel circuit cpp even though the methods circuitl do_it and circuit2 do it are not defined Circuit1 and circuit2 will be treated as black boxes as their methods have not been defined and the gate level simulation output file will include GateLevel circuitl h and GateLevel circuit2 h These files will be produced when circuit1 cpp and circuit2 cpp are compiled Similarly the VHDL output of SystemCrafter will produce component declarations for circuit1 and circuit2 which enable them to be instantiated The entity and architecture definitions will be produced by SystemCrafter when circuit1 cpp and circuit2 cpp are compiled Black Boxes Instead of using SystemCrafter to produce VHDL and SystemC definitions of circuit and circuit2 they may be produced using another synthesis tool or written by hand All that is necessary to be able to carry out a gate level simulation is to provide header files GateLevel circuit1 h and GateLevel circuit2 h Similarly to be able to simulate and synthesize the VHDL output you must provide architecture and entity definitions for circuit1 and circuit2 33 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 5 Language Reference 5 7 Rams Rams are efficient hardware blocks
17. atively you can use the command line to obtain an RTL Verilog description of your SystemC input design using the following command craft vlog options inputfilename See the previous section Command Line for detailed options Default Filenames The default output filenames are based on the basefilename which is the input filename less the final extension i e the basefilename of circuit cpp is circuit and the basefilename of circuit one cpp is circuit one The default action of SystemCrafter is to write VHDL or Verilog descriptions to files whose names are based on the class function and method names in the SystemC input prefixed with basefilename and an underscore and suffixed with vhd The default name of the architecture is the basefilename suffixed with syn By default no report file or gate level SystemC files are written VHDL Example With no options functions mynamel and myname2 in file myfile cpp compile to VHDL files myfile mynamel1 vhd and myfile myname2 vhd and no 21 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 4 Invocation report file or SystemC files are written The entities will be named mynamel and myname2 and the architectures mynamel syn and myname2 syn Verilog Example With no options functions mynamel and myname2 in file myfile cpp compile to Verilog files myfile mynamel v and myfile myname2 v and no report file or SystemC file
18. can use your existing C compiler s GUI and a detailed description of this is in the section Using Your Existing C Compiler s GUI Chapter 5 Language Reference lists the subset of SystemC that is Supported by the Starter Edition of SystemCrafter Chapter 6 Synthesis and Simulation Guide discusses the different outputs of SystemCrafter SC SystemC VHDL and Verilog User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 1 About SystemCrafter SC e Chapter 7 Appendices provides general recommendations for use particularly when writing the input SystemC description 6 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 2 Introduction This chapter explains how SystemCrafter SC fits into a typical design process Starting with a SystemC description of a circuit and finishing with a programmed FPGA It includes the following sections e Design Flow e Writing System C for Synthesis 2 1 Design Flow SystemCrafter compiles a SystemC description to RTL HDL Register Transfer Level Hardware Description Language either VHDL or Verilog for further synthesis by downstream tools The user writes a SystemC model which is used with a test bench and a C compiler to simulate the design When the user is happy with their SystemC specification they can run systemCrafter SystemCrafter SC will output a VHDL or Verilog description o
19. cuit cpp tester h tester cpp and main cpp as Shown below These files are contained in the samples gcd directory of your oystemCrafter SC distribution together with Visual C project files and a oystemCrafter SC project file for use with the SystemCrafter GUI Circuit Definition ifndef CIRCUIT H define CIRCUIT H ifndef SC SYNTHESIS include systemc h endif class circuit public so module 1 DUD Lie Bc 1neso Gint lt s72 gt gt inl inz Sc onute sc uint lt 32 gt gt result sc rn bool start clock sc onmrt boolc finish v id do goo 1 SC T TOR circuit i SC THREAD do gcd sensitive pos lt lt clock by endif CIRCUIT_H The header file circuit h is shown above A macro SC SYNTHESIS is defined by the preprocessor when the file is being compiled to hardware This is used to include the SystemC library file systemc h for simulation but not for synthesis The definition of do_gcd is placed in file circuit cpp as shown below include circuit h v id oG rourtzsdo godt SC uint 32 xreg yreg while 1 do wait while start xreg inl 15 www systemcrafter com User Manual 3 0 0 3 Using SystemCrafter SC In Your Design Flow yreg in2 wait while xreg yreg if xreg gt yreg xreg else yreg walt result xreg finish wait H e finish 0 wait Test bench
20. d f wait while start xreg inl yreg 1n2 wait while xreg yreg if xreg gt yreg xreg lt yreg else yreg xreg wait result xreg finish 1 wait finish 0 wait Description The class declaration defines a class circuit which is a SystemC module It has inputs inl in2 start and clock and outputs result and finish The class has one method do_gcd which is sensitive to the positive edge of an input clock The method will wait until start is non zero It will then read the inputs inl and in2 and calculate their GCD When the calculation is complete it will then write the result to output result and raise finish to 1 for one cycle It will then iterate The definition of do_gcd initially declares two variables xreg and yreg which hold 32 bit unsigned numbers A do while loop waits until start is non zero Then inputs inl and in2 are read into xreg and yreg The GCD calculation is performed which results in the GCD being stored in xreg and yreg xreg is then written to the output result and finish is raised to 1 and then lowered to O after the next clock cycle 14 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 3 Using SystemCrafter SC In Your Design Flow Source and Header Files The description of the circuit together with a test bench can be divided into a number of files circuit h cir
21. d as an input to implementation tools which target Xilinx FPGAs such as Xilinx XST SystemCrafter also outputs a gate level SystemC description of the output VHDL or Verilog The gate level SystemC description allows you to verify that the output behaviour matches the input SystemC by running it with your oystemC test bench Xilinx Reset Strategy Xilinx FPGA devices have dedicated routing and circuitry connecting every register in the device The dedicated global GSR Global Set Reset net is asserted and released during configuration immediately after the device is configured All the flip flops and latches receive this reset and are either set or reset depending on how the registers are defined During simulation the GSR is automatically pulsed for the first 100ns any test bench must take this into account and apply a wait for at least that time 36 User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 6 Synthesis And Simulation Guide before applying stimuli to the circuit under test VHDL and Verilog have different ways of modeling the GSR signal and these are explained in sections VHDL Synthesis and Simulation and Verilog synthesis and Simulation below 6 2 VHDL Synthesis and Simulation craft_gatelibrary vhd The VHDL output uses some subprograms which are contained in the file craft gatelibrary vhd This is supplied in the vhdl subdirectory of the systemCrafter distribution Xilinx Res
22. ease by selecting the Edit option in the drop down Close the Configuration Manager window 5 Now open the gcd project properties pages 42 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 7 Appendices a Set the configuration to be All Configurations b Under C C General Additional Include Directories add the location of your systemc h include file c Under C Language enable Run Time Type Info which the SystemC libraries require d Under Linker General Additional Library Directories add the location of your systemc lib file e Under Linker Input Additional Dependencies add systemc lib f Set the configuration to be GateLevel g Under C C General Additional include directories add the include directory from your SystemCrafter SC distribution h Under C C t Preprocessor Preprocessor definitions add SC GATELEVEL 6 Now you can build the System level simulation a In the Configuration Manager window set the configuration for the gcd project to be SystemLevel b From the build menu select Build gcd c If the build completed correctly you will have an executable simulation gcd exe in the SystemLevel subdirectory 7 Now we ll setup the GateLevel simulation First we need to add the names of the synthesized files the output from SystemCrafter SC to the project a Click on source files and select add new item b Set the location i Cl
23. eful not to put spaces between the and NOTE if you cut and paste from this manual you will have to type in the speech marks again otherwise the build will not work This also applies to the other custom build instructions below e Set Description to Performing SystemCrafter SC synthesis f Set Outputs to be S TargetDir InputName h S TargetDir S InputFileName g Set Additional Dependency the to be InputDir InputName h 11 Now you can build the gate level simulation a In the Configuration Manager window set the gcd project configuration to be GateLevel b From the build menu select Build gcd c If the build completed correctly you will have an executable simulation gcd exe in the GateLevel subdirectory d Visual C will also tell you that the GateLevel circuit cpp and GateLevel circuit h have been modified outside the source editor and ask if you wish to reload This is because SystemCrafter SC has output synthesized SystemC to these files so click Yes to all Use Now when you set the gcd project configuration to be GateLevel Visual C will call SystemCrafter and run the simulation on the generated gate level SystemC description and also generate a set of VHDL files When you set the gcd project configuration to SystemLevel Visual C will run the simulation directly from the files that you have written 44 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing H
24. et Strategy oystemCrafter uses the Xilinx VHDL ROC Reset on Configuration component to emulate the behaviour of the GSR The ROC component is connected to a reset signal which is used to reset certain registers This will be optimised away by the Xilinx synthesizer Some registers do not require resetting and these are not connected to the reset signal For further details on the ROC component see the Xilinx manuals Input and Output Types The VHDL output will preserve the size of the input and output signals and produce a type std logic for types of width 1 or std logic vector for types of width greater than 1 E g an input a of type sc uint 3 will be synthesized to a input a of type std logic vector 2 downto 0 37 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 6 Synthesis And Simulation Guide 6 3 Verilog Synthesis and Simulation craft_gatelibrary v The Verilog output uses some subprograms which are contained in the file craft gatelibrary v This is supplied in the vlog subdirectory of the systemCrafter distribution Xilinx Reset Strategy SystemCrafter uses the module ROC craft defined in the craft gatelibrary v to emulate the behaviour of the GSR pulse The module has an output signal called GSR which is connected to a reset signal and is used to reset certain registers This will be optimised away by the Xilinx synthesizer Some registers do not req
25. f the circuit This can be used with an appropriate test bench for simulation and further synthesized using standard synthesis tools For Xilinx FPGAs this may be Xilinx XST and place and route tools oystemCrafter also produces a gate level SystemC description of the output HDL which can be used for verification in the original SystemC test bench The design flow for a simple SystemC to hardware flow is shown below 7 User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 2 Introduction 2 2 Writing System C for Synthesis It will be necessary to refine an initial simulatable SystemC description to be able to synthesize it to hardware No synthesis tool will be able to compile any SystemC program to efficient hardware This is because the complete SystemC language is a superset of C designed for simulation and it is not possible to compile all constructs to hardware The above is true of VHDL and Verilog which were also originally written as Simulation languages VHDL and Verilog written for simulation purposes have to be refined to use a synthesizable subset for effective synthesis SystemC is the same To refine simulatable SystemC for synthesis using SystemCrafter SC it is necessary to use the SystemC constructs that SystemCrafter SC supports 8 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 2 Introduction These are described in the chapter
26. ick browse ii Make a new subdirectory GateLevel C Set the filename to be circuit cpp 8 Now add the synthesized header file to the project a Click on header files and select add new item b Set the location to be the new GateLevel subdirectory C Set the filename to be circuit h 9 We don t want GateLevel circuit cpp and GateLevel circuit h to be used in the SystemLevel build so set the property pages accordingly a Open the property pages for GateLevel circuit cpp b Set the configuration to be SystemLevel C Set General Excluded From Build to Yes 43 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 7 Appendices d Repeat for GateLevel circuit h 10 Now we need to set up the compiler to call SystemCrafter to generate GateLevel circuit cpp and GateLevel circuit h This is done using a Custom Build Step which is a standard way of calling external tools and is well documented in the Visual C manual a Open the property pages for gcd circuit cpp NOT gcd GateLevel circuit cpp b Set the configuration to be GateLevel c Under General Tool set Custom Build Tool Click apply and you ll now be able to see entries for custom build steps d Set Command Line to be c Program Files SystemCrafter SystemCrafter SC bin craft oh S TargetDir S InputName h oc S TargetDir S InputFileName o InputPath Put this all on one line and be car
27. nch files to be added to separate nodes within the project Both system level and gate level simulations can be built For more help on using the SystemCrafter SC GUI start it up and open the help index by pressing F1 or clicking on the Help menu and selecting Help Topics Alternatively SystemCrafter may be be called from within your preferred C compiler so that you can continue to use your compiler s GUI See Appendices section Using Your Existing C Compiler s GUI 4 2 Command Line The SystemCrafter SystemC synthesizer can be called from the command line using the following command craft options inputfilename Options are oh outputhfilename write a SystemC header output file to outputhfilename You must also set option oc 19 User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 4 Invocation oc outputcfilename write a SystemC source output file to outputcfilename You must also set option oh ovh outputvhdlfilename VHDL only write the VHDL output file to files prefixed with outputvhdlfilename rpt reportfilename write a report file to reportfilename vlog write the output HDL in Verilog xr ied write the output HDL in VHDL default ove outputvlogfilename Verilog only write the Verilog output file to files prefixed with outputvlogfilename Advanced options are doasyncreset synthesize resets specified by reset signal is as asynchronous resets inste
28. ng SystemCrafter SC In Your Design Flow The output files together with the appropriate craft gatelibrary can be Simulated and synthesized to FPGAs using the Xilinx synthesis tool XST followed by the other low level tools which are supplied by Xilinx 7 is s Aa B Pt i3 in 7 N 7 N 7 Sg ind in Mu V omma a hs a a ES za ES a a we ae ES ae ES a E PU up s xe ES Ed E P a p Pd ES hu t a T E a oe 3 2 Using The SystemCrafter SC GUI The SystemCrafter SC GUI is designed to make these flows easy to run The hardware files and test bench files are added to different nodes in a tree view of the project Pressing the Build System level simulation button uses your C compiler to build a system level simulation and pressing the Build Gate level simulation builds a gate level simulation For more help on using the SystemCrafter SC GUI start it up and open the 12 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 3 Using SystemCrafter SC In Your Design Flow help index by pressing F1 or clicking on the Help menu and selecting Help Topics Alternatively you can use SystemCrafter SC within your existing C compilers GUI See the Appendix section Using Your Existing C Compiler s GUI for this which includes a detailed description of how to set up the GCD project using SystemCrafter with Visual C net 2003
29. oduce an executable simulation This is just the standard SystemC simulation route a Ew LC d p Pu d n3 ge N Pa ws a S xx X a YA E ad at ES P BJ Sec a n zA E E EN P d E d n E pe E A E a M E N a 7 Gate Level Flow SystemC output The gate level flow introduces the use of SystemCrafter SC First oSystemCrafter SC is used to synthesize circuit cpp and its include file circuit h This produces a SystemC description of the synthesized circuit which is put in the subdirectory GateLevel resulting in the files GateLevel circuit cpp and GateLevel circuit h The gate level circuit can be simulated for verification GateLevel circuit cpp main cpp and tester cpp are compiled and linked with the SystemC library to produce an executable simulation Note that main cpp now includes the synthesized header file GateLevel circuit h and that GateLevel circuit h includes a SystemC library of gate descriptions craft gatelibrary h which is contained in the include directory of your distribution VHDL and Verilog output Running SystemCrafter SC also produces a set of HDL files either VHDL or Verilog that can be used with your standard synthesis tools Additional files craft gatelibrary vhd VHDL and craft gatelibrary v Verilog are supplied as part of the SystemCrafter distribution 11 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 3 Usi
30. on on specifying asynchronous resets see the information on command line options in the Command Line section sensitive pos and sensitive neg are used to attach a clock to a thread All threads in a class must be clocked by the same clock of the same polarity SC METHODs may be clocked or unclocked Unclocked combinatorial SC METHODS must be sensitive to all inputs Clocked sc METHODs will be edge sensitive sensitive pos Or sensitive neg to a clock signal They may also be edge sensitive to a reset signal 27 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 5 Language Reference 5 5 Interconnected Classes systemCrafter will synthesize classes that have been instantiated These classes can be connected together using signals sc_signal No other SystemC channels are supported In the following example three instances of circuit1 and one instance of circuit2 are instantiated and connected together in circuit class circuiti public so module public Sc in lt s0 Uint lt Sse gt inl Sc out sc ninte3 gt Outi sc in bool clkl voad do 1t SC CIOR GL TOHLEL 4 SC_THREAD do it sensitive pos lt lt clkl bi class circuit2 public sc module public SC 1n lt sC_ DITE gt ini SC ougt sc ulnte3 gt OuUut2 sc i1n lt bool gt cLk2 void do it SC CTOR circuit2 SC THREAD do it sensitive pos lt lt clk2 bi
31. r of any correction SystemCrafter Ltd will not assume any liability for the accuracy or correctness of any support supplied to any user SystemCrafter Ltd products are not intended for use in safety or life critical applications Any use in such applications is prohibited The contents of this document are owned and copyrighted by SystemCrafter Ltd 2004 2007 SystemCrafter Ltd All Rights Reserved Except as stated herein none of the material may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means without the prior permission of SystemCrafter Ltd www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together Table of Contents 1 ADOUE SISEMI 5C esris ridire kenere RETTE EE TNE E 5 AOU OT T E E T EE E E 7 Dadi DESIT TOW AA 7 2 2 Writing System C for SyntheSsis weeennnennnnennnenn 8 3 Using SystemCrafter SC In Your Design FIOW 10 3 1 Detailed Design FIOW ccccccecececcscecencececencecensecensecesseeecensecessesesenes 10 vicino M EE 11 aT aC Cl ii 11 Dy SC COU m m 11 VHDL and Verilog OUtPUL wmeennnnennnnnnnnennneennnes 11 3 2 Using The SystemCrafter SC GUI wmeennnennnnennn 12 3
32. ription If you synthesize a class circuit with inputs a and b and output c then the gate level SystemC output contains a class with the same names Similarly the VHDL output will contain an entity circuit and the Verilog output a module with the same inputs and outputs Names which are VHDL or Verilog keywords cannot be preserved in this way as this would result in an incorrect HDL description Such names are given the suffix vhdl craft and vlog craft VHDL Example An input in will be compiled to a VHDL description with input jn vhdl craft because in is a VHDL keyword Verilog Example An input input will be compiled to a Verilog description with input input vlog craft because input is a Verilog keyword Internally Generated Names ri Internally generated names have the suffix craft 40 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 7 Appendices 7 1 Hints and Tips 41 Don t expect any synthesizer to produce efficient hardware from a SystemC program written for simulation You can make your hardware faster and smaller by thinking carefully and refining it It is much easy to start writing your SystemC project using the subset of the language supported by SystemCrafter than to use the full language and then refine your design for synthesis Think about what happens in each clock cycle Decide where to process in parallel Minimize
33. s are written The modules will be named mynamel1 and myname2 Output to a Subdirectory You can use the directory hierarchy separator in a filename to output files to a different directory For Windows this is a V so you can output all of your VHDL files to a subdirectory called vhdl using the following command cratt ovh vwhdl circuit cpp The subdirectory must already exist 22 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 5 Language Reference This chapter describes the subset of SystemC supported by the Starter Edition of SystemCrafter It contains the following sections 23 Datatypes Expressions Statements Classes Structs and Functions Interconnected Classes Separate Compilation and Black Boxes Rams User Manual 3 0 0 5 Language Reference 5 1 Datatypes SystemCrafter Bringing Hardware And Software Together The following table shows which SystemC datatypes are supported by systemCrafter SC SC 1t sc_lv unsigned int SC WINE eoo unsigned long LINE sc_bigint unsigned char unsigned SC DIguxsit COnSt bool short Single dimensional arrays Sc Dic long enum SC logic char The data types below are not supported user defined classes structs unions fixed point sc_fixed sc_fix sc_ufix sc_ufixed multi dimensional arrays floating point float double pointers
34. ster sc Signal lt sc nunte325 gt amp inl SG sanz result sc signal lt bool gt s start s finish ac clock CRI elk 1 CIFCULEI e new circuit circuiti cirourtl aglook glkl s Circuit l Sstart s Start ircuitl gt gt finishis finish circuitl 1inl s inl circuitil in2 s in2 cxXtocurtl resulrt s results thetester new tester tester thetester result s result thetester inl s inl thetester in2 s in2 thetester start s start thetester finish s finish thetester clock clkl signal 17 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 3 Using SystemCrafter SC In Your Design Flow Soc Star Cea yeturn U If the macro SC GATELEVEL is defined then the synthesized header file the output of SystemCrafter SC is included the file GateLevel circuit h otherwise the input circuit header circuit h is included This is explained in the section Detailed Design Flow 18 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 4 Invocation This chapter explains how to use SystemCrafter SC and what options are available It contains the following sections e The SystemCrafter SC GUI e Command Line e Output Files 4 1 The SystemCrafter SC GUI The SystemCrafter GUI is easy to use and helps you to manage your design flow A tree view allows design files and test be
35. tements while Supported do while for The last statement in a loop must be a wait statement Jump statements break only Supported Supported in a switch statement recurn wait Supported Used to specify a clock transition wait until Not supported Jump statements continue break other than in a switch statement Not supported 26 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 5 Language Reference 5 4 Classes Structs and Functions port types and signals sc_in Supported SC OUL Sc signal classes and structs as subclasses of Supported sc module thread processes SC THREAD Supported SC_CTHREAD SC_METHOD Supported sensitive_pos sensitive_neg Supported sensitive instance variables Supported member functions methods Supported reset signal is Supported watching local watching Not supported overloading Not supported inheritance Not supported namespaces nested name specifiers Not supported port types and signals sc_inout Not supported Classes and structs must be subclasses of sc module They can be instantiated and connected together but not used as datatypes SC THREAD SC METHOD and SC CTHREAD can be used to attach member functions to classes Reset signals can be specified using reset signal is This SystemC construct specifies a synchronous reset For informati
36. the width of variables Don t use an int where an sc _uint lt 3 gt is large enough Use unsigned widthed variables wherever possible ie sc _uint lt gt Use rams instead of arrays where possible Think about whether you can use a block ram Don t take the size of the circuit written by SystemCrafter as a useful metric the synthesis process introduces redundant logic which will be removed by downstream tools The gate level SystemC simulation will require the SystemC simulator to process much more data that the system level simulation Simulation will be faster if you split your program across several input files and only simulate one at gate level at a time Some useful macros such as SC MODULE are defined in a header file craft systemc h which is supplied in the include directory of the distribution User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 7 Appendices 7 2 Using Your Existing C Compiler s GUI You can use SystemCrafter SC within your existing C compiler s GUI This allows you to continue to use the GUI that you are familiar with and once it has been set up it is very straightforward to use The C compiler calls oystemCrafter from your compilation sequence which will then both simulate the gate level SystemC output and automatically generate HDL files for input to downstream tools You do this in a similar way to how you would call other external compilation tools such as le
37. uire resetting and these are not connected to the reset signal For further details see the Xilinx manuals Input and Output Types The Verilog output will preserve the size of the input and output signals declaring them as input or output ports to the top level module 6 4 SystemC Synthesis and Simulation oystemCrafter writes a gate level SystemC netlist which describes the same circuit as the VHDL or Verilog output This can be used in your original SystemC test bench for verifying the output of SystemCrafter craft gatelibrary h The gate level SystemC output from SystemCrafter includes a gate level library craft gatelibrary h which is supplied with your distribution This library describes standard components such as inverters and registers You will need to ensure that you add the path to this include file to the options uses in your C compiler 38 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 6 Synthesis And Simulation Guide Input and Output Types oystemCrafter preserves the types of the inputs and outputs of your circuit in the gate level SystemC description So an input a of type sc uint 3 will be synthesized to a gate level SystemC description with an input a of type sc uint lt 3 gt 6 5 Differences Between System Level and Gate Level Simulation The simulation of the SystemC input and output of SystemCrafter should produce the same results Ho
38. wever due to the properties of the SystemC simulator and gate level circuits there are some cases where a badly designed circuit or test bench could produce different results These are detailed below Reset Strategy Some registers must be reset to a known state at the beginning of the gate level simulation This is accomplished by setting the outputs of these registers to O until sc simulation time is no longer less than 1 This means that the simulation of the circuit won t start until after time step 1 Timing of sensitive neg Threads that are sensitive to the negative edge of the clock sensitive neg are implemented using an inverter in the clock line of a register This means that there may be minor timing differences between the start of the system level simulation of the thread and the start of the gate level simulation of the thread In particular these will occur if you arrange for inputs to change exactly on the clock edge which is bad practice Uninitialized Variables Variables that are used before they have been written have an undefined value in C but most compilers set them to 0 A simulation of the VHDL or Verilog description generated by SystemCrafter will use an undefined value 39 www systemcrafter com User Manual 3 0 0 SystemCrafter Bringing Hardware And Software Together 6 Synthesis And Simulation Guide 6 6 Name Mappings oystemCrafter preserves the names you have used in your system level desc
39. x or yacc Before reading this explanation make sure that you are familiar with your compiler s support for calling external tools such as lex and yacc Visual C calls this a custom build step As an example we ll show how to setup the GCD project in the samples gcd directory of your SystemCrafter SC distribution using SystemCrafter SC with Visual C net 2003 The principles apply equally to other compilers The Visual C solution and project files are contained in your distribution Basic Principles Set up two configurations GateLevel and SystemLevel In the GateLevel configuration use a custom build step to run SystemCrafter SC on circuit cpp generating two files GateLevel circuit cpp and GateLevel circuit h Include these in the project which allows them to be compiled and linked with the SystemC library producing the gate level simulation The system level simulation just uses the standard SystemC simulation on your input files and GateLevel circuit cpp and GateLevel circuit h are excluded from the build Setup For Visual C 1 Open a new Win32 console project called gcd Click on Empty Project in the application settings 2 Add circuit cpp tester cpp and main cpp as source files 3 Add circuit h and tester h as header files 4 Open the Configuration Manager For the gcd entry in the Project Contexts table add new configurations SystemLevel and GateLevel Delete configurations Debug and Rel
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