SIS8300 µTCA FOR PHYSICS Digitizer User Manual
Contents
1. Memory 256 bit buffer buffer Block Address 32 bit Address byte Address Eet sae 256 bit block 32 bit block Daf 16bit Ox0 Gei v z 256 bit block 32 bit block e 16 bit l 0x2 GA eme 256 bit block S 32 bit block x2 ee 0x2 H 32 bit block oe seeeeeene 0x3 Sg 32 bit block i 32 bit block Ox7F FEEF 256 bit block 32 bit block 32 bit block 0x7 0x80 0000 256 bit block 0x80 0001 256 bit block 0x80 0002 256 bit block OxFF FFFF 256 bit block 128 bit block 32 bit Lu OxFFF FFFC 128 bit block 32 bit Le GE 128 bit block Ki gapi tenes OxFFF FFFE 128 bit block S 32 bit Lt OxFFF FFFF Page 16 of 45 U gt EE Ke gt SIS8300 uTCA for Physics Struck Documentation ysteme Digitizer IC 7 3 ADC Sample Log D l ZE ac EEP LUD IL s6e 4 0y lw ZU LG s elJ qH ejeg oway ssalppy Aowa ac Eep BUD s6e 4 0y BU ee s6e 4 0y SIUg ICTOluUOH 21607 Aiouei 0 Adoy UIEWIOd HID AdOD 10 ulewop MIO Aowan ZH uleWOop MIO LO sdp z sdgs ver sdoos Aejeq a Lody dir 000 Id LC vvEJEP LUD xEJEP LU Byep LU a qewweibod asing 66u Lu o Aejaq yoorg indu geq TE Zug LUS Loa PEP CUD EEP CUD RED CUD Li gl asing 611 zu uleWOPp 41D GC sdpez2. 4 3 SMD LEDs A number of surface mount red LEDs are on the SIS8300 to visualize part of the board status Page 10 of 45 Salaa innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 5 Front panel The SIS8300 is a uTCA for Physics board A sketch of the front panel is shown below Page 11 of 45 Struck Documentation SIS8300 a uTCA for Physics systeme Digitizer 5 1 Harlink LVDS In Outputs The Harlink LVDS Output and Input connectors have 5 signals each The Clock signal to the left hand side is marked with C and the other 4 signals are labelled with 1 4 5 2 SMA Clock Input The front panel SMA clock input is designed to accept a maximum peak to peak signal level of 3V into 50 Ohms The clock input signal is coupled to the internal logic via a capacitor The schematic of the input stage is shown below U200 PECL 1 6 INOUT ciy KE EXT CLKAO E ZS mmm E3 GND Lei VREF o 22 EXT CLKAO N A pepe 100nF o 2 EXT CLKAI P A FERT CKAIP VT lt gt 20 EXT CLKAI N Uin max 3Vp p D 3 3V QI Rin 50 Ohm Impedanz 17 EXT CLKA2 P_ AC pope Gx mw 6 EXT CLKA2 N SE page CON200 SMA8400A 1 9000 SMA _ CLK IN CLK GND 13 i 43 3V GND s D 3 3V i 4 3 3V GND 1 GND 24 433V GND ADCLK946BCPZ Page 12 of 45 Struck Documentation SIS8300 Ste innovative uTCA for Physics systeme Digitizer 6 Boar
3. Tap delay value Bit 1 Tap delay value Bit 1 Tap delay value Bit 0 Tap delay value Bit 0 7 20 Virtex 5 System Monitor registers define SIS8300_VIRTEX5_SYSTEM_MONITOR_DATA_REG Ox90 define SIS8300_VIRTEX5_SYSTEM_MONITOR_ADDR_REG 0x91 define SIS8300_VIRTEX5_SYSTEM_MONITOR_CTRL_REG Ox92 The Virtex 5 system monitor registers give access to temperature and voltages of the FPGA on the SIS86300 Refer to the sysmon c routine and the Virtex 5 FPGA documentation for details Page 32 of 45 Seale innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 21 Trigger setup register registers define SIS8300_TRIGGER_SETUP_CH1_REG 0x100 rd wr D32 define SIS8300 TRIGGER _ SETUP_CH10_ REG 0x109 rd wr D32 These read write registers hold the 8 bit wide trigger pulse length in sample clocks the Peaking and Gap Time of the trapezoidal FIR filter Gap Time SumG Time Peaking Time Bit Function Reserved eoo e O Trigger Pulse Length SumG time only FIR trigger EE ban gaa 9 SumGbitl 8 SumGbitO S 6 reserved S Peaking time P only FIR trigger Oo PbO The power up default value reads Ox 00000000 Si Sum of ADC input sample stream from x to x P P Peaking time number of values to sum SumG SumGap time distance in clock ticks of the two running sums The maximum SumG time 16 clocks The minimun SumG time 1 clocks Values gt 16 will be set to 16 Value 0 will b
4. 0x0 The power up default value is 0 Explanation memory sample start address The contents of the sample memory start address register is assigned as memory data storage address with the arm command key address arm sampling or with the enable command key address enable sampling The read function from these registers give the information of the actual sampling address for the given ADC channel at the moment only valid if the logic is not busy The value is given in 256 bit Blocks 16bit word address x 16 Read reserved Actual Sample Memory Address in 256 bit Blocks Function 16 bit word address x 16 the power up default value is 0 Page 36 of 45 Seale innovative Struck Documentation SIS8300 uTCA for Physics gen Digitizer 7 24 Sample Length register tdefine SIS8300_SAMPLE_LENGTH_REG Oxl2A rd wr D32 This register defines the number of sample blocks of each ADC Event or The size of one sample block for each ADC channel is 256 bit 16 x 16 bit word Bit 31 24 default after Reset 0x0 7 25 Ringbuffer Pretrigger Delay register define SIS8300_PRETRIGGER_DELAY_REG OxIZB rd wrf D32 7 This register defines the number of pre trigger delay samples for all channels The maximum pre trigger delay value is 2046 Bit 31 26 Page 37 of 45 Seale Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 8 RIM management Connected RTMs shall be compliant to the P
5. systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 11 MLVDS Input Output Control register define SIS8300_MLVDS_IO CONTROL REG 0x12 rd wr D32 Read Enable LVDS Output Bit 7 Enable LVDS Output Bit 7 Enable LVDS Output Bit 6 Enable LVDS Output Bit 6 BN NEE E ee 9 LVDS Input 1 External Trigger Enable LVDS Input 1 External Trigger Enable 8 LVDS Input 0 External Trigger Enable __ LVDS Input 0 External Trigger Enable 6 LVDS Input 6 External Trigger falling edge LVDS Input Bit6 BE E BE LVDS Input External Trigger falling edge LVDS Input Bit 1 Note external trigger in signals are synchronized with the FPGA CLKO5 Page 23 of 45 Saa innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 12 Harlink Connector Input Output Control register define SIS8300_HARLINK_IO_CONTROL_REG Och f rd wr Daz Read 30 Nofunction S O E BE Ne function No function S O No function ES Nomon SO otmen Nofunction i i i i ca i i 8s 6 o Harlink Connector Input 1 external trigger In Harlink Connector Output 1 adc chx or trigger out Note external trigger in signals are synchronized with the FPGA CLKO5 Page 24 of 45 Struck Documentation SIS8300 uTCA for Physics Digitizer Seale Innovative systeme 7 13 Clock Distribution Multiplexer control register define SIS8300_CLOCK_ DISTRIBUTION _MUX_REG 0x40 The SIS8300 has 5 IDT IC
6. uTCA for Physics systeme Digitizer 7 Firmware Description 7 1 Address Map Following 32 bit addresses are implemented Function 0x000 O R O Module Identifier Firmware Version register 0x001 R Serial number register S 0x003 R XILINX Virtex5 configuration memory Error Detection register E ee eee E A EE ee E E ll RS NG NG E BB RE WE ADC SPI Interface register ADC Input Tap delay register VIRTEX5_SYSTEM_MONITOR_ADDR register VIRTEX5_SYSTEM_MONITOR_ CTRL register ADC ch2 Trigger Setup register ADC ch10 Trigger Setup register ADC ch2 Trigger Threshold register ADC ch10 Trigger Threshold register Page 14 of 45 Struck Documentation SIS8300 innovative uTCA for Physics systeme Digitizer ADC chl Memory Sample Start Address Actual Address register ADC ch2 Memory Sample Start Address Actual Address register ADC ch10 Memory Sample Start Address Actual Address register ADC chx Sample Length Register ADC chx Ringbuffer Pretrigger Delay 0 to 2046 a ee ME es ee SR ME SE E Ox200 Bit O 1 Master Reset reset all registers Page 15 of 45 Seale Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 2 Memory buffer The structure of the memory buffer with 512 MByte Ge 4 x 1 GBit memory chips is illustrated below 4 x 64M x 16bit 256M x 16bit 32M x 128bit 16M x 256bit
7. 0 18 Clear reserved 2 9 0 17 Clear reserved 1 S O O 16 _ Switch offuser LED O O 9 Setreserved9 sd Statusreserved9 S 8 Setreserved8 L it Iesel 8 6 Setreserved6 sd Statusreserved S 0O Switch on user LED Status User LED LED on 0 LED off denotes power up default setting Page 20 of 45 Saa innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 9 ADC Acquisition Control Status register define SIS8300_ACQUISITION_CONTROL_STATUS_REG 0x10 7 rd wr D32 read IL Status DDR2 Memory OK Sof Status internal Sample Buffer Not Empty 40 Status internal Sample Logic Busy a Disable Sampling Reset Sample Logic 1 T Arm Sampling Status Arm for trigger Start with next trigger Wait for trigger 1 Start Sampling immediately Status Sampling Busy Arm and Start Trigger The power up default value is 0x0 Page 21 of 45 Seale Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 10 ADC Sample Control register define SIS8300_ SAMPLE CONTROL_REG 0x11 rd wr D32 7 ADC channels can be disabled from storing data to memory by setting the corresponding disable bit in this register write WE 10 Enable internal Trigger oS 9 Disable Sampling Chi 8 Disable Sampling CH Disable Sampling Ch3 Disable Sampling Ch2 Disable Sampling Ch1 The power up default value is 0x0 10 6 3 o Page 22 of 45 Saa innovative
8. write define SIS8300_ADC_SERIAL_INTERFACE_REG 0x48 read write D32 Several parameters of the ADC AD9268 chip can be configured with the SPI serial Peripheral Interface Please refer to the documentation of the ADC AD9268 chip for details ADC Synch cmd Write Read Logic BUSY Flag e ooo S 26 ADC Select Mux Bit oo 25 ADCSelectMuxBith TI 24 ADCSelectMuxBitO 23 Read Cmd S d O C ee Al Le 20 Address Bit12 19 Address Dn II le O O a ee 12 AddressBit4 11 Address Bit3 le HO Address Bit2 le 9 Address Bitd le 8 AddressBitO S D Werite Data Bit6 Read DataBit6 E a Write Data Bit Read Data Bit 1 0 Write Data Bit 0 LSB Read Data Bit 0 LSB The power up default value is 0x0 ADC Synch Cmd generates an synch pulse with AD9510 1 FPGA clock Page 31 of 45 Seale Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 19 ADC Input Tap delay registers 0x49 define SIS3305_ADC_INPUT_TAP_DELAY Ox49 The input tap delay registers are used to adjust the FPGA data strobe timing 31 1312 Ju 0 9 8 76 50 Function None ADC 9 10 ADC 7 8 ADC 5 6 ADC 3 4 ADC 1 2 None Tap delay value Select Select Select Select Select x 78ps Blof ap Delay Logic BUSY Flag fo NN a C 12 ADC9 10SelectBit o II ADC 7 8 Select Bit Li ADC 5 6 Select Bit 9 ADC 3 4 Select Bit li 8 ADC 1 2 Select Bit LI 6 Tapdelay value Bit6 Tapdelay value Dip se BEE BEN
9. CRC 19 MOLEX 13 DAC 13 MTCA 4 38 DC 41 multiplexer A 26 design 6 multiplexer B 26 DESY 5 multiplexer C 26 ECC 19 multiplexer D 26 ERNI 13 multiplexer E 26 firmware NXP 38 version 18 ordering options 39 Firmware 14 P 33 FPGA 6 parallel load 9 front panel 11 PCF8574 38 FRU 38 PCI Express 6 functionality 6 PEN 38 Harlink 12 PICMG 5 HARTING 13 platform management 7 IANA 38 Power Consumption 39 IANA PEN 38 register ICS853S057 25 ADC Acquisition Control Status 21 IDT 25 ADC IOB delay 32 impact 9 ADC Sample Control 22 introduction 5 ADC serial interface 31 IPMI 7 9 clock distribution AD9510 SPI interface 27 J32 7 9 clock distribution multiplexer control 25 J604 9 Clock Multiplier IC SI5326 SPI interface 29 J75 40 41 control 18 JTAG 9 13 14 DAC control 30 AVR 9 DAC Data 30 over PCle 19 firmware revision 18 register 19 Harlink Connector Input Output Control 24 jumper 9 Memory Sample Start Address 36 JYEBAO 13 MLVDS Input Output Control 23 LI 10 module Id 18 L2 10 ringbuffer pretrigger delay 37 LED 10 Sample Length 37 20A 10 serial number 18 Page 44 of 45 Struck Documentation trigger setup 33 34 trigger threshold 34 User Control Status 20 XILINX JTAG 19 XILINX Virtex5 Error Detection 19 registers Virtex 5 System Monitor 32 RTM 38 RTM connector schematics 43 RTM connectors 40 RTM management 38 SAMTEC 13 SFP 6 13 S1I5326 29 SIS8300 5 SMA 12 SYNDROME 19 TDI 19 TDO 19 temperature 32 TMS 19 SIS8300 uTCA for Physics Di
10. ICMG MTCA 4 specification in a way that they must have an on board HRC EEProm on address 0x50 and a NXP PCF8574 compatible port expander on address 0x7C Required port expander connection map for normal operation PO Hot Swap Switch low active P6 RowerEnable low active The EEprom shall contain any relevant device information FRU records about the RTM refer to PICMG AMC 0 Additionally the EEprom shall contain the new record types defined in PICMG MTCA 4 In order to be able to decide whether a connected RTM is compatible to the SIS8300 the RTM record shall contain one of the Zone 3 Identifier records listed in the table below Supported Zone 3 Identifier Records Interface Identifier OEM IANA PEN Private Zone 3 OEM record Descripton enterprise number compatibility Page 38 of 45 Seale innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 9 Appendix 9 1 Power Consumption The currents drawn by the SIS8300 are listed in the table below 100 mA These currents are typical values during normal operation They can vary depending on the loaded firmware design 9 2 Ordering options The available part numbers are listed in the table below Struck part number FPGA 04075 SIS8300 V2 with XC5VLXS0T 3FFG1136C 4x GBit To be defined XCS5SVLX110T 1 3FFG1136C 5 x 1 GBit Note The V1 and V2 preseries cards are stuffed with the fastest available speed grade 3 A l
11. OO NG gt Ce A E 11 AddressBit3 IS 10 fAddressBit2 le JD 9 Address Bit 8 Address BitO S o D Werite Data Bit6 Read DataBit6 Write Data Bit 1 Read Data Bit 1 0 Write Data Bit 0 LSB Read Data Bit 0 LSB The power up default value is Ox20000000 Page 27 of 45 Struck Documentation SIS8300 uTCA for Physics Digitizer Seale Innovative systeme Command Bit 31 30 Explanation Cmd Bit 1 Cmd Bit 0 Command O O No Function 0 I RAW CMD l Function CMD Generates a pulse at the Function Input pin of the AD9510 which is synchronous to the selected clock The clock selection is done via Bit 28 Function Syn CLK The actual function depends on the programming of the selected AD9510 Select Function synchronisation CLK Bit 28 Explanation Clock Source 0 PCI Clock FPGA CLK 69 Note 1 enable READ by writing 0x90 to addr 0x0 2 and set Read Cycle Bit Note Please refer to the SIS8300_AD9510_SPI_ Setup routine as illustration and to the AD9510 documentation for details Page 28 of 45 Seale innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 15 Clock Multiplier IC SI5326 SPI interface register define SIS8300_CLOCK_MULTIPLIER_SPI_REG x42 rd wr Clock Multiplier IC S15326 SPI interface register Several parameters of the Clock Multiplier SI5326 chip can be configured with the SPI serial Peripheral Interface Please refer to the docu
12. S853S057 clock multiplexer chips which are labelled A to E in the clock distribution schematic in section 2 4 The multiplexer control register holds the two select bits for the 5 multiplexer chips as shown in the table below The assignment of the inputs to the resources e clock inputs is listed in subsection 7 13 1 7 ma 2 no 7 000000C0 5 00000030 i i 00000003 Page 25 of 45 Saa innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 13 1 Clock Multiplexer input signal assignments 7 13 1 1 Multiplexer A Input Signals U222 Sel0 and Sell MUX1A_SEL Multiplexer A select lines Clock source Description D fO RTMCLK 0 Clock 2 from yRTM card 0 1 TCLKB_O Clock 2 Telecom Clock B from AMC Connector Backplane 1 fO TCLKAO Clock 1 Telecom Clock A from AMC Connector Backplane 7 13 1 2 Multiplexer B Input Signals U223 SelO and Sell MUX1B_SEL Multiplexer B select lines O O0 RTMCLK 1 Clock 2frompRTMcard _ __ S O i TCLKB_1 Clock 2 Telecom Clock B from AMC Connector Backplane 1 O TCLKA1 Clock 1 Telecom Clock A from AMC Connector Backplane 7 13 1 3 Multiplexer C Input Signals U240 Sel0 and Sell MUXAB_SEL Multiplexer C select lines 0 In EXT_CLKBO Clock from Harlink Connector CI1 4 IN frontpanel 0 II EXT_CLKAO Clock from SMA Connector CLK IN frontpanel 1 fO MUXA_CLKI Multiplexer A Output S
13. Seabee Innovative systeme SIS Documentation SIS8300 uTCA 16 bit Digitizer S1S8300 uTCA FOR PHYSICS Digitizer User Manual SIS GmbH Harksheider Str 102A 22399 Hamburg Germany Phone 49 0 40 60 87 305 0 Fax 49 0 40 60 87 305 20 email info struck de http www struck de Version SIS8300 M 0201 001 V200 doc as of 28 06 11 Page 1 of 45 Seale Innovative systeme SIS Documentation SIS8300 uTCA for Physics Digitizer Revision Table Modification Based on AG notes Clock Distribution Vendor Id PCI Id Register inlays Add registers 0 06 18 09 10 Front panel description RTM connectors RTM connectors 2 00 28 06 11 Changes with new PCB version V2 changed DAC interface add FPGA CRC check register RTM management chapter Page 2 of 45 SIS Documentation SIS8300 kuch Uo SN Sal ggf Innovative systeme uTCA 16 bit Digitizer Table of contents Table Of content 3 rive CHON E 5 1 1 Related GOCUMECI S Wc 0 isssssincsssoneacassasdndsensadavsnnananenensabonsehasdassnavaindeubandecawsnatecoahsndabannneasenehoabassnnasseandens 5 IER 6 2 1 Functionality 2 0 cece ceccccseeecceneeeeeeeeeeeeeeeeeeeeeneee ences eeeeeGeeeeseeeeGGEE EGEE GEEE OEES EES OSE GAE EEE OAE SESE SESE EERE 6 Ge NNO EE EE 6 ee EEN 7 pe mms e aa Eege EE 8 dE EE 9 3 1 EE 9 De SOUR WAI CHAOS FRC i aa E 9 BOP TN RE EE 9 E HR 10 4 1 AMC CED satin eect E E cation arate eaten see ent ae eae e
14. adiwrte 31 7 19 ADC Input Tap delay registers OxA0 cecccssceceeeeceneeeseeeeeseeeeeeneeeeeeeeseeeeseseeseeeeseeeesenseeaages 32 7 20 Virtex 5 System Monitor reogterg Sy 7 21 Trigger s tup EE 33 7 22 Trigger hreshold EE EE 34 T221 rigger RTE 34 laza FPR Wi er Mreno ea e d A E A ENRE AAAS ETEEN S AEN AEAEE E 35 7 23 Memory Sample Start Address Actual Sample Address regigterg 36 1 24 Sample Re 37 7 25 Ringbuffer Pretrigger Delay 1s E E 37 SEENEN 38 TPM TVG ee 39 9 1 EEN 39 RS ENEE 39 o gt REM Zome 3 connectors Sanda 6 sessancrsasasncaisanscncndapsempananneassdansaesbagdeacsbaananctionsatncedaatamoasanetauasactows 40 9 3 1 d EE EE 40 e EEN 41 Page 3 of 45 SIS Documentation SIS8300 del innovative uTCA for Physics qene Digitizer 9 3 3 Note on AC DC input stage gelecton OA RTM connector schematics ee 10 te Page 4 of 45 SIS Documentation SIS8300 BIER innovative uTCA 16 bit Digitizer systeme 1 Introduction The SIS8300 is a ten 10 channel 125 MS s digitizer with 16 bit resolution according to the UTCA for Physics draft standard SIS8300 with SFPs installed As we are aware that no manual is perfect we appreciate your feedback and will incorporate proposed changes and corrections as quickly as possible The most recent version of this manual can be obtained by email from info struck de the revision dates are online under http www struck de manuals html Note 1 It is PICMG s policy t
15. al uSshoWD Wane threshold value default after Reset 0x0 The value of the Sum trapezoidal value depends on the peaking time P Therefore the selection of the value of the Trapezoidal threshold depends on P also Trapezoidal value calculation Trapezoidal value SUM2 SUMI Where x P SUMI Si EK x P sumG SUM2 Sj j Xt sumG The FIR filter logic generates the Trapezoidal by subtraction of the two running sums This implies that the internal value of the trapezoid is on average 0 A trigger output pulse is generated e GT is set GT the Trigger Out Pulse will be issued if the actual trapezoidal value goes above the programmable trapezoidal threshold value e GT is cleared LT the Trigger Out Pulse will be issued if the actual trapezoidal value goes below the negated programmable trapezoidal threshold value Page 35 of 45 Seale Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 23 Memory Sample Start Address Actual Sample Address registers define SIS8300_SAMPLE START_ADDRESS_CH1_REG 0x120 7 rd wr D32 7 define SIS8300_SAMPLE START ADDRESS CHILD REG 0x129 rd wr D32 The write function to these registers defines the memory start address The value is given in 256 bit blocks ADC chl Memory Sample Start Address Actual Address register a reserved Memory Sample Start Address 256 bit blocks Function 16 bit word address x 16 default after Reset
16. d Layout A print of the silk screen of the component side is shown below Beso ven Si 2 3 S4 5 S6 S7 S8 ma a pum ee mg mig mg img Ce mis az Ss Pe ie d B TO ne eki LIP rea EL amy ad erg e Zo sch erg Agal ae Gi am D E L x Se k ia SE D SE SE ll g ch WW ke J28 B Reg em em em a DOUT em ees em em eeesesene I Je Ier wem wm b u40 U42 a g 355 J57 u60 eeneeeene sate KC KEE seesecces SIS GmbH 03 2011 SIS8300_V2 www struck de TTT titi i sesecseose Ta 46 o 148 A WG 183 8 T s 58 T 63 sessesose We ide aan mmm pm mie weie man pm e ITT eege AAA ECH TEP FEF FEY pE Rant TH seeeneene i Cen TTT amp ae Sc 8 Go SE Eise Kass Rey amp Se SR D TUTE E E Et ei Go Aa SC gt H e ee dunn maf Scam e C ONS e N S op C2305 mmm R CS c Z50N 8 BE Zb vr muma BAUNEN AE E209 ane He a2 ee i MNNM FP 1I CR CHIC E H F g feel S es a a R2230 E s b G TT z n 36 c SE eoneeee ety E VE E i a ee DEET CN Ti SZ emp ett at Sdt CB JE SZ emm z SE K MMMM Ls AST tt ea F mnnn WN ur Summa ZS r e Connector types The used connectors are listed in the table below J377 RTMKeying 00 IT Note The used Key may depend on the hardware configuration of the SIS8300 Page 13 of 45 Struck Documentation SIS8300 innovative
17. e set to 1 The maximum Peaking time 16 clocks The minimun Peaking time 1 clocks Values gt 16 will be set to 16 Value 0 will be set to 1 Page 33 of 45 Seale Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 22 Trigger Threshold registers define SIS8300_TRIGGER_THRESHOLD_CH1_REG 0x110 rd wr D322 define SIS8300_TRIGGER_THRESHOLD_CH10_REG 0x119 f d r D22 7 These read write registers hold the threshold values for the 10 ADC channels 7 22 1 Trigger Threshold Threshold value OFF T value ON default after Reset 0x0 A trigger output pulse is generated on two conditions e GT is set GT in trigger setup register the trigger Out pulse will be issued if the actual sampled ADC value goes above the threshold value ON and OFF A new Trigger Out Pulse will be suppressed until the ADC value goes below the threshold value OFF e GT is cleared LT in trigger setup register the trigger Out pulse will be issued if the actual sampled ADC value goes below the threshold value ON and OFF A new trigger Out pulse will be suppressed until the ADC value goes above the threshold value OFF the trigger Out pulse will be issued if the actual sampled ADC value goes below the threshold value GT greater than LT lower than Page 34 of 45 Seale Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 22 2F IR Trigger Threshold Funclion None Trapezaid
18. e tee ened esate A E 10 Be eru e NEE aces orate E tase act oom oatiee et ee hee E oo ect ee eset 10 4 3 SEIT E 10 EE 1 5 1 Harlink LVDS In JOumuts a eeeaeeeeeeeeeseneeeaeseeseaeeeaeneeseneeeaanes 12 32 SMA TR hn E 12 BOTE ON eo ces cea E E ce gst oddest rea aed hala digesta priate bh ane aa eeeom tame bade 13 et ah Te EE 14 7 1 CEET 14 Ta MWCO OU ME EE 16 pes WEN RRE 17 7 4 Module Id and Firmware Revision regster 18 7 5 Serial Number register ee 18 T0 A UWINX ITAGE SE enn a Saino ota cts Meat olenn Rotem ae dae 19 7 7 XILINX VirtexS Error RE EE 19 7o User COMMON EE EE 20 7 9 ADC Acquisition eege et Al JA40 ADC Nee e EI EE 22 7 11 MLVDS Input Output Control register iter ege eebe 23 7 12 Harlink Connector Input Output Control register ccc cseccccseeeceeeeeeeesecsencceseseeceneeeaeeesansesaanes 24 7 13 Clock Distribution Multiplexer control register 2 0 0 ceccccecceccseecceneeceeeeceenceeseseeeseeceeensenensesseseesaaees 29 7 13 1 Clock Multiplexer input signal assgoenments 26 7 14 Clock Distribution AD9510 Serial Interface SPI interface register 0x41 read write 000 21 7 15 Clock Multiplier IC SI5326 SPI interface regigter cc ceccccseccceeeecceeeeecenceesesecseneeesseesensessanes 29 7 16 DAC Control register EE 30 7 17 DAC Data register 0x46 read write sseesseesssesssessserssersserssersssrssserssersserssersserossrsssersseesseesseess 30 7 18 ADC Serial Interface SPI interface register 0x48 re
19. gitizer Salaa innovative systeme trigger threshold 34 TYCO 13 U 10 U222 26 U223 26 U240 26 U250 26 U251 26 U500 9 user LED 20 Virtex 5 6 Virtex5 Error Detection register 19 watchdog reset 9 XC5VLX110T 1FFG1136C 39 XC5VLXS50T 3FFG1136C 39 Xilinx 6 ZM 5 Zone 3 40 Page 45 of 45
20. ignal 7 13 1 4 Multiplexer D Input Signals U250 Sel0 and Sell MUX2A_SEL Multiplexer D select lines D 0 _ MUXA_CLKO Multiplexer A Output Signal D 1 MUL CLKI Clock Multiplier U242 Output 2 Signal 1 0 EXT_CLKB1 Clock from Harlink Connector C11 4 IN frontpanel Clock from SMA Connector CLK IN frontpanel 7 13 1 5 Multiplexer E Input Signals U251 Sel0 and Sell MUX2B_SEL Multiplexer E select lines Selected Input Net Name Clock source Description 0 l0 MUXB_CLKO Multiplexer B Output Signal 0 1 MUL_CLKO Clock Multiplier U242 Output 1 Signal 1 O EXT_CLKB2 Clock from Harlink Connector CI1 4 IN frontpanel EXT_CLKA2 Clock from SMA Connector CLK IN frontpanel Page 26 of 45 Saa innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 14 Clock Distribution AD9510 Serial Interface SPI interface register 0x41 read write define SIS8300_AD9510_ SPI REG x41 read write D32 The parameters of the Clock Distribution IC AD9510 chips can be configured with the SPI serial Peripheral Interface Bit Write fread Cmd Bit 1 Write Read Logic BUSY Flag Cmd Bit 0 ee Set Function Output Level Status of Set Function Output Level 28 Select Function Status of Select Function synchronisation CLK synchronisation CLK re at hme 23 Read Cycle Bit Jo O 22 RE E a o BE 20 _ Address Bit 12 o o 19 Address Dn II
21. mentation of the SI5326chip for details KS NEE RG ll Ji J Di LOL Status S In Le S153xxX INT_CIB Status O SS Instruction Byte Bit 7 NN 8 Instruction Byte Bit 0 NN Address Data Byte Bit 7 Read Data Bit 7 MSB ee Read Data Bit 0 Address Data Byte Bit 0 Read Data Bit 0 LSB The power up default value is 0x0 Cmd Bit 1 Cmd Bit 0 O 0 Execute SPI Write Read Cmd DJ ResetCmd S d O DecrementCmd Reset Cmd generates an lus reset pulse Decrement Cmd generates an lus Skew Decrement pulse Increment Cmd generates an lus Skew Increment pulse Note INC DEC Time between consecutive pulses must be greater than 16ms Page 29 of 45 Salaa innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 16 DAC Control register 0x45 read write define SIS8300_DAC_CONTROL_REG 0x45 read write D32 read C NEE e a pn LI l C a 1 TestMode Bit le D Test Mode Dun The power up default value is 0x0 OO Data from DAC Data register D Ramp TestMode _ Ao OF ADCIVADC2 gt DACIIDAC2 Note ADC 1 Clock is used as DAC clock 7 17 DAC Data register 0x46 read write define SIS8300 DAC DATA REG 0x46 read write D32 w A E BE E BE e ooo 0 DACI Data0 o The power up default value is 0x0 Page 30 of 45 Salaa innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 18 ADC Serial Interface SPI interface register 0x48 read
22. ne bit with every positive edge of TCK and the status of TDO is transferred to Bit 30 Bit 31 reflects the current value of TDO during a read access 7 7 XILINX Virtex5 Error Detection register define SIS8300_XILINX_ECC_REG 0x03 XILINX Virtex5 configuration memory error detection register SU 300 60 Frame ECC output indicating a valid SYNDROME value a ae O SYNDROME Status bit 1 0 SYNDROME Status bit 0 Page 19 of 45 Salaa innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 8 User Control Status register define SIS8300_USER_CONTROL_STATUS_REG 0x04 The control register is implemented as a selective J K register a specific function is enabled by writing a 1 into the set enable bit the function is disabled by writing a 1 into the Clear disable bit which location is 16 bit higher in the register An undefined toggle status will result from setting both the enable and disable bits for a specific function at the same time The only function at this point in time is user LED on off On read access the same register represents the status register 31 Clear reserved 1569 JN 30 Clearreserved 1469 0 29 Clear reserved 1369 JD 28 Clear reserved 126 o O 27 Clearreserved EC 26 Clear reserved 1069 JN 25 Joar reserved 9 C9 S o O 24 JOeat reserved 8 C9 S O 23 Joar reserved 769 Jl 22 Clear reserved 6 C9 S O O 21 Clear reserved 569 Jl 20 Clear reserved4 C9 o O 19 Clear reserved3 9
23. o prohibit claims of compliance with respect to a specification under development Any such claims must be understood as applying to a draft which is subject to change Note 2 The SIS8300 is developed in co operation with DESY under ZIM grant 2460101MS9 ZIM Zentrales Innovationsprogramm Mittelstand 1 1 Related documents A list of available firmware designs can be retrieved from http www struck de sis8300firm html Page 5 of 45 Struck Documentation SIS8300 eo uTCA for Physics systeme Digitizer 2 Design The central building block of the SIS8300 card is a Xilinx Virtex 5 FPGA It holds the 4 lane PCI Express interface and is in control of all active components 2 1 Functionality The key properties of the SIS8300 card are listed below Double size uTCA for Physics Board 4 Lane PCI Express Interface Dual SFP Card Cage for optional Multi Gigabit Link Xilinx Virtex 5 FPGA DDR2 Memory Interface 4 x GBit default DDR2 memory Atmegal28 IPMI External Clock and Trigger Inputs Frontpanel digital I O 41n 4 out on Harlink Connectors RTM ADC Analog Inputs I2C Bus 10 ADC Channels 125MS s 16 Bit 2 DAC Channels 250MS s 16 Bit Clock distribution with phase shifting 4 M LVDS uTCA Ports 2 uTCA Clocks 2 2 Block Diagram A simplified block diagram of the SIS8300 is shown below Page 6 of 45 Struck Documentation SIS8300 Siatle innovative uTCA for Physics systeme Digitizer 2 3 Platform Managemen
24. ower speed grade 1 version may be desirable for high volume applications when speed considerations are not an issue Page 39 of 45 Saa innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 9 3 RTM Zone 3 connectors J75 and J76 J75 and J76 are 90 pin right angle female connectors providing 30 contact pairs each 60 signal contacts and 30 ground contacts Every contact pair is surrounded by a L shaped male shield blade The shielding contact is designated with the names of the corresponding signal pair signal pin a and b is affiliated with shielding contact ab e g The picture below shows the connector contact layout as seen from the rear side of the board OUT MAOA MD 9 3 1 J75 connector pin assignments The J75 connector routes the differential analog input signals of the ADC channels and ground to the RTM The characters TF in signal names stand for signals to the AC coupled transformer input stages In same fashion PA stands for DC coupled preamplifier input Stage Col gt ef f e cd mei o o oaa ee et 9 GND CHI_TF CHI_TF GND GND GND GND CH8_PA CH8_PA 8 GND CH7_PA CH7_PA GND GND GND GND CH2_TF CH2_TF 6 GND CH5_PA CH5_PA GND GND GND GND CH4_TF CH4_TF Page 40 of 45 Saa innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 9 3 2 J76 connector pin assignments The J76 connecto
25. r is used to route power data and system management pins to the RTM board Col Row 10 GND GND GND GND GND GND GND GND GND o fono oe oeren op GND Lon oe 1 Oe 8 GND GND GND GND CLK2 CLK2 _ GND GND GND 6 GND Dii Dil GND D10 D10 GND D 5 GND D8 D8 GND D Div GND D A GND D D2 GND Di Di GND D DOr 9 3 3 Note on AC DC input stage selection The AC transformer or DC operation amplifier Opamp input path is selected on the SIS8300 card via 0603 solder bridges as illustrated for channels 0 and 1 on the screenshot below The designators for all channels can be found in the table below AC Transtormer Input DC Opamp Input Page 41 of 45 Seale innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer XXX Input for ADC O SW63A___ ADC CH0 O L8W3B ADC_CHO d woia _ ADC CHI ADC_CHI ADC_CH2 2 SWS58B LADC CH2 3 SWS6A LADCCH 5 SW43B ADC_CH8 SSS 9 SWATA LADCCH 9 SW4IB LADCCH S kuch 6 ES Bo Page 42 of 45 Sabre innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 9 4 RTM connector schematics ed S d nll i S H 5 1 X q s i A o 2 o E T 6 KE Sp ERmetZD 10x3P FEM J75G ERmetZD 10x3P FEM ERmetZD 10x3P FEM SY steme SIS8300 uRTM Connector Siesta innovative Wach Y vo
26. s ee ERmetZD 10x3P FEM ERmetZD 10x3P FEM ERmetZD 10x3P FEM Module guide Receptacle Connector for Analog signals to Input Stages Connector for Digital signals and Power geseeeee sseeeeee seseeeee sseeeece SEGEEGEE EE EE EE EE EE EE BZ Z OZ A BZ BZ Be SS De GE Z a 2 a 2 zlzlelalelzlslks sJ lelzielzlelz sl le lees SJzleizisdzlels lf al ff Gd io ir fc fb 6 PS SO i oo EEN SeEESISbE SlslElslsEt aaeeei adeleae alleles Sblsleblbsbislerlaislsbisleglsflerls a el i az EEEE S BSS138 pull ups Rpu min VDD Vil max Tout max Rpu min 3 3V 0 3 V 0 03mA Rpu min 1k for Fast Mode a ae g SEEE este det sheseee J Ashe Ssee Ee SE EE R T Zoe VS A E lt y D S J d i 7 i C y K Y 8 gt g i d d lt d Z S Page 43 of 45 Struck Documentation SIS8300 Neate innovative uTCA for Physics dame Digitizer 10 Index 12 V 39 A 10 33V 39 D105A 10 8 bit 9 D105B 10 A 10 D110A 10 AC 41 D110B 10 AD9268 31 D20B 10 AD9510 27 D20C 10 ADC Sample Logic 17 D20D 10 Address Map 14 D20E 10 AdvancedMC 6 D20F 10 AMC 6 D20G 10 AMC 0 38 D20H 10 Appendix 39 D21D 10 arm 36 LI 10 Atmega 13 L2 10 Atmegal28 9 U 10 Atmel 7 9 user 20 AVR JTAG 9 LEDs Block diagram 6 AMC 10 board layout 13 Front Panel 10 clock SMD 10 input 12 LVDS 12 clock distribution 8 M 33 clock multiplexer input signal assignments 26 MCH 9 CON600 9 connector types 13 memory buffer 16 microcontroller 7 9
27. sdg x sdoo Aejaq steet and 00d ap GC xvEJEP BUD xEJEP GYD ep oU a qewweibod asing 28u 645 0 ed yoorg indu ged 0Ly3 6y49 So0Y 39 OLY se ED OLYO xEJEP OLUYO EJep olya 1491 gt asind 4966u1 OLYG asing 6U XUD Ily sJe u eug SIE at d Page 17 of 45 Seale Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 4 Module Id and Firmware Revision register define SIS8300_IDENTIFIER_VERSION_REG 0x00 This register holds the module identifier SIS8300 and the firmware version and revision 31 16 FFFF0000 Module Identifier 0x8300 fo kel OOOOFFOO EE OOOOOO0OFF Example The initial version of the SIS8300 reads 0x83000101 7 5 Serial Number register define SIS8300_SERIAL_NUMBER_REG 0x01 This register holds the Serial Number of the module FFFF0000 Serial Number 1 65535 OOOOFFFF Page 18 of 45 Seale innovative Struck Documentation SIS8300 uTCA for Physics era Digitizer 7 6 XILINX JTAG register define SIS8300_XILINX_ITAG_REG 0x02 XILINX JTAG register This register is used in the firmware upgrade process over PCIe only A TCK is generated upon a write cycle to this register 20 1 LL Shifted TDO Juge 3 Juge 2 Inge JI Im S S o Im BOX Shifted TOO The read register function operates as a shift register for TDO The content of the read register is shifted to the right by o
28. t The management code of the SIS8300 is implemented in an Atmel Atmegal281 16MU microcontroller and can be upgrade in field over connector J32 see section 3 3 Page 7 of 45 Struck Documentation SIS8300 innovative uTCA for Physics systeme Digitizer 2 4 Clock Distribution The clock distribution scheme of the SIS8300 is illustrated below FPGA S SI LO oO SR __ O FPGA S SI LO E gt l 7 Om lt x ADCLK925 1 CH Cho 0 3 1 2 0 RTM_CLKO Si RTM_CLK1 H O Lo e oe S S en g E RTM_CLK2 x EXTCLKA ip SMA s 8 d x 5 CLK1 a x EXTCLKB J z N HARLINK eg x ZS 2 CLK2 a 2 x Page 8 of 45 Struck Documentation SIS8300 Siatle innovative uTCA for Physics systeme Digitizer 3 Jumper Connector Pin Assignments The following subsections describe the pin assignments of jumpers and connectors 3 1 CON100 JTAG The SIS8300 s on board logic can load its firmware from a serial PROM via the JTAG port on connector CON100 PCI Express or via the MMC Hardware like the XILINX HW USB JTAG in connection with the appropriate software will be required for in field JTAG firmware upgrades CON100 is a 2mm e metric 14 pin header that allows you to reprogram the firmware of the SIS8300 board with a JTAG programmer The pin out is shown in the schematic belo
29. w It is compatible with the cable that comes with the XILINX HW USB II G JTAG platform cable CON100 can be found at the right bottom side of the board D 2 5V CON100 E 9 s CON JTAG TMS 6 CON JTAG TCK 8 CON_JTAG TDO 10 CON JTAG TDI Note 1 The board has to be powered for reprogramming over JTAG Note 2 The FPGA uses 8 bit parallel mode to load the firmware from the serial PROM Make sure to check the Parallel Load box in Impact when specifying the programming properties for the PROM 3 2 J604 Watchdog Reset J604 can be found next to the left upper edge of U500 largest chip on the card With J604 closed the boards watchdog reset is connected to the reset logic J604 should be opened for JTAG firmware programming 3 3 J32 AVR JTAG This 10 pin header is used to connect to the JTAG of the Atmel Atmega128 microcontroller providing the IPMI MCH functionality of the SIS8300 J32 s ch TCK GND O s TDO VTREF O o TMS nSRST bo el nc nTRST bm 9 10 TDI GND O Page 9 of 45 Seale Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 4 LEDs 4 1 AMC LEDs The AMC LEDs are implemented according to the standard 4 2 Front Panel LEDs The SIS8300 in Gigalink stuffing option has 4 green front panel LEDs Function in Gigalink design PCI Express Access User LED PCIe Link up Optical Link 1 up ADC Sampling active Optical Link 2 up
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