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SMT335 User Manual - Sundance Multiprocessor Technology Ltd.

1. E1 ED2 F1 EDS G1 ED10 H1 ED14 E2 RAS 2 ED6 2 ED17 H2 ED22 E3 ED3 F3 ED7 G3 ED11 H3 ED23 4 ED8 G4 ED12 H4 CAS E5 F5 ED9 G5 ED13 H5 ED24 E6 SDBBACK F6 G6 H6 E7 C0S0 F7 G7 H7 E8 C0S7 F8 G8 H8 E9 C0S1 F9 G9 H9 E10 52 F10 G10 H10 E11 C0S3 F11 G11 H11 E12 C4S7 F12 G12 H12 E13 TIMNMI F13 G13 H13 E14 4 11 F14 G14 H14 E15 458 F15 G15 H15 E16 459 F16 G16 H16 E17 RESET F17 G17 H17 E18 F18 GA22 G18 GA18 H18 STAT2 E19 F19 GA21 G19 GA17 H19 GA13 E20 GA25 F20 GA20 G20 GA16 H20 E21 GA24 F21 STAT1 G21 GA15 H21 GA12 E22 GA23 F22 GA19 G22 GA14 H22 Version 3 0 Page 29 of 34 SMT335 User Manual J1 ED18 K1 ED28 L1 ED31 M1 EA2 J2 ED25 K2 ED20 L2 ED21 M2 EA17 J3 ED26 K3 SDRAMWE L3 SDRAMCS 94 ED19 K4 ED29 L4 ARE M4 EA4 J5 ED27 K5 ED30 L5 ARDY M5 EA5 J6 K6 L6 AOE M6 J7 K7 L7 M7 J8 K8 L8 M8 J9 K9 L9 M9 J10 K10 L10 M10 J11 K11 L11 M11 J12 K12 L12 M12 J13 K13 L13 M13 J14 K14 L14 M14 J15 K15 L15 M15 J16 K16 L16 M16 J17 K17 L17 GA9 M17 J18 GA28 K18 GA6 L18 AE M18 J19 11 K19 GAS L19 M19 DE J20 GA10 K20 L20 GA2 M20 5031 421 GA8 K21 STAT3 L21 GA1 M21 GD30 J22 K22 4 L22 22 GD29 Version 3 0 Page 30 of 34 SM
2. Error Bookmark not defined Reprogramming the firmware and boot code Error Bookmark not defined INTOTTUPTS Error Bookmark not defined Communication ports Error Bookmark not defined Data 65 waka aasawa Error Bookmark not defined HP Error Bookmark not defined lp c M Error Bookmark not defined SDB update cette E c ret d DU A aa sau Error Bookmark not defined SDB Clock selection Error Bookmark not defined GIODAT D S 5s qiias nn en en nca te Error Bookmark not defined Note for SMT310 SMT310Q SMT300 SMT300Q Error Bookmark not defined Clock Speed Error Bookmark not defined CED Setting ioiii niseni aoha eiai Error Bookmark not defined LED Registe aneii ai Error Bookmark not defined CONFIG amp Error Bookmark not defined lu Error Bookmark not defined IIOF interru pt eite Debet dei uicta dde Error Bookmark not defined Version 3 0 Page 6 of 34 SMT335 User Manual Gode Composestr Error Bookmark not defined Application Development Error Bookmark not defined Operating Conditions ns
3. SDBA CP3AA CP1 CP2 CLOCKSDBA C60 CLOCK 2 Version 3 0 Page 27 of 34 SMT335 User Manual Virtex Pin Out A1 B1 EDO C1 ED1 D1 ED16 A2 0 10 B2 C2 ED15 D2 AWE A3 SDBD15 B3 SDBBWEN C3 D3 A4 SDBD12 B4 C0S5 C4 D4 5 SDBD9 B5 SDBBUDO C5 COS8 D5 SDBBD2 0511 B6 SDBBUD1 C6 056 D6 SDBBD5 A7 SDBD6 B7 SDBBD13 C7 C0S9 D7 SDBBD8 A8 SDBD3 B8 SDBBD10 C8 08 SDBBD11 A9 54 B9 SDBBD7 9 09 SDBBD14 A10 SDBDO 10 SDBBD4 C10 CLKB D10 SDBBREQ A11 CLK100 SDBBD1 C11 CLKB D11 C4S0 A12 C585 12 559 C12 550 D12 C4S1 A13 C5S6 4510 C13 551 D13 452 14 557 B14 5510 C14 552 014 C4S3 A15 C60NMI B15 C5S11 C15 C5S3 D15 C484 16 C5S8 16 TIMIACK C16 C584 D16 455 17 C60IACK B17 IIOF2 C17 D17 C4S6 A18 B18 TIMNMI C18 D18 GA29 A19 B19 CONFIG C19 D19 A20 B20 C20 D20 Config DO A21 B21 C21 D21 GA26 A22 22 C22 GA27 022 STATO Comm ports are numbered CO to C5 Each has 12 elements i e CnS 0 11 50 STRB CnS1 RDY CnS2 REQ CnS3 ACK CnS 4 11 Data O 7 Version 3 0 Page 28 of 34 SMT335 User Manual
4. 18 boot code formalt 17 register descriptions 7 Boot 11 revision numbers bootstrap program 11 boot code 13 oe boards rere 18 FPGA MVE 13 jd soe 12 Speed sss none 14 speed select See Jumpers clock speed 14 Code Composer 17 pin out 24 Comports 0950 performance 14 Puro USME uei sassa aa 1 config 11 14 Contacting Sundance 6 SDRAM uiii Devi dau I IUE EE 12 email address 6 Serial Ports e 19 EMIF Control Registers 12 serial port 23 after reset i5 1335 7 SU pecan enn Sine uM EIE RUE 5 7 ACCESS 20 Sundance TIM carrier boards 18 protection algorithm 12 16 PRGA dentiam joo We E H configuration 11 VES BEEN layout 25 Jumpers 23
5. 0 41MHz SMT375 1 83MHz Global bus The SMT335 provides one global bus interface See general firmware description The latest global bus interface is double buffered for dma so that it can read ahead the next buffer while the first one is being read by the DSP Similarly a buffer is being written while the previous one is being sent The important thing is to set the global bus operation register before enabling the global bus interrupt on an external interrupt line so that the interrupt generated is the one relevant to the operation read write This has changed for the SMT335 firmware as it used to need the dma event to be forced for a write and that the external interrupt was enabled before the operation register was set This is the only change needed when updating from a version of the SMT335 prior to 3 13 6 Note for SMT310 SMT310Q SMT300 SMT300Q Burst Transfer across a 1KBytes page boundary is only supported from version 3 13 6 of the firmware To transfer over the PCI the global bus is set up to be able to perform burst transfer across the PCI bridge chip A burst transfer is happening whenever the global bus transfer size register is set to transfer more than one word at a time During a burst a word is transferred on every clock cycle The PC memory can be accessed through aperture 0 of the PCI Bridge but a burst transfer must not cross a 1KBytes boundary 256 words This is because the page size of the bridge chip is
6. Clock Speed on page Error Bookmark not defined for further details SDRAM Memory space CE2 is used to access 16MB of SDRAM over the EMI The SDRAM operates at one half of the core clock speed FLASH A 512KB Flash ROM device is connected to the C6000 EMI This device is accessed a byte at a time with word addresses from 0x0140 0000 to 0x015F FFFF using strobe CE1 in 32 bit asynchronous mode Each 32 bit load will give 8 bits of data in bits 7 0 of the result the state of bits 31 8 is undefined Version 3 0 Page 13 of 34 SMT335 User Manual The ROM holds boot code for the C6000 configuration data for the FPGA and optional user defined code A software protection algorithm is in place to prevent programs accidentally altering the ROM s contents Please contact Sundance for further information about re programming this device Error Reference source not found Error Reference source not found Error Reference source not found Error Reference source not found Version control Revision numbers for both the boot code and FPGA firmware are stored in the Flash ROM during programming as zero terminated ASCII strings These revision numbers are located using byte offsets from the base of the Flash ROM 0x01400000 The offsets are held as 4 byte words at the end of the ROM 0x015FFFF8 for the FPGA firmware offset and 0x0147FFFC for the boot code offset The distribution disk contains a program read version 335 out in the direc
7. TMS320C44 Addendum SDB Technical Specification V2 1 or above TMS320C4x User s Guide literature number SPRUOGS describes the C4x 32 bit floating point processor developed for digital signal processing as well as parallel processing applications Covered are its architecture internal register structure instruction set pipeline specifications and operation of its six DMA channels and six communication ports Software and hardware applications are included Application Note Creating New Firmware Version 3 0 Page 34 of 34 SMT335 User Manual Index Application Development 17 L EDS unun a E Fed bkn 16 17 FPGA DONE 16 Architecture Description 10 MCBSP tasu g 19 Bibliography 32 Memory 20 Block Diagram 9 memory space to CE3 12 Board not working motherboards 18 firmware revision 4 EN LL LR 16 Notational Conventions 7 firmware version numbers 13 Operating Conditions 18 LED 1 illuminated 16 Power no 3 3v supply 18 S SV ave edic PR or e P re dt 18 old version SDB 14 power consumption
8. several registers that control the external memory interface EMIF There is one global control register and a separate register for each of the memory spaces CEO to CE3 A full description of these registers can be found in the C60000 Peripherals Reference GuideError Reference source not found Error Reference source not found Error Reference source not found The standard bootstrap will initialise these registers to the following values GC global control ee For half speed SBSRAM x0000377D For full speed SBSRAM default CEO 0x00000040 Indicates SBSRAM CE1 Ox30FF3F03 Defines asynchronous memory timings CE2 0x00000030 Indicates SDRAM CE3 0x00000030 VIRTEX FPGA Note Bits 12 amp 13 of the Global control register are listed as reserved in the current TI documentation With earlier versions of the C6000 silicon these 2 bits controlled the polarity of two clock outputs from the device To maintain code compatibility for all of our version modules we have left our documentation with bits 12 amp 13 set SBSRAM Memory space CEO is used to access 512KB of zero wait state SBSRAM over the C6000 external memory interface EMI SBSRAM is normally set to run at the speed of the C6000 core clock but the GC register can be used to reduce this to one half of the core clock speed The appropriate setting has to be determined in conjunction with the C6000 core speed and the external memory speed refer to
9. 032C0000 define GBSTA volatile unsigned int 0x03340000 define SDBSTAT volatile unsigned int 0x03380000 define STAT volatile unsigned int 0x033C0000 define SDBA volatile unsigned int 0x03400000 define SDBB volatile unsigned int 0x03500000 define SDBA STA volatile unsigned int 0x03480000 define SDBB STA volatile unsigned int 0x03580000 define SDBA INPUTFLAG volatile unsigned int 0x03440000 define SDBB INPUTFLAG volatile unsigned int 0x03540000 define SDBA OUTPUTFLAG volatile unsigned int 0x034C0000 define SDBB OUTPUTFLAG volatile unsigned int 0x035C0000 define GLOBAL BUS volatile unsigned int 0x03A00000 define GLOBAL BUS CTRL volatile unsigned int 0x03800000 define GLOBAL BUS STAR volatile unsigned int 0x03880000 define GLOBAL BUS LENGTH volatile unsigned int 0x03900000 define TCLK volatile unsigned int 0x03C00000 define TIMCONFIG volatile unsigned int 0x03C80000 define LED volatile unsigned int 0x03D00000 define IIOF volatile unsigned int 0x03D80000 define INTCTRL4 volatile unsigned int 0x03E00000 define SDBINTCTRL4 volatile unsigned int 0x03E40000 Version 3 0 Page 23 of 34 SMT335 User Manual define INTCTRL5 volatile unsigned int 0x03E80000 define SDBINTCTRL5 volatile unsigned int 0x03EC0000 define INTCTRL6 volatile unsigned int 0x03F00000 define SDBINTCTRL6 volatile unsigned in
10. 1KBytes In other words burst transfer must always be ended on a page boundary For example you should never burst from the pci address to XXXXX400H Address XXXXX400H would actually be targeting address XXXXXOOOH in the pci address space as the page accessed by this burst was in the address range XXXXX000H To make sure a page crossing does not happen during burst access an address alignment has to be performed The global bus transfer size has to be reduced not to Version 3 0 Page 16 of 34 SMT335 User Manual cross a page For DMA it is advised to align the transfer on 256 words and then set up the DMA to transfer by bursts of 256 words to ensure no page boundary is crossed during burst Version 3 0 Page 17 of 34 SMT335 User Manual Clock Speed You must consider EMIF device speeds when choosing the appropriate C6000 clock speed Under most circumstances the C6201 would be set to 200MHz and have an SBSRAM speed equal to the core speed the C6701 would be set to 166MHz See the description of jumper JP1 on page Error Bookmark not defined C6000 clock SBSRAM SDRAM FPGA 133 133 67 67 166 166 83 83 200 100 100 100 200 200 100 100 LED Setting The SMT335 has 5 LEDs LED 1 always displays the state of the FPGA DONE pin This LED is off when the FPGA is configured 1 and on when it is not configured DONE 0 This LED should go on when the board is fi
11. 600MIPS Address 16 Data 32 Control2 12 Virtex GLOBAL BUS COMM PORTS SDB Userapplications Address Data Control 75pins 4xComms 48pins 2xComms loc ks Ints 33pins C sow PRIMARY Version 3 0 Page 10 of 34 SMT335 User Manual Architecture Description The SMT335 TIM consists of a Texas Instruments TMS320C6201 running at 200MHz while the SMT375 has a TMS320C6701 running at 166MHz Modules are populated with 512KB of synchronous burst SRAM SBSRAM and 16MB of synchronous DRAM SDRAM giving a total memory capacity of 16 5MB A Field Programmable Gate Array FPGA is used to manage global bus accesses and implement six communication ports and two Sundance Digital Buses Version 3 0 Page 11 of 34 SMT335 User Manual TMS320C6201 6701 Bother processors will run with zero wait states from internal SRAM the TMS320C6201 at 200MHz and the TMS320C6701 at 166MHz An on board synthesiser from MicroClock provides the clock used for the C6000 jumpers on the TIM allow you to select clock speeds from 118MHz to 200MHz Unlike similar TIMs based on the 320 4 there is no option to provide an external clock source The TIM configuration feature is fully implemented This provides a single open collector line that can be held low until software configuration has been completed Boot Mode The SMT335 is configured to use the following boot sequence each time it is taken out of reset 1 The pr
12. Error Bookmark not defined cl Ne ea E Error Bookmark not defined EMO Re Error Bookmark not defined General Requirements Error Bookmark not defined Power Consumption Error Bookmark not defined S rial POMS al cie ERE CH Error Bookmark not defined C6201 Memory MNap Error Bookmark not defined Flash ACCESS Em Error Bookmark not defined Virtex Memory Map Error Bookmark not defined Ml Error Bookmark not defined JP1 Clock speed select Error Bookmark not defined JP2 Serial port header Error Bookmark not defined SDB Pin Out Error Bookmark not defined Virtex layout u uuu uuu as ku aie taii aurca idi Error Bookmark not defined Virtex Pin Out Error Bookmark not defined Bibliography EP Error Bookmark not defined NAEK q Error Bookmark not defined Contacting Sundance You can contact Sundance for additional information by sending email to support sundance com Version 3 0 Page 7 of 34 SMT335 User Manua
13. S9 YT INT5 U18 GD11 V18 W18 1 10 Y18 INT6 U19 GD10 V19 INIT W19 Y19 DONE U20 GD9 V20 GD6 W20 PROG Y20 U21 GD8 V21 GD5 W21 GD3 Y21 U22 GD7 V22 GD4 22 GD2 Y22 GD1 Version 3 0 Page 32 of 34 AA AB1 AA2 AB2 M0 V33 SDBAD10 ABS SDBAD15 AA4 C3S9 AB4 SDBAD12 5 SDBAUD1 5 SDBAD9 C3S10 AB6 SDBAD6 7 511 7 SDBAREQ AA8 DIRA AB8 SDBAACK SDBAD7 AB9 SDBAD3 AA10 SDBADA AB10 SDBADO 11 SDBAD1 AB11 CLKA AA12 INT7 12 TIMPAGE1 AA13 C288 AB13 C284 AA14 AB14 H3 15 IIOF1 AB15 C2S5 AA16 TIMRDY1 AB16 C2S9 17 250 17 C2S6 18 251 AB18 C287 AA19 C282 AB19 2510 AA20 253 AB20 2511 AA21 AB21 H1 AA22 GDO AB22 SMT335 User Manual Version 3 0 Page 33 of 34 SMT335 User Manual Bibliography c N TMS320C6201 C6701 Peripherals Reference Guide literature number SPRU190 describes common peripherals available on the TMS320C6201 C6701 digital signal processors This book includes information on the internal data and program memories the external memory interface EMIF the host port multichannel buffered serial ports direct memory access DMA clocking and phase locked loop PLL and the power down modes Application Note Flash Programming TIM 40 MODULE SPECIFICATION Including
14. SUNDANCE SM 335 375 User Manual User Manual QCF42 Version 3 0 5 2 01 Sundance Multiprocessor Technology Ltd 2001 Version 3 0 Page 2 of 34 SMT335 User Manual Revision History Date Comments Engineer Version 100700 1 1 27 07 00 Typing error corrected Comm Port status J V 08 08 00 New Burst mode selection from CP status J V 1 2 Global register display the interrupt status 09 08 00 Output FIFO status displays how many words J V can be sent 14 08 00 Global register and Interrupt control register reordered Need Bootv1 2 J 03 09 00 SDB naming corrected to A and B J V Global Bus modification for DMA use Comm port drawing modified Boot code Version 1 4 FPGA Firmware Version 2 0 top335V2_0_6 dat J V 14 09 00 NMI routing selection added 18 09 00 Global Bus transfer example corrected V 10 10 00 Global Bus wait state and bus sharing feature J V added Comm port status register OCPRDY ICPRDY moved to allow FIFO depth expansion Firmware version 2 5 6 27 10 00 Global Bus wait state increased to 15 Cf J 1 Control register Comm port status register Full reset bit added for crash recovery Firmware version 2 7 6 Version 3 0 09 11 00 07 12 00 11 12 00 24 01 01 13 4 01 30 8 01 11 04 02 _Version 3 0 1 0 1 Wegesoed 1 TS User Manual 3 of 34 SMT335 User Manual Do
15. T335 User Manual N1 EA18 P1 EA19 EA13 T1 EA16 N2 TINO P2 EA10 R2 EA14 T2 BEO N3 EA7 P3 EA11 R3 EA21 T3 TCLKO N4 EA8 EA12 R4 T4 BE1 N5 EA9 P5 EA20 R5 EA15 T5 BE2 N6 P6 R6 T6 N7 P7 R7 T7 N8 P8 R8 T8 N9 P9 R9 T9 N10 P10 R10 T10 N11 P11 R11 T11 N12 P12 R12 T12 N13 P13 R13 T13 N14 P14 R14 T14 N15 P15 R15 T15 N16 P16 R16 T16 N17 P17 R17 T17 N18 GD28 P18 GD24 R18 GD19 T18 GD15 N19 GD27 P19 GD23 R19 GD18 T19 GD14 N20 GD26 P20 GD22 R20 GD17 T20 GD13 N21 GD25 P21 GD21 R21 T21 GD12 N22 P22 GD20 R22 9016 T22 Version 3 0 Page 31 of 34 SMT335 User Manual U1 V1 LED1 W1 Y1 TCLK1 U2 DMACO V2 LED2 W2 Y2 TOUT1 U3 DMAC1 V3 LED3 W3 TOUTO Y3 U4 DMAC2 V4 LED4 W4 Y4 M2 V33 U5 M1 V33 V5 W5 C356 Y5 06 V6 W6 357 Y6 SDBAUDO 07 V7 51 W7 358 Y7 SDBAD8 U8 V8 C382 W8 SDBAWEN Y8 SDBAD5 U9 V9 C3S3 W9 SDBAD14 Y9 SDBAD2 U10 V10 C384 W10 SDBAD13 Y10 U11 CS3S0 V11 C3S5 W11 SDBAD11 Y11 CLKA U12 C1S0 V12 C181 W12 CLK100 Y12 1511 013 V13 C1S2 W13 TIMCE1 Y13 U14 V14 C1S3 W14 157 Y14 TIMRW1 U15 V15 C184 W15 TIMLOCK Y15 TIMSTRB1 U16 V16 155 W16 C188 Y16 INT4 U17 V17 C1S6 W17 C1
16. cumentation added for DMA transfers FPGA I O Slew rate changed to 5 12 Firmware version 2 8 6 SDB interrupt flags modified Global bus tri state signal not latched Global bus flag cleared when transfer direction is changed reply disabled during token exchange Firmware version 2 9 6 SDB Memory mapping updated Firmware version 3 0 6 Manual updated with quality template Timer routing detailed Comm port drawing corrected Reprogramming and version control described Interrupt Bug fixed SDB handling detailed Comm port bug reported Firmware version 3 3 6 General overhaul and clarification Power consumption and reset timing added Value of Bit 12 13 of the global control register explained Global bus additional feature Synchronisation with carrier board on SMT328 and SMT310 External trigger for ADC acquisition for SMT118 Fix for Comm port Burst mode selection between threads in bi directional transfer Firmware version 3 11 6 Version 3 0 15 05 02 30 01 03 Page 4 of 34 SMT335 User Manual Interrupt description Global bus BUSY bit description Interrupt control register 6 address corrected Global bus transfers description for SMT310 family Firmware version 3 11 6 Restructure of the document Double buffered global bus Will require code change if transfer via dma were used SDB synchronisation changed software change required Fi
17. emory SDB Global bus 80000000 Internal Data RAM PF Flash Access Address Resource ED31 ED30 CE1 0 0 Read Flash Write Flash Read Flash Pulse PROG Read Flash Write CCLK Read Flash Write Flash 01400000 015FFFFF Version 3 0 Page 22 of 34 SMT335 User Manual Virtex Memory Map See general firmware description with i 2 18 The memory mapping is as follows define volatile unsigned int 0x03000000 define CP1 volatile unsigned int 0x03080000 define CP2 volatile unsigned int 0x03100000 define CP3 volatile unsigned int 0x03180000 define CP4 volatile unsigned int 0x03200000 define CP5 volatile unsigned int 0x03280000 define STA volatile unsigned int 0x03040000 define CP1 STA volatile unsigned int 0x030C0000 define CP2 STA volatile unsigned int 0x03140000 define STA volatile unsigned int 0x031C0000 define STA volatile unsigned int 0x03240000 define CP5 STA volatile unsigned int 0x
18. epend on the way you sequence bus accesses C6201 can read at 100MHz from external to internal memory the rate for the C6701 is 83MHz If you want to store in external memory then the rate achievable are divided by two as the read and writes share the same bus which means respectively 50MHz and 41MHz The C6000 DMA channels are not efficient when moving data between two external memory areas sharing a common bus the transfer will take place a word at a time and not in more efficient bursts This is why it may not be advisable to use DMA to transfer data directly between external memory and a communication link Performance can be greatly improved by using an intermediate buffer in internal memory SDB The SMT335 provides two Sundance Digital Buses SDBs See general firmware description SDB update You should be aware that revisions of the SDB before V3 0 6 have a significantly different treatment of the status flags and a different address is used to program the SDB flag levels for input and output When upgrading from versions before V3 0 6 you will need to change the code for flag programming and accessing the status bits You should use version V3 3 6 or above because previous versions could generate spurious interrupts on input SDB Clock selection At any time you can change the speed of an SDB clock by altering SDBCLK Version 3 0 Page 15 of 34 SMT335 User Manual Module SDBCLK Clock Speed 0 50MHz SMT335 1 100MHz
19. g output cables from outside the host system Short circuiting any output to ground does not cause the host PC system to lock up or reboot General Requirements The module must be fixed to TIM40 compliant carrier board The SMT335 TIM is in a range of modules that must be supplied with a 3 3v power source In addition to the 5v supply specified in the TIM specification these new generation modules require an additional 3 3v supply to be presented on the two diagonally opposite TIM mounting holes The lack of this 3 3v power supply should not damage the module although it will obviously be inoperable prolonged operation under these circumstances is not recommended This module is not directly compatible with earlier generations of TIM motherboards although the 3 3v supply can be provided from a separate source It is however compatible with the latest generation of Sundance TIM carrier boards such as the SMT320V4 and subsequent versions PCI and SMT328 VME which present the 3 3v via conductive mounting pillars Use of the on SMT327 cPCI motherboards may require a firmware upgrade If LED 1 on the SMT335 remains illuminated once the TIM is plugged and powered up the SMT327 needs the upgrade The latest firmware is supplied with all new boards shipped Please contact Sundance directly if you have an older board and need the upgrade A SMT320V3 motherboard can be used providing a SMT335 TIM is not located in the fir
20. l Notational Conventions SMT335 Throughout this document the term SMT335 will usually be used to refer to both the SMT335 and the SMT375 It should be clear from the context when a distinction is being drawn between the two types of module Register Descriptions The format of registers is described using diagrams of the following form 31 24 23 16 15 8 7 0 OFLAGLEVEL R 00000000 RW 10000000 R 00000000 R 10000000 The digits at the top of the diagram indicate bit positions within the register and the central section names bits or bit fields The bottom row describes what may be done to the field and its value after reset Shaded fields are reserved and should only ever be written with zeroes R Readable by the CPU W Writeable by the CPU RW Readable and writeable by the CPU Binary digits indicate the value of the field after reset Version 3 0 Page 8 of 34 SMT335 User Manual Outline Description The SMT335 is a C6000 based size 1 TIM offering the following features SMT335 TMS320C6201 processor running at 200MHz SMT375 TMS320C6701 processor running at 166MHz Six 20MB s communication ports comm ports 512KB of fast SBSRAM 16MB of SDRAM 512KB Flash ROM for boot code and FPGA programming Global expansion connector High bandwidth data via 2 Sundance Digital Buses SDB D 0 0 D D D UD Version 3 0 Block Diagram Page 9 of 34 SMT335 User Manual SBSRAM 128K x32 512Kx8 C6201 1
21. ocessor copies a bootstrap program from the first 32KB of the flash memory into internal program RAM starting at address O 2 Execution starts at address 0 The standard bootstrap supplied with the SMT335 then performs the following operations 1 All relevant C6000 internal registers are set to default values 2 The FPGA is configured from data held in flash memory and sets up the communication ports the global bus and the Sundance Digital Buses This step must have been completed before data can be sent to the comm ports from external sources such as the host or other TIMs 3 A C4x style boot loader is executed This will continually examine the communication ports until data appears on one of them The bootstrap will then load a program in boot format from that port the loader will not read data arriving on other ports See Application Development on page Error Bookmark not defined for details of the boot loader format 4 Finally control is passed to the loaded program The delay between the release of the board reset and the FPGA configuration is around 280ms for a SMT335 200MHz clock and 330ms for a SMT375 166MHz The worse case is with a board clocked at 118MHz no jumper fitted in which case the FPGA will be configured 480ms after the reset is released A typical time to wait after releasing the board reset is 500ms Version 3 0 Page 12 of 34 SMT335 User Manual EMIF Control Registers The C6000 contains
22. rmware version 3 13 6 It is important that you use the correct version of the firmware you should use firmware version 3 13 6 or later Check your firmware revision number with the program read_version_335 out and ask for a more recent version if necessary E mail support sundance Version 3 0 Page 5 of 34 SMT335 User Manual Table of Contents Revision History oreet e eicere Error Bookmark not defined Contacting Sundancoe Error Bookmark not defined Notational Conventions Error Bookmark not defined SMT3852 24 Sa Qa Saa Error Bookmark not defined Register Descriptions Error Bookmark not defined Outline Description Error Bookmark not defined Block Diagram Error Bookmark not defined Architecture Description Error Bookmark not defined TMS320C6201 6701 Error Bookmark not defined Boot Mode bebat ant Error Bookmark not defined EMIF Control Registers Error Bookmark not defined Error Bookmark not defined SDRAM RP ARRETE RE Error Bookmark defined FLAS ECCE Error Bookmark not defined Version
23. rst powered up and go off when the FPGA has been successfully programmed If the LED does not light at power on check that you have the mounting pillars and screws fitted properly If it stays on the DSP is not booting correctly The remaining LEDs can be controlled with the LED register Writing 1 will illuminate the LED writing O will turn it off See general firmware description CONFIG amp NMI See general firmware description Timer See general firmware description interrupt From version 3 11 6 of the firmware it is possible to generate pulses on the external interrupt lines of the TIM See general firmware description Version 3 0 Page 180f34 SMT335 User Manual This module is fully compatible with the Code Composer debug environment This extends to both the software and JTAG debugging hardware including the use the Sundance SMT6000 Server Loader and its associated librar ies 0x00003779 half speed SBSRAM 0x0000377D full speed SBSRAM recommended header Version 3 0 Page 19 of 34 SMT335 User Manual Operating Conditions Safely The module presents no hazard to the user EMC The module is designed to operate within an enclosed host system that provides adequate EMC shielding Operation within the EU EMC guidelines is only guaranteed when the module is installed within an appropriate host system The module is protected from damage by fast voltage transients introduced alon
24. st slot putting one there prevents the SMT320V3 from coming out of reset Any other type of TIM must be placed in the first slot of this motherboard to ensure correct operation The external ambient temperature must remain between 0 C and 40 C and the relative humidity must not exceed 95 non condensing Power Consumption The power consumption of this TIM is dependent on the operating conditions in terms of core activity and activity The maximum power consumption is 6W Version 3 0 Page 20 of 34 SMT335 User Manual Serial Ports The C6000 contains two multichannel buffered serial ports McBSP The signals involved are connected to a 0 1 pitch DIL pin header JP2 For a full description of signal activity and the serial protocols available please refer to Chapter 11 of Error Reference source not found Signal Pin Pin Signal FSX1 1 2 FSX0 FSR1 3 4 FSRO DX1 5 6 DXO DR1 7 8 DRO CLKX1 9 10 CLKXO CLKR1 11 12 CLKRO CLKS1 13 14 CLKSO GND 15 16 GND Version 3 0 Page 21 of 34 SMT335 User Manual C6201 Memory Map Starting Address RESOURCE 00000000 Internal Program RAM M External Memory Space CEO 00400000 0047FFFF SBSRAM 512KB SBSRAM External Memory Space CE1 01400000 015FFFFF Flash 512KB Flash 01800000 Internal Peripherals E External Memory Space CE2 02000000 02FFFFFF SDRAM 16MB SDRAM External Memory Space CE3 Comm ports 03000000 O3FFFFFF See Virtex m
25. t 0x03F40000 define INTCTRL7 volatile unsigned int 0x03F80000 define SDBINTCTRL7 volatile unsigned int 0x03FC0000 Version 3 0 Page 24 of 34 SMT335 User Manual Jumpers JP1 Clock speed select S2 51 50 C6000 CLK MHz IN IN IN 200 IN IN OUT 182 IN OUT IN 167 IN OUT OUT 154 OUT IN IN 143 OUT IN OUT 133 OUT OUT IN 125 OUT OUT OUT 118 50 S1 and S2 refer to the following link positions on JP1 S2 S1 SO JP2 Serial port header Refer to the 320 6201 Peripheral Reference Guide Error Reference source not found for a description of the signals and their usage 2 4 6 8 10 12 14 16 FSX0 FSRO DRO CLKXO CLKRO CLKSO GND FSX1 FSR1 DX1 DR1 CLKX1 CLKR1 CLKS1 GND 1 3 5 7 9 11 13 15 Version 3 0 SDB Pin Out Page 25 of 34 SMT335 User Manual Pin Signal Signal Pin 1 CLK GND 2 3 DO GND 4 5 D1 GND 6 7 D2 GND 8 9 D3 GND 10 11 D4 GND 12 13 D5 GND 14 15 D6 GND 16 17 D7 GND 18 19 D8 GND 20 21 D9 GND 22 23 D10 GND 24 25 D11 GND 26 27 D12 GND 28 29 D13 GND 30 31 D14 GND 32 33 D15 GND 34 35 UDO DIR 36 37 WEN REQ 38 39 UD1 ACK 40 Version 3 0 Page 26 of 34 SMT335 User Manual Virtex layout CLOCKSDBB C60 CIOCK 2 SDBB 4 CP5 VIRTEX 300 FG456
26. tory Reprogramming version control You can load and run this program from code composer to display both the FPGA and boot code version numbers Reprogramming the firmware and boot code The Reprogramming flash directory of the distribution disk contains a utility that will run under code composer and program the flash ROM The utility is called pflashx z out where x y 21 the FPGA version number You load the utility with the code composer Load Program option from the File menu Once the program has loaded you should select Run from the Debug menu The reprogramming process takes a minute or so and should display Flash programming complete when it has finished After the program has run you should Halt the processor from the Debug menu and select Run Free To confirm that the programming has been successful you should use the Sundance Server to reset the board and execute one of the supplied test programs A detailed description of the reprogramming process is available as an Application Note Error Reference source not found which will also help you to develop your own core in the FPGA Version 3 0 Page 14 of 34 SMT335 User Manual Interrupts See general firmware description Communication ports The SMT335 provides six comm ports See general firmware description Data rates When using the communication links of a C6000 you must remember that the links share a single bus so the performance you get will d

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