15-W Stereo Class-D Audio Power Amplifier
Contents
1. INSTRUMENTS SLOS578 MAY 2008 www ti com 0 Voc 24V Voc 24 V Votripple 0 2 Vpp 10 Voripple 0 2 Vpp RL 8 Q SE RL 8 Q SE m Gain 20 dB Q 20 Gain 20 dB I 2 30 w cc cc 5 s M 8 8 T T 50 E m 60 o Q 5 m O np 70 80 90 100 20 100 1k 10k 20k 20 100 1k 10k 20k f Frequency Hz f Frequency Hz G026 G027 Figure 29 PSRR Without AVCC Filter Figure 30 PSRR With AVCC Filter vec A R8 L2 C17 33 uF 470 uF SHUTDOWN C7 0 1uF 220 O 3 ril 5 gt O MUTE o C3 1 PVCCLI pvssL1 4 4 1 0 ue 2 SDZ PVSSL2 234 G q atte Ops 2 e s 2 2 LIN AVCC1 a C15 0 22 uF lt FIRIN TPAS124D2 AVCC2 ag g BYP GAINO 7 g GND1 GAIN1 6 C12 0 22 pF C4 70 GND2 lt BSR 45 E o 1 0 uF 7 PVCCR1 Z OUTR 47 a VCLAMP Li PVSSR1 ae 12 pvccr2 E PVSSR2 KEB u 4 g mo ie JA aur Je gt aiz C1 j 0 1 wr CNN C10 O Oka I 2 ADE o i as 7 2 gt L fu Le i o o Ni Ni z z hs o o S S N h hd T Figure 31 Application Schematic with 220 Q 220 uF AVCC Filter BSN and BSP Capacitors The2. INSTRUMENTS SLOS578 MAY 2008 www ti com TYPICAL CHARACTERISTICS All tests are made at frequency 1 kHz unless otherwise noted TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY 10 10 Voc 12V Vcc 18V RL 4 SE RL 6 Q SE 8 Gain 20 dB 8 Gain 20 dB 1 1 5 Po 25W 5 2 2 12 wn Po 1W N 01 o 01 o o E E O Gg A g o o 0 01 Po 0 5W 0 01 z a a Po 0 5W T T F F 0 001 0 001 20 100 1k 10k 20k 20 100 1k 10k 20k f Frequency Hz f Frequency Hz G001 G002 Figure 1 Figure 2 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY 10 10 Voc 18 V Vec 24V RL 8 Q SE R 8 Q SE 9 Gain 20 dB 9 Gain 20 dB S 1 1 5 5 Po 5W Po 25W 9 Po 25W a a 2 04 g 01 x o o E E T T g g 00 N 0 01 z Po 1W z Po 1W Q Q T T F F 0 001 0 001 20 100 1k 10k 20k 20 100 1k 10k 20k f Frequency Hz f Frequency Hz G003 G004 Figure 3 Figure 4 6 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3124D2 Id TEXAS INSTRUMENTS www ti com TPA3124D2 SLOS578 MAY 2008 TYPICAL CHARACTERISTICS continued All tests are made at freguency 1 kHz unless otherwise noted TOTAL HARMONIC DISTORTION NOISE
3. TERMINAL NAME a VO P DESCRIPTION SD 2 wa signal for IC low disabled high operational TTL logic levels with compliance to RIN 6 I Audio input for right channel LIN 5 I Audio input for left channel GAINO 18 l Gain select least significant bit TTL logic levels with compliance to AVCC GAIN1 17 Gain select most significant bit TTL logic levels with compliance to AVCC MUTE 4 Mute signal for guick disable enable of outputs high outputs switch at 50 duty cycle low outputs enabled TTL logic levels with compliance to AVCC BSL 21 VO Bootstrap I O for left channel PVCCL 1 3 P Power supply for left channel H bridge not internally connected to PVCCR or AVCC LOUT 22 o Class D H bridge positive output for left channel PGNDL 23 24 P Power ground for left channel H bridge VCLAMP 11 P Internally generated voltage supply for bootstrap capacitors BSR 16 VO Bootstrap I O for right channel ROUT 15 o Class D H bridge negative output for right channel PGNDR 13 14 P Power ground for right channel H bridge PVCCR 10 12 P Power supply for right channel H bridge not connected to PVCCL or AVCC AGND 9 P Analog ground for digital analog cells in core AGND 8 P Analog ground for analog cells in core BYPASS 7 o eat dan ee inputs Nominally equal to AVCC 8 Also controls start up time via AVCC 19 20 P High voltage analog power supply Not internally connected to PVCCR or PVCCL Thermal pad Die pad
4. TPA3124D2 peg 0 22 uF Left Channel jl 33 uH 470 uF Right Channel if 1uF 0 22 uF AN 9 9 1 uF 0 22 uF ME L BYPASS 33 uH j nae 470 pF L 0 22 uF 10 V to 26V 10 V to 26V be Shutdown Control gt Mute Control gt 4 Step Gain Control S0267 02 Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet DLP is a registered trademark of Texas Instruments All other trademarks are the property of their respective owners PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright 2008 Texas Instruments Incorporated TPA3124D2 SLOS578 MAY 2008 Ig TEXAS INSTRUMENTS www ti com A These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam hy aA during storage or handling to prevent electrostatic damage to the MOS gates PWP TSSOP PACKAGE TOP VIEW PVCCL PGNDL SD PGNDL PVCCL LOUT MUTE BSL LIN AVCC RIN AVCC BYPASS GAINO AGND GAIN1 AGND BSR PVCCR ROUT VCLAMP PGNDR PVCCR PGNDR Table 1 TERMINAL FUNCTIONS
5. vec o 470 pF dk 470 uF M 110 pF non LOUT E 470 uF 1 0 pF P i z Bvect PGNDL 244 0 22 yF eft In SD PGNDL J PvcoL LOUTH mt 4 MUTE BSLZ O22 uF Jee LOUT a LIN TPA3124D2 V 20 DE OD A 8 RIN avec 18 BYPASS GAINoH TL ROUT B AGND GAINI HT 0 22 pF a Right In eHacnn ssri map me 77th PveeR ROUTHI me VCLAMP PGNDR PVCCR E PGNDR T022 uF 25 Shutdown 33 pH Contro M A ROUT Mute 470 uF Control 0 1 uF 10 pF S0268 02 Figure 32 Schematic for Single Ended SE Configuration 8 0 Speaker vec ak I 22 pH 470 F T470 uF 1 0 WF m OUT ll 1 0 pF 1 WI 2 Pvect PGNDL Lost 0 68 pF In 2 SD PGNDL 3 pveci LOUT 4 MUTE BsL 21 0 22 uF AN Agi aga AVEC 29 1 vec RIN AVCC n BYPASS GAINO 8 17 AGND GAIN1 0 22 pF 16 In 2 a AGND amp BSR at Gone To pF lt PVCCR ROUT Du T VCLAMP PGNDR PVCCR PGNDR 10 68 pF Shutdown 4 22 pH Control MA OUT Mute Control 1 0 pF 1 0 pF 0 1 uF 10 uF S0294 02 Figure 33 Schematic for Bridge Tied Load BTL Configuration 8 0 Speaker Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Link s 7PA3124D2 TPA3124D2 13 TEXAS INSTRUMENTS SLOS578
6. 1 kHz unless otherwise noted CROSSTALK vs FREQUENCY 20 Vce 18V Vo 1 Vrms 30 o RL 80 SE Po 0 125 W 40 Gain 20 dB 50 60 Right to Left 70 80 Left to Right 90 100 20 100 1k 10k 20k f Frequency Hz G009 Figure 9 GAIN PHASE vs FREGUENCY 40 600 Voc 24 V RL 4Q SE gt Gain 20 dB 200 Liit 22 WH 30 Cri 0 68 uF 400 Cac 1000 uF 25 300 Gain 4 20 200 8 a Phase 15 100 10 0 5 100 0 200 20 100 1k 10k 100k f Frequency Hz Figure 11 Submit Documentation Feedback G011 Crosstalk dB Gain dB CROSSTALK vs FREGUENCY 20 Voc 24V Vo 1 Vrms 30 o R 8 Q SE Po 0 125 W 40 Gain 20 dB 50 60 Right to Left 70 80 Left to Right 90 100 20 100 1k 10k 20k f Frequency Hz G010 Figure 10 GAIN PHASE vs FREQUENCY 40 600 Voc 24V Ri 8 Q SE 35 Gain 20 dB gt 99 Lg 33 WH 30 Cit 0 22 uF 400 Cac 470 uF 25 300 Gain i 20 200 8 G a 15 Phase 100 10 0 5 100 0 200 20 100 1k
7. MAY 2008 www ti com BASIC MEASUREMENT SYSTEM This section focuses on methods that use the basic equipment listed below e Audio analyzer or spectrum analyzer e Digital multi meter DMM e Oscilloscope e Twisted pair wires e Signal generator e Power resistor s e Linear regulated power supply e Filter components e EVM or other complete audio circuit Figure 34 shows the block diagrams of basic measurement systems for class AB and class D amplifiers A sine wave is normally used as the input signal because it consists of the fundamental frequency only no other harmonics are present An analyzer is then connected to the audio power amplifier APA output to measure the voltage output The analyzer must be capable of measuring the entire audio bandwidth A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins A System Two audio measurement system AP II by Audio Precision includes the signal generator and analyzer in one package The generator output and amplifier input must be ac coupled However the EVMs already have the ac coupling capacitors Cy so no additional coupling is required The generator output impedance should be low to avoid attenuating the test signal and is important because the input resistance of APAs is not high Conversely the analyzer input impedance should be high The output resistance Royt of the APA is normally in the hundreds of millioh
8. Interface interface ti com Medical www ti com medical Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Telephony www ti com telephony RF IF and ZigBee Solutions www ti com Iprf Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2008 Texas Instruments Incorporated
9. PINS DIM 4073225 H 12 05 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusions Mold flash and protrusion shall not exceed 0 15 per side D This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMA002 for information regarding recommended board layout This document is available at www ti com lt http www ti com gt E Falls within JEDEC MO 153 PowerPAD is a trademark of Texas Instruments v TEXAS INSTRUMENTS www ti com WP Texas THERMAL PAD MECHANICAL DATA INSTRUMENTS P R PDSO G24 www ti com P W THERMAL INFORMATION This PowerPAD package incorporates an exposed thermal pad that is designed to be attached to a printed circuit board PCB The thermal pad must be soldered directly to the PCB After soldering the PCB can be used as a heatsink In addition through the use of thermal vias the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device or alternatively can be attached to a special heatsink structure designed into the PCB This design optimizes the heat transfer from the integrated circuit IC For additional information on the PowerPAD package and how to take advantage of its
10. TOTAL HARMONIC DISTORTION NOISE vs vs OUTPUT POWER OUTPUT POWER 10 10 v R 4Q SE RL 629 SE Gain 20 dB Gain 20 dB D 2 2 1 F 1 lt lt 2 D D 2 2 A D o a 2 01 Voc 12 V 2e 014 o o G Gg T g g R 0 01 001 z z a a T T F F 0 001 0 001 0 01 0 1 1 10 40 0 01 0 1 1 10 40 Po Output Power W Po Output Power W G005 G006 Figure 5 Figure 6 TOTAL HARMONIC DISTORTION NOISE CROSSTALK vs vs OUTPUT POWER FREQUENCY 10 20 RL 8Q SE Voc 12V Gain 20 dB 30 Vo 1 Vrms RL 429 SE 3 Po 0 25 W 1 40 Gain 20 dB lt 2 5 m 50 2 T a ME 0 1 60 Right to Left D E 2 f 70 E Left to Right 001 80 I lt Q 90 T H 0 001 100 0 01 0 1 1 10 40 20 100 1k 10k 20k Po Output Power W Figure 7 Copyright 2008 Texas Instruments Incorporated G007 Submit Documentation Feedback Product Folder Link s TPA3124D2 f Frequency Hz G008 Figure 8 TPA3124D2 SLOS578 MAY 2008 Crosstalk dB Gain dB Ih TEXAS INSTRUMENTS www ti com TYPICAL CHARACTERISTICS continued All tests are made at frequency
11. balanced inputs for the system to be fully balanced thereby cancelling out any common mode noise in the circuit and providing the most accurate measurement The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs e Use a balanced source to supply the input signal e Use an analyzer with balanced inputs e Use twisted pair wire for all connections e Use shielding when the system environment is noisy e Ensure that the cables from the power supply to the APA and from the APA to the load can handle the large currents see Table 5 Table 5 shows the recommended wire size for the power supply and load cables of the APA system The real concern is the dc or ac power loss that occurs as the current flows through the cable These recommendations are based on 12 inch 30 5 cm long wire with a 20 kHz sine wave signal at 25 C Table 5 Recommended Minimum Wire Size for Power Cables DC POWER LOSS AC POWER LOSS Pout W R Q AWG Size mW mW 10 4 18 22 16 40 18 42 2 4 18 22 3 2 8 3 7 8 5 1 8 22 28 2 8 2 1 8 1 lt 0 75 8 22 28 1 5 6 1 1 6 6 2 Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Link s TPA3124D2 kid Texas PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 7 Jun 2008 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS A Reel Diameter Dimensio
12. kHz unless otherwise noted SUPPLY CURRENT SUPPLY CURRENT vs vs OUTPUT POWER OUTPUT POWER RL 4 Q SE R 8 Q SE Gain 20 dB Gain 20 dB lt lt g g 5 5 o o gt gt Q Q Q Q gt gt n n gt 0 3 6 9 12 15 0 5 10 15 20 25 Po Output Power W Po Output Power W G017 G018 Figure 17 A Dashed line represents thermally limited region Figure 18 POWER SUPPLY REJECTION RATIO POWER SUPPLY REJECTION RATIO vs vs FREGUENCY FREQUENCY 0 Voc 24 V Voc 24 V 10 Voripple 0 2 Vpp Votripple 0 2 Vpp RL 4 Q SE Ri 8 Q SE Q 20 Gain 20 dB m Gain 20 dB 30 B M 5 8 8 T 50 T a a 60 a a a gt gt a 80 a 90 100 20 100 1k 10k 20k 20 100 1k 10k 20k f Frequency Hz f Frequency Hz G019 G025 Figure 19 Figure 20 10 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3124D2 Id TEXAS INSTRUMENTS www ti com 10 0 1 0 01 THD N Total Harmonic Distortion Noise TPA3124D2 SLOS578 MAY 2008 TYPICAL CHARACTERISTICS continued All tests are made at freguency 1 kHz unless ot
13. p wia ani a yn bg soldered down on all applications to secure the 2 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3124D2 IB TEXAS TPA3124D2 INSTRUMENTS www ti com SLOS578 MAY 2008 ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless otherwise noted VALUE UNIT Voc Supply voltage AVCC PVCC 0 3 to 30 V V Logic input voltage SD MUTE GAINO GAIN1 0 3 to Voc 0 3 V Vin Analog input voltage RIN LIN 0 3 to 7 V Continuous total power dissipation See Dissipation Rating Table Ta Operating free air temperature range 40 to 85 C Ty Operating junction temperature range 40 to 150 C Tstg Storage temperature range 65 to 150 C h m SE Output Configuration 3 2 RL Load resistance minimum value Q BTL Output Configuration 6 4 Human body model all pins 2 kV ESD Electrostatic Discharge So model all 500 V 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability DISSIPATION RATINGS PACKAGE 2 Ta lt 25 C DERATING FACTOR Ta 70 C Ta 85 C 24 p
14. 10k 100k f Frequency Hz G012 Figure 12 Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3124D2 Id TEXAS INSTRUMENTS www ti com TPA3124D2 SLOS578 MAY 2008 TYPICAL CHARACTERISTICS continued All tests are made at frequency 1 kHz unless otherwise noted OUTPUT POWER OUTPUT POWER vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE Ri 4 Q SE Ri 8 Q SE Gain 20 dB Gain 20 dB THD N 10 a a 5 5 gt gt o o l o o a a 10 11 12 13 14 15 10 12 14 16 18 20 22 24 26 Voc Supply Voltage V Voc Supply Voltage V G013 G014 A Dashed line represents thermally limited Figure 14 region Figure 13 EFFICIENCY EFFICIENCY vs vs OUTPUT POWER OUTPUT POWER 100 100 Vce 18V 90 go e 80 80 Vce 24V lt 70 70 L 60 a 60 z 4 c 50 2 50 D g 40 40 30 30 20 20 10 10 Ri 8 Q SE Gain 20 dB 0 0 0 1 2 3 4 5 6 7 0 2 4 6 8 10 12 Po Output Power W Po Output Power W G015 G016 Figure 15 Figure 16 Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link s 7PA3124D2 TPA3124D2 13 TEXAS INSTRUMENTS SLOS578 MAY 2008 www ti com TYPICAL CHARACTERISTICS continued All tests are made at freguency 1
15. AX UNIT Class D output offset voltage Vos measured differentially in BTL Vi 0 V Ay 36 dB 7 5 50 mV mode as shown in Figure 36 V BYPASS Bypass output voltage No load AVCC 8 V lcc a Quiescent supply current SD 2 V MUTE 0 V no load 16 30 mA Icco Quiescent supply current in MUTE 0 8 V no load 16 mA mute mode lcc a Quiescent supply current in _ sh tdown mode SD 0 8 V no load 0 39 1 mA rDS on Drain source on state 210 450 mo resistance GAINO 0 8 V 18 20 22 GAIN1 0 8 V GAINO 2 V 24 26 28 G Gain dB GAINO 0 8 V 30 32 34 GAIN 2 V GAINO 2 V 34 36 38 Mute attenuation Vi 1 Vrms 80 dB AC CHARACTERISTICS Ta 25 C Voc 24 V R 80 unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voc 24 Vypple 200 mVpp 100 Hz 48 ksvr Supply ripple rejection in dB pply ripp J Gain 20 dB 1 kHz 52 P Output power at 1 THD N Voc 24 V f 1 kHz 8 W 2 Output power at 10 THD N Vcc 24 V f 1 kHz 10 THD N Total harmonic distortion f 1kHz Po 5W 0 04 noise V Output integrated noise floor 20 M2 to 22 E ooo Men uV n p 9 Gain 20 dB 78 dBV Crosstalk Po 1 W f 1 kHz gain 20 dB 70 dB Max output at THD N lt 1 f 1 kHz SNR Signal to noise ratio gain 20 dB 92 dB Thermal trip point 150 C Thermal hysteresis 30 C fosc Oscillator frequency 250 300 350 kHz At mute Mute delay Time from mute input switches high until 30 usec outputs muted At unmute Unmute delay Ti
16. D2 is a high performance CMOS audio amplifier that reguires adeguate power supply decoupling to ensure that the output total harmonic distortion THD is as low as possible Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads For higher frequency transients spikes or digital hash on the line a good low equivalent series resistance ESR ceramic capacitor typically 0 1 uF to 1 uF placed as close as possible to the device Vcc lead works best For filtering lower frequency noise signals a larger aluminum electrolytic capacitor of 470 uF or greater placed near the audio power amplifier is recommended The 470 uF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs The PVCC terminals provide the power to the output transistors so a 470 uF or larger capacitor should be placed on each PVCC terminal A 10 uF capacitor on the AVCC terminal is adequate These capacitors must be properly derated for voltage and ripple current rating to ensure reliability Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Link s TPA3124D2 TPA3124D2 13 TEXAS
17. IA TEXAS INSTRUMENTS www ti com TPA3124D2 SLOS578 MAY 2008 15 W STEREO CLASS D AUDIO POWER AMPLIFIER FEATURES System Two Audio Precision are trademarks of Audio Precision Inc 10 W Ch Into an 8 0 Load From a 24 V Supply 15 W Ch into a 4 O Load from a 22 V Supply 30 W Ch into a 8 O Load from a 22 V Supply Operates From 10 V to 26 V Can Run From 24 V LCD Backlight Supply Efficient Class D Operation Eliminates Need for Heat Sinks Four Selectable Fixed Gain Settings Internal Oscillator No External Components Reguired Single Ended Analog Inputs Thermal and Short Circuit Protection With Auto Recovery Space Saving Surface Mount 24 Pin TSSOP Package Advanced Power Off Pop Reduction APPLICATIONS e Flat Panel Televisions e DLP TVs e CRT TVs e Powered Speakers DESCRIPTION The TPA3124D2 is a 15 W per channel efficient class D audio power amplifier for driving stereo speakers in a single ended configuration or a mono speaker in a bridge tied load configuration The TPA3124D2 can drive stereo speakers as low as 4 Q The efficiency of the TPA3124D2 eliminates the need for an external heat sink when playing music The gain of the amplifier is controlled by two gain select pins The gain selections are 20 26 32 and 36 dB The patented start up and shutdown sequences minimize pop noise in the speakers without additional circuitry SIMPLIFIED APPLICATION CIRCUIT
18. L OUTPUT TPA3124D2 Mono Configuration Many of the class D APAs and many class AB APAs have differential inputs and bridge tied load BTL outputs Differential inputs have two input pins per channel and amplify the difference in voltage between the pins Differential inputs reduce the common mode noise and distortion of the input circuit BTL is a term commonly used in audio to describe differential outputs BTL outputs have two output pins providing voltages that are 180 out of phase The load is connected between these pins This has the added benefits of guadrupling the output power to the load and eliminating a dc blocking capacitor A block diagram of the measurement circuit is shown in Figure 36 The differential input is a balanced input meaning the positive and negative pins have the same impedance to ground Similarly the SE output equates to a balanced output Evaluation Module Generator Audio Power Amplifier Analyzer En F Lait C fYYY Cit R Lyi Leite FY V i E Cit I J Twisted Pair Wire Twisted Pair Wire Figure 36 Differential Input BTL Output Measurement Circuit The generator should have balanced outputs and the signal should be balanced for best results An unbalanced output can be used but it may create a ground loop that affects the measurement accuracy The analyzer must also have
19. auses the outputs to run at a constant 50 duty cycle A logic low on this pin enables the outputs This terminal may be used as a quick disable enable of outputs when changing channels on a television or transitioning between different audio sources The MUTE terminal should never be left floating For power conservation the SHUTDOWN terminal should be used to reduce the quiescent current to the absolute minimum level USING LOW ESR CAPACITORS Low ESR capacitors are recommended throughout this application section A real as opposed to ideal capacitor can be modeled simply as a resistor in series with an ideal capacitor The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor SHORT CIRCUIT PROTECTION The TPA3124D2 has short circuit protection circuitry on the outputs that prevents damage to the device during output to output shorts and output to GND shorts after the filter and output capacitor at the speaker terminal Directly at the device terminals the protection circuitry prevents damage to device during output to output output to ground and output to supply When a short circuit is detected on the outputs the part immediately disables the output drive This is an unlatched fault Normal operation is restored when the fault is removed Copyright 2008 Texas Instruments Incorp
20. d in a single ended SE half bridge amplifier For mono applications TPA3124D2 may be used as a bridge tied load BTL amplifier The traditional class D modulation scheme which is used in the TPA3124D2 BTL configuration has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage Vcc Therefore the differential prefiltered output varies between positive and negative Vcc where filtered 50 duty cycle yields 0 V across the load The class D modulation scheme with voltage and current waveforms is shown in Figure 25 and Figure 26 Vec ov Output Current e ane a Figure 25 Class D Modulation for TPA3124D2 SE Configuration ov ov Vcc Differential Voltage Across Speaker ov Vee Output Current LDL lt Figure 26 Class D Modulation for TPA3124D2 BTL Configuration Supply Pumping One issue encountered in single ended SE class D amplifier designs is supply pumping Power supply pumping is a rise in the local supply voltage due to energy being driven back to the supply by operation of the class D amplifier This phenomenon is most evident at low audio frequencies and when both channels are operating at the same freguency and phase At low levels power supply pumping results in distortion in the audio output due to fluctuations in supply voltage At higher levels pumping can cause the overvoltage protection to operate which temporarily shuts down the audio output 12 S
21. d to analog ground AGND pins 8 and 9 The PVCCx decoupling capacitors and VCLAMP capacitors should each be grounded to power ground PGND pins 13 14 23 and 24 Analog ground and power ground should be connected at the thermal pad which should be used as a central ground connection or star ground for the TPA3124D2 e Output filter The reconstruction filter L1 L2 C9 and C16 should be placed as close to the output terminals as possible for the best EMI performance The capacitors should be grounded to power ground e Thermal pad The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability The dimensions of the thermal pad and thermal land are described in the mechanical section at the back of the data sheet See TI Technical Briefs SLMA002 and SLOA120 for more information about using the thermal pad For recommended PCB footprints see figures at the end of this data sheet For an example layout see the TPA3124D2 Evaluation Module TPA3124D2EVM User Manual SLOU189 Both the EVM user manual and the thermal pad application note are available on the TI Web site at http www ti com 18 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3124D2 Id TEXAS INSTRUMENTS TPA3124D2 www ti com SLOS578 MAY 2008
22. e Q Cse DC Blocking Capacitor uF fo 60 Hz 3 dB fe 40 Hz 3 dB fe 20 Hz 3 dB 4 680 1000 2200 6 470 680 1500 8 330 470 1000 Output Filter and Frequency Response For the best frequency response a flat passband output filter Second order Butterworth may be used The output filter components consist of the series inductor and capacitor to ground at the LOUT and ROUT pins There are several possible configurations depending on the speaker impedance and whether the output configuration is single ended SE or bridge tied load BTL Table 4 lists the recommended values for the filter components It is important to use a high quality capacitor in this application A rating of at least X7R is required 14 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3124D2 IB TEXAS TPA3124D2 INSTRUMENTS www ti com SLOS578 MAY 2008 Table 4 Recommended Filter Output Components Output Configuration Speaker Impedance Q Filter Inductor uH Filter Capacitor nF 4 22 680 Single Ended SE 8 33 220 Bridge Tied Load BTL 8 22 680 LOUT o A 5 LOUT ROUT L iter Liter Critter Citer ROUT OJ P Litter Citer 77 Figure 27 BTL Filter Configuration Figure 28 SE Filter Configuration Power Supply Decoupling Cs The TPA3124
23. h information is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may reguire a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellec
24. half H bridge output stages use only NMOS transistors Therefore they require bootstrap capacitors for the high side of each output to turn on correctly A 220 nF ceramic capacitor rated for at least 25 V must be connected from each output to its corresponding bootstrap input Specifically one 220 nF capacitor must be connected from LOUT to BSL and one 220 nF capacitor must be connected from ROUT to BSR The bootstrap capacitors connected between the BSx pins and their corresponding outputs function as a floating power supply for the high side N channel power MOSFET gate drive circuitry During each high side switching cycle the bootstrap capacitors hold the gate to source voltage high enough to keep the high side MOSFETs turned on 16 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3124D2 IB TEXAS TPA3124D2 INSTRUMENTS www ti com SLOS578 MAY 2008 VCLAMP Capacitor To ensure that the maximum gate to source voltage for the NMOS output transistors is not exceeded one internal regulator clamps the gate voltage One 1 uF capacitor must be connected from VCLAMP pin 11 to ground and must be rated for at least 16 V The voltages at the VCLAMP terminal may vary with Vcc and may not be used for powering any other circuitry VBYP Capacitor Selection The scaled supply reference VBYP nominally provides an AVCC 8 internal bias for the preamplifier stages The external capacitor for t
25. heat dissipating abilities refer to Technical Brief PowerPAD Thermally Enhanced Package Texas Instruments Literature No SLMAQO2 and Application Brief PowerPAD Made Easy Texas Instruments Literature No SLMAQ04 Both documents are available at www ti com The exposed thermal pad dimensions for this package are shown in the following illustration 24 3 7 Exposed Thermal Pad Top View NOTE All linear dimensions are in millimeters Exposed Thermal Pad Dimensions 4206332 14 J 10 08 LAND PATTERN PWP R PDS0 G24 PowerPAD Example Board Layout Stencil Openings Via pattern and copper pad size Based on a stencil thickness may vary depending on layout constraints of 127mm 005inch Reference table below for other Increasing copper area will solder stencil thicknesses enhance thermal performance See Note D 22x0 65 24x0 25 pa Intanat UVU UO al CMU MMU 155 Z q See Note E Y 2 5 6 A X UL z ka 5 16 Solder mask a ela over copper See Note C D 22x0 65 7 8 i Example Non Soldermask Defined Pad Example Solder Mask Opening Se Nate P 007 All Around 0 a 4207609 12 G 12 08 NOTES A All linear dimensions are in millimeters B This draw
26. herwise noted TOTAL HARMONIC DISTORTION NOISE Voc 24 V RL 8 Q BTL Gain 20 dB vs FREQUENCY THD N Total Harmonic Distortion Noise Yo 0 001 20 100 1k 10k 20k f Frequency Hz G020 Figure 21 OUTPUT POWER vs SUPPLY VOLTAGE 50 RL 8 Q BTL 45 Gain 20 dB 40 7 35 4 BP 30 F 32 sf o 25 THD N 10 a a 5 o 20 ec 15 THD N 1 10 5 0 10 12 14 16 18 20 22 24 26 Voc Supply Voltage V G023 A Dashed line represents thermally limited region Figure 23 Copyright 2008 Texas Instruments Incorporated Product Folder Link s 10 0 1 0 01 0 001 0 01 100 90 TOTAL HARMONIC DISTORTION NOISE vs OUTPUT POWER RL 8 Q9 BTL Gain 20 dB Vcc 12V Voc 18 V 0 1 1 10 40 Po Output Power W G021 Figure 22 EFFICIENCY vs OUTPUT POWER RL 8 Q BTL Gain 20 dB 2 4 6 8 10 12 Po Output Power W G024 Figure 24 Submit Documentation Feedback 11 TPA3124D2 TPA3124D2 13 TEXAS INSTRUMENTS SLOS578 MAY 2008 www ti com APPLICATION INFORMATION CLASS D OPERATION This section focuses on the class D operation of the TPA3124D2 Traditional Class D Modulation Scheme The TPA3124D2 operates in AD mode There are two main configurations that may be used For stereo operation the TPA3124D2 should be configure
27. his reference Cayp is a critical component and serves several important functions During start up or recovery from shutdown mode Cpyp determines the rate at which the amplifier starts The start up time is proportional to 0 5 s per microfarad Thus the recommended 1 uF capacitor results in a start up time of approximately 500 ms The second function is to reduce noise produced by the power supply caused by coupling with the output drive signal This noise could result in degraded power supply rejection and THD N The circuit is designed for a Cgyp value of 1 uF for best pop performance The input capacitors should have the same value A ceramic or tantalum low ESR capacitor is recommended SHUTDOWN OPERATION The TPA3124D2 employs a shutdown mode of operation designed to reduce supply current Icc to the absolute minimum level during periods of nonuse for power conservation The SHUTDOWN input terminal should be held high see specification table for trip point during normal operation when the amplifier is in use Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low current state Never leave SHUTDOWN unconnected because amplifier operation would be unpredictable For the best power up pop performance place the amplifier in the shutdown or mute mode prior to applying the power supply voltage MUTE Operation The MUTE pin is an input for controlling the output state of the TPA3124D2 A logic high on this terminal c
28. in TSSOP 4 16 W 33 3 mW C 2 67 W 2 16 W 1 For the most current package and ordering information see the Package Option Addendum at the end of this document or see the TI website at www ti com 2 This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high k PCB The thermal pad must be soldered to a thermal land on the printed circuit board See the PowerPAD Thermally Enhanced Package application note SLMA002 RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT Voc Supply voltage PVCC AVCC 10 26 V VH High level input voltage SD MUTE GAINO GAIN1 2 V VL Low level input voltage SD MUTE GAINO GAIN1 0 8 V SD Vi Voc Vcc 30 V 125 liq High level input current MUTE V Voc Voc 30 V 125 uA GAINO GAIN1 V Vcc Vec 24 V 125 SD Vj 0 Vcc 30 V 1 lit Low level input current MUTE V 0 V Voc 30 V 1 uA GAINO GAIN1 V 0 V Vcc 24 V 1 Ta Operating free air temperature 40 85 C Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TPA3124D2 TPA3124D2 SLOS578 MAY 2008 DC CHARACTERISTICS Ta 25 C Voc 24 V R 80 unless otherwise noted Ih TEXAS INSTRUMENTS www ti com PARAMETER TEST CONDITIONS MIN TYP M
29. ing is subject to change without notice C Customers should place a note on the circuit board fabrication drawing not to alter the center solder mask defined pad D This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMA002 SLMA004 and also the Product Data Sheets for specific thermal information via requirements and recommended board layout These documents are available at www ti com lt http www ti com gt Publication IPC 7351 is recommended for alternate designs E Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release Customers should contact their board assembly site for stencil design recommendations Example stencil design based on a 50 volumetric metal load solder paste Refer to IPC 7525 for other stencil recommendations F Customers should contact their board fabrication site for solder mask tolerances between and around signal pads PowerPAD is a trademark of Texas Instruments W Texas IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that suc
30. me from mute input switches low until 120 msec outputs unmuted 4 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3124D2 IB TEXAS TPA3124D2 INSTRUMENTS www ti com SLOS578 MAY 2008 FUNCTIONAL BLOCK DIAGRAM lt gt BSL AVCC lt gt gt gt AVDD lt gt PVCCL REGULATOR lt gt LOUT lt gt PGNDL LIN AVDD 2 AGND lt gt SD CONTROL BIAS THERMAL Aye aan MUTE MUTE lt gt CONTROL OSC RAMP VVN BYPASS lt gt BYPASS GAIN1 lt gt E AV GAINO lt gt CONTROL lt gt BSR lt gt PVCCR lt gt ROUT lt gt PGNDR RIN Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link s TPA3124D2 TPA3124D2 Ip TEXAS
31. ms and can be ignored for all but the power related calculations Figure 34 a shows a class AB amplifier system It takes an analog signal input and produces an analog signal output This amplifier circuit can be directly connected to the AP II or other analyzer input This is not true of the class D amplifier system shown in Figure 34 b which requires low pass filters in most cases in order to measure the audio output waveforms This is because it takes an analog input signal and converts it into a pulse width modulated PWM output signal that is not accurately processed by some analyzers 20 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3124D2 J TEXAS TPA3124D2 INSTRUMENTS www ti com SLOS578 MAY 2008 Power Supply Signal R Analyzer Generator 20 Hz 20 kHz 6 a Basic Class AB Power Supply Lt hh o Signal 3 Coz Analyzer Generator Class D APA filt T R 20 Hz 20 kHz gt b Traditional Class D Figure 34 Audio Measurement Systems Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Link s TPA3124D2 TPA3124D2 i TEXAS INSTRUMENTS SLOS578 MAY 2008 www ti com SE Input and SE Output TPA3124D2 Stereo Configuration The SE input and output configuration is used with class AB amplifiers A block diagram of a fully SE measurement circuit is shown in Figure 35 SE inputs no
32. n designed to accommodate the component width BO Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness y Overall width of the carrier tape Pitch between successive cavity centers t Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes User Direction of Feed All dimensions are nominal Device Package Package Pins SPO Reel Reel A0 mm BO mm KO mm P1 W Pin1 Type Drawing Diameter Width mm mm Quadrant mm W1 mm TPA3124D2PWPR HTSSOP PWP 24 2000 330 0 16 4 6 95 8 3 1 6 8 0 16 0 Q1 Pack Materials Page 1 kid Texas PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 7 Jun 2008 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TPA3124D2PWPR HTSSOP PWP 24 2000 346 0 346 0 33 0 Pack Materials Page 2 MECHANICAL DATA PWP R PDSO G PowerPAD PLASTIC SMALL OUTLINE PACKAGE 20 PIN SHOWN A Thermal Pad See Note D i Gage Plane 4 A 4 Seating Plane L 120 MAX 015 f T010
33. orated Submit Documentation Feedback 17 Product Folder Link s TPA3124D2 TPA3124D2 13 TEXAS INSTRUMENTS SLOS578 MAY 2008 www ti com THERMAL PROTECTION Thermal protection on the TPA3124D2 prevents damage to the device when the internal die temperature exceeds 150 C There is a 15 C tolerance on this trip point from device to device Once the die temperature exceeds the thermal set point the device enters into the shutdown state and the outputs are disabled This is not a latched fault The thermal fault is cleared once the temperature of the die is reduced by 30 C The device begins normal operation at this point with no external system interaction PRINTED CIRCUIT BOARD PCB LAYOUT Because the TPA3124D2 is a class D amplifier that switches at a high frequency the layout of the printed circuit board PCB should be optimized according to the following guidelines for the best possible performance e Decoupling capacitors The high frequency 0 1 uF decoupling capacitors should be placed as close to the PVCC pins 1 3 10 and 12 and AVCC pins 19 and 20 terminals as possible The VBYP pin 7 capacitor and VCLAMP pin 11 capacitor should also be placed as close to the device as possible Large 220 uF or greater bulk power supply decoupling capacitors should be placed near the TPA3124D2 on the PVCCL and PVCCR terminals e Grounding The AVCC pins 19 and 20 decoupling capacitor and VBYP pin 7 capacitor should each be grounde
34. rmally have one input pin per channel In some cases two pins are present one is the signal and the other is ground SE outputs have one pin driving a load through an output ac coupling capacitor and the other end of the load is tied to ground SE inputs and outputs are considered to be unbalanced meaning one end is tied to ground and the other to an amplifier input output The generator should have unbalanced outputs and the signal should be referenced to the generator ground for best results Unbalanced or balanced outputs can be used when floating but they may create a ground loop that affects the measurement accuracy The analyzer should have balanced inputs to cancel out any common mode noise in the measurement Twisted Pair Wire Twisted Pair Wire Figure 35 SE Input SE Output Measurement Circuit The following general rules should be followed when connecting to APAs with SE inputs and outputs e Use an unbalanced source to supply the input signal e Use an analyzer with balanced inputs e Use twisted pair wire for all connections e Use shielding when the system environment is noisy e Ensure the cables from the power supply to the APA and from the APA to the load can handle the large currents see Table 5 22 Submit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3124D2 D ONAE TPA3124D2 www ti com SLOS578 MAY 2008 DIFFERENTIAL INPUT AND BT
35. rovided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory reguirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 reguirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such reguirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Clocks and Timers www ti com clocks Digital Control www ti com digitalcontrol
36. s the absolute minimum input impedance of the TPA3124D2 At the higher gain settings the input impedance could increase as high as 72 kQ Table 2 Gain Setting AMPLIFIER GAIN dB NPUT IMPEDANCE GAIN1 GAINO Ty ko TYPICAL 0 0 20 60 0 1 26 30 1 0 32 15 1 1 36 9 INPUT RESISTANCE Changing the gain setting can vary the input resistance of the amplifier from its smallest value 10 kQ 20 to the largest value 60 kQ 20 As a result if a single capacitor is used in the input high pass filter the 3 dB cutoff frequency may change when changing gain steps Input ii Signal The 3 dB frequency can be calculated using Equation 1 Use the Z values given in Table 2 Copyright 2008 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link s TPA3124D2 TPA3124D2 13 TEXAS INSTRUMENTS SLOS578 MAY 2008 www ti com INPUT CAPACITOR C In the typical application input capacitor C is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation In this case C and the input impedance of the amplifier Z form a high pass filter with the corner freguency determined in Eguation 2 3 dB fe 2 The value of C is important as it directly affects the bass low frequency performance of the circuit Consider the example where Z is 20 kQ and the specification calls for a flat bass response down to 20 Hz Eq
37. tual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be p
38. uation 2 is reconfigured as Eguation 3 1 C 21 Zi f 3 In this example C is 0 4 uF so one would likely choose a value of 0 47 uF as this value is commonly used If the gain is known and is constant use Z from Table 2 to calculate Cj A further consideration for this capacitor is the leakage path from the input source through the input network Cj and the feedback network to the load This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom especially in high gain applications For this reason a low leakage tantalum or ceramic capacitor is the best choice When polarized capacitors are used the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2 V which is likely higher than the source dc level Note that it is important to confirm the capacitor polarity in the application Additionally lead free solder can create dc offset voltages and it is important to ensure that boards are cleaned properly Single Ended Output Capacitor Co In single ended SE applications the dc blocking capacitor forms a high pass filter with the speaker impedance The frequency response rolls off with decreasing frequency at a rate of 20 dB decade The cutoff frequency is determined by fe TCL Table 3 shows some common component values and the associated cutoff frequencies Table 3 Common Filter Responses Speaker Impedanc
39. ubmit Documentation Feedback Copyright 2008 Texas Instruments Incorporated Product Folder Link s TPA3124D2 If TEXAS TPA3124D2 INSTRUMENTS www ti com SLOS578 MAY 2008 Several things can be done to relieve power supply pumping The lowest impact is to operate the two inputs out of phase 180 and reverse the speaker connections Because most audio is highly correlated this causes the supply pumping to be out of phase and not as severe If this is not enough the amount of bulk capacitance on the supply must be increased Also improvement is realized by hooking other supplies to this node thereby sinking some of the excess current Power supply pumping should be tested by operating the amplifier at low frequencies and high output levels Gain Setting via GAINO and GAIN1 Inputs The gain of the TPA3124D2 is set by two input terminals GAINO and GAIN1 The gains listed in Table 2 are realized by changing the taps on the input resistors and feedback resistors inside the amplifier This causes the input impedance Z to be dependent on the gain setting The actual gain settings are controlled by ratios of resistors so the gain variation from part to part is small However the input impedance from part to part at the same gain may shift by 20 due to shifts in the actual resistance of the input resistors For design purposes the input network discussed in the next section should be designed assuming an input impedance of 8 kQ which i
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