Computing device having instructions which access either a
Contents
1. 712 208 711 5 157 148 173 which are selected by a bank selection instruction The memory bank selected by the bank selection instruction is 56 References Cited accessed by a memory access instruction immediately fol U S PATENT DOCUMENTS lowing the bank selection instruction Following any instruction other than the bank selection instruction a 4 028 675 6 1977 Frankenberg 365 222 default memory bank is selected automatically This scheme Pe OL dy o SADE 333 12 eliminates the need to select the default memory bank PU 3 foot eem doom explicitly and the need to save and restore the contents of a 001 i EH 5193169 A 3 1993 Ishikawa 7 10 22 bank selection register when interrupts are served 5 655 000 A 8 1997 Bjerge et al 711 2 5 751 988 A 5 1998 Fujimura 711 220 8 Claims 4 Drawing Sheets 8 BANK REGISTER INSTRUCTION MEMORY INSTRUCTION DECODER ACCUMULATOR U S Patent Sep 21 2004 Sheet 1 of 4 US 6 795 911 B1 FIG 1 64 KBYTES x 8 BANKS US 6 795 911 B1 Sheet 2 of 4 Sep 21 2004 U S Patent NOILONYLSNI AHOWAIN NOLLONYLSNI 1 61V 9LV Old U S Patent Sep 21 2004 Sheet 3 of 4 US 6 795 911 B1 16 19 US 6 795 911 B1 Sheet 4 of 4 Sep 21 2004 U S Patent YOLVINANNDOV NOILONYLSNI AYOWAW NOILONYLSNI H31SI03H NVS82. HOlWd V 91 US 6 795 911 B1 1 COMPUTING DEVICE HAVING INSTRUCTIONS WHICH ACCESS EITHER A PERMANENTLY FIXED DEFAULT MEMORY BANK OR A MEMORY BANK SPECIFIED BY AN IMMEDIATELY PRECEDING BANK SELECTION INSTRUCTION BACKGROUND OF THE INVENTION The present invention relates to a computing device such as a microprocessor employing a memory divided into banks Microprocessors capable of addressing multiple memory banks are well known in the computing art The instruction set of a microprocessor of this type includes a bank selection instruction that sets a bank address in a bank register Memory access instructions specify addresses that can apply to any bank When a memory access instruction is executed the address specified in the instruction is combined with the value in the bank register to generate an address specifying both a particular memory bank and a particular location in that memory bank If the software running on the microprocessor is of the multitasking type different tasks or processes may use different memory banks Typically each process begins with a bank selection instruction that sets the address of the desired bank in the bank register If necessary the bank selection instruction can be executed again during the pro cess to switch banks If one process interrupts another the bank register contents are saved onto a stack and restored when the interrupting process ends so that the interrupted process can re
3. which are input by the selector 28 The output terminal of the first AND gate 22 is coupled to the clock CK input terminal of the set reset flip flop 20 The output terminal of the second AND gate 24 is coupled through inverter 26 to the clear CLR input terminal of the set reset flip flop 20 The data input terminal D and set input terminal S of the set reset flip flop 20 are coupled to the power supply thus being held at the high 1 logic level The data output terminal of the set reset flip flop 20 is coupled to the selector 28 The set and clear inputs S and CLR are active low The selector 28 also has a set of grounded input terminals When the output of the set reset flip flop 20 is high 1 the selector 28 selects the A A o address bits received from the bank register 8 When the Q output of the set reset flip flop 20 is low 0 the selector 28 selects the grounded 0 inputs The selected inputs of the selector 28 become the output address bits supplied by the bank control unit 10 to the memory banks 16 Next the operation of this microprocessor 1 will be described The microprocessor 1 has a conventional instruction set with a bank selection instruction that writes desired values of address bits to into the bank register 8 The bank selection instruction also disables interrupts for one instruc tion execution cycle so that an interrupt received during the execut
4. DESCRIPTION OF THE INVENTION An embodiment of the invention will be described with reference to the attached drawings in which like parts are indicated by like reference characters FIG 1 illustrates a memory divided into eight banks numbered from zero to seven Each memory bank has addresses from 0000H to FFFFH the H suffix indicating hexadecimal notation These addresses are specified by sixteen address bits Each memory bank has a capacity of sixty four kilobytes FIG 2 shows a microprocessor 1 embodying the present invention using the bank memory shown in FIG 1 The microprocessor 1 comprises a processing unit 2 with an internal instruction memory 4 an instruction decoder 6 a bank register 8 a bank control unit 10 a data input output I O port 12 an accumulator 14 and various other facilities not visible The processing unit 2 is coupled to the eight memory banks 16 by an address bus carrying sixteen address bits A to A 5 an additional address bus carrying four more address bits 5 to and a data bus carrying sixteen parallel data bits Dg to D The twenty address bits from to have values from 00000H to OFFFFH identifying locations in memory bank zero through 70000H to identifying locations in memory bank seven The memory banks 16 are part of the microprocessor 1 prefer ably being integrated onto the same semiconductor substrate as the processing unit 2 Incidentally the term m
5. conversion of existing software SUMMARY OF THE INVENTION An object of the present invention is to enable a comput ing device to access multiple memory banks without requir ing all processes to execute bank selection instructions Another object is to eliminate the saving and restoring of bank register contents 10 15 20 25 40 45 50 55 60 65 2 The invented method of selecting memory bank includes the steps of selecting a memory bank specified by a bank selection instruction for use by the next instruction executed after the bank selection instruction and automatically selecting a predetermined default memory bank following execution of any instruction other than the bank selection instruction The invented computing device has a bank register storing a value specifying one of a plurality of memory banks and bank control unit operating in a first state and second state In the first state the bank control unit selects the memory bank specified by the bank register In the second state the bank control unit selects the predetermined memory bank BRIEF DESCRIPTION OF THE DRAWINGS In the attached drawings FIG 1 illustrates a memory divided into banks FIG 2 is a block diagram of a microprocessor embodying the present invention FIG 3 is a more detailed block diagram of the bank control unit in FIG 2 and FIG 4 is a block diagram of a conventional micropro cessor DETAILED
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7. 25 35 40 45 50 55 60 65 4 interval the selector 28 selects the grounded inputs and supplies A A address value of OH selecting bank Zero The bank designated by the bank register 8 is thus selected only during the execution of the next instruction following each bank selection instruction At other times bank zero is selected regardless of the contents of the bank register 8 Consequently absent an immediately preceding bank selec tion instruction a memory access instruction accesses memory bank zero by default The memory access instructions decoded by the instruc tion decoder 6 specify sixteen bit memory addresses which the instruction decoder places on the A A address bus signal lines These sixteen bit addresses indicate locations in all eight memory banks 16 without specifying which memory bank is to be accessed but there is no ambiguity By default memory access instruction accesses memory bank zero If immediately preceded by a bank selection instruction the memory access instruction accesses the memory bank specified in the bank selection instruction A memory access transfers data on the data bus lines Do to D between the selected memory bank 16 and for example the accumulator 14 the data passing through the data input output port 12 Data can also be transferred between the selected memory bank and other facilities not visible in the processing unit 2 Memory bank zero preferab
8. US006795911B1 United States Patent 12 10 Patent No US 6 795 911 B1 Miyano 45 Date of Patent Sep 21 2004 54 COMPUTING DEVICE HAVING 5 895 481 4 1999 Yap 711 5 INSTRUCTIONS WHICH ACCESS EITHER A 5 937 199 A 8 1999 Temple 710 262 PERMANENTLY FIXED DEFAULT MEMORY 6 260 101 7 2001 Hansen et al 710 22 BANK OR A MEMORY BANK SPECIFIED BY FOREIGN PATENT DOCUMENTS AN IMMEDIATELY PRECEDING BANK SELECTION INSTRUCTION J ss d n 75 Inventor Tomomi Miyano Miyazaki JP JP 7 325757 12 1995 OTHER PUBLICATIONS 73 Assignee Oki Electric Industry Co Ltd Tokyo JP Intel Corporation iAPX 86 88 186 188 User s Manual Hardware Reference 1985 pp 1 1 and 1 7 to 1 10 Notice Subject to any disclaimer the term of this Harvey R E 8086 Processor Registers http web archi patent is extended or adjusted under 35 ve org web 19991111090421 http ourworld compuserve U S C 154 b by 0 days com homepages r harvey doc cpu htm 1999 21 Appl No 09 493 157 22 Filed Jan 28 2000 Primary Examiner Eddie Chan Assistant Examiner David J Huisman 51 pestilence G06F 12 00 GO6F 9 00 74 Attorney Agent or Firm Volentine Francos PLLC y Ag 52 0 8 Cl 712 225 712 208 57 ABSTRACT 58 Field of Search 712 228 225 computing device accesses multiple memory banks
9. ermanently fixed default memory bank and accessing the default memory bank according to the executed memory access instruction 2 The method of claim 1 wherein said step a further comprises the steps of storing a value specified by the bank selection instruction in a bank register setting a bi stable circuit to a first state when the bank selection instruction is executed and setting said first part of the according to the value stored in the bank register when the bi stable circuit is in the first state and said step b further comprises the steps of setting the bi stable circuit to a second state following said execution of each instruction other than the bank selection instruction and setting said first part of the address to said permanently fixed value when the bi stable circuit is in the second state 3 The method of claim 1 further comprising the step of disabling interrupts during the execution of the bank selec tion instruction 4 A computing device having a memory permanently divided into a plurality of mutually exclusive memory 10 15 20 35 40 45 50 60 65 6 banks the computing device also having an instruction set that includes memory access instructions and a bank selec tion instruction the computing device further having a bank register storing a value specifying an arbitrary one of the plurality of mutually exclusive memory banks the comput ing device generating an addres
10. icroprocessor as used herein also includes computing devices that are commonly referred to as microcomputers and microcontrollers The instruction decoder 6 decodes instructions received from the instruction memory 4 supplies address bits A to A5 to the memory banks supplies address bits to Ayo to the bank register 8 and controls the bank control unit 10 The bank control unit 10 receives address bits A to Ajo from the bank register 8 and supplies either the received address bits or four bits having a fixed value of OH to the US 6 795 911 B1 3 memory banks 16 depending on signals received from the instruction decoder 6 The four bits to output by the bank control unit 10 select one of the memory banks 16 Three bits would be adequate since there are only eight banks but four bits give the microprocessor 1 the capability to address up to sixteen memory banks The other sixteen address bits A to s specify a location in the memory bank selected by bits to Ajo FIG 3 shows the internal structure of the bank control unit 10 which comprises a set reset flip flop 20 a pair of AND gates 22 24 an inverter 26 and a selector 28 The signals received by the bank control unit 10 include a bank output enable signal BEN which is input by the first AND gate 22 a clock signal CLK input by both AND gates 22 24 a bank output disable signal BDIS input by the second AND gate 24 and address bits A to Al
11. ion of the bank selection instruction is not recognized until after the next instruction has been executed Upon decoding the bank selection instruction besides sending address bits to to the bank register 8 the instruction decoder 6 sets the bank enable signal BEN to the high level and the bank disable signal BDIS to the low level The clear input terminal of the set reset flip flop 20 is thereby set to the inactive high level and input of the clock signal CLK to the clock input terminal CK is enabled During the next clock cycle the high logic level that is constantly received at the data input terminal D is latched in the set reset flip flop 20 in synchronization with the clock signal causing the Q output signal to go high thereby causing the selector 28 to select the A address values received from the bank register 8 Upon decoding any instruction other than the bank selec tion instruction the instruction decoder 6 sets the bank enable signal BEN to the low level at for example the beginning of the instruction execution cycle and sets the bank disable signal BDIS to the high level at the end of the instruction execution cycle The signal output from inverter 26 goes low for the duration of one high CLK pulse thereby clearing the set reset flip flop 20 and forcing the Q output signal to go low The Q output signal remains low until the next bank selection instruction is executed Throughout this 10 15 20
12. ly includes memory mapped special function registers memory mapped input output ports the interrupt vector table and other frequently accessed addresses In typical applications many processes will need to access only memory bank zero These processes can be coded using only standard memory access instruc tions specifying sixteen bit addresses without any bank selection instructions at all The code size and execution time of these processes are thereby reduced Processes that access other memory banks require a separate bank selection instruction each time a bank other than bank zero is accessed even when the same bank is accessed repeatedly While this requirement is a disadvantage the disadvantage is offset by the advantage that these processes can switch from another bank to bank zero without having to execute a bank selection instruction A further advantage of the invented microprocessor is that when one process interrupts another the bank register contents do not have to be saved and restored Even if an interrupt request is received during the execution of a bank selection instruction the memory access instruction to which the bank selection instruction applies is executed before the interrupt is served so the interrupt handling process can alter the bank register contents with impunity Eliminating the saving and restoring of the bank register is a significant advantage in real time control applications A further advantage is
13. ng a memory bank for access by a computing device having a memory permanently divided into a plurality of mutually exclusive memory banks the computing device also having an instruction set that includes memory access instructions and a bank selection instruction the computing device generating an address upon execution of each memory access instruction the address being divided into a first part and a second part the first part and the second part being mutually exclusive the first part including at least one first address bit for selecting the memory bank from among the plurality of mutually exclu sive memory banks and the second part including a plurality of second address bits used in common for specifying addresses within any selected one of the plurality of mutu ally exclusive memory banks the method comprising the steps of a upon execution of each memory access instruction which follows a bank selection instruction setting said first part of the address generated by the computing device according to the bank selection instruction to select the memory bank specified by the bank selection instruction and accessing the specified memory bank according to the executed memory access instruction and b upon execution of each memory access instruction which does not follow a bank selection instruction automatically setting said first part of the address generated by the computing device to a permanently fixed value to select a p
14. s upon execution of each memory access instruction the address being divided into a first part and a second part the first part and the second part being mutually exclusive the first part including at least one first address bit for selecting an arbitrary one of the plurality of mutually exclusive memory banks and the second part including a plurality of second address bits for specifying addresses within the arbitrary selected memory bank the computing device comprising a bank control unit operating in a first state and a second state wherein in the first state the bank control unit sets said first part of the address to the value stored in said bank register to select the memory bank specified by the bank register and wherein in the second state the bank control unit sets said first part of the address to a permanently fixed value to select a permanently fixed one of the memory banks wherein said bank control unit operates in said first state upon execution of each memory access instruction which follows a the bank selection instruction and wherein said bank control unit operates in said second state upon execution of each memory access instruction which does not follow a the bank selection instruction 5 The computing device of claim 4 wherein the bank selection instruction sets said value in the bank register further comprising an instruction decoder decoding the instructions in the instruction set setting the bank control uni
15. sume use of the correct bank An advantage of this scheme is that the memory address space can be expanded beyond the size that can be addressed by any one memory access instruction without increasing the bit length of the memory access instructions A disadvantage however is that saving and restoring the contents of the bank register delays the switchover from one process to the other This is a particular disadvantage in real time control systems requiring quick response to inter rupts A further disadvantage is that every process must set the bank register to be sure that memory accesses will be directed to the correct bank There may be for example many short processes that use only one memory bank all sharing the same memory bank Each of these processes must still start by executing the bank selection instruction which adds an unnecessary instruction to the process code and further delays the start of the process These disadvantages could be overcome by adding bank selection bits to the memory access instructions enabling each memory access instruction to specify both a memory bank and a location in the memory bank but that would be a highly inefficient solution Code size would be greatly increased and extra circuits would be needed to analyze the added instruction bits increasing the size and cost of the microprocessor itself The expanded instructions would also be incompatible with existing instruction sets requiring much
16. t to the first state when the bank selection instruction is decoded and setting the bank control unit to the second state following execution of each instruction other than the bank selection instruction in the instruction set 6 The computing device of claim 4 wherein the bank control unit comprises a bi stable circuit generating a first control value in the first state and a second control value in the second state and a selector coupled to the bi stable circuit having a first input terminal receiving the value stored in the bank register and a second input terminal receiving said permanently fixed value selecting the first input ter minal when the bi stable circuit generates the first control value selecting the second input terminal when the bi stable circuit generates the second control value and supplying the value received at the selected input terminal to the memory banks as said first part of the address 7 The computing device of claim 4 wherein the com puting device is a microprocessor 8 The computing device of claim 5 wherein the instruc tion decoder sends the bank control unit a first signal and a second signal the first signal setting the bank control unit to the first state the second signal setting the bank control unit to the second the first signal being output when the bank selection instruction is decoded the second signal being output when any instruction other than the bank selection instruction is
17. that the invented microprocessor operates efficiently regardless of whether or not there are multiple memory banks and enables the number of banks to be expanded from one to more than one without requiring modifications to existing software An operating system and other programs coded for a single bank environment can be used without change in a multiple bank environment For comparison FIG 4 shows a conventional micropro cessor 30 with multiple memory banks The conventional microprocessor 30 has the structure shown in FIG 2 without the bank control unit The bank register 8 is always used to select the memory bank so even instructions that access bank zero must be preceded by a bank selection instruction and the bank register contents must be saved and restored at interrupts US 6 795 911 B1 5 The invention is not limited to the embodiment described above For example the memory banks need not all be integrated into the microprocessor External memory banks can be accessed in the same way The structure of the bank control unit shown in FIG 3 can be modified in various ways For example the second AND gate 24 and inverter 26 can be replaced by a NAND gate The set reset flip flop 20 can be replaced by any type of bi stable circuit that can be switched between two states Those skilled in the art will recognize that further varia tions are possible within the scope claimed below What is claimed is 1 A method of selecti
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