CCG1: USB Type-C Port Controller with PD
Contents
1. SS CYPRESS ZS SaaS ZS SS e Puccini Mlle al PERFORM Figure 13 Notebook DRP Application Diagram PFET To System 5 4 s 8 4 p S 50kKQ S 5 From 5V PFET VBUS System D als s 4 S 50k2 s A 5 S 100kQ 1 z 5 Volts 1000 1 1W 10kQ 1 NFET T CS P F ck wer g d 0 20 196 VBUS_DISCHARGE oh ol 3 9kO 1 i 5 s s CS M 10k2 1 E VDDD 5V AN bis tur e PFET 5 3332 40 pa 35 36 24 L3 NFET Fj Se sl wy EREM S Sp e sigo T 1 9 Q a o el s E 5 G BPR ES DAIN a 2 aad 2 23 S PP VDDD 1MO 5 Rd oe H o z Za 2 CORP VV CS P HRECS P 2 g SS 9 40kQ 5 D CS M bWuCS M gt 5 aie 22 NFET NFET 76 VSEL2 GPIO1 o 9 SLUD z 47 C_SEUGPIO2 a S 3900 1 S K IFAULTIGPIOS ici cci AA c VDDD ae gt lt VBUS_DISCHARGE lt 25 VBUS_DISCHARGE 1200 1 S ep CC 1 3 Ca Type C IB amp MUXSEL 1 CC1 CTRL Receptacle 44 MUXSEL 2 10kO 1 4 MUXSEL 3 ANV cc2 4 9 MUXSEL 4 E e CYPD1122 40LQXI oll 14 40QFN 5 gt PFET HPD 4 A HOTPLUG DET CC2 VCONN CTR Le STVSEL1 3900 1 26 NFET Cc2 Na SLU Seel 21 s p La DEV_DET 1200 1 4 7nF L Tima 5 z a VDDB L E Ra S SI Embedded Tee 4 10 Controller SWD_CLK CC2 CTRL B W lo sc ee Da E Q a Blizc_spa A RP on 5 a Zoe INT D CC2 RP de D 30 lt gt 27 NFET XRES m m o CC2 RD GIG ar is 0 1uF SS s E USB 9 34 39 VDDD HS Chipset 52. Acronym Description opamp operational amplifier OCP Overcurrent protection OVP Overvoltage protection PCB printed circuit board PGA programmable gain amplifier PHY physical layer POR power on reset PRES precise power on reset PSoc Programmable System on Chip PWM pulse width modulator RAM random access memory RISC reduced instruction set computing RMS root mean square RTC real time clock RX receive SAR successive approximation register SCL DC serial clock SDA DC serial data S H sample and hold SPI Serial Peripheral Interface a communications protocol SRAM static random access memory SWD serial wire debug a test protocol TX transmit UART Universal Asynchronous Transmitter Receiver a communications protocol UFP upstream facing port USB Universal Serial Bus USBIO USB input output PSoC pins used to connect to a USB port XRES external reset I O pin Page 31 of 34 PERFORM Document Conventions Units of Measure Table 27 Units of Measure PRELIMINARY Symbol Unit of Measure C degrees Celsius Hz hertz KB 1024 bytes kHz kilohertz kQ kilo ohm Mbps megabits per second MHz megahertz MQ mega ohm Msps megasamples per second HA microampere uF microfarad us microsecond uV microvolt uW microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond
3. Type C PI ype ug Type C Plug VBUS VCONN 1 BAT54V 7 BAT54V 7 VCONN 2 A1 ci ca ki A2 100k 100k 10 7 P 20kO 1 100kQ 1 10 D Ia 2SK3796 i 1 c 2SK3796 S RE s 1k 1uF I 1k 5 Ra T 5 Ra_Far L A5 c7 L CC1_LPREF VDDD A1 A2 M A6 B4 C2 D2 cpio D amp E1 E2 E3 E6 E7 C vCONN DET D4 E4 RA DISCONNECT IP m o E5 RA_FAR_DISCONNECT cc_vrerc 22ntL 22 4k1 A3 2k 1 1k 1 B CYPD1103 35FNXI TX_GND 1 L XRES 35CSP TX REF WII ATpF natu p5 tP5 Bypass d ln TX u P3 TuF y mil n7 22 Q 596 4 VCCD CC1 TX B7 vss DC DC SWD SWD_ CC1 RN SCL SDA IO CLK CC4 LPRX P i ck NTNS3164NZ D cc cc SuperSpeed and HighSpeed Lines GND Document Number 001 93639 Rev E Page 20 of 34 wes PRELIMINARY CCG1 Datasheet aa a s CYPRESS PERFORM Figure 9 Single Chip Cable Component Count 13 Type C Plug Type C Plug VBUS VCONN 1 BATS4V 7 BAT54V 7 VCONN 2 A1 j t c2 A2 L Kj 1k 5 Ra wi 1k 5 Ra Far l A5 c7 l CC1LPREF VDDD A1 A2 A4 A6 B4 C2 D2 pel D6 E1 E2 E3 E6 E7 C6 ycONN DET D4 E RA DISCONNECT ee o E lpa FAR DISCONNECT cc vnEE CS 22nfL 324k1 A3 2k1 31k 1 Se CYPD1103 35FNXI X GND 1 H XRES 35CSP TX REF WI 47pF BS PI pypass E 1uF TX U D uF A D 220 5 i VCCD CC1 TX Bll vss d DC GC SWD SWD_ GON SCL SDA lO CL
4. C2 D2 D6 E1 E2 E3 E6 E7 Document Number 001 93639 Rev E Page 4 of 34 ER Z PRELIMINARY CCG1 Datasheet PERFORM Following is the pin definitions for 40 pin QFN and 35 ball WLCSP for the notebook tablet smartphone and monitor applications Refer to Table 22 for part numbers to package mapping 40 QFN 1 40 QFN 2 35 CSP 2 SE Functional Pins Pins Pins Balls Type Description MUXSEL_1 1 1 D5 O External Data Mux Select signal 1 MUXSEL_2 2 2 D6 O External Data Mux Select signal 2 CC1_CTRL 3 3 D3 UO CC1 control 0 TX enabled z RX sense CC2_CTRL 4 4 E4 UO CC2 control 0 TX enabled z RX sense MUXSEL_3 5 5 E5 O External Data Mux Select signal 3 MUXSEL_4 6 6 E6 O External Data Mux Select signal 4 CS P 7 7 E3 Current Sensing Plus input CS_M 8 8 E2 l Current Sensing Minus input VSS 9 9 GND Ground CC1 10 10 E1 UO Configuration Channel 1 MUXSEL_5 11 11 D2 O External Data Mux Select signal 5 SWD IO 12 12 D1 UO SWD IO SWD CLK 13 13 C1 l SWD Clock HOTPLUG_DET 14 14 C2 UO HotPlug Detection for Display Port Alternate Mode GPIO1 15 UO GPIO VSEL2 15 O Voltage Select signal 2 for selecting output voltage GPIO2 16 UO GPIO IO C SEL 16 l Configuration Select signal GPIO3 17 UO GPIO IFAULT 17 l Current Fault Indication 0 No fault 1 Current fault I2C_SCL 18 18 B1 UO I2C Clock signal I2C_SDA 19 19 B2 UO I2C Data s
5. Q ohm pF picofarad ppm parts per million ps picosecond S second sps samples per second V volt Document Number 001 93639 Rev E CCG1 Datasheet Page 32 of 34 Revision PERFORM History PRELIMINARY CCG1 Datasheet Description Title CCG1 Datasheet USB Type C Port Controller with Power Delivery Document Number 001 93639 Revision ECN Orig of Change Submission Date Description of Change ik 4520316 MSMI 09 30 2014 New data sheet A 4531795 SJH 10 13 2014 Updated Functional Definition Updated Figure 8 Figure 9 Figure 10 Figure 11 Figure 14 Figure 13 Added Figure 15 Updated Pinouts Updated Power Updated Figure 5 Figure 8 Updated Ordering Information Added Note 21 and referred the same note in 40 pin QFN corresponding to CYPD1122 40LQXI Added Note 23 and referred the same note in 40 pin QFN corresponding to CYPD1134 40LQXI B 4569912 SJH 11 21 2014 Updated Features Added 16 pin SOIC related information Updated Functional Definition Updated Pin Definitions Added Table 2 Updated Pinouts Updated Figure 2 Figure 4 Added Figure 3 Updated Power Updated Figure 5 Figure 8 Added Figure 6 Updated Electrical Specifications Updated Device Level Specifications Updated Memory Added Note 10 and referred the same note in Frey parameter Added details corresponding to spec ID SID182B under Frey parameter Updated Figure 14
6. SID61 VoL Output voltage low level 0 6 V loy 4 mA at 1 8 V Vppp SID62 VoL Output voltage low level 0 6 V Jo 8 mAat3 V VDDD SID62A VoL Output voltage low level 0 4 V loL 3 mAat3 V VDDD SID63 RpuLLUP Pull up resistor 3 5 5 6 8 5 kQ SID64 RPULLDOWN Pull down resistor 3 5 5 6 8 5 kQ SID65 lu Input leakage current absolute value SS m 2 0 nA 25 C Vppp 3 0 V Note 8 Vi must not exceed Vppp 0 2 V Document Number 001 93639 Rev E Page 15 of 34 ies PRELIMINARY CCG1 Datasheet e PERFORM Table 7 I O DC Specifications continued T Details Spec ID Parameter Description Min Typ Max Units Conditions SID65A liL CTBM Input leakage current absolute value 4 0 nA B for analog pins SID66 Cin Input capacitance 7 0 pF SID67 VuvsTTL Input hysteresis LVTTL 15 0 40 0 mV Vppp 2 2 7 V Guaranteed by characterization SID68 Vuyscmos Input hysteresis CMOS 200 0 mV Vppp 2 4 5 V Guaranteed by characterization SID69 IDIODE Current through protection diode to 100 0 pA Guaranteed by Vpp Vss characterization SID69A lror GPIO Maximum Total Source or Sink Chip 200 0 mA Guaranteed by 7 Current characterization Table 8 I O AC Specifications Guaranteed by Characterization Details Spec ID Parameter Description Min Typ Max Units Conditions SID70 TRISEF Rise ti
7. Ta 16 SOIC Operating ambient temperature 40 25 00 105 C Ty 16 SOIC Operating junction temperature 40 120 C TJA Package 0JA 40 pin QFN 15 34 C Watt TJA Package 0JA 35 CSP 28 00 C Watt TJA Package 0JA 16 SOIC 85 00 C Watt Tje Package 0Jc 40 pin QFN 02 50 C Watt Te Package OC 35 CSP 00 40 C Watt Tje Package 0Jc 16 SOIC 49 00 C Watt Table 24 Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature 16 pin SOIC 260 C 30 seconds 40 pin QFN 260 C 30 seconds 35 ball WLCSP 260 C 30 seconds Table 25 Package Moisture Sensitivity Level MSL IPC JEDEC J STD 2 Package MSL 16 pin SOIC MSL 3 40 pin QFN MSL 3 35 ball WLCSP MSL 1 Document Number 001 93639 Rev E Page 28 of 34 Wwe s PRELIMINARY CCG1 Datasheet PERFORM Figure 16 40 pin QFN Package Outline 001 80659 TOP VIEW SIDE VIEW BOTTOM VIEW 6 00 0 10 PIN 1 ID 40 31 re 0 08 1 O 30 4 30 Ch H D i po d D CT PIN 1 DOT 2 1 KS c i E 0 05 g u 2 D ac 0 07 d 2 C 5 Su d D C 10 2 ar Cho J hnannnanng 11 20 0 05 MAX 20 am wel aseo dax 4 60 0 10 NOTES 1 Ry HATCH AREA IS SOLDERABLE EXPOSED PAD 2 REFERENCE JEDEC MO 248 3 PACKAGE WEIGHT 68 2 mg 001 80659 4 ALL DIMENSIONS ARE IN MILLI
8. 51 85068 E Document Number 001 93639 Rev E Page 30 of 34 PERFORM Acronyms Table 26 Acronyms Used in this Document PRELIMINARY CCG1 Datasheet Table 26 Acronyms Used in this Document continued Acronym Description ADC analog to digital converter API application programming interface ARM advanced RISC machine a CPU architecture CC Configuration Channel CPU central processing unit CRC cyclic redundancy check an error checking protocol CS Current Sense DFP downstream facing port DIO digital input output GPIO with only digital capabilities no analog See GPIO EEPROM electrically erasable programmable read only memory EMI electromagnetic interference ESD electrostatic discharge FPB flash patch and breakpoint FS full speed GPIO general purpose input output applies to a PSoC pin IC integrated circuit IDE integrated development environment C or IIC Inter Integrated Circuit a communications protocol ILO internal low speed oscillator see also IMO IMO internal main oscillator see also ILO UO input output see also GPIO DIO SIO USBIO LVD low voltage detect LVTTL low voltage transistor transistor logic MCU microcontroller unit NC no connect NMI nonmaskable interrupt NVIC nested vectored interrupt controller Document Number 001 93639 Rev E
9. Pinout SWD_CLK VBUS_P_CTRL VBUS_VMON VBUS_VREF CC_VREF ET 9 GPIO ISCONNEC w wu wv SOIC Top View CC1 RX ee a d m NNECT J SWD IO cc VSEL2 VSEL1 cs CC_CTRL CC_VREF VBUS_DISCHARGE VSSA O 4 S Document Number 001 93639 Rev E CCG1 Datasheet Page 11 of 34 PERFORM Power The following power system diagram shows the minimum set of power supply pins as implemented for the CCG1 The system has one regulator in Active mode for the digital circuitry There is no analog regulator the analog circuits run directly from the VDDA input There is a separate regulator for the Deep Sleep mode There is a separate low noise regulator for the bandgap The supply voltage range is 1 8 to 5 5 V with all functions and circuits operating over that range The CCG1 is powered by an external power supply that can be anywhere in the range of 1 8 to 5 5 V This range is also designed for battery powered operation For example the chip can be powered from a battery system that starts at 3 5 V and works down to 1 8 V In this mode the internal regulator of the CCG1 supplies the internal logic and the VCCD output of the CCG1 PRELIMINARY CCG1 Datasheet must be bypassed to ground via an external capacitor in the range of 1 to 1 6 uF X5R ceramic or better No voltage source should be applied to this pin VDDA and VDDD must be shorted together the ground
10. VBUS VMON Analog input P1 0 35 l VBUS Over voltage Protection monitoring signal VBUS_VREF Analog input P1 1 36 l VBUS reference signal for Over voltage Protection detection VBUS P CTRL Active HIGH Strong drive Push P1 2 37 O Full rail control signal for Pull enabling disabling Provider load FET HOTPLUG_DE Active HIGH Open drain drives low P1 3 38 10 HotPlug Detection for Display Port T Alternate Mode CC_VREF VBU Active High Analog input Strong P1 4 39 IO Data reference signal for CC lines S_DISCHARGE drive Push Pull Document Number 001 93639 Rev E Signal used for discharging VBUS line during voltage change Page 8 of 34 PRELIMINARY CCG1 Datasheet E PERFORM Table 2 Pin Definitions for 40 Pin QFN for Notebook DFP continued PSoC4A Pane ena bin Se MICE Drive Mode Port for MOM Type Description 40 QFN MUXSEL 5 Open drain drives low P1 7 40 Oo External Data Mux Select signal 5 Document Number 001 93639 Rev E Page 9 of 34 PERFORM Following is the pin definition for 16 pin SOIC for the Power Adapter application Refer to Table 22 for part numbers to package mapping PRELIMINARY Table 3 Pin Definitions for 16 pin SOIC for Power Adapter Application Functional Pin Name e Ce Type Description SWD_CLK 1 l SWD Clock VBUS_P_CTRL 2 O Full rail control signal for enabling d
11. l CC1 control 0 TX enabled z RX sense CC1_TX D7 O Configuration Channel 1 SWD_IO D1 UO SWD I O SWD_CLK C1 l SWD clock I2C_SCL B1 UO HHC clock signal I2C SDA B2 UO I C data signal XRES B6 l Reset VCCD AT POWER Regulated digital supply output Connect a 1 to 1 6 pF capacitor No external source should be connected VDDD C7 POWER Power supply for both analog and digital sections VSSA B7 GND Analog ground CC VREF C5 l Data reference signal for CC lines TX_U B3 O Signals for internal use only The TX_U output signal should be connected to the TX_M signal TX_M B5 l TX_REF_IN D3 l Reference signal for internal use Connect to TX_REF output via a 2 4K 1 resistor TX_GND A3 l Connect to GND via 2K 1 resistor TX_REF_OUT D4 O Reference signal generated by connecting internal current source to two 1K external resistors RA_DISCONNECT E4 O Optional control signal to remove RA after assertion of VCONN 0 RA disconnected 1 RA connected VCONN_DET C6 l Local VCONN detection signal 0 VCONN is not locally applied 1 VCONN is locally applied CC1_LPREF AN l Reference signal for internal use Connect to the output of resistor divider from VDDD RA_FAR_DISCONNECT E5 O Optional control signal to remove RA after assertion of VCONN NC for 2 chip cable 0 RA disconnected 1 RA connected BYPASS D5 l Bypass capacitor for internal analog circuits CC1_LPRX C3 l Configuration channel 1 RX signal for Low Power States GPIO A1 A2 A4 A6 General purpose I Os B4
12. 00 1 1 6nF L UM 1 Embedded ERE h Controller u QU 56ko 5 lac cc E CC2 mp pel 9 RP a Larl dek ES 22kO 5 a Got B uU K cc2RP15 V SEH Ge 10kQ 5 30 i lt 29 21 XRES 58 2928 2 gg CC2RP30 AAN Lab us 0 1uF L 98 8 os USB 23 5 kb a9 Chipset a T 5 Volts Hs i E MUXSEL_x HS SS 0 55 Vote 21 5kQ 1 DP SBU DisplayPort E Di VBUS_DISCHARGE 265kQ 1 Seo MM Lines Chipset 7 DP2 3 gt AUX Mux AUX Page 25 of 34 CYPRESS PERFORM PRELIMINARY CCG1 Datasheet Figure 15 Monitor Application Block Diagram VBUS DC Input pu ues EE PFET 4 s s D c 5W g 5 100kKQ 1 E 5 Volis I 1002 1 1W ge 1 o d Laus Deruaper ZE NFET 9 8 s ves EE 350 hs cs P 0 20 196 am d CS M REG VDDD 5V 10kO 1 C Se VBUS_ s u TI DISCHARGE 4 Deeg 33 432 op tis j35 36 24 7 a Bd wW e IS el 848 e ow E sy Jel e 5 amp ze im ES ERU i E4 ES ER i Rp 10kQ E 5 ag z 23 PA e Cs P 5 2 ga 6 C a a gt o a z OI CS M gt 2 2 Rd Dot NFET VSEL1 S SEH sup ed SlvsEL2 GPIO1 o 9900 1 Ei pl 1 l6 sELIGPIO2 CC VDDD IFAULT GPIO3 ci VBUS_C_CTRLIVBUS_OK 1202 1 t7nE 3 Type C CC1_CTRU Receptacle IMUXSE
13. 34 B7 GND Analog ground pin VBUS_VMON 35 35 C4 l VBUS Overvoltage Protection monitoring signal VBUS_VREF 36 36 C5 l VBUS reference signal for Overvoltage Protection detection VSEL1 37 37 C6 O Voltage Select signal 1 for selecting the output voltage VBUS_C_CTRL 38 D7 O Full rail control signal for enabling disabling Consumer load FET VBUS_OK 38 VBUS_OK 1 VBUS Voltage ok VBUS_OK 0 VBUS Overvoltage detected CC_VREF 39 39 D4 l Data reference signal for CC lines VBUS_P_CTRL 40 40 E7 O Full rail control signal for enabling disabling Provider load FET Document Number 001 93639 Rev E Page 6 of 34 PERFORM PRELIMINARY CCG1 Datasheet Following is the pin definition for 40 pin QFN for Notebook DFP application Refer to Table 22 for part numbers to package mapping Table 2 Pin Definitions for 40 Pin QFN for Notebook DFP A S E PSoC4A rune oral Pin aah at Drive Mode Port for aoe Type Description 40 QFN MUXSEL_1 Open drain drives low P2 0 1 Oo External Data Mux Select signal 1 MUXSEL 2 i Open drain drives low P2 1 2 Oo External Data Mux Select signal 2 CC1 CTRL Analog input Strong P2 2 10 CC1 control drive push pull 0 Tx enabled z RX sense CC2_CTRL Analog input Strong P2 3 4 IO 8 drive push pull CC2 control 0 TX enabled z RX sense MUXSEL_3 Open drain drives low P2 4 5 Oo External Data Mux Select sign
14. D l Wns C PERFORM General Description YPRESS PRELIMINARY CCG1 Datasheet USB Type C Port Controller with Power Delivery CCG1 provides a complete USB Type C and USB Power Delivery port control solution The scalable and reconfigurable core architecture of CCG1 enables a base Type C solution that can scale to a complete 100 W USB Power Delivery with Alternate Mode mux support CCG1 is also a Type C cable ID IC for active and passive cables The ARM Cortex MO CPU based core can use common open source firmware or custom solutions developed with common libraries and APIs CCG1 is the CC controller that detects connector insert plug orientation and Vconn switching signals CCG 1 makes it easier to add USB Power Delivery to any architecture because it provides the control signals to manage external VBUS and Vconn power management solutions as well as external mux controls for most single cable docking solutions CCG1 s packaging options and programmability enables any USB Type C and USB Power Delivery solution Applications m Notebooks tablets monitors docking stations m Power adapters USB Type C cables Features 32 bit MCU Subsystem m 48 MHz ARM Cortex MO CPU with 32 KB flash and 4 KB SRAM Integrated analog blocks m 12 bit 1 Msps ADC for VBUS voltage and current monitoring m Dynamic overcurrent and overvoltage protection Integrated digital blocks m Two configurable 16 bit TCPWM blocks m One DC master or s
15. DC Specifications Guaranteed by Design Spec ID Parameter Description Min Typ Max Units Details Conditions SID218 weu IMO operating currentat48 MHz 1000 0 pA Table 19 IMO AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID223 FiuoroL1 Frequency variation 7 2 0 With API called calibration SID226 TsrARTIMO IMO startup time 12 0 US SID229 T JITRMSIMO3 RMS Jitter at 48 MHz 139 0 ps Internal Low Speed Oscillator Table 20 ILO DC Specifications Guaranteed by Design Spec ID Parameter Description Min Typ Max Units Details Conditions SID231 liLo1 ILO operating current at 32 kHz 0 30 1 05 pA Guaranteed by characterization SID233 li oiEAK ILO leakage current 2 0 15 0 nA Guaranteed by design Table 21 ILO AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID234 Tstartio ILO startuptime 20 ms Guaranteed by characterization SID236 Ti opurv ILO duty cycle 40 0 50 0 60 0 Guaranteed by characterization SID237 Eu ern 32 kHz trimmed frequency 15 0 32 0 50 0 kHz 60 with trim Document Number 001 93639 Rev E Page 19 of 34 ER Z PRELIMINARY CCG1 Datasheet CYPRESS PERFORM Applications in Detail Figure 8 Single Chip Cable Component Count 719
16. E Page 22 of 34 PRELIMINARY CCG1 Datasheet PERFORM Figure 12 16 pin SOIC Power Adapter Application Diagram PFET 5 20 Volts DMG7401SFG 7 From Secondary s 4 VBUS side 100k G 10k 100k1 4our l 100ohms 10k1 i NFET id MGSF1NO3L abe d 0 1uF Sense 33v Resistor on La NFET D the return VBUS DISCHARGE MGSF1NO3L E MGSF1NO3LT1G a path of S Secondary Hw Rsense 4 100k 10mohm I L O 1uF 1uF l I I 57k1 L 36 8 2 3 d VBUS_DISCHARGE aa J z u 1uF O Q a H oa E E ks 5 9 sz St 3 3v E al E E 12 2 A a 21 5k1 cs m z gt VBUS DISCHARGE 10 To CC VREF VBUS VSEL1 VSEL2 Primary E 0 55 Volts 43K 1 L Side 5V o H 13 lt anl CYPD1132 16SXI ww o 7 lt 4 Wece10 16SOIC T sa 3 o i up Io RPS 47k 5 wo 7 swD CLK 26501 5 cc 5 I XRES 330pF 15001 1 et I SR 0 1uF cc crm i VSSD VSSA F 9 Document Number 001 93639 Rev E Page 23 of 34 PRELIMINARY CCG1 Datasheet
17. Figure 13 Figure 15 Added Figure 12 and Figure 14 Updated Ordering Information Updated part numbers Added a column Si ID Updated Packaging Updated Table 23 Updated details in maximum value column corresponding to T4 and Ty parameters Added 16 pin SOIC related information Updated Table 24 C 4596141 SJH 12 14 2014 Updated Figure 6 Figure 14 Figure 16 Updated Table 7 Table 22 D 4646123 SJH 02 04 2015 Updated pin definitions for 40 pin QFN and 35 ball WLCSP Updated 40 pin QFN Pinout Updated conditions for Device Level Specifications Updated diagrams in Applications in Detail section Updated Ordering Information E 4686050 VGT 03 13 2015 Document Number 001 93639 Rev E Removed information about 28 pin SSOP Updated Table 2 Table 22 Table 23 Table 24 Table 25 Table 26 Updated Figure 2 Figure 5 Page 33 of 34 X PRELIMINARY CCG1 Datasheet PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at Cypress Locations Products PSoC Solutions Automotive cypress com go automotive psoc cypress com solutions Clocks amp Buffers cypress com go clocks PSoC 1 PSoC 3 PSoC 4 PSoC 5LP Interface cypress com go interface Cypress Develo
18. K CC1LPRX P P K S cf NTNS3164NZ D cc CC SuperSpeed and HighSpeed Lines GND Document Number 001 93639 Rev E Page 21 of 34 E PRELIMINARY CCG1 Datasheet SS SSS TERR LZ de SS SaaS sas CYPRESS Zi LT Kee ee PERFORM Figure 10 Two Chip Cable Component Count 15 paddle Type C Plug Type C PI ype C Plug VBUS VBUS a VCONN 1 Seege T Don prs A hom T o 20kQ 1 100kQ 1 20k 1 100kQ 1 af 28k3796 MT ge fe 28k3796 tk bea i i wl 1k 5 b 1 I 5 li A5 C7 A5 c7 i 1 CCiLPREF VDDD A1 A2 A4 AG B4 C2 D2 CCiIPREF VDDD Ai A2 A4 A6 B4 C2 D2 cpio D Et E2 E3 E6 E7 GPio _D6 E1 E2 E3 E6 E7 _ 6 VCONN_DET C6 CONN DET D4 D4 A E nA DISCONNECT PER QUT ika i EMRA DISCONNECT IECH 1k 1 _E5 RA_FAR_DISCONNECT cc vneR C 22nfl 22 4k 1 _E5IRA FAR DISCONNECT cc vnEr C5 nt 2 2 4k 1 A3 2k 1 1k1 ls 2k1 21k 1 CYPD1103 35FNXi TX GND 1 i ET CYPD1103 35FNxi TX GND i 9 XRES 35CSP TX REF iN P XRES 35CSP TX REF IN P3 ATpF B5 ATpF B5 D5 BYPASS BN D5 BYPASS TAM TX
19. L_1 IMUXSEL_2 10ko cc2 MUXSEL 3 wuxseca CYPD1122 40LQXI S IMUXSEL_5 40QFN og s PFET CC2 VCONN CTRI EMT 3900 1 NFET 26 cc2 SIAS oor L 21 E pl a DEV_DET 1200 1 21 7nF LL I I Embedded swo_10 4 SC Controller SWwD_CLK CC2 CTRL d i sc rat W tzc SDA P Rp ei L 20 c INT D CC2 RP p c DAC gt 27 Rd Yoe 30 RES 28 o CC2 RD i O 1uF 22 SI HS tA us S ba 39 USB 5 Volts Chipset ale MUXSEL_x ak ss D 7 HS SS Volts 21 50k2 1 DP SBU 1 Senn Lines mu e men 2 65k2 1 DP2 3 HS SS DP isplayPor Chipset 4 amp 7 DPO0 1 2 3 Ss ux Le aux Document Number 001 93639 Rev E Page 26 of 34 PERFORM Ordering Information PRELIMINARY The CCG1 part numbers and features are listed in the following table Table 22 CCG1 Ordering Information CCG1 Datasheet 11 er Type C Overcurrent Overvoltage Terminati 14 Part Number Application Bon lmeratecion allerotection E Role Package Si ID CYPD1103 35FNXIT Cable EMCA 1 No No RJ Cable 35 NLCSP 8 0490 CYPD1131 35FNXIT Notebook 1 Yes Yes RJ Ral DRP2 I35 wi CSP SI 0491 Tablet Smartphone CYPD1121 40LQXI Monitor 1 Yes Yes RJ R71 pRPPOI 40 QFN A 0489 CYPD1122 40LQXI Notebook 1 Yes Yes RJ R71 DRPPOI 40 QFNP1 048A CYPD1134 40LQXI Notebook 1 Yes Yes SA DER 49 QENE I 048B Desktop CYPD1132 168XI PowerAdapter 1 Yes Yes RI DER 16 SOIC 0498 CYPD1132 168XQ Power Adapter 1 Ye
20. MCU subsystem which is optimized for low power operation with extensive clock gating It mostly uses 16 bit instructions and executes a subset of the Thumb 2 instruction set This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex M3 and M4 thus enabling upward compatibility The Cypress implementation includes a hardware multiplier that provides a 32 bit result in one cycle It includes a nested vectored interrupt controller NVIC block with 32 interrupt inputs and a Wakeup Interrupt Controller WIC The WIC can wake the processor up from the Deep Sleep mode allowing power to be switched off to the main processor when the chip is in the Deep Sleep mode The Cortex MO CPU provides a Non Maskable Interrupt NMI input which is made available to the user when it is not in use for system functions requested by the user The CPU also includes a debug interface the serial wire debug SWD interface which is a 2 wire form of JTAG the debug configuration used for CCG1 has four break point address comparators and two watchpoint data comparators Flash The CCG1 device has a flash module with a flash accelerator tightly coupled to the CPU to improve average access times from the flash block The flash block is designed to deliver 1 wait state WS access time at 48 MHz and 0 WS access time at 24 MHz The flash accelerator delivers 85 of single cycle SRAM access performance on av
21. METERS The center pad on the QFN package should be connected to ground VSS for best mechanical thermal and electrical performance If not connected to ground it should be electrically floating and not connected to any other signal Figure 17 35 Ball WLCSP Package Outline 001 93741 TOP VIEW SIDE VIEW BOTTOM VIEW 5 Bex 123456 7 76543241 Heel i Co 7 B b j doe core B c l T E e D D E 1 1 r 3 CE E eech ag Ce nu NOTES 1 REFERENCE JEDEC PUBLICATION 95 DESIGN GUIDE 4 18 2 ALL DIMENSIONS ARE IN MILLIMETERS 001 93744 Document Number 001 93639 Rev E Page 29 of 34 PRELIMINARY CCG1 Datasheet PERFORM Figure 18 16 pin SOIC 150 Mils 16 15 SZ16 15 Package Outline 51 85068 PIN 1 ID 8 NOTE 1 DIMENSIONS IN INCHESEMM MAX B 2 REFERENCE JEDEC MS 012 015703987 3 PACKAGE WEIGHT refer to PMDD spec 001 04308 0230 5842 0 244 6 197 PART S1615 STANDARD PKG SZ1615 LEAD FREE PKG 9 16 0 386 9 8041 0 010 0 2541 i i 0 016 0 4061 0 393 9 982 SEATING PLANE RW e 0 06101 549 0 068 1 7271 A 4 i Cy o004t01023 T 0 05071 2701 BSC i 0 016 0 406 Mee tod 0 013800 350 0 004101021 0 03510 8891 0 019210 4871 0 0098 0 2491 X 45
22. Notebook DFP continued CCG1 Datasheet 3 PSoC4A Functional Pin Active HIGH 40 QFN NC Drive Mode Port for Type Description Name LOW 40 QFN 3 Pins CC2 RP 3 0 Active HIGH Open drain drives P4 3 21 O Open Source signal to connect high RP to CC2 line 3A current z RP not connected 1 RP connected CC1_LPRX Analog input P0 0 22 Configuration channel 1 RX signal for Low Power States CC1 LPREF Analog input PO 1 23 Reference signal for internal use CC2 LPRX Analog input P0 2 24 l Configuration channel 2 RX signal for Low Power States CC2_LPREF Analog input P0 3 25 Reference signal for internal use CC2 Sun drive push P0 4 26 O Configuration Channel 2 pu CC1_VCONN_ Active LOW Open drain drives low P 5 27 Oo Open Drain signal to control a CTRL PFET power switch for VCONN on CC1 line 0 VCONN switch closed z VCONN switch open CC2 VCONN Active LOW Open drain driveslow p0 6 28 O Open Drain signal to control a CTRL PFET power switch for VCONN on CC2 line 0 VCONN switch closed z VCONN switch open IFAULT Active HIGH Digital input P0 7 29 Current Fault Indication on VBUS 0 No fault 1 Over Current fault XRES Active LOW Analog input XRES 30 l Reset VCCD 2 VCCD 31 POWE Connect 1uf Capacitor between R VCCD and Ground VDDD S VDDD 32 ide 5 V Supply VDDA S VDDA 33 P SV Supply VSSA VSSA 34 GND E PAD a E PAD E PAD GND
23. U TX u BS Lm Sal 220 5 1UF an pz 220 556 CCD CC1 TX CCD CC1 TX B7 BE BT vssA c4 pe GC swD_swD_ CC RXC po GC SWD SWD CC1_RX SCL SDA IO CLK CC1LPRX SCL SDA IO OK cci LPRX CS P P P P P P P P J s S NTNS3164NZ elk NTNS3164NZ cc E cc f SuperSpeed and HighSpeed Lines SuperSpeed and HighSpeed Lines La GND ve 4 Figure 11 Two Chip Cable Component Count 11 paddle Type C Plug Type C Plug VBUS VBUS YP VCONN 1 VOONNS dk es Ra val dul 5 FRA l I H Las c7 Je Ic7 j CC1_LPREF VDDD A1 A2 A4 A6 B4 C2 D2 CC1_LPREF VDDD A1 A2 A4 A6 B4 C2 D2 cpio 28 Et E2 E3 E6 E7 GPio _D6 E1 E2 E3 E6 E7 C6 VCONN_DET bi 8 vcoNN DET TX REF our roum E RA DISCONNECT De DS Dina DISCONNECT iR 21k 1 E5 RA_FAR_DISCONNECT cc vnERC antl 24k19 ES RA FAR DISCONNECT cc vREFCS 22nf 224k 1 A3 2k 1 2 1k1 lng 2k 1 1k 1 B6 CYPD1103 35FNxi TX GND 1 H A CYPD1103 35FNXI TX GND 1 i 9 XRES 35CSP Tx REF WU XRES 35CSP TX REF WI 47pF RE B5 ATpF m B5 TX M DS pypass XM DSI BYPASS E 1UF A7 les 220 5 1UF A TEM ks 220 5 MCCD CC1 TX VW veco CC1 TX B7 B7 lyssa Ce TXEN SA VSSA cc1 TXEN S4 pe GC SWD SWD CC RXc IC GC SWD SWD CC1_RXI SCL SDA lO CLK CC1 LPRX scl SDA IO CLK cci LPRX C2 P P li P F li D P J d oj NTNSS164NZ sje NTNS3164NZ 5j cc 5 cc Apt SuperSpeed and HighSpeed Lines SuperSpeed and HighSpeed Lines YP GND one SL Document Number 001 93639 Rev
24. Volts Fa I ss MUXSEL_x DES HS SS Volte 21 5kO 1 DP SBU DisplayPort By 265kQ 19 pod Bit Chipset Z DO d DEUS FS l Z aux AUX Document Number 001 93639 Rev E Page 24 of 34 CYPRESS PERFORM PRELIMINARY CCG1 Datasheet Figure 14 Notebook DFP Application Diagram Document Number 001 93639 Rev E From 5v PFET VBUS D E g D I mem E 50KO E 0 020 1 5 100 1 oF Current Monitor e 1000 1 1W is A iFAULT NFET esp d E ver E 0 20 196 VBUS DISCHARGE s E w CSM 10k2 1 VDDD 5V oturL wur Jee E d D 31 33 32 37 35 36 27 1uF 1 a E E zi E hs 56kQ 5 NET 888 S CC RP DEFS AMV H RP 390pF 1 88 9 55 S Ge EEN 1 ROME Cca RP 15 11 AM 3 g B d 70a eg De a S LR ag AAA cS M M cs M 5 CC1 LPRX g E S 3900 1 cci AA il 29 1200 196 Sy cci iFAULT p iFAULT 121 get 3 Type C CC1 CTRL Receptacle at MUXSEL 1 10k 1 4 2 MUXSEL 2 CC2 VCONN ml cc2 lt q S5 muxse3 CYPD1134 40LQXI 7 ES Sen 4 S MUXSEL 4 40QFN 24 4 J NUXSEL 5 Gen MARS HPD S HOTPLUG DET ag 90019 HER cc2 ipi I S 390pF Benn 12
25. Y Contents Functional Definition eene 3 CPU and Memory Subsystem sees 3 System ResOoUrces irikirik trente ne 3 EE 3 Pin Definitions eene 4 dlc 11 Power 12 Electrical Specifications eee 14 Absolute Maximum Ratings ne 14 Device Level Specifications sssssss 14 Digital Peripherals 17 sia 18 System Resources sese 18 Applications in Detail eee 20 Document Number 001 93639 Rev E CCG1 Datasheet Ordering Information eee 27 Ordering Code Definitions eessssss 27 Packaging esee nennen nennen nnne 28 ACTONYIMS M 31 Document Conventions eene 32 Units of Measure ire erc nce 32 Revision History eere 33 Sales Solutions and Legal Information 34 Worldwide Sales and Design Support 34 laic e PSoC Solutions Cypress Developer Community ssssss 34 Technical Support esseee 34 Page 2 of 34 PERFORM Functional Definition CPU and Memory Subsystem PU The Cortex MO CPU in the CCG1 is part of the 32 bit
26. al 42 0 ns SID146 TPWMENEXT Enable pulse width external 42 0 ns SID147 Tpwmreswint Reset pulse width internal 42 0 ns SID148 TpPwMREswExr Reset pulse width external 42 0 ns C Table 11 Fixed I C DC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Conditions SID149 lc Block current consumption at 100 kHz 10 5 pA SID150 li2c2 Block current consumption at 400 kHz E x 135 0 pA SID151 li2c3 Block current consumption at 1 Mbps 310 0 pA SID152 li2c4 2C enabled in Deep Sleep mode 1 4 pA Table 12 Fixed I C AC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Conditions SID153 Fioc4 Bit rate 1 0 Mbps Document Number 001 93639 Rev E Page 17 of 34 PERFORM PRELIMINARY CCG1 Datasheet Memory Table 13 Flash DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID173 Vpg Erase and program voltage 1 8 5 5 V Table 14 Flash AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID174 Trowwrrte Row block write time erase 200 ms Row block 128bytes and program SID175 Trowerase Rowerae
27. al 3 MUXSEL 4 Open drain drives low P2 5 6 O External Data Mux Select signal 4 CS P Analog input P2 6 7 l Current Sensing Plus input CS_M Analog input P2 7 8 Current Sensing Minus input VSS s VSS 9 GND Ground CC1 a drive push P3 0 10 Oo Configuration Channel 1 pu CC1 RP 1 5 Active HIGH Open drain drives P3 1 11 O Open Drain signal to connect RP high to CC1 line 1 5A current z RP not connected 1 RP connected SWD IO E P3 2 12 IO SWD IO SWD CLK P3 3 13 l SWD Clock CC1_RP_3 0 Active HIGH Open drain drives P3 4 14 Oo Open Source signal to connect high RP to CC1 line 3A current z RP not connected 1 RP connected CC1 RP DEF Active HIGH Open drain drives P3 5 15 Oo Open Drain signal to connect RP high to CC1 line Default current z RP not connected 1 RP connected CC2 RP DEF Active HIGH Open drain drives P3 6 16 Oo Open Drain signal to connect RP high to CC2 line Default current z RP not connected 1 RP connected CC2 RP 1 5 Active HIGH Open drain drives P3 7 17 Oo Open Drain signal to connect RP high to CC2 line 1 5A current z RP not connected 1 RP connected DC SCL Active LOW Open drain drives low P4 0 18 IO 12C Clock signal DC SDA Active LOW Open drain drives low P4 1 19 IO CC Data signal DC INT Active LOW Open drain drives low p4 2 20 O GC Interrupt Document Number 001 93639 Rev E Page 7 of 34 PERFORM PRELIMINARY Table 2 Pin Definitions for 40 Pin QFN for
28. all WLCSP Example NZ VSS VDDD VDDA 0 1 uF C2 EE C1 1yF NZ VSS WVZ Document Number 001 93639 Rev E VCONN CC VR DET EF VCCD GPIO o GPIO C3 1 uF WY VSS XRES TX M oum E cu m X e TX REF TX REF _OUT IN GPIO dq SWD C SWD 1 Page 13 of 34 ER Z PRELIMINARY CCG1 Datasheet PERFORM Electrical Specifications Absolute Maximum Ratings Table 4 Absolute Maximum Ratings E Details Spec ID Parameter Description Min Typ Max Units condones SID1 Vppp ABS Digital supply relative to Vssp 0 5 6 0 V Absolute max SID2 Vccp ABS Direct digital core voltage input relative 0 5 1 95 V Absolute max J to Vssp SID3 VGPiO ABS GPIO voltage 0 5 Vppp 0 5 V Absolute max SIDA IGPIO_ABS Maximum current per GPIO 25 0 25 0 mA Absolute max SID5 IGPIO injection GPIO injection current Max for Vip gt 0 50 0 5 mA Absolute max i Vppp and Min for Vu lt Vss current injected per pin BID44 ESD HBM Electrostatic discharge human body 2200 V model BID45 ESD CDM Electrostatic discharge charged device 500 V model BID46 LU Pin current for latch up 200 200 mA Device Level Specifications All specifications are valid for 40 C x T4 lt 85 C and Tx 100 C for 35 CSP and 40 QFN package options Specifications are valid for 40 C lt Ta lt 105 C and T 120 C for 16 SOIC package options Spe
29. cifications are valid for 1 8 V to 5 5 V except where noted Table 5 DC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SID53 Vppp Power supply input voltage 1 8 5 5 V With regulator enabled SID54 Vccp Output voltage for core logic 1 8 V SID55 Cerc External regulator voltage bypass 1 0 1 3 1 6 uF X5R ceramic or better SID56 CExc Power supply decoupling capacitor 1 0 uF X5R ceramic or better Active Mode Vppp 1 8 to 5 5 V Typical values measured at Vpp 3 3 V SID19 Ipp14 Execute from flash CPU at 48 MHz 12 8 m mA T 25 C SID20 Ipp15 Execute from flash CPU at 48 MHz 13 8 mA Sleep Mode Vppp 1 8 to 5 5 V SID25A Ipp20A 12C wakeup and comparators on 1 7 2 2 mA Deep Sleep Mode Vppp 1 8 to 3 6 V Regulator on SID31 Ipp26 Fe wakeup on 1 3 pA T 225 C 3 6V SID32 Ipp27 DC wakeup on 50 0 pA T 85 C Deep Sleep Mode Vppp 3 6 to 5 5 V SID34 Ipp29 c wakeup 15 0 pA T 25 C 5 5 V Note 7 Usage above the absolute maximum conditions listed in Table 4 may cause permanent damage to the device Exposure to absolute maximum conditions for extended periods of time may affect device reliability The maximum storage temperature is 150 C in compliance with JEDEC Standard JESD22 A103 High Temperature Storage Life When used below absolute maximum conditions but above normal operating con
30. d for various functions Refer to the pinout tables for the definitions The GPIO block implements the following m Eight drive strength modes a Analog input mode input and output buffers disabled a Input only a Weak pull up with strong pull down a Strong pull up with weak pull down a Open drain with strong pull down a Open drain with strong pull up a Strong pull up with strong pull down a Weak pull up with weak pull down m Input threshold select CMOS or LVTTL m Individual control of input and output buffer enabling disabling in addition to the drive strength modes m Hold mode for latching previous state used for retaining I O state in Deep Sleep mode m Selectable slew rates for dV dt related noise control to improve EMI During power on and reset the I O pins are forced to the disable state so as not to crowbar any inputs and or cause excess turn on current A multiplexing network known as a high speed UO matrix is used to multiplex between various signals that may connect to an I O pin Page 3 of 34 ER Z PRELIMINARY CCG1 Datasheet PERFORM Pin Definitions Following is the pin definition 1 for 35 Ball WLCSP for the Cable EMCA application Refer to Table 22 for part numbers to package mapping Table 1 Pin Definitions for 35 ball WLCSP for EMCA Cable Application Functional Pin Name SE Type Description CC1 RX C4
31. ditions the device may not operate to specification Document Number 001 93639 Rev E Page 14 of 34 Se 4 PRELIMINARY CCG1 Datasheet Table 5 DC Specifications continued Details Spec ID Parameter Description Min Typ Max Units Conditions XRES Current SID307 Jop xR Supply current while XRES asserted 2 0 5 0 mA Table 6 AC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SID48 Fopu CPU frequency DC 48 0 MHz 1 8 lt Vpp lt 5 5 SID49 TsiEEP Wakeup from sleep mode 0 US Guaranteed by characterization SID50 TpEEPSLEEP Wakeup from Deep Sleep mode 25 0 US 24 MHz IMO Guaranteed by characterization SID52 TresetwiptH External reset pulse width 1 0 Hs Guaranteed by characterization VO Table 7 I O DC Specifications Spec ID Parameter Description Min Typ Max Units C pele e SID57 Vy Input voltage high threshold 0 7 x V CMOS Input VDDD SID58 Vu Input voltage low threshold 0 3 x V CMOS Input VDDD SID241 Vull LVTTL input Vppp lt 2 7 V 0 7x V VDDD SID242 Vu LVTTL input Vppp lt 2 7 V 0 3 x V VDDD SID243 Vull LVTTL input Mopp 2 7 V 2 0 V SID244 Vu LVTTL input Mopp 2 7 V 0 8 V SID59 Vou Output voltage high level Vpp V lop 4 mA at 0 3 V Vppp SID60 Vou Output voltage high level Vppp V lou 1 mA at 0 5 1 8 V Vppp
32. erage Part of the flash module can be used to emulate EEPROM operation if required SROM A supervisory ROM that contains boot and configuration routines is provided 9 System Resources Power System The power system is described in detail in the section Power on page 12 It provides assurance that voltage levels are as required for each respective mode and either delay mode entry on power on reset POR for example until voltage levels are as required for proper function or generate resets Brown Out Detect BOD or interrupts Low Voltage Detect LVD The CCG1 operates with a single external supply over the range of 1 8 to 5 5 V and has three different power modes Active Sleep and Deep Sleep transitions between modes are managed by the power system Serial Communication Blocks SCB The CCG1 has one SCB which can implement an I C interface The hardware DC block implements a full multi master and slave interface it is capable of multimaster arbitration This block is capable of operating at speeds of up to 1 Mbps Fast Mode Plus and has flexible buffering options to reduce interrupt overhead and latency for the CPU It also supports EZ IC that creates a mailbox address range in the memory of the CCG1 and effec tively reduces 12C communication to reading from and writing to an array in memory In addition the block supports an 8 deep Document Number 001 93639 Rev E PRELIMINARY CCG1 Datasheet FIFO fo
33. eset or flash operations will be interrupted and cannot be relied on to have completed Reset sources include the XRES pin software resets CPU lockup states and privilege violations improper power supply levels and watchdogs Make certain that these are not inadvertently activated 10 Cypress provides a retention calculator to calculate the retention lifetime based on customers individual temperature profiles for operation over the 40 C to 105 C ambient temperature range Contact customercare cypress com Document Number 001 93639 Rev E Page 18 of 34 PRELIMINARY CCG1 Datasheet PERFORM SWD Interface Table 17 SWD Interface Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID213 F SWDCLK1 3 3 V lt Vppp lt 5 5 V 14 0 MHz SWDCLK lt 1 3 CPU clock frequency SID214 F SWDCLK2 1 8 V lt Vppp lt 3 3 V 7 0 MHz SWDCLK s 1 3 CPU clock frequency SID215 T SWDI SETUP T 1fSWDCLK X 025 T ns Guaranteed by characterization SID216 T SWDI HOLD T 1 f SWDCLK 0 25 T ns Guaranteed by characterization SID217 T SWDO VALID T 1 f SWDCLK 0 5 T ns Guaranteed by characterization SID247A T SWDO HOLD T 1fSWDCLK 1 ns Guaranteed by characterization Internal Main Oscillator Table 18 IMO
34. ignal I2C INT 20 20 A2 O I2C Interrupt DEV_DET 21 21 A1 O Device detection signal indicating the attached device type CC1_RD 22 22 C3 O Open Drain signal to connect RD to CC 1 line z RD not connected 0 RD connected CC1_RP 23 23 A5 O Open Source signal to connect RP to CC 1 line z RP not connected 1 RP connected Document Number 001 93639 Rev E Page 5 of 34 ies PRELIMINARY CCG1 Datasheet e PERFORM 40 QFN 1 40 QFN 2 35 CSP 2 inn Functional Pins Pin Pin Balls Type Description CC1 VCONN CTRL 24 24 A4 O Open Drain signal to control a PFET power switch for VCONN on CC 1 line 0 VCONN switch closed z VCONN switch open VBUS_DISCHARGE 25 25 A3 O Signal used for discharging VBUS line during voltage change CC2 26 26 B3 O Configuration Channel 2 CC2_RD 27 27 A6 O Open Drain signal to connect RD to CC 2 line z RD not connected 0 RD connected CC2_RP 28 28 B4 O Open Source signal to connect RP to CC 2 line z RP not connected 1 RP connected CC2 VCONN CTRL 29 29 B5 O Open Drain signal to control a PFET power switch for VCONN on CC 2 line 0 VCONN switch closed z VCONN switch open XRES 30 30 B6 l Reset VCCD 31 31 AT POWER Regulated digital supply output Connect a 1 to 1 6 uF capacitor No external source should be connected VDDD 32 32 C7 POWER Power supply for digital sections VDDA 33 33 C7 POWER Power Supply for analog sections VSSA 34
35. isabling provider load FET VBUS_VMON 3 l VBUS over voltage protection monitoring signal VBUS_VREF 4 l VBUS reference signal for over voltage protection detection XRES 5 Active Low Reset VCCD 6 Connect 1 uF capacitor between VCCD and GROUND VSSD 7 Ground VDDD 8 Power 3 3 V 5 V VSSA 9 Ground CC_VREF VBUS_DISCHARG 10 UO Data reference signal for CC line 0 55 Volt Signal used for E discharging VBUS line during voltage decrease CC_CTRL 11 UO CC1 control 0 TX enabled z RX sense CS 12 l Low Side Current Sense VSEL1 13 O Voltage select signal for selecting the output voltage 5 12 20 V VSEL2 14 O Voltage select signal for selecting the output voltage 5 12 20 V CC 15 UO Configuration Channel TX RX SWD IO 16 UO SWD I O Document Number 001 93639 Rev E Page 10 of 34 CCG1 Datasheet VCONN_D PRELIMINARY Figure 2 40 pin QFN Pinout x 9 e 2 m 2 38 E Kuz O 5 x uo ju rz aWq Oss ot ou o al a nono IS uDdDH9QQ0 mOMMNMANHNH AADO 2025222522522 re WWW HHH SS SG SS AG gz MUXSEL_1 bai 30 XRES MUXSEL_2 fa 2 29 ei CC2_VCONN_CTRL CC1_CTRL i 3 28 m CC2 RP CC2 CTRL bai QFN 27 CC2 RD MUXSEL 3E 5 Top View 26 CC2 MUXSEL_4 fa 6 25 VBUS_DISCHARGE CS_P 7 24 CC1_VCONN_CTRL CS Mat 23 m CC1 RP vss 9 22m CC1 RD CC1 B 10 21 DEV DET e Sisi e Si Xf RH HHH HHH J 2aus8Sgae Boon gbg g a SOSSaSRERRS 3 o2 ol D a a u o E 550 ka Figure 3 16 pin SOIC
36. lave Type C Support m Integrated transceiver BB PHY m Supports up to two USB ports with PD m Supports routing of all protocols through an external mux PD Support m Supports Provider and Consumer roles m Supports all power profiles Low power operation m 1 8 V to 5 5 V operation m Sleep 1 3 mA Deep Sleep 1 3 uA Packages m 40 pin QFN m 16 pin SOIC m 35 ball wafer level CSP WLCSP Figure 1 CCG1 Block Diagram l 2 3 5 6 CCG1 USB Type C Port Controller with PD MCU Subsystem ARM CORTEX M0 48 MHz SRAM 4KB Serial Wire Debug Advanced High Performance Bus AHB Notes Timer counter pulse width modulation block Serial communication block configurable as PC Base band Termination resistor denoting a Downstream Facing Port DFP Termination resistor denoting a Upstream Facing Port UFP poA Gs NO Cypress Semiconductor Corporation Document Number 001 93639 Rev E Integrated Analog Blocks cc pi m RY na Control Integrated Digital Blocks TCPWM SCB Profiles and Configurations BB MAC BB PHY 198 Champion Court VO Subsystem Veus Control Vconn Control Voltage Select MUX Control Current Control FC Device Detect Programmable Interconnect and Routing LETS Sense Vconn Sense Termination resistor denoting an Electronically Marked Cable Assembly EMCA San Jose CA 95134 1709 408 943 2600 Revised March 13 2015 a PRELIMINAR
37. me 2 0 12 0 ns 3 3 V Vppp Cload 25 pF SID71 TFALLF Fall time 2 0 12 0 ns 3 3 V Vppp Cload 25 pF XRES Table 9 XRES DC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SID77 Vum Input voltage high threshold 0 7 x V CMOS input VDDD SID78 Vu Input voltage low threshold 0 3 x V CMOS input VDDD SID79 RPuLLUP Pull up resistor 3 5 5 6 8 5 kQ SID80 Cin Input capacitance 3 0 pF SID81 VHYSXRES Input voltage hysteresis 100 0 B mV Guaranteed by characterization SID82 IDIODE Current through protection diode to 100 0 pA Guaranteed by Vppp Vss characterization Document Number 001 93639 Rev E Page 16 of 34 PERFORM Digital Peripherals The following specifications apply to the Timer Counter PWM peripherals in the Timer mode PRELIMINARY CCG1 Datasheet Pulse Width Modulation PWM for VSEL and CUR_LIM Pins Table 10 PWM AC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Conditions SID140 TPwMFREQ Operating frequency 48 0 MHz SID141 TPWMPWINT Pulse width internal 42 0 7 ns SID142 TPWMEXT Pulse width external 42 0 ns SID143 TPWMKILLINT Kill pulse width internal 42 0 ns SID144 TpwMkILLExt Kill pulse width external 42 0 ns SID145 TPWMEINT Enable pulse width intern
38. per Community Power Control cypress com go powerpsoc Community Forums Blogs Video Training Memory cypress com go memory PSoC cypress com go psoc Technical Support Touch Sensing cypress com go touch cypress com go support USB Controllers cypress com go USB Wireless RF cypress com go wireless Cypress Semiconductor Corporation 2014 2015 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty pro
39. r receive and transmit which by increasing the time given for the CPU to read data greatly reduces the need for clock stretching caused by the CPU not having read data on time The IC peripheral is compatible with the I C Standard mode Fast mode and Fast mode Plus devices as defined in the NXP I C bus specification and user manual UM10204 The UC bus I O is implemented with GPIO in open drain modes The CCG1 is not completely compliant with the Ko spec in the following respects m GPIO cells are not overvoltage tolerant and therefore cannot be hot swapped or powered up independently of the rest of the Ke system m Fast mode Plus has an lo specification of 20 mA at a Vo of 0 4 V The GPIO cells can sink a maximum of 8 mA lo with a Vo maximum of 0 6 V m Fast mode and Fast mode Plus specify minimum Fall times which are not met with the GPIO cell Slow strong mode can help meet this spec depending on the Bus Load m When the SCH is an I C Master it interposes an IDLE state between NACK and Repeated Start the 2c spec defines Bus free as following a Stop condition so other Active Masters do not intervene but a Master that has just become activated may start an Arbitration cycle m When the SCB is in the I2C Slave mode and Address Match on External Clock is enabled EC AM 1 along with operation in the internally clocked mode EC OP 0 then its lc address must be even GPIO The CCG1 has 34 GPIOs which are configure
40. s VSSA and VSS must also be shorted together Bypass capacitors must be used from VDDD to ground The typical practice for systems in this frequency range is to use a capacitor in the 1 uF range in parallel with a smaller capacitor 0 1 uF for example Note that these are simply rules of thumb and that for critical applications the PCB layout lead inductance and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing Examples of bypass schemes follow Figure 5 40 pin QFN Example VDDD 1 uF CH Les C2 0 1 uF VSS 4 Os E Ediz E Reto O Os u a o 9 gt gt a o ioo 2712u22 C5 1 F a ma u 2988225 fe Err gt 8385 88S 885 MUXSEL_1 amp 1 lt lt OQA 309 XRES anoo MUXSEL Ze 2 9 A AO 294 CC2 VCONN CTRL VSS CC1_CTRLE 3 zz zz coo RP CC2 CTRLE 4 ER cco RD MUXSEL 3 amp 5 QFN MUXSEL_4 e Top Vi d BUE DISCHARGE cs Ph Top View 25 X cs 24 CC1 VCONN CTRL E 23 CC1_RP RSS CC1 RD CC1 fs 10 Em o De DEV DET DEENEN VSS Weg osno b dgoa59290 7 0200o2o0vooO9 ZS mz 2 ES a a z oF E o X SWD CLK 1 16 SWD IO VBUS P CTRLE2 15 et CC VBUS_VMON 3 soic 14 E VSEL2 4 18 e VSEL1 oe yur e MEDMER T cs vss tH 6 VCCD 11 m CC CTRL 7 VSSD 10 CC VREF VBUS DISCHARGE 8 VDDD 9 VSSA 0 1 uF C2 Document Number 001 93639 Rev E C11 pF VSS Page 12 of 34 PRELIMINARY PERFORM CCG1 Datasheet Figure 7 35 b
41. s Yes RI DER 16 SOIC 0498 Ordering Code Definitions CY PDX XXX XX XX X X T Tape and reel for CSP N A for other packages Temperature Range Industrial Q Extended industrial Lead X Pb free Package Type LQ QFN FN CSP S SOIC Number of pins in the package 0X OCP and OVP not supported 1X reserved 2X 3X OCP and OVP supported Number of Type C Ports 1 1 Port 2 2 Port Product Type 1 First generation product family CCG1 Marketing Code PD Power delivery product family Company ID CY Cypress Notes 11 All part numbers support Input voltage range from 1 8 to 5 5 V Industrial parts support 40 C to 85 C Extended Industrial parts support 40 C to 105 C 12 Number of USB Type C Ports Supported 13 Default Veonn Termination 14 PD Role 15 Type C Cable Termination 16 35 WLCSP 1 pinout 17 USB Device Termination 18 35 WLCSP 2 pinout 19 USB Host Termination 20 Dual Role Port 21 40 QFN 1 pinout 22 40 QFN 2 pinout 23 40 QFN 3 pinout 24 Downstream Facing Port Document Number 001 93639 Rev E Page 27 of 34 Wwe s PRELIMINARY CCG1 Datasheet PERFORM Packaging Table 23 Package Characteristics Parameter Description Conditions Min Typ Max Units Ta 40 QFN 35 CSP Operating ambient temperature 40 25 00 85 C Ty 40 QFN 35 CSP Operating junction temperature 40 100 C
42. se agreement Document Number 001 93639 Rev E Revised March 13 2015 Page 34 of 34 All products and company names mentioned in this document may be the trademarks of their respective holders
43. tim 130 ms SID176 TROWPROGRAM Row program time after erase 7 0 ms SID178 TBULKERASE Bulk erase time 32 KB 35 ms SID180 Tpevprog Total device program time 7 0 seconds Guaranteed by characterization SID181 Fenp Flash endurance 100K cycles Guaranteed by characterization SID182 Fre Flash retention TA x 55 C 20 years Guaranteed by characterization 100 K P E cycles SID182A Flash retention T4 x 85 C 10 years Guaranteed by characterization 10 K P E cycles SID182B Flash retention 85 C lt TA lt 3 years Guaranteed by characterization 105 C 10K P E cycles System Resources Power on Reset POR with Brown Out Table 15 Imprecise Power On Reset PRES Spec ID Parameter Description Min Typ Max Units Details Conditions SID185 VnisEipon Rising trip voltage 0 80 1 45 V Guaranteed by characterization SID186 VFALLIPOR Falling trip voltage 0 75 1 40 V Guaranteed by characterization SID187 Viponuvsr Hysteresis 15 0 200 0 mV Guaranteed by characterization Table 16 Precise Power On Reset POR Spec ID Parameter Description Min Typ Max Units Details Conditions SID190 VFALLPPOR BOD trip voltage in active and 1 64 SS V Guaranteed by characterization sleep modes SID192 VeattppsLp BOD trip voltage in Deep Sleep 1 40 V Guaranteed by characterization Note 9 Itcan take as much as 20 milliseconds to write to flash During this time the device should not be R
44. visions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software licen
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