Compact Flash Interface for the MPC8245
Contents
1. continued Interface Signal Description Type Pins PC Card eee ae Notes Memory D 15 0 Data bus VO 31 30 29 28 27 Common 3 49 48 47 6 5 4 3 2 23 22 21 INPACK Input acknowledge Oo 43 Common IORD I O read strobe 34 Common IOWR O write strobe 35 Common VS 1 2 Voltage sense O 33 40 Common WAIT IORDY Wait ready O 42 Common WE Write enable l 36 Common Unique Signals ATASEL IDE mode enable l 9 v OE Output enable v v REG Register select l 44 v v RESET Reset active high l 41 v v RESET Reset active low y IOIS16 IO0CS16 16 bit access O 24 v WP Write protect v v RDY BSY Ready busy O 37 v IREQ Interrupt request v INTRQ Interrupt request v BVD1 Bus voltage detect 1 0 46 v STSCHG Status changed v PDIAG Pass diag v BVD2 Bus voltage detect 1 0 45 v SPKR Speaker v DASP Disk active Slv Pr vy Power Vec Power 3 3 V 13 38 Common Compact Flash Interface for the MPC8245 Rev 2 Freescale Semiconductor 3 Preliminary Subject to Change Without Notice Interface Considerations Table 1 CF Device Connections continued Interface Signal Description Type Pins Notes PC Card pccard vO True IDE Memory Ground Ground 1 50 Common Notes 1 A3 A10 must be ground for IDE mode 2 CS CE are all chip select2. example reference designs available on the Freescale website Compact Flash Interface for the MPC8245 Rev 2 Freescale Semiconductor 15 Preliminary Subject to Change Without Notice How to Reach Us Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number AN2293 Rev 2 09 2006 Preliminary Subject to Change Without Noti
3. Type Mapping Benefits Costs Direct CS0 RCS2 Simple CS connections Needs logic to detect RCS2 RCS3 for CS1 RCS3 address data buffering Decoded CS0 RCS2 and MAO Logic needed for CS0 CS1 mapping Direct use of RCS for buffer enable CS1 RCS2 and MAO Compact Flash Interface for the MPC8245 Rev 2 Freescale Semiconductor 5 Preliminary Subject to Change Without Notice Chip Selects For direct CS connection typical connections for the chip selects and buffer controls are shown in Figure 2 MPC8245 CF Device Figure 2 Dual RCS Connections Dual RCS connections can be implemented with the following VHDL code or equivalent EN_B lt 0 WHEN RCS2_B 0 AND RCS3_B 0 ELSE 1 Single RCS controls are shown in Figure 3 MPC8245 CF Device CEO B lt 0 WHEN RCS2_B 0 AND MAO 0 ELSE 1 CE1 B lt 0 WHEN RCS2_B 0 AND MAO 1 ELSE 1 Since either selection typically requires a small amount of logic the choice is usually driven by other system design factors Compact Flash Interface for the MPC8245 Rev 2 6 Freescale Semiconductor Preliminary Subject to Change Without Notice Timing Issues 5 Timing Issues An important consideration of the CF interface is the AC timing both signal to signal relationships and the overall duration of signals Signal to signal relationships are maintained by proper programming of the Po
4. 64 in this example 5 2 Write Timing The write cycle is similar to the read cycle except a different control signal is used The write access timing waveform is shown in Figure 7 while the parameters and values are shown in Table 4 Compact Flash Interface for the MPC8245 Rev 2 10 Freescale Semiconductor Preliminary Subject to Change Without Notice Timing Issues A 2 0 lt gt HELIwL lt twLIwWH gt IOWR toviwH gt lt gt tlwHpx Figure 7 CF True IDE Mode Write Cycle Table 4 CF True IDE Mode Write Timing Timing Parameter Description Min Max Unit toviwH Data setup before IOWR 60 ns IWHDX Data hold following IOWR 30 z ns tiwLiwH IOWR width time 165 ns taVIWL Address setup before IOWR 70 ns tiwHax Address hold following IOWR 20 ns tELIWL CE setup before IOWR 5 ns IWHEH CE hold following IOWR 20 ns The restrictions on timing are very similar to that of the read path except that data must be present before IOWR is released For write cycles the interface logic is shown in Figure 8 MPC8245 CF Device MA 20 0 A 2 0 RCS 2 3 Figure 8 MPC8245 PortX to CF Write Interface Compact Flash Interface for the MPC8245 Rev 2 Freescale Semiconductor 11 Preliminary Subject to Change Without Notice Complete IDE Interface Connections This is so similar to the read path that the read and
5. ERCR1 RCS2_ TS WAIT TIMER 00010 two cycles between accesses Because AS is latched for reasons previously discussed the ASRISE parameter is not critical The RCS3 control register ERCR2 uses the same settings if it is used with the CF interface Other register fields such as Flash location are application dependent After this point card specific initialization can be performed For IDE disk interface devices the usual sequence is 1 Issue RESET command to control register Poll status until not busy Issue RECALIBRATE command to control register Poll status until not busy Issue IDENTIFY command to control register DV ee iS Poll status until not busy 7 Read 256 words of data from command pointer Now application programs can read and write data and commands to the device Usually the desired 512 byte block of data is indexed using the LBA Logical Block Address a 28 bit address Note that the MPC8245 cannot boot from the CF device The EXTROM port is used and this requires software setup A small boot loader can initialize the PortX interface and then jump 8 References This section lists additional reference information e MPC8245 documentation refer to www freescale com MPC8245 Integrated Processor User s Manual MPC8245 Integrated Processor Hardware Specifications e CompactFlash Specifications refer to www compactflash org e For reference purposes many designers may refer to application notes and
6. Freescale Semiconductor Application Note Document Number AN2293 Rev 2 09 2006 Compact Flash Interface for the MPC8245 by Gary Milliorn CPD Application Freescale Semiconductor Inc Austin TX This application note describes the connections necessary to attach a compact flash device to the MPC8245 embedded microprocessor The compact flash CF standard maintained by the CompactFlash Organization describes a standard way to connect and communicate with compact memory I O and disk drive modules These devices are often used in embedded systems to provide low cost mass storage or upgradable OS installations simply by replacing a CF device and rebooting CF devices can easily be upgraded with socketed devices or permanently attached with a caged connector CF memory cards are available with up to 512 Mbytes of nonvolatile memory storage and CF miniature hard disk cards that feature up to 1 GB of storage There are three classes of CF cards e PC card memory e PC card I O True IDE The PC card memory and true IDE interfaces are popular with embedded systems because of the predictable nature of the devices raw storage PC memory cards implement both the memory and true IDE interfaces and disk drives implement only true IDE interfaces This application note discusses the design issues for a true IDE device Freescale Semiconductor Inc 2002 2006 All rights reserved ne WN ona Contents CONVENTONG s
7. at DRDY must be asserted low continuously until the RCS 2 3 signals are de asserted This is correctly implemented in the preceding equations For IORDY when available if the signal is deasserted implying it is available it prevents the timer from incrementing and thereby triggering DRDY to end the cycle When IORDY is released the timer resumes at this point This allows both IORDY extensions to the cycle and timer controlled extensions with the latter controlling in cases where IORDY is not supported The timing diagram in Figure 6 shows a CF IDE read cycle as implemented by the MPC8245 PortX interface with accompanying logic 39 696 400 39 800 000 39 900 000 40 000 000 40 100 000 40 200 000 40 366 790 ps Group A a 0 31 h 00000000 00 as b 1 asl_b 0 cfctr h 00000020 00000000 00000000 clk 1 UUU U U UUU U U h ZZZZZZZZ ZZZZZZZZ T B083 4BFF drdy b 0 foe b 0 fwe b iord b iordy iowr_b vr drdy b 0 rces2_b 0 rces3_b Figure 6 MPC8245 CF Read Cycle As expected the DRDY facility extended the access time well beyond the capabilities of the ROMFAL ROMNAL settings and allowed the access to take as many cycles as necessary
8. by the MPC8245 four to five clocks Compact Flash Interface for the MPC8245 Rev 2 8 Freescale Semiconductor Preliminary Subject to Change Without Notice Timing Issues With these restrictions considered the interface logic necessary to perform reads is shown in Figure 5 MPC8245 CF Device A 2 0 CEO CE1 Figure 5 MPC8245 PortX to CF Read Interface The VHDL equations portions to implement these functions are CF Read Logic SIGNAL TIMER std_logic_vector 4 downto 0 SIGNAL ASL B std_logic BEGIN DELAY RST B RCS2_B AND RCS3 B IORD_B lt 0 WHEN RCS2_B 0 AND ASL B 0 AND FOE B 0 AND DRDY B 1 ELSE 1 ASLL PROCESS SDCLK AS _B DELAY RST B BEGIN IF DELAY RST_B 0 THEN reset ASL B on RCSx clear ASL B lt 1 ELSIF AS B 0 THEN latch ASL B on AS B ASL B lt 0 END IF END PROCESS DELAY PROCESS SDCLK IORDY DELAY RST B BEGIN IF DELAY RST B 0 THEN idle timer TIMER lt others gt 0 Compact Flash Interface for the MPC8245 Rev 2 Freescale Semiconductor 9 Preliminary Subject to Change Without Notice Timing Issues ELSIF IORDY 0O THEN halt timer if not ready TIMER lt TIMER ELSIF SDCLK EVENT AND SDCLK 1 THEN else increment TIMER lt TIMER 00001 END IF END PROCESS DELAY DRDY lt 0 WHEN TIMER gt 10000 ELSE 1 Note th
9. ce Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which
10. e treated as general design information for creating a CF interface and not as a drop in component All the software contained in this application note is copyrighted 2002 by Freescale Inc and may be used freely by Freescale customers for use on MPC8245 based systems as long as the copyright notice remains present in each literal or derived module or source file The code can be freely modified to suit customized applications You are not obligated to make your own proprietary modifications to the code available to the public nor to maintain copyrights of your own modifications 1 Conventions The CF specification uses a prefix to indicate an active low signal XX while this application note uses an overbar XX For VHDL equations the suffix _B indicates an active low signal otherwise active high is assumed 2 Connections Table 1 summarizes all three signal types of the CF devices Table 1 CF Device Connections Interface Signal Description Type Pins Notes PC Card PCCardiO True IDE Memory Common Signals A 10 0 Address l 8 10 11 12 Common 1 14 15 16 17 18 19 20 CD 1 2 Card detect O 26 25 Common CS 0 1 CE 1 2 Chip selects l 7 32 Common 2 CSEL Cable select l 39 Common Compact Flash Interface for the MPC8245 Rev 2 2 Freescale Semiconductor Preliminary Subject to Change Without Notice Connections Table 1 CF Device Connections
11. hat are unique to operating multiple IDE disk drives DASP PDIAG can be ignored in this application The IOIS 16 signal for example is used to indicate 8 bit versus 16 bit accesses and is not needed Because software can set the extended ROM banks to a 16 bit mode only 16 bit accesses occur With these restrictions the IDE mode connections can be summarized as shown in Table 5 Table 5 CF IDE Device Connections Signal Description Type Pins Connections A 10 3 Address 8 10 11 12 14 15 To ground 16 17 A 2 0 Address 18 19 20 To MA 2 0 in same order through optional but recommended buffer CD 1 2 Card detect O 26 25 No connect Compact Flash Interface for the MPC8245 Rev 2 12 Freescale Semiconductor Preliminary Subject to Change Without Notice Complete IDE Interface Connections Table 5 CF IDE Device Connections continued Signal Description Type Pins Connections CS 0 1 Chip selects l 7 32 To RCS2 RCS3 or to decoder logic CSEL Cable select l 39 To ground D 15 0 Data bus O 31 30 29 28 27 To MDH 0 15 through optional but 49 48 47 6 5 4 3 recommended buffer 2 23 22 21 INPACK Input acknowledge O 43 No connect IORD I O read strobe l 34 To FPGA IOWR I O write strobe l 35 To FPGA VS 1 2 Voltage sense O 33 40 No connect IORDY Ready O 42 To FPGA WE Write enable l 36 To Vcc 3 3 V ATASEL IDE
12. igher address lines for the PortX interface buffering the parity lines is not needed if only the CF IDE interface is used which uses only A 2 0 Other signals such as FWE FOE can be lightly loaded and not need additional buffering Buffers for unidirectional signals such as address and FWE are easily implemented because the buffer can be permanently enabled For bidirectional data signals the standard buffer control signals DIR A B and OE should be connected as shown in Figure 1 with logic to control the buffer dependent on how chip selects are implemented Compact Flash Interface for the MPC8245 Rev 2 4 Freescale Semiconductor Preliminary Subject to Change Without Notice Chip Selects MPC8245 MA 12 0 MD 0 63 MDP 0 7 CS 0 7 32245 CF Device Figure 1 MPC8245 Buffering 4 Chip Selects The CF devices require two separate chip selects to implement access to data versus control registers or to emulate the two chip selects for IDE status and control Since the address space requirements of a CF device are less than that provided by the PortX interface there are two possible ways to provide these chip selects use RCS2 and RCS3 as a direct connection or use just one of RCS 2 3 with address decode logic to partition the chip select into two The choice may depend on other system requirements each has benefits and costs as shown in Table 2 Table 2 CF True IDE Mode Read Timing
13. mode enable 9 To ground REG Register select l 44 To Vcc 3 3 V RESET Reset active low 41 To HRESET or PCIRST IOIS16 IOCS16 16 bit access O 24 No connect INTRQ Interrupt request O 37 Through inverter to IRQ 0 4 PDIAG Pass diag VO 46 Pull up to optional activity LED DASP Disk active Slv Pr O 45 No connect Voc Power 3 3 V 13 38 To 3 3 V Ground Ground 1 50 To ground These connections produce a diagram as shown in Figure 10 Compact Flash Interface for the MPC8245 Rev 2 Freescale Semiconductor Preliminary Subject to Change Without Notice Complete IDE Interface Connections MPC8245 CF Device MDH 0 15 FOE D 15 0 1 2 LVT32245 MA 2 0 MA 20 1O N N m 5 N SDCLK IRQ 0 4 Figure 10 CF IDE Interface Compact Flash Interface for the MPC8245 Rev 2 14 Freescale Semiconductor Preliminary Subject to Change Without Notice Software Setup 7 Software Setup The MPC8245 PortX interface must be properly programmed before the CF device can be used The following register fields need to be set to the values shown ERCR1 RCS2_ EN 1 default ERCR1 RCS2_BURST 0 non burst for CF ERCR1 RCS2_ DBW 01 01 16 bits though 8 is also possible ERCR1 RCS2_ CTL 11 11 handshake mode required ERCR1 ROMFAL 11111 not used set to max ERCR1 ROMNAL 11111 not used set to max ERCR1 ASFALL 00100 delay 4 clocks ERCR1 ASRISE 00110 rise 6 clocks
14. nimum of 70 ns is required before IORD can be asserted additional logic is required to implement IORD other than a simple logical function of RCS 2 3 and FWE To implement the delayed IORD the ASFALL facility of the PortX interface is used The signal AS can be programmed to be asserted low 1 to 15 clocks after the start of any cycle read or write By setting ASFALL to 70 ns bus clock 1 the AS signal will be asserted low gt 70 ns after the start of any cycle Additional logic combines AS with RCS 2 3 and FWE to produce the IORD signal Since AS is typically much shorter in duration than the handshake controlled RCSn signal it needs to be latched to extend the duration Also RCSn can be delayed but that takes as much logic as a simple set reset flip flop Similarly the address signal needs to be maintained after IORD though data does not Since the MPC8245 may change the address after releasing RCS 2 3 the ASRISE setting would normally be used to remove the signal one or two clocks early In handshake mode the DRDY signal can be used to disable ASRISE early but if DRDY is not asserted early the normal ASRISE timing values are in effect The effect is that AS assertion is usually much shorter than the overall access time and AS cannot be used by itself unless the targeted card is guaranteed to work at that speed this is an optimizable option The hold time is maintained by the inherent disable time provided
15. parameters and values are shown in Table 3 A 2 0 lt IGHAX lt tiGHEH UGLIGH gt IORD tigLav gt lt gt 1tIigHax D 15 0 Figure 4 CF True IDE Mode Read Cycle Compact Flash Interface for the MPC8245 Rev 2 Freescale Semiconductor 7 Preliminary Subject to Change Without Notice Timing Issues Table 3 CF True IDE Mode Read Timing Pail a Description Min Max Unit ticLav Data delay after IORD 100 ns tigHax Data hold following IORD 0 ns tiGLIGH IORD width time 165 ns taviGL Address setup before IORD 70 ns tiGHax Address hold following IORD 20 ns tELIGL CE setup before IORD 5 ns tiGHEH CE hold following ORD 20 ns First notice is that the overall access time can be as high as 255 ns tavIGL tigLIGH UGHAX This is just beyond the capability of the MPC8245 Flash PortX interface operating at 133 MHz and even then the setup hold time relationships are not exactly as required When this is the case DRDY handshake mode is typically used as previously detailed Further examining the waveform and timing values it is clear there is no required relationship between address and chip select the MPC8245 PortX interface provides one clock of address setup prior to the chip select so the address and CE signals can be mapped to the standard PortX MA 20 0 and RCS 2 3 signals However since a mi
16. rtX controller and will be covered in the following sections The overall duration of signals becomes an issue when considering the high speed of the MPC8245 PortX interface possibly 8 ns clocks with a 133 MHz bus and the relatively slow speeds allowed by the CF standard Referring to the overall access times discussed in Section 5 1 Read Timing and Section 5 2 Write Timing cycles may take up to 255 ns or approximately 31 clocks at 133 MHz Since this is just beyond the limits of the standard mode of the MPC8245 PortX interface the handshake mode is needed The handshake mode allows PortX cycles to stretch out indefinitely until the DRDY signal is asserted This mode is not discussed here as a thorough familiarity with the MPC8245 PortX interface is assumed refer to Sections 6 3 5 and 6 3 6 of the MPCS8245 Integrated Processor User s Manual A slight complication of the CF interface is that the IORDY WAIT signal which would be a natural means of controlling the MPC8245 PortX handshake mode is optional and not mandatory Bit 11 of the IDE capabilities word indicates whether it is supported or not Unless only ORD Y compatible devices are used IORDY is not usable as a sole means of timing control for a general purpose CF IDE interface Since it is not clear what percentage of CF devices support IORDY the control logic incorporates both 5 1 Read Timing The read access timing waveform is shown in Figure 4 while the
17. s they just have slightly different names 3 D15 is the MSB for the CF while MDHO is the MSB for the MPC8245 The CF signals are either similar or sideband signals implementing unusual controls that can be ignored in many cases Only a handful must change to control CF memory I O or IDE cards Designers implementing PC memory or PC I O modes should be able to adapt to those devices with only slight modifications to the logic in this application note 3 Interface Considerations The CF specification uses standard CMOS signaling levels at Voc 3 3 V a standard CF device and the MPC8245 can be directly connected with no level translation or high strength drivers needed However on many systems the MPC8245 PortX interface signals used to control the CF device are also needed to provide address and parity to the SDRAM and boot flash memory and possibly also control auxiliary flash storage and other devices Because CF devices are allowed to present a 100 pF load on each signal to ensure the ability to operate at high speeds a small amount of isolation buffering probably results in a more robust and faster system refer to Figure 1 Therefore this application note shows a small buffer on critical signals but this buffer is only for the purpose noted previously The buffer can be eliminated if a system timing analysis allows this is strictly up to the system designer Because the memory parity signals are used only to implement the h
18. s cci cho ce eebosande de eke EA 2 Connections A reena E 2554s EEEN ERNER E 2 Interface Considerations n onanan 00000 4 Chip Selects c casa chee gated patea Gee As gale 5 Timing ISSUES irrar emn niriana gis and gialeseane diene 6 7 5 1 Read Timings ss sc cise diss oie ssiae eb oS e patee 7 3 2 Waite THM sses sepies oiid diie ara 10 Complete IDE Interface Connections 12 Software Setup 0 0 0 0 c eee eee eee 15 Referente Sha eeka a R sea secadiiace 15 lop oe gt freescale semiconductor Conventions All three types are generally described with differences noted to assist designers who want only PC memory or PC I O devices The connections of the CF card in PC memory and PC I O modes are similar to those of the IDE mode but with a different register interface and slight changes of interface signals Finally CF devices feature the ability to be hot plugged that is inserted and removed while power is applied This is not required for most embedded applications and requires special power sequencing and dynamic signal reconfiguration logic that is far beyond the purpose of this application note NOTE The VHDL in this application note is compiled and verified with a software test bench but has not been verified in hardware There may be significant errors in this application note or the CF test bench may not have revealed latent errors in the example code Therefore this application note should b
19. the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by Power org All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2002 2006 2 freescale Power semiconductor
20. write logic can be combined and the following equations is all that is needed to create a read write controller for the CF device IOWR_B lt 0 WHEN RCS2_B 0 AND ASL B 0 AND FWE_B 0 AND DRDY B 1 ELSE 1 The timing diagram in Figure 9 shows a CF IDE write cycle as implemented by the MPC8245 PortX interface with accompanying logic 41 564 610 41 700 000 41 800 000 41 900 000 42 000 000 42 235 000 ps Group A a 0 31 h 00000000 as b 1 asl_b 0 cfctr h 00000020 00000000 00000000 clk 1 MUU UU UU UU h 22222222 22222222 7C80 A083 drdy b 0 foe b 0 fwe_b iord b iordy iowr_b r_drdy b 0 rces2_b 0 rces3_b Figure 9 MPC8245 CF Write Cycle 6 Complete IDE Interface Connections In true IDE mode the CF device is accessed as if it were an IDE disk drive operating in PIO non DMA modes with only the corresponding standard complement of eight address lines Normally these extra address lines are grounded but to allow a common interface for true IDE and PC card memory modes it is sufficient simply to drive the unused address lines to 0x0000 during accesses Several signals t
Download Pdf Manuals
Related Search