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UM10601 LPC800 User manual

1. 141 a aaaaaanaaaannranannnnnn 131 10 7 11 Configure the SCT without using states 142 Chapter 11 LPC800 Multi Rate Timer MRT 11 1 How to read this chapter 143 11 2 Feat res c o deeb ee eee are RERO 143 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 321 of 326 NXP Semiconductors UM10601 11 3 11 4 11 5 11 5 1 11 5 2 11 6 Basic configuration Pin General description Repeat interrupt mode One shot interrupt mode Register description 11 6 1 11 6 2 11 6 3 11 6 4 11 6 5 11 6 6 Chapter 28 Supplementary information Time interval register 146 Timer 147 Control register 147 Status register 148 Idle channel register 148 Global interrupt flag register 149 Chapter 12 LPC800 Windowed Watchdog Timer WWDT 12 1 How to read this chapter 150 12 5 3 Changing the WWDT reload value 153 12 2 Feat res RR a 150 12 6 Register description 154 12 3
2. 150 12 61 Watchdog mode 154 12 4 Pin 150 12 6 2 Watchdog Timer Constant register 156 m 12 6 3 Watchdog Feed register 156 n 1 pod d d MID MN 12 6 4 Watchdog Timer Value register 157 1252 En doni TIE RE 152 12 6 5 Watchdog Timer Warning Interrupt register 157 12 5 3 Using the WWDT lock features jug Sere 187 12 5 3 1 Disabling the WWDT clock 15 12 7 Functional description 158 Chapter 13 LPC800 Analog comparator 13 1 How to read this chapter 159 13 5 1 Reference voltages 161 13 2 Features 159 13 5 2 Settling 161 13 3 Basic 159 bae Pia de es eee tutes fud 5 13 3 1 Connect the comparator output the SCT 159 pe omparator outputs A E 13 4 _ jeo 190 Register description aad i meameebesn ans 162 135 General description 160 13 6 1 Comparator control register 162 PHO si ss aae 13 6 2 Voltage ladder register 164 Chapter 14 LPC800 Self wake up timer WKT 14 1 How to read this chapter 165 14 5 General description 165 142 Features cio
3. 243 20 3 Basic 241 20 6 Functional description 245 20 3 1 Bootloader versions 241 20 6 1 Memory map after any reset 245 204 242 ds p ar 20 5 Generaldescription 242 M Chapter 21 LPC800 Flash ISP programming 21 1 How to read this chapter 247 21 5 1 15 Read CRC checksum address no of 21 2 247 bytes csse 257 21 3 Pin 247 21 5 1 16 UART ISP Return 258 214 General description 247 21 5 2 IAP 259 icc E EE 21 5 2 1 Prepare sector s for write operation IAP 261 21 4 1 Flash configuration eet nee sten 247 21 5 2 2 Copy RAM to flash IAP 261 21 4 2 ed icc IE 248 21523 Erase Sector s 262 21 4 3 Code Read Protection 249 215 24 Blank check sector s 263 21 4 3 1 ISP entry 250 21525 Read Part Identification number 263 21 5 description 251 21 526 Read Boot code version number IAP 263 21 5 1 UART ISP commands 251 21 5 2 7 Compare lt address1 gt
4. UM10601 LPC800 User manual Rev 1 1 24 January 2013 Preliminary user manual Document information Info Content Keywords ARM Cortex M0 LPC800 USART I2C LPC810M021FN8 LPC811M001FDH16 LPC812M101FDH16 LPC812M101FD20 LPC812M101FDH20 Abstract LPC800 user manual NXP Semiconductors U M1 0601 Revision history LPC800 User manual Rev Date Description 1 1 20130124 LPC800 user manual Modifications Flash signature creation algorithm corrected See Section 19 5 1 Flash signature generation System PLL output frequency restricted to 100 MHz MTB register memory space changed to 1 kB in Figure 2 LPC800 Memory mapping Description of the External trace buffer command register updated See Section 4 6 20 External trace buffer command register Flash interrupt removed in Table 3 Chapter 27 summarizing the ARM Cortex M0 instruction set added ISP Read CRC checksum command added See Section 21 5 1 15 Read CRC checksum address lt no of bytes gt Section 20 3 1 Boot loader versions added MRT implementation changed to 31 bit timer See Chapter 11 Bit description of Table 139 Idle channel register IDLE_CH address 0x4000 40F4 bit description corrected Updates for clarification in Chapter 17 LPC800 SPIO0 1 Updates for clarification in Chapter 16 LPC800 I2C bus interface Updates for clarification in Chapter 15 LP
5. 68 pee O bus mode 54 6544 PIOO 8 69 6 4 7 Programmable glitch filter 54 6 5 15 7 70 6 5 Register description 55 6 5 16 71 6 5 1 PIOO 17register 56 6 5 17 72 6 5 2 PIOO IS register 57 6 5 18 1 0_14 73 6 5 3 PIOO_12 register 58 Chapter 7 LPC800 GPIO port 7 1 How to read this chapter 74 7 6 5 GPIO port pin registers 76 7 2 74 766 GPIO masked port pin registers 77 7 6 7 GPIO port set registers 77 7 3 Basic 74 74 Pi i 74 7 6 8 GPIO port clear 77 ee bud MELDE 7 6 9 GPIO port toggle registers 78 13 description HaT LE n 7 7 Functional description 78 7 6 Register description pnm Ed 75 7 7 1 Reading pin 78 7 6 4 CNE CC GPIO ouput RE 78 7 6 2 GPIO port word pin registers 75 79 7 6 3 GP
6. 185 15 6 Register description 174 5 7 3 1 Hardware flow 185 15 6 1 USART Configuration register 175 15 732 Software flow 186 15 6 2 USART Control register 176 15 6 3 USART Status register 178 15 6 4 USART Interrupt Enable read and set register 179 15 6 5 USART Interrupt Enable Clear register 180 15 6 6 USART Receiver Data register 181 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 322 of 326 NXP Semiconductors UM10601 Chapter 16 LPC800 I2C bus interface Chapter 28 Supplementary information 16 1 How to read this chapter 187 16 6 7 12 Interrupt Status register 200 16 2 Features 187 16 6 8 Master Control register 201 16 3 187 us Mas Ee SB kp s puede Bes 16 3 1 Configure the 12C for wake up 188 boe zm 16 3 1 1 Wake up from Sleep mode 188 16 612 amp lave Data 204 16 3 1 2 Wake up from Deep sleep and Power down 16 6 13 Slave pie registers EE 205 188 16614 Slave address Qualifier 0 register 205 16 4 Pin description Huc lE 18
7. 4 GPIO INT BMAT UO RXD 5 USARTO UO CTS UO SCLK S oS DIGITAL PERIPHERAL DIGITAL PERIPHERAL ANALOG gt PERIPHERAL Fig 13 Functional diagram of the switch matrix Remark From all available movable and fixed pin functions you can assign multiple functions to the same pin but no more than one output or bidirectional function see Figure 13 Use the following guidelines when assigning pins t is allowed to send one input signal on a pin to multiple internal inputs by programming the same pin number in more than one PINASSIGN register Example You can enable the CLKIN input in the PINENABLEO register on pin PIOO 1 and also assign one ore more SCT inputs to pin PIOO 1 through the PINASSIGN registers to feed the CLKIN into the SCT You can send the input on one pin to all SCT inputs to use as an SCT abort signal It is allowed to let one digital output function control one or more digital inputs by programming the same pin number in the PINASSIGN register bit fields for the output and inputs Example You can assign the same pin number to the ACMP OUT function and an SCT input CTIN n This connects the comparator output to input n of the SCT You can loop back the USART transmit output to the receive input by assigning the same pin number to Un RXD and Un TXD e It is not allowed to connect more than one output or bidirectional function
8. 112 9 4 1 Movable lt 107 9 5 9 Pin assign register 8 113 9 4 2 Switch matrix register interface 108 9 5 10 Pin enable register O 113 9 5 Register description 109 Chapter 10 LPC800 State Configurable Timer SCT 10 1 How to read this chapter 115 10 6 19 SCT capture registers 0 to 4 REGMODEn 10 2 Features 115 132 10 3 Basic 115 10 6 20 5 n reload registers 0 to 4 ima HE 90 octets rete ack en eS Use POI d 115 10 6 21 SCT capture control registers 0 to 4 REGMODEn 10 4 Pin lt 116 VM EDEN CMM 132 10 5 Generaldescription 116 10 6 22 SCT event state mask registers 0 to5 133 10 6 Register description 118 10 6 28 SCT event control registers 0 t05 133 10 6 1 SCT configuration register 121 10 6 24 SCT output set registers 0 to 3 135 10 6 2 SCT control register 122 10 6 25 SCT output clear registers 0 to3 135 10 6 3 SCT limit register 123 10 7 Functional description 136 10 6 4 SCT halt condition register 124 10 7 1 Match 136 10 6 5 stop condition register
9. 50 573 46 Ed E ifa c ne 50 5 7 3 1 Power configuration in Active mode 46 577 Nd configuration Deep power down m 5 7 4 Sleep mode 47 a ag 5 7 41 Power configuration in Sleep mode 47 57 7 2 Programming Deep power down En 5 7 4 2 Programming Sleep mode 47 57 7 3 Wake up from Deep power down mode 5 5 7 4 8 Wake up from Sleep 47 Chapter 6 LPC800 I O configuration IOCON 6 1 How to read this chapter 52 6 5 4 5 register 59 6 2 A E EEE 52 6 5 5 0 _4 5 60 6 3 Basic 52 6 5 6 61 A 6 5 7 2 register 62 6 4 General 53 658 PIOO 11 register 63 6 4 1 Pin configuration DTE 53 6 5 9 PIOO 10 64 6 4 2 Pin 22 RR tr Ded 53 6 5 10 16 65 Bo panes 53 6 5 11 15 66 6 44 Open drain 54 6542 1 67 Bs e o 54 6543 PIOO0
10. Fig 49 Connecting the SWD pins to a standard SWD connector Boundary scan The RESET pin selects between the JTAG boundary scan RESET LOW and the ARM SWD debug RESET HIGH The ARM SWD debug port is disabled while the part is in reset To perform boundary scan testing follow these steps Erase any user code residing in flash Power up the part with the RESET pin pulled HIGH externally Wait for at least 250 us Pull the RESET pin LOW externally Perform boundary scan operations c Once the boundary scan operations are completed assert the TRST pin to enable the SWD debug mode and release the RESET pin pull HIGH Remark The JTAG interface cannot be used for debug purposes Remark POR BOD reset or a LOW on the TRST pin puts the test TAP controller in the Test Logic Reset state The first TCK clock while RESET HIGH places the test in Run Test Idle mode All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 301 of 326 NXP Semiconductors U M1 0601 Chapter 25 LPC800 Debugging 25 5 4 Micro Trace Buffer MTB The MTB registers are located at memory address 0x1400 0000 and are described in Ref 2 The EXTTRACE register in the syscon block see Section 4 6 20 starts and stops tracing in conjunction with the TSTARTEN and TSTOPEN bits in th
11. Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 lt Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 62 of 326 NXP Semiconductors UM10601 6 5 8 PIOO 11 register Chapter 6 LPC800 I O con
12. Pin interrupts Select up to eight external interrupt pins from all GPIO port pins in the SYSCON block Table 32 The pin selection process is the same for pin interrupts and the pattern match engine The two features are mutually exclusive Enable the clock to the pin interrupt register block in the SYSAHBCLKCTRL register Table 18 bit 6 If you want to use the pin interrupts to wake up the part from deep sleep mode or power down mode enable the pin interrupt wake up feature in the STARTERPO register Table 33 Each selected pin interrupt is assigned to one interrupt in the NVIC interrupts 24 to 31 for pin interrupts 0 to 7 Pattern match engine Select up to eight external pins from all GPIO port pins in the SYSCON block Table 32 The pin selection process is the same for pin interrupts and the pattern match engine The two features are mutually exclusive UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 80 of 326 NXP Semiconductors U M1 0601 Chapter 8 LPC800 Pin interrupts pattern match engine Enable the clock to the pin interrupt register block in the SYSAHBCLKCTRL register Table 18 bit 6 Each bit slice of the pattern match engine is assigned to one interrupt in the NVIC interrupts 24 to 31 for slices O to 7 The combined interrupt f
13. Preliminary user manual Rev 1 1 24 January 2013 110 of 326 NXP Semiconductors U M1 0601 9 5 4 9 5 5 9 5 6 UM10601 Chapter 9 LPC800 Switch matrix Pin assign register 3 Table 99 Pin assign register PINASSIGNG address 0x4000 CO00C bit description Bit Symbol Description Reset value 7 0 U2 RTS U2 RTS function assignment The value is the pin number to OXFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 15 8 U2 CTS I U2 CTS function assignment The value is the pin number to be OXFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 23 16 U2 SCLK IO 02 SCLK function assignment The value is the pin number to be OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 31 24 SPIO SCK IO SPIO SCK function assignment The value is the pin number to OxFF be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 Pin assign register 4 Table 100 Pin assign register 4 PINASSIGN4 address 0x4000 C010 bit description Bit Symbol Description Reset value 7 0 SPIO MOSI IO MOSI function assignment The value is the pin number to be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 15 8 SPIO MISO IO SPIO_MISIO function assignment The value is the pin number
14. Bit Symbol Value Description Reset value 22 20 CFG4 Specifies the match contribution condition for bit slice 4 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was Cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 4 High level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0x5 Low level Match occurs when there is a low level on the specified input 0x6 Constant 0 This bit slice never contributes to a match should be used to disable any unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs on an event i e when either a rising or falling edge is first detected on the specified input this is a non stick
15. Pin interrupt rising edge register This register contains ones for pin interrupts selected in the PINTSELn registers see Section 4 6 27 on which a rising edge has been detected Writing ones to this register clears rising edge detection Ones in this register assert an interrupt request for pins that are enabled for rising edge interrupts All edges are detected for all pins selected by the PINTSELn registers regardless of whether they are interrupt enabled Table 87 Pin interrupt rising edge register RISE address 0xA000 401C bit description Bit Symbol Description Reset Access value 7 0 RDET Rising edge detect Bit n detects the rising edge of the pin 0 R W selected in PINTSELn Read 0 No rising edge has been detected on this pin since Reset or the last time a one was written to this bit Write 0 no operation Read 1 a rising edge has been detected since Reset or the last time a one was written to this bit Write 1 clear rising edge detection for this pin 31 8 Reserved All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 89 of 326 NXP Semiconductors U M1 0601 8 6 9 8 6 10 8 6 11 UM10601 Chapter 8 LPC800 Pin interrupts pattern match engine Pin interrupt falling edge register This register contains ones for pin interrupts selected in the PINTSELn registers see S
16. 0 remain so for at least the time specified by the Transfer_delay value in the DLY register SSEL not deasserted This piece of data is not treated as the end of a transfer SSEL will not be deasserted at the end of this data SSEL deasserted This piece of data is treated as the end of a transfer SSEL will be deasserted at the end of this piece of data End of Frame Between frames a delay may be inserted as defined by the 0 Frame_delay value in the DLY register The end of a frame may not be particularly meaningful if the FRAME_DELAY value 0 This control can be used as part of the support for frame lengths greater than 16 bits Data not EOF This piece of data transmitted is not treated as the end of a frame Data EOF This piece of data is treated as the end of a frame causing the FRAME_DELAY time to be inserted before subsequent data is transmitted Receive Ignore This allows data to be transmitted using the SPI without the need to 0 read unneeded data from the receiver to simplify the transmit process Read received data Received data must be read in order to allow transmission to progress In slave mode an overrun error will occur if received data is not read before new data is received Ignore received data Received data is ignored allowing transmission without reading unneeded received data No receiver flags are generated All information provided in this document is subject to legal disclaimers NXP B V 2
17. SRC2 010 select input 2 for bit slice 2 SRC3 010 select input 2 for bit slice 3 SRC4 011 select input for bit slice 4 SRC5 110 select input 6 for bit slice 5 SRCE6 101 select input 5 for bit slice 6 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 99 of 326 NXP Semiconductors U M1 0601 Chapter 8 LPC800 Pin interrupts pattern match engine SRCT 111 select input 7 for bit slice 7 PMCTRL register Table 90 Bit 0 Setting this bit will select pattern matches to generate the pin interrupts in place of the normal pin interrupt mechanism For this example pin interrupt 0 will be asserted when a match is detected on the first product term which in this case is just a high level on input 1 Pin interrupt 2 will be asserted in response to a match on the second product term Pin interrupt 5 will be asserted when there is a match on the third product term Pin interrupt 7 will be asserted on a match on the last term Bit 1 Setting this bit will cause the RxEv signal to the ARM CPU to be asserted whenever a match occurs on ANY of the product terms in the expression Otherwise the RXEV line will not be used Bit 31 24 At any given time bits 0 2 5 and or 7 may be high if the corresponding product terms are currently matching The remaining b
18. CLKOUTSEL R W OxOEO CLKOUT clock source select 0 Table 20 CLKOUTUEN R W OxOE4 CLKOUT clock source update enable 0 Table 21 CLKOUTDIV R W OxOE8 CLKOUT clock divider 0 Table 22 UARTFRGDIV R W Ox0FO USART fractional generator divider value 0 Table 23 UARTFRGMULT R W Ox0F4 USART fractional generator multiplier value 0 Table 24 EXTTRACECMD R W OxOFC External trace buffer command register 0 Table 25 PIOPORCAPO R 0x100 POR captured PIO status 0 user dependent Table 26 0x104 Reserved IOCONCLKDIV6 R W 0x134 Peripheral clock 6 to the IOCON block for 0x0000 0000 Table 27 programmable glitch filter IOCONCLKDIV5 R W 0x138 Peripheral clock 5 to the IOCON block for 0x0000 0000 Table 27 programmable glitch filter IOCONCLKDIV4 R W 0x13C Peripheral clock 4 to the IOCON block for 0x0000 0000 Table 27 programmable glitch filter IOCONCLKDIV3 R W 0x140 Peripheral clock 3 to the IOCON block for 0x0000 0000 Table 27 programmable glitch filter IOCONCLKDIV2 R W 0x144 Peripheral clock 2 to the IOCON block for 0x0000 0000 27 programmable glitch filter IOCONCLKDIV 1 R W 0x148 Peripheral clock 1 to the IOCON block for 0x0000 0000 Table 27 programmable glitch filter IOCONCLKDIVO R W 0x14C Peripheral clock 0 to the IOCON block for 0x0000 0000 Table 27 programmable glitch filter BODCTRL R W 0x150 Brown Out Detect 0 Table 28 SYSTCKCAL R W 0x154 System tick counter calibration 0x0 Table 29 R W 0x168 Reserved IRQLATENCY R W 0x170 IQR delay
19. 13 12 SLVIDX UM10601 Value Description Reset Access value Master Start Stop Error flag This flag can be cleared by software 0 W1 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 writing a 1 to this bit It is also cleared automatically a 1 is written to MstContinue No Start Stop Error has occurred Start stop error has occurred The Master function has experienced a Start Stop Error A Start or Stop was detected at a time when it is not allowed by the 2 specification The Master interface has stopped driving the bus and gone to an idle state no action is required A request for a Start could be made or software could attempt to insure that the bus has not stalled Reserved Read value is undefined only zero should be written NA NA Slave Pending Indicates that the Slave function is waiting to continue 0 RO communication on the I2C bus and needs software service This flag will cause an interrupt when set if enabled via INTENSET The SLVPENDING flag is read only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the MSTCTL register In progress The Slave function does not currently need service Pending The Slave function needs service Information on what is needed can be found in the adjacent SLVSTATE field Slave State code Each value of this field indicates a specific required 0 RO service for the Slave function All other values are reserved Slave address Address plus R W received
20. 3 2 Features Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex M0 Tightly coupled interrupt controller provides low interrupt latency Controls system exceptions and peripheral interrupts The NVIC supports 32 vectored interrupts Four programmable interrupt priority levels with hardware priority level masking Software interrupt generation using the ARM exceptions SVCall and PendSV see Ref 1 Support for NMI e ARM Cortex MO Vector table offset register VTOR implemented 3 3 General description The Nested Vectored Interrupt Controller NVIC is an integral part of the Cortex M0 The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts 3 3 1 Interrupt sources Table 3 lists the interrupt sources for each peripheral function Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller Each line may represent more than one interrupt source Interrupts with the same priority level are serviced in the order of their interrupt number See Ref 1 for a detailed description of the NVIC and the NVIC register description Table 3 Connection of interrupt sources to the NVIC Interrupt Name Description Flags number 0 SPIO IRQ SPIO interrupt See Table 192 SPI Interrupt Enable read and Set register INTENSET addresses 0x4005 800C SPIO 0x4005 SPI1 bit descr
21. GPIO pins can be configured as input or output by software All GPIO pins default to inputs at reset Pininterrupt registers allow pins to be sensed and set individually 7 3 Basic configuration For the GPIO port registers enable the clock to the GPIO port registers in the SYSAHBCLKCTRL register Table 18 bit 6 7 4 Pin description All GPIO functions are fixed pin functions The switch matrix assigns every GPIO port pin to one and only one pin on the LPC800 package By default the switch matrix connects all package pins except supply and ground pins to their GPIO port pins The pin description table see Table 285 shows how the GPIO port pins are assigned to LPC800 package pins 7 5 General description The GPIO port registers can be used to configure each GPIO pin as input or output and read the state of each pin if the pin is configured as input or set the state of each pin if the pin is configured as output UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 74 of 326 NXP Semiconductors U M1 0601 Chapter 7 LPC800 GPIO port 7 6 Register description The GPIO port registers and the GPIO pin interrupt registers are located on the ARM I O port The I O port supports single cycle access Remark In all GPIO registers bits that are not shown are reserved GPIO po
22. NXP Semiconductors UM10601 Chapter 13 LPC800 Analog comparator Table 151 Comparator control register CTRL address 0x4002 4000 bit description Bit Symbol Value Description Reset value 10 8 COMP VP SEL Selects positive voltage input 0 0x0 Voltage ladder output 0x1 ACMP 11 0x2 ACMP 12 0x3 Reserved 0 4 Reserved 0x5 Reserved 0x6 Internal reference voltage bandgap 0 7 Reserved 13 11 COMP VM SEL Selects negative voltage input 0 0x0 Voltage ladder output 0 1 ACMP 11 0x2 ACMP 12 0x3 Reserved 0 4 Reserved 0x5 Reserved 0x6 Internal reference voltage bandgap 0 7 Reserved 19 14 Reserved Write as O 20 EDGECLR Interrupt clear bit To clear the COMPEDGE bitand 0 thus negate the interrupt request toggle the EDGECLR bit by first writing a 1 and then a O 21 COMPSTAT Comparator status This bit reflects the state of the 0 comparator output 22 Reserved Write as O 0 23 COMPEDGE Comparator edge detect status 0 24 Reserved Write as 0 0 26 25 HYS Controls the hysteresis of the comparator When the 0 comparator is outputting a certain state this is the difference between the selected signals in the opposite direction from the state being output that will Switch the output 0x0 None the output will switch as the voltages cross 0 1 5 mV 0x2 10 mV 0x3 20 mV 31 27 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Pr
23. NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 17 3 1 Configure the SPIs for wake up In sleep mode any signal that triggers an SPI interrupt can wake up the part provided that the interrupt is enabled in the INTENSET register and the NVIC As long as the SPI clock SPI PCLK remains active in sleep mode the SPI can wake up the part independently of whether the SPI block is configured in master or slave mode In Deep sleep or Power down mode the SPI clock is turned off as are all peripheral clocks However if the SPI is configured in slave mode and an external master provides the clock signal the SPI can create an interrupt asynchronously This interrupt if enabled in the STARTERP 1 register in the NVIC and in the SPI s INTENSET register can then wake up the core 17 3 1 1 Wake up from Sleep mode Configure the SPI in either master or slave mode See Table 189 Enable the SPI interrupt in the NVIC Any SPI interrupt wakes up the part from sleep mode Enable the SPI interrupt in the INTENSET register Table 192 17 3 1 2 Wake up from Deep sleep or Power down mode Configure the SPI in slave mode See Table 189 You must connect the SCK function to a pin and connect the pin to the master e Enable the SPI interrupt in the STARTERP1 register See Table 34 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description n the PDAWAKE register configure all peripherals
24. OXFF to be assigned to this function The following pins are available PIOO 0 0 to PIOO 17 0x11 23 16 SPIO SSEL IO SPIO SSEL function assignment The value is the pin number to OxFF be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 2 Ox11 31 24 SPM SCK IO SCK function assignment The value is the pin number to OxFF be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 Pin assign register 5 Table 101 Pin assign register 5 PINASSIGNS address 0x4000 C014 bit description Bit Symbol Description Reset value 7 0 SPl1_MOSI_IO SPI1 MOSI function assignment The value is the pin number to OxFF be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 111 of 326 NXP Semiconductors U M1 0601 Chapter 9 LPC800 Switch matrix Table 101 Pin assign register 5 PINASSIGNS address 0x4000 C014 bit description Bit Symbol Description Reset value 15 8 SPlI1 MISO IO SPI1_MISIO function assignment The value is the pin number OxFF to be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 2 Ox11 23 16 SPM SSEL IO SPI SSEL function assignment The value is the pin number to OxFF be ass
25. Preliminary user manual Rev 1 1 24 January 2013 76 of 326 NXP Semiconductors U M1 0601 7 6 6 7 6 7 7 6 8 UM10601 Chapter 7 LPC800 GPIO port Table 73 GPIO port 0 pin register PINO address 0xA000 2100 bit description Bit Symbol Description Reset Access value 17 0 PORTO Reads pin states or loads output bits bit O 0 bit1 ext R W PIOO 1 bit 17 PIOO 17 0 Read pin is low write clear output bit 1 Read pin is high write set output bit 31 18 Reserved 0 GPIO masked port pin registers These registers are similar to the PIN registers except that the value read is masked by ANDing with the inverted contents of the corresponding MASK register and writing to one of these registers only affects output register bits that are enabled by zeros in the corresponding MASK register Table 74 GPIO masked port 0 pin register MPINO address 0xA000 2180 bit description Bit Symbol Description Reset Access value 17 0 Masked port register bit PIOO 0 bit 1 PIOO 1 bit ext R W 17 PIOO_17 0 Read pin is LOW and or the corresponding bit in the MASK register is 1 write clear output bit if the corresponding bit in the MASK register is 0 1 Read pin is HIGH and the corresponding bit in the MASK register is 0 write set output bit if the corresponding bit in the MASK register is 0 31 18 Reserved 0 GPIO port set registers Ou
26. UM10601 Chapter 16 LPC800 I2C bus interface Common registers Table 170 I2C Configuration register CFG address 0x4005 0000 bit description Table 171 I2C Status register STAT address 0x4005 0004 bit description Table 178 I2C Interrupt Status register INTSTAT address 0x4005 0018 bit description Table 174 Interrupt Enable Set and read register INTENSET address 0x4005 0008 bit description Table 175 Interrupt Enable Clear register INTENCLR address 0x4005 000C bit description Table 176 time out register TIMEOUT address 0x4005 0010 bit description Table 177 I2C Clock Divider register DIV address 0x4005 0014 bit description Master function registers Table 179 Master Control register MSTCTL address 0x4005 0020 bit description Table 180 Master Time register MSTTIME address 0x4005 0024 bit description Table 181 Master Data register MSTDAT address 0x4005 0028 bit description Slave function registers Table 182 Slave Control register SLVCTL address 0x4005 0040 bit description Table 182 Slave Control register SLVCTL address 0x4005 0040 bit description Table 184 Slave Address registers SLVADR 0 3 address 0x4005 0048 SLVADRO to 0x4005 0054 SLVADR3 bit description Table 185 Slave address Qualifier 0 register SLVQUALO address 0x4005 0058 bit description Monitor function register Table 186 Monitor dat
27. 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x1CO Description Pin assign register 0 Assign movable functions UO TXD UO RXD UO RTS UO CTS Pin assign register 1 Assign movable functions UO SCLK U1 TXD U1 RXD U1 RTS Pin assign register 2 Assign movable functions UT CTS U1 SCLK U2 TXD U2 RXD Pin assign register 3 Assign movable function U2_RTS U2 CTS U2 SCLK SPIO SCK Pin assign register 4 Assign movable functions MOSI SPIO MISO SPIO SSEL SPI1_SCK Pin assign register 5 Assign movable functions SPI1 MOSI SPI1_MISO SPI1_SSEL CTIN 0 Pin assign register 6 Assign movable functions CTIN 1 CTIN 2 CTIN 3 CTOUT 0 Pin assign register 7 Assign movable functions CTOUT 1 CTOUT 2 CTOUT 3 I2C_SDA Pin assign register 8 Assign movable functions 12C_SCL ACMP CLKOUT GPIO_INT_BMAT Reserved Pin enable register 0 Enables fixed pin functions ACMP 10 11 SWCLK SWDIO XTALIN XTALOUT RESET CLKIN VDDCMP Reset value OxFFFF FFFF OxFFFF FFFF OxFFFF FFFF OxFFFF FFFF OxFFFF FFFF OxFFFF FFFF OxFFFF FFFF OxFFFF FFFF OxFFFF FFFF 0x1B3 Reference Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102 Table 103 Table 104 Table 105 9 5 1 Pin assign register 0 Table 96 Pin assign register 0 PINASSIGNO address 0x4000 C000 bit description Bit Symbol Description Reset value 7 0 UO TXD TXD func
28. 1 Pending interrupt The interrupt is pending because TIMER3 has reached the end of the time interval If the INTEN bit in the CONTROLS register is also set to 1 the interrupt for timer channel 3 and the global interrupt are raised Writing a 1 to this bit clears the interrupt request 31 4 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 149 of 326 UM10601 Chapter 12 LPC800 Windowed Watchdog Timer WWDT Rev 1 1 24 January 2013 Preliminary user manual 12 1 How to read this chapter 12 2 Features The watchdog timer is identical on all LPC800 parts Internally resets chip if not reloaded during the programmable time out period Optional windowed operation requires reload to occur between a minimum and maximum time out period both programmable Optional warning interrupt can be generated at a programmable time prior to watchdog time out Programmable 24 bit timer with internal fixed pre scaler Selectable time period from 1 024 watchdog clocks Twpcik x 256 x 4 to over 67 million watchdog clocks 224 x 4 in increments of 4 watchdog clocks Safe watchdog operation Once enabled requires a hardware reset or a Watchdog reset to be disabled Incorrect feed sequence causes immediate watchdog event if enabled The watchdog reload value can
29. 116 Table 107 Register overview State Configurable Timer base address 0x5000 4000 Table 108 SCT configuration register CONFIG address 0x5000 4000 bit description Table 109 SCT control register CTRL address 0x5000 4004 bit description 122 Table 110 SCT limit register LIMIT address 0x5000 4008 bit description 124 Table 111 SCT halt condition register HALT address 0x5004 400C bit description Table 112 SCT stop condition register STOP address 0x5000 4010 bit description Table 113 SCT start condition register START address 0x5000 4014 bit description Table 114 SCT counter register COUNT address 0x5000 4040 bit 126 Table 115 SCT state register STATE address 0x5000 4044 bit 126 Table 116 SCT input register INPUT address 0x5000 4048 bit 127 Table 117 SCT match capture registers mode register REGMODE address 0x5000 404C bit description 128 Table 118 SCT output register OUTPUT address 0x5000 4050 bit description 128 Table 119 SCT bidirectional output control register OUTPUTDIRCTRL address 0x5000 4054 bit description 128 Table 120 SCT conflict resolution register RES address 0x5000 4058 bit description Table 121 SCT flag enable register EVEN a
30. NXP Semiconductors U M1 0601 8 6 7 8 6 8 UM10601 Chapter 8 LPC800 Pin interrupts pattern match engine Table 85 Pin interrupt active level or falling edge interrupt set register SIENF address 0xA000 4014 bit description Bit Symbol Description Reset Access value 7 0 SETENAF Ones written to this address set bits in the IENF thus NA WO enabling interrupts Bit n sets bit n in the IENF register 0 No operation 1 Select HIGH active interrupt or enable falling edge interrupt 31 8 Reserved Pin interrupt active level or falling edge interrupt clear register For each of the 8 pin interrupts selected in the PINTSELn registers see Section 4 6 27 one bit in the CIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register e If the pin interrupt mode is edge sensitive PMODE 0 the falling edge interrupt is cleared e If the pin interrupt mode is level sensitive PMODE 1 the LOW active interrupt is selected Table 86 Pin interrupt active level or falling edge interrupt clear register CIENF address 0xA000 4018 bit description Bit Symbol Description Reset Access value 7 0 CENAF Ones written to this address clears bits in the IENF thus NA WO disabling interrupts Bit n clears bit n in the IENF register 0 No operation 1 LOW active interrupt selected or falling edge interrupt disabled 31 8 Reserved
31. On the LPC800 most functions can be assigned through the switch matrix to any external pin that is not a power or ground pin These functions are called movable functions A few functions like the crystal oscillator pins XTALIN XTALOUT or the analog comparator inputs can only be assigned to one particular external pin with the appropriate electrical characteristics These functions are called fixed pin functions If a fixed pin function is not used it can be replaced by any other movable function For fixed pin analog functions the switch matrix enables the analog input or output and disables the digital pad GPIOs are special fixed pin functions Each GPIO is assigned to one and only one external pin by default External pins are therefore identified by their fixed pin GPIO function The level on a digital input is always reflected in the GPIO port register and in the pin interrupt pattern match state if selected regardless of which digital function is assigned to the pin through the switch matrix UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 105 of 326 NXP Semiconductors U M1 0601 Chapter 9 LPC800 Switch matrix SYSCON PIN PINTSEL 7 0 INTERRUPT ackage 9 digital input SPIO DIGITAL PAD digital output PIO0 m D digital output ena analog ena ANALOG PAD analog i o
32. Preliminary user manual Rev 1 1 24 January 2013 195 of 326 NXP Semiconductors U M1 0601 Chapter 16 LPC800 I2C bus interface Table 171 I2C Status register STAT address 0x4005 0004 bit description continued Bit Symbol Value Description Reset Access value 24 EVENTTIMEOUT Event Time out Interrupt flag Indicates when the time between 0 W1 events has been longer than the time specified by the TIMEOUT register Events include Start Stop and clock edges The flag is cleared by writing a 1 to this bit No time out is created when the I2C bus is idle 0 No time out 12C bus events have not caused a time out Event time out The time between 12 bus events has been longer than the time specified by the I2C TIMEOUT register 25 SCLTIMEOUT SCL Time out Interrupt flag Indicates when SCL has remained low 0 W1 longer than the time specific by the TIMEOUT register The flag is cleared by writing a 1 to this bit 0 No time out SCL low time has not caused a time out Time out SCL low time has caused a time out 31 26 Reserved Read value is undefined only zero should be written NA NA Table 172 Master function state codes MSTSTATE MstState Description Actions 0 Idle The Master function is available to be used for a new Send a Start or disable MstPending interrupt if transaction the Master function is not needed currently 1 Received data is available Master Receiver mode Address Read data and eit
33. Rd lt imm gt ADCS Rd Rd Rm ADD SP SP lt gt ADD Rd SP lt imm gt ADR Rd label SUBS Rd Rn Rm SUBS Rd Rn lt imm gt SUBS Rd Rd lt imm gt SBCS Rd Rd Rm SUB SP SP lt imm gt RSBS Rd Rn 0 MULS Rd Rm Rd CMP Rn Rm CMN Rn Rm CMP Rn lt imm gt All information provided in this document is subject to legal disclaimers Cycles a ope oe oe or oe oe oe oe os om amp op S S Ln NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 308 of 326 NXP Semiconductors UM10601 Table 287 Cortex MO instruction summary Chapter 27 LPC800 Appendix Operation Logical Shift Rotate Load Store Push Pop UM10601 Description AND Exclusive OR OR Bit clear Move NOT AND test Logical shift left by immediate Logical shift left by register Logical shift right by immediate Logical shift right by register Arithmetic shift right Arithmetic shift right by register Rotate right by register Word immediate offset Halfword immediate offset Byte immediate offset Word register offset Halfword register offset Signed halfword register offset Byte register offset Signed byte register offset PC relative SP relative Multiple excluding base Multiple including base Word immediate offset Halfword immediate offset Byte immediate offset Word register offset Halfword register of
34. Reserved Reset value 1 tbd UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 114 of 326 10 1 How to read UM10601 Chapter 10 LPC800 State Configurable Timer SCT Rev 1 1 24 January 2013 Preliminary user manual this chapter The SCT is available on all LPC800 parts 10 2 Features Two 16 bit counters or one 32 bit counter Counters clocked by bus clock or selected input Up counters or up down counters State variable allows sequencing across multiple counter cycles The following conditions define an event a counter match condition an input or output condition a combination of a match and or and input output condition in a specified state and the count direction Events control outputs interrupts and the SCT states Match register 0 can be used as an automatic limit n bi directional mode events can be enabled based on the count direction Match events can be held until another qualifying event occurs Selected events can limit halt start or stop a counter Supports 4inputs 4 outputs 5match capture registers 6 events 2 states 10 3 Basic configuration Configure the SCT as follows Use the SYSAHBCLKCTRL register Table 18 to enable the clock to the SCT register interface and peripheral clock Th
35. 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 lt Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 59 of 326 NXP Semiconductors UM10601 6 5 5 PIOO 4 register Table 53 PIOO 4 register PIOO 4 address 0x4004 4010 bit description Chapter 6 LPC800 I O configuration IOCON Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor e
36. 79 0x0000 1000 0x0000 13FF yes yes 5 1 80 95 0x0000 1400 0x0000 17FF yes yes 6 1 96 111 0x0000 1800 0x0000 1BFF yes yes 7 1 112 127 0x0000 1C00 0x0000 1FFF yes yes 8 1 128 143 0x0000 2000 0x0000 23FF yes 9 1 144 159 0x0000 2400 0x0000 27FF yes 10 1 160 175 0x0000 2800 0x0000 2BFF yes 11 1 176 191 0x0000 2 00 0x0000 2FFF yes 12 1 192 207 0 0000 3000 0x0000 33FF yes 13 1 208 223 0 0000 3400 0x0000 37FF yes 14 1 224 239 0 0000 3800 0x0000 3BFF yes 15 1 240 255 0 0000 3C00 0x0000 3FFF yes Flash content protection mechanism The part is equipped with the Error Correction Code ECC capable Flash memory The purpose of an error correction module is twofold The ECC first decodes data words read from the memory into output data words Then the ECC encodes data words to be written to the memory The error correction capability consists of single bit error correction with Hamming code The operation of the ECC is transparent to the running application The ECC content itself is stored in a flash memory not accessible by the user s code to either read from it or write into it on its own 6 bit of ECC corresponds to every consecutive 32 bit of the user accessible Flash Consequently Flash bytes from 0x0000 0000 to 0x0000 0003 are protected by the first 6 bit ECC Flash bytes from 0x0000 0004 to 0x0000 0007 are protected by the second 6 bit ECC byte etc Whenever the CPU requests
37. Post delay 0 2 clock stall Modetcpar 9 sk VPP VS Mode3 CPOL 1 sck Y a ae ee V Wd Vd Y X YMsB LSB MSB MiSo Y MS8 LSB 5 Y LSB 4 First data frame Second data frame Fig 38 Examples of data stalls UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 231 of 326 UM10601 Chapter 18 LPC800 Cyclic Redundancy Check CRC engine Rev 1 1 24 January 2013 Preliminary user manual 18 1 How to read this chapter The CRC engine is available on all LPC800 parts 18 2 Features Supports three common polynomials CRC CCITT CRC 16 and CRC 32 CRC CCITT x16 x12 5 1 CRC 16 x8 x15 2 1 32 x32 x26 x23 x22 x16 x12 4 x11 x10 4 8 4x74 x54 x44 2 x 1 Bit order reverse and 1 s complement programmable setting for input data and CRC sum Programmable seed number setting Supports CPU PIO back to back transfer Accept any size of data width per write 8 16 or 32 bit 8 bit write 1 cycle operation 16 bit write 2 cycle operation 8 bit x 2 cycle 32 bit write 4 cycle operation 8 bit x 4 cycle 18 3 Basic configuration Enable the clock to the CRC engine in the SYSAHBCLKCTRL register Table 18 bit 13 18 4 Pin description The CRC engine has no configurable pin
38. Reserved 21 16 HALTMSK H If bit n is one event n sets the HALT H bit in the CTRL register 0 event 0 bit 16 event 1 bit 17 event 5 bit 21 31 22 Reserved SCT stop condition register If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers STOPT_L and STOP_H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 124 of 326 NXP Semiconductors U M1 0601 Chapter 10 LPC800 State Configurable Timer SCT Table 112 SCT stop condition register STOP address 0x5000 4010 bit description Bit Symbol Description Reset value 5 0 STOPMSK L If bit n is one event n sets the STOP L bit in the CTRL register 0 event 0 bit 0 event 1 bit 1 event 5 bit 5 156 Reserved 21 16 STOPMSK If bit n is one event n sets the STOP bit in the CTRL register 0 event 0 bit 16 event 1 bit 17 event 5 bit 21 31 22 Reserved 10 6 6 SCT start condition register If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers START L and START Both the L and H registers can be rea
39. SCT bidirectional output control register OUTPUTDIRCTRL address 0x5000 4054 bit description Bit Symbol Value Description Reset value 3 2 SETCLR1 Set clear operation on output 1 Value 0x3 is reserved Do not program this value 0 0x0 Any Set and clear do not depend on any counter 0x1 L counting down Set and clear are reversed when counter L or the unified counter is counting down 0x2 H counting down Set and clear are reversed when counter H is counting down Do not use if UNIFY 1 5 4 SETCLR2 Set clear operation on output 2 Value 0x3 is reserved Do not program this value 0 0x0 Any Set and clear do not depend on any counter 0x1 L counting down Set and clear are reversed when counter L or the unified counter is counting down 0x2 H counting down Set and clear are reversed when counter H is counting down Do not use if UNIFY 1 7 6 SETCLR3 Set clear operation on output 3 Value 0x3 is reserved Do not program this value 0 0x0 Any Set and clear do not depend on any counter 0x1 L counting down Set and clear are reversed when counter L or the unified counter is counting down 0x2 H counting down Set and clear are reversed when counter H is counting down Do not use if UNIFY 1 31 8 Reserved 5 10 6 13 SCT conflict resolution register UM10601 The registers OUTn_SETn Section 10 6 24 and OUTnCLRn Section 10 6 25 allow both setting and clearing to be indicated for an output in the same clock cycle even for the same
40. SLVADR2 R W 0x50 Slave address 2 0x01 Table 184 SLVADR3 R W 0x54 Slave address 3 0x01 Table 184 SLVQUALO R W 0x58 Slave Qualification for address 0 0 Table 185 MONRXDAT RO 0x80 Monitor receiver data register 0 Table 186 16 6 1 12C Configuration register The CFG register contains mode settings that apply to Master Slave and Monitor functions Table 170 12C Configuration register CFG address 0x4005 0000 bit description Bit Symbol Value Description Reset Value 0 MSTEN Master Enable When disabled configurations settings for 0 the Master function are not changed but the Master function is internally reset 0 Disabled The 12C Master function is disabled 1 Enabled The I C Master function is enabled 1 SLVEN Slave Enable When disabled configurations settings for 0 the Slave function are not changed but the Slave function is internally reset 0 Disabled The 12C slave function is disabled Enabled The I C slave function is enabled UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 191 of 326 NXP Semiconductors UM10601 UM10601 Chapter 16 LPC800 I2C bus interface Table 170 12C Configuration register CFG address 0x4005 0000 bit description Bit Symbol 2 MONEN 3 TIMEOUTEN 4 MONCLKSTR 31 5 Value Description Reset Value Monitor Enable W
41. Some status flags can be 0 0102 Table 191 cleared by writing a 1 to that bit position All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 213 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 Table 188 Register overview SPI base address 0x4005 8000 SPIO and 0x4008 C000 SPI1 continued Name Access Offset Description Reset Reference value INTENSET R W Ox00C SPI Interrupt Enable read and Set 0 Table 192 complete value may be read from this register Writing a 1 to any implemented bit position causes that bit to be set INTENCLR W 0x010 SPI Interrupt Enable Clear Writinga1 NA Table 193 to any implemented bit position causes the corresponding bit in INTENSET to be cleared RXDAT R 0x014 SPI Receive Data NA Table 194 TXDATCTL R W 0x018 SPI Transmit Data with Control 0 Table 195 TXDAT R W Ox01C SPI Transmit Data 0 Table 196 TXCTL R W 0x020 Transmit Control 0 Table 197 DIV R W 0x024 SPI clock Divider 0 Table 198 INTSTAT R 0x028 Interrupt Status 0x02 Table 199 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 214 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 17 6 1 SPI Configuration register The CFG register
42. The minimum time that SSEL is deasserted is 3 SPI clock times OxF The minimum time that SSEL is deasserted is 16 SPI clock times 31 16 Reserved Read value is undefined only zero should be written NA UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 216 of 326 NXP Semiconductors UM10601 Chapter 17 LPC800 SPI0 1 17 6 3 SPI Status register The STAT register provides SPI status flags for software to read and a control bit for forcing an end of transfer Flags other than read only flags may be cleared by writing ones to corresponding bits of STAT STAT contains 2 error flags in slave mode only RXOV and TXUR These are receiver overrun and transmit underrun respectively If either of these errors occur during operation the SPI should be disabled then re enabled in order to make sure all internal states are cleared before attempting to resume operation In this register the following notation is used RO Read only W1 write 1 to clear Table 191 SPI Status register STAT addresses 0x4005 8008 SPIO 0x4005 C008 SPI1 bit description Bit Symbol 0 RXRDY 1 TXRDY 2 RXOV 3 TXUR 4 SSA 5 SSD 6 STALLED UM10601 Description Receiver Ready flag When 1 indicates that data is available to be read from the receiver buffer Cleared after a read of the RXDAT
43. The transmitter uses the CTS input or RTS output in loopback mode for flow control purposes 10 Reserved Read value is undefined only zero should be NA written 11 SYNCEN Selects synchronous or asynchronous operation 0 0 Asynchronous mode is selected Synchronous mode is selected 12 CLKPOL Selects the clock polarity and sampling edge of received 0 data in synchronous mode 0 Falling edge Un RXD is sampled on the falling edge of SCLK 1 Rising edge Un RXD is sampled on the rising edge of SCLK 13 Reserved Read value is undefined only zero should be NA written 14 SYNCMST Synchronous mode Master select 0 0 Slave When synchronous mode is enabled the USART is a slave 1 Master When synchronous mode is enabled the USART is a master 15 LOOP Selects data loopback mode 0 0 Normal operation Loopback mode This provides a mechanism to perform diagnostic loopback testing for USART data Serial data from the transmitter Un TXD is connected internally to serial input of the receive Un RXD Un TXD and Un RTS activity will also appear on external pins if these functions are configured to appear on device pins The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN 31 16 Reserved Read value is undefined only zero should be NA written 15 6 2 USART Control register The CTRL register controls aspects of USART operation that are more likely to change during operation UM10
44. This function is selected by default 0 Enable SWCLK This function is enabled on pin PIOO 3 Disable SWCLK GPIO function PIOO 3 is selected on this pin Any other movable function can be assigned to pin PIOO 3 3 SWDIO EN Enables fixed pin function Writing a 1 deselects the function and any movable 0 function can be assigned to this pin This function is selected by default 0 Enable SWDIO This function is enabled on pin PIOO 2 Disable SWDIO GPIO function PIOO 2 is selected on this pin Any other movable function can be assigned to pin PIOO 2 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 113 of 326 NXP Semiconductors UM10601 Chapter 9 LPC800 Switch matrix Table 105 Pin enable register 0 PINENABLEO address 0x4000 C1C0 bit description Bit Symbol Value 4 XTALIN EN 5 XTALOUT EN 6 RESET EN 7 CLKIN 8 VDDCMP 31 9 Description Enables fixed pin function Writing a 1 deselects the function and any movable function can be assigned to this pin By default the fixed pin function is deselected and GPIO is assigned to this pin Enable XTALIN This function is enabled on pin PIOO 8 Disable XTALIN GPIO function PIOO 8 default or any other movable function can be assigned to pin PIOO 8 Enables fixed pin function Writing a 1 deselects the function and any movable function can be
45. bit description Bit Symbol Value Description Reset value 0 MSTCONTINUE Master Continue This bit is write only 0 0 No effect Continue Informs the Master function to continue to the next operation This must done after writing transmit data reading received data or any other housekeeping related to the next bus operation UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 201 of 326 NXP Semiconductors U M1 0601 16 6 9 UM10601 Chapter 16 LPC800 I2C bus interface Table 179 Master Control register MSTCTL address 0x4005 0020 bit description Bit Symbol Value Description Reset value 1 MSTSTART Master Start control This bit is write only 0 0 No effect Start A Start will be generated on the 12 bus at the next allowed time 2 MSTSTOP Master Stop control This bit is write only 0 0 No effect 1 Stop A Stop will be generated on the I C bus at the next allowed time preceded by a NACK to the slave if the master is receiving data from the slave Master Receiver mode 31 Reserved Read value is undefined only zero should be NA 2 written Master Time The MSTTIME register allows programming of certain times that may be controlled by the Master function These include the clock SCL high and low times repeated Start setup time and transmitted data setup time The I2
46. err code is the return state of the function An 0 indicates success All non zero indicates an error Refer to Error Table e 2C PARM is a structure with parameters passed to the function Refer to Section 23 4 22 e 2C RESULT is a containing the results after the function executes To initiate a master mode write read the I2C_PARAM has to be setup I2C PARAM is a structure with various variables needed by the I2C ROM Driver to operate correctly The structure contains the following e Number of bytes to be transmitted Number of bytes to be receive Pointer to the transmit buffer Pointer to the receive buffer Pointer to callback function Stop flag The RESULT structure contains the results after the function executes The structure contains the following Number of bytes transmitted Number of bytes received Remark The number of bytes transmitted will be updated for i2c master transmit intr and i2c master transmit poll The number of bytes received will only be update on i2c master receive poll i2c master receive intr i2c master tx rx poll and i2c master tx rx intr All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 289 of 326 NXP Semiconductors U M1 0601 23 5 5 UM10601 Chapter 23 LPC800 I2C bus ROM API In all the master mode routines
47. i2c setup LPC I2C BASE uint32 t amp I2C Handle 0 error code pI2cApi i2c set bitrate I2C HANDLE T i2c handle PCLK in Hz bps in hz error code pI2cApi i2c set slave addr I12C HANDLE T i2c handle slave slave addr mask UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 288 of 326 NXP Semiconductors U M1 0601 23 5 4 UM10601 Chapter 23 LPC800 I2C bus ROM API 12C Master Transmit Receive The Master mode drivers give the user the choice of either polled wait for the message to finish or interrupt driven routines non blocking Polled routines are recommended for testing purposes or very simple I2C applications These routines allow the Master to send to Slaves with 7 bit or 10 bit addresses The following routines are polled routines err code i2c master transmit poll I2C HANDLE T I2C PARAM I2C RESULT err code i2c master receive poll I2C HANDLE T I2C PARAM I2C RESULT err code i2c master tx rx poll I2C HANDLE T I2C PARAM I2C RESULT The following routines are interrupt driven routines err code i2c master transmit intr I2C HANDLE T I2C PARAM I2C RESULT err code i2c master receive intr I2C HANDLE T I2C PARAM I2C RESULT err code i2c master tx rx intr I2C HANDLE T I2C PARAM I2C RESULT Where
48. uint32 ti2c get firmware version void None 12C ROM Driver version number Returns the version number The firmware version is an unsigned 32 bit number 12C Get Status Table 269 12 Get Status Routine Prototype Input parameter Return Description I2C Get Status 12 MODE T i2c get status I2C HANDLE I2C HANDLE T Handle to the allocated SRAM area Status code Returns status code The status code indicates the state of the I2C bus Refer to I2C Status Code Table All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 284 of 326 NXP Semiconductors UM10601 23 4 18 23 4 19 Error codes Table 271 Error codes Chapter 23 LPC800 I2C bus ROM API 12C time out value Table 270 12 time out value Routine Prototype Input parameter Return Description 12C time out value ErrorCode ti2c set timeout I2C HANDLE T h i2c uint32 t timeout I2C HANDLE T Handle to the allocated SRAM area uint32 t timeout time value is timeout 16 i2c function clock If timeout 0 timeout feature is disabled Status code Returns status code The status code indicates the state of the I2C bus Refer I2C Status Code Table Error Code Description Comment 0 Successful completion Function was completed successfully 1 General error 0x000
49. value 15 0 DATA Transmit Data This field provides from 4 to 16 bits of data to be 0 transmitted 31 16 Reserved Only zero should be written NA 17 6 9 SPI Transmitter Control register UM10601 The TXCTL register provides a way to separately access control information for the SPI These bits are another view of the same named bits in the TXDATCTL register see Section 17 6 7 Changing bits in TXCTL has no effect unless data is later written to the TXDAT register Data written to TXDATCTL overwrites the TXCTL register When control information needs to be changed during transmission the TXDATCTL register should be used see Section 17 6 7 instead of TXDAT Control information can then be written along with data All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 222 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 Table 197 SPI Transmitter Control register TXCTL addresses 0x4005 8020 SPIO 0x4005 C020 SPI1 bit description Bit Symbol Description Reset value 15 0 Reserved Read value is undefined only zero should be written 16 TX SSEL Transmit Slave Select 0x0 19 17 Reserved 0x0 20 EOT End of Transfer 0 21 EOF End of Frame 0 22 RXIGNORE Receive Ignore 0 23 Reserved Read value is undefined only zero should be written NA 27 24 FLEN Frame Length 0x
50. 1 3 3 Changing the divider values Changing the divider ratio while the PLL is running is not recommended As there is no way to synchronize the change of the MSEL and PSEL values with the dividers the risk exists that the counter will read in an undefined value which could lead to unwanted spikes or drops in the frequency of the output clock The recommended way of changing between divider settings is to power down the PLL adjust the divider settings and then let the PLL start up again 4 7 1 4 Frequency selection The PLL frequency equations use the following parameters also see Figure 4 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 39 of 326 NXP Semiconductors U M1 0601 4 7 1 4 1 4 7 1 4 2 UM10601 Chapter 4 LPC800 System configuration SYSCON Table 39 PLL frequency parameters Parameter System PLL FCLKIN Frequency of sys pllclkin input clock to the system PLL from the SYSPLLCLKSEL multiplexer see Section 4 6 8 FCCO Frequency of the Current Controlled Oscillator CCO 156 to 320 MHz FCLKOUT Frequency of sys pllclkout This is the PLL output frequency and must be 100 MHz P System PLL post divider ratio PSEL bits in SYSPLLCTRL see Section 4 6 3 M System PLL feedback divider register MSEL bits in SYSPLLCTRL see Section 4 6 3 Normal mode In this mode th
51. 16 7 1 16 7 1 1 16 7 2 UM10601 Bus rates and timing considerations Due to the nature of the I C bus it is generally not possible to guarantee a specific clock rate on the SCL pin On the I2C bus the The clock can be stretched by any slave device extended by software overhead time etc In a multi master system the master that provides the shortest SCL high time will cause that time to appear on SCL as long as that master is participating in I2C traffic i e when it is the only master on the bus or during arbitration between masters Rate calculations give a base frequency that represents the fastest that the IC bus could operate if nothing slows it down Rate calculations SCL high time in 12C function clocks CLKDIV 1 MSTSCLHIGH 2 SCL low time in I C function clocks CLKDIV 1 MSTSCLLOW 2 Nominal SCL rate I C function clock rate SCL high time SCL low time Time out A time out feature on an I C interface can be used to detect a stuck bus and potentially do something to alleviate the condition Two different types of time out are supported Both types apply whenever the I C block and the time out function are both enabled Master Slave or Monitor functions do not need to be enabled In the first type of time out reflected by the EVENTTIMEOUT flag in the STAT register the time between bus events governs the time out check These events include Start Stop and all changes on the I C
52. 293 Fig 49 Connecting the SWD pins to a standard SWD GOIlDe ctor eet trem prse 301 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 318 of 326 NXP Semiconductors U M1 0601 Chapter 28 Supplementary information 28 6 Contents Chapter 1 LPC800 Introductory information 1 1 Introduction 3 1 4 Block diagram 6 1 2 Features lr 3 1 5 General description 7 1 3 Ordering 5 1 5 1 ARM Cortex M0 core configuration 7 Chapter 2 LPC800 Memory mapping 2 1 How to read this chapter 8 2 2 1 Memory 9 2 2 General 8 2 2 2 Micro Trace Buffer 9 Chapter 3 LPC800 Nested Vectored Interrupt Controller NVIC 3 1 How to read this chapter 10 3 3 1 Interrupt sources 10 3 2 F al res osse Rana Roa KERERE 10 332 Non Maskable Interrupt NMI 12 3 3 General 10 3 3 3 Vector table offset 12 Chapter 4 LPC800 System configuration SYSCON 4 1 How to read this chapter 13 4 6 17 CLKOUT clock d
53. 5 Pin interrupt active level or falling edge interrupt 92 enable register 88 8 6 13 Pattern Match Interrupt Bit Slice Configuration 8 6 6 Pin interrupt active level or falling edge interrupt I6dglStOl is cse pe hha ph se bate 94 set 89 87 Functional description 99 8 6 7 Pin interrupt active level or falling edge interrupt 8 7 1 Pin interrupts 99 clear register DM LIT IE 89 872 Pattern Match engine example 100 8 6 8 Pin interrupt rising edge register 90 8 7 3 Pattern match engine edge detect examples 101 8 6 9 Pin interrupt falling edge register 90 8 6 10 Pin interrupt status register 91 Chapter 9 LPC800 Switch matrix 9 1 How to read this chapter 103 9 5 1 Pin assign register O 109 92 103 952 Pin assign register 1 110 9 3 Basic 103 953 Pin assign register2 110 9 3 1 Connect an internal signal to a package pin 104 ae assign dedu y QU SE M 9 3 2 Enable an analog input or other special bs a MEN AL 104 58 Pin assign register E id NS 9 5 7 Pin assign register 6 112 9 4 General description EORR 105 9 5 8 Pin assign register 7
54. 6 3 Boot process flowchart RESET INITIALIZE no CRP1 2 3 ENABLED v ENABLE DEBUG USER CODE VALID WATCHDOG FLAG SET CRP3 NO ISP no ENABLED ENTER ISP MODE 1 LOW Y EXECUTE INTERNAL USER CODE USER CODE VALID boot from UART Y RUN AUTO BAUD M AUTO BAUD SUCCESSFUL RECEIVE CRYSTAL FREQUENCY 1 RUN UART ISP COMMAND HANDLER 1 This step is included for backward compatibility and the response is ignored by the boot loader Fig 41 Boot process flowchart UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 246 of 326 UM10601 Chapter 21 LPC800 Flash ISP and IAP programming Rev 1 1 24 January 2013 Preliminary user manual 21 1 How to read this chapter See Table 213 for different flash configurations Table 213 LPC800 flash configurations Type number Flash LPC810M021FN8 4kB LPC811M001FDH16 8 kB LPC812M101FDH16 16 kB LPC812M101FD20 16 kB LPC812M101FDH20 16 kB 21 2 Features n System Programming In System programming ISP is programming or reprogramming the on chip flash memory using the bootloader software and UART serial port n Application Programming In Application IAP programming is performing erase and write operatio
55. All other values are reserved Idle The Master function is available to be used for a new transaction Receive ready Received data available Master Receiver mode Address plus Read was previously sent and Acknowledged by slave Transmit ready Data can be transmitted Master Transmitter mode Address plus Write was previously sent and Acknowledged by slave NACK Address Slave NACKed address NACK Data Slave NACKed transmitted data Master Arbitration Loss flag This flag can be cleared by software 0 W1 writing a 1 to this bit It is also cleared automatically a 1 is written to MSTCONTINUE No loss No Arbitration Loss has occurred Arbitration loss The Master function has experienced an Arbitration Loss At this point the Master function has already stopped driving the bus and gone to an idle state Software can respond by doing nothing or by sending a Start in order to attempt to gain control of the bus when it next becomes idle Reserved Read value is undefined only zero should be written NA NA All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 193 of 326 NXP Semiconductors UM10601 Chapter 16 LPC800 I2C bus interface Table 171 I2C Status register STAT address 0x4005 0004 bit description continued Bit Symbol 6 MSTSTSTPERR SLVPENDING 10 9 SLVSTATE 11 SLVNOTSTR
56. All rights reserved Preliminary user manual Rev 1 1 24 January 2013 78 of 326 NXP Semiconductors U M1 0601 7 7 3 7 7 4 UM10601 Chapter 7 LPC800 GPIO port e Writing to a Byte Pin register loads the output bit from the least significant bit Writing to a Word Pin register loads the output bit with the OR of all of the bits written This feature follows the definition of truth of a multi bit value in programming languages Writing to a port s PORT register loads the output bits of all the pins written to Writing to a port s MPORT register loads the output bits of pins identified by zeros in corresponding positions of the port s MASK register Writing ones to a port s SET register sets output bits Writing ones to a port s CLR register clears output bits Writing ones to a port s NOT register toggles complements inverts output bits The state of a port s output bits can be read from its SET register Reading any of the registers described in Section 7 7 1 returns the state of pins regardless of their direction or alternate functions Masked I O A port s MASK register defines which of its pins should be accessible in its MPORT register Zeroes in MASK enable the corresponding pins to be read from and written to MPORT Ones in MASK force a pin to read as 0 and its output bit to be unaffected by writes to MPORT When a port s MASK register contains all zeros its PORT and MPORT registers op
57. At least one of the four slave addresses has been matched by hardware Slave receive Received data is available Slave Receiver mode Slave transmit Data can be transmitted Slave Transmitter mode Reserved Slave Not Stretching Indicates when the slave function is stretching 1 RO the 12C clock This is needed in order to gracefully invoke Deep Sleep or Power down modes during slave operation This read only flag reflects the slave function status in real time Stretching The slave function is currently stretching the 12 bus clock Deep Sleep or Power down mode cannot be entered at this time Not stretching The slave function is not currently stretching the 2 bus clock Deep sleep or Power down mode could be entered at this time Slave address match Index This field is valid when the I C slave 0 RO function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers and provides an identification of the address that was matched It is possible that more than one address could be matched but only one match can be reported here Slave address 0 was matched Slave address 1 was matched Slave address 2 was matched Slave address 3 was matched All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 194 of 326 NXP Semiconductors
58. B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 145 of 326 NXP Semiconductors U M1 0601 Chapter 11 LPC800 Multi Rate Timer MRT Table 134 Register overview MRT base address 0x4000 4000 Name Access Address Description Reset value Reference offset INTVAL3 R W 0x30 MRTS Time interval value register This value is 0 Table 135 loaded into the TIMERS register TIMER3 R W 0x34 MRT3 Timer register This register reads the value Ox7FFFFFFF Table 136 of the down counter CTRL3 R W 0x38 Control register This register controls the 0 Table 137 MRT modes R W Ox3C MRTS Status register 0 Table 138 IDLE CH R OxF4 Idle channel register This register returns the 0 Table 139 number of the first idle channel IRQ_FLAG R W OxF8 Global interrupt flag register 0 Table 140 11 6 1 Time interval register This register contains the MRT load value and controls how the timer is reloaded The load value is IVALUE 1 Table 135 Time interval register INTVAL 0 3 address 0x4000 4000 INTVALO to 0x4000 4030 INTVAL3 bit description Bit Symbol Value Description Reset value 30 0 IVALUE Time interval load value This value is loaded into the 0 TIMERn register and the MRTn starts counting down from IVALUE 1 If the timer is idle writing a non zero value to this bit field starts the timer immediately If the timer is running writing a zero to this bit field does
59. CPOL 1 SCK SSEL lt gt lt gt Pre_delay Data frame Post_delay Pre and post delay CPHA 1 Pre_delay 2 Post_delay 1 Mode 1 CPOL 0 SCK Mode 3 CPOL 1 SCK SSEL gt lt Pre delay Data frame Post delay Fig 35 Pre delay and Post delay UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 226 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 17 7 2 2 Frame delay The Frame delay value controls the amount of time at the end of each frame This delay is inserted when the EOF bit 1 Frame delay is illustrated by the examples in Figure 36 Note that frame boundaries occur only where specified This is because frame lengths can be any size involving multiple data writes See Section 17 7 5 for more information Frame delay 0 Frame delay 2 Pre delay 0 Post delay 0 fo ah ane d Lo ae ie NEC NINE CUN TRU lt gt lt gt lt gt First data frame Frame delay Second data frame Frame delay 1 Frame delay 2 Pre delay 0 Post delay 0 wieso sx wescensg s VELL UAL sc L liiihiliiliig 4 gt lt T gt First data frame Frame delay Second data frame Fig 36 Frame delay UM10601 All information provided in this document is subject to legal di
60. Description Reset value 7 0 LATENCY 8 bit latency value 0x010 31 8 Reserved NMI source selection register The NMI source selection register selects a peripheral interrupt as source for the NMI interrupt of the ARM Cortex MO core For a list of all peripheral interrupts and their IRQ numbers see Table 3 For a description of the NMI functionality see Section 3 3 2 Table 31 NMI source selection register NMISRC address 0x4004 8174 bit description Bit Symbol Description Reset value 4 0 IRQNO The IRQ number of the interrupt that acts as the Non Maskable Interrupt 0 NMI if bit 31 is 1 See Table 3 for the list of interrupt sources and their IRQ numbers 30 5 Reserved 31 NMIEN Write a 1 to this bit to enable the Non Maskable Interrupt NMI source 0 selected by bits 4 0 Remark If the NMISRC register is used to select an interrupt as the source of Non Maskable interrupts and the selected interrupt is enabled one interrupt request can result in both a Non Maskable and a normal interrupt This can be avoided by disabling the normal interrupt in the NVIC Pin interrupt select registers Each of these 8 registers selects one pin from all digital pins as the source of a pin interrupt or as the input to the pattern match engine To select a pin for any of the eight pin interrupts or pattern match engine inputs write the GPIO port pin number as 0 to 17 for pins PIOO 0 to PIOO 17 to the INTPIN bits For example
61. HALT is 0 the L or unified counter does not run but I O events 0 related to the counter can occur If such an event matches the mask in the Start register this bit is cleared and counting resumes 2 HALT L When this bit is 1 the L or unified counter does not run and no events can occur 1 reset sets this bit When the HALT L bit is one the STOP L bit is cleared If you want to remove the halt condition and keep the SCT in the stop condition not running then you can change the halt and stop condition with one single write to this register Remark Once set only software can clear this bit to restore counter operation UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 122 of 326 NXP Semiconductors UM10601 Chapter 10 LPC800 State Configurable Timer SCT Table 109 SCT control register CTRL address 0x5000 4004 bit description Bit Symbol Value Description Reset value 3 CLRCTR L Writing a 1 to this bit clears the L or unified counter This bit always reads as 0 0 BIDIR L L or unified counter direction select 0 0 Up The counter counts up to its limit condition then is cleared to zero 125 PREL 15 13 16 DOWNH 17 STOP H 18 HALT 19 CLRCTR H 20 BIDIR H 28 21 31 29 Bidirectional The counter counts up to its limit then counts down to a li
62. L 4 y Fig 17 Capture logic 10 7 3 Event selection State variables allow control of the SCT across more than one cycle of the counter Counter matches input output edges and state values are combined into a set of general purpose events that can switch outputs request interrupts and change state UM10601 values All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 136 of 326 NXP Semiconductors U M1 0601 Chapter 10 LPC800 State Configurable Timer SCT H matches select L matches MATCHSELi inputs uin oda select event i outputs IOSELi OUTSELi IOCONDi COMBMODEi STATEMASKi select H STATE L STATE HEVENTi Fig 18 Event selection 10 7 4 Output generation Figure 19 shows one output slice of the SCT Events gt Set NoChangeConflict i register i SETCLRi OUT Select m gt Output i OiRES reg Clear register i SCT clock Fi
63. Movable functions assign to pins PIOO 0 to PIO_17 through switch matrix Function name U2 RXD U2 RTS U2 CTS U2 SCLK SPIO_SCK SPIO_MOSI SPIO_MISO SPIO SSEL SPI1_SCK SPI1_MOSI SPI1_MISO SPI1_SSEL CTIN_O CTIN 1 CTIN 2 CTIN 3 CTOUT 0 CTOUT 1 CTOUT 2 CTOUT 3 I2C0 SCL I2C0_SDA ACMP_O CLKOUT Type y o y o GPIO INT BMAT Description Receiver input for USART2 Request To Send output for USART2 Clear To Send input for USART2 Serial clock input output for USART2 in synchronous mode Serial clock for SPIO Master Out Slave In for SPIO Master In Slave Out for SPIO Slave select for SPIO Serial clock for SPI Master Out Slave In for SPI Master In Slave Out for SPI1 Slave select for SPI SCT input 0 SCT input 1 SCT input 2 SCT input 3 SCT output 0 SCT output 1 SCT output 2 SCT output 3 I2C bus clock input output open drain if assigned to pin PIOO 10 High current sink only if assigned to 10 and if 12C Fast mode Plus is selected in the I O configuration register I C bus data input output open drain if assigned to pin PIOO 11 High current sink only if assigned to pin 11 and if I2C Fast mode Plus is selected in the I O configuration register Analog comparator output Clock output Output of the pattern match engine All information provided in this document is subject to legal disclaim
64. Output register when the H counter was not halted SCT match registers 0 to 4 REGMODEn bit 0 Match registers are compared to the counters to help create events When the UNIFY bit is 0 the L and registers are independently compared to the L and counters When UNIFY is 1 the L and H registers hold a 32 bit value that is compared to the unified counter A Match can only occur in a clock in which the counter is running STOP and HALT are both 0 Match registers can be read at any time Writing to a Match register while the associated counter is running does not affect the Match register and results in a bus error Match events occur in the SCT clock in which the counter is or would be incremented to the next value When a Match event limits its counter as described in Section 10 6 3 the value in the Match register is the last value of the counter before it is cleared to zero or decremented if BIDIR is 1 There is no write through from Reload registers to Match registers Before starting a counter software can write one value to the Match register used in the first cycle of the counter and a different value to the corresponding Match Reload register used in the second cycle All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 131 of 326 NXP Semiconductors U M1 0601 10 6 19 10 6 20 10 6
65. PIO0_8 XTALIN PIOO 9 XTALOUT PIOO 1 ACMP 2 CLKIN TDI 15 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 303 of 326 NXP Semiconductors U M1 0601 Chapter 26 LPC800 Packages and pin description PIOO 17 PIOO 14 PIOO 13 C PIOO 0 ACMP I1 TDO PIOO 12 PIOO_6 VDDCMP RESET PIOO 5 7 PIOO_4 WAKEUP TRST LPC812M101FDH20 Vss SWCLK PIO0_3 TCK TSSOP20 Vpp SWDIO PIOO 2 TMS PIOO 11 PIOO 10 16 PIOO 8 XTALIN PIOO 9 XTALOUT 1 ACMP IZ CLKIN TDI PIOO 15 aaa 003775 Fig 53 Pin configuration TSSOP20 package 26 2 Pin description The pin description table Table 285 shows the pin functions that are fixed to specific pins on each package These fixed pin functions are selectable between the GPIO comparator SWD and the XTAL pins By default the GPIO function is selected except on pins PIOO 2 PIOO 3 and PIOO 5 JTAG functions are available in boundary scan mode only Movable function for the I2C USART SPI and SCT pin functions can be assigned through the switch matrix to any pin that is not power or ground in place of the pin s fixed functions The following exceptions apply For full I2C bus compatibility assign the I2C functions to the open drain pins PIOO_11 and PIOO 10 Do not assign more than one output to an
66. SPIO 0x4005 C010 SPI1 bit description 220 Table 194 SPI Receiver Data register RXDAT addresses 0x4005 8014 SPIO 0x4005 C014 SPI1 bit description zi rune dtd e 220 Table 195 SPI Transmitter Data and Control register TXDATCTL addresses 0x4005 8018 SPIO 0x4005 C018 SPI1 bit description 221 Table 196 SPI Transmitter Data Register TXDAT addresses 0x4005 801C SPIO 0x4005 C01C SPI1 bit description 222 Table 197 SPI Transmitter Control register TXCTL addresses 0x4005 8020 SPIO 0x4005 C020 SPI1 bit description 223 Table 198 SPI Divider register DIV addresses 0x4005 8024 SPIO 0x4005 C024 SPI1 bit lt 223 Table 199 SPI Interrupt Status register INTSTAT addresses 0x4005 8028 SPIO 0x4005 C028 SPI1 bit description 223 Table 200 SPI mode summary 225 NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 316 of 326 NXP Semiconductors UM10601 Table 201 Register overview CRC engine base address 0x5000 0000 234 Table 202 CRC mode register MODE address 0x5000 0000 bit 234 Table 203 CRC seed register SEED address 0x5000 0004 bit 234 Table 204 CRC checksum
67. Specifies the factor by which the SCT clock is prescaled to produce the H counter 0 clock The counter clock is clocked at the rate of the SCT clock divided by PRELH 1 Remark Clear the counter by writing a 1 to the CLRCTR bit whenever changing the PRE value Reserved 10 6 3 SCT limit register If UNIFY 1 in CONFIG register only the L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers LIMIT L and LIMIT H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation The bits in this register set which events act as counter limits When a limit event occurs the counter is cleared to zero in unidirectional mode or changes the direction of count in bidirectional mode When the counter reaches all ones this state is always treated as a limit event and the counter is cleared in unidirectional mode or in bidirectional mode begins counting down on the next clock edge even if no limit event as defined by the SCT limit register has occurred UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 123 of 326 NXP Semiconductors U M1 0601 10 6 4 10 6 5 UM10601 Chapter 10 LPC800 State Configurable Timer SCT Note that in addition to using this register to specify events that serve as l
68. T handle CONFIG T set Routine uart get mem size Prototype uint32 ramsize in bytes uart get mem size void Input parameter None Return Memory size in bytes Description Get the memory size needed by one UART instance UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 294 of 326 NXP Semiconductors UM10601 24 4 2 24 4 3 24 4 4 24 4 5 UM10601 UART setup Chapter 24 LPC800 USART API ROM driver routines Table 275 uart_setup Routine Prototype Input parameter uart_setup UART HANDLE T setup uint32 t base addr uint8 t ram base addr Base address of register for this uart block ram Pointer to the memory space for uart instance The size of the memory space can be obtained by the uart get mem size function Return The handle to corresponding uart instance Description Setup UART instance with provided memory and return the handle to this instance UART init Table 276 uart init Routine uart init Prototype uint32 t uart init UART HANDLE T handle UART CONFIG set Input parameter handle The handle to the uart instance set configuration for uart operation Return Fractional divider value if System clock is not integer multiples of baud rate Description Setup baud rate and operation mode for uart then enable uart
69. Table 154 Control register CTRL address 0x4000 8000 bit description Bit Symbol Value Description Reset value 1 ALARMFLAG Wake up or alarm timer flag 0 No time out The self wake up timer has not timed out Writing a 0 to has no effect 1 Time out The self wake up timer has timed out This flag generates an interrupt request which can wake up the part from any reduced power mode including Deep power down if the clock source is the low power oscillator Writing a 1 clears this status bit 2 CLEARCTR Clears the self wake up timer 0 0 No effect Reading this bit always returns 0 1 Clear the counter Counting is halted until a new count value is loaded 31 3 Reserved 14 6 2 Count register Do not write to this register while the counting is in progress Remark In general reading the timer state is not recommended There is no mechanism to ensure that some bits of this register don t change while a read is in progress if the read happens to coincide with an self wake up timer clock edge If you must read this value it is recommended to read it twice in succession Table 155 Counter register COUNT address 0x4000 800C bit description Bit Symbol Description Reset value 31 0 VALUE A write to this register pre loads start count value into the timer and starts the count down sequence A read reflects the current value of the timer UM10601 All information provided in this document is subject to legal disclai
70. Table 17 System clock divider register SYSAHBCLKDIV Table 38 Device ID register DEVICE_ID address 0x4004 address 0x4004 8078 bit description 25 83F4 bit description 38 Table 18 System clock control register Table 39 PLL frequency parameters 40 SYSAHBCLKCTRL address 0x4004 8080 bit Table 40 PLL configuration examples 40 description 25 Table 41 Wake up sources for reduced power modes 43 Table 19 USART clock divider register UARTCLKDIV Table 42 Register overview PMU base address 0x4002 address 0x4004 8094 bit description 27 ie adobe das GR dae bash deed 43 Table 20 CLKOUT clock source select register Table 43 Power control register PCON address 0x4002 CLKOUTSEL address 0x4004 80E0 bit 0000 bit description 44 description 27 Table 44 General purpose registers 0 to GPREG 0 3 Table 21 CLKOUT clock source update enable register address 0x4002 0004 GPREGO to 0x4002 0010 CLKOUTUEN address 0x4004 80E4 bit GPREG3 bit description 44 COSCHPUON enses pam unes e X d 28 Table 45 Deep power down control register DPDCTRL Table 22 CLKOUT clock divider registers CLKOUTDIV address 0x4002 0014 bit description 45 address 0x4004 80E8 bit description 28 Table 46 Peripheral configuration in reduced power Table 23 USART fractional
71. UART get character Table 277 uart get char Routine uart get char Prototype uint8 t uart get char UART HANDLE T handle Input parameter handle The handle to the uart instance Return Received data Description Receive one Char from uart This functions is only returned after Char is received In case Echo is enabled the received data is sent out immediately UART put character Table 278 uart put char Routine uart put char Prototype void uart put char UART HANDLE T handle uint8 t data Input parameter Return Description handle The handle to the uart instance data data to be sent out None Send one Char through uart This function is only returned after data is sent All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 295 of 326 UM10601 Chapter 24 LPC800 USART API ROM driver routines NXP Semiconductors 24 4 6 UART get line Table 279 uart get line Routine uart get line Prototype uint32 t uart get line UART HANDLE T handle UART T param Input parameter handle The handle to the uart instance param Refer to T definition Return Error code ERR UART RECEIVE ON UART receive is ongoing Description Receive multiple bytes from UART 24 4 7 UART put line Table 280 uart put line Routine uart put line Prototype u
72. UM10601 Chapter 16 LPC800 I2C bus interface Table 171 I2C Status register STAT address 0x4005 0004 bit description continued Bit 14 15 16 17 18 19 Symbol SLVSEL SLVDESEL MONRDY MONOV MONACTIVE MONIDLE 23 20 UM10601 Value Description Reset Access value Slave selected flag SLVSEL is set after an address match when 0 software tells the Slave function to acknowledge the address It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function when slave software decides to NACK a matched address or when there is a Stop detected on the bus SL VSEL is not cleared if software NACKs data 0 Not selected The Slave function is not currently selected Selected The Slave function is currently selected Slave Deselected flag This flag will cause an interrupt when set if 0 enabled via INTENSET This flag can be cleared by writing a 1 to this bit 0 Not deselected The Slave function has not become deselected This does not mean that it is currently selected That information can be found in the SLVSEL flag 1 Deselected The Slave function has become deselected This is specifically caused by the SLVSEL flag changing from 1 to 0 See the description of SLVSEL for details on when that event occurs Monitor Ready This flag is cleared when the MONRXDAT register is 0 read 0 No data The Monitor function does not curren
73. USART API ROM driver routines Rev 1 1 24 January 2013 Preliminary user manual 24 1 How to read this chapter The USART ROM driver routines are available on all LPC800 parts 24 2 Features Send and receive characters in asynchronous or synchronous mode Send and receive multiple characters line in asynchronous or synchronous UART mode 24 3 General description The UART API handles sending and receiving characters using any of the USART blocks in asynchronous mode Remark Because all USARTS share a common fractional divider the uart init routine returns the value for the common divider UART driver routines function table uart get mem size Ptr to ROM Driver table Ox1FFF 1FF8 uart isr ROM Driver Table 0x04 0x08 0x0C Ptr to Device Table 3 0x10 Ptr to Device Table 4 0x14 0x24 Ptr to UART driver routines Ptr to Device Table n Fig 48 USART driver routines pointer structure UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 293 of 326 NXP Semiconductors UM10601 Chapter 24 LPC800 USART API ROM driver routines 24 4 API description The UART API contains functions to send and receive characters via any of the USART blocks Table 273 UART API calls API call uint32 t ramsize in bytes
74. USART supports hardware flow control using RTS and or CTS signalling If RTS is configured to appear on a device pin so that it can be sent to an external device it indicates to an external device the ability of the receiver to receive more data If connected to a pin and if enabled to do so the CTS input can allow an external device to throttle the USART transmitter Figure 29 shows an overview of RTS and CTS within the USART UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 185 of 326 NXP Semiconductors U M1 0601 Chapter 15 LPC800 USARTO 1 2 STAT CTS STAT DELTACTS change detect CFG CTSEN CFG LOOP Transmitter Receiver Fig 29 Hardware flow control using RTS and CTS 15 7 3 2 Software flow control Software flow control could include XON XOFF flow control or other mechanisms these are supported by the ability to check the current state of the CTS input and or have an interrupt when CTS changes state via the CTS and DELTACTS bits respectively in the STAT register and by the ability of software to gracefully turn off the transmitter via the TXDIS bit in the CTRL register UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1
75. USARTO 0x4006 8024 USART1 0x4006 C024 USART2 bit description Bit Symbol Description Reset Value 0 RXRDY Receiver Ready flag 0 1 Reserved Read value is undefined only zero should be NA written 2 TXRDY Transmitter Ready flag 1 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 183 of 326 NXP Semiconductors U M1 0601 Chapter 15 LPC800 USARTO 1 2 Table 167 USART Interrupt Status register INTSTAT address 0x4006 4024 USARTO 0x4006 8024 USART1 0x4006 C024 USART2 bit description Bit Symbol Description Reset Value 4 3 Reserved Read value is undefined only zero should be NA written 5 DELTACTS This bit is set when a change in the state of the CTS input is 0 detected 6 TXDISINT Transmitter Disabled Interrupt flag 0 7 Reserved Read value is undefined only zero should be NA written 8 OVERRUNINT Overrun Error interrupt flag 0 10 9 Reserved Read value is undefined only zero should be NA written 11 DELTARXBRK This bit is set when a change in the state of receiver break 0 detection occurs 12 START This bit is set when a start is detected on the receiver input 0 13 FRAMERRINT Framing Error interrupt flag 0 14 PARITYERRINT Parity Error interrupt flag 0 15 RXNOISEINT Received Noise interrupt flag 0 31 16 Reserved Read value is undefined only zer
76. a multiple of 4 PARAM ERROR CODE READ PROTECTION ENABLED Description This command is used to read the CRC checksum of a block of RAM or flash memory This command is blocked when code read protection is enabled Example S 268436736 4 lt CR gt lt LF gt reads the CRC checksum for 4 bytes of data from address 0x1000 0500 If checksum value is OXCBF43926 then the host will receive 8421780262 lt CR gt lt LF gt 21 5 1 16 UART ISP Return Codes Table 235 UART ISP Return Codes Summary Return Mnemonic Description Code 0 CMD_SUCCESS Command is executed successfully Sent by ISP handler only when command given by the host has been completely and successfully executed 1 INVALID COMMAND Invalid command 2 SRC ADDR ERROR Source address is not on word boundary 3 DST ADDR ERROR Destination address is not on a correct boundary 4 SRC ADDR NOT MAPPED Source address is not mapped in the memory map Count value is taken in to consideration where applicable 5 DST ADDR NOT MAPPED Destination address is not mapped in the memory map Count value is taken in to consideration where applicable 6 COUNT ERROR Byte count is not multiple of 4 or is not a permitted value 7 INVALID SECTOR Sector number is invalid or end sector number is greater than start sector number SECTOR NOT BLANK Sector is not blank 9 SECTOR NOT PREPARED FOR Command to prepare sector for write operation WRITE OPERATION was not executed 10 COMPARE ERR
77. a read from the user accessible Flash both 32 bits of raw data containing the specified memory location and the matching ECC byte are evaluated If the ECC mechanism detects a single error in the fetched data a correction will be applied before data are provided to the CPU When a write request into the user accessible Flash is made writing the user specified content is accompanied by a matching ECC value calculated and stored in the ECC memory When a sector of Flash memory is erased the corresponding ECC bits are also erased Once a 6 bit ECC is written it can not be updated unless it is erased first Therefore for the implemented ECC mechanism to perform properly data must be written into the flash memory in groups of 4 bytes or multiples of 4 aligned as described above All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 248 of 326 NXP Semiconductors U M1 0601 Chapter 21 LPC800 Flash ISP and IAP programming 21 4 3 Code Read Protection CRP Code Read Protection is a mechanism that allows the user to enable different levels of security in the system so that access to the on chip flash and use of the ISP can be restricted When needed CRP is invoked by programming a specific pattern in flash location at 0x0000 02FC IAP commands are not affected by the code read protection Important any CRP change beco
78. allows a wide variety of timing counting output modulation and input capture operations UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 116 of 326 NXP Semiconductors U M1 0601 Chapter 10 LPC800 State Configurable Timer SCT The most basic user programmable option is whether a SCT operates as two 16 bit counters or a unified 32 bit counter In the two counter case in addition to the counter value the following operational elements are independent for each half e State variable Limit halt stop and start conditions Values of Match Capture registers plus reload or capture control values In the two counter case the following operational elements are global to the SCT Clock selection Inputs Events Outputs Interrupts Events outputs and interrupts can use match conditions from either counter Remark In this chapter the term bus error indicates an SCT response that makes the processor take an exception system clock clock SCT clock synced inputs processing prescaler s match capture registers inputs control logic generation event i outputs Fig 14 SCT block diagram UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary u
79. analog clock Fclkana With the digital part the analog output clock Fclkana can be divided to the required output clock frequency wdt_osc_clk The analog output frequency Fclkana can be adjusted with the FREQSEL bits between 600 kHz and 4 6 MHz With the digital part Fclkana will be divided divider ratios 2 4 64 to wdt osc using the DIVSEL bits The output clock frequency of the watchdog oscillator can be calculated as wdt osc clk Fclkana 2 x 1 DIVSEL 9 3 kHz to 2 3 MHz nominal values Remark Any setting of the FREQSEL bits will yield a Fclkana value within 40 of the listed frequency value The watchdog oscillator is the clock source with the lowest power consumption If accurate timing is required use the IRC or system oscillator Remark The frequency of the watchdog oscillator is undefined after reset The watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL register before using the watchdog oscillator Table 11 Watchdog oscillator control register WDTOSCCTRL address 0x4004 8024 bit description Bit Symbol Value Description Reset value 4 0 DIVSEL Select divider for Fclkana 0 wdt osc Fclkana 2 x 1 DIVSEL 00000 2 x 1 DIVSEL 2 00001 2 x 1 DIVSEL 4 Tm 2 x 1 DIVSEL 64 8 5 FREQSEL Select watchdog oscillator analog output frequency 0x00 Fclkana 0x1 0 6 MHz 0x2 1 05 MHz 0x3 1 4 MHz 0 4 1 75 MHz 0 5 2 1 MHz 0x6 2 4 MHz 0 7 2
80. and IAP programming Blank check sector s sector number end sector number gt Table 228 UART ISP Blank check sector command Command Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD SUCCESS SECTOR NOT BLANK followed by Offset of the first non blank word location Contents of non blank word location INVALID SECTOR PARAM ERROR Description This command is used to blank check one or more sectors of on chip flash memory Blank check on sector 0 always fails as first 64 bytes are re mapped to flash boot block When CRP is enabled the blank check command returns 0 for the offset and value of sectors which are not blank Blank sectors are correctly reported irrespective of the CRP setting Example 2 3 lt CR gt lt LF gt blank checks the flash sectors 2 and 3 Read Part Identification number Table 229 UART ISP Read Part Identification command Command J Input None Return Code CMD SUCCESS followed by part identification number in ASCII see Table 230 Description This command is used to read the part identification number Table 230 Part identification numbers Device Hex coding LPC810M021FN8 0x0000 8100 LPC811M001FDH16 0x0000 8110 LPC812M101FDH16 0x0000 8120 LPC812M101FD20 0x0000 8121 LPC812M101FDH20 0x0000 8122 Read Boot code version number Table 231 UART ISP Read Boot Code version number command Comman
81. and no locking time out set_p returns PLL_CMD_SUCCESS in result 0 and 36000 in result 1 The new system clock is 36 MHz All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 275 of 326 NXP Semiconductors U M1 0601 22 5 1 6 22 5 2 22 9 2 1 22 5 2 2 UM10601 Chapter 22 LPC800 Power profile ROM driver System clock approximately equal to the expected value command 0 12000 command 1 16500 command 2 CPU FREQ APPROX command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock a system clock of approximately 16 5 MHz and no locking time out set pll returns CMD SUCCESS in result 0 and 16000 in result 1 The new system clock is 16 MHz Power control See Section 22 5 1 1 and Section 22 5 2 2 for examples of the power control API Invalid frequency device maximum clock rate exceeded command 0 30 command 1 PWR CPU PERFORMANCE command 2 40 rom gt pWRD gt set_power command result The above setup would be used in a system running at the main and system clock of 30 MHz with a need for maximum CPU processing power Since the specified 40 MHz clock is above the 30 MHz maximum set power returns PWR INVALID FREQ in result 0 without changing anything in the existing power setup An applicabl
82. and the checksum computation is complete All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 234 of 326 NXP Semiconductors UM10601 Chapter 18 LPC800 Cyclic Redundancy Check CRC engine Table 204 CRC checksum register SUM address 0x5000 0008 bit description Bit Symbol Description Reset value 31 0 SUM The most recent CRC sum can be read through this 0x0000 FFFF register with selected bit order and 1 s complement post processes 18 6 4 CRC data register This register is a Write only register containing the data block for which the CRC sum will be calculated Table 205 CRC data register WR DATA address 0x5000 0008 bit description Bit Symbol 31 0 WR DATA Description Reset value Data written to this register will be taken to perform calculation with selected bit order and 1 s complement pre process Any write size 8 16 or 32 bit are allowed and accept back to back transactions 18 7 Functional description The following sections describe the register settings for each supported CRC standard 18 7 1 CRC CCITT set up Polynomial x16 x12 x5 1 Seed Value OxFFFF Bit order reverse for data input NO 1 s complement for data input NO Bit order reverse for CRC sum NO 1 s complement for CRC sum NO CRC MODE 0x0000 0000 CRC
83. available ready 16 3 1 2 Wake up from Deep sleep and Power down modes Enable the 12C interrupt in the NVIC Enable the 12C interrupt in the STARTERP 1 register in the SYSCON block to create the interrupt signal asynchronously while the core and the peripheral are not clocked See Table 34 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description In the PDAWAKE register configure all peripherals that need to be running when the part wakes up Configure the 12C in slave mode Enable the 12 the interrupt in the 12C INTENCLR register which configures the interrupt as wake up event Examples are the following events Slave deselect Slave pending wait for read write or ACK Address match Data available ready for the monitor 16 4 Pin description The 12 pins are movable pin functions and are assigned to pins on the LPC800 packages through the switch matrix You have two choices to connect the 12C pins UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 188 of 326 NXP Semiconductors U M1 0601 Chapter 16 LPC800 I2C bus interface 1 Connect to special 12C open drain pins PIOO 10 and PIOO 11 2 Connect to any other pin that can host a movable function When the I C function is connected to specialized 12C pins it compl
84. be re written with a O 0 A watchdog time out will not cause a chip reset 1 A watchdog time out will cause a chip reset 2 WDTOF Watchdog time out flag Set when the watchdog timer 0 only times out by a feed error or by events associated with after WDPROTECT Cleared by software Causes a chip external reset if WDRESET 1 reset UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 154 of 326 NXP Semiconductors U M1 0601 Chapter 12 LPC800 Windowed Watchdog Timer WWDT Table 142 Watchdog mode register MOD 0x4000 4000 bit description Bit Symbol Value Description Reset value 3 WDINT Warning interrupt flag Set when the timer reaches the 0 value in WDWARNINT Cleared by software 4 WDPROTECT Watchdog update mode This bit can be set once by 0 software and is only cleared by a reset 0 The watchdog time out value TC can be changed at any time 1 The watchdog time out value TC can be changed only after the counter is below the value of WDWARNINT and WDWINDOW 5 LOCK A 1 in this bit prevents disabling or powering down the 0 watchdog oscillator This bit can be set once by software and is only cleared by any reset 31 6 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined Once the WDEN WDPROTECT or WDRESET bits are set
85. bit in the Control register and decrements the counter on the same clock if the counter is enabled in that clock Match vs I O events Counter operation is complicated by the prescaler and by clock mode 01 in which the SCT clock is the bus clock However the prescaler and counter are enabled to count only when a selected edge is detected on a clock input The prescaler is enabled when the clock mode is not 01 or when the input edge selected by the CLKSEL field is detected The counter is enabled when the prescaler is enabled and PRELIM 0 or the prescaler is equal to the value in PRELIM An I O component of an event can occur any SCT clock when its counter HALT bit is 0 In general a Match component of an event can only occur in a UT clock when its counter HALT and STOP bits are both 0 and the counter is enabled Table 133 shows when the various kinds of events can occur Table 133 Event conditions COMBMODE IOMODE Event can occur on clock IO Any Event can occur whenever HALT 0 type A MATCH Any Event can occur when HALT 0 and STOP 0 and the counter is enabled type C OR Any From the IO component Event can occur whenever HALT 0 A From the match component Event can occur when HALT 0 and STOP 0 and the counter is enabled C AND LOW or HIGH Event can occur when HALT 0 and STOP 0 and the counter is enabled C AND RISE or FALL Event can occur whenever HALT 0 A All informatio
86. chapter The MRT is available on all LPC800 parts 11 2 Features 31 bit interrupt timer Four channels independently counting down from individually set values Repeat and one shot interrupt modes 11 3 Basic configuration Configure the MRT using the following registers n the SYSAHBCLKCTRL register set bit 10 Table 18 to enable the clock to the register interface Clear the MRT reset using the PRESETCTRL register Table 7 The global MRT interrupt is connected to interrupt 10 in the NVIC 11 4 Pin description The MRT has no configurable pins 11 5 General description The Multi Rate Timer MRT provides a repetitive interrupt timer with four channels Each channel can be programmed with an independent time interval Each channel operates independently from the other channels in one of the following modes Repeat interrupt mode See Section 11 5 1 One shot interrupt mode See Section 11 5 2 The modes for each timer are set in the timer s control register See Table 137 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 143 of 326 NXP Semiconductors UM1 0601 Chapter 11 LPC800 Multi Rate Timer MRT Fig 21 MRT block diagram 1 DEC D Q IRQ GEN IRQO TIMER INTVAL Wi 5 c o WR ed sl Sw HE NER k IRQ 1 3 CHANNE
87. cleared by writing a 1 to them Interrupt Enable read and Set register Contains an individual interrupt enable bit for each potential USART interrupt A complete value may be read from this register Writing a 1 to any implemented bit position causes that bit to be set Interrupt Enable Clear register Allows clearing any combination of bits in the INTENSET register Writing a 1 to any implemented bit position causes the corresponding bit to be cleared Receiver Data register Contains the last character received Receiver Data with Status register Combines the last character received with the current USART receive status Allows software to recover incoming data and status together Transmit Data register Data to be transmitted is written here Baud Rate Generator register 16 bit integer baud rate divisor value Interrupt status register Reflects interrupts that are currently enabled Reset value 0 0x000E o 0x0005 Reference Table 158 Table 159 Table 160 Table 161 Table 162 Table 163 Table 164 Table 165 Table 166 Table 167 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 174 of 326 NXP Semiconductors UM10601 Chapter 15 LPC800 USARTO 1 2 15 6 1 USART Configuration register The CFG register contains communication and mode settings for
88. clock SCL This time out is asserted when the time All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 207 of 326 NXP Semiconductors U M1 0601 16 7 3 16 7 4 UM10601 Chapter 16 LPC800 I2C bus interface between any of these events is longer than the time configured in the TIMEOUT register This time out could be useful in monitoring an 12 bus within a system as part of a method to keep the bus running of problems occur The second type of 2 time out is reflected by the SCLTIMEOUT flag in the STAT register This time out is asserted when the SCL signal remains low longer than the time configured in the TIMEOUT register This corresponds to SMBus time out parameter TriMEour In this situation a slave could reset its own I C interface in case it is the offending device If all listening slaves including masters that can be addressed as slaves do this then the bus will be released unless it is a current master causing the problem Refer to the SMBus specification for more details Both types of time out are generated when the I C bus is considered busy Ten bit addressing Ten bit addressing is accomplished by the IC master sending a second address byte to extend a particular range of standard 7 bit addresses In the case of the master writing to the slave the 12C frame simply continues with data after
89. clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 lt Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 70 of 326 NXP Semiconductors UM10601 6 5 16 PIOO 6 register Chapter 6 LPC800 I O configuration IOCON Table 64 6 register PIOO 6 address 0x4004 4040 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are re
90. event This SCT conflict resolution register resolves this conflict To enable an event to toggle an output set the OnRES value to 0x3 in this register and set the event bits in both the Set and Clear registers Table 120 SCT conflict resolution register RES address 0x5000 4058 bit description Bit Symbol Value Description Reset value 1 0 OORES Effect of simultaneous set and clear on output 0 0 0x0 No change 0 1 Set output or clear based on the SETCLRO field 0 2 Clear output or set based on the SETCLRO field 0x3 Toggle output 3 2 O1RES Effect of simultaneous set and clear on output 1 0 0x0 No change 0x1 Set output or clear based on the SETCLR1 field 0 2 Clear output or set based on the SETCLR1 field 0x3 Toggle output All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 129 of 326 NXP Semiconductors U M1 0601 10 6 14 10 6 15 10 6 16 UM10601 Chapter 10 LPC800 State Configurable Timer SCT Table 120 SCT conflict resolution register RES address 0x5000 4058 bit description Bit Symbol Value Description Reset value 5 4 O2RES Effect of simultaneous set and clear on output 2 0 0x0 No change 0x1 Set output or clear based on the SETCLR2 field 0 2 Clear output n or set based on the SETCLR2 field 0x3 Toggle output 7 6 OSRES Effect of simul
91. function calls the callback functions must be define Upon the completion of a read write as specified by the PARAM structure the callback functions will be invoked 12 Slave Mode Transmit Receive In slave mode polled routines are intended for testing purposes It is up to the user to decide whether to use the polled or interrupt driven mode While operating the Slave driver in polled mode can be useful for program development and debugging most applications will need the interrupt driven versions of Slave Receive and Transmit in the final software The following routines are polled routines err code i20 slave receive poll I2C HANDLE T I2C PARAM I2C RESULT err code i2c slave transmit poll I2C HANDLE T I2C PARAM I2C RESULT The following routines are interrupt driven routines err code i2c slave receive intr I2C HANDLE T I2C PARAM I2C RESULT err code i2c slave transmit intr I2C HANDLE T I2C PARAM I2C RESULT Where err code is the return state of the function An 0 indicates success All non zero indicates an error Refer to the Error Code Table e 2C PARM is a structure with parameters passed to the function Section 23 4 22 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 290 of 326 NXP Semiconductors U M1 0601 23 5 6 Chapter 23 LPC800 I2C bus ROM
92. interrupt in the NVIC Any USART interrupt wakes up the part from sleep mode Enable the USART interrupt in the INTENSET register Table 161 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 170 of 326 NXP Semiconductors U M1 0601 Chapter 15 LPC800 USARTO 1 2 15 3 2 2 Wake up from Deep sleep or Power down mode Configure the USART in synchronous slave mode See Table 158 You must connect the SCLK function to a pin and connect the pin to the master e Enable the USART interrupt in the STARTERP 1 register See Table 34 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description Enable the USART interrupt in the NVIC n the PDAWAKE register configure all peripherals that need to be running when the part wakes up The USART wakes up the part from Deep sleep or Power down mode on all events that cause an interrupt and areal so enabled in the INTENSET register Typical wake up events are A start bit has been received The RXDATA buffer has received a byte Data is ready to be transmitted in the TXDATA buffer and a serial clock from the master has been received Achange in the state of the CTS pin if the CTS function is connected lt tbd gt Remark By enabling or disabling the interrupt in the INTENSET registe
93. mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 lt Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 73 of 326 UM10601 Chapter 7 LPC800 GPIO port Rev 1 1 24 January 2013 Preliminary user manual 7 1 How to read this chapter All GPIO registers refer to 32 pins per port Depending on the package type not all pins are available and the corresponding bits in the GPIO registers are reserved see Table 67 Table 67 GPIO pins available Package GPIO Port 0 TSSOP16 PIOO 0 to PIOO 13 TSSOP20 PIOO 0 to PIOO 17 SOP20 PIOO 0 to PIOO 17 DIP8 PIOO 0 to PIOO 5 7 2 Features e GPIO port registers are located on the ARM Cortex MO I O port for fast access The ARM Cortex MO I O port supports single cycle access GPIO ports
94. of every event IOSEL 0 selects pins CTIN 0 or CTOUT_O IOSEL selects pins CTIN 3 or CTOUT_3 Selects the I O condition for event n The detection of edges on outputs lag the 0 conditions that switch the outputs by one SCT clock In order to guarantee proper edge state detection an input must have a minimum pulse width of at least one SCT clock period LOW Rise Fall HIGH Selects how the specified match and I O condition are used and combined OR The event occurs when either the specified match or I O condition occurs MATCH Uses the specified match only IO Uses the specified I O condition only AND The event occurs when the specified match and I O condition occur simultaneously This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest numbered event occurring for that state Add STATEV value is added into STATE the carry out is ignored Load STATEV value is loaded into STATE This value is loaded into or added to the state selected by HEVENT depending on STATELD when this event is the highest numbered event occurring for that state If STATELD and STATEV are both zero there is no change to the STATE value All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 134 of 326 NXP Semiconductors U M1 0601 Chapter 10 LPC800 State
95. of the TCK signal This pin is used for JTAG boundary scan when the RESET pin is LOW JTAG Test Reset The TRST pin can be used to reset the test logic within the debug logic This pin includes an internal pull up and is used for JTAG boundary scan when the RESET pin is LOW 25 5 Functional description 25 5 1 Debug limitations It is recommended not to use the debug mode during Deep sleep or Power down mode mode During a debugging session the System Tick Timer is automatically stopped whenever the CPU is stopped Other peripherals are not affected 25 5 2 Debug connections for SWD For debugging purposes it is useful to provide access to the ISP entry pin PIOO 1 This pin can be used to recover the part from configurations which would disable the SWD port such as improper PLL configuration reconfiguration of SWD pins entry into Deep power down mode out of reset etc This pin can be used for other functions such as GPIO but it should not be held LOW on power up or reset UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 300 of 326 NXP Semiconductors U M1 0601 25 5 3 UM10601 Chapter 25 LPC800 Debugging VDD VTREF LPC800 Signals from SWD connector ISP entry The VTREF pin on the SWD connector enables the debug connector to match the target voltage
96. of the counter events can change the state multiple times and thus create a large variety of event controlled transitions on the SCT outputs and or interrupts Once configured the SCT can run continuously without software intervention and can generate multiple output patterns entirely under the control of events To configure the SCT see Section 10 7 9 To start run and stop the SCT see Section 10 7 10 To configure the SCT as simple event controlled counter timer see Section 10 7 11 Configure the SCT To set up the SCT for multiple events and states perform the following configuration steps Configure the counter 1 Configure the L and H counters in the CONFIG register by selecting two independent 16 bit counters L counter and H counter or one combined 32 bit counter in the UNIFY field 2 Select the SCT clock source in the CONFIG register fields CLKMODE and CLKSEL from any of the inputs or an internal clock Configure the match and capture registers 1 Select how many match and capture registers the application uses total of up to 5 n the REGMODE register select for each of the 5 match capture register pairs whether the register is used as a match register or capture register 2 Define match conditions for each match register selected Each match register MATCH sets one match value if a 32 bit counter is used or two match values if the L and H 16 bit counters are used Each match relo
97. output for the match event in the CTRL register See Table 130 The EVn CTRL registers also control what type of output signal is created 4 If you want to capture a timer value on a capture signal a Configure the register map for capture registers See Table 117 b Create one or more capture events See Table 130 c Connect the CTIN functions to pins see Section 10 4 and configure the signal to create an event See Table 130 5 Start the timer by writing to the CRTL register See Table 109 6 Read the capture registers to read the timer value at the time of the capture events 10 4 Pin description The SCT inputs and outputs are movable functions and are assigned to external pins through the switch matrix See Section 9 3 1 Connect an internal signal to a package pin to assign the SCT functions to pins on the LPC800 package Table 106 SCT pin description Function CTIN 0 CTIN 1 CTIN 2 CTIN 3 CTOUT 0 CTOUT 1 CTOUT 2 CTOUT 3 Direction Pin any any any any any any any 7 7 any Description SCT input 0 SCT input 1 SCT input 2 SCT input 3 SCT output 0 SCT output 1 SCT output 2 SCT output 3 SWM register PINASSIGN5 PINASSIGN6 PINASSIGN6 PINASSIGN6 PINASSIGN6 PINASSIGN7 PINASSIGN7 PINASSIGN7 Reference Table 101 Table 102 Table 102 Table 102 Table 102 Table 103 Table 103 Table 103 10 5 General description The State Configurable Timer SCT
98. parity 0 1 Reserved Ox2 Even parity Adds a bit to each character such that the number of 1s in a transmitted character is even and the number of 1s in a received character is expected to be even Ox3 Odd parity Adds a bit to each character such that the number of 1s in a transmitted character is odd and the number of 1s in a received character is expected to be odd 6 STOPLEN Number of stop bits appended to transmitted data Only a 0 single stop bit is required for received data 0 1 stop bit 1 2 stop bits This setting should only be used for asynchronous communication 7 Reserved Only write 0 to this bit 8 Reserved Read value is undefined only zero should be NA written UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 175 of 326 NXP Semiconductors U M1 0601 Chapter 15 LPC800 USARTO 1 2 Table 158 USART Configuration register CFG address 0x4006 4000 USARTO 0x4006 8000 USART1 0x4006 C000 USART2 bit description continued Bit Symbol Value Description Reset Value 9 CTSEN CTS Enable Determines whether CTS is used for flow 0 control CTS can be from the input pin or from the USART s own RTS if loopback mode is enabled See Section 15 7 3 for more information 0 No flow control The transmitter does not receive any automatic flow control signal 1 Flow control enabled
99. peripheral or enabling its interrupt use the switch matrix to connect the peripheral to external pins The boot loader assigns the SWD functions to pins PIOO_2 and PIOO_3 If the user code disables the SWD functions through the switch matrix to use the pins for other functions the SWD port is disabled Remark For the purpose of programming the pin functions through the switch matrix every pin except the power and ground pins is identified in a package independent way by its GPIO port pin number All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 103 of 326 NXP Semiconductors U M1 0601 Chapter 9 LPC800 Switch matrix 9 3 1 Connect an internal signal to a package pin PIOO 17 PIOO 14 PIOO 13 PIOO 0 ACMP lI1 TDO E m disable XTALIN PIOO 12 6 VDDCMP PINENABLEO bit 4 1 RESET PIOO 5 PIOO 7 LPC800 PIOO_4 WAKEUP TRST 020 Vss SWCLK PIOO_3 TCK SWDIO PIOO_2 TMS PIOO 11 PIOO 10 PIOO0 16 8 gt PIOO 8 pin number 8 PIOO 9 XTALOUT PIOO 1 ACMP 2 CLKIN TDI 15 Y assign FUNC 00 PINASSIGNO bits 7 0 0 8 16 gt pin number 16 assign FUNC 00 RXD PINASSIGNO bits 15 8 0x10 function UO TXD assigned to SO20 package pin 14 function UO RXD assigned to S
100. pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 lt Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 58 of 326 NXP Semiconductors UM10601 6 5 4 PIOO 5 register Chapter 6 LPC800 I O configuration IOCON Table 52 5 register PIOO 5 address 0x4004 400C bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode
101. programming flash wait states and for generating the the flash signature 19 4 Register description Table 206 Register overview FMC base address 0x4004 0000 Name Access Address Description Reset Reference offset value FLASHCFG R W 0x010 Flash configuration register lt tbd gt Table 207 FMSSTART R W 0x020 Signature start address register 0 Table 208 FMSSTOP R W 0x024 Signature stop address register 0 Table 209 FMSWO R 0x02C Signature word Table 210 19 4 1 Flash configuration register Depending on the system clock frequency access to the flash memory can be configured with various access times by writing to the FLASHCFG register Remark Improper setting of this register may result in incorrect operation of the flash memory UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 237 of 326 NXP Semiconductors U M1 0601 19 4 2 19 4 3 19 4 4 UM10601 Chapter 19 LPC800 Flash controller Table 207 Flash configuration register FLASHCFG address 0x4004 0010 bit description Bit Symbol Value Description Reset value 1 0 FLASHTIM Flash memory access time FLASHTIM 1 is equal to the 0 1 number of system clocks used for flash access 0x0 1 system clock flash access time for system clock frequencies of up to 20 MHz 0 1 2 system clocks flash access time for system clock freq
102. provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 169 of 326 NXP Semiconductors UM10601 Chapter 15 LPC800 USARTO 1 2 SYSCON block system clock U_PCLK UARTFRGADD UARTFRGDIV RTC oscillator USARTO 32 kHz T BAUD SERIAL CLOCK GENERATOR USART1 T BAUD SERIAL CLOCK U PCLK GENERATOR UARTCLKDIV 1 MULT DIV T USART2 BAUD SERIAL CLOCK GENERATOR Fig 27 USART clocking UO SCLK U1 SCLK U2 SCLK For details on the clock configuration see Section 15 7 1 Clocking and Baud rates 15 3 2 Configure the USART for wake up The USART can wake up the system from sleep mode in asynchronous or synchronous mode on any enabled USART interrupt If the USART is configured for synchronous slave mode the USART block can create an interrupt on a received signal even when the USART block receives no clocks from the ARM Cortex M0 core that is in Deep sleep or Power down mode As long as the USART receives a clock signal from the master it can receive up to one byte in the RXDATA register while in Deep sleep or Power down mode Any interrupt raised as part of the receive data process can then wake up the part 15 3 2 1 Wake up from Sleep mode Configure the USART in either asynchronous mode or synchronous mode See Table 158 Enable the USART
103. read and set register The INTENSET register is used to enable various USART interrupt sources Enable bits in INTENSET are mapped in locations that correspond to the flags in the STAT register The complete set of interrupt enables may be read from this register Writing ones to implemented bits in this register causes those bits to be set The INTENCLR register is used to clear bits in this register Table 161 USART Interrupt Enable read and set register INTENSET address 0x4006 400C USARTO 0x4006 800C USART1 0 4006 CO0C USART2 bit description Bit Symbol Description Reset Value 0 RXRDYEN When 1 enables an interrupt when there is a received 0 character available to be read from the RXDATA register 1 Reserved Read value is undefined only zero should be NA written 2 TXRDYEN When 1 enables an interrupt when the TXDATA register is 0 available to take another character to transmit 4 amp Reserved Read value is undefined only zero should be NA written 5 DELTACTSEN When 1 enables an interrupt when there is a change in the 0 state of the CTS input 6 TXDISINTEN When 1 enables an interrupt when the transmitter is fully 0 disabled as indicated by the TXDISINT flag in STAT See description of the TXDISINT bit for details 7 Reserved Read value is undefined only zero should be NA written 8 OVERRUNEN When 1 enables an interrupt when an overrun error 0 occurred 10 9 Reserved Read value is undefined
104. register Transmitter Ready flag When 1 this bit indicates that data may be written to the transmit buffer Previous data may still be in the process of being transmitted Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register Receiver Overrun interrupt flag This flag applies only to slave mode Master 0 This flag is set when the beginning of a received character is detected while the receiver buffer is still in use If this occurs the receiver buffer contents are preserved and the incoming data is lost Data received by the SPI should be considered undefined if RxOv is set Transmitter Underrun interrupt flag This flag applies only to slave mode Master 0 In this case the transmitter must begin sending new data on the next input clock if the transmitter is idle If that data is not available in the transmitter holding register at that point there is no data to transmit and the TXUR flag is set Data transmitted by the SPI should be considered undefined if TXUR is set Slave Select Assert This flag is set whenever any slave select transitions from deasserted to asserted in both master and slave modes This allows determining when the SPI transmit receive functions become busy and allows waking up the device from reduced power modes when a slave mode access begins This flag is cleared by software Slave Select Deassert This flag is set whenever any asserted slave selects tr
105. register SUM address 0x5000 0008 bit description 235 Table 205 CRC data register WR DATA address 0x5000 0008 bit description 235 Table 206 Register overview FMC base address 0x4004 0000 2 rece oues erronee eR 237 Table 207 Flash configuration register FLASHCFG address 0x4004 0010 bit description 238 Table 208 Flash Module Signature Start register FMSSTART 0x4004 0020 bit description 238 Table 209 Flash Module Signature Stop register FMSSTOP 0x4004 0024 bit description 238 Table 210 FMSWO register bit description FMSWO address 0 4004 0026 239 Table 211 Boot loader versions 241 Table 212 244 Table 213 LPC800 flash configurations 247 Table 214 LPC800 flash configuration 248 Table 215 Code Read Protection options 249 Table 216 Code Read Protection hardware software INCEFACTION s ek tinet ic ts 249 Table 217 ISP commands allowed for different CRP levels co Sud 250 Table 218 UART ISP command summary 251 Table 219 UART ISP Unlock command 251 Table 220 UART ISP Set Baud Rate command 252 Table 221 UART ISP Echo command 252 Table 222 UART ISP Write to RAM command 252 Table 223 UART ISP Read Memory command 253 Table 224 UART ISP Prepare sector
106. register TC 0x4000 4004 bit description 156 Table 145 Watchdog Feed register FEED 0x4000 4008 bit description 157 Table 146 Watchdog Timer Value register TV 0 4000 400C bit description 157 Table 147 Watchdog Timer Warning Interrupt register WARNINT 0x4000 4014 bit description 157 Table 148 Watchdog Timer Window register WINDOW 0x4000 4018 bit description 158 Table 149 Analog comparator pin description 160 Table 150 Register overview Analog comparator base address 0x4002 4000 162 Table 151 Comparator control register CTRL address 0x4002 4000 bit description 162 Table 152 Voltage ladder register LAD address 0x4002 4004 bit 164 Table 153 Register overview WKT base address 0x4000 ope TP a 166 Table 154 Control register CTRL address 0x4000 8000 bit description ise ae tb REQUE 166 Table 155 Counter register COUNT address 0x4000 800C NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 315 of 326 NXP Semiconductors UM10601 bit description 167 Table 156 USART pin description 171 Table 157 Register overview USART base address 0x4006 4000 USARTO 0x4006 8000 USART1 0x4006 C000 5 2 174 Table 1
107. register TC 0x4000 4004 bit description Bit Symbol Description Reset Value 23 0 COUNT Watchdog time out value 0x00 OOFF 31 24 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined Watchdog Feed register Writing OxAA followed by 0x55 to this register will reload the Watchdog timer with the WDTC value This operation will also start the Watchdog if it is enabled via the WDMOD register Setting the WDEN bit in the WDMOD register is not sufficient to enable the Watchdog A valid feed sequence must be completed after setting WDEN before the Watchdog is capable of generating a reset Until then the Watchdog will ignore feed errors After writing OxAA to WDFEED access to any Watchdog register other than writing 0x55 to WDFEED causes an immediate reset interrupt when the Watchdog is enabled and sets the WDTOF flag The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence It is good practice to disable interrupts around a feed sequence if the application is such that an interrupt might result in rescheduling processor control away from the current task in the middle of the feed and then lead to some other access to the WDT before control is returned to the interrupted task All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Pr
108. register low counter 16 bit Table 112 STOP_H R W 0x012 SCT stop condition register high counter 16 bit Table 112 START R W 0x014 SCT start condition register 0x0000 0000 Table 113 START_L R W 0x014 SCT start condition register low counter 16 bit Table 113 START_H R W 0x016 SCT start condition register high counter 16 bit Table 113 0x018 Reserved 0x03C COUNT R W 0x040 SCT counter register 0x0000 0000 Table 114 COUNT_L R W 0x040 SCT counter register low counter 16 bit Table 114 COUNT_H R W 0x042 SCT counter register high counter 16 bit Table 114 STATE R W 0x044 SCT state register 0x0000 0000 Table 115 STATE_L R W 0x044 SCT state register low counter 16 bit Table 115 STATE_H R W 0x046 SCT state register high counter 16 bit Table 115 INPUT RO 0x048 SCT input register 0x0000 0000 Table 116 REGMODE R W 0x04C SCT match capture registers mode register 0x0000 0000 Table 117 REGMODE_L R W 0x04C SCT match capture registers mode register low Table 117 counter 16 bit REGMODE_H R W Ox04E SCT match capture registers mode register high Table 117 counter 16 bit OUTPUT R W 0x050 SCT output register 0x0000 0000 Table 118 OUTPUTDIRCTRL R W 0x054 SCT output counter direction control register 0x0000 0000 Table 119 RES R W 0x058 SCT conflict resolution register 0x0000 0000 Table 120 0x050 0x060 0x064 Reserved OxOEC EVEN R W OxOFO SCT event enable register 0x0000 0000 Table 121 EVFLAG R W Ox0F4 SCT event fla
109. reserved Preliminary user manual Rev 1 1 24 January 2013 281 of 326 NXP Semiconductors UM10601 Chapter 23 LPC800 I2C bus ROM API 23 4 7 12C Master Transmit Receive Interrupt 23 4 8 23 4 9 UM10601 Table 259 12C Master Transmit Receive Interrupt Routine Prototype Input parameter Return Description I2C Master Transmit Receive Interrupt ErrorCode ti2c master tx rx intr 2C HANDLE T 12C I2C RESULT I2C HANDLE T Handle to the allocated SRAM area I2C PARAM Pointer to the I2C PARAM struct I2C RESULT Pointer to the I2C RESULT struct ErrorCode First transmits bytes in the send buffer to a slave and secondly receives bytes from slave and store it in the receive buffer The slave address with the R W bit 20 is expected in the first byte of the send buffer After the task is finished the slave address with the R W bit 1 is in the first byte of the receive buffer STOP condition is sent at end unless stop flag 20 Program control will be returned immediately and task will be completed on an interrupt driven basis When task is completed the callback function is called I2C Slave Receive Polling Table 260 12C Slave Receive Polling Routine Prototype Input parameter Return Description I2C Slave Receive Polling ErrorCode_t i2c_slave_receive_poll I2C_HANDLE_T 126 I2C RESULT I2C HANDLE T Handle to the allocated SRAM a
110. reserved oj m o o 0x0000 4000 16 kB on chip flash LPC812 F WB 4 kB on chip flash LPC810 ox0000 0000 Fig 2 LPC800 Memory mapping analog comparator PMU self wake up timer 0x0000 00CO 8 kB on chip flash LPC811 active interrupt vectors 0 0000 0000 0x4008 0000 0x4007 0000 0x4006 C000 0x4006 8000 0x4006 4000 0x4006 0000 0x4005 C000 0x4005 8000 0x4005 4000 0x4005 0000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 0x4003 4000 0x4003 0000 0x4002 C000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000 aaa 005748 The private peripheral bus includes the ARM Cortex M0 peripherals such as the NVIC SysTick and the core control registers 2 2 2 Micro Trace Buffer MTB The LPC800 supports the ARM Cortex M0 Micro Trace Buffer UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 9 of 326 UM10601 Chapter 3 LPC800 Nested Vectored Interrupt Controller NVIC Rev 1 1 24 January 2013 Preliminary user manual 3 1 How to read this chapter The NVIC is identical on all LPC800 parts The SPI1 and USART2 interrupts are implemented on parts LPC812M101FDH20 and LPC812M101FDH16 only
111. reserved Preliminary user manual Rev 1 1 24 January 2013 125 of 326 NXP Semiconductors U M1 0601 10 6 8 UM10601 Chapter 10 LPC800 State Configurable Timer SCT Table 114 SCT counter register COUNT address 0x5000 4040 bit description Bit Symbol Description Reset value 15 0 CTR_L When UNIFY 0 read or write the 16 bit L counter value When 0 UNIFY 1 read or write the lower 16 bits of the 32 bit unified counter 31 16 When UNIFY 0 read or write the 16 bit counter value When 0 UNIFY 1 read or write the upper 16 bits of the 32 bit unified counter SCT state register If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers STATE L and STATE H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation Software can read the state associated with a counter at any time Writing the state is only allowed when the counter HALT bit is 1 when HALT is 0 a write attempt does not change the state and results in a bus error The state variable is the main feature that distinguishes the SCT from other counter timer PWM blocks Events can be made to occur only in certain states Events in turn can perform the following actions set and clear outputs limit stop and start the counter cause interrupts modify the state variable The v
112. return code INVALID COMMAND when an undefined command is received Commands and return codes are in ASCII format CMD SUCCESS is sent by ISP command handler only when received ISP command has been completely executed and the new ISP command can be given by the host Exceptions from this rule are Set Baud Rate Write to RAM Read Memory and Go commands Table 218 UART ISP command summary ISP Command Usage Described in Unlock U Unlock Code Table 219 Set Baud Rate B Baud Rate stop bit Table 220 Echo A setting Table 221 Write to RAM W start address gt number of bytes gt Table 222 Read Memory R address number of bytes Table 223 Prepare sector s for P start sector number end sector number Table 224 write operation Copy RAM to flash C Flash address RAM address number of bytes Table 225 Go G address lt Mode gt Table 226 Erase sector s E start sector number end sector number Table 227 Blank check sector s start sector number end sector number Table 228 Read Part ID J Table 229 Read Boot code version Table 231 Compare M address lt address2 gt number of bytes gt Table 232 ReadUID N Table 233 Read CRC checksum S address number of bytes Table 234 21 5 1 4 Unlock Unlock code Table 219 UART ISP Unlock command Command U Input Unlock code 2313010 Return Code CMD SUCCESS INVALID CODE PARAM ERROR Description This command is
113. rights reserved Preliminary user manual Rev 1 1 24 January 2013 141 of 326 NXP Semiconductors U M1 0601 10 7 11 UM10601 Chapter 10 LPC800 State Configurable Timer SCT The current state can be read at any time by reading the STATE register To change the current state by software that is independently of any event occurring set the HALT bit and write to the STATE register to change the state value Writing to the STATE register is only allowed when the counter is halted the HALT_L and or HALT_H bits are set and no events can occur Configure the SCT without using states The SCT can be used as standard counter timer with external capture inputs and match outputs without using the state logic To operate the SCT without states configure the SCT as follows Write zero to the STATE register zero is the default Write zero to the STATELD and STATEV fields in the EVCTRL registers for each event Write Ox1 to the EVn STATE register of each event Writing 0 1 enables the event In effect the event is allowed to occur in a single state which never changes while the counter is running All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 142 of 326 UM10601 Chapter 11 LPC800 Multi Rate Timer MRT Rev 1 1 24 January 2013 Preliminary user manual 11 1 How to read this
114. s for write operation command leere 253 Table 225 UART ISP Copy RAM to flash command 254 Table 226 UART ISP Go command 255 Table 227 UART ISP Erase sector command 255 Table 228 UART ISP Blank check sector command 256 Table 229 UART ISP Read Part Identification command 256 Table 230 Part identification numbers Table 231 UART ISP Read Boot Code version number command sa eR ee Ree 256 Table 232 UART ISP Compare command 257 Table 233 UART ISP ReadUID command 257 Table 234 UART ISP Read CRC checksum command 258 Table 235 UART ISP Return Codes Summary 258 Table 236 IAP Command Summary 260 Table 237 IAP Prepare sector s for write operation COMMANG EROR RU ES 261 Table 238 IAP Copy RAM to flash command 262 Table 239 IAP Erase Sector s command 262 Table 240 IAP Blank check sector s command 263 Table 241 IAP Read Part Identification command 263 Table 242 IAP Read Boot Code version number UM10601 Table 243 Table 244 Table 245 Table 246 Table 247 Table 248 Table 249 Table 250 Table 251 Table 252 Table 253 Table 254 Table 255 Table 256 Table 257 Table 258 Table 259 Table 260 Table 261 Table 262 Table 263 Table 264 Table 265 Table 266 Table 267 Table 268 Table 269 Table 270 Table 271 Table 272 Table
115. status flag can cause an interrupt if enabled to do so by the SCLTIMEOUTEN bit in the INTENSET register The SCLTIMEOUT can be used with the SMBus Also see Section 16 7 2 Time out All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 199 of 326 NXP Semiconductors U M1 0601 16 6 6 16 6 7 UM10601 Chapter 16 LPC800 I2C bus interface Table 176 time out register TIMEOUT address 0x4005 0010 bit description Bit Symbol Description Reset value 3 0 TOMIN Time out time value bottom four bits These are hard wired to OxF OxF This gives a minimum time out of 16 12 function clocks and also a time out resolution of 16 12C function clocks 15 4 TO Time out time value Specifies the time out interval value in increments OXFFF of 16 I C function clocks as defined by the CLKDIV register To change this value while 12 is in operation disable all time outs write a new value to TIMEOUT then re enable time outs 0x000 A time out will occur after 16 counts of the 12C function clock 0x001 A time out will occur after 32 counts of the 12C function clock OxFFF A time out will occur after 65 536 counts of the 12C function clock 31 16 Reserved Read value is undefined only zero should be written NA I2C Clock Divider register The CLKDIV register divides down the Peripheral
116. that on Vpop 13 5 2 Settling times After the voltage ladder is powered on it requires stabilization time until comparisons using it are accurate Much shorter settling times apply after the LADSEL value is changed and when either or both voltage sources are changed Software can deal with these factors by repeatedly reading the comparator output until a number of readings yield the same result 13 5 3 Interrupts The interrupt output comes from edge detection circuitry in this module Rising edges falling edges or both edges can set the COMPEDGE bit and thus request an interrupt COMPEDGE and the interrupt request are cleared when software writes a 1 to EDGECLR UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 161 of 326 NXP Semiconductors U M1 0601 13 5 4 Chapter 13 LPC800 Analog comparator Comparator outputs The comparator output conditioned by COMPSA bit can be routed to an external pin When COMPSA is 0 and the comparator interrupt is disabled the comparator can be used with the bus clock disabled Table 18 System clock control register SYSAHBCLKCTRL address 0x4004 8080 bit description to save power if the control registers don t need to be written The status of the comparator output can be observed through the comparator status register bit The comparator output can b
117. the following If LOAD 1 the timer stops immediately e If LOAD 0 the timer stops at the end of the time interval 31 LOAD Determines how the timer interval value IVALUE 1 is 0 loaded into the TIMERn register This bit is write only Reading this bit always returns O 0 No force load The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected 1 Force load The INTVALn interval value IVALUE 1 is immediately loaded into the TIMERn register while TIMERn is running UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 146 of 326 NXP Semiconductors U M1 0601 11 6 2 11 6 3 Chapter 11 LPC800 Multi Rate Timer MRT Timer register The timer register holds the current timer value This register is read only Table 136 Timer register TIMER 0 3 address 0x4000 4004 TIMERO to 0x4000 4034 TIMER3 bit description Bit Symbol Description Reset value 30 0 VALUE Holds the current timer value of the down counter The initial value OX00FF of the TIMERn register is loaded as IVALUE 1 from the INTVALn FFFF register either at the end of the time interval or immediately in the following cases INTVALn register is updated in the idle state INTVALn register is updated with LOAD 1 When the timer is in idle
118. the 2 address bytes For the master to read from a slave it needs to reverse the data direction after the second address byte This is done by sending a Repeated Start followed by a repeat of the same standard 7 bit address with a Read bit The slave must remember that it had been addressed by the previous write operation and stay selected for the subsequent read with the correct partial I2C address For the Master function the 12 is simply instructed to perform the 2 byte addressing as a normal write operation followed either by more write data or by a Repeated Start with a repeat of the first part of the 10 bit slave address and then reading in the normal fashion For the Slave function the first part of the address is automatically matched in the same fashion as 7 bit addressing The Slave address qualifier feature see Section 16 6 14 can be used to intercept all potential 10 bit addresses first address byte values FO through F6 or just one In the case of Slave Receiver mode data is received in the normal fashion after software matches the first data byte to the remaining portion of the 10 bit address The Slave function should record the fact that it has been addressed in case there is a follow up read operation For Slave Transmitter mode the slave function responds to the initial address in the same fashion as for Slave Receiver mode and checks that it has previously been addressed with a full 10 bit address If the address ma
119. the transmit buffer s first byte must be the slave address with the R W bit set to 0 To enable a master read the receive buffer s first byte must be the slave address with the R W bit set to 1 The following conditions must be fulfilled to use the I2C driver routines in master mode For 7 bit addressing the first byte of the send buffer must have the slave address in the most significant 7 bits and the least significant R W bit 0 Example Slave address 0x53 first byte is OxA6 For 7 bit addressing the first byte of the receive buffer must have the slave address in the most significant 7 bits and the least significant R W bit 2 1 Example Slave Addr 0x53 first byte OxA7 For 10 bit address the first byte of the transmit buffer must have the slave address most significant 2 bits with the R W bit 20 The second byte must contain the remaining 8 bit of the slave address For 10 bit address the first byte of the receive buffer must have the slave address most significant 2 bits with the R W bit 21 The second byte must contain the remaining 8 bit of the slave address The number of bytes to be transmitted should include the first byte of the buffer which is the slave address byte Example 2 data bytes 7 bit slave addr 3 e The application program must enable 12 interrupts When I2C interrupt occurs the i2c isr handler function must be called from the application program When using the interrupt
120. to flash is not returned See Table 225 The ISP mode uses the USARTO interface for communication If USARTO is used in an application reset USARTO see Table 7 before using the IAP command 57 Reinvoke ISP See Table 244 UART following deviations from the specification apply UART synchronous mode not supported API functions uart put line and uart get line do not return an interrupt on error See Table 279 and Table 280 UART API return codes are numbered 0x0007 0001 to 0x0007 0005 12C No changes Power No changes profiles UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 241 of 326 NXP Semiconductors U M1 0601 Chapter 20 LPC800 Boot ROM Table 211 Boot loader versions Bootloader Marking Description version v13 2 2A ISP IAP The following updates compared to v13 1 apply The IAP erase page command allows multiple page erase Any start page number that is smaller or equal to the end page number is allowed as start page in the IAP erase page command See Table 246 Code SECTOR NOT PREPARED FOR WRITE OPERATION in ISP command C Write RAM to flash is returned See Table 225 AP command 57 Reinvoke ISP can be called without resetting USARTO first SP command S Read CRC checksum added See Table 234 UART The following updates compared to v13 1 ap
121. to the RXDAT register when it is already in use The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur 0 No interrupt will be generated when a receiver overrun occurs An interrupt will be generated if a receiver overrun occurs 3 TXUREN Determines whether an interrupt occurs when a transmitter underrun occurs This 0 happens in slave mode when there is a need to transmit data when none is available 0 No interrupt will be generated when the transmitter underruns An interrupt will be generated if the transmitter underruns UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 218 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 Table 192 SPI Interrupt Enable read and Set register INTENSET addresses 0x4005 800C SPIO 0x4005 CO0C SPI1 bit description Bit Symbol Value Description Reset value 4 SSAEN Determines whether an interrupt occurs when the Slave Select is asserted 0 0 No interrupt will be generated when any Slave Select transitions from deasserted to asserted 1 An interrupt will be generated when any Slave Select transitions from deasserted to asserted 5 SSDEN Determines whether an interrupt occurs when the Slave Select is deasserted 0 0 No interrupt will be generated when al
122. uart get mem size void UART HANDLE T uart setup uint32 t base addr uint8 t ram uint32 t uart ini UART HANDLE T handle CONFIG set uint8 t uart get char UART HANDLE T handle void uart put char UART HANDLE T handle uint8 t data uint32 t uart get line UART HANDLE T handle UART PARAM T param uint32 t uart put line UART HANDLE T handle UART T param void uart is UART HANDLE T handle Description Reference UART get memory size Table 274 UART set up Table 275 UART init Table 276 UART get character Table 277 UART put character Table 278 UART get line Table 279 UART put line Table 280 UART interrupt service routine Table 281 The following structure has to be defined to use the UART API typedef struct 11 index of all the uart driver functions uint32 t uart get mem size void UART HANDLE uart setup uint32 t base addr uint8_t ram u Il u V u polling functions c u interrupt functions void uart isr UART HANDLE T handle UARTD API T II end of structure 24 4 14 UART get memory size Table 274 uart get mem size nt8 t uart get charUART HANDLE T handle id uart put char UART HANDLE handle uint8_t data nt32 t uart get HANDLE handle PARAM param nt32 t uart put lineUART HANDLE T handle PARAM T param nt32 t uart init UART HANDLE
123. user manual Rev 1 1 24 January 2013 51 of 326 UM10601 Chapter 6 LPC800 I O configuration IOCON Rev 1 1 24 January 2013 Preliminary user manual 6 1 How to read this chapter The block is identical for all LPC800 parts Registers for pins that are not available on a specific package are reserved Table 47 Pinout summary Package Pins configuration registers available TSSOP16 PIOO 0 to PIOO 13 TSSOP20 PIOO 0 to PIOO 17 SOP20 PIOO 0 to PIOO 17 DIP8 PIOO 0 to PIOO 5 6 2 Features The following electrical properties are configurable for each pin Pull up pull down resistor Open drain mode Hysteresis Digital glitch filter with programmable time constant Analog mode for a subset of pins see the LPC81xM data sheet The true open drain pins PIOO 10 and PIOO 11 can be configured for different I2C bus speeds 6 3 Basic configuration Enable the clock to the IOCON in the SYSAHBCLKCTRL register Table 18 bit 18 Once the pins are configured you can disable the IOCON clock to conserve power UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 52 of 326 NXP Semiconductors UM10601 6 4 General description Chapter 6 LPC800 I O configuration IOCON 6 4 4 Pin configuration pin configured as digital output driver pin confi
124. write ones to reserved bits NA The value read from a reserved bit is not defined 12 7 Functional description The following figures illustrate several aspects of Watchdog Timer operation WDCLK 4 Se Beat Re Re ee ee eee er NI Watchdo Confer s 125A X 1259 X 1258 X 1257 X Early Feed Event Watchdog Reset Conditions WINDOW 0x1200 WARNINT 0x3FF TC 0x2000 Fig 23 Early watchdog feed with windowed mode enabled WDCLK 4 NN NN NN NT NINE NEOUS Watchdog Counter 1201 1200 11 11FEX 11FD 11FC X 2000 1FFF 1FFE 1FFD 1FEC Correct Feed Event Watchdog Reset Conditions WDWINDOW 0x1200 WDWARNINT Ox3FF WDTC 0x2000 Fig 24 Correct watchdog feed with windowed mode enabled woetk 4 AAS AA NS NAI eae 0403 X 0402 X 0401 X 0400 X03FF XosrE KosFc KosrB XosFA 03F 9 Watchdog Interrupt Conditions WINDOW 0x1200 WARNINT TC 0x2000 Fig 25 Watchdog warning interrupt UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 158 of 326 UM10601 Chapter 13 LPC800 Analog comparator Rev 1 1 24 January 2013 Preliminary user manual 13 1 How to read this chapter 13 2 Features The analog
125. 0 31 28 Reserved Read value is undefined only zero should be written 17 6 10 SPI Divider register The DIV register determines the clock used by the SPI in master mode For details on clocking see Section 17 7 3 Clocking and data rates Table 198 SPI Divider register DIV addresses 0x4005 8024 SPIO 0x4005 C024 SPI1 bit description Bit Symbol Description Reset Value 15 0 DIVVAL Rate divider value Specifies how the PCLK for the SPI is divided to 0 produce the SPI clock rate in master mode DIVVAL is 1 encoded such that the value 0 results in PCLK 1 the value 1 results in PCLK 2 up to the maximum possible divide value of OxFFFF which results in PCLK 65536 31 16 Reserved Read value is undefined only zero should be written NA 17 6 11 SPI Interrupt Status register The read only INTSTAT register provides a view of those interrupt flags that are currently enabled This can simplify software handling of interrupts See Table 191 for detailed descriptions of the interrupt flags Table 199 SPI Interrupt Status register INTSTAT addresses 0x4005 8028 SPIO 0x4005 C028 SPI1 bit description Bit Symbol Description Reset value 0 RXRDY Receiver Reagy flag 0 1 TXRDY Transmitter Ready flag 1 2 RXOV Receiver Overrun interrupt flag 0 3 TXUR Transmitter Underrun interrupt flag 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All r
126. 0 Selects pin interrupt input 4 as the source to bit slice O Selects pin interrupt input 5 as the source to bit slice O Selects pin interrupt input 6 as the source to bit slice 0 Selects pin interrupt input 7 as the source to bit slice 0 Selects the input source for bit slice 1 Input 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Selects pin interrupt input O as the source to bit slice 1 Selects pin interrupt input 1 as the source to bit slice 1 Selects pin interrupt input 2 as the source to bit slice 1 Selects pin interrupt input 3 as the source to bit slice 1 Selects pin interrupt input 4 as the source to bit slice 1 Selects pin interrupt input 5 as the source to bit slice 1 Selects pin interrupt input 6 as the source to bit slice 1 Selects pin interrupt input 7 as the source to bit slice 1 Selects the input source for bit slice 2 Input 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Selects pin interrupt input 0 as the source to bit slice 2 Selects pin interrupt input 1 as the source to bit slice 2 Selects pin interrupt input 2 as the source to bit slice 2 Selects pin interrupt input 3 as the source to bit slice 2 Selects pin interrupt input 4 as the source to bit slice 2 Selects pin interrupt input 5 as the source to bit slice 2 Selects pin interrupt input 6 as the source to bit slice 2 Selects pin interrupt input 7 as the source to bit slice 2 Selects the input
127. 0 6 1 20 6 2 UM10601 Memory map after any reset The boot block is 8 kB in size The boot block is located in the memory region starting from the address 0x1FFF 0000 The bootloader is designed to run from this memory area but both the ISP and IAP software use parts of the on chip RAM The RAM usage is described later in this chapter The interrupt vectors residing in the boot block of the on chip flash memory also become active after reset i e the bottom 512 bytes of the boot block are also visible in the memory region starting from the address 0x0000 0000 Boot process During the boot process the boot loader checks if there is valid user code in flash The criterion for valid user code is as follows The reserved Cortex M0 exception vector location 7 offset 0x0000 001C in the vector table should contain the 2 s complement of the check sum of table entries 0 through 6 This causes the checksum of the first 8 table entries to be 0 The bootloader code checksums the first 8 locations in sector O of the flash If the result is 0 then execution control is transferred to the user code If the signature is not valid the auto baud routine synchronizes with the host via serial port USARTO The host should send a Ox3F as a synchronization character and wait for a response The host side serial port settings should be 8 data bits 1 stop bit and no parity The auto baud routine measures the bit time of the received synchronization ch
128. 0 UART ROM driver variables 297 2441 UART get memory 512 294 244 10 1 UART CONFIG structure 297 2442 UARTsetup 66 eee ee eee 295 24440 2 UART HANDLE 297 24 4 3 UART init 3 3 3 33 9 3 9 9 9 295 24 4 10 3 UART PARAM T DOPPLER 297 24 4 4 UART get 295 24 4 5 UART put 295 Chapter 25 LPC800 Debugging 25 1 How to read this chapter 299 25 Functional description 300 25 2 Features scs c us e RR RE Rea RA 299 25 5 1 Debug limitations 300 253 General 299 25 52 Debug connections for SWD 300 25 5 3 Boundary 301 25 4 Pin 299 2554 Micro Trace Buffer MTB 302 Chapter 26 LPC800 Packages and pin description 26 1 Packages 303 26 2 Pin description 304 Chapter 27 LPC800 Appendix 27 1 How to read this chapter 308 27 2 Generaldescription 308 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 325 of 326 NXP Semiconductor
129. 000 0090 Table 60 PIOO 1 ACMP H CLKIN 0x030 Reserved PIOO 9 R W 0x034 I O configuration for pin 0x0000 0090 Table 61 PIOO S XTALOUT PIOO 8 R W 0x038 I O configuration for pin PIOO_8 XTALIN 0x0000 0090 Table 62 PIOO 7 R W 0x03C I O configuration for PIOO 7 0x0000 0090 Table 63 PIOO 6 R W 0x040 I O configuration for pin 0x0000 0090 Table 64 PIO0O_6 VDDCMP PIOO 0 R W 0x044 I O configuration for pin 0x0000 0090 Table 65 PIOO 0 ACMP 10 PIOO 14 R W 0x048 I O configuration for pin PIOO_14 0x0000 0090 Table 66 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 55 of 326 NXP Semiconductors UM10601 6 5 1 PIOO 17 register Chapter 6 LPC800 I O configuration IOCON Table 49 17 register PIOO 17 address 0x4004 4000 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode ena
130. 013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 221 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 Table 195 SPI Transmitter Data and Control register TXDATCTL addresses 0x4005 8018 SPIO 0x4005 C018 SPI1 bit description continued Bit Symbol Value Description Reset value 23 Reserved Read value is undefined only zero should be written NA 27 24 FLEN Frame Length Specifies the frame length from 1 to 16 bits Note that frame lengths 0x0 greater than 16 bits are supported by implementing multiple sequential frames Note that if a 1 bit frame is selected the master function will always insert a delay with a length of one SCK time following the single clock seen on the SCK pin 0x0 Data frame is 1 bit in length 0x1 Data frame is 2 bits in length 0x2 Data frame is 3 bits in length OxF Data frame is 16 bits in length 31 28 Reserved Read value is undefined only zero should be written NA 17 6 8 SPI Transmitter Data Register The TXDAT register is written in order to send data via the SPI transmitter when control information is not changing during the transfer see Section 17 6 7 That data will be sent to the transmit shift register when it is available and another character may then be written to TXDAT Table 196 SPI Transmitter Data Register TXDAT addresses 0x4005 801C SPIO 0x4005 C01C SPI1 bit description Bit Symbol Description Reset
131. 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 lt Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 72 of 326 NXP Semiconductors UM10601 6 5 18 14 register Chapter 6 LPC800 I O configuration IOCON Table 66 14 register PIOO 14 address 0x4004 4048 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain
132. 1 LPC800 block diagram UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 6 of 326 NXP Semiconductors U M1 0601 Chapter 1 LPC800 Introductory information 1 5 General description 1 5 1 ARM Cortex M0 core configuration The ARM Cortex M0 core runs at an operating frequency of up to 30 MHz Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watch points The ARM Cortex MO core supports a single cycle I O enabled port IOP for fast GPIO access at address 0xA000 0000 The core includes a single cycle multiplier and a system tick timer SysTick UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 7 of 326 UM10601 Chapter 2 LPC800 Memory mapping Rev 1 1 24 January 2013 Preliminary user manual 2 1 How to read this chapter The memory mapping is identical for all LPC800 parts Different LPC800 parts support different flash memory sizes 2 2 General description UM10601 The LPC800 incorporates several distinct memory regions Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset The APB peripheral area is 512 kB in size and is divided to allow for up to 32 per
133. 12 6 3 UM10601 Chapter 12 LPC800 Windowed Watchdog Timer WWDT Table 143 Watchdog operating modes selection WDEN WDRESET Mode of Operation 0 X 0or1 Debug Operate without the Watchdog running 1 0 Watchdog interrupt mode the watchdog warning interrupt will be generated but watchdog reset will not When this mode is selected the watchdog counter reaching the value specified by WOWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated 1 1 Watchdog reset mode both the watchdog interrupt and watchdog reset are enabled When this mode is selected the watchdog counter reaching the value specified by WOWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated and the watchdog counter reaching zero will reset the microcontroller A watchdog feed prior to reaching the value of WDWINDOW will also cause a watchdog reset Watchdog Timer Constant register The TC register determines the time out value Every time a feed sequence occurs the value in the TC is loaded into the Watchdog timer The TC resets to 0x00 OOFF Writing a value below OxFF will cause 0x00 OOFF to be loaded into the TC Thus the minimum time out interval is Twpcik x 256 x 4 If the WDPROTECT bit in WDMOD 1 an attempt to change the value of TC before the watchdog counter is below the values of WDWARNINT and WDWINDOW will cause a watchdog reset and set the WDTOF flag Table 144 Watchdog Timer Constant
134. 124 4072 136 10 6 6 start condition register 125 1073 136 10 6 7 5 125 41074 197 10 6 8 5 126 1075 Interrupt 137 10 6 9 input 127 10 7 6 Clearing the 138 10 6 10 SCT match capture registers mode register 127 10 7 7 Match vs Oevents 138 10 6 11 5 128 4078 5 139 10 6 12 SCT bidirectional output control register 128 10 7 9 Configure the SCT 139 10 6 13 SCT conflict resolution register 129 10 7 9 1 Configure the counter 139 10 6 14 SCT flag enable register 130 10 7 92 Configure the match and capture registers 139 10 6 15 SCT event flag 130 10 7 9 3 Configure events and event responses 140 10 6 16 SCT conflict enable register 130 10 79 4 Configure multiple 141 10 6 17 SCT conflict flag register 131 10 79 5 Miscellaneous options 141 10 6 18 SCT match registers 0 to 4 REGMODEn 10 7 10
135. 16 CLKOUT clock source update enable register 27 4 7 1 4 2 PLL Power down mode 40 Chapter 5 LPC800 Reduced power modes and Power Management Unit PMU 5 1 How to read this chapter 41 5 4 Pin description 41 5 2 Features 41 5 5 General description 41 5 3 Basic configuration 41 5 5 1 Wake up 42 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 319 of 326 NXP Semiconductors UM10601 Chapter 28 Supplementary information 5 6 Register description 43 5 7 5 Deep sleep mode 48 5 6 1 Power control register 44 5 7 5 1 Power configuration in Deep sleep mode 48 5 6 2 General purpose registers O to 3 44 5 7 5 2 Programming Deep sleep mode 48 5 6 3 Deep power down control register 45 5 7 5 8 Wake up from Deep sleep mode 48 5 7 Functional description 46 5 7 6 Power down 49 5 7 1 Power n 46 5 7 6 1 Power configuration in Power down mode 49 5 7 2 Reduced power modes and WWDT lock 5 7 6 2 Programming Power down mode 49 POPES ol ocior c cv 46 5 7 6 3 Wake up from Power down mode
136. 167 USART Interrupt Status register INTSTAT address 0x4006 4024 USARTO 0x4006 8024 USART1 0x4006 C024 USART2 bit deScriptlon 2s reae e eem on iR 183 Table 168 I2C bus pin description 189 Table 169 Register overview I2C base address 0x4005 0000 cs tute tea Ses 191 Table 170 I2C Configuration register CFG address 0x4005 0000 bit 191 Table 171 I C Status register STAT address 0x4005 0004 bit description 193 Table 172 Master function state codes MSTSTATE 196 Table 173 Slave function state codes SLVSTATE 196 Table 174 Interrupt Enable Set and read register INTENSET address 0x4005 0008 bit description 2l ilv Er RR 197 Table 175 Interrupt Enable Clear register INTENCLR address 0x4005 000C bit description Table 176 time out register TIMEOUT address 0x4005 UM10601 All information provided in this document is subject to legal disclaimers Chapter 28 Supplementary information 0010 bit description 200 Table 177 I C Clock Divider register DIV address 0x4005 0014 bit description 200 Table 178 I C Interrupt Status register INTSTAT address 0x4005 0018 bit description 201 Table 179 Master Control register MSTCTL address 0x4005 0020 bit description 201 Table 180 Master Time register MSTTIME address 0x4005 0024 bit
137. 2 this occurs if the previously received data is not read before the end of the next piece of is received This stall happens one clock edge earlier than the transmitter stall In modes 1 and 3 the same kind of receiver stall can occur but just before the final clock edge of the received data Also a transmitter stall will not happen in modes 1 and 3 because the transmitted data is complete at the point where a stall would otherwise occur so it is not needed Stalls are reflected in the STAT register by the Stalled status flag which indicates the current SPI status All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 230 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 Transmitter stall CPHA 0 Frame delay 0 Pre delay 0 Post delay 0 2 clock stall Modeo cpoL 0 sck NT N NT NT NL Mode2 cPpoL 1 sek S 17 NL NL VS MOSI MSB LSB MSB LSB X X LSB Y ise Y gt lt gt First data frame Second data frame Receiver stall 0 Frame delay 0 Pre delay 0 Post delay 0 2 clock stall MdeocPoL 9 sek ff Z VN V NN wuezper 9 LA PN vse X LSB ise Y lt gt lt First data frame Second data frame Receiver stall CPHA 1 Frame delay 0 Pre delay 0
138. 2 ed ccu 185 Generaldescription 232 1872 CRC 16 E DP tsi ae 235 18 6 Register description 234 18 73 CRC 32 236 18 6 1 CRC mode register 234 Chapter 19 LPC800 Flash controller 19 1 How to read this chapter 237 19 4 3 Flash signature stop address register 238 19 2 Ig 237 19 4 4 Flash signature generation result register 238 19 3 General description 237 19 5 Functional description 239 19 4 Register description 237 19 5 1 Flash signature generation 239 19 4 1 Flash configuration register 237 195 111 Signature generation address and control 19 4 2 Flash signature start address register 238 registers eese nn n nn nn 239 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 323 of 326 NXP Semiconductors UM10601 Chapter 28 Supplementary information 19 5 1 2 Signature generation 239 19 5 1 3 Content verification 240 Chapter 20 LPC800 Boot ROM 20 1 How to read this chapter 241 20 5 1 Boot loader 242 20 2 Features 241 20 52
139. 21 UM10601 Chapter 10 LPC800 State Configurable Timer SCT Table 125 SCT match registers 0 to 4 MATCH 0 4 address 0x5000 4100 MATCHO to 0x5000 4110 MATCH4 bit description REGMODEn bit 0 Bit Symbol Description Reset value 15 0 VALMATCH L When UNIFY 0 read or write the 16 bit value to be compared 0 to the L counter When UNIFY 1 read or write the lower 16 bits of the 32 bit value to be compared to the unified counter 31 16 VALMATCH When UNIFY 0 read or write the 16 bit value to be compared 0 to the H counter When UNIFY 1 read or write the upper 16 bits of the 32 bit value to be compared to the unified counter SCT capture registers 0 to 4 REGMODEn bit 1 These registers allow software to read the counter values at which the event selected by the corresponding Capture Control registers occurred Table 126 SCT capture registers 0 to 4 CAP 0 4 address 0x5000 4100 CAPO to 0x5000 4110 CAP4 bit description REGMODEn bit 1 Bit Symbol Description Reset value 15 0 VALCAP_L When UNIFY read the 16 bit counter value at which this 0 register was last captured When UNIFY 1 read the lower 16 bits of the 32 bit value at which this register was last captured 31 16 When UNIFY 0 read the 16 bit counter value at which this 0 register was last captured When UNIFY 1 read the upper 16 bits of the 32 bit value at which this register was last captured SCT mat
140. 24 January 2013 15 of 326 NXP Semiconductors U M1 0601 Chapter 4 LPC800 System configuration SYSCON SYSCON AHB clock 0 core system main clock OCK DIVIDER System clock always on SYSAHBCLKDIV memories and peripherals peripheral clocks SYSAHBCLKCTRL 1 19 system clock enable CLOCK DIVIDER FRACTIONAL RATE USARTO UARTCLKDIV GENERATOR USART1 gt USART2 CLOCK DIVIDER IOCON IOCONCLKDIV glitch filter watchdog oscillator MAINCLKSEL main clock select IRC oscillator IRC oscillator M E system oscillator UN CLKOUT pin XOU Ger aor SYSTEM PLL watchdog oscillator CLKIN CLKOUTSEL CLKOUT clock select SYSPLLCLKSEL system PLL clock select watchdog oscillator gt WWDT IRC oscillator gt WKT low power oscillator gt WKT aaa 005749 Fig 3 LPC800 clock generation 4 5 2 Power control of analog components The system control block controls the power to the analog components such as the oscillators and PLL the BOD and the analog comparator For details see the following registers Section 4 6 30 Deep sleep mode configuration register Section 4 6 3 System PLL control register Section 4 6 6 Watchdog oscillator control register Section 4 6 5 System oscillator control register UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights r
141. 24 January 2013 186 of 326 UM10601 Chapter 16 LPC800 I2C bus interface Rev 1 1 24 January 2013 Preliminary user manual 16 1 How to read this chapter 16 2 Features The I2C bus interface is available on all parts Read this chapter if you want to understand the I2C operation and the software interface and want to learn how to use the 12C for wake up from reduced power modes The LPC800 provides an on chip ROM based I2C API to configure and operate the 12C See Table 252 2 API calls Independent Master Slave and Monitor functions Supports both Multi master and Multi master with Slave functions Multiple 2 slave addresses supported in hardware One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple 12C bus addresses 10 bit addressing supported with software assist Supports SMBus 16 3 Basic configuration UM10601 Configure I2C using the following registers In the SYSAHBCLKCTRL register set bit 5 Table 18 to enable the clock to the register interface Clear the 12 peripheral reset using the PRESETCTRL register Table 7 Enable disable the 12C interrupt in interrupt slots 8 in the NVIC Configure the I2C pin functions through the switch matrix See Section 16 4 The peripheral clock for the I2C is the system clock see Figure 30 Fig 30 12C clocking SYSCON system clock 2C PCLK lOlockdivider clock DI
142. 273 Table 274 Table 275 Table 276 Table 277 Table 278 Table 279 Table 280 Table 281 Table 282 Table 283 Table 284 Table 285 Table 286 Table 287 Table 288 All information provided in this document is subject to legal disclaimers Chapter 28 Supplementary information 263 IAP Compare command 264 IAP Reinvoke 1 265 IAP ReadUID command 265 IAP Erase page command 265 IAP Status Codes Summary 265 Memory mapping in debug mode 267 Power profile calls 270 _ 270 set routine 273 I2C calls 278 ISRiharidler RE 280 I2C Master Transmit Polling 280 I2C Master Receive Polling 280 I2C Master Transmit and Receive Polling 281 I2C Master Transmit Interrupt 281 I2C Master Receive Interrupt 281 I2C Master Transmit Receive Interrupt 282 I2C Slave Receive Polling 282 I2C Slave Transmit Polling 282 I2C Slave Receive Interrupt 283 I2C Slave Transmit Interrupt 283 I2C Set Slave Address 283 I2C Get Memory 5 283 l2C 284 I2C Set Bit Rate
143. 284 I2C Get Firmware Version 284 12 Get Status 284 I2C time out 285 Error Godes sisse 285 12 Status 285 UART calls 294 uart get mem size 294 Uart_S tUPp 2 eee 295 uart 295 uart get 295 uart put 295 uart get 296 uart put 296 ait ISt iss reu FG Rc EGRE 296 Errorcodes iei ee eR Pea eee RA 296 SWD pin description 299 JTAG boundary scan pin description 300 Pin description table fixed pins 305 Movable functions assign to pins PIOO 0 to 17 through switch matrix 306 Cortex MO instruction summary 308 Abbreviations 311 NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 317 of 326 NXP Semiconductors UM1 0601 Chapter 28 Supplementary information 28 5 Figures Fig 1 LPC800 block diagram 6 Fig 50 Pin configuration DIP8 package Fig 2 LPC800 Memory 9 810 0 21 8 303 Fig3 LPC800clock 16 Fig 51 Pin configuration TSSOP16 package 303 Fig
144. 4 System PLL block diagram 38 Fig 52 Pin configuration SO20 package Fig5 53 812 101 020 303 Fig 6 Pin interrupt connections 82 Fig 53 Pin configuration TSSOP20 package 304 Fig 7 Pattern match engine connections 84 Fig 8 Pattern match bit slice with detect logic 85 Fig 9 Pattern match engine examples sticky edge detect obe voted be voee ke prse dotes 101 Fig 10 Pattern match engine examples non sticky edge detect without pin 101 Fig 11 Pattern match engine examples non sticky edge detect pin interrrupt 102 Fig 12 Example Connect function UO RXD and UO TXD to pins 10 and 14 on the 5020 package 104 Fig 13 Functional diagram of the switch matrix 106 Fig 14 SCT block diagram 117 Fig 15 SCT counter and select logic 118 Fig 16 Match 136 Fig 17 Capture logic 136 Fig 18 Event selection 137 Fig 19 Output 51 137 Fig 20 SCT interrupt 137 Fig 21 MRT block diagram 144 Fig 22 Windowed Watchdog timer block diagram 152 Fig 23 Early watchdog feed with windowed mode enabled ERR
145. 4 5 6 4 6 6 4 7 UM10601 Chapter 6 LPC800 I O configuration IOCON The repeater mode enables the pull up resistor if the pin is high and enables the pull down resistor if the pin is low This causes the pin to retain its last known state if it is configured as an input and is not driven externally Repeater mode may typically be used to prevent a pin from floating and potentially using significant power if it floats to an indeterminate state if it is temporarily not driven Open drain mode An open drain mode can be enabled for all digital I O pins Except for pins PIOO 10 and PIOO 11 this mode is not a true open drain mode The input cannot be pulled up above Vpp Analog mode The switch matrix automatically configures the pin in analog mode whenever an analog input or output is selected as the pin s function I2C bus mode The I C bus pins PIOO 10 and PIOO 11 can be programmed to support a true open drain mode independently of whether the 12C function is selected or another digital function If the 12 function is selected all three IC modes Standard mode Fast mode and Fast mode plus are supported A digital glitch filter can be configured for all functions Pins PIOO 10 and PIOO 11 operate as high current sink drivers 20 mA independently of the programmed function Programmable glitch filter All GPIO pins are equipped with a programmable digital glitch filter The filter rejects input pulses with a selectable du
146. 5 OF ARBRITRATION 0x00060005 ERR I2C SLAVE NOT ADDRESSED 0x00060006 ERR I2C LOSS OF ARBRITRATION NAK BIT 0x00060007 ERR I2C GENERAL FAILURE 0x00060008 ERR 2 REGS SET DEFAULT All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 286 of 326 NXP Semiconductors U M1 0601 23 4 24 23 4 25 Chapter 23 LPC800 I2C bus ROM API ErrorCode t 12C Mode The i2c get status function returns the current status of the I2C engine The return codes can be defined as an enum structure typedef enum I2C mode IDLE MASTER SEND MASTER RECEIVE SLAVE SEND SLAVE RECEIVE I2C MODE T I2C ROM driver pointer The I2C ROM driver resides in the address Ox1FFF1FF8 The address must be declared to allow access to the ROM driver fdefine ROM DRIVERS ROM unsigned int OxlFFFIFF8 23 5 Functional description 23 5 1 23 5 2 UM10601 I2C Set up Before calling any setup functions in the I2C ROM the application program is responsible for doing the following 1 Enable the clock to the 12 peripheral 2 Enable the two pins required for the SCL and SDA outputs of the 12C peripheral 3 Allocate a RAM area for dedicated use of the 12C ROM Driver After the 12C block is configured the I2C ROM driver variables have to
147. 58 USART Configuration register CFG address 0x4006 4000 USARTO 0x4006 8000 USART1 0x4006 C000 USART2 bit description 175 Table 159 USART Control register CTRL address 0x4006 4004 USARTO 0x4006 8004 USART 1 0x4006 C004 USART2 bit description 177 Table 160 USART Status register STAT address 0x4006 4008 USARTO 0x4006 8008 USART1 0x4006 C008 USART2 bit description 178 Table 161 USART Interrupt Enable read and set register INTENSET address 0x4006 400C USARTO 0x4006 800C USART1 0x4006 USART2 bit description 179 Table 162 USART Interrupt Enable clear register INTENCLR address 0x4006 4010 USARTO 0x4006 8010 USART1 0x4006 C010 USART2 bit description 180 Table 163 USART Receiver Data register RXDATA address 0x4006 4014 USARTO 0x4006 8014 USART1 0x4006 C014 USART2 bit description ode 181 Table 164 USART Receiver Data with Status register RXDATASTAT address 0x4006 4018 USARTO 0x4006 8018 USART1 0x4006 C018 USART2 bit description 181 Table 165 USART Transmitter Data Register TXDATA address 0x4006 401C USARTO 0x4006 801C USART1 0x4006 C01C USART2 bit description 182 Table 166 USART Baud Rate Generator register BRG address 0x4006 4020 USARTO 0x4006 8020 USART1 0x4006 C020 USART2 bit descriptlon 2 remo dee 183 Table
148. 6 NXP Semiconductors U M1 0601 Chapter 16 LPC800 I2C bus interface Table 178 12 Interrupt Status register INTSTAT address 0x4005 0018 bit description Bit Symbol Description Reset value MSTPENDING Master Pending 1 3 1 Reserved MSTARBLOSS Master Arbitration Loss flag 0 5 Reserved Read value is undefined only zero should be NA written 6 MSTSTSTPERR Master Start Stop Error flag 0 7 Reserved Read value is undefined only zero should be NA written 8 SLVPENDING Slave Pending 0 10 9 Reserved Read value is undefined only zero should be NA written 11 SLVNOTSTR Slave Not Stretching status 1 14 12 Reserved Read value is undefined only zero should be NA written 15 SLVDESEL Slave Deselected flag 16 MONRDY Monitor Ready 17 MONOV Monitor Overflow flag 18 Reserved Read value is undefined only zero should be NA written 19 MONIDLE Monitor Idle flag 0 23 20 Reserved Read value is undefined only zero should be NA written 24 EVENTTIMEOUT Event time out Interrupt flag 25 SCLTIMEOUT SCL time out Interrupt flag 31 26 Reserved Read value is undefined only zero should be NA written 16 6 8 Master Control register The MSTCTL register contains bits that control various functions of the I2C Master interface Only write to this register when the master is pending MSTPENDING 1 in the STAT register Table 171 Table 179 Master Control register MSTCTL address 0x4005 0020
149. 6 0001 ERR I2C NAK 0x0006 0002 ERR I2C BUFFER OVERFLOW 0x0006 0003 ERR I2C BYTE COUNT ERR 0x0006 0004 ERR I2C LOSS OF ARBRITRATION 0x0006 0005 ERR I2C SLAVE NOT ADDRESSED 0x0006 0006 ERR I2C LOSS OF ARBRITRATION NAK BIT 0x0006 0007 ERR I2C GENERAL FAILURE Failure detected on I2C bus 0x0006 0008 ERR I2C REGS SET TO DEFAULT 12C clock frequency could not be set Default value of 0x04 is loaded into SCLH and SCLL 23 4 20 12 Status code Table 272 I2C Status code Status code Description 0 IDLE 23 4 21 23 4 21 1 UM10601 MASTER SEND MASTER RECEIVE SLAVE SEND SLAVE RECEIVE 12C ROM driver variables The I2C ROM driver requires specific variables to be declared and initialized for proper usage Depending on the operating mode some variables can be omitted 12C Handle The I2C handle is a pointer allocated for the I2C ROM driver The handle needs to be defined as an 12 handle TYPE typedef void I2C HANDLE T All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 285 of 326 NXP Semiconductors UM1 0601 23 4 22 23 4 23 UM10601 Chapter 23 LPC800 I2C bus ROM API After the definition of the handle the handle must be initialized with I2C base address and RAM reserved for the I2C ROM driver by making call to the i2c_setup function The callback function type must be
150. 601 Chapter 10 LPC800 State Configurable Timer SCT Each Capture Control register L H or unified 32 bit controls which events load the corresponding Capture register from the counter Table 128 SCT capture control registers 0 to 4 CAPCTRL 0 4 address 0x5000 4200 CAPCTRLO to 0x5000 4210 CAPCTRL4 bit description REGMODEn bit 1 Bit Symbol Description Reset value 5 0 CAPCONm L If bit m is one event m causes the CAPn L UNIFY 0 orthe 0 CAPn UNIFY 1 register to be loaded event 0 bit 0 event 1 bit 1 event 5 bit 5 156 Reserved 21 16 If bit m is one event m causes the CAPn UNIFY 0 0 register to be loaded event 0 bit 16 event 1 bit 17 event 5 bit 21 31 22 Reserved SCT event state mask registers 0 to 5 Each event has one associated SCT event state mask register that allow this event to happen in one or more states of the counter selected by the HEVENT bit in the corresponding EVn_CTRL register An event n is disabled when its EVn STATE register contains all zeros since it is masked regardless of the current state In simple applications that do not use states write 0x01 to this register to enable an event Since the state always remains at its reset value of 0 writing 0x01 permanently state enables this event Table 129 SCT event state mask registers 0 to 5 EV 0 5 STATE addresses 0x5000 4300 EVO STATE to 0x5000 4328 EV5 STATE b
151. 601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 176 of 326 NXP Semiconductors UM10601 Chapter 15 LPC800 USARTO 1 2 Table 159 USART Control register CTRL address 0x4006 4004 USARTO 0x4006 8004 USART1 0x4006 C004 USART2 bit description Bit Symbol 1 TXBRKEN 2 ADDRDET 5 3 6 TXDIS 9 CLRCC 31 10 Value Description Reset Value Reserved Read value is undefined only zero should be NA written Break Enable 0 Normal operation Continuous break is sent immediately when this bit is set and remains until this bit is cleared A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled TXDIS in CTRL is set and then waiting for the transmitter to be disabled TXDISINT in STAT 1 before writing 1 to TXBRKEN Enable address detect mode 0 Enabled The USART receiver is enabled for all incoming data Disabled The USART receiver ignores incoming data that does not have the most significant bit of the data typically the 9th bit 1 When the data MSB bit 1 the receiver treats the incoming data normally generating a received data interrupt Software can then check the data to see if this is an address that should be handled If it is the ADDRDET bit is cleared by software and further incoming data is h
152. 7 2 0 8 3 0 MHz 0x9 3 25 MHz OxA 3 5 MHz 0xB 3 75 MHz 4 0 MHz OxD 4 2 MHz OxE 4 4 MHz OxF 4 6 MHz 31 9 Reserved 0x00 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 22 of 326 NXP Semiconductors U M1 0601 Chapter 4 LPC800 System configuration SYSCON 4 6 7 System reset status register If another reset signal for example the external RESET pin remains asserted after the POR signal is negated then its bit is set to detected Write a one to clear the reset The reset value given in Table 12 applies to the POR reset Table 12 System reset status register SYSRSTSTAT address 0x4004 8030 bit description Bit Symbol Value Description Reset value 0 POR POR reset status 0 0 No POR detected 1 POR detected Writing a one clears this reset 1 EXTRST External reset status 0 0 No reset event detected 1 Reset detected Writing a one clears this reset 2 WDT Status of the Watchdog reset 0 0 No WDT reset detected 1 WDT reset detected Writing a one clears this reset 3 BOD Status of the Brown out detect reset 0 0 No BOD reset detected 1 BOD reset detected Writing a one clears this reset 4 SYSRST Status of the software system reset 0 0 No System reset detected 1 System reset detected Writing a one clears this reset 31 5 Reserved 4 6 8 System PLL clock source
153. 8 16 6 15 Monitor data register 206 165 1 189 16 7 Functional description 207 i 16 6 Register description 190 67 1 Bus rates and timing considerations 207 16 6 1 12C Configuration register 191 1671 1 207 16 6 2 12 5 193 16 7 2 207 16 6 3 Interrupt Enable Set and read register 197 16 73 208 16 6 4 Interrupt Enable Clear register 198 16 74 Clocking and power considerations 208 16 65 Time out value 199 4675 Interrupts 209 16 6 6 I2C Clock Divider register 200 Chapter 17 LPC800 SPIO0 1 17 1 How to read this chapter 210 17 6 7 SPI Transmitter Data and Control register 221 17 2 Pedl lBS dace Ea 210 17 68 SPI Transmitter Data Register 222 17 3 Basic configuration 210 17 6 9 SPI Transmitter Control register 222 ME AUDIRE DM NM 17 6 10 SPI Divider register 223 17 3 1 Configure the SPls for wake up 211 3 17 3 1 1 Wake up from Sleep 241 17 6 11 Interrupt Ss register 223 17 3 1 2 Wake up from Deep sleep
154. 800 Debugging Rev 1 1 24 January 2013 Preliminary user manual 25 1 How to read this chapter The debug functionality is identical for all LPC800 parts 25 2 Features Supports ARM Serial Wire Debug mode Direct debug access to all memories registers and peripherals No target resources are required for the debugging session Four breakpoints Two data watchpoints that can also be used as triggers Supports JTAG boundary scan Micro Trace Buffer MTB supported 25 3 General description Debug functions are integrated into the ARM Cortex M0 Serial wire debug functions are supported The ARM Cortex MO is configured to support up to four breakpoints and two watchpoints Support for boundary scan and Micro Trace Buffer is available 25 4 Pin description The SWD functions are assigned to pins through the switch matrix The SWD functions are fixed pin functions that are enabled through the switch matrix and can only be assigned to special pins on the package The SWD functions are enabled by default See Section 9 3 2 to enable the analog comparator inputs and the reference voltage input Table 283 SWD pin description Function Type Pin Description SWM register Reference SWCLK SWCLK PIOO 3 Serial Wire Clock This pin is the clock for SWD PINENABLEO Table 105 TCLK debug logic when in the Serial Wire Debug mode SWD This pin is pulled up internally SWDIO SWDIO PI
155. AM ptp I2C RESULT rrorCode t i2c slave receive poll I2C HANDLE T h i2c I2C PARAM ptp I2C RESULT ErrorCode t i2c slave transmit poll I2C HANDLE T h i2c I2C PARAM ptp ErrorCode t i2c slave receive intr I2C HANDLE T h i2c I2C PARAM ptp I2C RESULT rrorCode t i2c slave transmit intr I2C HANDLE T h i2c I2C PARAM ptp ErrorCode t i2c set slave addr I2C HANDLE T h_i2c uint32 t slave addr 0 3 uint32 t slave mask 0 3 OTHER functions int32 t i2c get mem size void ramsize in bytes memory needed I2C drivers UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 279 of 326 NXP Semiconductors U M1 0601 23 4 1 23 4 2 23 4 3 UM10601 Chapter 23 LPC800 I2C bus ROM API I2C HANDLE T i2c setup uint32 t i2c base uint32 t start of ram ErrorCode t i2c set bitrate I2C HANDLE T h i2c uint32 t P clk in hz uint32 t bitrate in bps uint32 t i2c get firmware version 2 MODE T i2c get status I2C HANDLE T h i2c I2CD API T ISR handler Table 253 ISR handler Routine ISR handler Prototype void i2c isr handler I2C HANDLE T Input parameter 12 _ HANDLE T Handle to the allocated SRAM area Return None Description I2C ROM Driver interrupt service routine This functio
156. API 2C RESULT is a containing the results after the function executes Section 23 4 22 To initiate a master mode write read the I2C PARAM has to be setup The l2C_PARAM is a structure with various variables needed by the I2C ROM Driver to operate correctly The structure contains the following e Number of bytes to be transmitted Number of bytes to be received Pointer to the transmit buffer Pointer to the receive buffer Pointer to callback function Stop flag The RESULT structure contains the results after the function executes The structure contains the following Number of bytes transmitted Number of bytes received Remark The number of bytes transmitted is updated only for i2c slave send poll and i2c slave send intr The number of bytes received is updated only for i2c slave receive poll and i2c slave receive intr To initiate a slave mode communication the receive function is called This can be either the polling or interrupt driven function 2 slave receive poll or i2c slave receive intr respectively The receive buffer should be as large or larger than any data or command that will be received If the amount of data exceed the receive buffer size an error code will be returned In slave receive mode the driver receives data until one of the following are true Address matching set in the set slave addr function with the R W bit set to 1 STOP or repeated START i
157. Allows trade off between interrupt 0 0000 0010 Table 30 latency and determinism NMISRC R W 0x174 NMI Source Control 0 Table 31 PINTSELO R W 0x178 GPIO Pin Interrupt Select register 0 0 Table 32 PINTSEL1 R W 0x17C GPIO Pin Interrupt Select register 1 0 Table 32 PINTSEL2 R W 0x180 GPIO Pin Interrupt Select register 2 0 Table 32 PINTSEL3 R W 0x184 GPIO Pin Interrupt Select register 3 0 Table 32 PINTSEL4 R W 0x188 GPIO Pin Interrupt Select register 4 0 Table 32 PINTSEL5 R W 0x18C GPIO Pin Interrupt Select register 5 0 Table 32 PINTSEL6 R W 0x190 GPIO Pin Interrupt Select register 6 0 Table 32 PINTSEL7 R W 0x194 GPIO Pin Interrupt Select register 7 0 Table 32 STARTERPO R W 0x204 Start logic 0 pin wake up enable register 0 Table 33 STARTERP1 R W 0x214 Start logic 1 interrupt wake up enable 0 Table 34 register UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 18 of 326 NXP Semiconductors U M1 0601 Chapter 4 LPC800 System configuration SYSCON Table 5 Register overview System configuration base address 0x4004 8000 continued Name PDSLEEPCFG PDAWAKECFG PDRUNCFG DEVICE ID Access Offset Description Reset value Reference R W 0x230 Power down states in deep sleep mode OxFFFF Table 35 R W 0x234 Power down states for wake up from OxEDFO Table 36 deep sleep R W 0x238 Power configuration register O
158. BLANK Result Contents of non blank word location This command is used to blank check a sector or multiple sectors of on chip flash memory To blank check a single sector use the same Start and End sector numbers Read Part Identification number IAP Table 241 IAP Read Part Identification command Command Input Return Code Result Description Read part identification number Command code 54 decimal Parameters None CMD_SUCCESS Result0 Part Identification Number This command is used to read the part identification number Read Boot code version number IAP Table 242 IAP Read Boot Code version number command Command Input Return Code Result Description Read boot code version number Command code 55 decimal Parameters None CMD_SUCCESS Result0 2 bytes of boot code version number Read as lt byte1 Major gt lt byte0 Minor gt This command is used to read the boot code version number All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 263 of 326 NXP Semiconductors UM10601 Chapter 21 LPC800 Flash ISP and IAP programming 21 5 2 7 Compare lt address1 gt address2 no of bytes gt IAP UM10601 Table 243 IAP Compare command Command Input Return Code Result Description Compare Command code 56 decimal ParamO
159. C 4 c a n 8 a a e gt a M to IN7 slice n 2 to slice Y n 2 to INO slice n 2 See Figure 8 for the detect logic block Fig 7 Pattern match engine connections UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 83 of 326 NXP Semiconductors U M1 0601 Chapter 8 LPC800 Pin interrupts pattern match engine The detect logic of each slice can detect the following events on the selected input Edge with memory sticky A rising edge a falling edge or a rising or falling edge that is detected at any time after the edge detection mechanism has been cleared The input qualifies as detected the detect logic output remains HIGH until the pattern match engine detect logic is cleared again Event non sticky Every time an edge rising or falling is detected the detect logic output for this pin goes HIGH This bit is cleared after one clock cycle and the detect logic can detect another edge Level A HIGH or LOW level on the selected input Figure 8 shows the details of the edge detection logic for each slice You can combine a sticky event with non sticky events to create a pin interrupt whenever a rising or falling edge occurs after a qualifying edge event You can create a time window during which rising or falling edges can create a pin interrupt by co
160. C MODE T i2c get status I2C HANDLE ErrorCode ti2c set timeout Il2C HANDLE h i2c uint32 t timeout Description Reference I2C Slave Receive Polling Table 260 I2C Slave Transmit Polling Table 261 I2C Slave Receive Interrupt Table 262 I2C Slave Transmit Interrupt Table 263 I2C Set Slave Address Table 264 12C Get Memory Size Table 265 12 Setup Table 266 I2C Set Bit Rate Table 267 12C Get Firmware Version Table 268 12C Get Status Table 269 I2C time out value Table 270 The following structure has to be defined to use the I2C MASTER functions typedef struct I2CD API index of all the i2c driver functions void i2c isr handler I2C HANDLE T h i2c ISR interrupt service request ErrorCode t i2c master transmit poll I2C HANDLE T h i2c I2C PARAM ptp I2C RESULT ptr ErrorCode t i2c master receive poll I2C HANDLE T h i2c I2C PARAM ptp 12C RESULT ptr ErrorCode t i2c master tx rx poll I2C HANDLE T h i2c I2C PARAM ptp I2C RESULT ptr I2C RESULT ptr SLAVE functions ptr I2C_RESULT ptr 1 I2C_RESULT ptr I2C RESULT ptr ErrorCode t i2c master transmit intr I2C HANDLE T h i2c I2C PARAM ptp ErrorCode t i2c master receive intr I2C HANDLE T h i2c I2C PARAM ptp ErrorCode t i2c master tx rx intr I2C HANDLE T h i2c I2C PAR
161. C clock pre divider is described in Table 177 Table 180 Master Time register MSTTIME address 0x4005 0024 bit description Bit Symbol Value Description Reset value 2 0 MSTSCLLOW Master SCL Low time Specifies the minimum low time 0 that will be asserted by this master on SCL Other devices on the bus masters or slaves could lengthen this time This corresponds to the parameter t ow in the 12C bus specification I C bus specification parameters tguF and tsu srA have the same values and are also controlled by MSTSCLLOW 0 0 2 clocks Minimum SCL low time is 2 clocks of the I2C clock pre divider 0x1 3 clocks Minimum SCL low time is clocks of the I2C clock pre divider 0x2 4 clocks Minimum SCL low time is 4 clocks of the 12C clock pre divider 0 3 5clocks Minimum SCL low time is 5 clocks of the I2C clock pre divider 0x4 6 clocks Minimum SCL low time is 6 clocks of the 12C clock pre divider 0x5 7 clocks Minimum SCL low time is 7 clocks of the I2C clock pre divider 0 6 8 clocks Minimum SCL low time is 8 clocks of the I2C clock pre divider Ox7 9 clocks Minimum SCL low time is 9 clocks of the 12C clock pre divider All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 202 of 326 NXP Semiconductors U M1 0601 16 6 10 16 6 11 UM10601 Chapter 16 LPC800 I2C bus interf
162. C register in the SYSCON block Table 31 To avoid using the same peripheral interrupt as NMI exception and normal interrupt disable the interrupt in the NVIC when you configure it as NMI Vector table offset The vector table contains the reset value of the stack pointer and the start addresses also called exception vectors for all exception handlers On system reset the vector table is located at address 0x0000 0000 Software can write to the VTOR register in the NVIC to relocate the the vector table start address to a different memory location For a description of the VTOR register see Ref 3 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 12 of 326 UM10601 Chapter 4 LPC800 System configuration SYSCON Rev 1 1 24 January 2013 Preliminary user manual 4 1 How to read this chapter The system configuration block is identical for all LPC800 parts USART2 and SPI1 are only available on parts LPC812M101FDH20 LPC812M101FDH16 and the corresponding clocks reset and wake up control bits are reserved for all other parts 4 2 Features Clock control Configure the system PLL Configure system oscillator and watchdog oscillator Enable clocks to individual peripherals and memories Configure clock output Configure clock dividers digital filter clock and USART baud rate cloc
163. C800 USARTO0 1 2 Updates for clarification in Chapter 8 LPC800 Pin interrupts pattern match engine Updates for clarification in Section 9 4 switch matrix to pin functional diagram Updates for clarification in Chapter 5 LPC800 Reduced power modes and Power Management Unit PMU Section 3 3 2 Non Maskable Interrupt NMI and Section 3 3 3 Vector table offset added Bit fields corrected in Section 10 6 USART baudrate clock output removed from USART features 1 20121109 Preliminary LPC800 user manual Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 2 of 326 UM10601 Chapter 1 LPC800 Introductory information Rev 1 1 24 January 2013 Preliminary user manual 1 1 Introduction 1 2 Features The LPC800 are an ARM Cortex MO based low cost 32 bit MCU family operating at CPU frequencies of up to 30 MHz The LPC800 support up to 16 kB of flash memory and 4 kB of SRAM The peripheral complement of the LPC800 includes a CRC engine one I C bus interface up to three USARTS up to two SPI interfaces one multi rate timer self wake up timer and state configurable timer one comparato
164. CON register Table 43 is cleared Write Ox3 to the PD bits in the PCON register see Table 43 Store data to be retained in the general purpose registers Section 5 6 2 Write one to the SLEEPDEEP bit in the ARM Cortex M0 SCR register Use the ARM WFI instruction 5 7 7 3 Wake up from Deep power down mode Pulling the WAKEUP pin LOW wakes up the LPC800 from Deep power down and the part goes through the entire reset process UM10601 1 On the WAKEUP pin transition from HIGH to LOW The PMU will turn on the on chip voltage regulator When the core voltage reaches the power on reset POR trip point a system reset will be triggered and the chip re boots All registers except the GPREGO to GPREGS will be in their reset state Once the chip has booted read the deep power down flag in the PCON register Table 43 to verify that the reset was caused by a wake up event from Deep power down and was not a cold reset Clear the deep power down flag in the PCON register Table 43 Optional Read the stored data in the general purpose registers Section 5 6 2 5 Set up the PMU for the next Deep power down cycle Remark The RESET pin has no functionality in Deep power down mode For using the self wake up timer for waking up from Deep power down mode see Section 14 5 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary
165. Clock PCLK to produce the I C function clock that is used to time various aspects of the I C interface The 12C function clock is used for some internal operations in the 12C block and to generate the timing required by the 12C bus specification some of which are user configured in the MSTTIME register for Master operation and the SLVTIME register for Slave operation See Section 16 7 1 1 Rate calculations for details on bus rate setup Table 177 Clock Divider register DIV address 0x4005 0014 bit description Bit Symbol Description Reset value 15 0 DIVVAL This field controls how the clock PCLK is used by the 12C functions 0 that need an internal clock in order to operate 0x0000 PCLK is used directly by the 12C function 0x0001 PCLK is divided by 2 before use by the I C function 0x0002 PCLK is divided by 3 before use by the I C function OxFFFF PCLK is divided by 65 536 before use by the I C function 31 16 Reserved Read value is undefined only zero should be written NA I2C Interrupt Status register The INTSTAT register provides register provides a view of those interrupt flags that are currently enabled This can simplify software handling of interrupts See Table 171 for detailed descriptions of the interrupt flags All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 200 of 32
166. Configurable Timer SCT Table 130 SCT event control register 0 to 5 EV 0 5 CTRL address 0x5000 4304 EVO CTRL to 0x5000 432C EV5 CTRL bit description Bit Symbol Value 20 MATCHMEM 22 21 DIRECTION 0x0 0 1 0 2 31 23 Description Reset value If this bit is one and the COMBMODE field specifies a match component to the triggering of this event then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up LESS THEN OR EQUAL TO the match value when counting down If this bit is zero a match is only be active during the cycle when the counter is equal to the match value Direction qualifier for event generation This field only applies when the counters are operating in BIDIR mode If BIDIR 0 the SCT ignores this field Value 0x3 is reserved Direction independent This event is triggered regardless of the count direction Counting up This event is triggered only during up counting when BIDIR 1 Counting down This event is triggered only during down counting when BIDIR 1 Reserved 10 6 24 SCT output set registers 0 to 3 Each output n has one set register that controls how events affect each output Whether outputs are set or cleared depends on the setting of the SETCLRn field in the SCT OUTPUTDIRCTRL register Table 131 SCT output set register OUT 0 3 SET address 0x5000 4500 OUTO SET to 0x5000 4518
167. DAT register provides the means to read the most recently received data for the Slave function and to transmit data using the Slave function Table 183 Slave Data register SLVDAT address 0x4005 0044 bit description Bit Symbol Description Reset Value 7 0 DATA Slave function data register 0 Read read the most recently received data for the Slave function Write transmit data using the Slave function 31 8 Reserved Read value is undefined only zero should be written NA All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 204 of 326 NXP Semiconductors U M1 0601 Chapter 16 LPC800 I2C bus interface 16 6 13 Slave Address registers The SLVADR O0 3 registers allow enabling and defining of the addresses that can be automatically recognized by the I2C slave hardware The value in the SLVADRO register is qualified by the setting of the SLVQUALO register When the slave address is compared to the receive address the compare can be affected by the setting of the SLVQUALO register see Section 16 6 14 The I C slave function has 4 address comparators The additional 3 address comparators do not include the address qualifier feature For handling of the general call address one of the 4 address registers can be programmed to respond to address 0 Table 184 Slave Address registers SLVADR 0 3
168. DST Starting flash or RAM address of data bytes to be compared This address should be a word boundary Param1 SRC Starting flash or RAM address of data bytes to be compared This address should be a word boundary Param2 Number of bytes to be compared should be a multiple of 4 CMD_SUCCESS COMPARE_ERROR COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED Result0 Offset of the first mismatch if the Status Code is COMPARE ERROR This command is used to compare the memory contents at two locations All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 264 of 326 NXP Semiconductors UM10601 Chapter 21 LPC800 Flash ISP and IAP programming 21 5 2 8 Reinvoke ISP IAP Table 244 IAP Reinvoke ISP Command Input Return Code Result Description Compare Command code 57 decimal None None This command is used to invoke the bootloader in ISP mode It maps boot vectors sets PCLK CCLK and configures USARTO pins UO RXD and UO TXD This command may be used when a valid user program is present in the internal flash memory and the PIOO 1 pin is not accessible to force the ISP mode 21 5 2 9 ReadUID IAP Table 245 IAP ReadUID command Command Compare Input Command code 58 decimal Return Code CMD SUCCESS Result Result0 The first 32
169. Deselect interrupt Enable The SlvDeSel interrupt is disabled The SlvDeSel interrupt is enabled Monitor data Ready interrupt Enable The MonRay interrupt is disabled The MonRay interrupt is enabled Monitor Overrun interrupt Enable The MonOv interrupt is disabled The MonOv interrupt is enabled Reserved Read value is undefined only zero should be written Reset value 0 NA NA NA NA NA NA NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 197 of 326 NXP Semiconductors UM10601 16 6 4 UM10601 Chapter 16 LPC800 I2C bus interface Table 174 Interrupt Enable Set and read register INTENSET address 0x4005 0008 bit description Bit Symbol Value Description Reset value 19 MONIDLEEN Monitor Idle interrupt Enable 0 0 The Monldle interrupt is disabled 1 The Monldle interrupt is enabled 23 20 Reserved Read value is undefined only zero NA should be written 24 EVENTTIMEOUTEN Event time out interrupt Enable 0 0 The Event time out interrupt is disabled 1 The Event time out interrupt is enabled 25 SCLTIMEOUTEN SCL time out interrupt Enable 0 0 The SCL time out interrupt is disabled 1 The SCL time out interrupt is enabled 31 26 Reserved Read value is undefined only zero NA should be written Interrupt Enable Clear register Writing a 1 to a bit position in INTENCLR clears the corresponding position in the INTENSET regi
170. ENABLEO Section 9 5 10 32 stage Voltage Ladder 13 5 General description UM10601 The analog comparator can compare voltage levels on external pins and internal voltages The comparator has 8 inputs multiplexed separately to its positive and negative inputs The multiplexers are controlled by the comparator register CTL see Figure 26 and Table 151 Input 0 of the multiplexer is the programmable voltage ladder output Bits 2 1 control the external inputs ACMP_1 2 1 Bits 6 of the multiplexer controls internal reference voltage input All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 160 of 326 NXP Semiconductors U M1 0601 Chapter 13 LPC800 Analog comparator ext VDDCMP LADREF AT y LADEN amp nACOMP PD VOLTAGE LADDER OUT COMP VP SEL ACMP 11 COMPSTAT ACMP 12 VSS VSS VSS internal 0 9V BANDGAP VSS n c to ACMP_O COMPSA COMP VM SEL EDGESEL COMPEDGE RST N to INTERRUPT 20F3 SAMPLING EDGECLR or e CONTROL STATUS REGISTER BITS EDGE DETECT ACOMP_RST_N Fig 26 Comparator block diagram 13 5 1 Reference voltages The voltage ladder can use two reference voltages from the VDDCMP or the Vpp pin The voltage ladder selects one of 32 steps between the pin voltage and Vss inclusive The voltage on VDDCMP should not exceed
171. ERn This bit is read only 0 0 Idle state TIMERn is stopped 1 Running TIMERn is running 31 2 Reserved 0 11 6 5 Idle channel register The idle channel register returns the lowest idle channel number The channel is considered idle when both flags is the STATUS register RUN and INTFLAG are zero In an application with multiple timers running independently you can calculate the register offset of the next idle timer by reading the idle channel number in this register The idle channel register allows you set up the next idle timer without checking the idle state of each timer Table 139 Idle channel register IDLE CH address 0x4000 40F4 bit description Bit Symbol Description Reset value 3 0 Reserved 0 74 CHAN Idle channel Reading the CHAN bits returns the lowest idle timer 0 channel If all timer channels are running CHAN 4 31 8 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 148 of 326 NXP Semiconductors U M1 0601 Chapter 11 LPC800 Multi Rate Timer MRT 11 6 6 Global interrupt flag register The global interrupt register combines the interrupt flags from the individual timer channels in one register Setting and clearing each flag behaves in the same way as setting and clearing the INTFLAG bit in each of the STATUSn registers Table 140 Global interrup
172. FFO gt Flash IAP Ptr to ROM Driver table Ox1FFF 1FF8 ROM Driver Table 0x0 Ptr to Device Table 0 0 4 Reserved Ptr to Device Table 1 0x8 Reserved Ptr to Device Table 2 0xC Reserved Ptr to Device power profile Device 3 0x10 function table Power profiles API function table Ptr to Device Table 4 0 14 Reserved Device 5 2C driver routines function table Ptr to I2C driver routine function table Ptr to Device Table Device n Ptr to Function 0 Ptr to Function 1 Ptr to Function 2 Ptr to Function n Fig 40 Boot ROM structure All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 243 of 326 NXP Semiconductors UM10601 UM10601 Table 212 API calls Chapter 20 LPC800 Boot ROM API Flash IAP Power profiles API 12C driver UART driver Description Reference Flash In Application programming Table 236 Configure system clock and power 249 consumption 12C ROM Driver UART get memory size Table 252 Table 273 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 244 of 326 NXP Semiconductors U M1 0601 Chapter 20 LPC800 Boot ROM 20 6 Functional description 2
173. IO pattern match function to a pin on the LPC800 package Table 78 Pin interrupt pattern match engine pin description Function Direction Pin Description SWM register Reference GPIO INT BMAT any GPIO pattern match PINASSIGN8 Table 104 output 8 5 General description Pins with configurable functions can serve as external interrupts or inputs to the pattern match engine You can configure up to eight pins total using the PINTSEL registers in the SYSCON block for these features UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 81 of 326 NXP Semiconductors U M1 0601 Chapter 8 LPC800 Pin interrupts pattern match engine 8 5 1 Pin interrupts From all available GPIO pins up to eight pins can be selected in the system control block to serve as external interrupt pins see Table 32 The external interrupt pins are connected to eight individual interrupts in the NVIC and are created based on rising or falling edges or on the input level on the pin SYSCON all pins PIOO m EDGE LEVEL A DETECT LOGIC NVIC pin interrupt 0 all pins m EDGE LEVEL NVIC pin interrupt 7 DETECT LOGIC PINTSEL7 n 6 for the DIP8 package n 14 for the TSSOP16 package n 18 for the TSSOP SOP20 packages Fig6 Pin interrupt connections 8 5 2 Pattern match engine The pattern
174. IO port direction registers 76 77 4 Recommended 79 7 6 4 GPIO port mask registers 76 Chapter 8 LPC800 Pin interrupts pattern match engine 8 1 How to read this chapter 80 8 5 2 Pattern match 82 8 2 80 8 5 2 1 85 8 3 Basic configuration 80 8 6 Register description 86 8 3 1 Configure pins as pin interrupts or as inputs tothe 8 6 1 Pin interrupt mode register 87 pattern match engine 81 8 6 2 Pin interrupt level or rising edge interrupt enable 84 81 register tette DEL 87 E 8 6 3 Pin interrupt level or rising edge interrupt set 8 5 General description 81 register 87 8 5 1 Pin 82 0 eee UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 320 of 326 NXP Semiconductors UM10601 Chapter 28 Supplementary information 8 6 4 Pin interrupt level or rising edge interrupt clear 8 6 11 Pattern Match Interrupt Control Register 91 register is EE 88 8 6 12 Pattern Match Interrupt Bit Slice Source 8 6
175. IOO 17 0x11 15 8 CTOUT 2 O CTOUT 2 function assignment The value is the pin number to OXFF be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 23 16 CTOUT CTOUT 3 function assignment The value is the pin number to OXFF be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 31 24 126 SDA IO I2C SDA function assignment The value is the pin number to OxFF be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 112 of 326 NXP Semiconductors UM10601 Chapter 9 LPC800 Switch matrix 9 5 9 Pin assign register 8 Table 104 Pin assign register 8 PINASSIGN8 address 0x4000 C020 bit description Bit Symbol Description Reset value 7 0 12 _ SCL IO 12C_SCL function assignment The value is the pin OxFF number to be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 2 Ox11 15 8 ACMP function assignment The value is the pin OxFF number to be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 2 Ox11 23 16 CLKOUT O CLKOUT function assignment The value is the pin OxFF number to be assigned to this function The following p
176. January 2013 43 of 326 NXP Semiconductors U M1 0601 5 6 1 5 6 2 Chapter 5 LPC800 Reduced power modes and Power Management Power control register The power control register selects whether one of the ARM Cortex MO controlled power down modes Sleep mode or Deep sleep Power down mode or the Deep power down mode is entered and provides the flags for Sleep or Deep sleep Power down modes and Deep power down modes respectively Table 43 Power control register PCON address 0x4002 0000 bit description Bit Symbol Value Description Reset value 2 0 PM Power mode 000 0x0 Default The part is in active or sleep mode 0 1 ARM WFI will enter Deep sleep mode 0x2 ARM WFI will enter Power down mode 0x3 ARM WFI will enter Deep power down mode ARM Cortex MO core powered down 3 NODPD 1 in this bit prevents entry to Deep power down mode 0 when 0x3 is written to the PM field above the SLEEPDEEP bit is set and a WFI is executed This bit is cleared only by power on reset so writing a one to this bit locks the part in a mode in which Deep power down mode is blocked Reserved Do not write ones to this bit SLEEPFLAG Sleep mode flag 0 Read No power down mode entered Part is in Active mode Write No effect 1 Read Sleep Deep sleep or Deep power down mode entered Write Writing a 1 clears the SLEEPFLAG bit to 0 10 9 Reserved Do not write ones to this bit 11 DPDFLAG Deep power down flag 0 Read De
177. KDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 68 of 326 NXP Semiconductors UM10601 6 5 14 PIOO 8 register Chapter 6 LPC800 I O configuration IOCON Table 62 8 register PIOO 8 address 0x4004 4038 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select
178. L 1 3 UM10601 11 5 1 Repeat interrupt mode The repeat interrupt mode generates repeated interrupts after a selected time interval This mode can be used for software based PWM or PPM applications When the timer n is in idle state writing a non zero value IVALUE to the INTVALn register immediately loads the time interval value IVALUE 1 and the timer begins to count down from this value When the timer reaches zero an interrupt is generated the value in the INTVALn register IVALUE 1 is reloaded automatically and the timer starts to count down again While the timer is running in repeat interrupt mode you can perform the following actions Change the interval value on the next timer cycle by writing a new value gt 0 to the INTVALn register and setting the LOAD bit to 0 An interrupt is generated when the timer reaches zero On the next cycle the timer counts down from the new value Change the interval value on the fly immediately by writing a new value gt 0 to the INTVALn register and setting the LOAD bit to 1 The timer immediately starts to count down from the new timer interval value An interrupt is generated when the timer reaches 0 Stop the timer at the end of time interval by writing a 0 to the INTVALn register and setting the LOAD bit to 0 An interrupt is generated when the timer reaches zero Stop the timer immediately by writing a 0 to the INTVALn register and setting the LOAD bit to 1 No interrupt is
179. NSET 0 register 15 RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET 0 register 31 16 Reserved Read value is undefined only zero should be NA written USART Receiver Data register The RXDATA register contains the last character received before any overrun Remark Reading this register changes the status flags in the RXDATASTAT register Table 163 USART Receiver Data register RXDATA address 0x4006 4014 USARTO 0x4006 8014 USART1 0x4006 C014 USART2 bit description Bit Symbol Description Reset Value 8 0 RXDAT The USART Receiver Data register contains the next received 0 character The number of bits that are relevant depends on the USART configuration settings 31 9 Reserved the value read from a reserved bit is not defined NA USART Receiver Data with Status register The RXDATASTAT register contains the next complete character to be read and its relevant status flags This allows getting all information related to a received character with one 16 bit read Remark Reading this register changes the status flags Table 164 USART Receiver Data with Status register RXDATASTAT address 0x4006 4018 USARTO 0 4006 8018 USART1 0x4006 C018 USART2 bit description Bit Symbol Description Reset Value 8 0 RXDAT The USART Receiver Data register contains the next received 0 character The number of bits that are relevant depends on the USART configuration settings 12 9 Res
180. O20 package pin 10 A pin is identified for the purpose of programming the switch matrix by its default GPIO port pin Fig 12 Example Connect function UO RXD UO TXD to pins 10 and 14 on the SO20 package The switch matrix connects all internal signals listed in the table of movable functions through the pin assignment registers to external pins on the package External pins are identified by their default GPIO pin number PIOO n Follow these steps to connect an internal signal FUNC to an external pin An example of a movable function is the UART transmit signal TXD 1 Find the function FUNC in the list of movable functions in Table 94 or in the data sheet 2 Use the LPC800 data sheet to decide which pin x on the LPC800 package to connect FUNC to 3 Use the pin description table to find the default GPIO function PIOO n assigned to package pin x m is the pin number 4 Locate the pin assignment register for the function FUNC in the switch matrix register description 5 Disable any special functions on pin PIOO n in the PINENABLEO register 6 Program the pin number n into the bits assigned to FUNC FUNC is now connected to pin x on the package 9 3 2 Enable an analog input or other special function The switch matrix enables functions that can only be assigned to one pin Examples are analog inputs all GPIO pins and the debug SWD pins UM10601 All information provided in this document is subject to legal disc
181. OCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 lt Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 67 of 326 NXP Semiconductors UM10601 6 5 13 PIOO 9 register Chapter 6 LPC800 I O configuration IOCON Table 61 PIOO_9 register PIOO 9 address 0 4004 4034 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCL
182. ONFIG uint32 t sys clk in hz Sytem clock in hz uint32 t baudrate in hz Baudrate in hz uint8 t config bit 1 0 I 00 7 bits length 01 8 bits lenght others reserved I bit3 2 I 00 No Parity 01 reserved 10 Even 11 Odd IIbit4 I 0 1 Stop bit 1 2 Stop bits uint8 t sync mod bit0 0 Async mode 1 mode 11611 Un is sampled on the falling edge of SCLK Il 1 Un_RXD is sampled on the rising edge of SCLK 116102 O Start and stop bits are transmitted as in asynchronous mode 1 I Start and stop bits are not transmitted 116103 the UART is a slave on Sync mode 1 1 the UART is a master on Sync mode uint16 t error en Bit0 OverrunEn bitl UnderrunEn bit2 FrameErrEn bit3 ParityErrEn bit4 RxNoiseEn Le UART HANDLE T The handle to the instance of the UART driver Each UART has one handle so there can be several handles for up to three UART blocks This handle is created by Init API and used by the transfer functions for the corresponding UART block typedef void UART HANDLE T define TYPE for uart handle pointer UART PARAM T typedef struct uart_A parms passed to uart driver function uint8 t buffer The pointer of buffer For uart get line function buffer for receiving data For uart put line function buffer for transmitting data uint32_t size IN The size of buffer The number of bytes transmitted received uintl6 t transfer mod
183. OO 2 Serial wire debug data input output The SWDIO 105 TMS pin is used by an external debug tool to communicate with and control the LPC800 This pin is pulled up internally UM10601 The boundary scan mode and the pins needed are selected by hardware see Section 25 5 3 There is no access to the boundary scan pins through the switch matrix All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 299 of 326 NXP Semiconductors UM10601 Chapter 25 LPC800 Debugging Table 284 JTAG boundary scan pin description Function Pin name Type TCK SWCLK PIOO_3 TCK TMS SWDIO PIOO_2 TMS TDI PIOO_1 ACMP_12 CLKIN TDI TDO PIOO H TDO TRST PIOO 4 WAKEUP TRST Description JTAG Test Clock This pin is the clock for JTAG boundary scan when the RESET pin is LOW JTAG Test Mode Select The TMS pin selects the next state in the TAP state machine This pin includes an internal pull up and is used for JTAG boundary scan when the RESET pin is LOW JTAG Test Data In This is the serial data input for the shift register This pin includes an internal pull up and is used for JTAG boundary scan when the RESET pin is LOW JTAG Test Data Output This is the serial data output from the shift register Data is shifted out of the device on the negative edge
184. OR Source and destination data not equal 11 BUSY Flash programming hardware interface is busy 12 PARAM ERROR Insufficient number of parameters or invalid parameter 13 ADDR ERROR Address is not on word boundary UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 258 of 326 NXP Semiconductors U M1 0601 21 5 2 UM10601 Chapter 21 LPC800 Flash ISP and IAP programming Table 235 UART ISP Return Codes Summary Return Mnemonic Description Code 14 ADDR_NOT_MAPPED Address is not mapped in the memory map Count value is taken in to consideration where applicable 15 CMD_LOCKED Command is locked 16 INVALID CODE Unlock code is invalid 17 INVALID BAUD RATE Invalid baud rate setting 18 INVALID STOP BIT Invalid stop bit setting 19 CODE READ PROTECTION Code read protection enabled ENABLED IAP commands For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory RAM containing command code and parameters Result of the IAP command is returned in the result table pointed to by register r1 The user can reuse the command table for result by passing the same pointer in registers rO and r1 The parameter table should be big enough to hold all the results in case the number of results are more than number of parameters Parameter passing i
185. OUT3 SET bit description Bit 5 0 31 6 Symbol Description Reset value SET A 1 in bit m selects event m to set output n or clear it if SETCLRn 0 0x1 or 0x2 event 0 bit 0 event 1 bit 1 event 5 bit 5 Reserved 10 6 25 SCT output clear registers 0 to Each output n has one clear register that controls how events affect each output Whether outputs are set or cleared depends on the setting of the SETCLRn field in the OUTPUTDIRCTRL register Table 132 SCT output clear register OUT 0 3 CLR address 0x5000 0504 OUTO CLR to 0x5000 051C OUT3 CLR bit description Bit Symbol Description Reset value 5 0 CLR A 1 in bit m selects event m to clear output or set itif SETCLRn 0 0x1 or 0x2 event 0 bit 0 event 1 bit 1 event 5 bit 5 31 6 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 135 of 326 NXP Semiconductors UM10601 10 7 Functional description Chapter 10 LPC800 State Configurable Timer SCT 10 7 1 Match logic Counter H Match Reload Match Match i H Regi H iH UNIFY Match Reload Match I Match iL i L RegiL Counter L Fig 16 Match logic 10 7 2 Capture logic Counter H capture capture control select regi H iH Events UNIFY SCT clock e capture select regiL Counter
186. PBYTE Read state of the pin PIOO n regardless of direction ext R W masking or alternate function except that pins configured as analog I O always read as 0 Write loads the pin s output bit 7 1 Reserved 0 on read ignored on write 0 7 6 2 GPIO port word pin registers UM10601 Each GPIO pin has a word register in this address range Any byte halfword or word read in this range will be all zeros if the pin is low or all ones if the pin is high regardless of direction masking or alternate function except that pins configured as analog I O always read as zeros Any write will clear the pin s output bit if the value written is all zeros else it will set the pin s output bit All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 75 of 326 NXP Semiconductors U M1 0601 7 6 3 7 6 4 7 6 5 UM10601 Chapter 7 LPC800 GPIO port Table 70 GPIO port 0 word pin registers W 0 17 addresses 0xA000 1000 WO to 0x5000 1048 W17 bit description Bit Symbol Description Reset Access value 31 0 PWORD Read 0 pin is LOW ext R W Write 0 clear output bit Read OxFFFF FFFF pin is HIGH Write any value 0x0000 0001 to OxFFFF FFFF set output bit Remark Only 0 or OxFFFF FFFF can be read Writing any value other than 0 will set the output bit GPIO port direction registers Each GPIO po
187. PIOO 16 register Chapter 6 LPC800 I O configuration IOCON Table 58 16 register PIOO 16 address 0 4004 4024 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 lt Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminar
188. PLL CLKIN sys_pllclkin SYSPLLCLKSEL Fig 44 LPC800 clock configuration for power API use 22 4 API description The power profile provides functions to configure the system clock and optimize the System setting for lowest power consumption UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 269 of 326 NXP Semiconductors U M1 0601 22 4 1 UM10601 Chapter 22 LPC800 Power profile ROM driver Table 249 Power profile API calls API call Description Reference set_pll command result Power API set pll routine Table 250 set power command result Power set power routine Table 251 The following elements have to be defined in an application that uses the power profiles typedef struct PWRD void set pll unsigned int cmd unsigned int resp void set power unsigned int cmd unsigned int resp PWRD typedef struct ROM const PWRD pWRD ROM ROM rom ROM Ox IFFFIFF8 3 sizeof ROM unsigned int command 4 result 2 set This routine sets up the system PLL according to the calling arguments If the expected clock can be obtained by simply dividing the system PLL input set p l bypasses the PLL to lower system power consumption Remark Before this routine is invoked the PLL clock source IRC system oscillator mus
189. RC registers are written to 0 4 High level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0x5 Low level Match occurs when there is a low level on the specified input 0x6 Constant 0 This bit slice never contributes to a match should be used to disable any unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs on an event i e when either a UM10601 rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 95 of 326 NXP Semiconductors U M1 0601 Chapter 8 LPC800 Pin interrupts pattern match engine Table 92 Pattern match bit slice configuration register PMCFG address 0xA000 4030 bit description continued Bit Symbol Value Description Reset value 16 14 CFG2 Specifies the match contribution condition for bit slice 2 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x2 Sticky falling edg
190. RE Ain ee 158 Fig 24 Correct watchdog feed with windowed mode enabled sv waar ite vr her Sede 158 Fig 25 Watchdog warning interrupt 158 Fig 26 Comparator block diagram 161 Fig 27 USART clocking 170 Fig 28 USART block 173 Fig 29 Hardware flow control using RTS and CTS 186 Fig 30 l2C 187 Fig 31 12 block diagram 189 Fig 32 SPI 210 Fig 33 SPI block diagram 213 Fig 34 Basic SPI operating modes 225 Fig 35 Pre delay and Post_delay 226 Fig 36 227 Fig 37 Transfer 228 Fig 38 Examples of data stalls 231 Fig 39 CRC block diagram 233 Fig 40 Boot ROM 243 Fig 41 Boot process flowchart 246 Fig 42 IAP parameter passing 261 Fig 43 Power profiles pointer structure 269 Fig 44 LPC800 clock configuration for power API use 269 Fig 45 Power profiles 273 Fig 46 2C bus driver routines pointer structure 278 Fig 47 12C slave mode set up address packing 288 Fig 48 USART driver routines pointer structure
191. RROR ADDR_NOT_MAPPED CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED This command is used to execute a program residing in RAM or flash memory It may not be possible to return to the ISP command handler once this command is successfully executed This command is blocked when code read protection is enabled The command must be used with an address of 0x0000 0200 or greater 512 T CR LF branches to address 0x0000 0200 in Thumb mode Erase sector s start sector number end sector number Table 227 UART ISP Erase sector command Command Input Return Code Description Example E Start Sector Number End Sector Number Should be greater than or equal to start sector number CMD SUCCESS BUSY INVALID SECTOR SECTOR NOT PREPARED FOR WRITE OPERATION CMD LOCKED PARAM ERROR CODE READ PROTECTION ENABLED This command is used to erase one or more sector s of on chip flash memory The boot block can not be erased using this command This command only allows erasure of all user sectors when the code read protection is enabled E 2 S CR LF erases the flash sectors 2 and 3 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 255 of 326 NXP Semiconductors U M1 0601 21 5 1 10 21 5 1 11 21 5 1 12 UM10601 Chapter 21 LPC800 Flash ISP
192. Rev 1 1 24 January 2013 130 of 326 NXP Semiconductors U M1 0601 10 6 17 10 6 18 UM10601 Chapter 10 LPC800 State Configurable Timer SCT Table 123 SCT conflict enable register CONEN address 0x5000 40F8 bit description Bit Symbol Description Reset value 3 0 The SCT requests interrupt when bit n of this register andthe SCT 0 conflict flag register are both one output 0 bit 0 output 1 bit 1 output 3 bit 3 31 4 Reserved SCT conflict flag register This register records interrupt enabled no change conflict events and provides details of a bus error Writing ones to the NCFLAG bits clears the corresponding read bits and negates the SCT interrupt request if all enabled Flag bits are zero Table 124 SCT conflict flag register CONFLAG address 0x5000 40FC bit description Bit Symbol Description Reset value 3 0 NCFLAG Bit n is one if a no change conflict event occurred on outputn 0 since reset or a 1 was last written to this bit output O bit 0 output 1 bit 1 output 3 bit 29 4 Reserved 30 BUSERRL most recent bus error from this SCT involved writing CTR 0 L Unified STATE L Unified MATCH L Unified or the Output register when the L U counter was not halted A word write to certain L and H registers can be half successful and half unsuccessful 31 BUSERRH most recent bus error from this SCT involved writing CTR 0 H STATE H MATCH H or the
193. SCON inputs and outputs are assigned to external pins through the switch matrix See Section 9 3 1 Connect an internal signal to a package pin to assign the CLKOUT function to a pin on the LPC800 package See Section 9 3 2 to enable the clock input the oscillator pins and the external reset input Table 4 SYSCON pin description Function Direction Pin Description SWM register Reference CLKOUT O any CLKOUT clock output PINASSIGN8 Table 104 CLKIN PIOO 1 ACMP I2 CLKIN External clock input to the system PINENABLEO Table 105 PLL Disable the ACMP 12 function in the PINENABLE register XTALIN PIOO 8 XTALIN Input to the system oscillator PINENABLEO Table 105 XTALOUT O PIOO_9 XTALOUT Output from the system oscillator PINENABLEO Table 105 RESET RESET PIOO 5 External reset input PINENABLEO Table 105 4 5 General description 4 5 1 Clock generation The system control block generates all clocks for the chip Only the low power oscillator used for wake up timing is controlled by the PMU Except for the USART clock and the clock to configure the glitch filters of the digital I O pins the clocks to the core and peripherals run at the same frequency The maximum system clock frequency is 30 MHz See Figure 3 Remark The main clock frequency is limited to 100 MHz UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1
194. SEED 0x0000 FFFF 18 7 2 CRC 16 set up Polynomial x16 x15 2 1 UM10601 Seed Value 0x0000 Bit order reverse for data input YES 1 s complement for data input NO Bit order reverse for CRC sum YES 1 s complement for CRC sum NO CRC_MODE 0x0000 0015 CRC_SEED 0x0000 0000 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 235 of 326 NXP Semiconductors U M1 0601 Chapter 18 LPC800 Cyclic Redundancy Check CRC engine 18 7 3 CRC 32 set up Polynomial x924 x26 x 3 x22 x16 x12 xTT a X104 x9 4 x7 4x9 4 x41 x Xx 1 Seed Value OxFFFF FFFF Bit order reverse for data input YES 1 s complement for data input NO Bit order reverse for CRC sum YES 1 s complement for CRC sum YES CRC_MODE 0x0000 0036 CRC_SEED OxFFFF FFFF UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 236 of 326 UM10601 Chapter 19 LPC800 Flash controller Rev 1 1 24 January 2013 Preliminary user manual 19 1 How to read this chapter The flash controller is identical on all LPC800 parts 19 2 Features Controls flash access time Provides registers for flash signature generation 19 3 General description The flash controller is accessible for
195. Semiconductors UM10601 UM10601 Chapter 4 LPC800 System config uration SYSCON Table 18 System clock control register SYSAHBCLKCTRL address 0x4004 8080 bit description continued Bit 10 11 12 13 14 15 16 17 18 Symbol Value GPIO 0 SWM 0 1 SCT 0 WKT 0 1 MRT 0 SPIO 0 1 SPI1 0 CRC 0 UARTO 0 1 UART1 0 UART2 0 1 WWDT 0 IOCON 0 1 All information provided in this Description Reset value Enables clock for GPIO port registers and GPIO 0 interrupt registers Disable Enable Enables clock for switch matrix Disable Enable Enables clock for state configurable timer Disable Enable Enables clock for self wake up timer Disable Enable Enables clock for multi rate timer Disable Enable Enables clock for SPIO Disable Enable Enables clock for SPI Disable Enable Enables clock for CRC Disable Enable Enables clock for USARTO Disable Enable Enables clock for USART1 Disable Enable Enables clock for USART2 Disable Enable Enables clock for WWDT Disable Enable Enables clock for IOCON block Disable Enable ument is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 26 of 326 NXP Semiconductors U M1 0601 Chapter 4 LPC800 System configuration SYSCON Table 18 System clock control regist
196. Table 26 POR captured PIO status register 0 Table 3 Connection of interrupt sources to the NVIC 10 PIOPORCAPO address 0x4004 8100 bit Table 4 SYSCON pin description 15 lt 30 Table 5 Register overview System configuration base Table 27 IOCON glitch filter clock divider registers 6 to 0 address 0 4004 8000 17 IOCONCLKDIV 6 0 address 0x4004 8134 Table 6 System memory remap register IOCONCLKDIV6 to 0x004 814C SYSMEMREMAP address 0x4004 8000 bit IOCONFILTCLKDIVO bit description 30 COSCHIPUON dee dE RUE 19 Table 28 BOD control register BODCTRL address 0x4004 Table 7 Peripheral reset control register PRESETCTRL 8150 bit description 31 address 0x4004 8004 bit description 19 Table 29 System tick timer calibration register Table 8 System PLL control register SYSPLLCTRL SYSTCKCAL address 0x4004 8154 bit address 0x4004 8008 bit description 21 lt 31 Table 9 System PLL status register SYSPLLSTAT Table 30 IRQ latency register IRQLATENCY address address 0x4004 800C bit description 21 0x4004 8170 bit description 32 Table 10 System oscillator control register SYSOSCCTRL Table 31 NMI source selection register NMISRC address address 0x4004 8020 bit description 21 0x4004 8174 bit descrip
197. Toggle output bit 31 18 Reserved 0 description 7 7 1 7 7 2 UM10601 Reading pin state Software can read the state of all GPIO pins except those selected for an analog function in the switch matrix logic A pin does not have to be selected for GPIO in the switch matrix in order to read its state There are several ways to read the pin state The state of a single pin can be read with 7 high order zeros from a Byte Pin register The state of a single pin can be read in all bits of a byte halfword or word from a Word Pin register The state of multiple pins in a port can be read as a byte halfword or word from a PORT register The state of a selected subset of the pins in a port can be read from a Masked Port MPORT register Pins having a 1 in the port s Mask register will read as 0 from its MPORT register GPIO output Each GPIO pin has an output bit in the GPIO block These output bits are the targets of write operations to the pins Two conditions must be met in order for a pin s output bit to be driven onto the pin 1 The pin must be selected for GPIO operation in the switch matrix 2 The pin must be selected for output by a 1 in its port s DIR register If either or both of these conditions is are not met writing to the pin has no effect There are multiple ways to change GPIO output bits All information provided in this document is subject to legal disclaimers NXP B V 2013
198. V SYSAHBCLKCTRL 5 I2C clock enable All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 187 of 326 NXP Semiconductors U M1 0601 Chapter 16 LPC800 I2C bus interface 16 3 1 Configure the I2C for wake up In sleep mode any activity on the I2C bus that triggers an I2C interrupt can wake up the part provided that the interrupt is enabled in the INTENSET register and the NVIC As long as the I2C clock I2C PCLK remains active in sleep mode the I2C can wake up the part independently of whether the 12C block is configured in master or slave mode In Deep sleep or Power down mode the I2C clock is turned off as all peripheral clocks However if the 12C is configured in slave mode and an external master on the I2C bus provides the clock signal the I2C block can create an interrupt asynchronously This interrupt if enabled in the NVIC the STARTERP1 register and in the I2C block s INTENCLR register can then wake up the core 16 3 1 1 Wake up from Sleep mode Enable the 12C interrupt in the NVIC Enable the I2C wake up event in the I2C INTENSET register Wake up on any enabled interrupts is supported see the INTENSET register Examples are the following events Master pending Change to idle state Start stop error Slave pending Address match in slave mode Data
199. XP Semiconductors U M1 0601 Chapter 1 LPC800 Introductory information State Configurable Timer SCT with input and output functions including capture and match assigned to pins through the switch matrix Multiple channel multi rate timer MRT for repetitive interrupt generation at up to four programmable fixed rates Self Wake up Timer WKT clocked from either the IRC or a low power low frequency internal oscillator CRC engine Windowed Watchdog timer WWDT Analog peripherals Comparator with external voltage reference with pin functions assigned or enabled through the switch matrix Serial interfaces Three USART interfaces with pin functions assigned through the switch matrix Two SPI controllers with pin functions assigned through the switch matrix One I C bus interface with pin functions assigned through the switch matrix Clock generation 12 MHz internal RC oscillator trimmed to 1 96 accuracy that can optionally be used as a system clock Crystal oscillator with an operating range of 1 MHz to 25 MHz Programmable watchdog oscillator with a frequency range of 9 4 kHz to 2 3 MHz 10 kHz low power oscillator for the WKT PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from the system oscillator the external clock input CLKIN or the internal RC oscillator Clock output function wit
200. Y CLKMODE CKSEL NORELAOD_L NORELOAD_H Value 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description Reset value SCT operation 0 16 bit The SCT operates as two 16 bit counters named L and H 32 bit The SCT operates as a unified 32 bit counter SCT clock mode 0 Bus clock The bus clock clocks the SCT and prescalers Prescaled bus clock The SCT clock is the bus clock but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge The minimum pulse width on the clock input is 1 bus clock period This mode is the high performance sampled clock mode Input The input selected by CKSEL clocks the SCT and prescalers The input is synchronized to the bus clock and possibly inverted The minimum pulse width on the clock input is 1 bus clock period This mode is the low power sampled clock mode Reserved SCT clock select All other values are reserved 0 Input 0 rising edges Input O falling edges Input 1 rising edges Input 1 falling edges Input 2 rising edges Input 2 falling edges Input 3 rising edges Input 3 falling edges A 1 in this bit prevents the lower match registers from being reloaded from their 0 respective reload registers Software can write to set or clear this bit at any time This bit applies to both the higher and lower registers when the UNIFY bit is set A 1 inthis bit prevents the higher match registers
201. _SCLK y o Serial clock input output for USART1 in synchronous PINASSIGNS Table 99 mode SPIO SCK Serial clock for SPIO PINASSIGN3 Table 99 SPIO MOSI Master Out Slave In for SPIO PINASSIGN4 Table 100 SPIO_MISO Master In Slave Out for SPIO PINASSIGN4 Table 100 SPIO_SSEL Slave select for SPIO PINASSIGN4 Table 100 SPI1 SCK Serial clock for SP11 PINASSIGNA Table 100 SPI1 MOSI Master Out Slave In for SPI PINASSIGN5 Table 101 SPI1 MISO Master In Slave Out for SPI PINASSIGN5 Table 101 SPI1 SSEL Slave select for SPI PINASSIGN5 Table 101 CTIN 0 SCT input 0 PINASSIGN5 Table 101 CTIN 1 SCT input 1 PINASSIGN6 Table 102 CTIN_2 SCT input 2 PINASSIGN6 Table 102 CTIN_3 SCT input 3 PINASSIGN6 Table 102 CTOUT 0 SCT output 0 PINASSIGN6 Table 102 CTOUT_1 SCT output 1 PINASSIGN7 Table 103 CTOUT_2 SCT output 2 PINASSIGN7 Table 103 CTOUT 3 SCT output 3 PINASSIGN7 Table 103 1260 SDA I2C bus data input output open drain if assigned to pin PINASSIGN7 Table 103 PIOO 11 High current sink only if assigned to pin PIOO 11 and if 12 Fast mode Plus is selected in the I O configuration register UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 107 of 326 NXP Semiconductors U M1 0601 Chapter 9 LPC800 Switch matrix Table 94 Movable functions assign to pins PIOO 0 to PIOO 17 t
202. a location where both transmit data and control information can be written simultaneously This allows detailed control of the SPI without a separate write of control information for each piece of data When control information remains static during transmit the TXDAT register should be used see Section 17 6 8 instead of the TXDATCTL register Control information can then be written separately via the TXCTL register see Section 17 6 9 The upper part of TXDATCTL bits 27 to 16 are the same bits contained in the TXCTL register The two registers simply provide two ways to access them For details on the slave select process see Section 17 7 4 For details on using multiple consecutive frames for frame lengths larger than 16 bit see Section 17 7 5 Data lengths greater than 16 bits Table 195 SPI Transmitter Data and Control register TXDATCTL addresses 0x4005 8018 SPIO 0x4005 C018 SPI1 bit description Bit Symbol Value Description Reset value 15 0 TXDAT Transmit Data This field provides from 1 to 16 bits of data to be transmitted 0 16 TXSSELN 0 1 19 17 20 EOT 0 1 21 EOF 0 22 RXIGNORE 0 UM10601 Transmit Slave Select This field controls what is output for SSEL in master mode 0 Remark The active state of the SSEL function is configured by bits in the CFG register SSEL asserted SSEL not asserted Reserved End of Transfer The asserted SSEL will be deasserted at the end of a transfer
203. a register MONRXDAT address 0x4005 0080 bit description All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 190 of 326 NXP Semiconductors U M1 0601 Chapter 16 LPC800 I2C bus interface Table 169 Register overview I2C base address 0x4005 0000 Name Access Offset Description Reset Reference value CFG R W 0x00 Configuration for shared functions 0 Table 170 STAT R W 0x04 Status register for Master Slave and Monitor functions 0x00080 Table 171 1 INTENSET R W 0x08 Interrupt Enable Set and read register 0 Table 174 INTENCLR W 0x0C Interrupt Enable Clear register NA Table 175 TIMEOUT R W 0x10 Time out value register OxFFFF Table 176 DIV R W 0x14 Clock pre divider for the entire 12C block This determines what 0 Table 177 time increments are used for the MSTTIME and SLVTIME registers INTSTAT R 0x18 Interrupt Status register for Master Slave and Monitor 0 Table 178 functions MSTCTL R W 0x20 Master control register 0 Table 179 MSTTIME R W 0x24 Master timing configuration 0x77 Table 180 MSTDAT R W 0x28 Combined Master receiver and transmitter data register NA Table 181 SLVCTL R W 0x40 Slave control register 0 Table 182 SLVDAT R W 0x44 Combined Slave receiver and transmitter data register NA Table 183 SLVADRO R W 0x48 Slave address 0 0x01 Table 184 SLVADR1 R W 0x4C Slave address 1 0x01 Table 184
204. ace Table 180 Master Time register MSTTIME address 0x4005 0024 bit description continued Bit Symbol Value Description Reset value 6 4 MSTSCLHIGH Master SCL High time Specifies the minimum high time 0 that will be asserted by this master on SCL Other masters in a multi master system could shorten this time This corresponds to the parameter the 12C bus specification I C bus specification parameters tsu sro and tup srA have the same values and are also controlled by MSTSCLHIGH 0 0 2 clocks Minimum SCL high time is 2 clock of the 12 clock pre divider 0 1 clocks Minimum SCL high time is clocks of the IC clock pre divider 0 2 4clocks Minimum SCL high time is 4 clock of the IC clock pre divider 0 3 5 clocks Minimum SCL high time is 5 clock of the 12 clock pre divider 0 4 6 clocks Minimum SCL high time is 6 clock of the 2 clock pre divider 0 5 7 clocks Minimum SCL high time is 7 clock of the IC clock pre divider 0 6 8 clocks Minimum SCL high time is 8 clock of the 12C clock pre divider 0 7 9 clocks Minimum SCL high time is 9 clocks of the 12C clock pre divider 31 7 Reserved Read value is undefined only zero should be written Master Data register The MSTDAT register provides the means to read the most recently received data for the Master function and to transmit data using the Master function Table 181 Master Data register MSTDAT address 0
205. ad register MATCHRELOAD sets a reload value that is loaded into the match register when the counter reaches a limit condition or the value 0 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 139 of 326 NXP Semiconductors UM10601 Chapter 10 LPC800 State Configurable Timer SCT 10 7 9 3 Configure events and event responses 1 Define when each event can occur in the following way in the EVn CTRL registers up to 6 one register per event Select whether the event occurs on an input or output changing on an input or output level a match condition of the counter or a combination of match and input output conditions in field COMBMODE For a match condition Select the match register that contains the match condition for the event to occur Enter the number of the selected match register in field MATCHSEL If using L and H counters define whether the event occurs on matching the L or the H counter in field HEVENT For an SCT input or output level or transition Select the input number or the output number that is associated with this event in fields IOSEL and OUTSEL Define how the selected input or output triggers the event edge or level sensitive in field IOCOND 2 Define what the effect of each event is on the SCT outputs in the OUTn SET or OUTn CLR registers up to 4 outputs one register p
206. address 0x4005 0048 SLVADRO to 0x4005 0054 SLVADR3 bit description Bit Symbol Value Description Reset value 0 SADISABLE Slave Address n Disable 1 0 Enabled Slave Address n is enabled and will be recognized with any changes specified by the SLVQUALO register 1 Ignored Slave Address n is ignored 7 1 SLVADR Seven bit slave address that is compared to received 0 addresses if enabled 31 8 Reserved Read value is undefined only zero should be NA written 16 6 14 Slave address Qualifier 0 register The SLVQUALO register can alter how Slave Address 0 is interpreted UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 205 of 326 NXP Semiconductors U M1 0601 16 6 15 UM10601 Chapter 16 LPC800 I2C bus interface Table 185 Slave address Qualifier 0 register SLVQUALO address 0x4005 0058 bit description Bit Symbol Value Description Reset Value 0 QUALMODEO Reserved Read value is undefined only zero should be 0 written 0 The SLVQUALO field is used as a logical mask for matching address 0 1 The SLVQUALO field is used to extend address 0 matching in a range of addresses 7 1 SLVQUALO Slave address Qualifier for address 0 A value of 0 causes 0 the address in SLVADRO to be used as is assuming that it is enabled If QUALMODEO 0 any bit in this field which is set to 1 wil
207. affect the outputs and results in an bus error Software can read this register at any time to sense the state of the outputs Table 118 SCT output register OUTPUT address 0x5000 4050 bit description Bit Symbol Description Reset value 3 0 OUT Writing a 1 to bit n makes the corresponding output HIGH 0 makes 0 the corresponding output LOW output 0 bit 0 output 1 bit 1 output 3 bit 3 31 4 Reserved SCT bidirectional output control register This register specifies for each output the impact of the counting direction on the meaning of set and clear operations on the output see Section 10 6 24 and Section 10 6 25 Table 119 SCT bidirectional output control register OUTPUTDIRCTRL address 0x5000 4054 bit description Bit Symbol Value Description Reset value 1 0 SETCLRO Set clear operation on output 0 Value 0x3 is reserved Do not program this value 0 0x0 Any Set and clear do not depend on any counter 0x1 L counting down Set and clear are reversed when counter L or the unified counter is counting down 0x2 H counting down Set and clear are reversed when counter H is counting down Do not UM10601 use if UNIFY 1 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 128 of 326 NXP Semiconductors U M1 0601 Chapter 10 LPC800 State Configurable Timer SCT Table 119
208. ain The WKT can be used for waking up the part from any low power mode including Deep power down mode or for general purpose timing 14 3 Basic configuration In the SYSAHBCLKCTRL register set bit 9 Table 18 to enable the clock to the register interface Clear the WKT reset using the PRESETCTRL register Table 7 The WKT interrupt is connected to interrupt 15 in the NVIC Enable the low power oscillator in the PMU Table 45 Enable the IRC and IRC output in the PDRUNCFG register Table 37 See Section 5 7 1 to enable the various power down modes 14 4 Pin description The WKT has no configurable pins 14 5 General description 14 5 1 UM10601 The self wake up timer is a 32 bit loadable down counter Writing any non zero value to this timer automatically enables the counter and launches a count down sequence When the counter is being used as a wake up timer this write can occur just prior to entering a reduced power mode When a starting count value is loaded the self wake up timer automatically turns on counts from the pre loaded value down to zero generates an interrupt and or a wake up request and then turns itself off until re launched by a subsequent software write WKT clock sources The self wake up timer can be clocked from two alternative clock sources A 750 kHz clock derived from the IRC oscillator This is the default clock All information provided in this document is subject to legal
209. alue is the pin number to be OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 23 16 U1 RXD I U1 RXD function assignment The value is the pin number to OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 31 24 U1 RTS O U1 RTS function assignment The value is the pin number to be OXFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 Pin assign register 2 Table 98 Pin assign register 2 PINASSIGN2 address 0x4000 C008 bit description Bit Symbol Description Reset value 7 0 U1 CTS I U1 CTS function assignment The value is the pin number tobe OxXFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 15 8 U1 SCLK IO U1_SCLK function assignment The value is the pin number to OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 23 16 U2 TXD O U2 TXD function assignment The value is the pin number to be OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 31 24 U2 RXD I U2_RXD function assignment The value is the pin number to be OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved
210. alue of a state variable is completely under the control of the application If an application does not use states the value of the state variable remains zero which is the default value A state variable can be used to track and control multiple cycles of the associated counter in any desired operational sequence The state variable is logically associated with a state machine diagram which represents the SCT configuration See Section 10 6 22 and 10 6 23 for more about the relationship between states and events The STATELD STADEV fields in the event control registers of all defined events set all possible values for the state variable The change of the state variable during multiple counter cycles reflects how the associated state machine moves from one state to the next Table 115 SCT state register STATE address 0x5000 4044 bit description Bit Symbol Description Reset value 4 0 STATE L State variable 0 15 5 Reserved 20 16 STATE H State variable 0 31 21 Reserved All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 126 of 326 NXP Semiconductors U M1 0601 Chapter 10 LPC800 State Configurable Timer SCT 10 6 9 SCT input register Software can read the state of the SCT inputs in this read only register in two slightly different forms The only situation in which these values are dif
211. ame way as registers GPREGO to GPREG3 Remark If there is a possibility that the external voltage applied on pin Vpp drops below 2 2 V during Deep power down the hysteresis of the WAKEUP input pin has to be disabled in this register before entering Deep power down mode in order for the chip to wake up Remark Enabling the low power oscillator in Deep power down mode increases the power consumption Only enable this oscillator if you need the self wake up timer to wake up the part from Deep power down mode You may need the self wake up timer if the wake up pin is used for other purposes and the wake up function is not available Table 45 Deep power down control register DPDCTRL address 0x4002 0014 bit description Bit Symbol 0 WAKEUPHYS 1 WAKEPAD DISABLE 2 LPOSCEN 3 LPOSCDPDEN 31 4 Value Description Reset value WAKEUP pin hysteresis enable 0 0 Disabled Hysteresis for WAKEUP pin disabled 1 Enabled Hysteresis for WAKEUP pin enabled WAKEUP pin disable Setting this bit disables the wake up pin so it can be 0 used for other purposes Remark Never set this bit if you intend to use a pin to wake up the part from Deep power down mode You can only disable the wake up pin if the self wake up timer is enabled and configured Remark Setting this bit is not necessary if Deep power down mode is not used 0 Enabled The wake up function is enabled on pin PIOO 4 1 Disabled Setting this bit disables the wake up fun
212. ammed in this register is the denominator of the divider used by the fractional rate generator to create the fractional component of PCLK 2 The MULT value of the fractional divider is programmed in the UARTFRGMULT register See Table 24 Remark To use of the fractional baud rate generator you must write OxFF to this register to yield a denominator value of 256 All other values are not supported See also Section 15 3 1 Configure the USART clock and baud rate Section 15 7 1 Clocking and Baud rates All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 28 of 326 NXP Semiconductors U M1 0601 4 6 19 4 6 20 UM10601 Chapter 4 LPC800 System configuration SYSCON Table 23 USART fractional generator divider value register UARTFRGDIV address 0x4004 80F0 bit description Bit Symbol Description Reset value 7 0 DIV Denominator of the fractional divider DIV is equal to the programmed 0 value 1 Always set to OxFF to use with the fractional baud rate generator 31 8 Reserved USART fractional generator multiplier value register All USART peripherals share a common clock U_PCLK which can be adjusted by a fractional divider U PCLK UARTCLKDIV 1 MULT DIV UARTCLKDIV is the USART clock configured in the UARTCLKDIV register The fractional portion 1 MULT DIV is de
213. an be compared with an expected signature and thus makes saves time and code space The method for generating the signature is described in Section 19 5 1 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 238 of 326 NXP Semiconductors U M1 0601 Chapter 19 LPC800 Flash controller Table 210 FMSWO register bit description FMSWO address 0x4004 002C Bit Symbol Description Reset value 31 0 SIG 32 bit signature 19 5 Functional description 19 5 1 19 5 1 1 19 5 1 2 UM10601 Flash signature generation The flash module contains a built in signature generator This generator can produce a 32 bit signature from a range of flash memory A typical usage is to verify the flashed contents against a calculated signature e g during programming The address range for generating a signature must be aligned on flash word boundaries i e 32 bit boundaries Once started signature generation completes independently While signature generation is in progress the flash memory cannot be accessed for other purposes and an attempted read will cause a wait state to be asserted until signature generation is complete Code outside of the flash e g internal RAM can be executed during signature generation This can include interrupt services if the interrupt vector table is re mapped to memory other than t
214. andled normally Reserved Read value is undefined only zero should be NA written Transmit Disable 0 Not disabled USART transmitter is not disabled Disabled USART transmitter is disabled after any character currently being transmitted is complete This feature can be used to facilitate software flow control Reserved Read value is undefined only zero should be NA written Continuous Clock generation By default SCLK is only 0 output while data is being transmitted in synchronous mode Clock on character In synchronous mode SCLK cycles only when characters are being sent on Un TXD or to complete a character that is being received Continuous clock SCLK runs continuously in synchronous mode allowing characters to be received on Un RxD independently from transmission on Un TXD Clear Continuous Clock 0 No affect on the CC bit Auto clear The CC bit is automatically cleared when a complete character has been received This bit is cleared at the same time Reserved Read value is undefined only zero should be NA written UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 177 of 326 NXP Semiconductors U M1 0601 Chapter 15 LPC800 USARTO 1 2 15 6 3 USART Status register The STAT register primarily provides a complete set of USART status flags for software to read Flags oth
215. ansition to deasserted in both master and slave modes This allows determining when the SPI transmit receive functions become idle This flag is cleared by software Stalled status flag This indicates whether the SPI is currently in a stall condition Reset Access value 1 0 RO 1 RO All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 217 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 Table 191 SPI Status register STAT addresses 0x4005 8008 SPIO 0x4005 C008 SPI1 bit description Bit Symbol Description Reset Access value 1 7 ENDTRANSFER Transfer control bit Software can set this bit to force an end to the current 0 RO W1 transfer when the transmitter finishes any activity already in progress as if the EOT flag had been set prior to the last transmission This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer The bit is cleared when the transmitter becomes Idle as the transfer comes to an end Forcing an end of transfer in this manner causes any specified FrameDelay and TransferDelay to be inserted 8 IDLE Idle status flag This bit is 1 whenever the SPI master function is fully idle This 1 RO means that the transmit holding register is empty and the transmitter is not in the process o
216. apter 6 LPC800 I O configuration IOCON Table 57 10 register PIOO 10 address 0x4004 4020 bit description Bit Symbol Value Description Reset value 5 0 Reserved 0 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin 7 s 9 8 I2ZCMODE reads as 0 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 Reserved 1 Selects 12C mode 00 Select Standard mode I2ZCMODE 00 default or Standard I O functionality 2 01 if the pin function is GPIO FUNC 000 0 0 Standard mode Fast mode I2C 0 1 Standard functionality 0x2 Fast mode Plus l2C 0x3 Reserved 10 Reserved 12 11 S MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIV4 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 64 of 326 NXP Semiconductors UM10601 6 5 10
217. aracter in terms of its own frequency the 12 MHz IRC frequency and programs the baud rate generator of the serial port It also sends an ASCII string Synchronized lt CR gt lt LF gt to the host In response the host should send the same string Synchronized lt CR gt lt LF gt The boot loader auto baud routine looks at the received characters to verify synchronization If synchronization is verified then OK lt CR gt lt LF gt string is sent to the host The host should respond by sending the crystal frequency in kHz at which the part is running The response is required for backward compatibility of the boot loader code and on the LPC800 is ignored The boot loader configures the part to run at the 12 MHz IRC frequency Once the crystal frequency response is received the part is initialized and the ISP command handler is invoked For safety reasons an Unlock command is required before executing the commands resulting in flash erase write operations and the Go command The rest of the commands can be executed without the unlock command The Unlock command is required to be executed once per ISP session The Unlock command is explained in Table 219 UART ISP Unlock command All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 245 of 326 NXP Semiconductors U M1 0601 Chapter 20 LPC800 Boot ROM 20
218. are POR reset values Table 134 Register overview MRT base address 0x4000 4000 Name INTVALO TIMERO CTRLO STATO INTVAL1 TIMER1 CTRL1 STATI INTVAL2 TIMER2 CTRL2 STAT2 UM10601 Access Address Description R W R R W R W R W R W R W R W R W R W R W R W offset 0x0 0 4 0x8 OxC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C Time interval value register This value is loaded into the TIMERO register MRTO Timer register This register reads the value of the down counter MRTO Control register This register controls the MRTO modes MRTO Status register MRT1 Time interval value register This value is loaded into the TIMER1 register MRT1 Timer register This register reads the value of the down counter MRT1 Control register This register controls the MRT1 modes MRT1 Status register MRT2 Time interval value register This value is loaded into the TIMER register MRT2 Timer register This register reads the value of the down counter MRT2 Control register This register controls the MRT2 modes MRT2 Status register All information provided in this document is subject to legal disclaimers Reset value Reference 0 Table 135 Ox7FFF FFFF Table 136 0 Table 137 0 Table 138 0 Table 135 Ox7FFF FFFF Table 136 0 Table 137 0 Table 138 0 Table 135 Ox7FFF FFFF Table 136 0 Table 137 0 Table 138 NXP
219. aspects of the USART that would normally be configured once in an application Remark If software needs to change configuration values the following sequence should be used 1 Make sure the USART is not currently sending or receiving data 2 Disable the USART by writing a O to the Enable bit 0 may be written to the entire register 3 Write the new configuration value with the ENABLE bit set to 1 Table 158 USART Configuration register CFG address 0x4006 4000 USARTO 0x4006 8000 USART1 0x4006 C000 USART2 bit description Bit Symbol Value Description Reset Value 0 ENABLE USART Enable 0 0 Disabled The USART is disabled and the internal state 32 DATALEN machine and counters are reset While Enable 0 all USART interrupts are disabled When Enable is set again CFG and most other control bits remain unchanged For instance when re enabled the USART will immediately generate a TxRady interrupt if enabled in the INTENSET register because the transmitter has been reset and is therefore available Enabled The USART is enabled for operation Reserved Read value is undefined only zero should be NA written Selects the data size for the USART 00 0x0 7 bit Data length 0 1 8 bit Data length 0x2 9 bit data length The 9th bit is commonly used for addressing in multidrop mode See the ADDRDET bit in the CTRL register 0x3 Reserved 5 4 PARITYSEL Selects what type of parity is used by the USART 00 0x0 No
220. assigned to this pin By default the fixed pin function is deselected and GPIO is assigned to this pin Enable XTALOUT This function is enabled on pin PIOO 9 Disable XTALOUT GPIO function PIOO 9 default or any other movable function can be assigned to pin PIOO 9 Enables fixed pin function Writing a 1 deselects the function and any movable function can be assigned to this pin This function is selected by default Enable RESET This function is enabled on pin PIOO 5 Disable RESET GPIO function PIOO 5 is selected on this pin Any other movable function can be assigned to pin PIOO 5 Enables fixed pin function Writing a 1 deselects the function and any movable function can be assigned to this pin By default the fixed pin function is deselected and GPIO is assigned to this pin Functions CLKIN and ACMP 12 are connected to the same pin PIOO 1 To use CLKIN disable ACMP 12 in bit 1 of this register and enable CLKIN Enable CLKIN This function is enabled on pin PIOO 1 Disable CLKIN GPIO function PIOO 1 default or any other movable function can be assigned to pin CLKIN Enables fixed pin function Writing a 1 deselects the function and any movable function can be assigned to this pin By default the fixed pin function is deselected and GPIO is assigned to this pin Enable VDDCMP This function is enabled on pin PIOO 6 Disable VDDCMP GPIO function PIOO 6 default or any other movable function can be assigned to pin PIOO 6
221. be set up 1 Initialize pointer to the I2C API function table 2 Declare the PARAM and RESULT struct 3 Declare Error Code struct 4 Declare the transmit and receive buffer If interrupts are used then additional driver variables have to be set up 1 Declare the I2C T type 2 Declare callback functions 3 Declare 12C ROM Driver ISR within the 12C ISR 4 Enable 12 interrupt I2C Master mode set up The I2C ROM Driver support polling and interrupts In the master mode 7 bit and 10 bit addressing are supported The setup is as follows All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 287 of 326 NXP Semiconductors UM1 0601 Chapter 23 LPC800 I2C bus ROM API 1 Allocate SRAM for the I2C ROM Driver by making a call to the 2 get mem size function 2 Create the I2C handle by making a call to the i2c_setup function 3 Set the I2C operating frequency by making a call to the i2c set bitrate function 12 1 ROM DRIVERS PTR pI2CD setup I2C function table pointer size in bytes 2 gt 12 get mem size i2c handle plI2cApi i2c setup LPC I2C BASE uint32 t amp I2C Handle 0 error code pI2cApi i2c set bitrate I2C HANDLE T i2c handle PCLK in Hz bps in hz 23 5 3 12 Slave mode set up The I2C ROM Driver support polling an
222. bit word at the lowest address Result1 The second 32 bit word Result2 The third 32 bit word Result3 The fourth 32 bit word Description This command is used to read the unique ID 21 5 2 10 Erase page Table 246 IAP Erase page command Command Erase page Input Command code 59 decimal Param0 Start page number Param1 End page number should be greater than or equal to start page Param2 System Clock Frequency CCLK in kHz Return Code CMD SUCCESS BUSY SECTOR NOT PREPARED FOR WRITE OPERATION INVALID SECTOR Result None Description This command is used to erase a page or multiple pages of on chip flash memory To erase a single page use the same start and end page numbers 21 5 2 11 IAP Status Codes Table 247 IAP Status Codes Summary Status Mnemonic Description Code 0 CMD_SUCCESS Command is executed successfully 1 INVALID COMMAND Invalid command 2 SRC ADDR ERROR Source address is not on a word boundary 3 DST ADDR ERROR Destination address is not on a correct boundary UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 265 of 326 NXP Semiconductors U M1 0601 Chapter 21 LPC800 Flash ISP and IAP programming Table 247 IAP Status Codes Summary Status Mnemonic Description Code 4 SRC ADDR NOT MAPPED Source address is not mapped in the memory map Count value is taken in to con
223. bled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 lt Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 56 of 326 NXP Semiconductors UM10601 6 5 2 PIOO 13 register Chapter 6 LPC800 I O configuration IOCON Table 50 13 register PIOO 13 address 0x4004 4004 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin
224. ccess Address Description Reset Reference offset value CTRL R W 0x0 Self wake up timer control register 0 Table 154 COUNT R W Counter register Control register The WKT interrupt must be enabled in the NVIC to wake up the part using the self wake up counter Table 154 Control register CTRL address 0x4000 8000 bit description Bit Symbol Value Description Reset value 0 CLKSEL Select the self wake up timer clock source 0 0 Divided IRC clock This clock runs at 750 kHz and provides time out periods of up UM10601 to approximately 95 minutes in 1 33 us increments Remark This clock is not available in not available in Deep sleep power down deep power down modes Do not select this option if the timer is to be used to wake up from one of these modes Low power clock This is the nominally 10 kHz clock and provides time out periods of up to approximately 119 hours in 100 us increments The accuracy of this clock is limited to 45 over temperature and processing Remark This clock is available in all power modes Prior to use the low power oscillator must be enabled The oscillator must also be set to remain active in Deep power down if needed All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 166 of 326 NXP Semiconductors U M1 0601 Chapter 14 LPC800 Self wake up timer WKT
225. ce SYSMEMREMAP R W 0x000 System memory remap 0x2 Table 6 PRESETCTRL R W 0x004 Peripheral reset control 0x0000 1FFF Table 7 SYSPLLCTRL R W 0x008 System PLL control 0 Table 8 SYSPLLSTAT R 0x00C System PLL status 0 Table 9 0 010 Reserved 0x014 Reserved SYSOSCCTRL R W 0x020 System oscillator control 0x000 Table 10 WDTOSCCTRL R W 0x024 Watchdog oscillator control 0x0A0 Table 11 0x028 Reserved 0x02C Reserved SYSRSTSTAT R W 0x030 System reset status register 0 Table 12 SYSPLLCLKSEL R W 0x040 System PLL clock source select 0 Table 13 SYSPLLCLKUEN R W 0x044 System PLL clock source update enable 0 Table 14 MAINCLKSEL R W 0x070 Main clock source select 0 Table 15 MAINCLKUEN R W 0x074 Main clock source update enable 0 Table 16 SYSAHBCLKDIV R W 0x078 System clock divider 1 Table 17 SYSAHBCLKCTRL R W 0x080 System clock control Ox1F Table 18 UARTCLKDIV R W 0x094 USART clock divider 0 Table 19 5 0x098 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 17 of 326 NXP Semiconductors UM10601 Chapter 4 LPC800 System configuration SYSCON Table 5 Register overview System configuration base address 0x4004 8000 continued Name Access Offset Description Reset value Reference 0x09C Reserved Reserved OxOBC 0 0 Reserved
226. ch reload registers 0 to 4 REGMODEn bit 0 A Match register L H or unified 32 bit is loaded from the corresponding Reload register when BIDIR is 0 and the counter reaches its limit condition or when BIDIR is 1 and the counter reaches 0 Table 127 SCT match reload registers 0 to 4 MATCHREL 0 4 address 0x5000 4200 MATCHRELO to 0x5000 4210 MATCHREL4 bit description REGMODEn bit 0 Bit Symbol Description Reset value 15 0 RELOAD When UNIFY 0 read or write the 16 bit value to be loaded into 0 the SCTMATCHn L register When UNIFY 1 read or write the lower 16 bits of the 32 bit value to be loaded into the MATCHn register 31 16 RELOAD When UNIFY read or write the 16 bit to be loaded into the 0 MATCHn H register When UNIFY 1 read or write the upper 16 bits of the 32 bit value to be loaded into the MATCHn register SCT capture control registers 0 to 4 REGMODEn bit 1 If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers CAPCTRLn L and CAPCTRLn H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 132 of 326 NXP Semiconductors U M1 0601 10 6 22 10 6 23 UM10
227. changed on the following edge 1 Capture The SPI changes serial data on the first clock transition of the frame when the clock changes away from the rest state Data is captured on the following edge 5 CPOL Clock Polarity select 0 0 Low The rest state of the clock between frames is low 1 High The rest state of the clock between frames is high 6 Reserved Read value is undefined only zero should be written NA 7 LOOP Loopback mode enable Loopback mode applies only to Master mode and connects 0 transmit and receive data connected together to allow simple software testing 0 Disabled 1 Enabled 8 SPOL SSEL Polarity select 0 0 Low The SSEL pin is active low The value in the SSEL fields of the RXDAT TXDATCTL and TXCTL registers related to SSEL is not inverted relative to the pins 1 High The SSEL pin is active high The value in the SSEL fields of the RXDAT TXDATCTL and TXCTL registers related to SSEL is inverted relative to the pins 31 9 Reserved Read value is undefined only zero should be written NA UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 215 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 17 6 2 SPI Delay register The DLY register controls several programmable delays related to SPI signalling These delays apply only to master mode and are all stated in SPI c
228. chdog timer base address 0x4000 4000 Name Access Address Description Reset Reference offset value MOD R W 0x000 Watchdog mode register This 0 Table 142 register contains the basic mode and status of the Watchdog Timer TC R W 0x004 Watchdog timer constant register OxFF Table 144 This 24 bit register determines the time out value FEED WO 0x008 Watchdog feed sequence register NA Table 145 Writing OxAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC TV RO 0x00C Watchdog timer value register This OXFF Table 146 24 bit register reads out the current value of the Watchdog timer 0x010 Reserved z WARNINT R W 0x014 Watchdog Warning Interrupt compare 0 Table 147 value WINDOW R W 0x018 Watchdog Window compare value OxFF FFFF Table 148 Watchdog mode register The WDMOD register controls the operation of the Watchdog Note that a watchdog feed must be performed before any changes to the WDMOD register take effect Table 142 Watchdog mode register MOD 0x4000 4000 bit description Bit Symbol Value Description Reset value 0 WDEN Watchdog enable bit Once this bit has been written with 0 a 1 it cannot be re written with a 0 Once this bit is set to one the watchdog timer starts running after a watchdog feed 0 The watchdog timer is stopped 1 The watchdog timer is running 1 WDRESET Watchdog reset enable bit Once this bit has been 0 written with a 1 it cannot
229. cimal Table 242 Compare 56 decimal Table 243 Reinvoke ISP 57 decimal Table 244 Read UID 58 decimal Table 245 Erase page 59 decimal Table 246 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 260 of 326 NXP Semiconductors U M1 0601 Chapter 21 LPC800 Flash ISP and IAP programming COMMAND CODE PARAMETER 1 PARAMETER 2 PARAMETER n command parameter table ARM REGISTER ARM REGISTER r1 STATUS CODE RESULT 1 RESULT 2 RESULT n command result table Fig 42 IAP parameter passing 21 5 2 1 Prepare sector s for write operation IAP This command makes flash write erase operation a two step process Table 237 IAP Prepare sector s for write operation command Command Prepare sector s for write operation Input Command code 50 decimal Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Return Code CMD SUCCESS BUSY INVALID SECTOR Result None Description This command must be executed before executing Copy RAM to flash or Erase Sector s command Successful execution of the Copy RAM to flash or Erase Sector s command causes relevant sectors to be protected again The boot sector can not be prepared by this command To prepare a single sector use the same Start a
230. comparator is available on all LPC800 parts Selectable external inputs can be used as either the positive or negative input of the comparator The Internal voltage reference 0 9 V bandgap reference can be used as either the positive or negative input of the comparator 32 stage voltage ladder can be used as either the positive or negative input of the comparator Voltage ladder source selectable between the supply pin Vpp or VDDCMP pin Voltage ladder can be separately powered down when not required Interrupt capability 13 3 Basic configuration Configure the analog comparator using the following registers In the SYSAHBCLKCTRL register set bit 19 Table 18 to enable the clock to the register interface You can enable or disable the power to the analog comparator through the PDRUNCFG register Table 37 Clear the analog comparator peripheral reset using the PRESETCTRL register Table 7 The analog comparator interrupt is connected to interrupt 11 in the NVIC Configure the analog comparator pin functions through the switch matrix See Section 13 4 13 3 1 Connect the comparator output to the SCT You can use the comparator output function ACMP to start or stop the SCT or more generally create an SCT event To create an SCT event connect as follows UM10601 iF 2 Using the switch matrix connect to a pin See Table 149 Using the switch matrix connect any of the SCT input
231. comparator reset control 1 0 Assert the analog comparator reset 1 Clear the analog comparator controller reset 31 12 Reserved System PLL control register This register connects and enables the system PLL and configures the PLL multiplier and divider values The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources The input frequency is multiplied to a higher frequency and then divided down to provide the actual clock used by the CPU peripherals and memories The PLL can produce a clock up to the maximum allowed for the CPU Remark The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 20 of 326 NXP Semiconductors U M1 0601 4 6 4 4 6 5 Chapter 4 LPC800 System configuration SYSCON Table 8 System PLL control register SYSPLLCTRL address 0x4004 8008 bit description Bit Symbol Value Description Reset value 4 0 MSEL Feedback divider value The division value M is the 0 programmed MSEL value 1 00000 Division ratio M 1 un Division ratio M 32 6 5 PSEL Post divider ratio P The division ratio is 2 x P 0 0x0 P 1 0 1 2 0 2 4 0x3 P 8 31 77 Reserved Do not write ones to reserved bits System PLL status register Th
232. configurable hysteresis 5 V tolerant pin providing standard digital I O functions with configurable modes configurable hysteresis and analog I O for the system oscillator When configured as an analog I O the digital section of the pin is disabled and the pin is not 5 V tolerant Not a 5 V tolerant pin due to special analog functionality Pin provides standard digital I O functions with configurable modes configurable hysteresis and analog I O When configured as an analog I O the digital section of the pin is disabled Table 286 Movable functions assign to pins PIOO 0 to PIO 17 through switch matrix Function name Description UO TXD Transmitter output for USARTO UO RXD Receiver input for USARTO UO RTS Request To Send output for USARTO UO CTS Clear To Send input for USARTO UO SCLK Serial clock input output for USARTO in synchronous mode U1_TXD O Transmitter output for USART1 U1 RXD Receiver input for USART1 U1 RTS Request To Send output for USART1 U1 CTS Clear To Send input for USART1 U1 SCLK Serial clock input output for USART1 in synchronous mode U2 TXD O Transmitter output for USART2 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 306 of 326 NXP Semiconductors UM10601 UM10601 Chapter 26 LPC800 Packages and pin description Table 286
233. contains information for the general configuration of the SPI Typically this information is not changed during operation Some configurations such as CPOL CPHA and LSBF should not be made while the SPI is not fully idle See the description of the Idle status in Table 191 for more information Remark If the interface is re configured from Master mode to Slave mode or the reverse an unusual case the SPI should be disabled and re enabled with the new configuration Table 189 SPI Configuration register CFG addresses 0x4005 8000 SPIO 0x4005 C000 SPI1 bit description Bit Symbol Value Description Reset value 0 Enable SPI enable 0 0 Disabled The SPI is disabled and the internal state machine and counters are reset 1 Enabled The SPI is enabled for operation Reserved Read value is undefined only zero should be written NA 2 Master Master mode select 0 0 Slave mode The SPI will operate in slave mode SCK MOSI and the SSEL signals are inputs MISO is an output 1 Master mode The SPI will operate in master mode SCK MOSI and the SSEL signals are outputs MISO is an input 3 LSBF LSB First mode enable 0 0 Standard Data is transmitted and received in standard MSB first order 1 Reverse Data is transmitted and received in reverse order LSB first 4 CPHA Clock Phase select 0 0 Change The SPI captures serial data on the first clock transition of the frame when the clock changes away from the rest state Data is
234. ction on pin PIOO 4 Enable the low power oscillator for use with the 10 kHz self wake up timer 0 clock You must set this bit if the CLKSEL bit in the self wake up timer CTRL bit is set Do not enable the low power oscillator if the self wake up timer is clocked by the divided IRC 0 Disabled 1 Enabled Enable the low power oscillator in Deep power down mode Setting this bit 0 causes the low power oscillator to remain running during Deep power down mode provided that bit 12 in this register is set as well You must set this bit for the self wake up timer to be able to wake up the part from Deep power down mode Remark Do not set this bit unless you use the self wake up timer to wake up from Deep power down mode 0 Disabled 1 Enabled Data retained during Deep power down mode 0x0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 45 of 326 NXP Semiconductors U M1 0601 Chapter 5 LPC800 Reduced power modes and Power Management 5 7 Functional description 5 7 1 5 7 2 5 7 3 5 7 3 1 UM10601 Power management The LPC800 support a variety of power control features In Active mode when the chip is running power and clocks to selected peripherals can be optimized for power consumption In addition there are four special modes of processor power reduction with different per
235. d The boot sector can not be written by this command Erase Sector s IAP Table 239 IAP Erase Sector s command Command Input Return Code Result Description Erase Sector s Command code 52 decimal Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Param2 System Clock Frequency CCLK in kHz CMD SUCCESS BUSY SECTOR NOT PREPARED FOR WRITE OPERATION INVALID SECTOR None This command is used to erase a sector or multiple sectors of on chip flash memory The boot sector can not be erased by this command To erase a single sector use the same Start and End sector numbers All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 262 of 326 NXP Semiconductors UM10601 Chapter 21 LPC800 Flash ISP and IAP programming 21 5 2 4 Blank check sector s IAP 21 5 2 5 21 5 2 6 UM10601 Table 240 IAP Blank check sector s command Command Input Return Code Result Description Blank check sector s Command code 53 decimal Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number CMD_SUCCESS BUSY SECTOR NOT BLANK INVALID SECTOR Result0 Offset of the first non blank word location if the Status Code is SECTOR NOT
236. d by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers The power configuration can be changed during run time Power configuration in Active mode Power consumption in Active mode is determined by the following configuration choices All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 46 of 326 NXP Semiconductors U M1 0601 5 7 4 5 7 4 1 5 7 4 2 5 7 4 3 UM10601 Chapter 5 LPC800 Reduced power modes and Power Management The SYSAHBCLKCTRL register controls which memories and peripherals are running Table 18 The power to various analog blocks PLL oscillators the BOD circuit and the flash block can be controlled at any time individually through the PDRUNCFG register Table 37 Power configuration register PDRUNCFG address 0x4004 8238 bit description The clock source for the system clock can be selected from the IRC default the System oscillator or the watchdog oscillator see Figure 3 and related registers The system clock frequency can be selected by the SYSPLLCTRL Table 8 and the SYSAHBCLKDIV register Table 17 The USART and CLKOUT use individual peripheral clocks with their own clock dividers The peripheral clocks can be shut down through the corresponding clock divider registers Sleep mode In Sleep mode the system clock to the ARM Cortex M0 cor
237. d K Input None Return Code SUCCESS followed by 2 bytes of boot code version number in ASCII format It is to be interpreted as lt byte1 Major gt lt byte0 Minor gt Description This command is used to read the boot code version number All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 256 of 326 NXP Semiconductors U M1 0601 21 5 1 13 21 5 1 14 21 5 1 15 UM10601 Chapter 21 LPC800 Flash ISP and IAP programming Compare lt address1 gt lt address2 gt lt no of bytes gt Table 232 UART ISP Compare command Command M Input Address1 DST Starting flash or RAM address of data bytes to be compared This address should be a word boundary Address2 SRC Starting flash or RAM address of data bytes to be compared This address should be a word boundary Number of Bytes Number of bytes to be compared should be a multiple of 4 Return Code CMD_SUCCESS Source and destination data are equal COMPARE_ERROR Followed by the offset of first mismatch COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED PARAM_ERROR Description This command is used to compare the memory contents at two locations Example M 8192 268468224 4 lt CR gt lt LF gt compares 4 bytes from the RAM address 0x1000 8000 to the 4 bytes from the flash address 0x2000 Rea
238. d Watchdog timer block diagram 12 5 2 Clocking and power control The watchdog timer block uses two clocks PCLK and WDCLK PCLK is used for the APB accesses to the watchdog registers and is derived from the system clock see Figure 3 The WDCLK is used for the watchdog timer counting and is derived from the watchdog oscillator The synchronization logic between the two clock domains works as follows When the MOD and TC registers are updated by APB operations the new value will take effect in 3 WDCLK cycles on the logic in the WDCLK clock domain When the watchdog timer is counting on WDCLK the synchronization logic will first lock the value of the counter on WDCLK and then synchronize it with PCLK so that the CPU can read the WDTV register Remark Because of the synchronization step software must add a delay of three WDCLK clock cycles between the feed sequence and the time the WDPROTECT bit is enabled in the MOD register The length of the delay depends on the selected watchdog clock WDCLK UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 152 of 326 NXP Semiconductors U M1 0601 12 5 3 12 5 3 1 12 5 3 2 UM10601 Chapter 12 LPC800 Windowed Watchdog Timer WWDT Using the WWDT lock features The WWDT supports several lock features which can be enabled to ensure that the WWDT is runn
239. d handler responds with OK lt CR gt lt LF gt when the transfer has finished Table 222 UART ISP Write to RAM command Command Input Start Address RAM address where data bytes are to be written This address should be a word boundary Number of Bytes Number of bytes to be written Count should be a multiple of 4 Return Code CMD SUCCESS ADDR ERROR Address not on word boundary ADDR NOT MAPPED COUNT ERROR Byte count is not multiple of 4 PARAM ERROR CODE READ PROTECTION ENABLED Description This command is used to download data to RAM This command is blocked when code read protection levels 2 or 3 are enabled Writing to addresses below 0x1000 0300 is disabled for CRP1 Example W 268436224 4 lt CR gt lt LF gt writes 4 bytes of data to address 0x1000 0300 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 252 of 326 NXP Semiconductors U M1 0601 21 5 1 5 21 5 1 6 21 5 1 7 UM10601 Chapter 21 LPC800 Flash ISP and IAP programming Read Memory lt address gt lt number of bytes gt Reads the the plain binary code of the data stream followed by the CMD_SUCCESS return code Table 223 UART ISP Read Memory command Command R Input Start Address Address from where data bytes are to be read This address should be a word boundary Number of Bytes Number
240. d in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 66 of 326 NXP Semiconductors UM10601 6 5 12 PIOO 1 register Chapter 6 LPC800 I O configuration IOCON Table 60 1 register PIOO 1 address 0x4004 402C bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 I
241. d interrupts in the slave mode In the slave mode only 7 bit addressing is supported The set up is as follows 1 Allocate SRAM for the I2C ROM Driver by making a call to the 2 get mem size function 2 Create the 12 handle by making a call to the i2c_setup function 3 Set the I2C operating frequency by making a call to the i2c set bitrate function 4 Set the slave address by making a call to the i2c set slave function The I2C ROM driver allows setting up to 4 slave addresses and 4 address masks as well as possibly enabling the General Call address The four slave address bytes are packed into the 4 byte variable Slave address byte 0 is the least significant byte and Slave address byte 3 is the most significant byte The Slave address mask bytes are ordered the same way in the other 32 bit variable When in slave receive mode all of these addresses or groups if masks are used will be monitored for a match If the General Call bit least significant bit of any of the four slave address bytes is set then the General Call address of 0x00 is monitored as well 31 25 24 23 17 16 15 9 8 7 1 0 Slave Address 3 GC Slave Address 2 GC Slave Address 1 GC Slave Address O GC Fig 47 12 slave mode set up address packing 12 1 ROM DRIVERS PTR pI2CD setup I2C function table pointer size in bytes pI2cApi i2c get mem size i2c handle plI2cApi
242. d or written individually or in a single 32 bit read or write operation The bits in this register select which events if any clear the STOP bit in the Control register Since no events can occur when HALT is 1 only software can clear the HALT bit by writing the Control register Table 113 SCT start condition register START address 0x5000 4014 bit description Bit Symbol Description Reset value 5 0 STARTMSK_L If bit n is one event n clears the STOP_L bit in the CTRL 0 register event 0 bit 0 event 1 bit 1 event 5 bit 5 15 6 Reserved 21 16 STARTMSK If bit n is one event n clears the STOP H bit in the CTRL 0 register event 0 bit 16 event 1 bit 17 event 5 bit 21 31 22 Reserved 10 6 7 SCT counter register If UNIFY 1 in the CONFIG register the counter is a unified 32 bit register and both the Land H bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers COUNT L and COUNT H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation In this case the L and H registers count independently under the control of the other registers Attempting to write a counter while it is running does not affect the counter but produces a bus error Software can read the counter registers at any time UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights
243. d so that a watchdog event will cause a reset and the counter reaches zero the CPU will be reset loading the stack pointer and program counter from the vector table as for an external reset The Watchdog time out flag WDTOF can be examined to determine if the Watchdog has caused the reset condition The WDTOF flag must be cleared by software When the Watchdog Timer is configured to generate a warning interrupt the interrupt will occur when the counter matches the value defined by the WARNINT register 12 5 1 Block diagram The block diagram of the Watchdog is shown below in the Figure 22 The synchronization logic PCLK WDCLK is not shown in the block diagram UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 151 of 326 NXP Semiconductors U M1 0601 Chapter 12 LPC800 Windowed Watchdog Timer WWDT feed ok wd dk 24 bit down counter e WDTV In range feed sequence range detect and protection WDINTVAL H zi 2 o amp interrupt compare shadow bit feed ok v v MOD WDPROTECT WDTOF WDINT WDRESET WDEN register 4 2 MOD 3 MOD 1 MOD O0 v chip reset _ watchdog interrupt gt Fig 22 Windowe
244. d to operate asynchronously from any on chip clocks and without the need for overclocking In slave mode this means that the SCK from the external master is used directly to run the transmit and receive shift registers and other logic In master mode the SPI rate clock produced by the SPI clock divider is used directly as the outgoing SCK The SPI clock divider is an integer divider The SPI in master mode can be set to run at the same speed as the selected PCLK or at lower integer divide rates The SPI rate will be PCLK_SPIn DIVVAL In slave mode the clock is taken from the SCK input and the SPI clock divider is not used 17 7 4 Slave select The SPI block provides for one Slave Select input in slave mode or output in master mode The SSEL can be set for normal polarity active low or can be inverted active high Representation of the SSEL in a register is always active low If the SSEL is inverted this is done as the signal leaves enters the SPI block In slave mode the asserted SSEL that is connected to a pin will activate the SPI In master mode the SSEL that is connected to a pin will be output as defined in the SPI registers In master mode the Slave Select is configured by the TXSSELN field which appears in both the TXCTL and TXDATCTL registers In slave mode the state of the SSEL is saved along with received data in the RXSSELN field of the RXDAT register 17 7 5 Data lengths greater than 16 bits The SPI inte
245. dUID Table 233 UART ISP ReadUID command Command N Input None Return Code CMD SUCCESS followed by four 32 bit words of E sort test information in ASCII format The word sent at the lowest address is sent first Description This command is used to read the unique ID Read CRC checksum lt address gt no of bytes gt Get the CRC checksum of a block of RAM or flash CMD SUCCESS followed by 8 bytes of CRC checksum in ASCII format The checksum is calculated as follows CRC 32 polynomial x32 x26 x23 x22 x16 x12 x11 x10 8 x7 x5 x4 X2 1 Seed Value OxFFFF FFFF No bit order reverse for data input No 1 s complement for data input No bit order reverse for CRC sum No 1 s complement for CRC sum All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 257 of 326 NXP Semiconductors U M1 0601 Chapter 21 LPC800 Flash ISP and IAP programming Table 234 UART ISP Read CRC checksum command Command S Input Address The data are read from this address for CRC checksum calculation This address must be on a word boundary Number of Bytes Number of bytes to be calculated for the CRC checksum must be a multiple of 4 Return Code CMD SUCCESS followed by data in plain binary format ADDR ERROR address not on word boundary ADDR NOT MAPPED COUNT ERROR byte count is not
246. ddress 0x5000 bit 130 Table 122 SCT event flag register EVFLAG address 0x5000 40F4 bit description 130 Table 123 SCT conflict enable register CONEN address 0x5000 40F8 bit description 131 Table 124 SCT conflict flag register CONFLAG address 0x5000 40FC bit description 131 Table 125 SCT match registers 0 to 4 MATCH 0 4 address 0x5000 4100 to 0x5000 4110 bit description REGMODEn Dit O sas eR eR REFUS 132 Table 126 SCT capture registers 0 to 4 CAP 0 4 address 0x5000 4100 CAPO to 0x5000 4110 CAP4 bit description REGMODEn bit 1 132 Table 127 SCT match reload registers 0 to 4 MATCHREL 0 4 address 0x5000 4200 MATCHRELO to 0x5000 4210 MATCHREL4 bit description REGMODEn bit 0 132 Table 128 SCT capture control registers 0 to 4 CAPCTRL 0 4 address 0x5000 4200 CAPCTRLO to 0x5000 4210 CAPCTRLA bit description REGMODEn bit 1 133 Table 129 SCT event state mask registers 0 to 5 UM10601 All information provided in this document is subject to legal disclaimers Chapter 28 Supplementary information EV 0 5 STATE addresses 0x5000 4300 EVO STATE to 0x5000 4328 EV5_STATE bit description cce ees ee dE 133 Table 130 SCT event control register 0 to 5 EV 0 5 CTRL address 0x5000 4304 EVO CTRL to 0x5000 432C EV5 CTRL bit descripti
247. defined if interrupts for the 12C ROM driver are used typedef void I2C CALLBK T uint32 t err code uint32 t n The callback function will be called by the I2C ROM driver upon completion of a task when interrupts are used PARAM and RESULT structure The I2C ROM driver input parameters consist of two structures a PARAM structure and RESULT structure The PARAM structure contains the parameters passed to the 12C ROM driver and the RESULT structure contains the results after the 12C ROM driver is called The PARAM structure is as follows typedef struct i2c_A parameters passed to ROM function int32 t num bytes send t32 t num bytes rec t9 t buffer ptr send t8 t buffer ptr rec _CALLBK_T func pt callback function pointer t8 t stop flag t8 t dummy 3 required for word alignment I2C PARAM Hs Ss og EB cB GO 19 8 eg 3 The RESULT structure is as follows typedef struct 12 RESULTs struct results here when returned uint32 t n bytes sent uint32 t n bytes recd I2C RESULT Error structure The error code returned by the I2C ROM driver is an enum structure The Error structure is as follows typedef enum LPC_OK 0 lt enum value returned on Success ERROR ERR I2C BASE 0x00060000 0x00060001 ERR I2C NAK ERR 2 0x00060002 ERR I2C BUFFER OVERFLOW 0x00060003 ERR I2C BYTE COUNT ERR 0x00060004 ERR I2C 105
248. description 202 Table 181 Master Data register MSTDAT address 0x4005 0028 bit description 203 Table 182 Slave Control register SL VCTL address 0x4005 0040 bit description 204 Table 183 Slave Data register SLVDAT address 0x4005 0044 bit description 204 Table 184 Slave Address registers SLVADR 0 3 address 0x4005 0048 SLVADRO to 0x4005 0054 SLVADR3 bit description 205 Table 185 Slave address Qualifier 0 register SLVQUALO address 0x4005 0058 bit description 206 Table 186 Monitor data register MONRXDAT address 0x4005 0080 bit description 206 Table 187 SPI Pin 212 Table 188 Register overview SPI base address 0x4005 8000 SPIO 0x4008 C000 SPI1 213 Table 189 SPI Configuration register CFG addresses 0x4005 8000 SPIO 0x4005 C000 SPI1 bit description 215 Table 190 SPI Delay register DLY addresses 0x4005 8004 SPIO 0x4005 C004 SPI1 bit description 216 Table 191 SPI Status register STAT addresses 0x4005 8008 SPIO 0x4005 C008 SPI1 bit description icr eri m ee RR 217 Table 192 SPI Interrupt Enable read and Set register INTENSET addresses 0x4005 800C SPIO 0x4005 SPI1 bit description 218 Table 193 SPI Interrupt Enable clear register INTENCLR addresses 0x4005 8010
249. disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 165 of 326 NXP Semiconductors U M1 0601 Chapter 14 LPC800 Self wake up timer WKT A10 kHz low power clock with a dedicated on chip oscillator as clock source The IRC derived clock is much more accurate than the alternative low power clock However the IRC is not available in most low power modes This clock must not be selected when the timer is being used to wake up from a power mode where the IRC is disabled The alternative clock source is a nominally 10 kHz low power clock sourced from a dedicated oscillator This oscillator resides in the always on voltage domain so it can be programmed to continue operating in Deep power down mode when power is removed from the rest of the part This clock is also be available during other low power modes when the IRC clock is shut down The Low Power oscillator is not accurate approximately 4596 over process and temperature The frequency measurement feature if available lt tbd gt can be used to determine what the actual frequency is before selecting a time out value to write into the self wake up timer The frequency may still drift however while counting is in progress particularly due to reduced chip temperature after a low power mode is entered 14 6 Register description 14 6 1 Table 153 Register overview WKT base address 0x4000 8000 Name A
250. e 0x00 For uart get line function transfer without termination For uart put line function transfer without termination 0x01 For uart get line function stop transfer when I lt CR gt lt LF gt are received For uart put line function transfer is stopped after I reaching V lt CR gt lt LF gt characters are sent out after that 0x02 For uart get line function stop transfer when lt LF gt 11 is received For uart_put_line function transfer is stopped after reaching 0 A lt LF gt character is sent out after that 0x03 For uart_get_line function RESERVED All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 297 of 326 NXP Semiconductors UM1 0601 Chapter 24 LPC800 USART API ROM driver routines ll For uart put line function transfer is stopped after I reaching 0 uintl6_t driver mode 110 00 Polling mode function is blocked until transfer is II finished 0x01 Intr mode function exit immediately callback function is invoked when transfer is finished 0x02 RESERVED UART CALLBK T callback func pt callback function UART PARAM UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 298 of 326 UM10601 Chapter 25 LPC
251. e Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 4 High level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0x5 Low level Match occurs when there is a low level on the specified input 0x6 Constant 0 This bit slice never contributes to a match should be used to disable any unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs on an event i e when either a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 19 17 Specifies the match contribution condition for bit slice 3 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x2 Sticky fal
252. e LPC800 system clock is the input clock to the SCT clock processing and is the source of the SCT clock Clear the SCT peripheral reset using the PRESETCTRL register Table 7 The SCT combined interrupt is connected to slot 8 in the NVIC Use the switch matrix to connect the SCT inputs and outputs to pins see Section 10 4 and internally see Section 10 5 10 3 1 Use the SCT as a simple timer To configure the SCT as a simple timer with match or capture functionality follow these steps UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 115 of 326 NXP Semiconductors UM10601 Chapter 10 LPC800 State Configurable Timer SCT 1 Set up the SCT as one 32 bit timer or one or two 16 bit timers See Table 108 2 Preload the 32 bit timer or the 16 bit timers with a count value See Table 114 3 If you want to create a match event when the timer reaches a match value a Configure the register map for match registers See Table 117 Configure one or more match registers with a match value See Table 125 b c For each match value create a match event See Table 130 d If you want to create an interrupt on a match event enable the event for interrupt See Table 122 e If you want to create a match output on a pin connect the CTOUTn function to a pin see Section 10 4 and select an
253. e MTB MASTER register The trace is stored in the local SRAM starting at address 0x1000 0000 The trace memory location is configured in the MTB POSITION register Remark The MTB BASE register is not implemented Reading the BASE register returns 0x0 independently of the SRAM memory area configured for trace UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 302 of 326 UM10601 Chapter 26 LPC800 Packages and pin description Rev 1 1 24 January 2013 26 1 Packages Preliminary user manual RESET PIOO 5 PIO0 4 WAKEUP TRST SWCLK PIOO_3 TCK SWDIO PIOO 2 TMS aaa 005747 Fig 50 Pin configuration DIP8 package LPC810M021FN8 PIOO 0 ACMP I1 TDO Vss Vpp PIOO 1 ACMP I2 CLKIN TDI 13 PIO0 12 RESET PIOO 5 PIOO_4 WAKEUP TRST SWCLK PIOO_3 TCK SWDIO PIOO 2 TMS PIOO 11 10 LPC811M001FDH16 LPC812M101FDH16 TSSOP16 aaa 003707 PIOO 0 ACMP I1 TDO PIO0 6 VDDCMP PIO0 7 Vss Vpp PIOO 8 XTALIN PIOO 9 XTALOUT PIOO 1 ACMP I2 CLKIN TDI 17 PIOO 13 PIOO 12 RESET PIO0 5 PIOO 4 WAKEUP TRST SWCLK PIOO_3 TCK SWDIO PIOO 2 TMS 11 PIOO 10 PIOO 16 aaa 003756 Fig 52 Pin configuration SO20 package LPC812M101FD20 PIOO 14 PIOO 0 ACMP I1 TDO PIOO_6 VDDCMP PIOO 7 Vss VDD
254. e bottom 10 bits of the counter have the same value as the 10 bits of WARNINT and the remaining upper bits of the counter are all 0 This gives a maximum time of 1 023 watchdog timer counts 4 096 watchdog clocks for the interrupt to occur prior to a watchdog event If WARNINT is 0 the interrupt will occur at the same time as the watchdog event Table 147 Watchdog Timer Warning Interrupt register WARNINT 0x4000 4014 bit description Bit Symbol Description Reset Value 9 0 WARNINT Watchdog warning interrupt compare value 0 31 10 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined Watchdog Timer Window register The WINDOW register determines the highest WDTV value allowed when a watchdog feed is performed If a feed sequence occurs when WDTV is greater than the value in WINDOW a watchdog event will occur WINDOW resets to the maximum possible WDTV value so windowing is not in effect All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 157 of 326 NXP Semiconductors U M1 0601 Chapter 12 LPC800 Windowed Watchdog Timer WWDT Table 148 Watchdog Timer Window register WINDOW 0x4000 4018 bit description Bit Symbol Description Reset Value 23 0 WINDOW Watchdog window value OxFF FFFF 31 24 Reserved user software should not
255. e clock The core is always clocked Section 4 6 13 System clock control register 4 3 3 Setup the system oscillator using XTALIN and XTALOUT If you want to use the system oscillator with the LPC800 you need to assign the XTALIN and XTALOUT pins which connect to the external crystal through the fixed pin function in the switch matrix XTALIN and XTALOUT can only be assigned to pins 8 and PIOO 9 UM10601 1 In the IOCON block remove the pull up and pull down resistors in the IOCON registers for pins PIOO 8 and PIOO 9 2 In the switch matrix block enable the 1 bit functions for XTALIN and XTALOUT 3 In the SYSOSCCTRL register disable the BYPASS bit and select the oscillator frequency range according to the desired oscillator output clock All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 14 of 326 NXP Semiconductors U M1 0601 Chapter 4 LPC800 System configuration SYSCON Related registers Table 62 PIOO 8 register PIOO 8 address 0x4004 4038 bit description Table 61 PIOO 9 register 9 address 0x4004 4034 bit description Table 105 Pin enable register 0 PINENABLEO address 0x4000 C1C20 bit description Table 10 System oscillator control register SYSOSCCTRL address 0x4004 8020 bit description 4 4 Pin description The SY
256. e is stopped and execution of instructions is suspended until either a reset or an interrupt occurs Peripheral functions if selected to be clocked in the SYSAHBCLKCTRL register continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself memory systems and related controllers and internal buses The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Power configuration in Sleep mode Power consumption in Sleep mode is configured by the same settings as in Active mode The clock remains running The system clock frequency remains the same as in Active mode but the processor is not clocked Analog and digital peripherals are selected as in Active mode Programming Sleep mode The following steps must be performed to enter Sleep mode 1 The PD bits in the PCON register must be set to the default value 0x0 2 The SLEEPDEEP bit in the ARM Cortex M0 SCR register must be set to zero 3 Use the ARM Cortex M0 Wait For Interrupt WFI instruction Wake up from Sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs After wake up due to an interrupt the microcontroller returns to its original power configuration defined by the contents of the PDRUNCFG and t
257. e lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned This effectively prevents false lock indications and thus ensures a glitch free lock signal 471 2 Power down control To reduce the power consumption when the PLL clock is not needed a PLL Power down mode has been incorporated This mode is enabled by setting the SYSPLL bit to one in the Power down configuration register Table 37 In this mode the internal current reference will be turned off the oscillator and the phase frequency detector will be stopped and the dividers will enter a reset state While in PLL Power down mode the lock output will be low to indicate that the PLL is not in lock When the PLL Power down mode is terminated by setting the SYSPLL PD bit to zero the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock 4 7 1 3 Divider ratio programming 4 7 1 3 1 Post divider The division ratio of the post divider is controlled by the PSEL bits The division ratio is two times the value of P selected by PSEL bits as shown in Table 8 This guarantees an output clock with a 5096 duty cycle 4 7 1 3 2 Feedback divider The feedback divider s division ratio is controlled by the MSEL bits The division ratio between the PLL s output clock and the input clock is the decimal value on MSEL bits plus one as specified in Table 8 4 7
258. e post divider is enabled giving a 50 duty cycle clock with the following frequency relations 1 Fclkout Mx Fclkin FCCO 2 x P To select the appropriate values for M and P it is recommended to follow these steps 1 Specify the input clock frequency Fclkin 2 Calculate to obtain the desired output frequency Fclkout with M Fetkout Felkin 3 Find a value so that FCCO 2 x P x Felkout 4 Verify that all frequencies and divider values conform to the limits specified in Table 8 Remark The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz Table 40 shows how to configure the PLL for a 12 MHz crystal oscillator using the SYSPLLCTRL register Table 8 The main clock is equivalent to the system clock if the system clock divider SYSAHBCLKDIV is set to one see Table 17 Table 40 PLL configuration examples PLL input Main clock bits M divider PSEL bits divider FCCO clock Fclkout Table 8 value Table 8 value frequency Sys plicikin Fclkin lt tbd gt lt tbd gt lt tbd gt lt tbd gt lt tbd gt lt tbd gt lt tbd gt 12 MHz 24 MHz 00001 binary 2 10 binary 4 192 MHz PLL Power down mode In this mode the internal current reference will be turned off the oscillator and the phase frequency detector will be stopped and the dividers will enter a reset state While in PLL Power down mode the lock output will be low to indicat
259. e power setup command 0 24 command 1 CPU EFFICIENCY command 2 24 rom gt pWRD gt set_power command result The above code specifies that an application is running at the main and system clock of 24 MHz with emphasis on efficiency set power returns SUCCESS in result 0 after configuring the microcontroller s internal power control features All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 276 of 326 UM10601 Chapter 23 LPC800 I2C bus ROM Rev 1 1 24 January 2013 Preliminary user manual 23 1 How to read this chapter The I2C bus ROM is available on all LPC800 parts 23 2 Features e Simple 12 drivers to send and receive data on the I2C bus Polled and interrupt driven receive and transmit functions for master and slave modes 23 3 General description The drivers are callable for use by any application program to send or receive data on the I2C bus With the I2C drivers it is easy to produce working projects using the I2C interface The ROM routines allow the user to operate the 12C interface as a Master or a Slave The software routines do not implement arbitration to make a Master switch to a Slave mode in the midst of a transmission Although multi master arbitration is not implemented in these 12C drivers it is possible to
260. e routed to the SCT via the switch matrix allowing to capture the time of a voltage crossing or to count crossings in either or both directions See Section 13 3 1 Connect the comparator output to the SCT 13 6 Register description 13 6 1 Table 150 Register overview Analog comparator base address 0x4002 4000 Name Access Address Description Reset value offset CTRL R W 0x000 Comparator control register 0 LAD R W 0x004 Voltage ladder register 0 Comparator control register This register enables the comparator configures the interrupts and controls the input multiplexers on both sides of the comparator All bits not shown in Table 151 are reserved and should be written as 0 Table 151 Comparator control register CTRL address 0x4002 4000 bit description Bit Symbol Value Description Reset value 2 0 Reserved Write as 0 0 4 3 EDGESEL This field controls which edges on the comparator 0 output set the COMPEDGE bit bit 23 below 0x0 Falling edges 0 1 Rising edges 0x2 Both edges 0x3 Both edges 5 Reserved Write as 0 0 6 COMPSA Comparator output control 0 0 Comparator output is used directly 1 Comparator output is synchronized to the bus clock for output to other modules 7 Reserved Write as 0 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 162 of 326
261. e that the PLL is not in lock When the PLL Power down mode is terminated by SYSPLL_PD bit to zero in the Power down configuration register Table 37 the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 40 of 326 UM10601 Chapter 5 LPC800 Reduced power modes and Power Management Unit PMU Rev 1 1 24 January 2013 Preliminary user manual 5 1 How to read this chapter 5 2 Features The LPC800 provides an on chip API in the boot ROM to optimize power consumption in active and sleep modes See Table 249 Power profile API calls Read this chapter to configure the reduced power modes Deep sleep mode Power down mode and Deep power down mode Reduced power modes control Low power oscillator control Four general purpose backup registers to retain data in Deep power down mode 5 3 Basic configuration The PMU is always on as long as Vpp is present 5 4 Pin description The LPC800 has no configurable pins In Deep power down only the WAKEUP pin pin PIOO 4 is functional The WAKEUP function can be disabled in the DPDCTRL register to lower the power consumption even more In this case enable the self wake up timer to provide an internal wake up signal See Sectio
262. eading of the flash memory for signature generation uses a self timed read mechanism and does not depend on any configurable timing settings for the flash A safe estimation for the duration of the signature generation is Duration int 60 tcy 3 x FMSSTOP FMSSTART 1 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 239 of 326 NXP Semiconductors U M1 0601 19 5 1 3 UM10601 Chapter 19 LPC800 Flash coniroller When signature generation is triggered via software the duration is in AHB clock cycles and tcy is the time in ns for one AHB clock The SIG_DONE bit in FMSTAT can be polled by software to determine when signature generation is complete After signature generation a 32 bit signature can be read from the FMSWO register The 32 bit signature reflects the corrected data read from the flash and the flash parity bits and check bit values Content verification The signature as it is read from the FMSWO register must be equal to the reference signature The following pseudo code shows the algorithm to derive the reference signature FMSSTART START to FMSSTOP STOPA FOR i 0 TO 30 nextSign i f Q address 1 sign i 1 f Q address 31 sign 0 sign 10 sign 30 sign 31 sign nextSign signature32 sign All information provided in
263. ection 4 6 27 on which a falling edge has been detected Writing ones to this register clears falling edge detection Ones in this register assert an interrupt request for pins that are enabled for falling edge interrupts All edges are detected for all pins selected by the PINTSELn registers regardless of whether they are interrupt enabled Table 88 Pin interrupt falling edge register FALL address 0xA000 4020 bit description Bit Symbol Description Reset Access value 7 0 FDET Falling edge detect Bit n detects the falling edge of the 0 R W selected in PINTSELn Read 0 No falling edge has been detected on this pin since Reset or the last time a one was written to this bit Write 0 no operation Read 1 a falling edge has been detected since Reset or the last time a one was written to this bit Write 1 clear falling edge detection for this pin 31 8 Reserved Pin interrupt status register Reading this register returns ones for pin interrupts that are currently requesting an interrupt For pins identified as edge sensitive in the Interrupt Select register writing ones to this register clears both rising and falling edge detection for the pin For level sensitive pins writing ones inverts the corresponding bit in the Active level register thus switching the active level on the pin Table 89 Pin interrupt status register IST address 0xA000 4024 bit description Bit Symbol Description Reset Access val
264. elect PIOO 2 General purpose digital input output pin SWCLK PIOO 3 6 5 B O SWCLKC Serial Wire Clock SWCLK is enabled by default on TCK this pin In boundary scan mode TCK Test Clock PIOO 3 General purpose digital input output pin PIOO_4 WAKEUP 5 4 2 E O PIOO_4 General purpose digital input output pin TRST In ISP mode this is the USARTO transmit pin UO TXD In boundary scan mode TRST Test Reset This pin triggers a wake up from Deep power down mode If you need to wake up from Deep power down mode via an external pin do not assign any movable function to this pin Pull this pin HIGH externally to enter Deep power down mode Pull this pin LOW to exit Deep power down mode A LOW going pulse as short as 50 ns wakes up the part RESET PIOO 5 4 3 1 IO RESET External reset input A LOW going pulse as short as 50 ns on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 PIOO 5 General purpose digital input output pin PIOO 6 VDDCMP 18 15 1 _ 6 General purpose digital input output pin VDDCMP Alternate reference voltage for the analog comparator PIOO 7 17 14 B VO PIOO 7 General purpose digital input output pin PIOO 8 XTALIN 14 11 B O 8 General purpose digital input output pin XTALIN Input to the oscil
265. eliminary user manual Rev 1 1 24 January 2013 156 of 326 NXP Semiconductors U M1 0601 12 6 4 12 6 5 12 6 6 UM10601 Chapter 12 LPC800 Windowed Watchdog Timer WWDT Table 145 Watchdog Feed register FEED 0x4000 4008 bit description Bit Symbol Description Reset Value 7 0 FEED Feed value should be OxAA followed by 0x55 NA 31 8 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Watchdog Timer Value register The WDTV register is used to read the current value of Watchdog timer counter When reading the value of the 24 bit counter the lock and synchronization procedure takes up to 6 WDCLK cycles plus 6 PCLK cycles so the value of WDTV is older than the actual value of the timer when it s being read by the CPU Table 146 Watchdog Timer Value register TV 0x4000 400C bit description Bit Symbol Description Reset Value 23 0 COUNT Counter timer value 0x00 OOFF 31 24 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined Watchdog Timer Warning Interrupt register The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog interrupt When the watchdog timer counter matches the value defined by WARNINT an interrupt will be generated after the subsequent WDCLK A match of the watchdog timer counter to WARNINT occurs when th
266. eliminary user manual Rev 1 1 24 January 2013 163 of 326 NXP Semiconductors UM10601 Chapter 13 LPC800 Analog comparator 13 6 2 Voltage ladder register This register enables and controls the voltage ladder The fraction of the reference voltage produced by the ladder is programmable in steps of 1 31 Table 152 Voltage ladder register LAD address 0x4002 4004 bit description Bit Symbol Value Description Reset value LADEN Voltage ladder enable 0 5 1 LADSEL Voltage ladder value The reference voltage Vref depends 0 on the LADREF bit below 00000 Vss 00001 1 x Vref 31 00010 2 x Vref 31 11111 Vref 6 LADREF Selects the reference voltage Vref for the voltage ladder 0 0 Supply pin Vpp 1 VDDCMP pin 31 77 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 164 of 326 UM10601 Chapter 14 LPC800 Self wake up timer WKT Rev 1 1 24 January 2013 Preliminary user manual 14 1 How to read this chapter 14 2 Features The self wake up timer is available on all LPC800 parts 32 bit loadable down counter Counter starts automatically when a count value is loaded Time out generates an interrupt wake up request The WKT resides in a separate always on power domain The WKT supports two clock sources One clock source originates from the always on power dom
267. embles characters as they are received after which they are passed to the receiver buffer register to await access by the CPU The USART transmitter block accepts data written by the CPU and buffers the data in the transmit holding register When the transmitter is available the transmit shift register takes that data formats it and serializes it to the serial output Un TXD The Baud Rate Generator block divides the incoming clock to create a 16x baud rate clock in the standard asynchronous operating mode The BRG clock input source is the shared Fractional Rate Generator that runs from the common USART peripheral clock U PCLK In synchronous slave mode data is transmitted and received using the serial clock directly In synchronous master mode data is transmitted and received using the baud rate clock without division Status information from the transmitter and receiver is saved and provided via the Stat register Many of the status flags are able to generate interrupts as selected by software Remark The fractional value and the USART peripheral clock are shared between all USARTs All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 172 of 326 NXP Semiconductors U M1 0601 Chapter 15 LPC800 USARTO 1 2 SYSCON block system clock U_PCLK Transmitter main clock UARTCLKDIV FRG H
268. ence Table 99 Table 100 Table 100 Table 100 Table 100 Table 101 Table 101 Table 101 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 212 of 326 NXP Semiconductors UM10601 17 5 General description Chapter 17 LPC800 SPI0 1 1 Fig 33 Tx Shift Register SPIn TXDAT amp State Machine Tx interrupts SPI interrupt Interrupt L control General controls amp format configurations 1 2 interrupts Rx Shift Register RXDAT i amp State Machine SSEL pin RxSSEL SSA SSD levels RxRdy RxOv SPOL DivVal SSEL field internal SPI_PCLK T clock s Clock divider SSEL Includes CPOL CPHA LSBF FLEN master enable transfer delay frame delay pre delay post delay SOT EOT EOF RXIgnore individual interrupt enables SPI block diagram 17 6 Register description UM10601 The Reset Value reflects the data stored in used bits only It does not include reserved bits content Table 188 Register overview SPI base address 0x4005 8000 SPIO and 0x4008 C000 SPI1 Name Access Offset Description Reset Reference value CFG R W 0x000 SPI Configuration register 0 Table 189 DLY R W 0x004 SPI Delay register 0 Table 190 STAT R W 0x008 SPI Status
269. ent 4 control register 0x0000 0000 Table 130 EV5 STATE R W 0x328 SCT event 5 state register 0x0000 0000 Table 129 EV5 CTRL R W 0x32C SCT event 5 control register 0x0000 0000 Table 130 OUTO SET R W 0x500 SCT output 0 set register 0x0000 0000 Table 131 OUTO_CLR R W 0x504 SCT output 0 clear register 0x0000 0000 Table 132 OUT1_SET R W 0x508 SCT output 1 set register 0x0000 0000 Table 131 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 120 of 326 NXP Semiconductors UM10601 Chapter 10 LPC800 State Configurable Timer SCT Table 107 Register overview State Configurable Timer base address 0x5000 4000 continued Name OUT1 CLR OUT2 SET OUT2 CLR OUTS SET OUT3 CLR Access Address Description Reset value Reference offset R W 0x50C SCT output 1 clear register 0x0000 0000 Table 132 R W 0x510 SCT output 2 set register 0x0000 0000 Table 131 R W 0x514 SCT output 2 clear register 0x0000 0000 Table 132 R W 0x518 SCT output 3 set register 0x0000 0000 Table 131 R W 0x51C SCT output 3 clear register 0x0000 0000 Table 132 10 6 1 SCT configuration register This register configures the overall operation of the SCT Write to this register before any other registers Table 108 SCT configuration register CONFIG address 0x5000 4000 bit description Bit 2 1 6 3 7 8 UM10601 Symbol UNIF
270. ent is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 37 of 326 NXP Semiconductors U M1 0601 Chapter 4 LPC800 System configuration SYSCON Table 38 Device ID register DEVICE ID address 0x4004 83F4 bit description Bit Symbol Description Reset value 31 0 DEVICEID 0 0000 8100 LPC810M021FN8 part dependent 0x0000 8110 LPC811M001FDH16 0x0000 8120 LPC812M101FDH16 0x0000 8121 LPC812M101FD20 0x0000 8122 LPC812M101FDH20 4 7 Functional description 4 7 1 System PLL functional description The LPC800 uses the system PLL to create the clocks for the core and peripherals irc_osc_clk CLKIN SYSPLLCLKSEL sys_osc_clk FCLKIN die gt De FCCO pd PSEL lt 1 0 gt B o LOCK b 2 I gt LOCK e DETECT FCLKOUT analog section pd d cd Fig 4 System PLL block diagram M As MSEL lt 4 0 gt UM10601 The block diagram of this PLL is shown in Figure 4 The input frequency range is 10 MHz to 25 MHz The input clock is fed directly to the Phase Frequency Detector PFD This block compares the phase and frequency of its inputs and generates a control signal when phase and or frequency do not match The loop filter filters these control signals and drives the current controlled oscillator CCO which gene
271. ep power down mode not entered Write No effect 1 Read Deep power down mode entered Write Clear the Deep power down flag 31 12 Reserved Do not write ones to this bit 0 General purpose registers 0 to 3 The general purpose registers retain data through the Deep power down mode when power is still applied to the Vpp pin but the chip has entered Deep power down mode Only a cold boot when all power has been completely removed from the chip will reset the general purpose registers Table 44 General purpose registers 0 to 3 GPREG 0 3 address 0x4002 0004 GPREGO to 0x4002 0010 GPREG3 bit description Bit Symbol Description Reset value 31 0 GPDATA Data retained during Deep power down mode 0x0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 44 of 326 NXP Semiconductors U M1 0601 5 6 3 Chapter 5 LPC800 Reduced power modes and Power Management Deep power down control register The Deep power down control register controls the low power oscillator that can be used by the self wake up timer to wake up from Deep power down mode In addition this register configures the functionality of the WAKEUP pin pin PIOO 4 The bits in the register not used for deep power down control bits 31 4 can be used for storing additional data which are retained in Deep power down mode in the s
272. er SYSAHBCLKCTRL address 0x4004 8080 bit description continued Bit Symbol Value Description Reset value 19 ACMP Enables clock to analog comparator 0 0 Disable 1 Enable 31 20 Reserved 4 6 14 USART clock divider register This register configures the clock for the fractional baud rate generator and all USARTs The UART clock can be disabled by setting the DIV field to zero this is the default setting Table 19 USART clock divider register UARTCLKDIV address 0x4004 8094 bit description Bit Symbol Description Reset value 7 0 DIV USART fractional baud rate generator clock divider values 0 0 Clock disabled 1 Divide by 1 to 255 Divide by 255 31 8 Reserved 4 6 15 CLKOUT clock source select register This register selects the signal visible on the CLKOUT pin Any oscillator or the main clock can be selected Bit 0 of the CLKOUTUEN register see Section 4 6 16 must be toggled from 0 to 1 for the update to take effect Table 20 CLKOUT clock source select register CLKOUTSEL address 0x4004 80E0 bit description Bit Symbol Value Description Reset value 1 0 SEL CLKOUT clock source 0 0x0 IRC oscillator 0 1 Crystal oscillator SYSOSC 0x2 Watchdog oscillator 0x3 Main clock 31 2 Reserved 0 4 6 16 CLKOUT clock source update enable register This register updates the clock source of the CLKOUT pin with the new clock after the CLKOUTSEL register has been written to In orde
273. er 0x0000 FFFF 203 SUM RO 0x008 CRC checksum register 0x0000 FFFF 204 WR_DATA WO 0x008 CRC data register Table 205 CRC mode register Table 202 CRC mode register MODE address 0x5000 0000 bit description Bit Symbol Description Reset value 110 CRC POLY CRC polynom 00 1X CRC 32 polynomial 01 CRC 16 polynomial 00 CRC CCITT polynomial 2 BIT_RVS_WR Data bit order 0 1 Bit order reverse for CRC_WR_DATA per byte 02 No bit order reverse for CRC_WR_DATA per byte 3 CMPL_WR Data complement 0 1 1 s complement for CRC_WR_DATA 0 No 1 s complement for CRC_WR_DATA 4 BIT_RVS_SUM CRC sum bit order 0 1 Bit order reverse for CRC_SUM 0 No bit order reverse for CRC_SUM 5 CMPL_SUM CRC sum complement 0 1 1 s complement for CRC_SUM OzNo 1 s complement for CRC_SUM 31 6 Reserved Always 0 when read 0x0000000 CRC seed register Table 203 CRC seed register SEED address 0x5000 0004 bit description Bit Symbol Description Reset value 31 0 CRC_SEED A write access to this register will load CRC seed value to 0 0000 FFFF CRC_SUM register with selected bit order and 1 s complement pre processes Remark A write access to this register will overrule the CRC calculation in progresses CRC checksum register This register is a Read only register containing the most recent checksum The read request to this register is automatically delayed by a finite number of wait states until the results are valid
274. er output For each SCT output select which events set or clear this output More than one event can change the output and each event can change multiple outputs 3 Define how each event affects the counter Set the corresponding event bit in the LIMIT register for the event to set an upper limit for the counter When limit event occurs in unidirectional mode the counter is cleared to zero and begins counting up on the next clock edge When a limit event occurs in bidirectional mode the counter begins to count down from the current value on the next clock edge Set the corresponding event bit in the HALT register for the event to halt the counter If the counter is halted it stops counting and no new events can occur The counter operation can only be restored by clearing the HALT L and or the HALT H bits in the CTRL register Set the corresponding event bit in the STOP register for the event to stop the counter If the counter is stopped it stops counting However an event that is configured as a transition on an input output can restart the counter Set the corresponding event bit in the START register for the event to restart the counting Only events that are defined by an input changing can be used to restart the counter 4 Define which events contribute to the SCT interrupt UM10601 Set the corresponding event bit in the EVEN and the EVFLAG registers to enable the event to contribute to the SCT interrupt All
275. er profile API ROM driver For a simplified clock configuration scheme see Figure 44 For more details see Figure 3 ParamO0 main clock The main clock is the clock rate the microcontroller uses to source the system s and the peripherals clock It is configured by either a successful execution of the clocking routine call or a similar code provided by the user This operand must be an integer between 1 to 50 MHz inclusive If a value out of this range is supplied set power returns PWR INVALID FREQ and does not change the power control system Param1 mode The input parameter mode Param 1 specifies one of four available power settings If an illegal selection is provided set power returns PWR INVALID MODE and does not change the power control system PWR DEFAULT keeps the device in a baseline power setting similar to its reset state PWR CPU PERFORMANCE configures the microcontroller so that it can provide more processing capability to the application CPU performance is 3096 better than the default option PWR EFFICIENCY setting was designed to find a balance between active current and the CPU s ability to execute code and process data In this mode the device outperforms the default mode both in terms of providing higher CPU performance and lowering active current PWR LOW CURRENT is intended for those solutions that focus on lowering power consumption rather than CPU performance Param2 system clock The system clock is the c
276. er than read only flags may be cleared by writing ones to corresponding bits of STAT Interrupt status flags that are read only and cannot be cleared by software can be masked using the INTENCLR register see Table 162 The error flags for received noise parity error framing error and overrun are set immediately upon detection and remain set until cleared by software action in STAT Table 160 USART Status register STAT address 0x4006 4008 USARTO 0x4006 8008 USART1 0x4006 C008 USART2 bit description Bit Symbol Description Reset Access value 1 0 RXRDY Receiver Ready flag When 1 indicates that data is available to be read from 0 RO the receiver buffer Cleared after a read of the RXDATA or RXDATASTAT registers 1 RXIDLE Receiver Idle When 0 indicates that the receiver is currently in the process of 1 RO receiving data When 1 indicates that the receiver is not currently in the process of receiving data 2 TXRDY Transmitter Ready flag When 1 this bit indicates that data may be written to 1 RO the transmit buffer Previous data may still be in the process of being transmitted Cleared when data is written to TXDATA Set when the data is moved from the transmit buffer to the transmit shift register 3 TXIDLE Transmitter Idle When 0 indicates that the transmitter is currently in the 1 RO process of sending data When 1 indicate that the transmitter is not currently in the process of sending data 4 CTS This bit reflec
277. er when it is available and another character may then be written to TXDATA Table 165 USART Transmitter Data Register TXDATA address 0x4006 401C USARTO 0x4006 801C USART1 0x4006 1 USART2 bit description Bit Symbol Description Reset Value 8 0 TXDAT Writing to the USART Transmit Data Register causes the data to be 0 transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met CTS low if CTSEN bit 1 TXDIS bit 0 31 9 Reserved Only zero should be written NA UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 182 of 326 NXP Semiconductors U M1 0601 15 6 9 15 6 10 Chapter 15 LPC800 USARTO 1 2 USART Baud Rate Generator register The Baud Rate Generator is a simple 16 bit integer divider controlled by the BRG register The BRG register contains the value used to divide the base clock in order to produce the clock used for USART internal operations A 16 bit value allows producing standard baud rates from 300 baud and lower at the highest frequency of the device up to 921 600 baud from a base clock as low as 14 7456 MHz Typically the baud rate clock is 16 times the actual baud rate This overclocking allows for centering the data sampling time within a bit cell and for noise reduction and detection by taking th
278. erate identically for reading and writing Applications in which interrupts can result in Masked GPIO operation or in task switching among tasks that do Masked GPIO operation must treat code that uses the Mask register as a protected restricted region This can be done by interrupt disabling or by using a semaphore The simpler way to protect a block of code that uses a MASK register is to disable interrupts before setting the MASK register and re enable them after the last operation that uses the MPORT or MASK register More efficiently software can dedicate a semaphore to the MASK registers and set capture the semaphore controlling exclusive use of the MASK registers before setting the MASK registers and release the semaphore after the last operation that uses the MPORT or MASK registers Recommended practices The following lists some recommended uses for using the GPIO port registers For initial setup after Reset or re initialization write the PORT registers To change the state of one pin write a Byte Pin or Word Pin register To change the state of multiple pins at a time write the SET and or CLR registers To change the state of multiple pins in a tightly controlled environment like a software state machine consider using the NOT register This can require less write operations than SET and CLR To read the state of one pin read a Byte Pin or Word Pin register To make a decision based on multiple pins read a
279. ers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 307 of 326 UM10601 Chapter 27 LPC800 Appendix Rev 1 1 24 January 2013 27 1 How to read this chapter Preliminary user manual This chapter summarizes the ARM Cortex M0 instructions The instruction set is identical for all LPC800 parts 27 2 General description The processor implements the ARMv6 M Thumb instruction set including a number of 32 bit instructions that use Thumb 2 technology The ARMv6 M instruction set contains all of the 16 bit Thumb instructions from ARMv7 M excluding CBZ CBNZ and IT the 32 bit Thumb instructions BL DMB DSB ISB MRS and MSR Table 287 shows the Cortex M0 instructions and their cycle counts The cycle counts are based on a system with zero wait states Table 287 Cortex MO instruction summary Operation Move Add Subtract Multiply Compare UM10601 Description 8 bit immediate Lo to Lo Any to Any Any to PC 3 bit immediate All registers Lo Any to Any Any to PC 8 bit immediate With carry Immediate to SP Form address from SP Form address from PC Lo and Lo 3 bit immediate 8 bit immediate With carry Immediate from SP Negate Multiply Compare Negative Immediate Assembler MOVS Rd lt imm gt MOVS Rd Rm MOV Rd Rm MOV PC Rm ADDS Rd Rn lt imm gt ADDS Rd Rn Rm ADD Rd Rd Rm ADD PC PC Rm ADDS
280. erved the value read from a reserved bit is not defined NA 13 FRAMERR Framing Error status flag This bit is valid when there is a character 0 to be read in the RXDATA register and reflects the status of that character This bit will set when the character in RXDAT was received with a missing stop bit at the expected location This could be an indication of a baud rate or configuration mismatch with the transmitting source All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 181 of 326 NXP Semiconductors U M1 0601 15 6 8 Chapter 15 LPC800 USARTO 1 2 Table 164 USART Receiver Data with Status register RXDATASTAT address 0x4006 4018 USARTO 0x4006 8018 USART1 0x4006 C018 USART2 bit description Bit Symbol Description Reset Value 14 PARITYERR Parity Error status flag This bit is valid when there is a character to 0 be read in the RXDATA register and reflects the status of that character This bit will be set when a parity error is detected in a received character 15 RXNOISE Received Noise flag See description of the RxNoiselnt bit in 0 Table 160 31 16 Reserved the value read from a reserved bit is not defined NA USART Transmitter Data Register The TXDATA register is written in order to send data via the USART transmitter That data will be transferred to the transmit shift regist
281. es as a Reload register when the register is used as a Match register Section 10 6 20 or as a Capture Control register when the register is used as a capture register Section 10 6 21 REGMODE H is used only when the UNIFY bit is O UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 127 of 326 NXP Semiconductors U M1 0601 10 6 11 10 6 12 Chapter 10 LPC800 State Configurable Timer SCT Table 117 SCT match capture registers mode register REGMODE address 0x5000 404C bit description Bit Symbol Description Reset value 4 0 REGMOD L Each bit controls one pair of match capture registers register 0 0 bit 0 register 1 bit 1 register 4 bit 4 0 registers operate as match registers 1 registers operate as capture registers 15 5 Reserved 20 16 REGMOD Each bit controls one pair of match capture registers register 0 0 bit 16 register 1 bit 17 register 4 bit 20 0 registers operate as match registers 1 registers operate as capture registers 31 21 Reserved SCT output register The SCT supports 4 outputs each of which has a corresponding bit in this register Software can write to any of the output registers when both counters are halted to control the outputs directly Writing to this register when either counter is stopped or running does not
282. escription Bit Symbol Value Description Reset value 0 IRCOUT PD IRC oscillator output wake up configuration 0 0 Powered 1 Powered down 1 PD IRC oscillator power down wake up configuration 0 0 Powered 1 Powered down 2 FLASH PD Flash wake up configuration 0 0 Powered 1 Powered down 3 BOD PD BOD wake up configuration 0 0 Powered 1 Powered down 4 Reserved 1 5 SYSOSC PD Crystal oscillator wake up configuration 1 0 Powered 1 Powered down 6 WDTOSC PD Watchdog oscillator wake up configuration 1 Changing this bit to powered down has no effect when the LOCK bit in the WWDT MOD register is set In this case the watchdog oscillator is always running 0 Powered 1 Powered down 7 SYSPLL PD System PLL wake up configuration 1 0 Powered 1 Powered down 11 8 Reserved Always write these bits as 0b1101 0b1101 1442 Reserved Always write these bits as 0b110 0b110 15 ACMP Analog comparator wake up configuration 1 0 Powered 1 Powered down 31 16 Reserved 0 Power configuration register The PDRUNCFG register controls the power to the various analog blocks This register can be written to at any time while the chip is running and a write will take effect immediately with the exception of the power down signal to the IRC To avoid glitches when powering down the IRC the IRC clock is automatically switched off at a clean point Therefore for the IRC a delay is possible before the power down state takes effect All information p
283. eserved Preliminary user manual Rev 1 1 24 January 2013 272 of 326 NXP Semiconductors U M1 0601 Chapter 22 LPC800 Power profile API ROM driver Fig 45 Power profiles usage using power profiles and changing system clock current clock new clock new mode use power routine call to change mode to DEFAULT use either clocking routine call or custom code to change system clock from current clockto new clock use power routine call to change mode to new mode UM10601 Table 251 set_power routine Routine set_power Input main clock in MHz Param1 mode PWR DEFAULT CPU PERFORMANCE PWR_ EFFICIENCY PWR LOW CURRENT 2 system clock in MHz Result Result0 CMD SUCCESS INVALID FREQ PWR INVALID MODE Th e following definitions are needed for set power routine calls set power mode options ine PWR DEFAULT 0 ine PWR CPU PERFORMANCE 1 ine PWR EFFICIENCY 2 ine PWR LOW CURRENT 3 et power result options ine PWR CMD SUCCESS 0 ine PWR_INVALID_FREQ 1 fine PWR INVALID MODE 2 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 273 of 326 NXP Semiconductors U M1 0601 22 4 2 1 22 4 2 2 22 4 2 3 Chapter 22 LPC800 Pow
284. eserved Preliminary user manual Rev 1 1 24 January 2013 16 of 326 NXP Semiconductors UM10601 4 5 3 4 5 4 Chapter 4 LPC800 System configuration SYSCON Configuration of reduced power modes The system control block configures analog blocks that can remain running in the reduced power modes the BOD and the watchdog oscillator for safe operation and enables various interrupts to wake up the chip when the internal clocks are shut down in Deep sleep and Power down modes For details see the following registers Section 4 6 32 Power configuration register Section 4 6 29 Start logic 1 interrupt wake up enable register Reset and interrupt control The peripheral reset control register in the system control register allows to assert and release individual peripheral resets See Table 7 Up to eight external pin interrupts can be assigned to any digital pin in the system control block see Section 4 6 27 Pin interrupt select registers 4 6 Register description All system control block registers reside on word address boundaries Details of the registers appear in the description of each function Reset values describe the content of the registers after the boot loader has executed All address offsets not shown in Table 5 are reserved and should not be written to Table 5 Register overview System configuration base address 0x4004 8000 Name Access Offset Description Reset value Referen
285. eset 2 UARTFRG RST N USART fractional baud rate generator 1 UARTFRG reset control 0 Assert the UARTFRG reset 1 Clear the UARTFRG reset UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 19 of 326 NXP Semiconductors U M1 0601 4 6 3 UM10601 Chapter 4 LPC800 System configuration SYSCON Table 7 Peripheral reset control register PRESETCTRL address 0 4004 8004 bit description Bit Symbol Value Description Reset value 3 USARTO_RST_N USARTO reset control 1 0 Assert the USARTO reset 1 Clear the USARTO reset 4 UART1_RST_N USART1 reset control 1 0 Assert the USART reset 1 Clear the USART1 reset 5 UART2_RST_N USART2 reset control 1 0 Assert the USART2 reset 1 Clear the USART2 reset 6 l2C N 12 reset control 1 0 Assert the 12C reset 1 Clear the 12 reset 7 MRT RST N Multi rate timer MRT reset control 1 0 Assert the MRT reset 1 Clear the MRT reset 8 SCT RST N SCT reset control 1 0 Assert the SCT reset 1 Clear the SCT reset 9 WKT RST N Self wake up timer WKT reset control 1 0 Assert the WKT reset 1 Clear the WKT reset 10 GPIO RST N GPIO and GPIO pin interrupt reset control 1 0 Assert the GPIO reset 1 Clear the GPIO reset 11 FLASH RST N Flash controller reset control 1 0 Assert the flash controller reset 1 Clear the flash controller reset 12 ACMP RST N Analog
286. est low rising falling state Data is captured on the following edge 1 0 2 Same as mode 0 with SCK inverted high rising falling 1 1 3 as mode 1 with SCK inverted high falling rising CPHA 0 Mode 0 CPOL 0 SCK lt gt 1 Mode 1 0 SCK Data frame Fig 34 Basic SPI operating modes UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 225 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 17 7 2 Frame delays Several delays can be specified for SPI frames These include Pre delay delay after SSEL is asserted before data clocking begins Post delay delay at the end of a data frame before SSEL is deasserted Frame delay delay between data frames when SSEL is not deasserted Transfer delay minimum duration of SSEL in the deasserted state between transfers 17 7 2 1 Pre delay and Post delay Pre delay and Post delay are illustrated by the examples in Figure 35 The Pre delay value controls the amount of time between SSEL being asserted and the beginning of the subsequent data frame The Post delay value controls the amount of time between the end of a data frame and the deassertion of SSEL Pre and post delay CPHA 0 Pre delay 2 Post delay 1 Mode 0 CPOL 0 SCK Mode 2
287. etely supports the I C bus specification up to Fast Mode Plus up to 1 MHz I C When the I C function is connected to standard pins that are set to open drain mode a functional I2C bus can be used in this way but some aspects of the I2C bus specification may not be met This can have an impact on the bus speed noise filtering and the capability of powering down the device without affecting the bus See Section 9 3 1 Connect an internal signal to a package pin to assign the I2C pins to any pin on the LPC800 package Table 168 I2C bus pin description Function Type Pin Description SWM register Reference 1260 SCL I O any use pin PIOO 10 or PIOO 11 for 12 serial clock PINASSIGN8 Table 104 compatibility with the full IC bus specification I2CO SDA I O any use pin PIOO 10 or PIOO 11 for I2CO0 serial data PINASSIGN7 Table 103 compatibility with the full IC bus specification 16 5 General description The architecture of the I2C bus interface is shown in Figure 31 Monitor function eneration function Fa 9 function i I2C0_SDA v CFG LOOP Fig 31 12C block diagram 16 6 Register description The register functions can be grouped as follows UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 189 of 326 NXP Semiconductors UM10601
288. evel or rising edge interrupt clear register For each of the 8 pin interrupts selected in the PINTSEL n registers see Section 4 6 27 one bit in the CIENR register clears the corresponding bit in the IENR register depending on the pin interrupt mode configured in the ISEL register f the pin interrupt mode is edge sensitive PMODE 0 the rising edge interrupt is cleared f the pin interrupt mode is level sensitive PMODE 1 the level interrupt is cleared All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 87 of 326 NXP Semiconductors U M1 0601 8 6 5 8 6 6 UM10601 Chapter 8 LPC800 Pin interrupts pattern match engine Table 83 Pin interrupt level or rising edge interrupt clear register CIENR address 0xA000 400C bit description Bit Symbol Description Reset Access value 7 0 CENRL Ones written to this address clear bits in the IENR thus NA WO disabling the interrupts Bit n clears bit n in the IENR register 0 No operation 1 Disable rising edge or level interrupt 31 8 Reserved Pin interrupt active level or falling edge interrupt enable register For each of the 8 pin interrupts selected in the PINTSELn registers see Section 4 6 27 one bit in the IENF register enables the falling edge interrupt or the configures the level sensitivity depending on the pin inter
289. f sending data 31 9 Reserved Read value is undefined only zero should be written NA NA 1 RO Read only W1 write 1 to clear 17 6 4 SPI Interrupt Enable read and Set register The INTENSET register is used to enable various SPI interrupt sources Enable bits in INTENSET are mapped in locations that correspond to the flags in the STAT register The complete set of interrupt enables may be read from this register Writing ones to implemented bits in this register causes those bits to be set The INTENCLR register is used to clear bits in this register See Table 191 for details of the interrupts Table 192 SPI Interrupt Enable read and Set register INTENSET addresses 0x4005 800C SPIO 0x4005 CO0C SPI1 bit description Bit Symbol Value Description Reset value 0 RXRDYEN Determines whether an interrupt occurs when receiver data is available 0 0 No interrupt will be generated when receiver data is available An interrupt will be generated when receiver data is available in the RXDAT register 1 TXRDYEN Determines whether an interrupt occurs when the transmitter holding register is 0 available 0 No interrupt will be generated when the transmitter holding register is available An interrupt will be generated when data may be written to TXDAT 2 RXOVEN Determines whether an interrupt occurs when a receiver overrun occurs This happens 0 in slave mode when there is a need for the receiver to move newly received data
290. ferent is if CLKMODE 2 in the CONFIG register Table 116 SCT input register INPUT address 0x5000 4048 bit description Bit Symbol Description Reset value 0 AINO Real time status of input 0 pin 1 AIN1 Real time status of input 1 pin 2 AIN2 Real time status of input 2 pin 3 AIN3 Real time status of input 3 pin 15 4 Reserved 16 SINO Input 0 state synchronized to the SCT clock 17 SIN1 Input 1 state synchronized to the SCT clock 18 SIN2 Input 2 state synchronized to the SCT clock 19 SIN3 Input 3 state synchronized to the SCT clock 31 20 Reserved 10 6 10 SCT match capture registers mode register If UNIFY 1 in the CONFIG register only the _L bits of this register are used The L bits control whether each set of match capture registers operates as unified 32 bit capture match registers If UNIFY 0 in the CONFIG register this register can be written to as two registers REGMODE L and REGMODE Both the L and registers can be read or written individually or in a single 32 bit read or write operation The L bits registers control the L match capture registers and the H bits registers control the match capture registers The SCT contains 5 Match Capture register pairs The Register Mode register selects whether each register pair acts as a Match register see Section 10 6 18 or as a Capture register see Section 10 6 19 Each Match Capture register has an accompanying register which serv
291. figuration IOCON Table 56 11 register PIOO 11 address 0 4004 401C bit description Bit Symbol Value Description Reset value 5 0 Reserved 0 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin 7 s 9 8 I2ZCMODE reads as 0 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 Reserved 1 Selects I2C mode 00 Select Standard mode I2CMODE 00 default or Standard I O functionality IZCMODE 01 if the pin function is GPIO FUNC 000 0x0 Standard mode Fast mode 12 0x1 Standard I O functionality 0 2 Fast mode Plus I2C 0x3 Reserved 10 Reserved 12 11 S MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 Select peripheral clock divider for input filter sampling 0 clock Value 0 7 is reserved 0x0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS3 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 63 of 326 NXP Semiconductors UM10601 6 5 9 PIOO 10 register Ch
292. formation provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 283 of 326 NXP Semiconductors UM10601 23 4 14 23 4 15 23 4 16 23 4 17 UM10601 Chapter 23 LPC800 I2C bus ROM API Table 265 12C Get Memory Size Routine I2C Get Memory Size Input parameter None Return uint32 Description Returns the number of bytes in SRAM needed by the 12C driver I2C Setup Table 266 12C Setup Routine 12C Setup Prototype I2C HANDLE T i2c setup i2c base start of ram Input parameter Return Description I2C base addr unint32 variable Base address for I2C peripherals Start of ram unint32 pointer Pointer to allocated SRAM I2C Handle Returns a handle to the allocated SRAM area 12C Set Bit Rate Table 267 12C Set Bit Rate Routine Prototype Input parameter Return Description 12C Set Bit Rate ErrorCode t i2c set bitrate I2C HANDLE T P clk in hz bitrate in bps I2C HANDLE T Handle to the allocated SRAM area P clk in hz unint32 variable The Peripheral Clock in Hz Bitrate in bps unint32 variable Requested I2C operating frequency in Hz ErrorCode Configures the I2C duty cycle registers and SCLL 12C Get Firmware Version Table 268 12 Get Firmware Version Routine Prototype Input parameter Return Description I2C Get Firmware Version
293. from being reloaded from their 0 respective reload registers Software can write to set or clear this bit at any time This bit is not used when the UNIFY bit is set All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 121 of 326 NXP Semiconductors U M1 0601 Chapter 10 LPC800 State Configurable Timer SCT Table 108 SCT configuration register CONFIG address 0x5000 4000 bit description continued Bit Symbol Value Description Reset value 16 9 INSYNC Synchronization for input N bit 9 input 0 bit 10 input 1 bit 16 2 input 7 1 A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock before it is used to create an event If an input is synchronous to the SCT clock keep its bit 0 for faster response When the CLKMODE field is 1x the bit in this field corresponding to the input selected by the CKSEL field is not used 17 AUTOLIMIT L A one in this bit causes a match on match register 0 to be treated as a de facto LIMIT condition without the need to define an associated event As with any LIMIT event this automatic limit causes the counter to be cleared to zero in uni directional mode or to change the direction of count in bi directional mode Software can write to set or clear this bit at any time This bit applies to both the higher and lower registe
294. fset Byte register offset SP relative Multiple Push Push with link register Pop Pop and return All information provided in this document is subject to legal disclaimers Assembler ANDS Rd Rd Rm EORS Rd Rd Rm ORRS Rd Rd Rm BICS Rd Rd Rm MVNS Rd Rm TST Rn Rm LSLS Rd Rm lt shift gt LSLS Rd Rd Rs LSRS Rd Rm lt shift gt LSRS Rd Rd Rs ASRS Rd Rm lt shift gt ASRS Rd Rd Rs RORS Rd Rd Rs LDR Rd Rn lt imm gt LDRH Rd Rn lt imm gt LDRB Rd Rn lt imm gt LDR Rd Rn Rm LDRH Rd Rn Rm LDRSH Rd Rn Rm LDRB Rd Rn Rm LDRSB Rd Rn Rm LDR Rd label LDR Rd SP lt imm gt LDM Rn lt loreglist gt LDM Rn lt loreglist gt STR Rd Rn lt imm gt STRH Rd Rn lt imm gt STRB Rd Rn lt imm gt STR Rd Rn Rm STRH Rd Rn Rm STRB Rd Rn Rm STR Rd SP lt imm gt STM Ral lt loreglist gt PUSH lt loreglist gt PUSH lt loreglist gt LR POP lt loreglist gt POP lt loreglist gt PC Cycles 2 or 122 2 or 1121 2 or 122 2 or 122 2 or 1121 2 or 122 2 or 122 2 or 1121 2 or 122 2 or 1121 1 NEI 1 NUI 2 or 122 2 or 122 2 or 121 2 or 122 2 or 122 2 or 1121 2 or 12 1 1 NUI 1 1 3 NISI NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 309 of 326 NXP Semiconductors UM10601 Table 287 Cortex MO i
295. functions to the same pin See Table 106 The selected SCT input can now monitor the ACMP_O function All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 159 of 326 NXP Semiconductors U M1 0601 Chapter 13 LPC800 Analog comparator 13 4 Pin description The analog comparator reference voltage the inputs and the output are assigned to external pins through the switch matrix You can assign the analog comparator output to any pin on the package that is not a supply or ground pin The comparator inputs and the reference voltage are fixed pin functions that must be enabled through the switch matrix and can only be assigned to special pins on the package See Section 9 3 1 Connect an internal signal to a package pin to assign the analog comparator output to any pin on the LPC800 package See Section 9 3 2 to enable the analog comparator inputs and the reference voltage input Table 149 Analog comparator pin description Function Type Pin Description SWM register Reference H PIOO 0 ACMP 11 Comparator input 1 PINENABLEO Section 9 5 10 ACMP 12 PIOO 0 ACMP I2 CLKIN Comparator input 2 Disable the CLKIN PINENABLEO Section 9 5 10 function in the PINENABLEO register Comparator output PINASSIGN8 Section 9 5 9 VDDCMP PIOO_6 VDDCMP External reference voltage source for PIN
296. g 19 Output slice i 10 7 5 Interrupt generation The SCT generates one interrupt to the NVIC Events gt Enable Flags register LOI 7 interrupt ___ Conflict Conflict Conflict events Flags Enable ist register COS Fig 20 SCT interrupt generation UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 137 of 326 NXP Semiconductors U M1 0601 10 7 6 10 7 7 UM10601 Chapter 10 LPC800 State Configurable Timer SCT Clearing the prescaler When enabled by a non zero PRE field in the Control register the prescaler acts as a clock divider for the counter like a fractional part of the counter value The prescaler is cleared whenever the counter is cleared or loaded for any of the following reasons Hardware reset e Software writing to the counter register Software writing a 1 to the CLRCTR bit in the control register an event selected by a 1 in the counter limit register when BIDIR 0 When BIDIR is 0 a limit event caused by an I O signal can clear a non zero prescaler However a limit event caused by a Match only clears a non zero prescaler in one special case as described Section 10 7 7 A limit event when BIDIR is 1 does not clear the prescaler Rather it clears the DOWN
297. g register 0x0000 0000 Table 122 CONEN R W OxOF8 SCT conflict enable register 0x0000 0000 Table 123 CONFLAG R W OxOFC SCT conflict flag register 0x0000 0000 Table 124 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 119 of 326 NXP Semiconductors UM10601 Chapter 10 LPC800 State Configurable Timer SCT Table 107 Register overview State Configurable Timer base address 0x5000 4000 continued Name Access Address Description Reset value Reference offset to MATCH4 R W 0x100 to SCT match value register of match channels 0 to 0 0000 0000 Table 124 0x110 4 REGMODO to REGMODE4 0 MATCH_LO to R W 0x100 to SCT match value register of match channels 010 Table 124 MATCH L4 0x110 4 low counter 16 bit REGMODO L to REGMODE4 L 0 MATCH_HO to R W 0x102 to SCT match value register of match channels 0 to Table 124 MATCH H4 0x112 4 high counter 16 bit REGMODO H to REGMODE4_H 0 to CAP4 0x100 to SCT capture register of capture channel 0 to 4 0x0000 0000 Table 126 0x110 REGMODO to REGMODE4 1 CAP_LO to CAP_L4 0 100 SCT capture register of capture channel 0 to 4 Table 126 0x110 low counter 16 bit REGMODO L to REGMODE4 L 1 CAP H4 0x102 to SCT capture register of capture channel 0 to 4 Table 126 0x13E high counter 16 bit REGMODO to REGMODE4 1 MATCHRELO
298. g with the data For details on the slave select process see Section 17 7 4 Table 194 SPI Receiver Data register RXDAT addresses 0x4005 8014 SPIO 0x4005 C014 SPI1 bit description Bit Symbol Description Reset value 15 0 RXDAT Receiver Data This contains the next piece of received data undefined The number of bits that are used depends on the FLen setting in TXCTL TXDATCTL 16 RXSSELN Slave Select for receive This field allows the state ofthe SSEL undefined pin to be saved along with received data The value will reflect the SSEL pin for both master and slave operation A zero indicates that a slave select is active The actual polarity of each slave select pin is configured by the related SPOL bit in CFG 19 17 Reserved 20 SOT Start of Transfer flag This flag will be 1 if this is the first frame after SSEL went from deasserted to asserted i e any previous transfer has ended This information can be used to identify the first piece of data in cases where the frame length is greater than 16 bit 31 21 Reserved the value read from a reserved bit is not defined NA UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 220 of 326 NXP Semiconductors U M1 0601 17 6 7 Chapter 17 LPC800 SPI0 1 SPI Transmitter Data and Control register The TXDATCTL register provides
299. generated when the INTVALn register is written All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 144 of 326 NXP Semiconductors UM10601 11 6 Register description Chapter 11 LPC800 Multi Rate Timer MRT 11 5 2 One shot interrupt mode The one shot interrupt generates one interrupt after a one time count With this mode you can generate a single interrupt at any point This mode can be used to introduce a specific delay in a software task When the timer is in the idle state writing a non zero value IVALUE to the INTVALn register immediately loads the time interval value IVALUE 1 and the timer starts to count down When the timer reaches 0 an interrupt is generated and the timer stops and enters the idle state While the timer is running in the one shot interrupt mode you can perform the following actions Update the INTVALn register with a new time interval value gt 0 and set the LOAD bit to 1 The timer immediately reloads the new time interval and starts counting down from the new value No interrupt is generated when the TIME INTVALn register is updated Write a 0 to the INTVALn register and set the LOAD bit to 1 The timer immediately stops counting and moves to the idle state No interrupt is generated when the INTVALn register is updated The reset values shown in Table 134
300. generator divider value register Immodes oie RI eee tbe XR DES 46 UARTFRGDIV address 0x4004 80F0 bit Table 47 Pinout 52 description as eee i 29 Table 48 Register overview I O configuration base Table 24 USART fractional generator multiplier value address 0x4004 4000 55 register UARTFRGMULT address 0x4004 80F4 Table 49 PIOO 17 register PIOO 17 address 0x4004 bit description 29 4000 bit 56 Table 25 External trace buffer command register Table 50 PIOO 13 register PIOO 13 address 0x4004 EXTTRACECMD address 0x4004 80 bit 4004 bit description 57 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 313 of 326 NXP Semiconductors UM10601 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 UM10601 PIOO 12 register PIOO 12 address 0x4004 4008 bit description PIOO 5 register PIOO 5 address 0x4004 400C bit descri
301. guration IOCON Table 27 IOCON glitch filter clock divider registers 6 to 0 IOCONCLKDIV 6 0 address 0x4004 8134 IOCONCLKDIV6 to 0x004 814C IOCONFILTCLKDIVO bit description 6 5 Register description Each port pin PlOn m has one IOCON register assigned to control the pin s function and electrical characteristics Table 48 Register overview I O configuration base address 0x4004 4000 Name Access Address Description Reset value Reference offset PIOO 17 R W 0x000 I O configuration for pin PIOO 17 0x0000 0090 Table 49 PIOO 13 R W 0x004 I O configuration for pin PIOO 13 0x0000 0090 Table 50 PIOO 12 R W 0x008 I O configuration for PIOO_12 0x0000 0090 Table 51 PIOO 5 R W 0x00C I O configuration for pin PIOO 5 RESET 0 0000 0090 Table 52 PIOO 4 R W 0x010 I O configuration for PIOO 4 0x0000 0090 Table 53 PIOO 3 R W 0x014 I O configuration for pin 0x0000 0090 Table 54 PIOO_3 SWCLK PIOO 2 R W 0x018 I O configuration for pin PIOO 2 5SWDIO 0x0000 0090 Table 55 PIOO 11 R W 0x01C I O configuration for pin PIOO 11 This 0 0000 0080 Table 56 is the pin configuration for the true open drain pin PIOO 10 R W 0x020 I O configuration for pin PIOO 10 This 0 0000 0080 Table 57 is the pin configuration for the true open drain pin PIOO 16 R W 0x024 I O configuration for pin PIOO 16 0x0000 0090 Table 58 PIOO 15 R W 0x028 I O configuration for pin PIOO 15 0x0000 0090 Table 59 PIOO 1 R W 0x02C I O configuration for pin 0x0
302. gured as digital input pin configured as analog input Fig 5 Pin configuration VDD open drain enable strong output enable pull up data output E strong pull down VDD weak pull up pull up enable DD pull down enable weak repeater mode P pull down enable 9 data input PROGRAMMABLE GLITCH FILTER select data inverter select glitch filter select analog input analog input Ba 6 4 2 6 4 3 UM10601 Pin function The pin function is determined entirely through the switch matrix By default one of the GPIO functions is assigned to each pin The switch matrix can assign all functions from the movable function table to any pin in the IOCON block or enable a special function like an analog input on a specific pin Related links Table 94 Movable functions assign to pins PIOO 0 to PIOO 17 through switch matrix Pin mode The MODE bit in the IOCON register allows enabling or disabling an on chip pull up resistor for each pin By default all pull up resistors are enabled except for the I2C bus pins PIOO 10 and PIOO 11 which do not have a programmable pull up resistor All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 53 of 326 NXP Semiconductors U M1 0601 6 4 4 6
303. h Remark Writing any value to either the PMCFG register or the PMSRC register or disabling the pattern match feature by clearing both the SEL PMATCH and ENA RXEV bits in the PMCTRL register to zeros will erase all edge detect history Table 91 Pattern match bit slice source register PMSRC address 0xA000 402C bit description Bit Symbol Value Description Reset value 7 0 Reserved Software should not write 1s to unused bits 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 91 of 326 NXP Semiconductors UM10601 Chapter 8 LPC800 Pin interrupts pattern match engine Table 91 Pattern match bit slice source register PMSRC address 0xA000 402C bit description Bit Symbol 10 8 SRCO 13 11 SRC1 16 14 SRC2 19 17 SRC3 UM10601 Value 0x0 0 1 0 2 0x3 0 4 0 5 0 6 0 7 0 0 0 1 0 2 0x3 0 4 0 5 0 6 0 7 0 0 0 1 0 2 0x3 0 4 0 5 0 6 0 7 0 0 0 1 0 2 0x3 0 4 0 5 0 6 0 7 Description Selects the input source for bit slice 0 Input 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Selects pin interrupt input O as the source to bit slice 0 Selects pin interrupt input 1 as the source to bit slice 0 Selects pin interrupt input 2 as the source to bit slice 0 Selects pin interrupt input 3 as the source to bit slice
304. h divider that can reflect the crystal oscillator the main clock the IRC or the watchdog oscillator Power control Integrated PMU Power Management Unit to minimize power consumption Reduced power modes Sleep mode Deep sleep mode Power down mode and Deep power down mode Wake up from Deep sleep and Power down modes on activity on USART SPI and I2C peripherals Timer controlled self wake up from Deep power down mode Power On Reset POR Brownout detect Unique device serial number for identification Single power supply Available as SO20 package TSSOP20 package TSSOP16 and DIP8 package UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 4 of 326 NXP Semiconductors UM10601 1 3 Ordering information Chapter 1 LPC800 Introductory information Table 1 Ordering information Type number Package Name LPC810M021FN8 DIP8 LPC811M001FDH16 TSSOP16 LPC812M101FDH16 TSSOP16 LPC812M101FD20 SO20 LPC812M101FDH20 TSSOP20 Description plastic dual in line package 8 leads 300 mil plastic thin shrink small outline package 16 leads body width 4 4 mm SOT403 1 plastic thin shrink small outline package 16 leads body width 4 4 mm SOT403 1 plastic small outline package 20 leads body width 7 5 mm Version SOT097 2 SOT163 1 plastic thi
305. he SYSAHBCLKDIV registers If a reset occurs the microcontroller enters the default configuration in Active mode All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 47 of 326 NXP Semiconductors U M1 0601 5 7 5 5 7 5 1 5 7 5 2 5 7 5 3 UM10601 Chapter 5 LPC800 Reduced power modes and Power Management Deep sleep mode In Deep sleep mode the system clock to the processor is disabled as in Sleep mode All analog blocks are powered down except for the BOD circuit and the watchdog oscillator which can be selected or deselected during Deep sleep mode in the PDSLEEPCFG register The main clock and therefore all peripheral clocks are disabled except for the clock to the watchdog timer if the watchdog oscillator is selected The IRC is running but its output is disabled The flash is in stand by mode Deep sleep mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself memory systems and related controllers and internal buses The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Power configuration in Deep sleep mode Power consumption in Deep sleep mode is determined by the Deep sleep power configuration setting in the PDSLEEPCFG Table 35 register The watchdog o
306. he corresponding bit in the INTENSET 0 register 1 Reserved Read value is undefined only zero should be NA written 2 TXRDYCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 4 3 Reserved Read value is undefined only zero should be NA written 5 DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 6 TXDISINTCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 7 Reserved Read value is undefined only zero should be NA written 8 OVERRUNCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 10 9 Reserved Read value is undefined only zero should be NA written 11 DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 12 STARTCLR Writing 1 clears the corresponding bit in the INTENSET 0 register UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 180 of 326 NXP Semiconductors U M1 0601 15 6 6 15 6 7 UM10601 Chapter 15 LPC800 USARTO 1 2 Table 162 USART Interrupt Enable clear register INTENCLR address 0x4006 4010 USARTO 0 4006 8010 USART1 0 4006 C010 USART2 bit description Bit Symbol Description Reset Value 13 FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 14 PARITYERRCLR Writing 1 clears the corresponding bit in the INTE
307. he flash memory The code that initiates signature generation should also be placed outside of the flash memory Signature generation address and control registers These registers control automatic signature generation A signature can be generated for any part of the flash memory contents The address range to be used for generation is defined by writing the start address to the signature start address register FMSSTART and the stop address to the signature stop address register FMSSTOP The start and stop addresses must be aligned to 32 bit boundaries Signature generation is started by setting the STRTBIST bit in the FMSSTOP register Setting the STRTBIST bit is typically combined with the signature stop address in a single write Table 208 and Table 209 show the bit assignments in the FMSSTART and FMSSTOP registers respectively Signature generation A signature can be generated for any part of the flash contents The address range to be used for signature generation is defined by writing the start address to the FMSSTART register and the stop address to the FMSSTOP register The signature generation is started by writing 1 to the SIG START bit in the FMSSTOP register Starting the signature generation is typically combined with defining the stop address which is done in the STOP bits of the same register The time that the signature generation takes is proportional to the address range for which the signature is generated R
308. hen disabled configurations settings for 0 the Monitor function are not changed but the Monitor function is internally reset Disabled The 12C monitor function is disabled Enabled The 12C monitor function is enabled 12C bus Time out Enable When disabled the time out 0 function is internally reset Disabled Time out function is disabled Enabled Time out function is enabled Both types of time out flags will be generated and will cause interrupts if they are enabled Typically only one time out will be used in a system Monitor function Clock Stretching 0 Disabled The monitor function will not perform clock stretching Software may not always be able to read data provided by the monitor function before it is overwritten This mode may be used when non invasive monitoring is critical Enabled The monitor function will perform clock stretching in order to ensure that software can read all incoming data supplied by the monitor function Reserved Read value is undefined only zero should be written All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 192 of 326 NXP Semiconductors UM10601 Chapter 16 LPC800 I2C bus interface 16 6 2 12C Status register The STAT register provides status flags and state information about all of the functions of the 12C block Some information in t
309. her continue send a Stop or plus Read was previously sent and Acknowledged by slave send a Repeated Start 2 Data can be transmitted Master Transmitter mode Send data and continue or send a Stop or Address plus Write was previously sent and Acknowledged by Repeated Start slave 3 Slave NACKed address Send a Stop or Repeated Start Slave NACKed transmitted data Send a Stop or Repeated Start Table 173 Slave function state codes SLVSTATE SlvState Description Actions 0 Address plus R W received At least one of the 4 Software can further check the address if needed for slave addresses has been matched by hardware instance if a subset of addresses qualified by SLVQUALO is to be used Software can ACK or NACK the address by writing 1 to either SLVCONTINUE or SLVNACK Also see Section 16 7 3 regarding 10 bit addressing 1 Received data is available Slave Receiver mode Read data reply with an or a NACK Data can be transmitted Slave Transmitter mode Send data Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 196 of 326 NXP Semiconductors UM10601 Chapter 16 LPC800 I2C bus interface 16 6 3 Interrupt Enable Set and read register UM10601 The INTENSET register controls which 12C status flags generate interrupts Writing a 1 to a bit position in this register e
310. his is a non sticky version of value 0x3 This bit is cleared after one clock cycle UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 97 of 326 NXP Semiconductors U M1 0601 Chapter 8 LPC800 Pin interrupts pattern match engine Table 92 Pattern match bit slice configuration register PMCFG address 0xA000 4030 bit description continued Bit Symbol Value Description Reset value 28 26 CFG6 Specifies the match contribution condition for bit slice 6 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was Cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 4 High level Match for th
311. his register is read only and some flags can be cleared by writing a 1 to them Access to bits in this register varies RO Read only W1 write 1 to clear Details on the master and slave states described in the MSTSTATE and SLVSTATE bits in this register are listed in Table 172 and Table 173 Table 171 12 Status register STAT address 0x4005 0004 bit description Bit Symbol 0 MSTPENDING 31 MSTSTATE 4 MSTARBLOSS UM10601 Value Description Reset Access value Master Pending Indicates that the Master is waiting to continue 1 RO 0x0 0x1 0x2 0x3 0x4 communication on the 12C bus pending or is idle When the master is pending the MSTSTATE bits indicate what type of software service if any the master expects This flag will cause an interrupt when set if enabled via the INTENSET register If the master is in the idle state and no communication is needed mask this interrupt In progress Communication is in progress and the Master function is busy and cannot currently accept a command Pending The Master function needs software service or is in the idle state If the master is not in the idle state it is waiting to receive or transmit data or the NACK bit Master State code The master state code reflects the master state 0 RO when the MSTPENDING bit is set that is the master is pending or in the idle state Each value of this field indicates a specific required service for the Master function
312. hrough switch matrix Function name Type Description SWM Pin assign Reference register I2CO0 SCL I2C bus clock input output open drain if assigned to PINASSIGN8 Table 104 PIOO 10 High current sink only if assigned to PIOO 10 and if lC Fast mode Plus is selected in the I O configuration register ACMP O Analog comparator output PINASSIGN8 Table 104 CLKOUT Clock output PINASSIGN8 Table 104 GPIO INT BMAT O Output of the pattern match engine PINASSIGN8 Table 104 9 4 2 Switch matrix register interface The switch matrix consists of two blocks of pin assignment registers PINASSIGN and PINENABLE Every function has an assigned field 1 bit or 8 bit wide within this bank of registers where you can program the external pin identified by its GPIO function you want the function to connect to GPIOs range from PIOO 0 to PIOO 17 and for assignment through the pin assignment registers are numbered 0 to 17 There are two types of functions which must be assigned to port pins in different ways 1 Movable functions PINASSIGNO to 8 All movable functions are digital functions Assign movable functions to pin numbers through the 8 bits of the PINASSIGN register associated with this function Once the function is assigned a pin PIOO n it is connected through this pin to a physical pin on the package Remark You can assign only one digital output function to an external pin at any given time Remark You can ass
313. ights reserved Preliminary user manual Rev 1 1 24 January 2013 223 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 Table 199 SPI Interrupt Status register INTSTAT addresses 0x4005 8028 SPIO 0x4005 C028 SPI1 bit description Bit Symbol Description Reset value 4 SSA Slave Select Assert 0 5 SSD Slave Select Deassert 0 31 6 Reserved Read value is undefined only zero should be written NA UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 224 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 17 7 Functional description 17 7 1 Operating modes clock and phase selection SPI interfaces typically allow configuration of clock phase and polarity These are sometimes referred to as numbered SPI modes as described in Table 200 and shown in Figure 34 CPOL and CPHA are configured by bits in the CFG register Section 17 6 1 Table 200 SPI mode summary SPI ES SCKrest data SCK data euis GANA Mode pessian state change edge sample edge The SPI captures serial data on the first clock transition of 0 0 the frame when the clock changes away from the rest low falling rising state Data is changed on the following edge The SPI changes serial data on the first clock transition of 0 1 1 the frame when the clock changes away from the r
314. ign more than one digital input function to one external pin 2 Fixed pin functions PINENABLEO Some functions require pins with special characteristics and cannot be moved to other physical pins Hence these functions are mapped to a fixed port pin Examples of fixed pin functions are the oscillator pins or comparator inputs Each fixed pin function is associated with one bit in the PINENABLEO register which selects or deselects the function f a fixed pin function is deselected any movable function can be assigned to its port and pin fixed pin function is deselected and no movable function is assigned to this pin the pin is assigned its GPIO function Onreset all fixed pin functions are deselected Ifa fixed pin analog function is selected its assigned pin cannot be used for any other function UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 108 of 326 NXP Semiconductors UM10601 9 5 Register description Chapter 9 LPC800 Switch matrix Table 95 Register overview Switch matrix base address 0x4000 C000 Name PINASSIGNO PINASSIGN1 PINASSIGN2 PINASSIGN3 PINASSIGN4 PINASSIGN5 PINASSIGN6 PINASSIGN7 PINASSIGN8 PINENABLEO Access Offset R W R W R W R W R W R W R W R W R W R W 0x000 0x004 0x008
315. igned to this function The following pins are available PIOO 0 2 0 to PIOO 17 2 Ox11 31 24 CTIN O I CTIN 0 function assignment The value is the pin number to OxFF assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 9 5 7 Pin assign register 6 Table 102 Pin assign register 6 PINASSIGN6 address 0x4000 C018 bit description Bit Symbol Description Reset value 7 0 CTIN 1 I CTIN 1 function assignment The value is the pin number to OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 0x11 15 8 2 I CTIN 2function assignment The value is the pin number to OXFF assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 23 16 CTIN 3 I CTIN function assignment The value is the pin number to OxFF assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 31 24 CTOUT 0 O CTOUT 0 function assignment The value is the pin number to OXFF be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 9 5 8 Pin assign register 7 Table 103 Pin assign register 7 PINASSIGNT address 0x4000 C01C bit description Bit Symbol Description Reset value 7 0 CTOUT 1 O CTOUT 1 function assignment The value is the pin number to OXFF be assigned to this function The following pins are available PIOO 0 0 to P
316. imited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information Source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior
317. imits it is also possible to automatically cause a limit condition whenever a match register 0 match occurs This eliminates the need to define an event for the sole purpose of creating a limit The AUTOLIMITL and AUTOLIMITH bits in the configuration register enable disable this feature see Table 108 Table 110 SCT limit register LIMIT address 0x5000 4008 bit description Bit Symbol Description Reset value 5 0 LIMMSK_L If bit n is one event n is used as a counter limit for the Lor 0 unified counter event 0 bit 0 event 1 bit 1 event 5 bit 5 156 Reserved 21116 LIMMSK H If bit n is one event n is used as a counter limit for the H 0 counter event 0 bit 16 event 1 bit 17 event 5 bit 21 31 22 Reserved SCT halt condition register If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers HALT L and HALT H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation Remark Any event halting the counter disables its operation until software clears the HALT bit or bits in the CTRL register Table 109 Table 111 SCT halt condition register HALT address 0x5004 400C bit description Bit Symbol Description Reset value 5 0 HALTMSK L If bit n is one event n sets the HALT L bit in the CTRL register 0 event 0 bit 0 event 1 bit 1 event 5 bit 5 156
318. in their internal states The flash memory is powered down The WWDT WKT and BOD can remain active to wake up the system on an interrupt 3 Deep power down mode For maximal power savings the entire system is shut down except for the general purpose registers in the PMU and the self wake up timer Only the general purpose registers in the PMU maintain their internal states The part can wake up on a pulse on the WAKEUP pin or when the self wake up timer times out On wake up the part reboots Remark The LPC800 is in active mode when it is fully powered and operational after booting 5 5 1 Wake up process If the part receives a wake up signal in any of the reduced power modes it wakes up to the active mode See these links for related registers and wake up instructions To configure the system after wake up Table 36 Wake up configuration register PDAWAKECFG address 0x4004 8234 bit description To use external interrupts for wake up Table 33 Start logic 0 pin wake up enable register 0 STARTERPO address 0x4004 8204 bit description and Table 32 Pin interrupt select registers PINTSEL 0 7 address 0x4004 8178 PINTSELO to 0x4004 8194 PINTSEL7 bit description To enable external or internal signals to wake up the part from Deep sleep or Power down modes Table 34 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description To configure the USART to wake up the part Sect
319. information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 140 of 326 NXP Semiconductors U M1 0601 Chapter 10 LPC800 State Configurable Timer SCT 10 7 9 4 Configure multiple states 1 In the STATE register for each event up to 6 events one register per event select the state or states up to 2 in which this event is allowed to occur Each state can be selected for more than one event Determine how the event affects the system state In the EVn_CTRL registers up to 6 events one register per event set the new state value in the STATEV field for this event If the event is the highest numbered in the current state this value is either added to the existing state value or replaces the existing state value depending on the field STATELD Remark If there are higher numbered events in the current state this event cannot change the state If the STATEV and STATELD values are set to zero the state does not change 10 7 9 5 Miscellaneous options There are a certain selectable number of capture registers Each capture register can be programmed to capture the counter contents when one or more events occur f the counter is in bidirectional mode the effect of set and clear of an output can be made to depend on whether the counter is counting up or down by writing to the OUTPUTDIRCTRL regis
320. ing at all times Disabling the WWDT clock source Changing the WWDT reload value Disabling the WWDT clock source If bit 5 in the WWDT MOD register is set the WWDT clock source is locked and can not be disabled either by software or by hardware when Sleep Deep sleep or Power down modes are entered Therefore the user must ensure that the watchdog oscillator for each power mode is enabled before setting bit 5 in the MOD register In Deep power down mode no clock locking mechanism is in effect because no clocks are running However an additional lock bit in the PMU can be set to prevent the part from even entering Deep power down mode see Table 42 Changing the WWDT reload value If bit 4 is set in the WWDT MOD register the watchdog time out value TC can be changed only after the counter is below the value of WDWARNINT and WDWINDOW The reload overwrite lock mechanism can only be disabled by a reset of any type All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 153 of 326 NXP Semiconductors U M1 0601 Chapter 12 LPC800 Windowed Watchdog Timer WWDT 12 6 Register description 12 6 1 The Watchdog Timer contains the registers shown in Table 141 The reset value reflects the data stored in used bits only It does not include the content of reserved bits Table 141 Register overview Wat
321. ins are available PIOO 0 2 0 to PIOO 17 2 Ox11 31 24 GPIO INT BMAT GPIO INT BMAT function assignment The value is the OxFF pin number to be assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 9 5 10 Pin enable register 0 Table 105 Pin enable register 0 PINENABLEO address 0x4000 C1C0 bit description Bit Symbol Value Description Reset value 0 ACMP l1 EN 1 ACMP I2 EN Enables fixed pin function Writing a 1 deselects the function and any movable function can be assigned to this pin By default the fixed pin function is deselected and GPIO is assigned to this pin 0 Enable ACMP 11 This function is enabled on pin PIOO 0 Disable 11 GPIO function PIOO 0 default or any other movable function can be assigned to pin PIOO 0 Enables fixed pin function Writing a 1 deselects the function and any movable function can be assigned to this pin By default the fixed pin function is deselected and GPIO is assigned to this pin Functions CLKIN and ACMP 12 are connected to the same pin PIOO 1 To use ACMP 12 disable the CLKIN function in bit 7 of this register and enable ACMP 12 1 1 0 Enable ACMP 12 This function is enabled on pin PIOO 1 1 Disable ACMP 12 GPIO function PIOO 1 default or any other movable function can be assigned to pin PIOO 1 2 SWCLK EN Enables fixed pin function Writing a 1 deselects the function and any movable 0 function can be assigned to this pin
322. int32 t uart put line UART HANDLE T handle UART T param Input parameter handle The handle to the uart instance param Refer to UART T definition Return Error code ERR UART SEND ON UART sending is ongoing Description Send string end with X0 or raw data through UART 24 4 8 UART interrupt service routine Table 281 uart isr Routine uart isr Prototype void uart is UART HANDLE T handle Input parameter handle The handle to the uart instance Return None Description UART interrupt service routine To use this routine the corresponding USART interrupt must be enabled This function is invoked by the user ISR 24 4 9 Error codes Table 282 Error codes Return code Error Code Description 0x0008 0001 ERR_UART_RXD_BUSY UART receive is busy ERR_UART_BASE 1 0x0008 0002 ERR_UART_TXD_BUSY UART transmit is busy 0x0008 0003 ERR_UART_OVERRUN_FRA _ Overrun error Frame error ME_PARITY_NOISE parity error RxNoise error 0x0008 0004 ERR_UART_UNDERRUN Underrun error 0x0008 0005 ERR_UART_PARAM Parameter error UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 296 of 326 NXP Semiconductors UM1 0601 24 4 10 24 4 10 1 24 4 10 2 24 4 10 3 UM10601 Chapter 24 LPC800 USART API ROM driver routines UART ROM driver variables UART CONFIG structure Typdef struct UART_C
323. ion 15 3 2 Configure the USART for wake up For configuring the self wake up timer Section 14 5 Foralist of all wake up sources Table 41 Wake up sources for reduced power modes UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 42 of 326 NXP Semiconductors UM10601 Chapter 5 LPC800 Reduced power modes and Power Management Table 41 Wake up sources for reduced power modes Conditions Enable interrupt in NVIC Enable pin interrupts in NVIC and STARTERPO registers Power mode Wake up source Sleep Any interrupt Deep sleep and Pin interrupts Power down BOD interrupt BOD reset e WWDT interrupt WWDT reset Self Wake up Timer WKT time out Interrupt from USART SPI I2C peripheral Enable interrupt in NVIC and STARTERP registers Enable interrupt in BODCTRL register BOD powered in PDSLEEPCFG register Enable reset in BODCTRL register BOD powered in PDSLEEPCFG register Enable interrupt in NVIC and STARTERP registers WWDT running Enable WWDT in WWDT MOD register and feed Enable interrupt in WWDT MOD register WDOsc powered in PDSLEEPCFG register WWDT running Enable reset in WWDT MOD register WDOsc powered in PDSLEEPCFG register Enable interrupt in NVIC and STARTERP registers Enable low power oscillator in the GPREG4
324. ipheral clock and the fractional divider for the baud rate calculation are set up in the SYSCON block as follows see Figure 27 1 Configure the UART clock by writing a value UARTCLKDIV gt 0 in the USART peripheral clock divider register This is the divided main clock common to all USARTs Section 4 6 14 USART clock divider register 2 If a fractional value is needed to obtain a particular baud rate program the fractional divider The fractional divider value is the fraction of MULT DIV The MULT value is programmed the UARTFRGMULT register and the DIV value is programmedwith the fixed value of 256 in the UARTFRGDIV register in the SYSCON block U PCLK UARTCLKDIV 1 MULT DIV The following rules apply for MULT and DIV Always set DIV to 256 by programming the UARTFRGDIV register with the value of OxFF Program any value between 0 and 255 in the UARTFRGMULT register Section 4 6 19 USART fractional generator multiplier value register Section 4 6 18 USART fractional generator divider value register 3 In asynchronous mode Configure the baud rate divider BRGVAL in the USARTn BRG register The baud rate divider divides the common USART peripheral clock by a factor of 16 multiplied by the baud rate value to provide the baud rate U PCLK 16 x BRGVAL Section 15 6 9 USART Baud Rate Generator register 4 In synchronous mode The serial clock is Un SCLK U PCLK BRGVAL UM10601 All information
325. ipherals Each peripheral is allocated 16 kB of space simplifying the address decoding The registers incorporated into the ARM Cortex M0 core such as NVIC SysTick and sleep mode control are located on the private peripheral bus The GPIO port and pin interrupt pattern match registers are accessed by the ARM Cortex M0 single cycle I O enabled port IOP All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 8 of 326 NXP Semiconductors UM10601 Chapter 2 LPC800 Memory mapping 2 21 Memory mapping APB peripherals LPC81xM 4GB 1 OxFFFF FFFF 31 28 reserved S reserved 0xE010 0000 ivate ipheral b reserved USART1 0xA000 8000 USARTO pin interrupts pattern match 0xA000 4000 reserved SPI1 SPIO 0xA000 0000 ES reserved ue 0x5000 8000 reserved 0x5000 4000 12C reserved 0x5000 0000 SYSCON pen IOCON flash controller reserved reserved ENS reserved reserved 0 5 GB L 0x2000 0000 reserved A reserved Ox1FFF 2000 reserved Ox1FFF 0000 reserved 8 kB boot ROM un reserved E 0x1400 0400 1 kB MTB registers 0x1400 0000 reserved reserved reserved 0x1000 1000 4kB SRAM LPC812 0x1000 0800 2kB SRAM LPC811 0x1000 0400 1 SRAM LPC810 reserved reserved Switch matrix 0x1000 0000 MRT WWDT DS
326. ipherals running Sleep mode Deep sleep mode Power down mode and Deep power down mode Table 46 Peripheral configuration in reduced power modes Peripheral Sleep mode Deep sleep Power down Deep mode mode power down mode IRC software configurable off off IRC output software configurable off off off Flash software configurable on off off BOD software configurable software software off configurable configurable PLL software configurable off off off SysOsc software configurable off off off WDosc WWDT software configurable software software off configurable configurable Digital peripherals software configurable off off off WKT low power software configurable software software software oscillator configurable configurable configurable Remark The Debug mode is not supported in Sleep Deep sleep Power down or Deep power down modes Reduced power modes and WWDT lock features The WWDT lock feature influences the power consumption in any of the power modes because locking the WWDT clock source forces the watchdog oscillator to be on independently of the Deep sleep and Power down mode software configuration through the PDSLEEPCFG register For details see Section 12 5 3 Using the WWDT lock features Active mode In Active mode the ARM Cortex M0 core memories and peripherals are clocked by the system clock or main clock The chip is in Active mode after reset and the default power configuration is determine
327. iption 1 SPI IRQ SPI1 interrupt Same as IRQ 2 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 10 of 326 NXP Semiconductors U M1 0601 Chapter 3 LPC800 Nested Vectored Interrupt Controller NVIC Table 3 Connection of interrupt sources to the NVIC Interrupt Name Description Flags number 3 UARTO IRQ USARTO interrupt See Table 161 USART Interrupt Enable read and set register INTENSET address 0x4006 400C USARTO 0x4006 800C USART1 0x4006 USART2 bit description 4 UART1_IRQ USART1 interrupt Same as UARTO IRQ 5 UART2_IRQ USART2 interrupt Same as UARTO IRQ 6 Reserved 7 Reserved 8 1260 IRQ 12 0 interrupt See Table 175 Interrupt Enable Clear register INTENCLR address 0x4005 000C bit description 9 SCT IRQ State configurable timer EVFLAG SCT event interrupt 10 MRT IRQ Multi rate timer interrupt Global MRT interrupt GFLAGO GFLAG1 GFLAG2 GFLAG3 11 CMP_IRQ Analog comparator interrupt COMPEDGE rising falling or both edges can set the bit 12 WDT_IRQ Windowed watchdog timer WARNINT watchdog warning interrupt interrupt 13 BOD_IRQ BOD interrupts BODINTVAL BOD interrupt level 14 Reserved 15 WKT_IRQ Self wake up timer interrupt ALARMFLAG 23 16 Reserved 24 PININTO IRQ Pin interrupt 0 or pattern PSTAT pin interrupt
328. is also treated as a watchdog event This allows preventing situations where a system failure may still feed the watchdog For example application code could be stuck in an interrupt service that contains a watchdog feed Setting the window such that this would result in an early feed will generate a watchdog event allowing for system recovery The Watchdog consists of a fixed divide by 4 pre scaler and a 24 bit counter which decrements when clocked The minimum value from which the counter decrements is OxFF Setting a value lower than OxFF causes OxFF to be loaded in the counter Hence the minimum Watchdog interval is Twpcik x 256 x 4 and the maximum Watchdog interval is TwpcLk x 224 x 4 in multiples of x 4 The Watchdog should be used in the following manner Set the Watchdog timer constant reload value in the TC register Set the Watchdog timer operating mode in the MOD register e Set a value for the watchdog window time in the WINDOW register if windowed operation is desired e Set a value for the watchdog warning interrupt in the WARNINT register if a warning interrupt is desired Enable the Watchdog by writing OxAA followed by 0x55 to the FEED register The Watchdog must be fed again before the Watchdog counter reaches zero in order to prevent a watchdog event If a window value is programmed the feed must also occur after the watchdog counter passes that value When the Watchdog Timer is configure
329. is bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0x5 Low level Match occurs when there is a low level on the specified input 0x6 Constant 0 This bit slice never contributes to a match should be used to disable any unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs on an event i e when either a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 31 29 CFG7 Specifies the match contribution condition for bit slice 7 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was Cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 4 High
330. is register is a Read only register and supplies the PLL lock status see Section 4 7 1 1 Table 9 System PLL status register SYSPLLSTAT address 0x4004 800C bit description Bit Symbol Value Description Reset value 0 LOCK PLL lock status 0 0 PLL not locked 1 PLL locked 31 1 Reserved E System oscillator control register This register configures the frequency range for the system oscillator Table 10 System oscillator control register SYSOSCCTRL address 0x4004 8020 bit description Bit Symbol Value Description Reset value 0 BYPASS Bypass system oscillator 0x0 0 Disabled Oscillator is not bypassed 1 Enabled PLL input sys osc clk is fed directly from the XTALIN pin bypassing the oscillator Use this mode when using an external clock source instead of the crystal oscillator 1 FREQRANGE Determines frequency range for Low power 0x0 oscillator 0 1 20 MHz frequency range 1 15 25 MHz frequency range 31 2 Reserved 0x00 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 21 of 326 NXP Semiconductors U M1 0601 4 6 6 Chapter 4 LPC800 System configuration SYSCON Watchdog oscillator control register This register configures the watchdog oscillator The oscillator consists of an analog and a digital part The analog part contains the oscillator function and generates an
331. isables ISP override using PIOO 1 pin It is up to the user s application to provide a flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART Caution If CRP3 is selected no future factory testing can be performed on the device Table 216 Code Read Protection hardware software interaction CRP option User Code PIOO 1 pinat SWD enabled Part enters partial flash Valid reset ISP mode update in ISP mode None No X Yes Yes Yes None Yes High Yes No NA None Yes Low Yes Yes Yes CRP1 Yes High No No NA CRP1 Yes Low No Yes Yes UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 249 of 326 NXP Semiconductors UM10601 21 4 3 1 UM10601 Chapter 21 LPC800 Flash ISP and IAP programming Table 216 Code Read Protection hardware software interaction CRP option CRP2 CRP2 CRP3 CRP1 CRP2 CRP3 User Code Valid reset Yes High No Yes Low No Yes X No No X No No X No No X No PIOO 1 pin at SWD enabled Part enters ISP mode No Yes No Yes Yes Yes partial flash update in ISP mode NA No NA Yes No No Table 217 ISP commands allowed for different CRP levels ISP command Unlock Set Baud Rate Echo Write to RAM Read Memory Prepare sector s for write operation Copy RAM to flash Go Erase sector s B
332. it description Bit Symbol Description Reset value 1 0 STATEMSKm lf bit m is one event n n 0 to 5 happens in state m of the 0 counter selected by the HEVENT bit m state number state 0 bit 0 state 1 bit 1 31 2 Reserved SCT event control registers 0 to 5 This register defines the conditions for event n to occur other than the state variable which is defined by the state mask register Most events are associated with a particular counter high low or unified in which case the event can depend on a match to that register The other possible ingredient of an event is a selected input or output signal When the UNIFY bit is 0 each event is associated with a particular counter by the HEVENT bit in its event control register An event cannot occur when its related counter is halted nor when the current state is not enabled to cause the event as specified in its event mask register An event is permanently disabled when its event state mask register contains all Os All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 133 of 326 NXP Semiconductors U M1 0601 Chapter 10 LPC800 State Configurable Timer SCT An enabled event can be programmed to occur based on a selected input or output edge or level and or based on its counter value matching a selected match register STOP bit 0 An even
333. itations apply 1 The smallest amount of data that can be written to flash by the copy RAM to flash command is 64 byte equal to one page 2 One page consists of 16 flash words lines and the smallest amount that can be modified per flash write is one flash word one line This limitation follows from the application of ECC to the flash write operation see Section 21 4 2 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 253 of 326 NXP Semiconductors UM10601 UM10601 Chapter 21 LPC800 Flash ISP and IAP programming 3 To avoid write disturbance a mechanism intrinsic to flash memories an erase should be performed after following 16 consecutive writes inside the same page Note that the erase operation then erases the entire sector Remark Once a page has been written to 16 times it is still possible to write to other pages within the same sector without performing a sector erase assuming that those pages have been erased previously Table 225 UART ISP Copy RAM to flash command Command Input Return Code Description Example C Flash Address DST Destination flash address where data bytes are to be written The destination address should be a 64 byte boundary RAM Address SRC Source RAM address from where data bytes are to be read Number of Bytes Number of bytes to be w
334. its will always be low 8 7 3 Pattern match engine edge detect examples slice 0 INOre SRCO 0 CFGO 0x3 sticky rising edge detection slice 1 IN1ev minterm INOre IN1ev IN1 pin interrupt raised on falling edge on input 1 any time pin interrupt 1 after INO has gone HIGH SRC1 1 CFG1 0x7 PROD ENPTS 0x1 non sticky edge detection Figure shows pattern match functionality only and accurate timing is not implied Inputs INn are shown synchronized to the System clock Fig 9 Pattern match engine examples sticky edge detect UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 100 of 326 NXP Semiconductors U M1 0601 Chapter 8 LPC800 Pin interrupts pattern match engine slice 0 INO SRCO 0 0 4 high level detection slice 1 INTev minterm f INO IN1ev IN1 no pin interrupt raised IN1 does not change while pin interrupt 1 INO level is HIGH SRC1 1 CFG1 0x7 PROD ENPTS 0x1 non sticky edge detection J Figure shows pattern match functionality only and accurate timing is not implied Inputs INn are shown synchronized to the System clock Fig 10 Pattern match engine examples non sticky edge detect without pin interrupt slice 0 INO INO JR pee SRCO 0 CFGO 0x4 high level detecti
335. ivider register 28 42 13 4 6 18 USART fractional generator divider value 4 3 Basic configuration 13 4 6 19 PEU RE VO d Iti li ni mueven 431 13 49 vial racional generator multip e 4 3 2 Configure the main clock and system clock 14 4 6 20 EV trace buffer command ister MS 29 4 3 3 Set up the system oscillator using XTALIN and ps 69 XTALOUT LLL Lu 14 4 6 21 POR captured PIO status register 0 30 em 4 6 22 IOCON glitch filter clock divider registers 4 4 Pin 15 IA I Bence 30 4 5 General 15 4623 BODcontrolregister 30 4 5 1 Clock 15 4 6 24 System tick counter calibration register 31 4 5 2 Power control of analog components 16 4 6 25 IRQ latency 31 4 5 3 Configuration of reduced power modes 17 4 6 06 source selection register 32 4 5 4 Reset and interrupt control 17 4627 Pininterrupt select registers 32 4 6 Register description 17 4 628 Start logic 0 pin wake up enable register 33 4 6 1 System memory remap register 19 4 6 29 Start logic 1 interrupt wake up enable register 34 4 6 2 Peripheral reset co
336. ized processing capability Efficiency mode corresponding to optimized balance of current consumption and CPU performance Low current mode corresponding to lowest power consumption In addition the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock Remark Disable all interrupts before making calls to the power profile API You can re enable the interrupts after the power profile API calls have completed The API calls to the ROM are performed by executing functions which are pointed by a pointer within the ROM Driver Table Figure 43 shows the pointer structure used to call the Power Profiles API UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 268 of 326 NXP Semiconductors U M1 0601 Chapter 22 LPC800 Power profile API ROM driver Power API function table set pll Ox1FFF 1FF8 ROM Driver Table 0x00 ee 0x04 0x08 0x0C Ptr to PowerAPI Table Ptr to Device Table Fig 43 Power profiles pointer structure ARM CORTEX MO main clock system clock irc osc clk SYSAHBCLKDIV SYSAHBCLKCTRL 1 E ROM enable wdt osc clk SYSAHBCLKCTRL n MAINCLKSEL n enable Sys plicikout Peripherals DIVIDER Sys osc clk i SYS
337. jected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 71 of 326 NXP Semiconductors UM10601 6 5 17 PIOO 0 register Chapter 6 LPC800 I O configuration IOCON Table 65 0 register PIOO 0 address 0x4004 4044 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0
338. k Monitor and release reset to individual peripherals Select pins for external pin interrupts and pattern match engine Configuration of reduced power modes Wake up control BOD configuration MTB trace start and stop Interrupt latency control Select a source for the NMI Calibrate system tick timer 4 3 Basic configuration Configure the SYSCON block as follows The SYSCON uses the CLKIN CLKOUT RESET and XTALIN OUT pins Configure the pin functions through the switch matrix See Section 4 4 Noclock configuration is needed The clock to the SYSCON block is always enabled By default the SYSCON block is clocked by the IRC 4 3 1 Setup the PLL The PLL creates a stable output clock at a higher frequency than the input clock If you need a main clock with a frequency higher than the 12 MHz IRC clock use the PLL to boost the input frequency 1 Power up the system PLL in the PDRUNCFG register Section 4 6 32 Power configuration register UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 13 of 326 NXP Semiconductors U M1 0601 Chapter 4 LPC800 System configuration SYSCON Select the PLL input in the SYSPLLCLKSEL register You have the following input options IRC 12 MHz internal oscillator System oscillator External crys
339. l asserted Slave Selects transition to deasserted An interrupt will be generated when all asserted Slave Selects transition to deasserted 31 6 Reserved Read value is undefined only zero should be written NA UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 219 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 17 6 5 SPI Interrupt Enable Clear register The INTENCLR register is used to clear interrupt enable bits in the INTENSET register Table 193 SPI Interrupt Enable clear register INTENCLR addresses 0x4005 8010 SPIO 0x4005 C010 SPI1 bit description Bit Symbol Description Reset value 0 RXRDYEN Writing 1 clears the corresponding bits in the INTENSET register 0 1 TXRDYEN Writing 1 clears the corresponding bits in the INTENSET register 0 2 RXOVEN Writing 1 clears the corresponding bits in the INTENSET register 0 3 TXUREN Writing 1 clears the corresponding bits in the INTENSET register 0 4 SSAEN Writing 1 clears the corresponding bits in the INTENSET register 0 5 SSDEN Writing 1 clears the corresponding bits in the INTENSET register 0 31 6 Reserved Read value is undefined only zero should be written NA 17 6 6 SPI Receiver Data register The read only RXDAT register provides the means to read the most recently received data The value of SSEL can be read alon
340. l cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADRO register If QUALMODEO 1 an address range is matched for address 0 This range extends from the value defined by SLVADRO to the address defined by SLVQUALO address matches when SLVADRO 7 1 lt received address lt SLVQUALO 7 1 31 8 Reserved Read value is undefined only zero should be NA written Monitor data register The read only MONRXDAT register provides information about events on the I C bus primarily to facilitate debugging of the 12C during application development All data addresses and data passing on the bus and whether these were acknowledged as well as Start and Stop events are reported The Monitor function must be enabled by the MONEN bit in the CFG register Monitor mode can be configured to stretch the 2 clock if data is not read from the MONRXDAT register in time to prevent it via the MONCLKSTR bit in the CFG register This can help ensure that nothing is missed but can cause the monitor function to be somewhat intrusive by potentially adding clock delays depending on software response time In order to improve the chance of collecting all Monitor information if clock stretching is not enabled Monitor data is buffered such that it is available until the end of the next piece of information from the 12 bus Table 186 Monitor data register MONRXDAT address 0x4005 0080 bit descrip
341. laimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 104 of 326 NXP Semiconductors U M1 0601 Chapter 9 LPC800 Switch matrix f you wantto assign a GPIO pin to a pin on any LPC800 package disable any special function available on this pin in the PINENABLEO register and do not assign any movable function to it By default all pins except pins PIOO 2 PIOO 3 and PIOO 5 are assigned to GPIO For all other functions that are not in the table of movable functions do the following a Locate the function in the pin description table in the data sheet This shows the package pin for this function b Enable the function in the PINENABLEO register All other possible functions on this pins are now disabled 9 4 General description The switch matrix connects internal signals functions to external pins Functions are signals coming from or going to a single pin on the package and coming from or going to an on chip peripheral block Examples of functions are the GPIOs the UART transmit output TXD or the clock output CLKOUT Many peripherals have several functions that must be connected to external pins The switch matrix also enables the output driver for digital functions that are outputs The electrical pin characteristics for both inputs and outputs internal pull up down resistors inverter digital filter open drain mode are configured by the IOCON block for each pin
342. lank check sector s Read Part ID Read Boot code version Compare ReadUID CRP1 yes yes yes yes above 0x1000 0300 only no yes yes not to sector 0 no yes sector 0 can only be erased when all sectors are erased no yes yes no yes CRP2 yes yes yes no no yes no no yes all sectors only no yes yes no yes CRP3 no entry in ISP mode allowed n a n a n a n a n a n a n a n a n a n a n a n a n a n a In case a CRP mode is enabled and access to the chip is allowed via the ISP an unsupported or restricted ISP command will be terminated with return code CODE READ PROTECTION ENABLED ISP entry protection In addition to the three CRP modes the user can prevent the sampling of pin PIOO 1 for entering ISP mode and thereby release pin PIOO 1 for other uses This is called the NO ISP mode The NO ISP mode can be entered by programming the pattern Ox4E69 7370 at location 0x0000 02FC All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 250 of 326 NXP Semiconductors U M1 0601 Chapter 21 LPC800 Flash ISP and IAP programming 21 5 API description 21 5 1 UART ISP commands The following commands are accepted by the ISP command handler Detailed status codes are supported for each command The command handler sends the
343. lator circuit and internal clock generator circuits Input voltage must not exceed 1 95 V PIOO S9 XTALOUT 13 10 8 O 1 PU PIOO 9 General purpose digital input output pin XTALOUT Output from the oscillator circuit PIOO 10 9 8 IA PIOO 10 General purpose digital input output pin Assign 12C functions to this pin when true open drain pins are needed for a signal compliant with the full 12C specification UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 305 of 326 NXP Semiconductors U M1 0601 Chapter 26 LPC800 Packages and pin description Table 285 Pin description table fixed pins Symbol 5 Type Reset Description AQA state Or F A PIOO 11 8 7 I3 IA PIOO 11 General purpose digital input output pin Assign 12C functions to this pin when true open drain pins are needed for a signal compliant with the full 12C specification PIOO 12 3 2 BVO PIOO 12 General purpose digital input output pin PIOO 13 2 1 B VO 1 PU PIOO 13 General purpose digital input output pin PIOO 14 20 VO PIOO 14 General purpose digital input output pin PIOO 15 11 A PIOO 15 General purpose digital input output pin PIOO 16 10 Ul VO PIOO 16 General purpose digital input output pin PIOO 17 1 VO PU PIOO 17 Gene
344. le 28 WWDT signal if the watchdog oscillator is enabled in the PDSLEEPCFG register All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 48 of 326 NXP Semiconductors U M1 0601 5 7 6 5 7 6 1 5 7 6 2 UM10601 Chapter 5 LPC800 Reduced power modes and Power Management WWDT interrupt using the interrupt wake up register 1 Table 34 The WWDT interrupt must be enabled in the NVIC The WWDT interrupt must be set in the WWDT register Reset from the watchdog timer The WWDT reset must be set in the WWDT MOD register In this case the watchdog oscillator must be running in Deep sleep mode see PDSLEEPCFG register and the WDT must be enabled in the SYSAHBCLKCTRL register Via any of the USART blocks if the USART is configured in synchronous mode See Section 15 3 2 Configure the USART for wake up e Via the I2C See Section 16 3 1 Via any of the SPI blocks See Section 17 3 1 Remark If the watchdog oscillator is running in Deep sleep mode its frequency determines the wake up time Power down mode In Power down mode the system clock to the processor is disabled as in Sleep mode All analog blocks are powered down except for the BOD circuit and the watchdog oscillator which must be selected or deselected during Power down mode in the PDSLEEPCFG register The main c
345. level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0x5 Low level Match occurs when there is a low level on the specified input 0x6 Constant 0 This bit slice never contributes to a match should be used to disable any unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs on an event i e when either a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 98 of 326 NXP Semiconductors U M1 0601 Chapter 8 LPC800 Pin interrupts pattern match engine 8 7 Functional description 8 7 1 8 7 2 UM10601 Pin interrupts In this interrupt facility up to 8 pins are identified as interrupt sources by the Pin Interrupt Select registers PINTSELO 7 All registers in the pin interrupt block contain 8 bits corresponding to the pins called out by the PINTSELO 7 registers The ISEL register defines whether each interrupt pin is edge or level sensitive The RISE and FALL registers detect edges on each interrupt pin and can be written to clear and set edge detection The IST register indicates whether each interrupt pin is currently requesting an interrup
346. level or rising edge interrupt set register SIENR address 0xA000 4008 bit description ue Res ree ead seed 88 Table 83 Pin interrupt level or rising edge interrupt clear register CIENR address 0xA000 400C bit lt 88 Table 84 Pin interrupt active level or falling edge interrupt enable register IENF address OxAO00 4010 bit description 89 Table 85 Pin interrupt active level or falling edge interrupt set register SIENF address 0 000 4014 bit description 89 Table 86 Pin interrupt active level or falling edge interrupt clear register CIENF address 0xA000 4018 bit lt 90 Table 87 Pin interrupt rising edge register RISE address OxA000 401C bit description 90 Table 88 Pin interrupt falling edge register FALL address OxA000 4020 bit description 90 Table 89 Pin interrupt status register IST address 0xA000 4024 bit description 91 Table 90 Pattern match interrupt control register PMCTRL address 0x4004A000 C4028 bit 91 Table 91 Pattern match bit slice source register PMSRC address 0x4004A000 C402C bit description 92 Table 92 Pattern match bit slice configuration register PMCFG address 0x4004A000 C4030 bit description 95 Table 93 Pin interrupt regi
347. liminary user manual Rev 1 1 24 January 2013 184 of 326 NXP Semiconductors U M1 0601 Chapter 15 LPC800 USARTO 1 2 The base clock produced by the FRG cannot be perfectly symmetrical so the FRG distributes the output clocks as evenly as is practical Since the USART normally uses 16x overclocking the jitter in the fractional rate clock in these cases tends to disappear in the ultimate USART output For setting up the fractional divider use the following registers Table 23 USART fractional generator divider value register UARTFRGDIV address 0x4004 80F0 bit description Table 24 USART fractional generator multiplier value register UARTFRGMULT address 0x4004 80F4 bit description For details see Section 15 3 1 Configure the USART clock and baud rate 15 7 1 2 Baud Rate Generator BRG The Baud Rate Generator see Section 15 6 9 is used to divide the base clock to produce a rate 16 times the desired baud rate Typically standard baud rates can be generated by integer divides of higher baud rates 15 7 1 3 Baud rate calculations Base clock rates are 16x for asynchronous mode and 1x for synchronous mode 15 7 2 Synchronous mode Remark Sync mode transmit and receive operate at the incoming clock rate in slave mode and the BRG selected rate not divided by 16 in master mode 15 7 3 Flow control The USART supports both hardware and software flow control 15 7 3 1 Hardware flow control The
348. ling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 4 High level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0x5 Low level Match occurs when there is a low level on the specified input 0x6 Constant 0 This bit slice never contributes to a match should be used to disable any unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs on an event i e when either a UM10601 rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 96 of 326 NXP Semiconductors U M1 0601 Chapter 8 LPC800 Pin interrupts pattern match engine Table 92 Pattern match bit slice configuration register PMCFG address 0xA000 4030 bit description continued
349. lkout or the watchdog oscillator or the IRC oscillator The main system clock clocks the core the peripherals and the memories Bit 0 of the MAINCLKUEN register see Section 4 6 11 must be toggled from 0 to 1 for the update to take effect Table 15 Main clock source select register MAINCLKSEL address 0x4004 8070 bit description Bit Symbol Value Description Reset value 1 0 SEL Clock source for main clock 0 0x0 IRC Oscillator 0x1 PLL input 0x2 Watchdog oscillator 0x3 PLL output 31 22 Reserved Main clock source update enable register This register updates the clock source of the main clock with the new input clock after the MAINCLKSEL register has been written to In order for the update to take effect first write a zero to bit O of this register then write a one Table 16 Main clock source update enable register MAINCLKUEN address 0x4004 8074 bit description Bit Symbol Value Description Reset value 0 ENA Enable main clock source update 0 0 No change 1 Update clock source 31 1 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 24 of 326 NXP Semiconductors U M1 0601 4 6 12 4 6 13 Chapter 4 LPC800 System configuration SYSCON System clock divider register This register controls how the main clock is divided to provide the system clock to
350. ll wait indefinitely for the PLL to lock A non zero value indicates how many times the code will check for a successful PLL lock event before it returns PLL NOT LOCKED In this case the PLL settings are unchanged and is returned as Result1 Remark The time it takes the PLL to lock depends on the selected PLL input clock source IRC system oscillator and its characteristics The selected source can experience more or less jitter depending on the operating conditions such as power supply and or ambient temperature This is why it is suggested that when a good known clock source is used and a PLL NOT LOCKED response is received the set pll routine should be invoked several times before declaring the selected PLL clock source invalid Hint setting Param3 equal to the system PLL frequency Hz divided by 10000 will provide more than enough PLL lock polling cycles set power This routine configures the device s internal power control settings according to the calling arguments The goal is to reduce active power consumption while maintaining the feature of interest to the application close to its optimum Remark Use the set power routine with SYSAHBCLKDIV 1 System clock divider register see Table 17 and Figure 44 set power returns a result code that reports whether the power setting was successfully changed or not All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights r
351. lock and therefore all peripheral clocks are disabled except for the clock to the watchdog timer if the watchdog oscillator is selected The IRC itself and the flash are powered down decreasing power consumption compared to Deep sleep mode Power down mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself memory systems and related controllers and internal buses The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Wake up times are longer compared to the Deep sleep mode Power configuration in Power down mode Power consumption in Power down mode can be configured by the power configuration setting in the PDSLEEPCFG Table 35 register in the same way as for Deep sleep mode see Section 5 7 5 1 The watchdog oscillator can be left running in Power down mode if required for the WWDT The BOD circuit can be left running in Power down mode if required by the application Programming Power down mode The following steps must be performed to enter Power down mode 1 The PD bits in the PCON register must be set to Ox2 Table 43 2 Select the power configuration in Power down mode in the PDSLEEPCFG Table 35 register 3 Select the power configuration after wake up in the PDAWAKECFG Table 36 register 4 If any of the available wake up interrupts are used for wake up enable the interrup
352. lock rate at which the microcontroller core is running when set power is called This parameter is an integer between from 1 and 50 MHz inclusive 22 5 Functional description 22 5 1 22 5 1 1 UM10601 Clock control See Section 22 5 1 1 to Section 22 5 1 6 for examples of the clock control API Invalid frequency device maximum clock rate exceeded command 0 12000 command 1 60000 command 2 CPU FREQ EQU command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock and a system clock of exactly 60 MHz The application was ready to infinitely wait for the PLL to lock But the expected system clock of 60 MHz exceeds the maximum of 50 MHz Therefore set pll returns PLL INVALID FREQ in result 0 and 12000 in result 1 without changing the PLL settings All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 274 of 326 NXP Semiconductors U M1 0601 22 5 1 2 22 5 1 3 22 5 1 4 22 5 1 5 UM10601 Chapter 22 LPC800 Power profile ROM driver Invalid frequency selection system clock divider restrictions command 0 12000 command 1 40 command 2 CPU FREQ LTE command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock a system clock of no more than 40 kHz and
353. locks Timing details are shown in Section 17 7 2 1 Pre delay and Post delay Section 17 7 2 2 Frame delay Section 17 7 2 3 Transfer delay Table 190 SPI Delay register DLY addresses 0x4005 8004 SPIO 0x4005 C004 SPI1 bit description Bit Symbol Description Reset value 3 0 PRE_DELAY Controls the amount of time between SSEL assertion and the beginning of a data 0 frame There is always one SPI clock time between SSEL assertion and the first clock edge This is not considered part of the pre delay 0x0 No additional time is inserted 0 1 1 SPI clock time is inserted 0 2 2 SPI clock times are inserted OxF 15 SPI clock times are inserted 7 4 POST_DELAY Controls the amount of time between the end of a data frame and SSEL deassertion 0 0x0 No additional time is inserted 0 1 1 SPI clock time is inserted 0 2 2 SPI clock times are inserted OxF 15 SPI clock times are inserted 11 8 FRAME DELAY Controls the minimum amount of time between adjacent data frames 0 0x0 No additional time is inserted 0 1 1 SPI clock time is inserted 0 2 2 SPI clock times are inserted OxF 15 SPI clock times are inserted 15 12 TRANSFER DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers 0 0x0 The minimum time that SSEL is deasserted is 1 SPI clock time Zero added time 0 1 The minimum time that SSEL is deasserted is 2 SPI clock times 0 2
354. lt address2 gt no of bytes gt 21 5 1 1 Unlock Unlock code gt 251 WAP terme ee e 264 21 5 1 2 Set Baud Rate Baud Rate stop bit 252 21 5 2 8 265 21 5 1 8 Echo lt gt 252 21 5 2 9 ReadUID 265 21 5 1 4 Write to RAM start address gt number of 21 5 2 10 Erase 265 DYESS sed 252 21 5 2 11 IAP Status 265 21 5 1 5 Read Memory address number of 216 Functional description 266 bytes gt enn 253 21 6 1 UART Communication protocol 266 SIEG dd d lt start sect 21611 UART ISP command format 266 gt lt 29 215 17 Copy RAM to flash Flash address gt 20813 ARTISPda oma 288 address no of bytes gt 253 216 2 Memory and interrupt use for ISP and IAP 266 uoa MU eise 255 21624 Interrupts during UART ISP 266 SUBS Frase seclors lt starl semp 21 6 2 2 Interrupts during IAP 267 isi uice ents 255 21623 RAM used by ISP command handler 267 hri lt sectornumber send pse 21624 RAM used by IAP command handler 267 E pude do Sow e miens M eres 21511 Read Pan Wenitcat
355. match feature allows complex boolean expressions to be constructed from the same set of eight GPIO pins that were selected for the GPIO pin interrupts Each term in the boolean expression is implemented as one slice of the pattern match engine A slice consists of an input selector and a detect logic The slice input selector selects one input from the available eight inputs with each input connected to a pin by the input s PINTSEL register The detect logic monitors the selected input continuously and creates a HIGH output if the input qualifies as detected Several terms can be combined to a minterm by designating a slice as an endpoint of the expression A pin interrupt for this slice is asserted when the minterm evaluates as true UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 82 of 326 NXP Semiconductors U M1 0601 Chapter 8 LPC800 Pin interrupts pattern match engine to IN7 from slice 1 n 1 to INO tied HIGH for slice 0 slice n 1 A SYSCON slice n endpoint configured PMCFG bit n 1 PROD ENDPTS all pins PIOO m NVIC pin interrupt n PINTSELO DETECT LOGIC PMSCR bits SCRn all pins m PINTSEL7 slice n 1 endpoint configured PMCFG bit n 1 1 PROD ENDPTS tied HIGH for slice 7 DETECT NVIC pin interrupt 1 LOGI
356. match interrupt bit slice configuration register Reset Reference value 0 Table 80 0 Table 81 NA Table 82 NA Table 83 0 Table 84 NA Table 85 NA Table 86 0 Table 87 0 Table 88 0 Table 89 0 Table 90 0 Table 91 Table92 Pin interrupt mode register For each of the 8 pin interrupts selected in the PINTSEL n registers see Section 4 6 27 one bit in the ISEL register determines whether the interrupt is edge or level sensitive Table 80 Pin interrupt mode register ISEL address 0xA000 4000 bit description Bit Symbol Description 7 0 PMODE Selects the interrupt mode for each pin interrupt Bit n Reserved configures the pin interrupt selected in PINTSELn 0 Edge sensitive 1 Level sensitive Reset Access value 0 R W All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 86 of 326 NXP Semiconductors U M1 0601 8 6 2 8 6 3 8 6 4 UM10601 Chapter 8 LPC800 Pin interrupts pattern match engine Pin interrupt level or rising edge interrupt enable register For each of the 8 pin interrupts selected in the PINTSELn registers See Section 4 6 27 one bit in the IENR register enables the interrupt depending on the pin interrupt mode configured in the ISEL register e If the pin interrupt mode is edge sensitive PMODE 0 the rising edge interrupt is enabled e If
357. mbining a level detect with an event detect See Section 8 7 3 for details Fig 8 INO IN1 IN2 IN3 IN4 INS ING IN7 To o From Previous Rise Detect Slice sticky with synch clear PMCFG Fall Detect Prod_Endpts i PMSRC SRC i sticky with synch clear 3 Pattern Match i Intr Req i MUX oS 4 _ Rise Detect non sticky Fall Detect Pattern match bit slice with detect logic non sticky To Next Slice PMCFG CFG i UM10601 8 5 2 1 Inputs and outputs of the pattern match engine The connections between the pins and the pattern match engine are shown in Figure 7 All inputs to the pattern match engine are selected in the syscon block and can be GPIO port pins or another pin function depending on the switch matrix configuration All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 84 of 326 NXP Semiconductors U M1 0601 8 5 2 2 UM10601 Chapter 8 LPC800 Pin interrupts pattern match engine The pattern match logic continuously monitors the eight inputs and generates interrupts when any one or more minterms product terms of the specified boolean expression is matched A separate interrupt request is generated for each individual minterm In addition the pa
358. mers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 167 of 326 UM10601 Chapter 15 LPC800 USARTO 1 2 Rev 1 1 24 January 2013 Preliminary user manual 15 1 How to read this chapter USARTO and USART1 are available on all parts USART2 is available on parts LPC812M101FDH16 and LPC812M101FDH20 only Read this chapter for a description of the USART peripheral and the software interface The LPC800 also provides an on chip ROM based USART API to configure and operate the USART See Table 273 15 2 Features e 7 8 or 9 data bits and 1 or 2 stop bits Synchronous mode with master or slave operation Includes data phase selection and continuous clock option Multiprocessor multidrop 9 bit mode with software address compare RS 485 possible with software address detection and transceiver direction control Parity generation and checking odd even or none One transmit and one receive data buffer e RTS CTS for hardware signaling for automatic flow control Software flow control can be performed using Delta CTS detect Transmit Disable control and any GPIO as an RTS output Received data and status can optionally be read from a single register Break generation and detection Receive data is 2 of 3 sample voting Status flag set when one sample differs Built in Baud Rate Generator A fractional rate divider is shared among all USARTS I
359. mes effective only after the device has gone through a power cycle Table 215 Code Read Protection options Name Pattern programmed in 0x0000 02FC NO ISP 0 4 69 7370 CRP1 0x12345678 CRP2 0x87654321 CRP3 0x43218765 Description Prevents sampling of pin PIOO 1 for entering ISP mode PIOO 1 is available for other uses Access to chip via the SWD pins is disabled This mode allows partial flash update using the following ISP commands and restrictions Write to RAM command should not access RAM below 0x1000 0300 Access to addresses below 0x1000 0200 is disabled Copy RAM to flash command can not write to Sector 0 Erase command can erase Sector 0 only when all sectors are selected for erase Compare command is disabled Read Memory command is disabled This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased Since compare command is disabled in case of partial updates the secondary loader should implement checksum mechanism to verify the integrity of the flash Access to chip via the SWD pins is disabled The following ISP commands are disabled Read Memory Write to RAM Go Copy RAM to flash Compare When CRP2 is enabled the ISP erase command only allows erasure of all user sectors Access to chip via the SWD pins is disabled ISP entry by pulling PIOO 1 LOW is disabled if a valid user code is present in flash sector O This mode effectively d
360. mit condition or to O Specifies the factor by which the SCT clock is prescaled to produce the L or unified 0 counter clock The counter clock is clocked at the rate of the SCT clock divided by PRE_L 1 Remark Clear the counter by writing a 1 to the CLRCTR bit whenever changing the PRE value Reserved This bit is 1 when the H counter is counting down Hardware sets this bit whenthe 0 counter limit is reached and BIDIR is 1 Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0 When this bit is 1 and HALT is 0 the H counter does not run but I O events related 0 to the counter can occur If such an event matches the mask in the Start register this bit is cleared and counting resumes When this bit is 1 the counter does not run and no events can occur A reset sets 1 this bit When the HALT H bit is one the STOP H bit is cleared If you want to remove the halt condition and keep the SCT in the stop condition not running then you can change the halt and stop condition with one single write to this register Remark Once set this bit can only be cleared by software to restore counter operation Writing a 1 to this bit clears the counter This bit always reads as 0 Direction select Up The H counter counts up to its limit condition then is cleared to zero Bidirectional The H counter counts up to its limit then counts down to a limit condition or to 0
361. ms are to be inserted in the expression Two types of edge detection on each input are possible Sticky A rising edge a falling edge or a rising or falling edge that is detected at any time after the edge detection mechanism has been cleared The input qualifies as detected the detect logic output remains HIGH until the pattern match engine detect logic is cleared again e Non sticky Every time an edge rising or falling is detected the detect logic output for this pin goes HIGH This bit is cleared after one clock cycle and the edge detect logic can detect another edge Remark To clear the pattern match engine detect logic write any value to either the PMCFG register or the PMSRC register or disable the pattern match feature by clearing both the SEL PMATCH and ENA RXEV bits in the PMCTRL register to zeros This will erase all edge detect history Table 92 Pattern match bit slice configuration register PMCFG address 0xA000 4030 bit description Bit Symbol Value Description Reset value 6 0 PROD _ A 1 in any bit of this field causes the corresponding bit slice to be the final component 0 0 ENDPTS UM10601 of a product term in the boolean expression This has two effects 1 The interrupt request associated with this bit slice will be asserted whenever a match to that product term is detected 2 The next bit slice will start a new independent product term in the boolean expression i e an OR will be inserted i
362. n 5 6 3 Deep power down control register Remark When entering Deep power down mode an external pull up resistor is required on the WAKEUP pin to hold it HIGH In addition pull the RESET pin HIGH to prevent it from floating while in Deep power down mode 5 5 General description UM10601 Power on the LPC800 is controlled by the PMU by the SYSCON block and the ARM Cortex M0 core The following reduced power modes are supported in order from highest to lowest power consumption 1 Sleep mode The sleep mode affects the ARM Cortex M0 core only Peripherals and memories are active 2 Deep sleep and power down modes The Deep sleep and power down modes affect the core and the entire system with memories and peripherals All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 41 of 326 NXP Semiconductors U M1 0601 Chapter 5 LPC800 Reduced power modes and Power Management a In Deep sleep mode the peripherals receive no internal clocks The flash is in stand by mode The SRAM memory and all peripheral registers as well as the processor maintain their internal states The WWDT WKT and BOD can remain active to wake up the system on an interrupt b In Power down mode the peripherals receive no internal clocks The internal SRAM memory and all peripheral registers as well as the processor mainta
363. n be found input parameter mode Param2 should be used to specify if the actual system clock can be less than or equal greater than or equal or approximately the value specified as the expected system clock Paramf A call specifying FREQ EQU will only succeed if the PLL can output exactly the frequency requested in Param1 CPU FREQ LTE can be used if the requested frequency should not be exceeded such as overall current consumption and or power budget reasons CPU FREQ GTE helps applications that need a minimum level of CPU processing capabilities CPU FREQ APPROX results in a system clock that is as close as possible to the requested value it may be greater than or less than the requested value If an illegal mode is specified set pll returns PLL INVALID MODE If the expected system clock is out of the range supported by this routine set returns PLL FREQ NOT FOUND In these cases the current PLL setting is not changed and Paramo0 is returned as Result1 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 271 of 326 NXP Semiconductors U M1 0601 22 4 1 3 22 4 2 UM10601 Chapter 22 LPC800 Power profile ROM driver Param3 system PLL lock time out It should take no more than 100 us for the system PLL to lock if a valid configuration is selected If Param3 is zero set pll wi
364. n mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 2 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0x1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0x0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 61 of 326 NXP Semiconductors UM10601 6 5 7 2 register Chapter 6 LPC800 I O configuration IOCON Table 55 2 register PIOO 2 address 0x4004 4018 bit description
365. n must be called from the 12 ISR when using 12C Rom Driver interrupt mode I2C Master Transmit Polling Table 254 12C Master Transmit Polling Routine I2C Master Transmit Polling Prototype ErrorCode_t i2c_master_transmit_poll I2C_HANDLE_T l2C_PARAM I2C RESULT Input parameter 12 _ HANDLE T Handle to the allocated SRAM area I2C PARAM Pointer to the I2C PARAM struct I2C RESULT Pointer to the I2C RESULT struct Return ErrorCode Description Transmits bytes in the send buffer to a slave The slave address with the R W bit 0 is expected in the first byte of the send buffer STOP condition is sent at end unless stop flag 0 When the task is completed the function returns to the line after the call 12C Master Receive Polling Table 255 12C Master Receive Polling Routine I2C Master Receive Polling Prototype ErrorCode ti2c master receive poll l2C HANDLE 126 I2C RESULT Input parameter 126 HANDLE Handle to the allocated SRAM area I2C Pointer to the I2C PARAM struct I2C RESULT Pointer to the I2C RESULT struct Return ErrorCode Description Receives bytes from slave and put into receive buffer The slave address with the R W bit 0 is expected in the first byte of the send buffer After the task is finished the slave address with the R W bit 1 is in the first byte of the receive buffer STOP condition is sent at end unless stop flag 20 When the
366. n on the on chip flash memory as directed by the end user application code You can use ISP and IAP when the part resides in the end user board Flash page write and erase supported 21 3 Pin description When pin PIOO 1 is pulled LOW on reset the part enters ISP mode and the ISP command handler starts up In ISP mode pin PIOO 0 is connected to function UO RXD and pin PIOO 4 is connected to function UO TXD on the USARTO block 21 4 General description 21 4 4 Flash configuration Most IAP and ISP commands operate on sectors and specify sector numbers In addition a page erase command is supported The following table shows the correspondence between page numbers sector numbers and memory addresses The size of a sector is 1 kB and the size of a page is 64 Byte One sector contains 16 pages UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 247 of 326 NXP Semiconductors U M1 0601 21 4 2 UM10601 Chapter 21 LPC800 Flash ISP and IAP programming Table 214 LPC800 flash configuration Sector Sector Page Address range 4kB 8 kB 16 kB number size number flash flash flash kB 0 1 0 15 0x0000 0000 0x0000 OSFF yes yes yes 1 1 16 31 0x0000 0400 0x0000 07FF yes yes yes 2 1 32 47 0x0000 0800 0x0000 OBFF yes yes yes 3 1 48 63 0x0000 0x0000 OFFF yes yes yes 4 1 64
367. n provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 138 of 326 NXP Semiconductors U M1 0601 10 7 8 10 7 9 10 7 9 1 10 7 9 2 UM10601 Chapter 10 LPC800 State Configurable Timer SCT SCT operation In its simplest single state configuration the SCT operates as an event controlled one or bidirectional counter Events can be configured to be counter match events an input or output level transitions on an input or output pin or a combination of match and input output behavior In response to an event the SCT output or outputs can transition or the SCT can perform other actions such as creating an interrupt or starting stopping or resetting the counter Multiple simultaneous actions are allowed for each event Furthermore any number of events can trigger one specific action of the SCT An action or multiple actions of the SCT uniquely define an event A state is defined by which events are enabled to trigger an SCT action or actions in any stage of the counter Events not selected for this state are ignored In a multi state configuration states change in response to events A state change is an additional action that the SCT can perform when the event occurs When an event is configured to change the state the new state defines a new set of events resulting in different actions of the SCT Through multiple cycles
368. n shrink small outline package 20 leads body width 4 4 mm SOT360 1 Table 2 Ordering options Type number Flash kB LPC810MO021FN8 4 LPC811M001FDH16 8 LPC812M101FDH16 16 LPC812M101FD20 16 LPC812M101FDH20 16 SRAM kB USART PC SPI 1 2 1 1 2 2 1 1 4 3 1 2 4 2 1 1 4 3 1 2 Comparator 1 i i i GPIO Package 14 14 18 18 DIP8 TSSOP16 TSSOP16 5020 TSSOP20 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 5 of 326 NXP Semiconductors U M1 0601 Chapter 1 LPC800 Introductory information 1 4 Block diagram LPC800 SWCLK SWD R TEST DEBUG Tex INTERFACE PIOO HIGH SPEED ROM GPIO ARM CORTEX MO FLASH sRAM PIN INTERRUPTS 4 8 16 kB 8kB PATTERN MATCH save save CTOUT 3 0 CTIN 3 0 AHB LITE BUS U slave TO APB IDGE Pa BR WWDT gt gt USARTO C IOCON 18x SWITCH MULT RATE TIMER MATRIX usanr i RXD CTS SCLK SCK SSEL MISO MOSI 9 seo SCK SSEL MISO MOSI USART2 SELF WAKE UP TIMER ALWAYS ON POWER DOMAIN BESET CLOCK RESET CLKIN GENERATION CLKOUT POWER CONTROL SYSTEM FUNCTIONS ACMP_11 2 VDDCMP clocks and ACMP O controls aaa 005746 Fig
369. n the boolean expression following the element controlled by this bit slice Reserved Bit slice 7 is automatically considered a product end point 0 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 94 of 326 NXP Semiconductors U M1 0601 Chapter 8 LPC800 Pin interrupts pattern match engine Table 92 Pattern match bit slice configuration register PMCFG address 0xA000 4030 bit description continued Bit Symbol Value Description Reset value 10 8 CFGO Specifies the match contribution condition for bit slice 0 06000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC regi
370. nabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 06001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 S MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 60 of 326 NXP Semiconductors UM10601 6 5 6 PIOO 3 register Table 54 3 register PIOO 3 address 0x4004 4014 bit description Chapter 6 LPC800 I O configuration IOCON Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects functio
371. nables an interrupt in the corresponding position in the STAT register if an interrupt is supported there Reading INTENSET indicates which interrupts are currently enabled Table 174 Interrupt Enable Set and read register INTENSET address 0x4005 0008 bit description Bit 3 1 11 14 12 15 16 17 18 Symbol MSTPENDINGEN MSTARBLOSSEN MSTSTSTPERREN SLVPENDINGEN SLVNOTSTREN SLVDESELEN MONRDYEN MONOVEN All information provided in this document is subject to legal disclaimers Value Description Master Pending interrupt Enable The MstPending interrupt is disabled The MstPending interrupt is enabled Reserved Read value is undefined only zero should be written Master Arbitration Loss interrupt Enable The MstArbLoss interrupt is disabled The MstArbLoss interrupt is enabled Reserved Read value is undefined only zero should be written Master Start Stop Error interrupt Enable The MstStStpErr interrupt is disabled The MstStStpErr interrupt is enabled Reserved Read value is undefined only zero should be written Slave Pending interrupt Enable The SlvPending interrupt is disabled The SlvPending interrupt is enabled Reserved Read value is undefined only zero should be written Slave Not Stretching interrupt Enable The SlvNotSir interrupt is disabled The SlvNotSir interrupt is enabled Reserved Read value is undefined only zero should be written Slave
372. nd End sector numbers 21 5 2 2 Copy RAM to flash IAP See Section 21 5 1 4 for limitations on the write to flash process UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 261 of 326 NXP Semiconductors UM10601 21 5 2 3 UM10601 Chapter 21 LPC800 Flash ISP and IAP programming Table 238 IAP Copy RAM to flash command Command Input Return Code Result Description Copy RAM to flash Command code 51 decimal ParamO DST Destination flash address where data bytes are to be written This address should be a 64 byte boundary Param1 SRC Source RAM address from which data bytes are to be read This address should be a word boundary Param2 Number of bytes to be written Should be 64 128 256 512 1024 Param3 System Clock Frequency CCLK in kHz CMD SUCCESS SRC ADDR ERROR Address not a word boundary DST ADDR ERROR Address not on correct boundary SRC ADDR NOT MAPPED DST ADDR NOT MAPPED COUNT ERROR Byte count is not 256 512 1024 4096 SECTOR NOT PREPARED FOR WRITE OPERATION BUSY None This command is used to program the flash memory The affected sectors should be prepared first by calling Prepare Sector for Write Operation command The affected sectors are automatically protected again once the copy command is successfully execute
373. nd mask a PORT register All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 79 of 326 UM10601 Chapter 8 LPC800 Pin interrupts pattern match engine Rev 1 1 24 January 2013 Preliminary user manual 8 1 How to read this chapter The pin interrupt generator and the pattern match engine are available on all LPC800 parts 8 2 Features Pin interrupts Upto eight pins can be selected from all GPIO pins as edge or level sensitive interrupt requests Each request creates a separate interrupt in the NVIC Edge sensitive interrupt pins can interrupt on rising or falling edges or both Level sensitive interrupt pins can be HIGH or LOW active Pattern match engine Upto eight pins can be selected from all GPIO pins to contribute to a boolean expression The boolean expression consists of specified levels and or transitions on various combinations of these pins Each bit slice minterm product term comprising the specified boolean expression can generate its own dedicated interrupt request Any occurrence of a pattern match can be programmed to also generate an RXEV notification to the ARM CPU The RXEV signal can be connected to a pin Pattern match can be used in conjunction with software to create complex state machines based on pin inputs 8 3 Basic configuration
374. nding a BOD interrupt to the NVIC and for forced reset Reset and interrupt threshold values listed in Table 28 are typical values Both the BOD interrupt and the BOD reset depending on the value of bit BODRSTENA in this register can wake up the chip from Sleep Deep sleep and Power down modes See the LPC800 data sheet for the BOD reset and interrupt levels All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 30 of 326 NXP Semiconductors U M1 0601 4 6 24 4 6 25 UM10601 Chapter 4 LPC800 System configuration SYSCON Table 28 control register BODCTRL address 0x4004 8150 bit description Bit Symbol Value Description Reset value 1 0 BODRSTLEV BOD reset level 0 0x0 Level 0 0x1 Level 1 0x2 Level 2 0x3 Level 3 3 2 BODINTVAL BOD interrupt level 0 0x0 Reserved 0x1 Level 1 0x2 Level 2 0x3 Level 3 4 BODRSTENA BOD reset enable 0 0 Disable reset function 1 Enable reset function 31 5 Reserved 0x00 System tick counter calibration register This register determines the value of the SYST CALIB register Table 29 System tick timer calibration register SYSTCKCAL address 0x4004 8154 bit description Bit Symbol Description Reset value 25 0 CAL System tick timer calibration value 0 31 26 Reserved IRQ latency register The IRQLATENCY register is an eight bi
375. no time out while waiting for the PLL to lock Since the maximum divider value for the system clock is 255 and running at 40 kHz would need a divide by value of 300 set pll returns PLL INVALID FREQ in result 0 and 12000 in result 1 without changing the PLL settings Exact solution cannot be found PLL command 0 12000 command 1 25000 command 2 CPU FREQ EQU command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock and a system clock of exactly 25 MHz The application was ready to infinitely wait for the PLL to lock Since there is no valid PLL setup within earlier mentioned restrictions set p l returns PLL FREQ NOT FOUND in result 0 and 12000 in result 1 without changing the PLL settings System clock less than or equal to the expected value command 0 12000 command 1 25000 command 2 CPU FREQ LTE command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock a system clock of no more than 25 MHz and no locking time out set pll returns PLL CMD SUCCESS in result 0 and 24000 in result 1 The new system clock is 24 MHz System clock greater than or equal to the expected value command 0 12000 command 1 25000 command 2 CPU FREQ command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock a system clock of at least 25 MHz
376. nstruction summary Chapter 27 LPC800 Appendix Operation Description Assembler Cycles Branch Conditional B cc lt label gt 1 or 2141 Unconditional B label 2 With link BL label 3 With exchange BX Rm 2 With link and exchange BLX Rm 2 Extend Signed halfword to word SXTH Rd Rm 1 Signed byte to word SXTB Rd Rm 1 Unsigned halfword UXTH Rd Rm 1 Unsigned byte UXTB Rd Rm 1 Reverse Bytes in word REV Rd Rm 1 Bytes in both halfwords REV16 Rd Rm 1 Signed bottom half word REVSH Rd Rm 1 State change Supervisor Call SVC lt imm gt Disable interrupts CPSID i 1 Enable interrupts CPSIE i 1 Read special register MRS Rad lt specreg gt 3 Write special register MSR lt gt Rn 3 Breakpoint BKPT lt imm gt 5 Hint Send event SEV 1 Wait for interrupt WFI 216 Wait for event WFE 216 Yield YIELDUI 1 No operation NOP 1 Barriers Instruction synchronization ISB 3 Data memory DMB 3 Data synchronization DSB 3 1 Nisthe number of elements in the list 2 2 cycles if to AHB interface or SCS 1 cycle if to single cycle I O port 3 Nisthe number of elements in the list including PC or LR 4 2iftaken 1 if not taken 5 Cycle count depends on core and debug configuration 6 Excludes time spend waiting for an interrupt or event 7 Executes as UM10601 All information provided in this document is subject to legal disclaimers Rev 1 1 24 January 2013 NXP B V 2013 All rights reser
377. nterrupts available for Receiver Ready Transmitter Ready Receiver Idle change in receiver break detect Framing error Parity error Overrun Underrun Delta CTS detect and receiver sample noise detected Loopback mode for testing of data and flow control 15 3 Basic configuration Remark The on chip USART API provides software routines to configure and use the USART See Table 273 Configure USARTO 1 2 for receiving and transmitting data n the SYSAHBCLKCTRL register set bit 14 to 16 Table 18 to enable the clock to the register interface Clear the USARTO 1 2 peripheral resets using the PRESETCTRL register Table 7 e Enable or disable the USARTO 1 2 interrupts in slots 3 to 5 in the NVIC UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 168 of 326 NXP Semiconductors U M1 0601 Chapter 15 LPC800 USARTO 1 2 Configure the USARTO 1 2 pin functions through the switch matrix See Section 15 4 Configure the USART clock and baud rate See Section 15 3 1 Configure the USARTO0 1 2 to wake up the part from low power modes Configure the USART to receive and transmit data in synchronous slave mode See Section 15 3 2 15 3 1 Configure the USART clock and baud rate All three USARTs use a common peripheral clock PCLK and if needed a fractional baud rate generator The per
378. ntrol register 19 4 6 30 Deep sleep mode configuration register 35 4 6 3 System PLL control register 20 4 6 31 Wake up configuration register 35 4 6 4 System PLL status register 21 4 6 32 Power configuration register 36 4 6 5 System oscillator control register 21 4633 Device ID register 37 4 6 6 Watchdog oscillator control register 22 4 7 Functional description 38 4 6 7 System reset status register 23 4 7 1 System PLL functional description 38 4 6 8 System PLL clock source select register 23 4 7 1 1 Lock 39 4 6 9 System PLL clock source update register 24 4 7 1 2 Power down 39 4 6 10 Main clock source select register 24 4 7 4 8 Divider ratio programming 39 4 6 11 Main clock source update enable register 24 4 7 4 8 1 39 4 6 12 System clock divider register 25 4 7 1 3 2 Feedback 39 4 6 13 System clock control register 25 4 7 1 3 3 Changing the divider values 39 4 6 14 USART clock divider register 27 471 4 Frequency selection 39 4 6 15 CLKOUT clock source select register 27 4 7 1 4 1 Normal 40 4 6
379. o should be NA written 15 7 Functional description 15 7 1 15 7 1 1 UM10601 Clocking and Baud rates In order to use the USART clocking details must be defined such as setting up the BRG and typically also setting up the FRG See Figure 27 Fractional Rate Generator FRG The Fractional Rate Generator can be used to obtain more precise baud rates when the peripheral clock is not a good multiple of standard or otherwise desirable baud rates The FRG is typically set up to produce an integer multiple of the highest required baud rate or a very close approximation The BRG is then used to obtain the actual baud rate needed The FRG register controls the USART Fractional Rate Generator which provides the base clock for the USART The Fractional Rate Generator creates a lower rate output clock by suppressing selected input clocks When not needed the value of 0 can be set for the FRG which will then not divide the input clock The FRG output clock is defined as the inputs clock divided by 1 MULT 256 where MULT is in the range of 1 to 255 This allows producing an output clock that ranges from the input clock divided by 1 1 256 to 1 255 256 just more than 1 to just less than 2 Any further division can be done specific to each USART block by the integer BRG divider contained in each USART All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Pre
380. of bytes to be read Count should be a multiple of 4 Return Code CMD SUCCESS followed by actual data plain binary ADDR ERROR Address not on word boundary ADDR NOT MAPPED COUNT ERROR Byte count is not a multiple of 4 PARAM ERROR CODE READ PROTECTION ENABLED Description This command is used to read data from RAM or flash memory This command is blocked when code read protection is enabled Example R 268435456 4 lt CR gt lt LF gt reads 4 bytes of data from address 0x1000 0000 Prepare sector s for write operation start sector number end sector numbers This command makes flash write erase operation a two step process Table 224 UART ISP Prepare sector s for write operation command Command P Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD SUCCESS BUSY INVALID SECTOR PARAM ERROR Description This command must be executed before executing Copy RAM to flash or Erase Sector s command Successful execution of the Copy RAM to flash or Erase Sector s command causes relevant sectors to be protected again The boot block can not be prepared by this command To prepare a single sector use the same Start and End sector numbers Example P 0 0 lt CR gt lt LF gt prepares the flash sector 0 Copy RAM to flash Flash address gt RAM address gt no of bytes gt When writing to the flash the following lim
381. ol 15 SLVDESELCLR 16 MONRDYCLR 17 MONOVCLR 18 19 MONIDLECLR 23 20 24 EVENTTIMEOUTCLR 25 SCLTIMEOUTCLR 31 26 Description Slave Deselect interrupt clear Monitor data Ready interrupt clear Monitor Overrun interrupt clear Reserved Read value is undefined only zero should be written Monitor Idle interrupt clear Reserved Read value is undefined only zero should be written Event time out interrupt clear SCL time out interrupt clear Reserved Read value is undefined only zero should be written Reset value NA NA NA Time out value register The TIMEOUT register allows setting an upper limit to certain IC bus times informing by status flag and or interrupt when those times are exceeded Two time outs are generated and software can elect to use either of them 1 EVENTTIMEOUT checks the time between bus events while the bus is not idle Start SCL rising SCL falling and Stop The EVENTTIMEOUT status flag in the STAT register is set if the time between any two events becomes longer than the time configured in the TIMEOUT register The EVENTTIMEOUT status flag can cause an interrupt if enabled to do so by the EVENTTIMEOUTEN bit in the INTENSET register 2 SCLTIMEOUT checks only the time that the SCL signal remains low while the bus is not idle The SCLTIMEOUT status flag in the STAT register is set if SCL remains low longer than the time configured in the TIMEOUT register The SCLTIMEOUT
382. olding Register Baud Rate and Clocking Generation Interrupt Generation Status USARTO interrupt Flow Control Break amp parity generation amp detection Receiver Receiver Receiver Buffer Shift Register Register USARTO block USART1 block USART2 block U PCLK UARTCLKDIV 1 MULT DIV Fig 28 USART block diagram UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 173 of 326 NXP Semiconductors UM10601 Chapter 15 LPC800 USARTO 1 2 15 6 Register description The reset value reflects the data stored in used bits only It does not include the content of reserved bits Table 157 Register overview USART base address 0x4006 4000 USARTO 0x4006 8000 USART1 0x4006 C000 USART2 Name CFG CTRL STAT INTENSET INTENCLR RXDATA RXDATASTAT TXDATA BRG INTSTAT Access Offset R W 0x000 R W 0x004 R W 0x008 R W 0x00C 0 010 R 0x014 R 0x018 R W 0x01C R W 0x020 R 0x024 Description USART Configuration register Basic USART configuration settings that typically are not changed during operation USART Control register USART control settings that are more likely to change during operation USART Status register The complete status value can be read here Writing 1s clears some bits in the register Some bits can be
383. on 134 Table 131 SCT output set register OUT 0 3 SET address 0x5000 4500 OUTO SET to 0x5000 4518 OUT3_SET bit description 135 Table 132 SCT output clear register OUT 0 3 CLR address 0x5000 0504 OUTO CLR to 0x5000 051C OUT3_CLR bit description 135 Table 133 Event conditions 138 Table 134 Register overview MRT base address 0x4000 4000 ur IER a I DR PPP T 145 Table 135 Time interval register INTVAL 0 3 address 0x4000 4000 INTVALO to 0x4000 4030 INTVAL3 bit description 146 Table 136 Timer register TIMER 0 3 address 0x4000 4004 TIMERO to 0x4000 4034 TIMER3 bit descriptlon ieri emen 147 Table 137 Control register CTRL 0 3 address 0x4000 4008 CTRLO to 0x4000 4038 CTRL3 bit description m ERR 147 Table 138 Status register STAT 0 3 address 0x4000 400C STATO to 0x4000 403C STAT3 bit description eamm 148 Table 139 Idle channel register IDLE CH address 0x4000 40F4 bit description 148 Table 140 Global interrupt flag register IRQ FLAG address 0x4000 40F8 bit description 149 Table 141 Register overview Watchdog timer base address 0x4000 4000 154 Table 142 Watchdog mode register MOD 0x4000 4000 bit description ise em ede ERI RETE 154 Table 143 Watchdog operating modes selection 156 Table 144 Watchdog Timer Constant
384. on slice 1 IN1ev minterm f INO IN1ev IN1 pin interrupt raised on rising edge of IN1 during pin interrupt 1 the HIGH level of INO SRC1 1 CFG1 0x7 PROD ENPTS 0x1 non sticky edge detection Figure shows pattern match functionality only and accurate timing is not implied Inputs INn are shown synchronized to the System clock Fig 11 Pattern match engine examples non sticky edge detect pin interrupt UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 101 of 326 UM10601 Chapter 9 LPC800 Switch matrix Rev 1 1 24 January 2013 Preliminary user manual 9 1 How to read this chapter 9 2 Features The switch matrix is identical for all LPC800 parts The USART2 and SPI1 functions are only available on parts LPC812M101FDH20 and LPC812M101FDH16 and the corresponding Switch matrix select bits are reserved for all other parts Flexible assignment of digital peripheral functions to pins Enable disable of analog functions 9 3 Basic configuration UM10601 Once configured no clocks are needed for the switch matrix to function The system clock is needed only to write to or read from the pin assignment registers After the switch matrix is configured disable the clock to the switch matrix block in the SYSAHBCLKCTRL register Before activating a
385. on umber 0 20 21641 Comparing fash images L 267 Dl ead Boot code version number ap Wi 21 5 1 13 Compare lt address1 gt address2 no of s pai 267 DYESS nnt ERREUR RES 257 21 5 1 14 ReadUID 257 Chapter 22 LPC800 Power profile API ROM driver 22 1 How to read this chapter 268 22 4 21 Param0 main 274 22 2 Features 268 22 4 28 274 22 3 General 268 22 4 2 3 Param2 system clock 274 224 269 225 Functional description 274 Bo4d set 270 22 5 1 Clock control i 22 4 1 1 system PLL input frequency and 22 5 1 1 Invalid frequency device maximum clock rate Param1 expected system clock 271 exceeded te atte s E 224 1 2 Param2 mode 271 22 5 1 2 Invalid frequency selection system clock divider 22 4 1 3 Param3 system PLL lock time out 272 restrictions AM MN UR A MCA CE 275 2242 _ 272 22 5 1 8 Exact solution cannot be found PLL 275 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary u
386. onality This eliminates the possibility of spurious interrupts as the feature is being enabled Table 90 Pattern match interrupt control register PMCTRL address 0xA000 4028 bit description Bit Symbol Value Description Reset value 0 SEL PMATCH Specifies whether the 8 pin interrupts are controlled by 0 the pin interrupt function or by the pattern match function 0 Pin interrupt Interrupts are driven in response to the standard pin interrupt function 1 Pattern match Interrupts are driven in response to pattern matches 1 ENA RXEV Enables the RXEV output to the ARM cpu and ortoa 0 GPIO output when the specified boolean expression evaluates to true 0 Disabled RXEV output to the cpu is disabled 1 Enabled RXEV output to the cpu is enabled 2322 Reserved Do not write 1s to unused bits 0 31 24 This field displays the current state of pattern matches 0 0 A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs Pattern Match Interrupt Bit Slice Source register The bit slice source register specifies the input source for each of the eight pattern match bit slices Each of the possible eight inputs is selected in the pin interrupt select registers in the SYSCON block See Section 4 6 27 Input 0 corresponds to the pin selected in the PINTSELO register input 1 corresponds to the pin selected in the PINTSEL1 register and So fort
387. only zero should be NA written UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 179 of 326 NXP Semiconductors U M1 0601 Chapter 15 LPC800 USARTO 1 2 Table 161 USART Interrupt Enable read and set register INTENSET address 0x4006 400C USARTO 0x4006 800C USART1 0x4006 CO0C USART2 bit description Bit Symbol Description Reset Value 11 DELTARXBRKEN When 1 enables an interrupt when a change of state has 0 occurred in the detection of a received break condition break condition asserted or deasserted 12 STARTEN When 1 enables an interrupt when a received start bit has 0 been detected 13 FRAMERREN When 1 enables an interrupt when a framing error has been 0 detected 14 PARITYERREN When 1 enables an interrupt when a parity error has been 0 detected 15 RXNOISEEN When 1 enables an interrupt when noise is detected See 0 description of the RXNOISEINT bit in Table 160 31 16 Reserved Read value is undefined only zero should be NA written 15 6 5 USART Interrupt Enable Clear register The INTENCLR register is used to clear bits in the INTENSET register Table 162 USART Interrupt Enable clear register INTENCLR address 0x4006 4010 USARTO 0x4006 8010 USART1 0x4006 C010 USART2 bit description Bit Symbol Description Reset Value 0 RXRDYCLR Writing 1 clears t
388. optionally be protected such that it can only be changed after the warning interrupt time is reached Flag to indicate Watchdog reset The Watchdog clock WDCLK source is the WatchDog oscillator The Watchdog timer can be configured to run in Deep sleep or Power down mode Debug mode 12 3 Basic configuration The WWDT is configured through the following registers e Power to the register interface WWDT PCLK clock In the SYSAHBCLKCTRL register set bit 17 in Table 18 Enable the WWDT clock source the watchdog oscillator in the PDRUNCFG register Table 37 This is the clock source for the timer base For waking up from a WWDT interrupt enable the watchdog interrupt for wake up in the STARTERP register Table 34 12 4 Pin description UM10601 The WWDT has no external pins All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 150 of 326 NXP Semiconductors U M1 0601 Chapter 12 LPC800 Windowed Watchdog Timer WWDT 12 5 General description The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a programmable time if it enters an erroneous state When enabled a watchdog reset is generated if the user program fails to feed reload the Watchdog within a predetermined amount of time When a watchdog window is programmed an early watchdog feed
389. or Power down 17 7 Functional description oe 225 211 17 7 1 Operating modes clock and phase selection 225 17 4 211 s ids 17 5 Generaldescription 213 17722 delay S E 227 17 6 Register description 213 47723 Transfer 228 176 1 SPI Configuration register 215 177 3 Clocking and datarates 229 17 6 2 SPI Delay 216 177 311 Data rate calculations 229 17 6 3 5 15 217 17274 229 17 64 SPI Interrupt Enable read and Set register 218 17 75 lengths greater than 16 bits 229 17 6 5 SPI Interrupt Enable Clear register 220 1776 230 17 6 6 SPI Receiver Data register 220 apter 18 clic Redundanc ec engine Chapter 18 LPC800 Cyclic Redund Check CRC 18 1 How to read this chapter 232 18 6 2 CRC seed 234 18 2 232 18 63 checksum register 234 18 3 232 1864 CHE data register pL ELE 235 184 _ 23
390. parts LPC812M101FDH16 and LPC812M101FDH20 only 17 2 Features Data frames of 1 to 16 bits supported directly Larger frames supported by software Master and slave operation Data can be transmitted to a slave without the need to read incoming data This can be useful while setting up an SPI memory Control information can optionally be written along with data This allows very versatile operation including any length frames One Slave Select input output with selectable polarity and flexible usage Remark Texas Instruments SSI and Microwire modes are not supported 17 3 Basic configuration Configure SPIO 1 using the following registers n the SYSAHBCLKCTRL register set bit 11 and 12 Table 18 to enable the clock to the register interface Clear the SPIO 1 peripheral resets using the PRESETCTRL register Table 7 Enable disable the SPIO 1 interrupts in interrupt slots 40 and 1 in the NVIC Configure the SPIO 1 pin functions through the switch matrix See Section 17 4 e The peripheral clock for both SPls is the system clock see Figure LPC800 clock generation SPIO 1 SYSCON SPI0 1_PCLK system clock Clock divider SYSAHBCLKCTRL 11 12 SPI0 1 clock enable Fig 32 SPI clocking UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 210 of 326
391. peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 lt Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 69 of 326 NXP Semiconductors UM10601 6 5 15 PIOO 7 register Chapter 6 LPC800 I O configuration IOCON Table 63 7 register PIOO 7 address 0x4004 403C bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3
392. ply UART synchronous mode supported API functions uart put line and uart get line do return an interrupt on error See Table 279 and Table 280 UART API return codes are numbered 0x0008 0001 to 0x0008 0005 See Table 282 12 No changes Power No changes profiles 20 4 Pin description When pin PIOO 1 is pulled LOW on reset the part enters ISP mode and the ISP command handler starts up In ISP mode pins PIOO 0 is connected to function RXD and pin PIOO 4 is connected to function UO TXD on the USARTO block 20 5 General description 20 5 1 UM10601 Boot loader The boot loader controls initial operation after reset and also provides the means to accomplish programming of the flash memory via USART This could be initial programming of a blank device erasure and re programming of a previously programmed device or programming of the flash memory by the application program in a running system The boot loader code is executed every time the part is powered on or reset The boot loader can execute the ISP command handler or the user application code A LOW level after reset at the PIOO 1 pin is considered as an external hardware request to start the ISP command handler via USART For details on the boot process see Section 20 6 2 Boot process Remark SRAM location 0x1000 0000 to 0x1000 0050 is not used by the bootloader and the memory content in this area is retained during reset SRAM memor
393. pt 281 23424 12C 287 23 4 6 I2C Master Receive Interrupt 281 23 4 25 12 ROM driver pointer 287 23 4 7 I2C Master Transmit Receive Interrupt 282 23 5 E nctlonal descristion 287 23 4 8 I2C Slave Receive Polling 282 s Pe ermal 287 234 9 12 Slave Transmit Polling 282 23 51 2 5 8 23 4 10 12 Slave Receive Interrupt 283 23 52 2C Master mode set up 2 23 4 11 12C Slave Transmit Interrupt 283 23 5 3 I2C Slave mode set up 8 23 412 I2C Set Slave Address 283 23 5 4 I2C Master Transmit Receive 289 23 4 13 2 Get Memory Size o 283 29 55 12 Slave Mode Transmit Receive 290 23 4 14 IBC gaa 23 5 6 2 291 23 4 15 12 284 Chapter 24 LPC800 USART API ROM driver routines 24 1 How to read this chapter 293 24 4 6 UART get 296 242 Features isses nnn nnn 293 244 7 296 24 3 General 293 24 4 8 UART interrupt service routine 296 5 d API di 2449 296 24 4 1
394. ption 59 PIOO 4 register PIOO 4 address 0x4004 4010 bit description 60 PIOO 3 register PIOO 3 address 0x4004 4014 bit description 61 PIOO 2 register PIOO 2 address 0x4004 4018 bit description 62 PIOO 11 register PIOO 11 address 0x4004 401C bit description 63 PIOO 10 register PIOO 10 address 0x4004 4020 bit description 64 PIOO 16 register PIOO 16 address 0x4004 4024 bit description 65 15 register PIOO 15 address 0x4004 4028 bit description 66 PIOO 1 register PIOO 1 address 0x4004 402C bit description 67 PIOO 9 register PIOO 9 address 0x4004 4034 bit description 68 PIOO 8 register PIOO 8 address 0x4004 4038 bit description 69 PIOO 7 register PIOO 7 address 0x4004 403C bit description 70 PIOO 6 register PIOO 6 address 0x4004 4040 bit description 71 PIOO 0 register PIOO 0 address 0x4004 4044 bit description 72 PIOO 14 register PIOO 14 address 0x4004 4048 bit description 738 GPIO pins available 74 Register overview GPIO port base address 0xA000 0000 75 GPIO port 0 byte pin registe
395. r Table 161 you can customize when the wake up occurs in the USART receive transmit protocol 15 4 Pin description The USART receive transmit and control signals are movable functions and are assigned to external pins through the switch matrix See Section 9 3 1 Connect an internal signal to a package pin to assign the USART functions to pins on the LPC800 package Table 156 USART pin description Function Direction Pin Description SWM register Reference UO TXD any Transmitter output for USARTO Serial transmit data PINASSIGNO Table 96 UO any Receiver input for USARTO Serial receive data PINASSIGNO Table 96 UO RTS any Request To Send output for USARTO Active low signal PINASSIGNO Table 96 indicates that the USARTO is ready to receive data This signal supports inter processor communication through the use of hardware flow control This feature is active when the USART RTS signal is configured to appear on a device pin UO CTS any Clear To Send input for USARTO Active low signal indicates PINASSIGNO Table 96 that the external device that is in communication with the USART is ready to accept data This feature is active when enabled by the CTSEn bit in CFG register and when configured to appear on a device pin When deasserted high by the external device the USART will complete transmitting any character already in progress then stop until CTS is again asserted low UM10601 All information pro
396. r function configurable I O ports through a switch matrix an input pattern match engine and up to 18 general purpose l O pins UM10601 System ARM Cortex M0 processor running at frequencies of up to 30 MHz with single cycle multiplier and fast single cycle I O port ARM Cortex M0 built in Nested Vectored Interrupt Controller NVIC System tick timer Serial Wire Debug SWD and JTAG boundary scan modes supported Micro Trace Buffer MTB supported Memory Up to 16 kB on chip flash programming memory with 64 Byte page write and erase 4 kB SRAM ROM API support Boot loader USART drivers 12C drivers Power profiles Flash In Application Programming IAP and In System Programming ISP Digital peripherals High speed GPIO interface connected to the ARM Cortex MO IO bus with up to 18 General Purpose I O GPIO pins with configurable pull up pull down resistors programmable open drain mode input inverter and glitch filter High current source output driver 20 mA on four pins High current sink driver 20 mA on two true open drain pins GPIO interrupt generation capability with boolean pattern matching feature on eight GPIO inputs Switch matrix for flexible configuration of each I O pin function All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 3 of 326 N
397. r down mode immediately when a start is detected Cleared by software UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 178 of 326 NXP Semiconductors U M1 0601 Chapter 15 LPC800 USARTO 1 2 Table 160 USART Status register STAT address 0x4006 4008 USARTO 0x4006 8008 USART1 0x4006 C008 USART2 bit description Bit Symbol Description Reset Access value 13 FRAMERRINT Framing Error interrupt flag This flag is set when a character is received with 0 W1 a missing stop bit at the expected location This could be an indication of a baud rate or configuration mismatch with the transmitting source 14 PARITYERRINT Parity Error interrupt flag This flag is set when a parity error is detected ina 0 W1 received character 15 RXNOISEINT Received Noise interrupt flag Three samples of received data are taken in 0 W1 order to determine the value of each received data bit except in synchronous mode This acts as a noise filter if one sample disagrees This flag is set when a received data bit contains one disagreeing sample This could indicate line noise a baud rate or character format mismatch or loss of synchronization during data reception 31 16 Reserved Read value is undefined only zero should be written NA NA 1 RO Read only W1 write 1 to clear 15 6 4 USART Interrupt Enable
398. r for the update to take effect at the input of the CLKOUT pin first write a zero to bit 0 of this register then write a one UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 27 of 326 NXP Semiconductors U M1 0601 4 6 17 4 6 18 UM10601 Chapter 4 LPC800 System configuration SYSCON Table 21 CLKOUT clock source update enable register CLKOUTUEN address 0x4004 80E4 bit description Bit Symbol Value Description Reset value 0 ENA Enable CLKOUT clock source update 0 0 No change 1 Update clock source 31 1 Reserved 2 CLKOUT clock divider register This register determines the divider value for the signal on the CLKOUT pin Table 22 CLKOUT clock divider registers CLKOUTDIV address 0x4004 80E8 bit description Bit Symbol Description Reset value 7 0 DIV CLKOUT clock divider values 0 0 Disable CLKOUT clock divider 1 Divide by 1 to 255 Divide by 255 31 8 Reserved USART fractional generator divider value register All USART peripherals share a common clock U_PCLK which can be adjusted by a fractional divider PCLK UARTCLKDIV 1 MULT DIV UARTCLKDIV is the USART clock configured in the UARTCLKDIV register The fractional portion 1 MULT DIV is determined by the two USART fractional divider registers in the SYSCON block 1 The DIV value progr
399. ral purpose digital input output pin Vpp 15 12 6 3 3 V supply voltage Vss 16 13 7 Ground 1 2 3 4 5 6 7 8 9 Pin state at reset for default function Input Al Analog Input Output PU internal pull up enabled pins pulled up to full Vpp level 1 inactive no pull up down enabled 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis includes high current output driver True open drain pin I amp C bus pins compliant with the I2C bus specification for IC standard mode 2 Fast mode and I C Fast mode Plus Do not use this pad for high speed applications like the SPI clock RESET functionality is not available in Deep power down mode Use the WAKEUP pin to reset the chip and wake up from Deep power down mode An external pull up resistor is required on this pin for the Deep power down mode 5 V tolerant pin providing standard digital I O functions with configurable modes configurable hysteresis and analog input When configured as an analog input the digital section of the pin is disabled and the pin is not 5 V tolerant 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis In Deep power down mode pulling this pin LOW wakes up the chip 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and
400. rates the main clock and optionally two additional phases The CCO frequency range is 156 MHz to 320 MHz These clocks are either divided by 2xP by the programmable post divider to create the output clocks or are sent directly to the outputs The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock The output signal of the phase frequency detector is also monitored by the lock detector to signal when the PLL has locked on to the input clock Remark The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz because the main clock is limited to a maximum frequency of 100 MHz All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 38 of 326 NXP Semiconductors U M1 0601 Chapter 4 LPC800 System configuration SYSCON 4 7 1 1 Lock detector The lock detector measures the phase difference between the rising edges of the input and feedback clocks Only when this difference is smaller than the so called lock criterion for more than eight consecutive input clock periods the lock output switches from low to high A single too large phase difference immediately resets the counter and causes the lock signal to drop if it was high Requiring eight phase measurements in a row to be below a certain figure ensures that th
401. ration of shorter than one two or three cycles of a filter clock S MODE 1 2 or 3 For each individual pin the filter clock can be selected from one of seven peripheral clocks PCLKO to 6 which are derived from the main clock using the IOCONCLKDIVO to 6 registers The filter can also be bypassed entirely Any input pulses of duration Tpuise of either polarity will be rejected if Tpulse lt x S MODE Input pulses of one filter clock cycle longer may also be rejected Tpulse TPcLkn S MODE 1 Remark The filtering effect is accomplished by requiring that the input signal be stable for S MODE 1 successive edges of the filter clock before being passed on to the chip Enabling the filter results in delaying the signal to the internal logic and should be done only if specifically required by an application For high speed or time critical functions ensure that the filter is bypassed If the delay of the input signal must be minimized select a faster PCLK and a higher sample mode S MODE to minimize the effect of the potential extra clock cycle If the sensitivity to noise spikes must be minimized select a slower PCLK and lower sample mode Related registers and links All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 54 of 326 NXP Semiconductors UM10601 Chapter 6 LPC800 I O confi
402. rea I2C PARAM Pointer to the I2C PARAM struct I2C RESULT Pointer to the I2C RESULT struct ErrorCode Receives data from master When the task is completed the function returns to the line after the call I2C Slave Transmit Polling Table 261 12C Slave Transmit Polling Routine Prototype Input parameter Return Description I2C Slave Transmit Polling ErrorCode ti2c slave transmit poll IBC HANDLE T Il2C I2C RESULT I2C HANDLE 7T Handle to the allocated SRAM area I2C PARAM Pointer to the I2C PARAM struct I2C RESULT Pointer to the I2C RESULT struct ErrorCode Sends data bytes back to master When the task is completed the function returns to the line after the call All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 282 of 326 NXP Semiconductors UM10601 23 4 10 23 4 11 23 4 12 23 4 13 UM10601 Chapter 23 LPC800 I2C bus ROM API I2C Slave Receive Interrupt Table 262 12 Slave Receive Interrupt Routine Prototype Input parameter Return Description I2C Slave Receive Interrupt ErrorCode_t i2c_slave_receive_intr I2C_HANDLE_T 126 I2C RESULT I2C HANDLE T Handle to the allocated SRAM area I2C PARAM Pointer to the I2C PARAM struct I2C RESULT Pointer to the I2C RESULT struct E
403. reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0x1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 lt Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 57 of 326 NXP Semiconductors UM10601 6 5 3 PIOO 12 register Chapter 6 LPC800 I O configuration IOCON Table 51 PIOO 12 register PIOO 12 address 0x4004 4008 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on
404. ree samples of incoming data Details on how to select the right values for BRG can be found later in this chapter see Section 15 7 1 Remark If software needs to change the baud rate the following sequence should be used 1 Make sure the USART is not currently sending or receiving data 2 Disable the USART by writing a 0 to the Enable bit 0 may be written to the entire registers 3 Write the new BRGVAL 4 Write to the CFG register to set the Enable bit to 1 Table 166 USART Baud Rate Generator register BRG address 0x4006 4020 USARTO 0x4006 8020 USART1 0x4006 C020 USART2 bit description Bit Symbol Description Reset Value 15 0 BRGVAL This value is used to divide the USART input clock to determine the 0 baud rate based on the input clock from the FRG 0 The FRG clock is used directly by the USART function 1 The FRG clock is divided by 2 before use by the USART function 2 The FRG clock is divided by 3 before use by the USART function OxFFFF The FRG clock is divided by 65 536 before use by the USART function 31 16 Reserved Read value is undefined only zero should be written NA USART Interrupt Status register The read only INTSTAT register provides a view of those interrupt flags that are currently enabled This can simplify software handling of interrupts See Table 160 for detailed descriptions of the interrupt flags Table 167 USART Interrupt Status register INTSTAT address 0x4006 4024
405. register in the PCON block Select low power clock for WKT clock in the WKT CTRL register Start the WKT by writing a time out value to the WKT COUNT register Enable interrupt in NVIC and STARTERP registers Enable USART I2C SPI interrupts Provide an external clock signal to the peripheral Configure the USART in synchronous slave mode and I2C and SPI in slave mode Deep power down WAKEUP pin 4 Enable the WAKEUP function in the GPREG4 register in the PMU WKT time out Enable the low power oscillator in the GPREG4 register in the PMU Enable the low power oscillator to keep running in Deep power down mode in the GPREG4 register in the PMU Select low power clock for WKT clock in the WKT CTRL register Start WKT by writing a time out value to the WKT COUNT register 5 6 Register description Table 42 Register overview PMU base address 0x4002 0000 Name Access Address Description Reset Reference offset value PCON R W 0x000 Power control register 0x0 Table 43 GPREGO R W 0x004 General purpose register 0 0x0 Table 44 GPREG1 R W 0x008 General purpose register 1 0x0 Table 44 GPREG2 R W 0x00C General purpose register 2 0x0 Table 44 GPREG3 R W 0x010 General purpose register 3 0x0 Table 44 DPDCTRL R W 0x014 Deep power down control 0x0 Table 45 register UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24
406. reset must be set in the WWDT MOD register Via any of the USART blocks See Section 15 3 2 Configure the USART for wake up Via the 12 See Section 16 3 1 Via any of the SPI blocks See Section 17 3 1 Deep power down mode In Deep power down mode power and clocks are shut off to the entire chip with the exception of the WAKEUP pin and the self wake up timer During Deep power down mode the contents of the SRAM and registers are not retained except for a small amount of data which can be stored in the general purpose registers of the PMU block All functional pins are tri stated in Deep power down mode except for the WAKEUP pin Remark Setting bit 3 in the PCON register Table 43 prevents the part from entering Deep power down mode Power configuration in Deep power down mode Deep power down mode has no configuration options All clocks the core and all peripherals are powered down Only the WAKEUP pin and the self wake up timer are powered Programming Deep power down mode The following steps must be performed to enter Deep power down mode 1 Pull the WAKEUP pin externally HIGH All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 50 of 326 NXP Semiconductors U M1 0601 o Inm Chapter 5 LPC800 Reduced power modes and Power Management Ensure that bit 3 in the P
407. rface handles data frame sizes from 1 to 16 bits directly Larger sizes can be handled by splitting data up into groups of 16 bits or less For example 24 bits can be supported as 2 groups of 16 bits and 8 bits or 2 groups of 12 bits among others Frames of any size including greater than 32 bits can supported in the same way Details of how to handle larger data widths depend somewhat on other SPI configuration options For instance if it is intended for Slave Selects to be deasserted between frames then this must be suppressed when a larger frame is split into more than one part Sending 2 groups of 12 bits with SSEL deasserted between 24 bit increments for instance would require changing the value of the EOF bit on alternate 12 bit frames UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 229 of 326 NXP Semiconductors U M1 0601 17 7 6 UM10601 Chapter 17 LPC800 SPI0 1 Data stalls A stall for Master transmit data can happen in modes 0 and 2 when SCK cannot be returned to the rest state until the MSB of the next data frame can be driven on MOSI In this case the stall happens just before the final clock edge of data if the next piece of data is not yet available A stall for Master receive can happen when a receiver overrun would otherwise occur if the transmitter was not stalled In modes 0 and
408. ritten Should be 64 128 256 512 1024 CMD SUCCESS SRC ADDR ERROR Address not on word boundary DST ADDR ERROR Address not on correct boundary SRC ADDR NOT MAPPED DST ADDR NOT MAPPED COUNT ERROR Byte count is not 64 128 256 512 1024 SECTOR NOT PREPARED FOR WRITE OPERATION BUSY CMD LOCKED PARAM ERROR CODE READ PROTECTION ENABLED This command is used to program the flash memory The Prepare Sector s for Write Operation command should precede this command The affected sectors are automatically protected again once the copy command is successfully executed The boot block cannot be written by this command This command is blocked when code read protection is enabled C 0 268467504 512 lt CR gt lt LF gt copies 512 bytes from the RAM address 0x1000 0800 to the flash address 0 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 254 of 326 NXP Semiconductors UM10601 Chapter 21 LPC800 Flash ISP and IAP programming 21 5 1 8 Go address lt mode gt 21 5 1 9 UM10601 Table 226 UART ISP Go command Command Input Return Code Description Example G Address Flash or RAM address from which the code execution is to be started This address should be on a word boundary Mode T Execute program in Thumb Mode CMD_SUCCESS ADDR_E
409. rom all slices or slice combinations can be connected to the ARM RXEV request and to pin function GPIO INT BMAT through the switch matrix movable function register PINASSIGNS Table 104 8 3 1 Configure pins as pin interrupts or as inputs to the pattern match engine Follow these steps to configure pins as pin interrupts 1 Determine the pins that serve as pin interrupts on the LPC800 package See the data sheet for determining the GPIO port pin number associated with the package pin 2 For each pin interrupt program the GPIO port pin number into one of the eight PINTSEL registers in the SYSCON block Remark The port pin number serves to identify the pin to the PINTSEL register Any function including GPIO can be assigned to this pin through the switch matrix 3 Enable each pin interrupt in the NVIC Once the pin interrupts or pattern match inputs are configured you can set up the pin interrupt detection levels or the pattern match boolean expression See Section 4 6 27 Pin interrupt select registers in the SYSCON block for the PINTSEL registers 8 4 Pin description The inputs to the pin interrupt and pattern match engine are determined by the pin interrupt select registers in the SYSCON block See Section 8 3 1 The pattern match engine output is assigned to an external pin through the switch matrix See Section 9 3 1 Connect an internal signal to a package pin for the steps that you need to follow to assign the GP
410. rorCode t i2c master tx rx poll l2C HANDLE 126 I2C Master Transmit and Receive Table 256 I2C RESULT Polling ErrorCode ti2c master transmit intr 2C HANDLE T Il2C PARAM 12C Master Transmit Interrupt Table 257 I2C RESULT ErrorCode t i2c master receive intr J2C HANDLE T 12C PARAM 12C Master Receive Interrupt Table 258 I2C RESULT ErrorCode ti2c master tx rx intr 2C HANDLE T I2C I2C Master Transmit Receive Table 259 I2C RESULT Interrupt UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 278 of 326 NXP Semiconductors UM10601 Table 252 12 API calls Chapter 23 LPC800 I2C bus ROM API API call ErrorCode t i2c slave receive poll lPC HANDLE 126 I2C RESULT ErrorCode ti2c slave transmit poll IBC HANDLE T l2C I2C RESULT ErrorCode t i2c slave receive intr I 2C HANDLE T I2C I2C RESULT ErrorCode t i2c slave transmit intr J2C HANDLE 12C_PARAM I2C RESULT ErrorCode ti2c set slave addr I2C HANDLE T slave 0 3 slave mask 0 3 uint32 ti2c get mem size void I2C HANDLE T i2c setup i2c base adar start of ram ErrorCode t i2c set bitrate Il2C HANDLE P in hz bitrate in bps uint32 ti2c get firmware version void I2
411. rovided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 36 of 326 NXP Semiconductors UM10601 Chapter 4 LPC800 System configuration SYSCON Power configuration register PDRUNCFG address 0x4004 8238 bit description Table 37 Bit Symbol 0 IRCOUT PD 1 PD 2 FLASH PD 3 BOD PD 4 5 SYSOSC PD 6 WDTOSC PD 7 SYSPLL PD 11 8 1442 15 ACMP 31 16 Value Description IRC oscillator output power Powered Powered down IRC oscillator power down Powered Powered down Flash power down Powered Powered down BOD power down Powered Powered down Reserved Crystal oscillator power down Powered Powered down Watchdog oscillator power down Changing this bit to powered down has no effect when the LOCK bit in the WWDT MOD register is set In this case the watchdog oscillator is always running Powered Powered down System PLL power down Powered Powered down Reserved Always write these bits as 061101 Reserved Always write these bits as 06110 Analog comparator power down Powered Powered down Reserved Reset value 0 0b1101 0b110 1 4 6 33 Device ID register This device ID register is a read only register and contains the part ID for each LPC800 part This register is also read by the ISP IAP commands see Table 230 UM10601 All information provided in this docum
412. rrorCode Receives data from master Program control will be returned immediately and task will be completed on an interrupt driven basis When task is completed the callback function is called I2C Slave Transmit Interrupt Table 263 12C Slave Transmit Interrupt Routine Prototype Input parameter I2C Slave Transmit Interrupt ErrorCode_t i2c_slave_transmit_intr I2C_HANDLE_T 12C_PARAM I2C RESULT I2C HANDLE T Handle to the allocated SRAM area I2C PARAM Pointer to the I2C PARAM struct I2C RESULT Pointer to the I2C RESULT struct Return ErrorCode Description Sends data to the Master Program control will be returned immediately and task will be completed on an interrupt driven basis When task is completed the callback function is called I2C Set Slave Address Table 264 12 Set Slave Address Routine I2C Set Slave Address Prototype ErrorCode ti2c set slave addr I2C HANDLE slave O 3 Input parameter slave mask O0 3 I2C HANDLE T Handle to the allocated SRAM area Slave addr O0 3 unint32 variable 7 bit slave address Slave mask 0 3 unint32 variable Slave address mask Return ErrorCode Description Sets the slave address and associated mask The set slave addr function supports four 7 bit slave addresses and masks I2C Get Memory Size Table 265 12C Get Memory Size Routine I2C Get Memory Size Prototype uint32 t i2c get mem size void All in
413. rrupts during UART ISP The boot block interrupt vectors located in the boot block of the flash are active after any reset All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 266 of 326 NXP Semiconductors U M1 0601 21 6 2 2 21 6 2 3 21 6 2 4 21 6 3 21 6 3 1 21 6 3 2 UM10601 Chapter 21 LPC800 Flash ISP and IAP programming Interrupts during IAP The on chip flash memory is not accessible during erase write operations When the user application code starts executing the interrupt vectors from the user flash area are active Before making any IAP call either disable the interrupts or ensure that the user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM The IAP code does not use or disable interrupts RAM used by ISP command handler The stack of ISP commands is located at 0x1000 0270 The maximum stack usage is 540 byte and grows downwards RAM used by IAP command handler The maximum stack usage in the user allocated stack space is 148 bytes and grows downwards Debugging Comparing flash images Depending on the debugger used and the IDE debug settings the memory that is visible when the debugger connects might be the boot ROM the internal SRAM or the flash To help determine which memory is present in the current debug environment check the value con
414. rs B 0 17 addresses 0xA000 0000 BO to OxA000 0012 B17 bit description GPIO port 0 word pin registers W 0 17 addresses 0xA000 1000 WO to 0x5000 1048 W17 bit description 76 GPIO direction port 0 register DIRO address 0xA000 2000 bit description 76 GPIO mask port 0 register MASKO address 0xA000 2080 bit description 76 GPIO port 0 pin register PINO address 0xA000 2100 bit 77 GPIO masked port 0 pin register MPINO address 0xA000 2180 bit description 77 GPIO set port 0 register SETO address 0xA000 2200 bit 77 GPIO clear port 0 register CLRO address 0xA000 2280 bit lt 78 GPIO toggle port 0 register address 0xA000 2300 bit description 78 SCTPin interrupt pattern match engine pin descrIptiob wae 81 Register overview Pin interrupts pattern match All information provided in this document is subject to legal disclaimers Chapter 28 Supplementary information engine base address OxA000 4000 86 Table 80 Pin interrupt mode register ISEL address 0xA000 4000 bit description 87 Table 81 Pin interrupt level or rising edge interrupt enable register IENR address 0xA000 4004 bit description 87 Table 82 Pin interrupt
415. rs when the UNIFY bit is set 18 AUTOLIMIT H A one in this bit will cause a match on match register 0 to be treated as a de facto LIMIT condition without the need to define an associated event As with any LIMIT event this automatic limit causes the counter to be cleared to zero in uni directional mode or to change the direction of count in bi directional mode Software can write to set or clear this bit at any time This bit is not used when the UNIFY bit is set 31 19 Reserved 10 6 2 SCT control register If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers CTRL L and CTRL H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation bits in this register can be written to when the counter is stopped or halted When the counter is running the only bits that can be written are STOP or HALT Other bits can be written in a subsequent write after HALT is set to 1 Table 109 SCT control register CTRL address 0x5000 4004 bit description Bit Symbol Value Description Reset value 0 DOWN L This bit is 1 when the L or unified counter is counting down Hardware sets this bit 0 when the counter limit is reached and BIDIR is 1 Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0 1 STOP L When this bit is 1 and
416. rt addresses can be read and written as bytes halfwords or words ext indicates that the data read after reset depends on the state of the pin which in turn may depend on an external source Table 68 Register overview GPIO port base address 0xA000 0000 Name Access Address Description Reset Width Reference offset value BO to B17 R W 0x0000 to 0x0012 Byte pin registers port 0 pins ext byte 8 bit Table 69 PIOO 0 to PIOO 17 Wo to W17 R W 0x1000 to 0x1048 Word pin registers port 0 ext word 32 bit Table 70 DIRO R W 0x2000 Direction registers port 0 0 word 32 bit Table 71 MASKO R W 0x2080 Mask register port 0 0 word 32 bit Table 72 PINO R W 0x2100 Port pin register port 0 ext word 82 bit Table 73 MPINO R W 0x2180 Masked port register port 0 ext word 32 bit Table 74 SETO R W 0x2200 Write Set register for port 0 0 word 32 bit Table 75 Read output bits for port 0 CLRO WO 0x2280 Clear port 0 NA word 32 bit Table 76 NOTO WO 0x2300 Toggle port 0 NA word 32 bit Table 77 7 6 1 GPIO port byte pin registers Each GPIO pin has a byte register in this address range Software typically reads and writes bytes to access individual pins but can read or write halfwords to sense or set the state of two pins and read or write words to sense or set the state of four pins Table 69 GPIO port 0 byte pin registers B 0 17 addresses 0xA000 0000 BO to 0xA000 0012 B17 bit description Bit Symbol Description Reset Access value 0
417. rt has one direction register for configuring the port pins as inputs or outputs Table 71 GPIO direction port 0 register DIRO address 0 000 2000 bit description Bit Symbol Description Reset Access value 17 0 DIRPO Selects pin direction for pin PIOO n bit 0 PIOO 0 bit1 0 R W PIOO 1 bit 17 PIOO 17 0 input 1 output 31 18 Reserved 0 GPIO port mask registers These registers affect writing and reading the MPORT registers Zeroes in these registers enable reading and writing ones disable writing and result in zeros in corresponding positions when reading Table 72 GPIO mask port 0 register MASKO address 0xA000 2080 bit description Bit Symbol Description Reset Access value 17 0 MASKPO Controls which bits corresponding to PIOO n are active in the 0 R W POMPORT register bit PIOO 0 bit 1 PIOO 1 bit 17 PIOO 17 0 Read MPORT pin state write MPORT load output bit 1 Read MPORT 0 write MPORT output bit not affected 31 18 Reserved 0 GPIO port pin registers Reading these registers returns the current state of the pins read regardless of direction masking or alternate functions except that pins configured as analog I O always read as 05 Writing these registers loads the output bits of the pins written to regardless of the Mask register All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved
418. rupt mode configured in the ISEL register f the pin interrupt mode is edge sensitive PMODE 0 the falling edge interrupt is enabled e If the pin interrupt mode is level sensitive PMODE 1 the active level of the level interrupt HIGH or LOW is configured Table 84 Pin interrupt active level or falling edge interrupt enable register IENF address 0xA000 4010 bit description Bit Symbol Description Reset Access value 7 0 ENAF Enables the falling edge or configures the active level interrupt 0 R W for each pin interrupt Bit n configures the pin interrupt selected in PINTSELn 0 Disable falling edge interrupt or set active interrupt level LOW 1 Enable falling edge interrupt enabled or set active interrupt level HIGH 31 8 Reserved Pin interrupt active level or falling edge interrupt set register For each of the 8 pin interrupts selected in the PINTSELn registers see Section 4 6 27 one bit in the SIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register f the pin interrupt mode is edge sensitive PMODE 0 the falling edge interrupt is set e If the pin interrupt mode is level sensitive PMODE 1 the HIGH active interrupt is selected All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 88 of 326
419. s NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 270 of 326 NXP Semiconductors U M1 0601 22 4 1 1 22 4 1 2 UM10601 Chapter 22 LPC800 Power profile ROM driver define CPU_FREQ_EQU define CPU_FREQ_LTE define CPU_FREQ_GTE define CPU_FREQ_APPROX set_pll result options define PLL_CMD_SUCCESS 0 define PLL_INVALID_FREQ 1 define PLL INVALID MODE 2 3 4 c define PLL FREQ NOT FOUND define PLL NOT LOCKED For a simplified clock configuration scheme see Figure 44 For more details see Figure 3 ParamO system PLL input frequency and Param1 expected system clock set pll configures a setup in which the main clock does not exceed 30 MHz see Figure 44 It easily finds a solution when the ratio between the expected system clock and the system PLL input frequency is an integer value but it can also find solutions in other cases The system PLL input frequency must be between 10000 to 25000 kHz 10 MHz to 25 MHz inclusive The expected system clock Param 1 must be between 1 and 30000 kHz inclusive If either of these requirements is not met set pll returns PLL INVALID FREQ and returns as Result since the PLL setting is unchanged Param2 mode The first priority of set pllis to find a setup that generates the system clock at exactly the rate specified in 1 If it is unlikely that an exact match ca
420. s 18 5 General description The Cyclic Redundancy Check CRC generator with programmable polynomial settings supports several CRC standards commonly used UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 232 of 326 NXP Semiconductors UM10601 Chapter 18 LPC800 Cyclic Redundancy Check CRC engine CRC CRC SUM V Fig 39 CRC block diagram MODE 1 CRC SEED CRCID comT POLY 2 ph t p3 MUX D S E I CRC 16 CRC COMP REVERSE B2 MUX 1 s BIT J POLY MUX REG B1 COMP REVERSE E L L CRC 32 CRC WR BUF POLY CRC FSM UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 233 of 326 NXP Semiconductors U M1 0601 Chapter 18 LPC800 Cyclic Redundancy Check CRC engine 18 6 Register description 18 6 1 18 6 2 18 6 3 UM10601 Table 201 Register overview CRC engine base address 0x5000 0000 Name Access Address Description Reset value Reference offset MODE R W 0x000 CRC mode register 0x0000 0000 Table 202 SEED R W 0x004 CRC seed regist
421. s UM10601 Chapter 28 Supplementary information Chapter 28 Supplementary information 28 1 Abbreviations 311 28 2 References 311 28 3 Legal 312 28 3 1 Definitions Rem 312 28 3 2 Disclaimers ores ees 312 28 3 3 Trademarks 312 28 4 Tables iiiniclclacilceex enc ks 313 28 5 FIQUICS see 318 28 6 ContentS 32 23 55 2 ux 319 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information B V 2013 For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 24 January 2013 Document identifier UM10601 All rights reserved
422. s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities 28 3 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP B V NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 312 of 326 NXP Semiconductors UM10601 Chapter 28 Supplementary information 28 4 Tables Table 1 Ordering information 5 lt 30 Table 2 Ordering lt 5
423. s cates 165 14 5 1 165 14 3 Basic configuration 165 14 6 Register 166 144 165 14 6 1 Control register 166 14 6 2 Count register 167 Chapter 15 LPC800 USARTO0 1 2 15 1 How to read this chapter 168 15 6 7 USART Receiver Data with Status register 181 1 amp 2 Features cesser cnr RR ana 168 15 68 USART Transmitter Data Register 182 15 3 168 15 69 USART Baud Rate Generator register 183 15 8 1 Configure the USART clock and baud rate 169 19 9 10 USART Interrupt Status register 183 15 3 2 Configure the USART for wake up 170 15 7 Functional description 184 15 3 2 1 Wake up from Sleep mode 170 15 7 1 Clocking and Baud 184 15 3 2 2 Wake up from Deep sleep or Power down 15 7 1 1 Fractional Rate Generator FRG 184 171 15 7 1 2 Baud Rate Generator BRG 185 15 4 Pin 171 15 7 1 3 Baud rate calculations 185 455 General description 172 15 7 2 Synchronous mode 185 DBSEHIUOIN cra tasi 15 7 3 Flow
424. s illustrated in the Figure 42 The number of parameters and results vary according to the IAP command The maximum number of parameters is 5 passed to the Copy RAM to FLASH command The maximum number of results is 4 returned by the ReadUID command The command handler sends the status code INVALID COMMAND when an undefined command is received The IAP routine resides at OX1FFF 1FFO location and it is thumb code The IAP function could be called in the following way using C Define the IAP location entry point Since the Oth bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address define IAP LOCATION Ox1fff ffl Define data structure or pointers to pass IAP command table and result table to the IAP function unsigned long command 5 unsigned long result 4 or unsigned long command unsigned long result command unsigned long 0 result unsigned long 0 Define pointer to function type which takes two parameters and returns void Note the IAP returns the result with the base address of the table residing in R1 typedef void IAP unsigned int unsigned int IAP iap_entry All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 259 of 326 NXP Semiconductors U M1 0601 UM10601 Chapter 21 LPC800 Fla
425. s in the REGMODE register determine whether each set of Match Capture registers uses the match or capture functionality REGMODEn 1 Registers operate as match and reload registers REGMODEn 0 Registers operate as capture and capture control registers UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 118 of 326 NXP Semiconductors UM10601 Chapter 10 LPC800 State Configurable Timer SCT Table 107 Register overview State Configurable Timer base address 0x5000 4000 Name Access Address Description Reset value Reference offset CONFIG R W 0x000 SCT configuration register 0x0000 7E00 Table 108 CTRL R W 0x004 SCT control register 0x0004 0004 Table 109 CTRL_L R W 0x004 SCT control register low counter 16 bit Table 109 CTRL_H R W 0x006 SCT control register high counter 16 bit Table 109 LIMIT R W 0x008 SCT limit register 0x0000 0000 Table 110 LIMIT L R W 0x008 SCT limit register low counter 16 bit Table 110 LIMIT_H R W 0x00A SCT limit register high counter 16 bit Table 110 HALT R W Ox00C SCT halt condition register 0x0000 0000 Table 111 HALT L R W 0x00C SCT halt condition register low counter 16 bit Table 111 HALT_H R W Ox00E SCT halt condition register high counter 16 bit Table 111 STOP R W 0x010 SCT stop condition register 0x0000 0000 Table 112 STOP_L R W 0x010 SCT stop condition
426. s received Anerror condition is detected When using the interrupt function calls the callback functions must be define Upon the completion of a read write as specified by the PARAM structure the callback functions will be invoked 12C time out feature timeout Timeout time value Specifies the timeout interval value in increments of 16 I2C function clocks Min value is 16 if timeout 0 timeout feature is disabled if timeout 0 time value is timeout 16 i2c function clock ErrorCode t i2c set timeout I2C HANDLE T h_i2c uint32 t timeout I2C DRIVER TypeDef h declare pointer to i2c structure handle h I2C DRIVER TypeDef h assign handle pointer address if timeout 0 h i2c base TimeOut timeout 1 lt lt 4 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 291 of 326 NXP Semiconductors U M1 0601 Chapter 23 LPC800 I2C bus ROM API Enable timeout feature h gt i2c_base gt CFG BI2C TIMEOUT EN else disable timeout feature h gt i2c_base gt CFG amp BI2C TIMEOUT EN return LPC OK i2c set timeout UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 292 of 326 UM10601 Chapter 24 LPC800
427. s to be powered down in Deep sleep and Power down modes An exception are the BOD and watchdog oscillator which can be configured to remain running through this register The WDTOSC PD value written to the PDSLEEPCFG register is overwritten if the LOCK bit in the WWDT MOD register see Table 142 is set See Section 12 5 3 for details Table 35 Deep sleep configuration register PDSLEEPCFG address 0x4004 8230 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0b111 3 BOD PD BOD power down control for Deep sleep and 1 Power down mode 0 Powered 1 Powered down 5 4 Reserved 11 WDTOSC PD Watchdog oscillator power down control for 1 Deep sleep and Power down mode Changing this bit to powered down has no effect when the LOCK bit in the WWDT MOD register is set In this case the watchdog oscillator is always running 0 Powered 1 Powered down 15 7 Reserved 0b111111111 31 16 Reserved 0 Wake up configuration register This register controls the power configuration of the device when waking up from Deep sleep or Power down mode All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 35 of 326 NXP Semiconductors U M1 0601 4 6 32 UM10601 Chapter 4 LPC800 System configuration SYSCON Table 36 Wake up configuration register PDAWAKECFG address 0x4004 8234 bit d
428. scillator can be left running in Deep sleep mode if required for the WWDT The BOD circuit can be left running in Deep sleep mode if required by the application Programming Deep sleep mode The following steps must be performed to enter Deep sleep mode 1 The PD bits in the PCON register must be set to Ox1 Table 43 2 Select the power configuration in Deep sleep mode in the PDSLEEPCFG Table 35 register 3 Select the power configuration after wake up in the PDAWAKECFG Table 36 register 4 If any of the available wake up interrupts are needed for wake up enable the interrupts in the interrupt wake up registers Table 33 Table 34 and in the NVIC 5 Write one to the SLEEPDEEP bit in the ARM Cortex M0 SCR register 6 Use the ARM WFI instruction Wake up from Deep sleep mode The microcontroller can wake up from Deep sleep mode in the following ways Signal on one of the eight pin interrupts selected in Table 32 Each pin interrupt must also be enabled in the STARTERPO register Table 33 and in the NVIC BOD signal if the BOD is enabled in the PDSLEEPCFG register BOD interrupt using the deep sleep interrupt wake up register 1 Table 34 The BOD interrupt must be enabled in the NVIC The BOD interrupt must be selected in the BODCTRL register Reset from the BOD circuit In this case the BOD circuit must be enabled in the PDSLEEPCFG register and the BOD reset must be enabled in the BODCTRL register Tab
429. sclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 227 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 17 7 2 3 Transfer delay The Transfer delay value controls the minimum amount of time that SSEL is deasserted between transfers because the EOT bit 1 When Transfer delay 0 SSEL may be deasserted for a minimum of one SPI clock time Transfer delay is illustrated by the examples in Figure 37 Frame delay 0 Frame delay 2 Pre delay 0 Post delay 0 Mosi Y MSB Y LSB MSB isy fo ah ane d Lo ae ie NEC NINE CUN TRU lt gt lt i First data frame Frame delay Second data frame Frame delay 1 Frame delay 2 Pre delay 0 Post delay 0 X use i X use 4 gt lt gt lt gt First data frame Frame delay Second data frame Fig 37 Transfer delay UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 228 of 326 NXP Semiconductors U M1 0601 Chapter 17 LPC800 SPI0 1 17 7 3 Clocking and data rates In order to use the SPI clocking details must be defined This includes configuring the system clock and selection of the clock divider value in DIV See Figure 32 17 7 3 1 Data rate calculations The SPI interface is designe
430. select register This register selects the clock source for the system PLL The SYSPLLCLKUEN register see Section 4 6 9 must be toggled from LOW to HIGH for the update to take effect Table 13 System PLL clock source select register SYSPLLCLKSEL address 0x4004 8040 bit description Bit Symbol Value Description Reset value 1 0 SEL System PLL clock source 0 0x0 IRC 0 1 Crystal Oscillator SYSOSC 0x2 Reserved 0x3 CLKIN External clock input 31 2 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 23 of 326 NXP Semiconductors U M1 0601 4 6 9 4 6 10 4 6 11 Chapter 4 LPC800 System configuration SYSCON System PLL clock source update register This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to In order for the update to take effect first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN Table 14 System PLL clock source update enable register SYSPLLCLKUEN address 0x4004 8044 bit description Bit Symbol Value Description Reset value 0 ENA Enable system PLL clock source update 0 0 No change 1 Update clock source 31 1 Reserved a Main clock source select register This register selects the main system clock which can be the system PLL sys pllc
431. ser manual Rev 1 1 24 January 2013 324 of 326 NXP Semiconductors UM10601 Chapter 28 Supplementary information 22 5 1 4 System clock less than or equal to the expected 22 5 2 Power 276 eg ut uere 275 22 5 2 4 Invalid frequency device maximum clock rate 22 5 1 5 System clock greater than or equal to the exceeded 276 expected 275 22 5 2 2 applicable power setup 276 22 5 1 6 System clock approximately equal to the expected Value et ede RR 276 Chapter 23 LPC800 I2C bus ROM 23 1 How to read this chapter 277 23 4416 12C Get Firmware Version 284 28 2 bros anniari rinin 277 23 417 12 Get 284 23 3 General 277 E value ae 2 pci au 23 4 20 12 Status 285 andler 23 4 21 12C ROM driver variables 285 23 42 12 Master Transmit Polling 280 294214 12 285 23 4 3 I2C Master Receive Polling 280 23 4 2 and RESULT structure 286 23 4 4 I2C Master Transmit and Receive Polling 281 23 4 03 Error structure 286 23 4 5 I2C Master Transmit Interru
432. ser manual Rev 1 1 24 January 2013 117 of 326 NXP Semiconductors U M1 0601 Chapter 10 LPC800 State Configurable Timer SCT clock logic CLKMODE CKSEL INSYNC SCT clock System clock input edges inputs preClock events LIMIT H select LIMIT L e prescaler H H counter counter H counter L Unified counter mux STOP START HALT mux prescaler L select STOP L START L HALT L e L counter CTRL H CTRL L Fig 15 SCT counter and select logic 10 6 Register description The register addresses of the State Configurable Timer are shown in Table 107 For most of the SCT registers the register function depends on the setting of certain other register bits 1 The UNIFY bit in the CONFIG register determines whether the SCT is used as one 32 bit register for operation as one 32 bit counter timer or as two 16 bit counter timers named L and H The setting of the UNIFY bit is reflected in the register map UNIFY 1 Only one register is used for operation as one 32 bit counter timer UNIFY 0 Access the L and registers by a 32 bit read or write operation or can be read or written to individually for operation as two 16 bit counter timers Typically the UNIFY bit is configured by writing to the CONFIG register before any other registers are accessed 2 The REGMODEn bit
433. setting INTPIN to 0x5 in PINTSELO selects pin 5 for pin interrupt 0 To determine the GPIO port pin number on a given LPC800 package see the pin description table in the data sheet Remark The GPIO port pin number serves to identify the pin to the PINTSEL register Any digital input function including GPIO can be assigned to this pin through the switch matrix Each of the 8 pin interrupts must be enabled in the NVIC using interrupt slots 24 to 31 see Table 3 To use the selected pins for pin interrupts or the pattern match engine see Section 8 5 2 Pattern match engine All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 32 of 326 NXP Semiconductors U M1 0601 Chapter 4 LPC800 System configuration SYSCON Table 32 Pin interrupt select registers PINTSEL 0 7 address 0x4004 8178 PINTSELO to 0x4004 8194 PINTSEL7 bit description Bit Symbol Description Reset value 5 0 INTPIN Pin number select for pin interrupt or pattern match engine input 0 PIOO 0 to PIOO 17 correspond to numbers 0 to 17 31 6 Reserved 4 6 28 Start logic 0 pin wake up enable register The STARTERPO register enables the selected pin interrupts for wake up from deep sleep mode and power down modes Remark Also enable the corresponding interrupts in the NVIC See Table 3 Connection of interrupt so
434. sh ISP and IAP programming Setting function pointer iap_entry IAP IAP LOCATION Whenever you wish to call IAP you could use the following statement iap entry command result As per the ARM specification The ARM Thumb Procedure Call Standard SWS ESPC 0002 A 05 up to 4 parameters can be passed in the rO r1 r2 and r3 registers respectively Additional parameters are passed on the stack Up to 4 parameters can be returned in the rO r1 r2 and r3 registers respectively Additional parameters are returned indirectly via memory Some of the IAP calls require more than 4 parameters If the ARM suggested scheme is used for the parameter passing returning then it might create problems due to difference in the C compiler implementation from different vendors The suggested parameter passing scheme reduces such risk The flash memory is not accessible during a write or erase operation IAP commands which results in a flash write erase operation use 32 bytes of space in the top portion of the on chip RAM for execution The user program should not be use this space if IAP flash programming is permitted in the application Table 236 IAP Command Summary IAP Command Command Code Described in Prepare sector s for write operation 50 decimal Table 237 Copy RAM to flash 51 decimal Table 238 Erase sector s 52 decimal Table 239 Blank check sector s 53 decimal Table 240 Read Part ID 54 decimal Table 241 Read Boot code version 55 de
435. sideration where applicable 5 DST ADDR NOT MAPPED Destination address is not mapped in the memory map Count value is taken in to consideration where applicable 6 COUNT ERROR Byte count is not multiple of 4 or is not a permitted value 7 INVALID SECTOR Sector number is invalid 8 SECTOR NOT BLANK Sector is not blank 9 SECTOR NOT PREPARED Command to prepare sector for write operation was FOR WRITE OPERATION not executed 10 COMPARE ERROR Source and destination data is not same 11 BUSY Flash programming hardware interface is busy 21 6 Functional description 21 6 1 21 6 1 1 21 6 1 2 21 6 1 3 21 6 2 21 6 2 1 UM10601 UART Communication protocol All UART ISP commands should be sent as single ASCII strings Strings should be terminated with Carriage Return CR and or Line Feed LF control characters Extra lt CR gt and lt LF gt characters are ignored All ISP responses are sent as lt CR gt lt LF gt terminated ASCII strings Data is sent and received in plain binary format UART ISP command format Command Parameter 0 Parameter 1 Parameter_n lt CR gt lt LF gt Data Data only for Write commands UART ISP response format Return_Code lt CR gt lt LF gt Response_0 lt CR gt lt LF gt Response_1 lt CR gt lt LF gt Response n CR LF Data Data only for Read commands UART ISP data format The data stream is in plain binary format Memory and interrupt use for ISP and IAP Inte
436. smit intr l 2C HANDLE T I2C PARAM I2C RESULT I2C HANDLE T Handle to the allocated SRAM area I2C Pointer to the I2C PARAM struct I2C RESULT Pointer to the I2C RESULT struct ErrorCode Transmits bytes in the send buffer to a slave The slave address with the R W bit 0 is expected in the first byte of the send buffer STOP condition is sent at end unless stop flag 20 Program control will be returned immediately and task will be completed on an interrupt driven basis When task is completed the callback function is called I2C Master Receive Interrupt Table 258 12C Master Receive Interrupt Routine Prototype Input parameter Return Description I2C Master Receive Interrupt ErrorCode t i2c master receive intr 2C HANDLE 12C_PARAM I2C RESULT I2C HANDLE T Handle to the allocated SRAM area I2C Pointer to the I2C PARAM struct I2C RESULT Pointer to the I2C RESULT struct ErrorCode Receives bytes from slave and put into receive buffer After the task is finished the slave address with the R W bit 1 is in the first byte of the receive buffer STOP condition is sent at end unless stop flag 20 Program control will be returned immediately and task will be completed on an interrupt driven basis When task is completed the callback function is called All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights
437. source for bit slice 3 Input 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Selects pin interrupt input 0 as the source to bit slice 3 Selects pin interrupt input 1 as the source to bit slice 3 Selects pin interrupt input 2 as the source to bit slice 3 Selects pin interrupt input 3 as the source to bit slice 3 Selects pin interrupt input 4 as the source to bit slice 3 Selects pin interrupt input 5 as the source to bit slice 3 Selects pin interrupt input 6 as the source to bit slice 3 Selects pin interrupt input 7 as the source to bit slice 3 All information provided in this document is subject to legal disclaimers Reset value 0 NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 92 of 326 NXP Semiconductors UM10601 Chapter 8 LPC800 Pin interrupts pattern match engine Table 91 Pattern match bit slice source register PMSRC address 0xA000 402C bit description Bit Symbol 22 20 SRC4 25 28 SRC5 28 26 SRC6 31 29 SRC7 Value 0x0 0 1 0 2 0x3 0 4 0 5 0 6 0 7 0 0 0 1 0 2 0x3 0 4 0 5 0 6 0 7 0 0 0 1 0 2 0x3 0 4 0 5 0 6 0 7 0 0 0 1 0 2 0x3 0 4 0 5 0 6 0 7 Description Selects the input source for bit slice 4 Input 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Selects pin interrupt input O as the source to bit slice 4 Selects pin interrup
438. state reading this bit fields returns 1 OXOOFF FFFF 31 Reserved 0 Control register The control register configures the the mode for each MRT and enables the interrupt Table 137 Control register CTRL 0 3 address 0x4000 4008 CTRLO to 0x4000 4038 CTRL3 bit description Bit Symbol Value Description Reset value 0 INTEN Enable the TIMERn interrupt 0 0 Disable 1 Enable 2 1 MODE Selects timer mode 0 0x0 Repeat interrupt mode 0 1 One shot interrupt mode 0x2 Reserved 0x3 Reserved 31 3 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 147 of 326 NXP Semiconductors U M1 0601 Chapter 11 LPC800 Multi Rate Timer MRT 11 6 4 Status register This register indicates the status of each MRT Table 138 Status register STAT 0 3 address 0x4000 400C STATO to 0x4000 403C STAT3 bit description Bit Symbol Value Description Reset value 0 INTFLAG Monitors the interrupt flag 0 0 No pending interrupt Writing a zero is equivalent to no operation 1 Pending interrupt The interrupt is pending because TIMERn has reached the end of the time interval If the INTEN bit in the CONTROLn is also set to 1 the interrupt for timer channel n and the global interrupt are raised Writing a 1 to this bit clears the interrupt request 1 RUN Indicates the state of TIM
439. status match engine slice 0 interrupt 25 PININT1 IRQ Pin interrupt 1 or pattern PSTAT pin interrupt status match engine slice 1 interrupt 26 PININT2 IRQ Pin interrupt 2 or pattern PSTAT pin interrupt status match engine slice 2 interrupt 27 PININT3_IRQ Pin interrupt 3 or pattern PSTAT pin interrupt status match engine slice 3 interrupt 28 PININT4_IRQ Pin interrupt 4 or pattern PSTAT pin interrupt status match engine slice 4 interrupt UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 11 of 326 NXP Semiconductors U M1 0601 Chapter 3 LPC800 Nested Vectored Interrupt Controller NVIC Table 3 Connection of interrupt sources to the NVIC Interrupt Name Description Flags number 29 PININT5 IRQ Pin interrupt 5 or pattern PSTAT pin interrupt status match engine slice 5 interrupt 30 PININT6 IRQ Pin interrupt 6 or pattern PSTAT pin interrupt status match engine slice 6 interrupt 31 PININT7 IRQ Pin interrupt 7 or pattern PSTAT pin interrupt status match engine slice 7 interrupt 3 3 2 3 3 3 UM10601 Non Maskable Interrupt NMI The LPC800 supports the NMI which can be triggered by an peripheral interrupt or triggered by software The NMI has the highest priority exception other than the reset You can set up any peripheral interrupt listed in Table 3 as NMI using the NMISR
440. ster disabling that interrupt INTENCLR is a write only register Bits that do not correspond to defined bits in INTENSET are reserved and only zeroes should be written to them Table 175 Interrupt Enable Clear register INTENCLR address 0x4005 000C bit description Bit Symbol Description Reset value 0 MSTPENDINGCLR Master Pending interrupt clear Writing 1 to this bit clears 0 the corresponding bit in the INTENSET register if implemented 3 1 Reserved Read value is undefined only zero shouldbe NA written 4 MSTARBLOSSCLR Master Arbitration Loss interrupt clear 0 5 Reserved Read value is undefined only zero shouldbe NA written 6 MSTSTSTPERRCLR Master Start Stop Error interrupt clear 0 7 Reserved Read value is undefined only zero should be NA written 8 SLVPENDINGCLR Slave Pending interrupt clear 0 10 9 Reserved Read value is undefined only zero should be NA written 11 SLVNOTSTRCLR Slave Not Stretching interrupt clear 0 1442 Reserved Read value is undefined only zero should be All information provided in this document is subject to legal disclaimers written NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 198 of 326 NXP Semiconductors UM10601 16 6 5 UM10601 Chapter 16 LPC800 I2C bus interface Table 175 Interrupt Enable Clear register INTENCLR address 0x4005 000C bit description continued Bit Symb
441. sters are written to 0 4 High level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0x5 Low level Match occurs when there is a low level on the specified input 0x6 Constant 0 This bit slice never contributes to a match should be used to disable any unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs on an event i e when either a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 13 11 1 Specifies the match contribution condition for bit slice 1 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMS
442. sters for edge and level sensitive pins 99 Table 94 Movable functions assign to pins PIOO 0 to PIOO 17 through switch matrix 107 Table 95 Register overview Switch matrix base address 0x4000 C000 109 Table 96 Pin assign register 0 PINASSIGNO address 0x4000 C000 bit description 109 Table 97 Pin assign register 1 PINASSIGN1 address 0x4000 C004 bit description 110 Table 98 Pin assign register 2 PINASSIGN2 address 0x4000 C008 bit description 110 Table 99 Pin assign register PINASSIGNS address 0x4000 C000 bit description 111 Table 100 Pin assign register 4 PINASSIGN4 address 0x4000 C010 bit description 111 Table 101 Pin assign register 5 PINASSIGNS address 0x4000 C014 bit description 111 Table 102 Pin assign register 6 PINASSIGN6 address 0x4000 C018 bit description 112 Table 103 Pin assign register 7 PINASSIGN7 address 0x4000 C010 bit description 112 Table 104 Pin assign register 8 PINASSIGNS address NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 314 of 326 NXP Semiconductors UM10601 0x4000 C020 bit description 113 Table 105 Pin enable register 0 PINENABLEO address 0x4000 1 bit description 113 Table 106 SCT pin description
443. t Master Out Slave In The MOSI signal transfers serial data from the master to the slave When the SPI is a master it outputs serial data on this signal When the SPI is a slave it clocks in seri whenever the Master bit in SPInCfg equals 1 regardless of the SPI interface is used the clock is al data from this signal MOSI is driven the state of the Enable bit Master In Slave Out The MISO signal transfers serial data from the slave to the master When the SPI is a master serial data is input from this signal When the SPI is a slave serial data is output to this signal MISO is driven when the SPI block is enabled the Master bit in CFG equals 0 and when the slave is s Slave Select When the SPI interface is a master it will drive the SSEL signals to an active state before the start of serial data and then release them to an inactive state after the serial data has been sent By default this signal is active low but can be selected to operate as active high When the SPI is a slave any SSEL in an active state indicates that this slave is being addressed The SSEL pin is driven whenever the Master bit in the CFG register equals 1 regardless of the elected by one or more SSEL signals state of the Enable bit Serial Clock Master Out Slave In Master In Slave Out Slave Select SWM register PINASSIGN3 PINASSIGN4 PINASSIGN4 PINASSIGN4 PINASSIGN4 PINASSIGN5 PINASSIGN5 PINASSIGN5 Refer
444. t and this register can also be written to clear interrupts The other pin interrupt registers play different roles for edge sensitive and level sensitive pins as described in Table 93 Table 93 Pin interrupt registers for edge and level sensitive pins Name Edge sensitive function Level sensitive function IENR Enables rising edge interrupts Enables level interrupts SIENR Write to enable rising edge interrupts Write to enable level interrupts CIENR Write to disable rising edge interrupts Write to disable level interrupts IENF Enables falling edge interrupts Selects active level SIENF Write to enable falling edge interrupts Write to select high active CIENF Write to disable falling edge interrupts Write to select low active Pattern Match engine example Suppose the desired boolean pattern to be matched is IN1 IN1 IN2 IN2 IN3 IN6fe IN5 IN7ev with IN6fe sticky falling edge on input 6 IN7ev non sticky event rising or falling edge on input 7 Each individual term in the expression shown above is controlled by one bit slice To specify this expression program the pattern match bit slice source and configuration register fields as follows PMSRC register Table 91 CLR EDGEDET A 1 may be written to bit 5 to clear any pre existing edge detects on bit slice 5 if that is what is desired SRCO 001 select input 1 for bit slice 0 SRC1 001 select input 1 for bit slice 1
445. t be selected Table 13 the main clock source must be set to the input clock to the system PLL Table 15 and the system AHB clock divider must be set to 1 Table 17 set pll attempts to find a PLL setup that matches the calling parameters Once a combination of a feedback divider value SYSPLLCTRL M a post divider ratio SYSPLLCTRL P and the system AHB clock divider SYSAHBCLKDIV is found set pll applies the selected values and switches the main clock source selection to the system PLL clock out if necessary The routine returns a result code that indicates if the system PLL was successfully set PLL CMD SUCCESS or not in which case the result code identifies what went wrong The current system frequency value is also returned The application should use this information to adjust other clocks in the device the SSP UART and WDT clocks and or clockout Table 250 set pll routine Routine set Input ParamO0 system PLL input frequency in kHz Param1 expected system clock in kHz Param2 mode CPU FREQ EQU CPU FREQ LTE CPU FREQ GTE CPU FREQ APPROX Param3 system PLL lock time out Result Result0 SUCCESS PLL INVALID FREQ PLL INVALID MODE PLL FREQ NOT FOUND PLL NOT LOCKED Result1 system clock in kHz The following definitions are needed when making set pll power routine calls set pll mode options All information provided in this document is subject to legal disclaimer
446. t can be enabled by the event counter s HALT bit and STATE register In bi directional mode events can also be enabled based on the direction of count Each event can modify its counter STATE value If more than one event associated with the same counter occurs in a given clock cycle only the state change specified for the highest numbered event among them takes place Other actions dictated by any simultaneously occurring events all take place Table 130 SCT event control register 0 to 5 EV 0 5 CTRL address 0x5000 4304 EVO CTRL to 0x5000 432C EV5 CTRL bit description Bit Symbol Value Description Reset 3 0 MATCHSEL 4 HEVENT 0 1 5 OUTSEL 0 1 9 6 IOSEL 11 10 IOCOND 0x0 0 1 0 2 0x3 13 12 COMBMODE 0x0 0 1 0 2 0x3 14 STATELD 0 19 15 STATEV UM10601 value Selects the Match register associated with this event if any A match can occur only 0 when the counter selected by the HEVENT bit is running Select L H counter Do not set this bit if UNIFY 1 0 L state Selects the L state and the L match register selected by MATCHSEL H state Selects the H state and the H match register selected by MATCHSEL Input output select 0 Input Selects the inputs elected by IOSEL Output Selects the outputs selected by IOSEL Selects the input or output signal associated with this event if any Do not select an 0 input in this register if CLKMODE is 1x In this case the clock input is an implicit ingredient
447. t flag register FLAG address 0x4000 40F8 bit description Bit Symbol Value Description Reset value 0 GFLAGO Monitors the interrupt flag of TIMERO 0 0 No pending interrupt Writing a zero is equivalent to no operation 1 Pending interrupt The interrupt is pending because TIMERO has reached the end of the time interval If the INTEN bit in the CONTROLO register is also set to 1 the interrupt for timer channel 0 and the global interrupt are raised Writing a 1 to this bit clears the interrupt request 1 GFLAG1 Monitors the interrupt flag of TIMER1 0 0 No pending interrupt Writing a zero is equivalent to no operation 1 Pending interrupt The interrupt is pending because TIMER1 has reached the end of the time interval If the INTEN bit in the CONTROL1 register is also set to 1 the interrupt for timer channel 1 and the global interrupt are raised Writing a 1 to this bit clears the interrupt request 2 GFLAG2 Monitors the interrupt flag of TIMER2 0 0 No pending interrupt Writing a zero is equivalent to no operation 1 Pending interrupt The interrupt is pending because TIMER2 has reached the end of the time interval If the INTEN bit in the CONTROL2 register is also set to 1 the interrupt for timer channel 2 and the global interrupt are raised Writing a 1 to this bit clears the interrupt request 3 GFLAG3 Monitors the interrupt flag of TIMERS 0 0 No pending interrupt Writing a zero is equivalent to no operation
448. t input 1 as the source to bit slice 4 Selects pin interrupt input 2 as the source to bit slice 4 Selects pin interrupt input 3 as the source to bit slice 4 Selects pin interrupt input 4 as the source to bit slice 4 Selects pin interrupt input 5 as the source to bit slice 4 Selects pin interrupt input 6 as the source to bit slice 4 Selects pin interrupt input 7 as the source to bit slice 4 Selects the input source for bit slice 5 Input 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Selects pin interrupt input 0 as the source to bit slice 5 Selects pin interrupt input 1 as the source to bit slice 5 Selects pin interrupt input 2 as the source to bit slice 5 Selects pin interrupt input 3 as the source to bit slice 5 Selects pin interrupt input 4 as the source to bit slice 5 Selects pin interrupt input 5 as the source to bit slice 5 Selects pin interrupt input 6 as the source to bit slice 5 Selects pin interrupt input 7 as the source to bit slice 5 Selects the input source for bit slice 6 Input 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Selects pin interrupt input 0 as the source to bit slice 6 Selects pin interrupt input 1 as the source to bit slice 6 Selects pin interrupt input 2 as the source to bit slice 6 Selects pin interrupt input 3 as the source to bit slice 6 Selects pin interrupt input 4 as the source to bit slice 6 Selects pin interrupt input 5 as the source
449. t register which specifies the minimum number of cycles 0 255 permitted for the system to respond to an interrupt request The intent of this register is to allow the user to select a trade off between interrupt response time and determinism Setting this parameter to a very low value e g zero will guarantee the best possible interrupt performance but will also introduce a significant degree of uncertainty and jitter Requiring the system to always take a larger number of cycles whether it needs it or not will reduce the amount of uncertainty but may not necessarily eliminate it Theoretically the ARM Cortex M0 core should always be able to service an interrupt request within 15 cycles However system factors external to the cpu such as bus latencies or peripheral response times can increase the time required to complete a previous instruction before an interrupt can be serviced Therefore accurately specifying a minimum number of cycles that will ensure determinism will depend on the application The default setting for this register is 0x010 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 31 of 326 NXP Semiconductors U M1 0601 4 6 26 4 6 27 UM10601 Chapter 4 LPC800 System configuration SYSCON Table 30 IRQ latency register IRQLATENCY address 0x4004 8170 bit description Bit Symbol
450. tained at flash address 0x0000 0004 This address contains the entry point to the code in the ARM Cortex MO vector table which is the bottom of the boot ROM the internal SRAM or the flash memory respectively Table 248 Memory mapping in debug mode Memory mapping mode Memory start address visible at 0x0000 0004 Bootloader mode Ox1FFF 0000 User flash mode 0x0000 0000 User SRAM mode 0x1000 0000 Serial Wire Debug SWD flash programming interface Debug tools can write parts of the flash image to RAM and then execute the IAP call Copy RAM to flash repeatedly with proper offset All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 267 of 326 UM10601 Chapter 22 LPC800 Power profile API ROM driver Rev 1 1 24 January 2013 Preliminary user manual 22 1 How to read this chapter The power profiles are available for all LPC800 parts 22 2 Features ncludes ROM based application services Power Management services Clocking services 22 3 General description The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile The power configuration routine configures the LPC800 for one of the following power modes Default mode corresponding to power configuration after reset CPU performance mode corresponding to optim
451. tal oscillator using the XTALIN XTALOUT pins External clock input CLKIN Select this pin through the switch matrix Section 4 6 8 System PLL clock source select register Update the PLL clock source in the SYSPLLCLKUEN register Section 4 6 9 System PLL clock source update register Configure the PLL M and N dividers Section 4 6 3 System PLL control register Wait for the PLL to lock by monitoring the PLL lock status Section 4 6 4 System PLL status register 4 3 2 Configure the main clock and system clock The clock source for the registers and memories is derived from main clock The main clock can be sourced from the IRC at a fixed clock frequency of 12 MHz or from the PLL The divided main clock is called the system clock and clocks the core the memories and the peripherals register interfaces and peripheral clocks 1 Select the main clock You have the following options IRC 12 MHz internal oscillator default PLL output You must configure the PLL to use the PLL output Section 4 6 10 Main clock source select register Update the main clock source Section 4 6 11 Main clock source update enable register Select the divider value for the system clock A divider value of 0 disables the system clock Section 4 6 12 System clock divider register Select the memories and peripherals that are operating in your application and therefore must have an activ
452. taneous set and clear on output 3 0 0x0 No change 0 1 Set output or clear based on the SETCLR3 field 0 2 Clear output or set based on the SETCLR3 field 0x3 Toggle output 31 8 Reserved SCT flag enable register This register enables flags to request an interrupt if the FLAGn bit in the SCT event flag register Section 10 6 15 is also set Table 121 SCT flag enable register EVEN address 0x5000 40F0 bit description Bit Symbol Description Reset value 5 0 IEN The SCT requests an interrupt when bit n of this register and the 0 event flag register are both one event 0 bit 0 event 1 bit 1 event 5 bit 5 31 6 Reserved SCT event flag register This register records events Writing ones to this register clears the corresponding flags and negates the SCT interrupt request if all enabled Flag bits are zero Table 122 SCT event flag register EVFLAG address 0x5000 40F4 bit description Bit Symbol Description Reset value 5 0 FLAG Bit n is one if event n has occurred since reset or a 1 was last written to 0 this bit event 0 bit 0 event 1 bit 1 event 5 bit 5 31 6 Reserved SCT conflict enable register This register enables the no change conflict events specified in the SCT conflict resolution register to request an IRQ All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual
453. task is completed the function returns to the line after the call All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 280 of 326 NXP Semiconductors UM10601 Chapter 23 LPC800 I2C bus ROM API 23 4 4 12 Master Transmit and Receive Polling 23 4 5 23 4 6 UM10601 Table 256 12C Master Transmit and Receive Polling Routine Prototype Input parameter Return Description I2C Master Transmit and Receive Polling ErrorCode_t i2c master tx rx poll l2C HANDLE T l2C_PARAM I2C RESULT I2C HANDLE T Handle to the allocated SRAM area I2C PARAM Pointer to the I2C PARAM struct I2C RESULT Pointer to the I2C RESULT struct ErrorCode First transmit bytes in the send buffer to a slave and seconaly receives bytes from slave and store it in the receive buffer The slave address with the R W bit 0 is expected in the first byte of the send buffer After the task is finished the slave address with the R W bit 1 is in the first byte of the receive buffer STOP condition is sent at end unless stop flag 0 When the task is completed the function returns to the line after the call I2C Master Transmit Interrupt Table 257 12C Master Transmit Interrupt Routine Prototype Input parameter Return Description I2C Master Transmit Interrupt ErrorCode ti2c master tran
454. tched is address 0 and address qualification is enabled software must check that the first part of the 10 bit address is a complete match to the previous address before acknowledging the address Clocking and power considerations The Master function of the I C always requires a peripheral clock to be running in order to operate The Slave function can operate without any internal clocking when the slave is not currently addressed This means that reduced power modes up to Power down mode can be entered and the device will wake up when the I C Slave function recognizes an address Monitor mode can similarly wake up the device from a reduced power mode when information becomes available All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 208 of 326 NXP Semiconductors U M1 0601 Chapter 16 LPC800 I2C bus interface 16 7 5 Interrupts The 12C provides a single interrupt output that handles all interrupts for Master Slave and Monitor functions UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 209 of 326 UM10601 Chapter 17 LPC800 SPIO 1 Rev 1 1 24 January 2013 Preliminary user manual 17 1 How to read this chapter SPIO is available on all parts SPI1 is available on
455. ter 10 7 40 Run the SCT UM10601 1 Configure the SCT see Section 10 7 9 Configure the SCT Write to the STATE register to define the initial state By default the initial state is state 0 To start the SCT write to the CTRL register Clear the counters Clear or set the STOP L and or STOP_H bits Remark The counter starts counting once the STOP bit is cleared as well If the STOP bit is set the SCT waits instead for an event to occur that is configured to start the counter For each counter select unidirectional or bidirectional counting mode field BIDIR_L and or BIDIR_H Select the prescale factor for the counter clock CTRL register Clear the HALT_L and or HALT H bit By default the counters are halted and no events can occur To stop the counters by software at any time stop or halt the counter write to STOP L and or STOP H bits or HALT L and or HALT bits in the CTRL register When the counters are stopped both an event configured to clear the STOP bit or software writing a zero to the STOP bit can start the counter again When the counter are halted only a software write to clear the HALT bit can start the counter again No events can occur When the counters are halted software can set any SCT output HIGH or LOW directly by writing to the OUT register All information provided in this document is subject to legal disclaimers NXP B V 2013 All
456. termined by the two USART fractional divider registers in the SYSCON block 1 The DIV denominator of the fractional divider value is programmed in the UARTFRGDIV register See Table 23 2 The MULT value programmed in this register is the numerator of the fractional divider value used by the fractional rate generator to create the fractional component to the baud rate See also Section 15 3 1 Configure the USART clock and baud rate Section 15 7 1 Clocking and Baud rates Table 24 USART fractional generator multiplier value register UARTFRGMULT address 0x4004 80F4 bit description Bit Symbol Description Reset value 7 0 MULT Numerator of the fractional divider MULT is equal to the programmed 0 value 31 8 Reserved External trace buffer command register This register works in conjunction with the MTB master register to start and stop tracing Also see Section 25 5 4 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 29 of 326 NXP Semiconductors U M1 0601 4 6 21 4 6 22 4 6 23 UM10601 Chapter 4 LPC800 System configuration SYSCON Table 25 External trace buffer command register EXTTRACECMD address 0x4004 80FC bit description Bit Symbol Description Reset value 0 START Trace start command Writing a one to this bit sets the TSTART signal 0 to the MTB
457. terrupt wake up 0 0 Disabled 1 Enabled 2 Reserved 3 USARTO USARTO interrupt wake up Configure USART 0 in synchronous slave mode 0 Disabled 1 Enabled 4 USART1 USART1 interrupt wake up Configure USART 0 in synchronous slave mode 0 Disabled 1 Enabled 5 USART2 USART2 interrupt wake up Configure USART 0 in synchronous slave mode 0 Disabled 1 Enabled 7 6 Reserved 7 12 I2C interrupt wake up 0 0 Disabled 1 Enabled 11 9 Reserved E 12 WWDT WWDT interrupt wake up 0 0 Disabled 1 Enabled 13 BOD BOD interrupt wake up 0 0 Disabled 1 Enabled 14 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 34 of 326 NXP Semiconductors U M1 0601 4 6 30 4 6 31 UM10601 Chapter 4 LPC800 System configuration SYSCON Table 34 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description continued Bit Symbol Value Description Reset value 15 WKT Self wake up timer interrupt wake up 0 0 Disabled 1 Enabled 31 16 Reserved Deep sleep mode configuration register The bits in this register BOD PD and WDTOSC OD can be programmed to control aspects of Deep sleep and Power down modes The bits are loaded into corresponding bits of the PDRUNCFG register when Deep sleep mode or Power down mode is entered Remark Hardware forces the analog block
458. that need to be running when the part wakes up Enable the SPI interrupt in the NVIC Enable the interrupt in the INTENSET register which configures the interrupt as wake up event Table 192 Examples are the following wake up events Achange in the state of the SSEL pin Data available to be received Receiver overrun 17 4 Pin description The SPI signals are movable functions and are assigned to external pins through the switch matrix See Section 9 3 1 Connect an internal signal to a package pin to assign the SPI functions to pins on the LPC800 package UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 211 of 326 NXP Semiconductors UM10601 Table 187 SPI Pin Description Chapter 17 LPC800 SPI0 1 Function SPIO_SCK SPIO MOSI SPIO MISO SPIO SSEL SPI1_SCK SPI1_MOSI SPI1_MISO SPI1_SSEL Direct Pin Description ion any Serial Clock SCK is clock signal used synchronize the transfer of data It is driven by the master and received by the any any any any any any any slave When programmable to be active high or active low SCK only switches during a data transfer It is driven whenever the Master bit in CFG equals 1 regardless of the state of the Enable bi
459. the core memories and the peripherals The system clock can be shut down completely by setting the DIV field to zero Table 17 System clock divider register SYSAHBCLKDIV address 0x4004 8078 bit description Bit Symbol Description Reset value 7 0 DIV System AHB clock divider values 0x01 0 System clock disabled 1 Divide by 1 to 255 Divide by 255 31 8 Reserved System clock control register The SYSAHBCLKCTRL register enables the clocks to individual system and peripheral blocks The system clock bit 0 provides the clock for the AHB the bridge the ARM Cortex M0 the SYSCON block and the PMU This clock cannot be disabled Table 18 System clock control register SYSAHBCLKCTRL address 0x4004 8080 bit description Bit Symbol Value Description Reset value 0 SYS Enables the clock for the AHB the APB bridge the 1 Cortex M0 core clocks SYSCON and the PMU This bit is read only and always reads as 1 0 Reserved 1 Enable 1 ROM Enables clock for ROM 1 0 Disable 1 Enable 2 RAM Enables clock for SRAM 1 0 Disable 1 Enable 3 FLASHREG Enables clock for flash register interface 1 0 Disable 1 Enable 4 FLASH Enables clock for flash 1 0 Disable 1 Enable 5 12 Enables clock for I2C 0 0 Disable 1 Enable UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 25 of 326 NXP
460. the pin interrupt mode is level sensitive PMODE 1 the level interrupt is enabled The IENF register configures the active level HIGH or LOW for this interrupt Table 81 Pin interrupt level or rising edge interrupt enable register IENR address 0xA000 4004 bit description Bit Symbol Description Reset Access value 7 0 ENRL Enables the rising edge or level interrupt for each pin 0 R W interrupt Bit n configures the pin interrupt selected in PINTSELn 0 Disable rising edge or level interrupt 1 Enable rising edge or level interrupt 31 8 Reserved Pin interrupt level or rising edge interrupt set register For each of the 8 pin interrupts selected in the PINTSELn registers see Section 4 6 27 one bit in the SIENR register sets the corresponding bit in the IENR register depending on the pin interrupt mode configured in the ISEL register f the pin interrupt mode is edge sensitive PMODE 0 the rising edge interrupt is set f the pin interrupt mode is level sensitive PMODE 1 the level interrupt is set Table 82 Pin interrupt level or rising edge interrupt set register SIENR address 0xA000 4008 bit description Bit Symbol Description Reset Access value 7 0 SETENRL Ones written to this address set bits in the IENR thus NA WO enabling interrupts Bit n sets bit n in the IENR register 0 No operation 1 Enable rising edge or level interrupt 31 8 Reserved Pin interrupt l
461. they can not be cleared by software Both flags are cleared by an external reset or a Watchdog timer reset WDTOF The Watchdog time out flag is set when the Watchdog times out when a feed error occurs or when PROTECT 1 and an attempt is made to write to the TC register This flag is cleared by software writing a O to this bit WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the value specified by WARNINT This flag is cleared when any reset occurs and is cleared by software by writing a O to this bit In all power modes except Deep power down mode a Watchdog reset or interrupt can occur when the watchdog is running and has an operating clock source The watchdog oscillator can be configured to keep running in Sleep Deep sleep modes and Power down modes If a watchdog interrupt occurs in Sleep Deep sleep mode or Power down mode and the WWDT interrupt is enabled in the NVIC the device will wake up Note that in Deep sleep and Power down modes the WWDT interrupt must be enabled the STARTERP1 register in addition to the NVIC See the following registers Table 34 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 155 of 326 NXP Semiconductors U M1 0601 12 6 2
462. this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 240 of 326 UM10601 Chapter 20 LPC800 Boot ROM Rev 1 1 24 January 2013 Preliminary user manual 20 1 How to read this chapter The boot loader is identical for all parts The Boot ROM implementation changes with the chip version See Section 20 3 1 20 2 Features 8kB on chip boot ROM Contains the boot loader with In System Programming ISP facility and the following APIs n Application Programming IAP of flash memory Power profiles for optimizing power consumption and system performance USART drivers 2C drivers 20 3 Basic configuration The clock to the ROM is enabled by default No configuration is required to use the ROM 20 3 1 Boot loader versions The LPC800 boot loader is updated with a new chip version You can determine the boot loader version using the ISP command Read Boot code version see Section 21 5 1 12 or from the part marking Table 211 Boot loader versions Bootloader Marking Description version v13 1 initial 1 ISP IAP The following deviations from the specification apply version The the IAP erase page command allows only single page erase The start page parameter must the same as the end page parameter See Table 246 Code SECTOR NOT PREPARED FORWRITE OPERATION in ISP command C Write RAM
463. tion 32 Table 11 Watchdog oscillator control register Table 32 Pin interrupt select registers PINTSEL 0 7 WDTOSCCTRL address 0x4004 8024 bit address 0x4004 8178 PINTSELO to 0x4004 COSCHPUON PEE 22 8194 PINTSEL7 bit description 33 Table 12 System reset status register SYSRSTSTAT Table 33 Start logic O pin wake up enable register 0 address 0x4004 8030 bit description 23 STARTERPO address 0x4004 8204 bit Table 13 System PLL clock source select register description 33 SYSPLLCLKSEL address 0x4004 8040 bit Table 34 Start logic 1 interrupt wake up enable register description 0 ertet ias 23 STARTERP1 address 0x4004 8214 bit Table 14 System PLL clock source update enable register description 34 SYSPLLCLKUEN address 0x4004 8044 bit Table 35 Deep sleep configuration register description 2 pama pioni RR RR XS 24 PDSLEEPCFG address 0x4004 8230 bit Table 15 Main clock source select register MAINCLKSEL description 35 address 0x4004 8070 bit description 24 Table 36 Wake up configuration register PDAWAKECFG Table 16 Main clock source update enable register address 0x4004 8234 bit description 36 MAINCLKUEN address 0x4004 8074 bit Table 37 Power configuration register PDRUNCFG description p ccc o ces ee s x eed 24 address 0x4004 8238 bit description 37
464. tion Bit Symbol Value Description Reset value 7 0 MONRXDAT Monitor function Receiver Data This reflects every data 0 byte that passes on the 12C pins and adds indication of Start Repeated Start and data NACK 8 MONSTART Monitor Received Start 0 0 No detect The monitor function has not detected a Start event on the IC bus 1 Start detect The monitor function has detected a Start event on the I C bus All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 206 of 326 NXP Semiconductors U M1 0601 Chapter 16 LPC800 I2C bus interface Table 186 Monitor data register MONRXDAT address 0x4005 0080 bit description Bit Symbol Value Description Reset value 9 MONRESTART Monitor Received Repeated Start 0 0 No start detect The monitor function has not detected a Repeated Start event on the I C bus 1 Repeated start detect The monitor function has detected a Repeated Start event on the 12C bus 10 MONNACK Monitor Received NACK 0 0 Acknowledged The data currently being provided by the monitor function was acknowledged by at least one master or slave receiver 1 Not acknowledged The data currently being provided by the monitor function was not acknowledged by any receiver 31 11 Reserved Read value is undefined only zero should be NA written 16 7 Functional description
465. tion assignment The value is the pin number tobe OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 109 of 326 NXP Semiconductors U M1 0601 9 5 2 9 5 3 UM10601 Chapter 9 LPC800 Switch matrix Table 96 Pin assign register 0 PINASSIGNO address 0x4000 C000 bit description Bit Symbol Description Reset value 15 8 UO RXD I UO function assignment The value is the pin number to be OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 23 16 UO RTS RTS function assignment The value is the pin number tobe OXFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 31 24 UO CTS I UO CTS function assignment The value is the pin number tobe OXFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 Pin assign register 1 Table 97 Pin assign register 1 PINASSIGN1 address 0x4000 C004 bit description Bit Symbol Description Reset value 7 0 UO SCLK SCLK function assignment The value is the pin number to be 0xFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 15 8 U1 TXD U1 TXD function assignment The v
466. tly have data available Data waiting The Monitor function has data waiting to be read Monitor Overflow flag 0 0 No overrun Monitor data has not overrun Overrun A Monitor data overrun has occurred This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register Writing 1 to this bit clears the flag Monitor Active flag This flag indicates when the Monitor function 0 considers the IC bus to be active Active is defined here as when some Master is on the bus a bus Start has occurred more recently than a bus Stop 0 Inactive The Monitor function considers the 12C bus to be inactive 1 Active The Monitor function considers the 12C bus to be active Monitor Idle flag This flag is set when the Monitor function sees the 0 2 bus change from active to inactive This can be used by software to decide when to process data accumulated by the Monitor function This flag will cause an interrupt when set if enabled via the INTENSET register The flag can be cleared by writing a 1 to this bit 0 Not idle The 12 bus is not idle or this flag has been cleared by software 1 Idle The 12C bus has gone idle at least once since the last time this flag was cleared by software Reserved Read value is undefined only zero should be written NA RO W1 RO W1 RO W1 NA All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved
467. to HIGH and starts tracing if the TSTARTEN bit in the MTB master register is set to one as well 1 STOP Trace stop command Writing a one to this bit sets the TSTOP signal 0 in the MTB to HIGH and stops tracing if the TSTOPEN bit in the MTB master register is set to one as well 31 2 Reserved 0 POR captured PIO status register 0 The PIOPORCAPO register captures the state of GPIO port 0 at power on reset Each bit represents the reset state of one GPIO pin This register is a read only status register Table 26 POR captured PIO status register 0 PIOPORCAPO address 0x4004 8100 bit description Bit Symbol Description Reset value 17 0 PIOSTAT State of PIOO 17 through PIOO 0 at power on reset Implementation dependent 31 18 Reserved IOCON glitch filter clock divider registers 6 to 0 These registers individually configure the seven peripheral input clocks IOCONFILTR PCLK to the IOCON programmable glitch filter The clocks can be shut down by setting the DIV bits to OxO Table 27 1 glitch filter clock divider registers 6 to 0 IOCONCLKDIV 6 0 address 0x4004 8134 IOCONCLKDIV6 to 0x004 814C IOCONFILTCLKDIVO bit description Bit Symbol Description Reset value 7 0 DIV IOCON glitch filter clock divider values 0 0 Disable IOCONFILTR PCLK 1 Divide by 1 to 255 Divide by 255 31 8 Reserved 0x00 BOD control register The BOD control register selects four separate threshold values for se
468. to R W 0x200 to SCT match reload value register 0 to 4 0x0000 0000 Table 127 MATCHREL4 0x210 REGMODO 0 to REGMODE4 0 MATCHREL 10 to R W 0x200 to SCT match reload value register 0 to 4 low Table 127 MATCHREL_L4 0x210 counter 16 bit REGMODO L 0 to REGMODE4 L 0 MATCHREL_HO to R W 0x202 to SCT match reload value register 0 to 4 high Table 127 MATCHREL_H4 0x212 counter 16 bit REGMODO 0 to REGMODE4_H 0 CAPCTRLO to 0 200 to SCT capture control register 0 to 4 REGMODO 0 0000 0000 Table 128 CAPCTRL4 0x210 1 to REGMODE4 1 CAPCTRL_LO to 0 200 to SCT capture control register 0 to 4 low counter Table 128 CAPCTRL L4 0x210 16 bit REGMODO L 1 to REGMODE4 L 1 CAPCTRL_HO to 0x202 to SCT capture control register 0 to 4 high counter Table 128 CAPCTRL_H4 0x212 16 bit REGMODO 1 to REGMODE4 1 EVO STATE R W 0x300 SCT event 0 state register 0x0000 0000 Table 129 EVO_CTRL R W 0x304 SCT event 0 control register 0x0000 0000 Table 130 EV1_STATE R W 0x308 SCT event 1 state register 0x0000 0000 Table 129 EV1_CTRL R W Ox30C SCT event 1 control register 0x0000 0000 Table 130 EV2 STATE R W 0x310 SCT event 2 state register 0x0000 0000 Table 129 EV2 CTRL R W 0x314 SCT event 2 control register 0x0000 0000 Table 130 EV3_STATE R W 0x318 SCT event 3 state register 0x0000 0000 Table 129 EV3 CTRL R W 0x31C SCT event control register 0x0000 0000 Table 130 EV4 STATE R W 0x320 SCT event 4 state register 0x0000 0000 Table 129 EV4 CTRL R W 0x324 SCT ev
469. to a pin When you assign any function to a pin through the switch matrix the GPIO output becomes disabled UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 106 of 326 UM10601 Chapter 9 LPC800 Switch matrix NXP Semiconductors 9 4 1 Movable functions Table 94 Movable functions assign to pins PIOO 0 to PIOO 17 through switch matrix Function name Type Description SWM Pin assign Reference register UO TXD O Transmitter output for USARTO PINASSIGNO Table 96 UO RXD Receiver input for USARTO PINASSIGNO Table 96 UO RTS Request To Send output for USARTO PINASSIGNO Table 96 UO CTS Clear To Send input for USARTO PINASSIGNO Table 96 UO SCLK Serial clock input output for USARTO in synchronous PINASSIGN1 Table 97 mode U1_TXD O Transmitter output for USART1 PINASSIGN1 Table 97 U1 RXD Receiver input for USART1 PINASSIGN1 Table 97 U1 RTS Request To Send output for USART1 PINASSIGN1 Table 97 U1 CTS Clear To Send input for USART1 PINASSIGN2 Table 98 U1 SCLK Serial clock input output for USART1 in synchronous PINASSIGN2 Table 98 mode U2 TXD Transmitter output for USART2 PINASSIGN2 Table 98 U2 RXD Receiver input for USART2 PINASSIGN2 Table 98 U2 RTS Request To Send output for USART1 PINASSIGN3 Table 99 U2_CTS Clear To Send input for USART1 PINASSIGN3 Table 99 U2
470. to bit slice 6 Selects pin interrupt input 6 as the source to bit slice 6 Selects pin interrupt input 7 as the source to bit slice 6 Selects the input source for bit slice 7 Input 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Selects pin interrupt input 0 as the source to bit slice 7 Selects pin interrupt input 1 as the source to bit slice 7 Selects pin interrupt input 2 as the source to bit slice 7 Selects pin interrupt input 3 as the source to bit slice 7 Selects pin interrupt input 4 as the source to bit slice 7 Selects pin interrupt input 5 as the source to bit slice 7 Selects pin interrupt input 6 as the source to bit slice 7 Selects pin interrupt input 7 as the source to bit slice 7 Reset value 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 93 of 326 NXP Semiconductors U M1 0601 8 6 13 Chapter 8 LPC800 Pin interrupts pattern match engine Pattern Match Interrupt Bit Slice Configuration register The bit slice configuration register configures the detect logic and contains bits to select from among eight alternative conditions for each bit slice that cause that bit slice to contribute to a pattern match The seven LSB s of this register specify which bit slices are the end points of product terms in the boolean expression i e where OR ter
471. to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected UM10601 All information provided in this document is subject to legal disclaimers to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer
472. tput bits can be set by writing ones to these registers regardless of MASK registers Reading from these register returns the port s output bits regardless of pin directions Table 75 GPIO set port 0 register SETO address 0xA000 2200 bit description Bit Symbol Description Reset Access value 17 0 SETPO Read or set output bits 0 R W 0 Read output bit write no operation 1 Read output bit write set output bit 31 18 Reserved 0 GPIO port clear registers Output bits can be cleared by writing ones to these write only registers regardless of MASK registers All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 77 of 326 NXP Semiconductors U M1 0601 7 6 9 7 7 Functional Chapter 7 LPC800 GPIO port Table 76 GPIO clear port 0 register CLRO address 0xA000 2280 bit description Bit Symbol Description Reset Access value 17 0 CLRPO Clear output bits NA WO 0 No operation 1 Clear output bit 31 18 Reserved 0 GPIO port toggle registers Output bits can be toggled inverted complemented by writing ones to these write only registers regardless of MASK registers Table 77 GPIO toggle port 0 register address 0xA000 2300 bit description Bit Symbol Description Reset Access value 17 0 NOTPO Toggle output bits NA WO 0 no operation 1
473. ts in the interrupt wake up registers Table 33 Table 34 and in the NVIC All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 49 of 326 NXP Semiconductors U M1 0601 5 7 6 3 5 7 7 5 7 7 1 5 7 7 2 UM10601 Chapter 5 LPC800 Reduced power modes and Power Management 5 Write one to the SLEEPDEEP bit in the ARM Cortex M0 SCR register 6 Use the ARM WFI instruction Wake up from Power down mode The microcontroller can wake up from Power down mode in the same way as from Deep sleep mode Signal on one of the eight pin interrupts selected in Table 32 Each pin interrupt must also be enabled in the STARTERPO register Table 33 and in the NVIC signal if the is enabled in the PDSLEEPCFG register BOD interrupt using the interrupt wake up register 1 Table 34 The BOD interrupt must be enabled in the NVIC The BOD interrupt must be selected in the BODCTRL register Reset from the BOD circuit In this case the BOD reset must be enabled in the BODCTRL register Table 28 WWDT signal if the watchdog oscillator is enabled in the PDSLEEPCFG register WWDT interrupt using the interrupt wake up register 1 Table 34 The WWDT interrupt must be enabled in the NVIC The WWDT interrupt must be set in the WWDT register Reset from the watchdog timer WWDT
474. ts the current state of the CTS signal regardless of the setting of NA RO the CTSEN bit in the CFG register This will be the value of the CTS input pin unless loopback mode is enabled 5 DELTACTS This bit is set when a change in the state is detected for the CTS flag above 0 W1 This bit is cleared by software 6 TXDISINT Transmitter Disabled Interrupt flag When 1 this bit indicates that the USART 0 RO transmitter is fully idle after being disabled via the TXDIS in the CFG register TXDIS 1 Reserved Read value is undefined only zero should be written NA NA OVERRUNINT Overrun Error interrupt flag This flag is set when a new character is received 0 W1 while the receiver buffer is still in use If this occurs the newly received character in the shift register is lost 9 Reserved Read value is undefined only zero should be written NA NA 10 RXBRK Received Break This bit reflects the current state of the receiver break 0 RO detection logic It is set when the Un pin remains low for 16 bit times Note that FRAMERRINT will also be set when this condition occurs because the stop bit s for the character would be missing RXBRK is cleared when the Un RXD pin goes high 11 DELTARXBRK This bit is set when a change in the state of receiver break detection occurs 0 W1 Cleared by software 12 START This bit is set when a start is detected on the receiver input Its purpose is 0 W1 primarily to allow wake up from Deep sleep or Powe
475. ttern match module can be enabled to generate a Receive Event RXEV output to the ARM core when the entire boolean expression is true i e when any minterm is matched The RXEV output is also be routed to GPIO INT BMAT pin This allows the GPIO module to provide a rudimentary programmable logic capability employing up to eight inputs and one output The pattern match function utilizes the same eight interrupt request lines as the pin interrupts so these two features are mutually exclusive as far as interrupt generation is concerned A control bit is provided to select whether interrupt requests are generated in response to the standard pin interrupts or to pattern matches Note that if the pin interrupts are selected the RXEV request to the CPU can still be enabled for pattern matches Remark Pattern matching cannot be used to wake the part up from power down modes Pin interrupts must be selected in order to use the pins for wake up Boolean expressions The pattern match module is constructed of eight bit slice elements Each bit slice is programmed to represent one component of one minterm product term within the boolean expression The interrupt request associated with the last bit slice for a particular minterm will be asserted whenever that minterm is matched See bit slice drawing Figure 8 The pattern match capability can be used to create complex software state machines Each minterm and its corresponding individual interr
476. ue 7 0 PSTAT Pin interrupt status Bit n returns the status clears the edge 0 R W interrupt or inverts the active level of the pin selected in PINTSELn Read 0 interrupt is not being requested for this interrupt pin Write 0 no operation Read 1 interrupt is being requested for this interrupt pin Write 1 edge sensitive clear rising and falling edge detection for this pin Write 1 level sensitive switch the active level for this pin in the IENF register 31 8 Reserved Pattern Match Interrupt Control Register The pattern match control register contains one bit to select pattern match interrupt generation as opposed to pin interrupts which share the same interrupt request lines and another to enable the RXEV output to the cpu This register also allows the current state of any pattern matches to be read If the pattern match feature is not used either for interrupt generation or for RXEV assertion the two LSB s of this register should be left at 0600 to conserve power All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 90 of 326 NXP Semiconductors U M1 0601 8 6 12 Chapter 8 LPC800 Pin interrupts pattern match engine Remark Set up the pattern match configuration in the PMSRC and PMCFG registers before writing to this register to enable or re enable the pattern match functi
477. uencies of up to 30 MHz 0x2 Reserved 0x3 Reserved 31 2 Reserved User software must not change the value of these bits Bits 31 2 must be written back exactly as read Flash signature start address register Table 208 Flash Module Signature Start register FMSSTART 0x4004 0020 bit description Bit Symbol Description Reset value 16 0 START Signature generation start address corresponds to AHB byte 0 address bits 20 4 31 37 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Flash signature stop address register Table 209 Flash Module Signature Stop register FMSSTOP 0x4004 0024 bit description Bit Symbol Value Description Reset value 16 0 STOPA Stop address for signature generation the word 0 specified by STOPA is included in the address range The address is in units of memory words not bytes 3047 Reserved user software should not write ones to 0 reserved bits The value read from a reserved bit is not defined 31 STRTBIST When this bit is written to 1 signature generation starts 0 At the end of signature generation this bit is automatically cleared Flash signature generation result register The signature generation result register returns the flash signature produced by the embedded signature generator The generated flash signature can be used to verify the flash memory contents The generated signature c
478. upt represents a different transition event to a new state Software can then establish the new set of conditions that is a new boolean expression that will cause a transition out of the current state Example Assume the expression INO IN1 IN3 IN1 IN2 IN3 INA is specified through the registers PMSRC Table 91 and PMCFG Table 92 Each term in the boolean expression INO IN1 IN3 etc represents one bit slice of the pattern match engine e In the first term INO IN1 INS3 bit slice 0 monitors for a high level on input INO bit slice 1 monitors for a low level on input IN1 and bit slice 2 monitors for a rising edge on input IN3 If this combination is detected that is if all three terms are true the interrupt associated with bit slice 2 will be asserted n the second term IN1 IN2 bit slice monitors input IN1 for a high level bit slice 4 monitors input IN2 for a high level If this combination is detected the interrupt associated with bit slice 4 will be asserted e In the third term INO IN3 IN4 bit slice 5 monitors input INO for a high level bit slice 6 monitors input IN3 for a low level and bit slice 7 monitors input IN4 for a low level If this combination is detected the interrupt associated with bit slice 7 will be asserted All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminar
479. urces to the NVIC Table 33 Start logic 0 pin wake up enable register 0 STARTERPO address 0x4004 8204 bit description Bit Symbol Value Description Reset value 0 PINTO GPIO pin interrupt 0 wake up 0 0 Disabled 1 Enabled 1 PINT1 GPIO pin interrupt 1 wake up 0 0 Disabled 1 Enabled 2 PINT2 GPIO pin interrupt 2 wake up 0 0 Disabled 1 Enabled 3 PINT3 GPIO pin interrupt 3 wake up 0 0 Disabled 1 Enabled 4 PINT4 GPIO pin interrupt 4 wake up 0 0 Disabled 1 Enabled 5 PINT5 GPIO pin interrupt 5 wake up 0 0 Disabled 1 Enabled 6 PINT6 GPIO pin interrupt 6 wake up 0 0 Disabled 1 Enabled 7 PINT7 GPIO pin interrupt 7 wake up 0 0 Disabled 1 Enabled 31 8 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 33 of 326 NXP Semiconductors U M1 0601 Chapter 4 LPC800 System configuration SYSCON 4 6 29 Start logic 1 interrupt wake up enable register This register selects which interrupts wake the LPC800 from deep sleep and power down modes Remark Also enable the corresponding interrupts in the NVIC See Table 3 Connection of interrupt sources to the NVIC Table 34 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description Bit Symbol Value Description Reset value 0 SPIO SPIO interrupt wake up 0 0 Disabled 1 Enabled 1 SPI SPI in
480. use them in a system design with more than one master If the flag returned from the driver indicates that the message was not successful due to loss of arbitration the application just resends the message UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 271 of 326 NXP Semiconductors U M1 0601 Chapter 23 LPC800 I2C bus ROM API I2C driver routines function table i2c isr handler Ptr to ROM Driver table i2c master transmit poll i2c get status ROM Driver Table 0x00 gt Ptr to Device Table 0 0x04 Ptr to Device Table 1 0x08 Ptr to Device Table 2 0x0C Ptr to Device Table 3 0x10 Ptr to Device Table 4 0x14 Ptr to I2C driver routines Ptrto Device Tablen Fig 46 I2C bus driver routines pointer structure 23 4 API description The I2C API contains functions to configure the 12C and send and receive data in master and slave modes Table 252 12C API calls API call Description Reference void i2c isr handler I2C HANDLE T I2C ROM Driver interrupt service Table 253 routine ErrorCode t i2c master transmit poll l2C HANDLE I2C 12C Master Transmit Polling Table 254 I2C RESULT ErrorCode t i2c master receive poll I2PC HANDLE T 12C PARAM 12C Master Receive Polling Table 255 126 RESULT Er
481. used to unlock Flash Write Erase and Go commands Example U 23130 lt CR gt lt LF gt unlocks the Flash Write Erase amp Go commands UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 251 of 326 NXP Semiconductors U M1 0601 21 5 1 2 21 5 1 3 21 5 1 4 UM10601 Chapter 21 LPC800 Flash ISP and IAP programming Set Baud Rate Baud Rate stop bit Table 220 UART ISP Set Baud Rate command Command B Input Baud Rate 9600 19200 38400 57600 115200 Stop bit 1 2 Return Code CMD SUCCESS INVALID BAUD RATE INVALID STOP BIT PARAM ERROR Description This command is used to change the baud rate The new baud rate is effective after the command handler sends the CMD SUCCESS return code Example B 57600 1 lt CR gt lt LF gt sets the serial port to baud rate 57600 bps 1 stop bit Echo setting Table 221 UART ISP Echo command Command A Input Setting ON 1 OFF 0 Return Code CMD SUCCESS PARAM_ERROR Description The default setting for echo command is ON When ON the ISP command handler sends the received serial data back to the host Example A 0 lt CR gt lt LF gt turns echo off Write to RAM lt start address gt lt number of bytes gt The host should send the plain binary code after receiving the CMD_SUCCESS return code This ISP comman
482. ved 310 of 326 Preliminary user manual UM10601 Chapter 28 Supplementary information Rev 1 1 24 January 2013 Preliminary user manual 28 1 Abbreviations Table 288 Abbreviations Acronym Description AHB Advanced High performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General Purpose Input Output PLL Phase Locked Loop RC Resistor Capacitor SPI Serial Peripheral Interface SMBus System Management Bus TEM Transverse ElectroMagnetic UART Universal Asynchronous Receiver Transmitter 28 2 References 1 0010484 cortex mOp rOpO trm ARM Cortex M0 Technical Reference Manual 2 0010486 ARM technical reference manual 3 ARMv6 M Architecture Reference Manual UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 311 of 326 NXP Semiconductors UM10601 28 3 Legal information Chapter 28 Supplementary information 28 3 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 28 3 2 Disclaimers L
483. vided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 171 of 326 NXP Semiconductors UM10601 Chapter 15 LPC800 USARTO 1 2 Table 156 USART pin description Function UO SCLK Ui TXD U1 RXD Ut RTS Ut CTS U1 SCLK U2 TXD U2 RXD U2 RTS U2 CTS U2 SCLK Direction Pin y o any y o any Description Serial clock input output for USARTO in synchronous mode Clock input or output in synchronous mode Transmitter output for USART1 Serial transmit data Receiver input for USART1 Request To Send output for USART1 Clear To Send input for USART1 Serial clock input output for USART1 in synchronous mode Transmitter output for USART2 Serial transmit data Receiver input for USART2 Request To Send output for USART2 Clear To Send input for USART2 Serial clock input output for USART2 in synchronous mode SWM register PINASSIGN1 PINASSIGN1 PINASSIGN1 PINASSIGN1 PINASSIGN2 PINASSIGN2 PINASSIGN2 PINASSIGN2 PINASSIGN3 PINASSIGN3 PINASSIGN3 Reference Table 97 Table 97 Table 97 Table 97 Table 98 Table 98 Table 98 Table 98 Table 99 Table 99 Table 99 15 5 General description UM10601 The USART receiver block monitors the serial input line Un RXD for valid input The receiver shift register ass
484. x4005 0028 bit description Bit Symbol Description Reset value 7 0 DATA Master function data register 0 Read read the most recently received data for the Master function Write transmit data using the Master function 31 8 Reserved Read value is undefined only zero should be written NA Slave Control register The SLVCTL register contains bits that control various functions of the IC Slave interface Only write to this register when the slave is pending SLVPENDING 1 in the STAT register Table 171 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 203 of 326 NXP Semiconductors U M1 0601 16 6 12 UM10601 Chapter 16 LPC800 I2C bus interface Table 182 Slave Control register SLVCTL address 0x4005 0040 bit description Bit Symbol Value Description Reset Value 0 SlvContinue Slave Continue 0 O No effect 1 Continue Informs the Slave function to continue to the next operation This must done after writing transmit data reading received data or any other housekeeping related to the next bus operation 1 SlvNack Slave NACK 0 0 No effect 1 NACK Causes the Slave function to NACK the master when the slave is receiving data from the master Slave Receiver mode 31 2 Reserved Read value is undefined only zero should be NA written Slave Data register The SLV
485. xEDFO Table 37 R Ox3F4 Device ID part dependent Table 38 4 6 1 4 6 2 System memory remap register The system memory remap register selects whether the exception vectors are read from boot ROM flash or SRAM By default the flash memory is mapped to address 0x0000 0000 When the MAP bits in the SYSMEMREMAP register are set to 0 0 or Ox1 the boot ROM or RAM respectively are mapped to the bottom 512 bytes of the memory map addresses 0x0000 0000 to 0x0000 0200 Table 6 System memory remap register SYSMEMREMAP address 0x4004 8000 bit description Bit Symbol Value Description Reset value 1 0 MAP System memory remap Value 0x3 is reserved 0x2 0x0 Boot Loader Mode Interrupt vectors are re mapped to Boot ROM 0 1 User RAM Mode Interrupt vectors are re mapped to Static RAM 0x2 User Flash Mode Interrupt vectors are not re mapped and reside in Flash 31 2 Reserved Peripheral reset control register The PRESETCTRL register allows software to reset specific peripherals A zero in any assigned bit in this register resets the specified peripheral A 1 clears the reset and allows the peripheral to operate Table 7 Peripheral reset control register PRESETCTRL address 0x4004 8004 bit description Bit Symbol Value Description Reset value 0 SPIO RST N SPIO reset control 1 0 Assert the SPIO reset 1 Clear the SPIO reset 1 SPI1 RST SPI reset control 1 0 Assert the SPI1 reset 1 Clear the SPI1 r
486. y version of value 0x3 This bit is cleared after one clock cycle 25 23 CFG5 Specifies the match contribution condition for bit slice 5 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was Cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 4 High level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0x5 Low level Match occurs when there is a low level on the specified input 0x6 Constant 0 This bit slice never contributes to a match should be used to disable any unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs on an event i e when either a rising or falling edge is first detected on the specified input t
487. y is not retained when the part powers down or enters Deep power down mode Assuming that power supply pins are on their nominal levels when the rising edge on RESET pin is generated it may take up to lt tbd gt 3 ms before PIOO 1 is sampled and the decision whether to continue with user code or ISP handler is made If PIOO 1 is sampled All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 242 of 326 NXP Semiconductors U M1 0601 20 5 2 UM10601 Chapier 20 LPC800 Boot ROM low and the watchdog overflow flag is set the external hardware request to start the ISP command handler is ignored If there is no request for the ISP command handler execution PIOO 1 is sampled HIGH after reset a search is made for a valid user program If a valid user program is found then the execution control is transferred to it If a valid user program is not found the auto baud routine is invoked Remark The sampling of pin PIOO 1 can be disabled through programming flash location 0x0000 O2FC see Section 21 4 3 Code Read Protection CRP ROM based APIs Once the part has booted the user can access several APIs located in the boot ROM to access the flash memory optimize power consumption and operate the USART I2C peripherals The structure of the boot ROM APIs is shown in Figure 40 Ptr to ROM Ox1FFF 1
488. y pin However more than one input can be assigned to a pin Pin PIOO 4 triggers a wake up from Deep power down mode If you need to wake up from Deep power down mode via an external pin do not assign any movable function to this pin The JTAG functions TDO TDI TCK TMS and TRST are selected on pins PIOO 0 to PIOO 4 by hardware when the part is in boundary scan mode UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Preliminary user manual Rev 1 1 24 January 2013 304 of 326 NXP Semiconductors U M1 0601 Chapter 26 LPC800 Packages and pin description Table 285 Pin description table fixed pins Symbol g Type Reset Description state 8228 2 Or F a PIOO 0 ACMP 11 19 16 8 BIIO PIOO 0 General purpose digital input output port O pin 0 TDO In ISP mode this is the USARTO receive pin UO RXD In boundary scan mode TDO Test Data Out Al ACMP 11 Analog comparator input 1 PIOO 1 ACMP 12 12 9 5 B O PIOO 1 General purpose digital input output pin ISP entry CLKIN TDI pin A LOW level on this pin during reset starts the ISP command handler In boundary scan mode TDI Test Data In Al ACMP 12 Analog comparator input 2 CLKIN External clock input SWDIO PIOO 2 TMS 7 6 4 BIO SWDIO Serial Wire Debug I O SWDIO is enabled by default on this pin In boundary scan mode TMS Test Mode S
489. y user manual Rev 1 1 24 January 2013 65 of 326 NXP Semiconductors UM10601 6 5 11 PIOO 15 register Chapter 6 LPC800 I O configuration IOCON Table 59 PIOO_15 register PIOO 15 address 0x4004 4028 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 8 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 S MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0x2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved 0 UM10601 All information provide
490. y user manual Rev 1 1 24 January 2013 85 of 326 NXP Semiconductors UM10601 Chapter 8 LPC800 Pin interrupts pattern match engine The ORed result of all three terms asserts the RXEV request to the CPU and the GPIO INT BMAT output That is if any of the three terms are true the output is asserted Related links Section 8 7 2 8 6 Register description 8 6 1 UM10601 Table 79 Register overview Pin interrupts and pattern match engine base address 0xA000 4000 Name ISEL IENR SIENR CIENR IENF SIENF CIENF RISE FALL IST PMCTRL PMSRC PMCFG Access Address Description R W R W WO WO R W WO WO R W R W R W R W R W R W offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 Pin Interrupt Mode register Pin interrupt level or rising edge interrupt enable register Pin interrupt level or rising edge interrupt Set register Pin interrupt level rising edge interrupt clear register Pin interrupt active level or falling edge interrupt enable register Pin interrupt active level or falling edge interrupt set register Pin interrupt active level or falling edge interrupt clear register Pin interrupt rising edge register Pin interrupt falling edge register Pin interrupt status register Pattern match interrupt control register Pattern match interrupt bit slice source register Pattern

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