MCF5282 User`s Manual Errata
Contents
1. Pin Functions o Primary Internal MAPBGA Pin l 5 Description vO Pull up Primary Secondary Tertiary R4 AN52 PQAO MAO Analog channel 52 O T4 AN53 PQA1 MA1 Analog channel 53 O P3 AN55 PQA3 ETRIG1 Analog channel 55 1 O R3 AN56 PQA4 ETRIG2 Analog channel 56 1 O P4 VRH High analog reference l T5 VRL Low analog reference l Debug and JTAG Test Port Control R9 JTAG_EN JTAG Enable l P9 DSCLK TRST Debug clock TAP reset l Yes T9 TCLK TAP clock l Yes P10 BKPT TMS Breakpoint TAP test mode l Yes select R10 DSI TDI _ Debug data in TAP data in l Yes T10 DSO TDO Debug data out TAP data out O C12 D12 A13 B13 DDATA 3 0 PDD 7 4 Debug data 1 0 C13 A14 B14 A15 PST 3 0 PDD 3 0 Processor status data 1 0 Test N10 TEST Test mode pin l Power Supplies R5 VDDA E Analog positive supply l P5 T1 VSSA Analog ground l P2 VDDH ESD positive supply l N8 VDDPLL PLL positive supply l P8 VSSPLL PLL ground l A6 C11 VPP Flash stress programming l voltage A12 05 D5 D11 VDDF Flash positive supply l B5 B12 VSSF Flash module ground l N11 VSTBY Standby power l MCF5282 User s Manual Errata Rev 15 Freescale Semiconductor Revision History Table 14 3 MCF52822. Change EMRBR register address from IPSBAR 0x11B8 to IPSBAR 0x1188 Deleted reference to nonexistent CF bits in the figure and bit descriptions for the GPTFLG2 register MCF5282 User s Manual Errata Rev 15 Freescale Semiconductor Errata for Revision 2 3 Table 1 MCF5282UM Rev 2 3 Errata continued Location Description Figure 23 18 Page 23 18 Remove the two 16 bit divider blocks from timer input as the divider is not available using external clock sources Section 23 5 1 2 2 Page 23 19 Remove 16 bit divider from equation as the divider is not available using external clock sources Section 25 5 8 Page 25 25 Change end of last sentence from and can be written by the host to 0 to and can be written by the host to 1 Table 25 17 Page 25 29 Remove the following information from the BITERR and ACKERR descriptions as these fields are read only To clear this bit first read it as a one then write it as a one Writing zero has no effect This is a rescindment of a previous documentation errata Change last sentence in ERRINT description from To clear this bit first read it as a one then write as a zero Writing a one has no effect to To clear this bit first read it as a one then write a one Writing a zero has no effect Add the following information to the BOFFINT and WAKEINT descriptions To clear this bit firs
3. To clear an interrupt flag first read the flag as a one then write it as a zero to To clear an interrupt flag first read the flag as a one then write it as a one Chapter 33 It is crucial during power up that VDD never exceeds VDDH by more that 0 3V There are diode devices between the two voltage domains and violating this rule can lead to a latch up condition Table 33 8 33 7 In the PLL Electrical Specifications table only specs for the 80 MHz MCF5282 device were listed Insert specs for the 66MHz device in the first 2 rows and also declare symbol fsys max aS Shown below Max Characteristic Symbol Min Unit 66MHz 80MHz PLL Reference Frequency Range MHz Crystal reference fref_crystal 2 8 33 10 0 External reference fret_ext 2 8 33 10 0 1 1 Mode fref 1 1 33 33 66 66 80 System Frequency fas fsys max fsysimax MHz External Clock Mode 0 66 66 80 On Chip PLL Frequency fret 32 66 66 80 3 Errata for Revision 2 0 Table 3 MCF5282UM Rev 2 0 Errata Location Description Table 33 8 33 9 Reference to TA TL to TH was not deleted Delete MCF5282 User s Manual Errata Rev 15 6 Freescale Semiconductor Errata for Revision 1 0 4 Errata for Revision 1 0 Table 4 MCF5282UM Rev 1 0 Errata Location Description 1 1 1 1 Change Real time debug support with two user visible hardware breakpoint registers To Real time debug
4. J15 DTOUT1 PTD2 URTS1 U1 U0 Request to Send 1 O URTSO J14 DTINO PTD1 UCTS1 U1 U0 Clear to Send 1 0 UCTSO J13 DTOUTO PTDO UCTS1 U1 U0 Clear to Send 1 0 UCTSO General Purpose Timers T13 R13 P13 N13 GPTA 3 0 PTA 3 0 Timer A IC OC PAI 1 0 Yes T12 R12 P12 N12 GPTB 3 0 PTB 3 0 Timer B IC OC PAI 1 0 Yes N14 SIZ1 PE3 SYNCA Timer A synchronization input 1 0 Yes M16 SIZO PE2 SYNCB Timer B synchronization input 1 0 Yes M15 TS PE1 SYNCA_ Timer A synchronization input 1 0 Yes M14 TIP PEO SYNCB_ Timer B synchronization input 1 O Yes DMA Timers K16 DTIN3 PTC3 URTS1 Timer 3 in 1 O URTSO K15 DTOUT3 PTC2 URTS1 Timer 3 out 0 URTSO K14 DTIN2 PTC1 UCTS1 Timer 2 in 1 O UCTSO K13 DTOUT2 PTCO UCTS1 Timer 2 out 0 UCTSO J16 DTIN1 PTD3 URTS1 Timer 1 in 1 0 URTSO J15 DTOUT1 PTD2 URTS1 Timer 1 out O URTSO J14 DTINO PTD1 UCTS1 Timer 0 in 1 O UCTSO J13 DTOUTO PTDO UCTS1 Timer 0 out 1 O UCTSO Queued Analog to Digital Converter QADC T3 ANO PQBO ANW Analog channel 0 1 O R2 AN1 PQB1 ANX Analog channel 1 1 0 T2 AN2 PQB2 ANY Analog channel 2 1 O R1 AN3 PQB3 ANZ Analog channel 3 1 O MCF5282 User s Manual Errata Rev 15 14 Freescale Semiconductor Errata for Revision 1 0 Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function continued
5. 10 2 Page 10 4 In footnote remove mention of the SWIACK register as it is not supported in the global IACK space Section 10 3 7 Page 10 16 Table 15 1 Page 15 3 Table 15 5 Page 15 7 Change last paragraph to In addition to the ACK registers within each interrupt controller there are global LnIACK registers A read from one of the global LnlIACK registers returns the vector for the highest priority unmasked interrupt within a level for all interrupt controllers There is no global SWIACK register However reading the SWIACK register from each interrupt controller returns the vector number of the highest priority unmasked request within that controller NOP command entry Replace SRAS asserted with SDRAM_CS 1 0 asserted Add the following note to the DACRn CBM field description Note It is important to set CBM according to the location of the command bit Section 16 5 Page 16 11 Remove last sentence in this section starting with BCRn decrements since SAA bit is not supported Chapter 17 The maximum buffer size of the FEC is 2032 bytes Replace any mention of the max size being 2047 bytes with 2032 bytes Section 17 4 6 Page 17 7 Add the following subsection entitled Duplicate Frame Transmission The FEC fetches transmit buffer descriptors TxBDs and the corresponding transmit data continuously until the transmit FIFO is full It does not determine whether the TxBD to b
6. 11 Change Internal Pull Up column to pull up indications in the table below 5 6 7 8 Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function Pin Functions Primar Internal MAPBGA Pin Description O y Pull up Primary Secondary Tertiary 1 Reset R11 RSTI Reset in l Yes P11 RSTO Reset out O Clock T8 EXTAL External clock crystal in l MCF5282 User s Manual Errata Rev 15 10 Freescale Semiconductor Errata for Revision 1 0 Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function continued Pin Functions Primar Internal MAPBGA Pin Description vO y Pull up Primary Secondary Tertiary 1 R8 XTAL Crystal drive O N7 CLKOUT Clock out O Chip Configuration Mode Selection R14 CLKMODO Clock mode select l Yes T14 CLKMOD1 Clock mode select l Yes T11 RCON Reset configuration enable l Yes H1 D26 PA2 Chip mode 0 K2 D17 PB1 Chip mode 1 O K3 D16 PBO Chip mode 1 O J4 D19 PB3 Boot device data port size 1 0 K1 D18 PB2 Boot device data port size 1 O J2 D21 PB5 Output pad drive strength O External Memory Interface and Ports C6 B6 A5 A 23 21 PF 7 5 CS
7. Added additional device number order information to Table 32 2 Table 32 2 Orderable Part Numbers Motorola Part Number Description Speed Temperature MCF5280CVF66 MCF5280 RISC Microprocessor 256 MAPBGA 66 67 MHz 40 to 85 C MCF5280CVF80 MCF5280 RISC Microprocessor 256 MAPBGA 80 MHz 40 to 85 C MCF5281CVF66 MCF5281 RISC Microprocessor 256 MAPBGA 66 67 MHz 40 to 85 C MCF5281CVF80 MCF5281 RISC Microprocessor 256 MAPBGA 80 MHz 40 to 85 C MCF5282CVF66 MCF5282 RISC Microprocessor 256 MAPBGA 66 67 MHz 40 to 85 C MCF5282CVF80 MCF5282 RISC Microprocessor 256 MAPBGA 80 MHz 40 to 85 C Chapter 33 Delete references to TA TL to TH Table 33 1 33 1 The Digital Input Voltage Vn absolute maximum rating should be 0 3 to 6 0 V Table 33 6 33 8 The normal operation analog supply current Ippa maximum value has been changed to 5 0 mA MCF5282 User s Manual Errata Rev 15 Freescale Semiconductor 9 Errata for Revision 1 0 Table 4 MCF5282UM Rev 1 0 Errata continued Location Description Figure 33 5 33 16 Replace Figure 33 5 SDRAM Read Cycle with the figure below o li l l2z al4 cLkouT f pze eroaa a A A 23 0 4 Row VNA Column X O B SORS y D 31 0 ae SDRAM_CS t 0 amp fH lt BS 3 0 y ACTV NOP READ NOP PRE 1 DACR CASL 2 Figure 33 5 SDRAM Read Cycle Table 14 3 14
8. H16 SCAS PSD4 SDRAM column VO address strobe G15 DRAMW PSD3 SDRAM write enable 1 0 H13 G16 SDRAM _CS 1 0 PSD 2 1 SDRAM chip selects 1 0 H14 SCKE PSDO SDRAM clock enable V0 External Interrupts Port B15 B16 014 C015 IRQ 7 1 PNQ 7 1 External interrupt request 1 O _ C16 D14 D15 Ethernet C10 EMDIO PAS5 URXD2 Management channel 0 serial data B10 EMDC PAS4 UTXD2 Management channel clock 1 O A8 ETXCLK PEH7 MAC Transmit clock 1 O D6 ETXEN PEH6 MAC Transmit enable 1 O D7 ETXDO PEH5 MAC Transmit data 1 0 B11 ECOL PEH4 MAC Collision 1 O _ A10 ERXCLK PEH3 MAC Receive clock 1 O _ C8 ERXDV PEH2 MAC Receive enable 1 O D9 ERXDO PEH1 MAC Receive data 1 0 _ A11 ECRS PEHO MAC Carrier sense 1 O A7 B7 C7 ETXD 3 1 PEL 7 5 MAC Transmit data I O D10 ETXER PEL4 MAC Transmit error 1 O A9 B9 C9 ERXD 3 1 PEL 3 1 m MAC Receive data I O B8 ERXER PELO MAC Receive error 1 O MCF5282 User s Manual Errata Rev 15 Freescale Semiconductor Errata for Revision 1 0 Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function continued Pin Functions o Primary Internal MAPBGA Pin Description Pull up Primary Secondary Tertiary ue 1 FlexCAN D16 CANRX PAS3 URXD2 FlexCAN Receive data 1 O E13 CANTX PAS
9. and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part ey Z freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2007 All rights reserved MCF5282UMAD Rev 15 05 2007
10. is i 1 NY Table 4 3 Page 4 5 Change reset value of ACRO ACR1 to See Section since some of the bits are undefined after reset Figure 4 2 Page 4 6 Change CACR fields to R W since they may be read via the debug module Table 4 5 Page 4 8 For split instruction data cache entry swap text in parantheses in the description field Instruction cache uses the upper half of the arrays while data cache uses the lower half Figure 4 3 Page 4 9 Change reset value of ACR Bits 31 16 14 13 6 5 and 2 are undefined and other bits are cleared Change ACR fields to R W since they may be read via the debug module Section 4 4 2 2 Page 4 9 Change note to NOTE Peripheral IPSBAR space should not be cached The combination of the CACR defaults and the two ACRn registers must define the non cacheable attribute for this address space Figure 5 1 Page 5 2 Change RAMBAR fields to R W since they may be read via the debug module Table 5 1 Page 5 2 The PRI1 PRI2 text description does not match the table below it It should be If a bit is set CPU has priority If a bit is cleared DMA has priority Chapter 8 Remove any references to the core watchdog timer being able to reset the device It is only able to interrupt the processor Use the peripheral watchdog timer described in Chapter 18 if needing a watchdog timer to reset the device Table 9 4 Page 9 7 In the table for MFD bit definition footno
11. support with one user visible hardware breakpoint register Table 2 2 2 7 Change the field description to read Interrupt level mask Defines the current interrupt level Interrupt requests are inhibited for all priority levels less than or equal to the current level except the edge sensitive level 7 request which cannot be masked Table 5 1 5 2 Replace the description of PRI1 and PRI2 with the following Description Priority bit PRI1 determines if DMA or CPU has priority in upper 32K bank of memory PRI2 determines if DMA or CPU has priority in lower 32K bank of memory If bit is set DMA has priority If bit is reset CPU has priority Priority is determined according to the following table Upper Bank Lower Bank PRI 1 2 iin Priority 00 DMA Accesses DMA Accesses 01 DMA Accesses CPU Accesses 10 CPU Accesses DMA Accesses 11 CPU Accesses CPU Accesses NOTE The Motorola recommended setting for the priority bits is 00 Table 5 1 5 3 Add the following note to the SPV bit description The BDE bit in the second RAMBAR register must also be set to allow dual port access to the SRAM For more information see Section 8 4 2 Memory Base Address Register RAMBAR MCF5282 User s Manual Errata Rev 15 Freescale Semiconductor Errata for Revision 1 0 Table 4 MCF5282UM Rev 1 0 Errata continued Location Description Figure 6 2 6 4 Replac
12. 2 UTXD2 FlexCAN Transmit data 1 O C E14 SDA PAS1 URXD2 I C Serial data 1 0 Yes E15 SCL PASO UTXD2 I C Serial clock O Yes QSPI F13 QSPI_DOUT PQSO QSPI data out I O E16 QSPI_DIN PQS1 QSPI data in I O F14 QSPI_CLK PQS2 QSPI clock 1 O G14 G13 F16 F15 QSPI_CS 3 0 PQS 6 3 QSPI chip select 1 O UARTs R7 URXD1 PUA3 U1 receive data 1 0 P7 UTXD1 PUA2 U1 transmit data I O N6 URXDO PUA1 UO receive data 1 0 T7 UTXDO PUAO UO transmit data 1 0 C10 EMDIO PAS5 URXD2 U2 receive data 1 0 B10 EMDC PAS4 UTXD2 U2 transmit data 1 0 D16 CANRX PAS3 URXD2 U2 receive data 1 0 E13 CANTX PAS2 UTXD2 U2 transmit data 1 0 E14 SDA PAS1 URXD2 U2 receive data I O Yes E15 SCL PASO UTXD2 U2 transmit data 1 0 Yes K16 DTIN3 PTC3 URTS1 U1 U0 Request to Send I O URTSO K15 DTOUT3 PTC2 URTS1 U1 U0 Request to Send I O URTSO K14 DTIN2 PTC1 UCTS1 U1 U0 Clear to Send O UCTSO K13 DTOUT2 PTCO UCTS1 U1 U0 Clear to Send I O UCTSO J16 DTIN1 PTD3 URTS1 U1 U0 Request to Send I O URTSO MCF5282 User s Manual Errata Rev 15 Freescale Semiconductor 13 Errata for Revision 1 0 Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function continued Pin Functions Primar Internal MAPBGA Pin Description vO y Pull up Primary Secondary Tertiary i
13. 6 4 Address bus O Yes C4 B4 A4 B3 A3 A 20 16 PF 4 0 Address bus O Yes A2 B1 B2 C1 A 15 8 PG 7 0 Address bus O Yes C2 C3 D1 D2 D3 D4 E1 E2 A 7 0 PH 7 0 Address bus O Yes E3 E4 F1 F2 F3 G1 G2 G3 D 31 24 PA 7 0 Data bus 1 0 G4 H1 H2 H3 H4 J1 J2 J3 D 23 16 PB 7 0 Data bus 1 0 J4 K1 K2 K3 L1 L2 L3 L4 D 15 8 PC 7 0 Data bus 1 O M1 M2 M3 M4 N1 N2 N3 P1 D 7 0 PD 7 0 Data bus 1 O N5 T6 R6 P6 P14 T15 R15 R16 BS 3 0 PJ 7 4 Byte strobe 1 0 Yes N16 OE PE7 Output enable VO P16 TA PE6 Transfer acknowledge I O Yes P15 TEA PE5 Transfer error acknowledge O Yes N15 R W PE4 Read write 0 Yes N14 SIZ1 PE3 SYNCA Transfer size 1 O Yes MCF5282 User s Manual Errata Rev 15 Freescale Semiconductor 11 Errata for Revision 1 0 Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function continued Pin Functions o Primary Internal MAPBGA Pin l z Description O Pull up Primary Secondary Tertiary M16 SIZO PE2 SYNCB Transfer size 1 O Yes M15 TS PE1 SYNCA_ Transfer start I O Yes M14 TIP PEO SYNCB Transfer in progress I O Yes Chip Selects L16 L15 L14 L13 CS 3 0 PJ 3 0 Chip selects 3 0 1 0 Yes C6 B6 A5 A 23 21 PF 7 5 CS 6 4 Chip selects 6 4 O Yes SDRAM Controller H15 SRAS PSD5 SDRAM row address strobe 1 0
14. Freescale Semiconductor MCF5282UMAD User s Manual Addendum Rev 15 05 2007 MCF5282 User s Manual Errata by Microcontroller Division This errata document describes corrections to the Table of Contents MCF5282 ColdFire Microcontroller User s Manual i a 5 bae ae EE E EFT rrata for Revision 2 A PEPEE EE S EAE order number MCF5282UM For convenience the Seale fOr Revision 20 i occe cai cases seesesaeednaeiserdeseedes 6 addenda items are grouped by revision Please check our 4 Errata for Revision 1 0 scccccscsssssssssssssssssssssssseee website at http www freescale com for the latest 5 Reveion PRIORY cos ocicsasasssrssieicismareneanrcimnenes 16 updates ey PS r O S Freescale Semiconductor Inc 2007 All rights reserved Po freesca le semiconductor Errata for Revision 2 3 1 Errata for Revision 2 3 Table 1 MCF5282UM Rev 2 3 Errata Location Description Table 2 1 Page 2 4 Remove last sentence in C bit field description Table 2 3 Page 2 7 Change PC s Written with MOVEC entry to No Section 2 5 Page 2 8 Change last bullet to Use of separate system stack pointers for user and supervisor modes Section 2 5 Page 2 9 Change last sentence in fourth paragraph step 2 to The IACK cycle is mapped to special locations within the interrupt controller s address space with the interrupt level encoded in the address Figure 3 6 Page 3 8 Add minus sign to the exponent so that it
15. Signals and Pin Numbers Sorted by Function continued Pin Functions Primar Internal MAPBGA Pin Description vO y Pull up Primary Secondary Tertiary i E6 E11 F5 F7 F10 VDD Positive supply l F12 G5 G6 G11 G12 H5 H6 H11 H12 J5 J6 J11 J12 K5 K6 K11 K12 L5 L7 L10 L12 M6 M11 A1 A16 E5 E12 F6 VSS Ground l F11 G7 G10 H7 H10 J7 J10 K7 K10 L6 L11 M5 M12 T16 NOTES 1 Pull ups are not active when GPIO functions are selected for the pins The primary functionality of a pin is not necessarily its default functionality Pins that have GPIO functionality will default to GPIO inputs Pull up is active only with the SYNCA function Pull up is active only with the SYNCB function Pull up is active only with the SDA function Pull up is active only with SCL function Pull up is active when JTAG_EN is driven high N OUA O 5 Revision History Table 5 provides a revision history for this document Table 5 Revision History Table Rev Number Substantive Changes Date of Release 0 Initial release 07 2003 1 Added page erase verify errata for Chapter 6 ColdFire Flash Module CFM 09 2003 2 Added errata for UART interrupt status register 11 2003 Added errata for PIT timer timeout equation e Added I2CR write errata e Added errata for Internal Pull Up column in MCF5282 Signals and Pin Numbers Sorted by Function table e Added er
16. cs for the 66MHz device in the first 2 rows and also declare symbol fsys max aS Shown below Max Characteristic Symbol Min Unit 66MHz 80MHz PLL Reference Frequency Range MHz Crystal reference fref_crystal 2 8 33 10 0 External reference fref ext 2 8 33 10 0 1 1 Mode fref 1 1 33 33 66 66 80 System Frequency fsys fsysmax fsys max MHz External Clock Mode 0 66 66 On Chip PLL Frequency fret 32 66 66 80 MCF5282 User s Manual Errata Rev 15 Freescale Semiconductor Errata for Revision 2 1 amp 2 2 Table 1 MCF5282UM Rev 2 3 Errata continued Location Description Table 33 8 Page 33 7 Change EXTAL Input High Voltage ViHexr Crystal Mode minimum spec from Vpp 1 0 to VXTAL 0 4 Change EXTAL Input Low Voltage ViLexr Crystal Mode maximum spec from 1 0 to VXTAL g 0 4 Section 33 13 1 Page 33 21 Remove second sentence There is no minimum frequency requirement Section 33 13 2 Page 33 22 Remove second sentence There is no minimum frequency requirement Remove second paragraph as this feature is not supported on this device The transmit outputs ETXD 3 0 ETXEN ETXER can be programmed to transition from either the rising or falling edge of ETXCLK and the timing is the same in either case This options allows the use of non compliant MII PHYs Refer to the Ethernet chapter for details of this option and how to enab
17. e fetched is already being processed internally as a result of a wrap As the FEC nears the end of the transmission of one frame it begins to DMA the data for the next frame In order to remain one BD ahead of the DMA it also fetches the TxBD for the next frame It is possible that the FEC will fetch from memory a BD that has already been processed but not yet written back that is it is read a second time with the R bit still set In this case the data is fetched and transmitted again Using at least three TxBDs fixes this problem for large frames but not for small frames To ensure correct operation for either large or small frames one of the following must be true e The FEC software driver ensures that there is always at least one TxBD with the ready bit cleared e Every frame uses more than one TxBD and every TxBD but the last is written back immediately after the data is fetched e The FEC software driver ensures a minimum frame size n The minimum number of TxBDs is then Tx FIFO Size n 4 rounded up to the nearest integer though the result cannot be less than three The default Tx FIFO size is 192 bytes this size is programmable Table 17 9 Page 17 17 Correct MIB block counters end addresses to IPSBAR 0x12FF Table 17 11 Page 17 19 Add RMON_R_DROP with an IPSBAR Offset of 0x1280 and a description of Count of frames not counted correctly Figure 17 26 Page 17 41 Section 20 5 13 Page 20 12
18. e Figure 6 2 CFM 512K Array Memory Map with the figure below iil Logical Block 1 256 Kbytes 0x0004 000C 0x0004 0008 0x0004 0004 0x0004 0000 L 0x0003 FFFF R A Flash Physical Block 0 Configuration Field 0x0000_0400 0x0000_0417 l Memory Memory Memory i Array 0H Array 1H Array 1L 0x0000 000C 0x0000 0008 oL 1 0x0000 0004 iL 0x0000 0000 oL o 0x0007 FFFF Flash Physical Block 2 Flash Physical Block 3 er ae arr aT Memory Memory Array 3H Array 3L Each memory array 64 Kbytes 16 bits wide x 32K Each physical block 128 Kbytes 32 bits wide x 32K Figure 6 2 CFM 512K Array Memory Map Table 6 12 6 16 Change value for page erase verify command to 0x06 Table 6 13 6 20 Change value for page erase verify command to 0x06 Table 8 3 8 5 Add the following note the BDE bit description The SPV bit in the CPU s RAMBAR must also be set to allow dual port access to the SRAM For more information see Section 5 3 1 SRAM Base Address Register RAMBAR Figure 9 1 9 3 Remove 2 from CLKGEN block 10 3 6 10 11 Add this text to the end of the first paragraph If a specific interrupt request is completely unused the ICRnx value can remain in its reset and disabled state 10 5 10 17 Add the following note The wakeup mask level taken from LPICR 6 4 is adjusted by hardware to allow a level 7 IRQ to generate a wakeup That is the wakeu
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20. een masked A spurious interrupt is generated because the CPU cannot determine the interrupt source To avoid this situation for interrupts sources with levels 1 6 first write a higher level interrupt mask to the status register before setting the mask in the IMR or the module s interrupt mask register After the mask is set return the interrupt mask in the status register to its previous value Since level seven interrupts cannot be disabled in the status register prior to masking use of the IMR or module interrupt mask registers to disable level seven interrupts is not recommended MCF5282 User s Manual Errata Rev 15 Freescale Semiconductor 5 Errata for Revision 2 0 Table 2 MCF5282UM Rev 2 1 amp 2 2 Errata continued Location Description Chapter 17 The maximum buffer size of the FEC is 2032 bytes Replace any mention of the max size being 2047 bytes with 2032 bytes Table 17 2 17 5 In PALR PAUR entry delete only needed for full duplex flow control Figure 17 23 17 39 Change FRSR to read write instead of read only 25 4 10 25 16 Change CANICR to ICRn Table 25 17 25 29 Add the following information to BITERR and ACKERR descriptions To clear this bit first read it as a one then write it as a one Writing zero has no effect Table 25 17 25 30 Change bit ordering ERRINT should be bit 2 and BOFFINT should be bit 1 Table 25 19 25 32 Change BUF nl field description from
21. evision 10 of this document as it was incorrect Only the internal UART clock source is prescaled by the 16 bit divider Added 2 UART external clock source errata removing the 16 bit divider from a figure and equation 08 2005 12 Added core watchdog unable to reset the device errata Added EMRBR register address errata Added lop and lo errata 12 2005 13 Added FlexCAN flag clearing mechanism errata in interrupt controller Added FlexCAN ESTAT register description errata for various bits Added ICRnx note regarding unique and non overlapping level and priority definitions Added DTOUT1 DTINO DTOUTO description field errata in GPIO chapter Added FEC MII transmit and receive specification section errata 08 2006 14 Deleted reference to nonexistent CF bits in the figure and bit descriptions for the GPTFLG2 register Added RMON_R_DROP counter errata 11 2006 15 Added various core EMAC cache SRAM and debug chapter errata Added Vj and Vi crystal mode spec changes Added DACRnr CBM field description note Added FEC MIB counter memory map errata Added Duplicate Frame Transmission section to FEC chapter Added DMA SAA bit errata Added global IACK register space errata 05 2007 MCF5282 User s Manual Errata Rev 15 Freescale Semiconductor 17 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not List
22. le it Table A 3 Page A 4 The CSMR1 and CSCR1 register addresses are incorrect They should be IPSBAR 0x090 and IPSBAR 0x096 respectively 2 Errata for Revision 2 1 amp 2 2 Table 2 MCF5282UM Rev 2 1 amp 2 2 Errata Location Description Figure 4 2 4 6 Changed bit 23 from DIDI to DISI Table 4 6 4 9 Under Configuration for Instruction Cache the Operation entry changed to Invalidate 2 KByte data cache Table 4 6 4 9 Under Configuration for Data Cache the Operation entry changed to Invalidate 2 KByte instruction cache Figure 6 3 6 6 Changed bit 8 to write only instead of read write Table 6 10 6 15 Removed selected by BKSL 1 0 as these are internal signal names not necessary for end user Table 9 4 9 7 In the table for MFD bit definition footnote 1 equation should read fret x 2 MFD 2 fsys oRFD fret X 2 MFD 2 lt fsys max fsys fsys max Where fsys max is the maximum system frequency for the particular MCF5282 device 66MHz or 80MHz 10 3 2 10 8 Add the following note If an interrupt source is being masked in the interrupt controller mask register IMR or a module s interrupt mask register while the interrupt mask in the status register SR I is set to a value lower than the interrupt s level a spurious interrupt may occur This is because by the time the status register acknowledges this interrupt the interrupt has b
23. p mask value used by the interrupt controller must be in the range of 0 6 Figure 12 4 12 8 Change CSCRn to reflect that AA is set to 1 at reset 13 5 13 15 Remove final paragraph The paragraph incorrectly states that the MCF5282 does not have a bus monitor MCF5282 User s Manual Errata Rev 15 8 Freescale Semiconductor Errata for Revision 1 0 Table 4 MCF5282UM Rev 1 0 Errata continued Location Description Table 17 13 17 26 Change encodings for bits 31 9 to OThe corresponding interrupt source is masked 1The corresponding interrupt source is not masked Chapter 19 Change PIT1 PIT4 to PITO PIT3 throughout chapter When a timer is referenced individually PIT1 should be PITO PIT2 should be PIT1 PIT3 should be PIT2 and PIT4 should be PIT3 Other chapters in the user s manual use the correct nomenclature PITO PITS 19 6 3 19 7 Change timeout period equation to the equation below Timeout period PRE 3 0 x PM 15 0 1 x 2 system clock Figure 23 11 Change UISR bits 5 3 to reserved bits 24 6 1 24 11 Change I2CR 0xA to I2CR OxA0 27 2 1 27 2 Change When interfacing to 16 bit ports the port C and D pins and PJ 7 6 BS 3 2 can be configured as general purpose input output I O To When interfacing to 16 bit ports the port C and D pins and PJ 5 4 BS 1 0 can be configured as general purpose input output I O 32 2 32 7
24. rata for SDRAM Read Cycle figure e Added errata for Chapter 19 PIT1 PIT4 should be PITO PIT3 01 2004 4 Added errata for spurious interrupt 03 2004 e Added errata for Table 33 8 Single instance of T T to Ty was overlooked in revision 2 0 of the manual This instance has now been removed 5 e Added errata for Section 25 4 10 change CANICR to ICRn 03 2004 Added errata for BITERR and ACKERR field descriptions e Added errata for BOFFINT and ERRINT bit sequence e Added errata for BUF nl field description MCF5282 User s Manual Errata Rev 15 16 Freescale Semiconductor Table 5 Revision History Table continued Revision History Rev Number Substantive Changes Date of Release 6 Added errata for Table 17 2 Added errata for FRSR register diagram 11 2004 Added errata for Figure 4 2 Table 4 6 Figure 6 3 and Table 6 10 11 2004 Added the below errata for MCF5282UM Rev 2 3 Added FEC max buffer size errata Added VDD VDDH power up requirement Added MFD bit definition footnote errata Added PLL spec table entries for 66MHz device 01 2005 Added INTFRCL figure errata Added BAM bit field example errata 03 2005 10 Added SDRAM NOP command errata Added UART clock source errata 07 2005 11 Added PRI1 PRI2 text description errata Added CSMR1 CSCR1 register address errata Removed Table 23 5 errata that was added in r
25. t read it as a one then write it as a one Writing zero has no effect Table 25 17 Page 25 27 Definition of bits ERRINT and BOFFINT are incorrect for register ESTAT ERRINT should be bit 1 BOFFINT should be bit 2 They should be cleared by writing a one instead of a zero Table 26 1 Page 26 5 Change description field for DTOUT1 from DMA timer 1 output Port TD 3 to DMA timer 1 output Port TD 2 Change description field for DTINO from DMA timer 0 input Port TD 3 to DMA timer 1 output Port TD 1 Change description field for DTOUTO from DMA timer 0 output Port TD 3 to DMA timer 1 output Port TD O Table 30 12 Page 30 14 Add the following note to the PBR Address field description Note PBR 0 should always be loaded with a 0 Table 30 20 Page 30 35 Chapter 33 Table 33 3 Page 33 3 Table 33 8 Page 33 7 Change CSR s initial state to Ox0000_0000 Add the following note It is crucial during power up that VDD never exceeds VDDH by more that 0 3V There are diode devices between the two voltage domains and violating this rule can lead to a latch up condition In the Voy and Vo entries change the respective lop and Io specs from lop 2 0mA to lop 5 0mA and Io 2 0mA to lo 5 0MA In the PLL Electrical Specifications table only specs for the 80 MHz MCF5282 device were listed Insert spe
26. te 1 equation should read fret x 2 MED 2 sys Oa fro MF 2 51 Where fsys max S the maximum system frequency for the particular MCF5282 device 66MHz or 80MHz f sys max fsys lt fsys max Section 10 3 6 Page 10 11 Include the following text in the section description and as a note in Figure 10 9 It is the responsibility of the software to program the ICRnx registers with unique and non overlapping level and priority definitions Failure to program the ICRnx registers in this manner can result in undefined behavior If a specific interrupt request is completely unused the ICRnx value can remain in its reset and disabled state Figure 10 6 Page 10 9 Interrupt Force Register Low INTFRCLn is illustrated as read only in the figure However this register should be read write MCF5282 User s Manual Errata Rev 15 2 Freescale Semiconductor Errata for Revision 2 3 Table 1 MCF5282UM Rev 2 3 Errata continued Location Table 10 14 Page 10 15 Table 12 7 Page 12 7 Description Change flag clearing mechanism for sources 24 26 They should read as follows Write ERR_INT 1 after reading ERR_INT 1 Write BOFF_INT 1 after reading BOFF_INT 1 Write WAKE_INT 1 after reading WAKE_INT 1 BAM bit field description the first example should read So if CSARO 0x0000 and CSMRO BAN 0x0001 instead of So if CSARO 0x0000 and CSMRO BAN 0x0008 Table
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