IP-Unidig-E-48
Contents
1. 1 0 1 0 Line Bit map of bytes at base 42 and base 46 DataBit 7 6 5 4 3 2 1 0 1 0 Line Bit map of byte at base C Data Bit RUNE Gert 0 O Wie ClockPolaity Dbl Buffer En Read 0 Clock Polarity Dbl Buffer En I O Pin Wiring This section gives the pin assignments and wiring recommendations for IP Unidig E 48 The pin numbers given in Figure 2 below correspond to numbers on the 50 pin IndustryPack I O connector to the wires on a 50 pin flat cable plugged into a standard IP carrier board and to the screw terminal numbers on the IP Terminal block I O 1 1 I O 2 2 I O 3 3 I O 4 4 I O 5 5 I O 6 6 I O 7 7 I O 8 8 1 0 9 9 I O 10 10 I O 11 11 I O 12 12 I O 13 13 I O 14 14 1 0 15 15 I O 16 16 I O 17 17 I O 18 18 1 0 19 19 I O 20 20 I O 21 21 I O 22 22 I O 23 23 I O 24 24 I O 25 25 I O 26 26 I O 27 27 I O 28 28 I O 29 29 1 0 30 30 I O 31 31 I O 32 32 1 0 33 33 I O 34 34 I O 35 35 I O 36 36 I O 37 37 I O 38 38 I O 39 39 I O 40 40 I O 41 41 I O 42 42 1 0 43 43 I O 44 44 I O 45 45 I O 46 46 I O 47 47 I O 48 48 Double Buffer Clk 49 GND 50 Figure 7 I O Pin Assignment IndustryPack Logic Interface Pin Assignment Figure 3 below gives the pin assignments for the IndustryPack Logic Interface on the IP Unidig E 48 Pins marked n c below are defined by the specification but are not used on IP Unidig E 48 Also see the User Manual for your IP Carrier b2. D0 ISA IBM PC AT Addressing IP Unidig E 48 normally is accessed one word at a time in the host s I O space Alternatively byte accesses may be used The actual application will depend on the carrier board See the carrier board manual for details Standard Word Access I O Space base 0 write Output lines 1 16 base 2 write Output lines 17 24 base 0 read Read Back lines 1 16 base 2 read Read Back lines 17 24 base 4 read Direct Read lines 1 16 base 6 read Direct Read lines 17 24 base C read write Control Register base 40 write Output lines 25 40 base 42 write Output lines 41 48 base 40 read Read Back lines 25 40 base 42 write Read Back lines 41 48 base 44 read Direct Read lines 25 40 base 46 read Direct Read lines 41 48 Figure 5 Word Access ISA Address Map Bit map of words at base 0 and base 4 Data Bit 15 14 13 12 111 101 9 8 7 6 5 4131 2 1 0 HO Lines 16515 14 19 12 11 10 9 8 734 6 Joe 3 02 1 Bit map of words at base 2 and base 6 Data Bit 15 14 13 12 10 9 8 7 6 5 4 3 2 1 OC a ef ae Ee ae eee 191 19 17 Bit map of words at base 40 and base 44 DataBit 15 14 13 12 111 10 9 8 71 6 5 4 3 2 1 1 0 Line Bit map of words at base 42 and base 46 DataBit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 11 0 TER
3. ER ENE EEE Ee EE ae 1 43 I Bit map of word at base C DaaBit 52 Write NET USE Clock Polarity Dbl Buffer En 0 Clock Polarity Dbl Buffer En Alternative Byte Access I O Space base 0 Output lines 1 8 base 1 Output lines 9 16 base 2 Output lines 17 24 base 0 Read back lines 1 8 base 1 Read back lines 9 16 base 2 Read back lines 17 24 base 4 Direct Read lines 1 8 base 5 Direct Read lines 9 16 base 6 Direct Read lines 17 24 base C Control Register base 40 i Output lines 25 32 base 41 i Output lines 33 40 base 42 Output lines 41 48 base 40 Read back lines 25 32 base 41 Read back lines 33 40 base 42 Read back lines 41 48 base 44 Direct Read lines 25 32 base 45 Direct Read lines 33 40 base 46 Direct Read lines 41 48 Figure 6 Byte Access ISA Address Map Bit map of bytes at base 0 and base 4 DataBit 7 6 5 4 3 2 1 0 YO Line 8 7 6 5 4 3 2 1 Bit map of bytes at base 1 and base 5 DataBit 7 6 5 4 3 2 1 0 I O Line 16 15 14 13 12 11 10 9 Bit map of bytes at base 2 and base 6 Data Bit 7 6 5 4 3 2 1 0 1 0 Line Bit map of bytes at base 40 and base 44 DataBit 7 6 5 4 3 2 1 0 Bit map of bytes at base 41 and base 45 DataBit 7 6 5 4 3 2
4. If double buffering is enabled the D ouble Buffer Clock Polarity Bit bit 1 in the Control Register is used to set the Double Buffer Clock polarity Setting the Double Buffer Clock Polarity Bit to a 0 will latch data on the rising edge and setting it to a 1 will latch data on the falling edge The power up default is 0 for both these bits Data Input The data may be read from two sets of address locations The first set of locations base 0 base 2 and base 40 and base 42 for word operations function as the Internal Read Back Register The data latched in the Internal O utput Latch is read from these addresses They support processor bit operations implemented as read modify write cycles and are also useful for debugging purposes The second set of locations base 4 base 6 and base 44 and base 46 for word operations is the Direct Read Register Data is latched into Input Register with the same clock which latches the D ouble Buffer Latch Figure 11 shows a block diagram Internal Double Buffer Latch Latch Read Back Buffer Data Bus Double Buffer Clk Clk Pol Sel Double Buffer Enable Figure 11 T O Line Block Diagram Construction and Reliability IndustryPacks were conceived and engineered for rugged industrial environments The IP UniDig E is constructed out of 0 062 inch thick FR4 V0 material The four copper layers consist of two signal layers on the top and bottom and two intern
5. workmanship and materials under normal use and service and in its original unmodified condition for a period of one year from the time of purchase If the product is found to be defective within the terms of this warranty GreenSpring Computer s sole responsibility shall be to repair or at GreenSpring Computer s sole option to replace the defective product The product must be returned by the original customer insured and shipped prepaid to G reenSpring Computers All replaced products become the sole property of GreenSpring Computers GreenSpring Computer s warranty of and liability for defective products is limited to that set forth herein GreenSpring Computers disclaims and excludes all other product warranties and product liability expressed or implied including but not limited to any implied warranties of merchandisability or fitness for a particular purpose or use liability for negligence in manufacture or shipment of product liability for injury to persons or property or for any incidental or consequential damages GreenSpring s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of GreenSpring Computers Inc Service Policy Before returning a product for repair verify as well as possible that the suspected unit is at fault Then call the Customer Service D epartment for a RETURN MATERIAL AUTHORIZATION RMA number Carefully package t
6. GreenSpring Modular I O IP Unidig E 48 48 Line Input Output with LineSafe ESD Protection IndustryPack User s Manual Manual Revision 3 7 28 99 Hardware Revision B IP Unidig E 48 415 327 3808 FAX 48 Line Input Output with LineSafe M ESD Protection IndustryPack GreenSpring Computers 181 Constitution Drive Menlo Park CA 94025 415 327 1200 This document contains information of 1994 1996 by GreenSpring Computers Inc n E IndustryPack is a trademark of GreenSpring Computers proprietary interest to GreenSpring Macintosh is a registered trademark of Apple Computers Computers It has been supplied in confidence and the recipient by accepting this material agrees that the subject matter will not be copied or reproduced in whole or in part nor its contents revealed in any manner or to any person except to meet the purpose for which it was delivered GreenSpring Computers has made every effort to ensure that this manual is accurate and complete Still the company reserves the right to make improvements or changes in the product described in this document at any time and without notice Furthermore GreenSpring Computers assumes no liability arising out of the application or use of the device described herein The electronic equipment described herein generates uses and can radiate radio frequency energy Operation of this equipment in a residential area is likely to cause radio interference in whic
7. al power and ground plane layers Through hole and surface mounting of components are used IC sockets use gold plated screw machine pins High insertion and removal forces are required which assists in keeping components in place If the application requires unusually high reliability or is in an environment subject to high vibration the user may solder the four corner pins of each socketed IC into the socket using a grounded soldering iron The IndustryPack connectors are keyed shrouded and have gold plated pins on both plugs and receptacles They are rated at 1 Amp per pin 200 insertion cycles minimum These connectors make consistent correct insertion easy and reliable The IP is secured to the carrier with four M2 metric stainless steel screws The heads of the screws are countersunk into the IP The four screws provide significant protection against shock vibration and incomplete insertion For most applications they are not required The IndustryPack provides a low temperature coefficient of 0 89 W C for uniform heat This is based on the temperature coefficient of the base FR4 material of 0 31 W m C taking into account the thickness and area of the IP This coefficient means that if 0 89 Watts is applied uniformly on the component side then the temperature difference between the component and the solder side is one degree Celsius 20 Warranty and Repair GreenSpring Computer warrants this product to be free from defects in
8. byte reserved Revision Model No IP Unidig E 48 Manufacturer ID GreenSpring ASCII C ASCII A ASCII P ASCII T Figure 10 ID PROM Data hex Theory of Operation IndustryPack Standards The IP Unidig E 48 is part of the IndustryPack family of modular I O products It meets the IndustryPack Logic Specification Contact G reenSpring Computers Inc for a copy of this Specification It is assumed the reader is at least casually familiar with both this document and 68000 processor architecture Control Logic All control logic is contained within a single Xilinx FPGA It is clocked by the 8 MHz IP Logic clock from the Support Module The IP responds to I O and ID selects It does not respond to memory selects however the ME MSel line is routed to the FPGA enabling easy modification for special needs The IP does not require wait states for either read or write cycles Thus the FPGA generates Ack on the clock cycle following either I O or ID Select Hold cycles from the Support Module are supported for both read and write cycles by extending Ack as required If no hold cycles are requested by the Support Module the IP is capable of supporting the full 8 MByte per second data transfer rate of the IP Logic Interface Specification I O Data Lines All input and output latches and buffers are contained within the Xilinx FPGA Each I O line has GreenSpring s unique LineSafe ESD protection circuit for added r
9. e Buffer E nable Double Buffer Enable bit This bit enables double buffering If this bit is set to a 1 the user must provide a clock on the Double Buffer Clock pin 49 This clock may be up to 1 MHz and must have an edge rate faster than 60 ns Writing a 0 disables double buffering This is the default Bit 1 D1 Double Buffer Clock Polarity Select Double Buffer Clock Polarity Select bit This bit controls the D ouble Buffer Clock polarity Writing a 1 will cause output data to be latched out of the IP and input data to be latched into the IP on the falling edge of the Double Buffer Clock Writing a 0 will cause data to be latched on the rising edge of the Double Buffer Clock This is the default Bit 7 2 D7 D2 These bits are reserved for future use and will be read as 0 Double Buffering Double buffering is a feature which allows all the inputs and outputs to be latched at the same time whether on a single IP or a system with multiple IPs This is useful for systems which require many inputs and outputs to be updated simultaneously To use double buffering an external TTL or CMOS level clock with an edge rate faster than 60 ns must be provided on Pin 49 the Double Buffer Clock Input pin and the D ouble Buffer Enable bit Bit 0 in the Control Register must be set The Double Buffer Clock polarity is programmable via the D ouble Buffer Clock Polarity bit Bit 1 in the Control Register Setting this bit to a 0 will caus
10. e the input and outputs to be latched on the rising edge of the Double Buffer Clock while setting the bit to 1 will latch the inputs and outputs on the falling edge ID PROM Every IP contains an IP PROM whose size is at least 12 x 8 bits The ID PROM aids in software auto configuration and configuration management The user s software or a supplied driver may verify that the device it expects is actually installed at the location it expects and is nominally functional The ID PROM contains the manufacturing revision level of the IP If a driver requires a particular revision IP it may check for it directly Standard data in the ID PROM on the IP Unidig E 48 is shown in Figure 10 below For more information on IP ID PRO Ms refer to the IndustryPack Logic Interface Specification available from GreenSpring Computers Inc The ID PROM on the IP Unidig E 48 is implemented in the Xilinx FPGA device The location of the ID PROM in the host s address space is dependent on the carrier board used For most VMEbus carriers the ID PROM space is directly above the IP s I O space or at IP base 80 Macintosh drivers use the ID PROM automatically RM 1260 address may be derived from Figure 5 below by multiplying the addresses given by two then subtracting one RM1270 addresses may be derived by multiplying the addresses given by two then adding one available for user CRC for bytes used No of bytes used Driver ID high byte Driver ID low
11. ersssersssessssessssns 3 Byte Access VME Address Map scssssssssssssssssssesssscsssessssecsssssssssssssecsssssssscssssccsssccsscsssecesseessss 5 Long Word Access VME Address Map c sssssssscssssssssssssssssssssssessssscssssssssscssseesssecessecssneeeseesese 7 Word Access ISA Address Map sseccsssesssssssssssssssssessssecssssssssssssnscsssecsssccsssesssssessecssuesssseseseeess 9 Byte Access ISA Address Map issesrssssrssssrsssrssssrsssersssrrsssrssssrsssersssersssrssssersssrssssersssersssesssser 10 V Pur Assignment ER eed 12 Logic Interface Pin Assignmenti iui lana 13 Control Register Bit D efinitions s essersssrnsssrsesessesesssseseserse 14 ID PROM Data OX unde eite ue ener pectet tu 16 I O Line Block Diagram err e t e REED 18 Product Description The IP Unidig E 48 is part of the IndustryPack family of modular I O components It provides 48 lines of digital I O each with G reenSpring s unique LineSafe electrostatic discharge ESD protection circuit for increased ruggedness Each line may be dynamically and individually configured for either input or output Outputs may be double buffered making it possible to synchronize multiple IPs Both internal read back and direct read registers are provided for ease of software development 16 bit word and 8 bit byte operations are supported The IP Unidig E 48 conforms to the IndustryPack Interface Specification This guarantees compatibility with multiple Support M
12. h case the user at his own expense will be required to take whatever measures may be required to correct the interference GreenSpring s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of GreenSpring Computers Inc This product has been designed to operate with IndustryPack carriers and compatible user provided equipment Connection of incompatible hardware is likely to cause serious damage Table of Contents Product Descriptions riore 1 VME bus Addt ssing ett i ea d liebe a le e tette n ettet eer 3 NubBus Addressing s reali One 8 ISA IBM PC AT Addressing ii i 9 TO Pin Wiring p ee 12 IndustryPack Logic Interface Pin Assignment csssssssessssecssecssssssecsssesssscsssecssssssssccsssecesecssseessseesssessse 13 Ionic eee 14 ID PROM e alal 16 ThEOTF OF O DeratioTi s aod ala 17 Construction and Reliabilily tete e ERROR XR e RR t 19 Marranty and Repair esaet ORDRES SIRE RR ERUNT 20 Specifications aie aie RR OR UR HERE EAR IRIS NUN HE a n utei 21 Order Information i aaa a 22 SCHEMATICS iriri oe RR 23 List of Figures IP Unidig E 48 Block Diagraim ecssecssssessssssssssssessssesssesssssssssecsssecssscssssessssccssscsssscsssecssseessss 2 Word Access VME Address Map s essssssersssrrssersssrrsssrrsssrssssrssssrssssersssersssrrssersss
13. he unit in the original shipping carton if this is available and ship prepaid and insured with the RMA number clearly written on the outside of the package Include a return address and the telephone number of a technical contact For out of warranty repairs a purchase order for repair charges must accompany the return G reenSpring Computers will not be responsible for damages due to improper packaging of retumed items For service on GreenSpring Products not purchased directly from G reenSpring Computers contact your reseller Products returned to G reenSpring Computers for repair by other than the original customer will be treated as out of warranty Out of Warranty Repairs Out of warranty repairs will be billed on a material and labor basis The current minimum repair charge is 100 Customer approval will be obtained before repairing any item if the repair charges will exceed one half of the quantity one list price for that unit Return transportation and insurance will be billed as part of the repair and is in addition to the minimum charge For Service Contact Customer Service Department GreenSpring Computers 181 Constitution Drive Menlo Park CA 94025 415 327 1200 415 327 3808 fax 21 Specifications Logic Interface Digital Interface Interface Level Software Interface Initialization Access Mode Wait States Transfer Rate Onboard Options Dimensions Construction Temperature Coefficient Power Re
14. location This is the default To write a zero on the I O signal line write a 0 to the I O bit location To write a one on the I O signal line write a 1 to the I O bit location Writing a one and setting the signal line to input mode is the same Passive pull up resistors are used with tri state drivers to implement the interface Using word access up to 16 bits may be programmed at once The IP implements a read back register at the same address used for writing to the signal line I O bits This permits set bit and clear bit instructions to be used in programming which are implemented by the host hardware as read modify write cycles Thus single bits at well as bit fields may be accessed The IP is organized into two 24 bit registers to maintain software compatibility with the Unidig family memory map The IP may also be accessed using byte or long word accesses If long word accesses are used from a 68020 68030 or 68040 host the I O space must be mapped into D 16 68000 and 68010 hosts internally map all long word accesses into 16 bits so no special precaution is necessary Long word accesses use two separate IP cycles The IP uses a Control Register to enable double buffering and control the polarity of the D ouble Buffer Clock T 0 Double Buffer Enable Read Write Double Buffer Clock Polarity Select Read Write Figure 9 Control Register Bit Definitions Control Register Bit Definitions Bit 0 2 DO LSB Doubl
15. ly suited for generating this clock though most TTL compatible clock sources may be used Two separate locations in I O space are provided for each signal line The first location is used to set the output state and also to read back the written value at the internal latch This read back function is valuable to support bit operations which are implemented by processors as read modify write cycles It is also useful in debugging making it possible to observe directly the last value written to the port The second location is the direct read port which is always used for reading input values This register may also be used to verify the correct logic signal is actually on the interface cable Figure 1 shows a block diagram of the IP Unidig E 48 Xilinx FPGA ID PROM I P Bus Interface Control Register Figure 1 Input Register 1 R Output Register 1 Input Register 48 Output Register 48 Clock Control IP Unidig E 48 Block Diagram LineSafe ESD Circuit LineSafe ESD Circuit Double Buffer LineSafe Clock ESD Circuit VMEbus Addressing IP Unidig E 48 normally is accessed one word at a time in the host s I O space Alternatively byte or long word accesses may be used If long words are used the host or support module must map 32 bit long words into two 16 bit cycles This is common for 68020 and 68030 implementation of the I O space Standard Word Access I O Space base 0x0 write Out
16. oard for more information GND GND 26 CLK 45V Reset R W 28 DO IDSel Di n c 30 D2 n c D3 n c 32 D4 n c D5 n c 34 D6 IOSel D7 n c 36 D8 AI D9 n c 13 38 D10 A2 n c 15 40 D12 A3 D13 n c 17 42 D14 A4 D15 n c 19 44 BSO AS BS1 n c 21 46 12V A6 12V Ack 23 48 5V n c GND GND 25 50 Note 1 The no connect n c signals above are defined by the IndustryPack Logic Interface Specification but not used by this IP See the Specification for more information Note 2 The layout of the pin numbers in this table corresponds to the physical placement of pins on the IP connector Thus this table may be used to easily locate the physical pin corresponding to a desired signal Pin 1 is marked with a square pad on the IndustryPack Figure 8 Logic Interface Pin Assignment Programming Programming the IP requires only the ability to read and write data in the host s I O space The base address is determined by the IP Support Module This document refers to this address as base After power on reset or VME system reset the IP requires a minimum delay of 300 milliseconds before any accesses are made by the host system This is to allow the Xilinx FPGA to configured itself Any accesses during this time will result in a bus error Reset sets all lines to be inputs and clears all bits in the Control Register Each of the 48 bits may be individually set as input or output To set a bit to be input write a 1 to the I O bit
17. odules Because the IPs may be mounted on different form factors while maintaining plug and software compatibility system prototyping may be done on one Support Module with final system implementation on a different one The IP Unidig E 48 is a member of the Unified Digital family of I O It is the only member with 48 outputs which are organized as two 24 bit registers Other members of the family include a 24 I O version with ESD protected I O buffered TTL I O differential I O optically isolated I O and high voltage I O Functions implemented within each output type include double buffered I O I O with interrupts on all input lines and four independent timers The software interface to the IP Unidig E 48 is simple and straight forward Writing a one to any line turns off the output driver allowing a passive pull up resistor to set the line to a logic high Writing a zero to any line turns on the driver driving the line to a logic low For input use a one is written to the corresponding line this is the power up default For output use the binary value desired is written to the corresponding line Input and output lines may be double buffered by setting a bit in the Control Register When this bit is set the user must provide an external clock of up to 1 MHz Another bit in the Control Register selects the polarity of this clock allowing inputs and outputs to be latched on either the rising or falling clock edge The IP Unidig T is ideal
18. put lines 1 16 base 0x2 write Output lines 17 24 base 0x0 read Read back lines 1 16 base 0x2 read Read back lines 17 24 base 0x4 read Direct read lines 1 16 base 0x6 read Direct read lines 17 24 base C read write Control Register base 0x40 write Output lines 25 40 base 0x42 write Output lines 41 48 base 0x40 read Read backlines 25 40 base 0x42 read Read backlines 41 48 base 0x44 read Direct read lines 25 40 base 0x46 read Direct read lines 41 48 Figure 2 Word Access VME Address Map Bit map of words at base 0 and base 6 Data Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 I O Line 16 15 14 13 2 i 0 9 8 7 615 4 3 24 1 Bit map of words at base 2 and base 8 DataBit 15 14 13 12 10 9 8 7 6 5 41 3 2 11 WO Line l 24 23 22 2t 20 19 18 17 Bit map of words at base 40 and base 44 Data Bit 15 14 13 12 111101 91 8 71 6 5141312111 0 1 0 Line Bit map of words at base 42 and base 46 DataBit 15 14 13 121 1110 918 71 6 5 J 4 3 2 11 0 VO Tie ER ER EN EN EE EN ENE EEE EEE 4E Bit map of word at base C Data Bit m52 1 0 k Wie Clock Polanty Dbl Buffer En Read 0 Clock Polarity Dbl Buffer En Alternate Byte Access I O Space base 0x0 write Output lines 9 16 base 0x1
19. quirements IndustryPack Logic Interface 48 digital signal lines with double buffered outputs and latched inputs Each line is either an input or an output TTL Tri state with 10 K Ohm pull up resistor standard 4 mA current sink The 48 I O lines are read and written to with either word or byte accesses There is an 8 bit Control register 300 millisecond delay from reset Forces all lines to be inputs Disables double buffering Byte or word in I O Space Byte or word in ID Space Zero 8 Mbytes second maximum continuous All options are software programmable Standard Single High IndustryPack width and length 1 8 x 3 9 inches Conformal Coated FR4 4 layer Printed Circuit Surface mounted components 0 89 W C for uniform heat across IP 45 0 VDC 50mA typical 22
20. t base D DaaBit 72 i 0 O Wit GlockPolarty Dbl Buffer En Read 0 Clock Polarity Dbl Buffer En Alternate Long Word Access I O Space base 0 write Output lines 1 24 base 0 read Read Back lines 1 24 base 4 read Direct Read lines 1 24 base C read write Control Register base 40 write Output lines 25 48 base 40 read Read Back lines 25 48 base 44 read Direct Read lines 25 48 Figure 4 Long Word Access VME Address Map Bit map of long words at base 0 and base 4 Data Bit I O Line 16 15 14 13 12 11 10 9 81 7 6 5 4 3 24 1 DataBit 15 14 13 12 111 101 9 8 7 6 5 4 3 2 1 yo Linee 24 23 22 21 20 19 18 17 Bit map of long words at base 40 and base 44 Data Bit 1 0 Line DataBit 15 14 13 12 111 101 9 8 7 6 5 4 3 2 1 IFO ine ee a Ee eee Bit map of long word at base C 31 18 15 0 Wie ClockPolarity DbLBufferEn Read o Clock Polarity Dbl BufferEn 0 NuBus Addressing NuBus addressing requires computing the address from the byte addresses given above under VME bus Addressing The formula is NuBus byte address VMEbus byte address 2 1 All byte data is still transferred on data lines D 7 D 0 Word addresses on the NuBus are the same as for VME Word data is transferred on data lines D15
21. uggedness This circuit uses a 33 Ohm resistor in series and an AVX TransGuard ESD filter with the equivalent of a 1100 pF capacitor to ground on each I O line Standard ESD handling precautions should still be used as the IP Logic Interface lines are unprotected Additionally external voltage should not be applied when the IP is unpowered This will damage the Xilinx FPGA Turning on and off all power supplies at the same time will eliminate this problem Outputs use active low tri state buffers which are controlled by the individual output lines In this manner they implement an open drain connection being enabled when the output is low and disabled when the output is high Three surface mount 10 K Ohm resistor networks pull up the I O lines to 5V when the outputs are disabled Data Output Each output has two latches associated with it If double buffering is enabled the D ouble Buffer Latch is clocked by the Double Buffer Clock Without double buffering this latch is clocked by the IP Clock Figure 6 shows a block diagram Outputs from the Double Buffer Latch directly drive the I O output lines Data is latched into the internal latch on the rising edge of the IP Clock after the IO Sel line is driven low Double buffering is enabled by setting the D ouble Buffer Enable Bit bit 0 in the Control Register toa 1 A TTL compatible signal must be provided on the External Clock pin 49 This signal must have an edge rate faster than 60 ns
22. write Output lines 1 8 base 0x3 write Output lines 17 24 base 0x0 read Read Back lines 9 16 base Ox1 read Read Back lines 1 8 base 0x3 read Read Back lines 17 24 base 0x4 read Direct Read lines 9 16 base 0x5 read Direct Read lines 1 8 base 0x6 read Direct Read lines 17 24 base D read write Control Register base 0x40 write Output lines 33 40 base 0x41 write Output lines 25 32 base 0x43 write Output lines 41 48 base 0x40 read Read Back lines 33 40 base 0x41 read Read Back lines 25 32 base 0x43 read Read Back lines 41 48 base 0x44 read Direct Read lines 33 40 base 0x45 read Direct Read lines 25 32 base 0x47 read Direct Read lines 41 48 Figure 3 Byte Access VME Address Map Bit map of bytes at base 0 and base 4 DataBit 7 6 5 4 3 2 1 0 I O Line 16 15 14 13 12 11 10 9 Bit map of bytes at base 1 and base 5 DataBit 7 6 5 4 3 2 1 0 YO Line 8 7 6 5 4 3 2 1 Bit map of bytes at base 3 and base 7 DataBit 7 6 5 4 3 2 1 0 1 0 Line Bit map of bytes at base 40 and base 44 DataBt 7 6 5 4 3 2 1 0 1 0 Line Bit map of bytes at base 41 and base 45 Data Bit 7 6 5 4 3 21 1 0 Bit map of bytes at base 43 and base 47 DataBit 7 6 5 4 3 2 1 0 1 0 Line Bit map of byte a
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IP Unidig E 48