EVBUM2275 - KAI-2001 / KAI-2020 / KAI
Contents
1. EVBUM2275 D Photon Transfer x Slope el Adu 9 19 electrons Noise floor 2 47 counts 22 7 electrons LVSAT 32027 electrons gt lt VSAT 35758 electrons 100 2 c 3 o Oo a z 10 o 2 O XX z 4 1 10 100 1000 10000 100000 Signal Mean Electrons Figure 2 KAl 2020 Measured Performance Dynamic Range and Noise Floor CONNECTOR ASSIGNMENTS AND PINOUTS SMB Connectors J1 J2 and J3 The emitter follower buffered VOUT_LEFT and VOUT_RIGHT signals are driven from the Imager Board via the SMB connectors J3 and J2 respectively VOUT_LEFT is the primary output from the CCD VOUT_RIGHT is only used when the CCD is clocked in dual channel mode Coaxial cable with a characteristic Table 6 J4 INTERFACE CONNECTOR PIN ASSIGNMENTS impedance of 75 Q should be used to connect the imager board to the Timing Generator Board to match the series and terminating resistors used on these boards J1 is an auxiliary SMB connector driven from a relay The relay switches between the VOUT_LEFT and VOUT_RIGHT signals allowing one video connection to transmit either output 9 IMAGER_IN10 10 IMAGER_IN10 11 AGND 12 AGND 13 IMAGER_IN9 14 IMAGER_IN9 15 AGND 16 AGND 17 IMAGER _IN8 18 IMA2. The V1 clock driver is a 2 level driver circuit switching between VMID and VLOW voltage levels CCD FDG Driver The Fast Dump clock drivers consist of a transistor that will switch the voltage on the FD pin of the CCD from FDG_LOW to FDG_HIGH during Fast Dump Gate operations When not in operation or when the Fast Dump Gate feature is not being utilized the FDG pin of the CCD is held at FDG_LOW The FDG_HIGH and FDG_LOW voltage levels of the FDG driver are set by potentiometers buffered by operational amplifiers configured as voltage followers The KAI 2093 image sensor does not have the Fast Dump Gate feature To support this device the Imager Board must be configured so that the CCD pin 11 is 0 0 V To accomplish this R91 is removed and R79 is installed VSUB VES Circuit The quiescent CCD substrate voltage VSUB is set by a potentiometer and resistor divider network The VSUB voltage is buffered by an operational amplifier configured with a gain of 1 40 to allow the voltage to be adjusted to nearly 14 0 V A blocking diode prevents the VSUB bias circuitry from being damaged by the higher voltage electronic shutter pulse For electronic shutter operation the VES signal drives a transistor amplifier circuit that AC couples the voltage difference between the VPLUS and VMINUS supplies onto the Substrate voltage This creates the necessary potential to clear all charge from the photodiodes thereby acting as an electronic shutte
3. components differently on the board Some circuitry on the Imager Board e g remote DAC control of bias and clock level voltages is intended for ON Semiconductor test purposes only and may not be populated INPUT REQUIREMENTS Table 1 POWER REQUIREMENTS Power Supplies Table 2 SIGNAL LEVEL REQUIREMENTS AA AA 2 r 18 20 Input Signals LVDS Vmin Vihreshold Vmax Units Signal Comments IMAGER_INO 0 0 1 2 4 V AMP_ENABLE Output Amplifier Enable IMAGER_IN1 0 0 1 2 4 V H1A H1A clock IMAGER_IN2 0 0 1 2 V H1B H1B clock V V 4 a 0 2 4 Semiconductor Components Industries LLC 2014 October 2014 Rev 2 Publication Order Number EVBUM2275 D EVBUM2275 D Table 2 SIGNAL LEVEL REQUIREMENTS FDG VES Fast Dump clock Electronic Shutter clock 0 2 4 0 2 4 0 2 4 0 2 4 ARCHITECTURE OVERVIEW The following sections describe the functional blocks of the Imager Board Refer to Figure 1 Power Filtering and Regulation Power is supplied to the Imager Board via the J4 interface connector The power supplies are de coupled and filtered with ferrite beads and capacitors to suppress noise Voltage regulators are used to create the 15 V and 15 V supplies from the VPLUS and VMINUS supplies LVDS Receivers TTL Buffers LVDS timing signals are input to the Imager Board via the J4 interface connector These signals are shifted to TTL levels before be
4. EVBUM2275 D KAI 2001 KAI 2020 KAI 2093 Imager Board User s Manual Description The KAI 2001 KAI 2020 KAI 2093 Imager Evaluation Board referred to in this document as the Imager Board is designed to be used as part of a two board set used in conjunction with a Timing Generator Board ON Semiconductor offers an Imager Board Timing Generator Board package that has been designed and configured to operate with the KAI 2001 KAI 2020 and KAI 2093 Image Sensors The Timing Generator Board generates the timing signals necessary to operate the CCD and provides the power required by the Imager Board The timing signals in LVDS format and the power are provided to the Imager Board via the interface connector J4 In addition the Timing Generator Board performs the processing and digitization of the analog video output of the Imager Board The Imager Board has been designed to operate KAI 2001 KAI 2020 and KAI 2093 with the specified performance at nominal operating conditions See the appropriate performance specifications for details ON Semiconductor www onsemi com EVAL BOARD USER S MANUAL For testing and characterization purposes the Imager Board provides the ability to adjust many of the CCD bias voltages and CCD clock level voltages by adjusting potentiometers on the board The Imager Board provides the means to modify other device operating parameters e g CCD reset clock pulse width by populating
5. GER _IN8 http onsemi com EVBUM2275 D Table 6 J4 INTERFACE CONNECTOR PIN ASSIGNMENTS a a Ra INICIOS ION ECC INCA TC a y INICIO IONES CLIC ICI OC A a e oo CO o o A S http onsemi com 7 EVBUM2275 D Warnings and Advisories Ordering Information ON Semiconductor is not responsible for customer Please address all inquiries and purchase orders to damage to the Imager Board or Imager Board electronics The customer assumes responsibility and care must be taken Truesense Imaging Inc when probing modifying or integrating the 1964 Lake Avenue ON Semiconductor Evaluation Board Kits Rochester New York 14615 Phone 585 784 5500 When programming the Timing Board the Imager Board must be disconnected from the Timing Board before power is applied If the Imager Board is connected to the Timing Board during the reprogramming of the Altera PLD damage to the Imager Board will occur Purchasers of an Evaluation Board Kit may at their discretion make changes to the Timing Generator Board firmware ON Semiconductor can only support firmware developed by and supplied by ON Semiconductor Changes to the firmware are at the risk of the customer E mail info truesenseimaging com ON Semiconductor reserves the right to change any information contained herein without notice All information furnished by ON Semiconductor is believed to be accurate ON Semiconductor and the Y are registered trademarks of Semiconductor Co
6. ccur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 eee a Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2275 D
7. ing sent to the CCD clock drivers CCD Pixel Rate Clock Drivers H1 H2 amp Reset Clocks The pixel rate CCD clock drivers utilize two fast switching transistors that are designed to translate TTL level input clock signals to the voltage levels required by the CCD The high level and low levels of the CCD clocks are set by potentiometers and are buffered by operational amplifiers configured as voltage followers Reset Clock One Shot The pulse width of the RESET_CCD clock may be set by U13 a programmable One Shot The One Shot can be configured to provide a RESET_CCD clock signal with a pulse width from 5 ns to 15 ns If pulse width control functionality is provided by the Timing Board the One Shot may be removed and bypassed by installing R147 CCD VCLK Drivers The vertical clock VCLK drivers consist of MOSFET driver IC s These drivers are designed to translate the TTL level clock signals to the voltage levels required by the CCD The high middle and low voltage levels of the vertical clocks are set by potentiometers buffered by operational amplifiers The VHIGH and VLOW op amps have a gain of 1 25 to allow the magnitude of the voltages to be adjusted to 12 5 V when using DAC control The current sources for these voltage levels are high current up to 600 mA transistors The V2_CCD high level clock voltage is switched from V_MID to V_HIGH once per frame to transfer the charge from the photodiodes to the vertical CCDs
8. iometer as noted The nominal values listed in Table 3 Table 3 DC BIAS VOLTAGES KAI 2001 KAI 2093 Description Symbol KAI 2020 Nominal Nominal Potentiometer Reset Drain RD 7 0 12 0 10 5 14 0 V R25 Output Amplifier VDD 15 0 15 0 V Fixed Supply Alternate Amplifier ALT_VDD 6 0 11 0 V R28 Supply 1 The recommended VSUB voltage is specified for each CCD image sensor and is labeled on the device container as VAB Clock Voltages subject to change The Min and Max voltages in the table The following clock voltage levels are fixed or adjusted indicate the approximate adjustable voltage range on the with a potentiometer as noted The nominal values listed in imager board These values may exceed the specified CCD Table 4 correspond to the device specification nominal operating conditions See the appropriate device settings at the time of this document s publication and are specification for details Table 4 CLOCK VOLTAGES KAI 2001 KAI 2093 Description Symbol Level Min KAI 2020 Nom Nom Max Unit Potentiometer Horizontal CCD Hxx_CCD Low 1 V R146 2 EI Ea High 5 R129 Vertical CCD Vx_CCD Low Clock Vx_CCD Mid a R107 v2_CCD High 83 Ld Reset Clock RESET_CCD 1 v Rie o R ES ad Fast Dump Clock FDG_CCD Low 11 R108 High 2 5 R93 The H1A_CCD H1B_CCD H2A_CCD and H2B_CCD low levels are controlled by the same potentiometer R146 The H1A_CCD H1B_CCD H2A_ CCD and H2B_CCD high leve
9. itry is for ON Semiconductor use only and is not enabled ESD Bias Voltage The RESET and HCLK gates on the KAI 2001 KAI 2020 and KAI 2093 CCDs are protected from ESD damage by internal circuitry The ESD bias voltage is set by a potentiometer buffered by an operational amplifier configured as a voltage follower The ESD bias voltage must be more negative than any of the protected gates during operation and powerup In order to ensure these conditions are met diodes are connected external to the CCD between the protected gates and VESD and between VSUB and VESD It is also recommended that during powerup of the Timing Board and Imager Board the VMINUS supply is applied before or simultaneously with the other power supplies For more information refer to the appropriate CCD Image Sensor Device Performance Specifications http onsemi com 3 EVBUM2275 D OPERATIONAL SETTINGS The Imager board is configured to operate the correspond to the device specification nominal settings at KAI 2001 KAI 2020 KAI 2093 Image Sensor under the the time of this document s publication and are subject to following operating conditions change The Min and Max voltages in the table indicate the approximate adjustable voltage range on the imager board These values may exceed the specified CCD operating conditions See the appropriate device specifications for details DC Bias Voltages The following voltages are fixed or adjusted with a potent
10. ls are controlled by the same potentiometer R129 V1_CCD and V2_CCD low levels are controlled by the same potentiometer R66 V1_CCD and V2_CCD mid levels are controlled by the same potentiometer R107 The KAI 2093 has no Fast Dump Gate CCD pin 11 is 0 0 V To accomplish this R91 is removed and R79 is installed D 66 lt lt lt lt J lt lt lt SORE a http onsemi com 4 EVBUM2275 D Reset Clock Pulse Width The pulse width of RESET_CCD may be set by R160 and R161 accordingly This feature is optional as the configuring P 2 0 the inputs to the programmable RESET pulsewidth may also be controlled from the Timing one shot U13 P 2 0 can be tied high or low to achieve the Board In that case U13 is removed and R147 is installed desired pulse width by populating the resistors R156 R157 to bypass this circuitry Table 5 RESET CLOCK PULSE WIDTH J3 Pe Sa ee ee O ON AA COS J2 SMB l SMB LINE EMITTER EMITTER PINE DRIVER FOLLOWER FOLLOWER DRIVER V V3RD PRCLK RCLK i H DRIVER DANE i 1SHOT optional v2 de J DRIVER FD CKT DC BIASES ESD OG RD ALT_VDD VSS IM VSUB H1A H2A H1B H2B tees yd i T LVDS TO TTL BUFFERS l l l l l l l l l DRIVER 15V REGULATOR LVDS RECEIVERS REGULATOR Le 4 P1 DAC CONNECTOR optional Figure 1 KAI 2001 KAI 2020 KAI 2093 Imager Board Block Diagram http onsemi com 5
11. mponents Industries LLC SCILLC or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may o
12. r to control exposure VDD Bias Voltage The VDDL and VDDR video output amplifier supplies in the CCD are coupled directly to the 15 V regulated supply on the Imager Board The Imager Board contains optional circuitry that allows this voltage to be adjusted through the Alternate VDD bias circuit The Imager Board contains optional Amplifier Enable circuitry to control a switch that switches the VDD voltage from 15 V to ALT_VDD http onsemi com 2 EVBUM2275 D CCD Image Sensor This evaluation board supports the KAI 2020 and KAI 2093 Image Sensors KAI 2001 Emitter Follower The VOUT_LEFT_CCD and VOUT_RIGHT_CCD video output signals are buffered using bipolar junction transistors in the emitter follower configuration These circuits also provide the necessary 5 mA current sink for the CCD output circuits The voltage gain of this stage is approximately 0 96 Line Drivers The buffered VOUT_LEFT_CCD and VOUT_RIGHT_CCD signals are AC coupled and driven from the Imager Board by operational amplifiers in a non inverting configuration The operational amplifiers are configured to have a gain of 1 25 which yields an overall gain of 0 6 when driving the properly terminated 75 Q video coaxial cabling from the SMB connector This is done to prevent overloading the AFE on the Timing Board The video output of either channel may be multiplexed to the VOUT_MUX output The multiplexer is controlled by the VIDEO MUX signal This circu
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