Evaluation Module User Manual
Contents
1. UOISSIWIWOD epeJ euoneula u sejejs pajiun ey Wou JepJo ue jo esneoeg DSP56852EVM User Manual Rev 3 Freescale Semiconductor vi Preface This reference manual describes in detail the hardware on the 56852 Evaluation Module Audience This document is intended for application developers who are creating software for devices using the Freescale 56852 part Organization This manual is organized into two chapters and two appendixes Chapter 1 Introduction provides an overview of the EVM and its features Chapter 2 Technical Summary describes in detail the 56852 hardware Appendix A DSP56852EVM Schematics contains the schematics of the 56852EVM Appendix B DSP56852EVM Bill of Material provides a list of the materials used on the 56852EVM board Suggested Reading More documentation on the 56852 and the 56852EVM kit may be found at URL www freescale com Preface Rev 3 Freescale Semiconductor vii Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Conventions This manual uses the following notational conventions Term or Value Symbol Examples Exceptions Active High Signals No special symbol AO Logic One attached to the signal CLKO name2. 12 0V DC AC to the 56852EVM is through a 2 1mm coax power jack An optional 5 0V DC power supply input is available through a 2 pin terminal block TB1 A 12 0V DC 1 2A power supply is provided with the 56852EVM however less than 500mA is required by the EVM The remaining current is available for user daughter card applications when connected to the daughter card interface The power regulation on the 56852EVM provides 5 0V DC voltage regulation for the codec s analog circuits and to the additonal voltage regulation logic on the EVM The additonal voltage regulation logic provides 1 8V DC voltage regulation for the controller s core and 3 3V DC voltage regulation for the controller s I O memory parallel JTAG interface and supporting logic refer to Figure 2 10 Power applied to the 56852EVM is indicated with a Power On LED referenced as LED7 P2 412 0V DC 5 0V Power Regulator Condition 3 3V Regulator 56852EVM PARTS 1 8V Regulator Figure 2 10 Schematic Diagram of the Power Supply Technical Summary Rev 3 Freescale Semiconductor 2 15 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EV
3. 128Kx16 bit of memory U2 with 1 wait state at 120MHz via CSO 128Kx16 bit of memory U3 with 1 wait state at 120MHz via CS1 CS2 M bit Serial EEPROM Data FLASH U4 4 00MHz crystal oscillator for controller frequency generation Y1 Optional external oscillator frequency input connectors JG3 and JG4 Joint Test Action Group JTAG port interface connector for an external debug Host Target Interface J3 On board Parallel JTAG Host Target Interface with a connector for a PC printer port cable P1 RS 232 interface for easy connection to a host processor U6 and P6 16 bit stereo codec interface U5 JG9 JG10 P3 and P4 Stereo headphone interface U12 and P5 Technical Summary Rev 3 Freescale Semiconductor 2 1 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Codec sample rate selector S4 Peripheral Daughter Card Expansion Connector to allow the user to connect his own SCI ISSI SPI or GPIO compatible peripheral to the controller J2 Memory Daughter Card Expansion Connector to allow the user to connect his own memory or memory device to the controller J1 On board power regulation from an external 12V DC supplied power input P2 e On board power regulatio
4. Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D 1 3 56852EVM Connections An interconnection diagram is shown in Figure 1 3 for connecting the PC and the external 12 0V DC AC power supply or external 5 0V DC lab power supply to the 56852EVM board Parallel Extension Cable 56852EVM PC compatible Computer E j a Connect cable A P2 TB 1D to Parallel Printer port j External 5 0V with 2 1mm 42 0V Lab receptacle P connector Ge Supply Figure 1 3 Connecting the 56852EVM Cables Perform the following steps to connect the 56852EVM cables 1 Connect the parallel extension cable to the Parallel port of the host computer 2 Connect the other end of the parallel extension cable to P1 shown in Figure 1 3 on the 56F801EVM board This provides the connection which allows the host computer to control the board 3 Make sure that the external 12 0V DC 1 2A switching power supply or the external 5 0V DC 1A lab power supply is not plugged into a 120V AC power source 4 Connect the 2 1mm output power plug from the external switching power supply into P2 shown in Figure 1 3 on the 56852EVM board Optionally attach an external 5 0V DC lab power supply via the
5. Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Program and Data Memory 2 2 Program and Data Memory The 56852EVM contains two 128Kx16 bit Fast Static RAM banks SRAM bank 0 is controlled by CSO and SRAM bank 1 is controlled by CS1 and CS2 2 2 1 SRAM Bank 0 SRAM bank 0 which is controlled by CSO uses a 128Kx16 bit Fast Static RAM GSI GS72116 labeled U2 for external memory expansion see the FSRAM schematic diagram in Figure 2 1 CSO can be configured to use this memory bank as 16 bit program memory data memory or both Additionally CSO can be configured to assign this memory s size and starting address to any modulo address space This memory bank will operate with one wait state access while the 56852 is running at 120MHz and can be disabled by removing the jumper at JG2 GS72116 A0 A16 DQO DQ15 OE WE Jumper Pin 1 2 Enable SRAM Jumper Removed Disable SRAM Figure 2 1 Schematic Diagram of the External CSO Memory Interface 2 2 2 SRAM Bank 1 SRAM bank 1 which is controlled by CS1 and CS2 uses a 128Kx16 bit Fast Static RAM GSI GS72116 labelled U3 for external memory expansion see the FSRAM schematic diagram in Figure 2 2 U
6. 1 3 JG5 1 3 JG6 1 3 JG7 1 3 JG8 1 3 JG9 1 3 L LED Preface ix MBGA Preface ix MPIO Preface ix O Operating Mode 2 8 P PCB Preface ix PLL Preface ix Index Rev 3 Freescale Semiconductor Index 1 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D R RAM Preface ix ROM Preface ix RS 232 interface 2 1 2 6 level converter 2 6 schematic diagram 2 6 RS 232 Serial Communications 2 6 S SCI Preface 1x SPI Preface x 2 2 SRAM Preface x external data 2 1 external program 2 1 SSI Preface x stereo 16 bit codec interface 2 1 Stereo headphone interface 2 1 W WS Preface x DSP56852EVM User Manual Rev 3 Index 2 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D C INNWAAZS89SdSC 3dAZS89SdSd 0L0Z Jeqwajdas 0 joud sejejs PAUN ay ul ejes Jo podui Joj BJeosees4 WOY ajqejiene jou eje Anu uino eJeu peyeolpul siequinu ped pue seul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju s8jejs paun ay woy JepJo Ue jo esneo eg C INNWAAZS
7. 2 11 A E AAA 2 13 210 RH 2 14 2 11 Power Upp SEET 2 15 ala SINO cosa dece he i Ua d PRA ea aaa AA 44 2 16 2 12 1 Analog Input Output 2 17 2 122 Digtal IIS AMA 2 17 2 13 Daughter Card MA 2 19 2 13 1 Memory Daughter Card Expansion Connector 2 19 2 13 2 Peripheral Daughter Card Expansion Connector 2 21 NONE 4 0 PPP 2 22 Table of Contents Rev 3 Freescale Semiconductor i Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Appendix A DSP56852EVM Schematics A WNWAFZS899gSA 3JAZS89SdSd 0102 Jequiajdas 0 joud sejejs pajiun ay ul ejes yo pwodui 104 ajeosaes4 WOY 9 qejreAe jou eje nueuno eJeu pejeorpui siequinu jed pue saul jonpoud peBexoed yog Uorsstwwog apei euoneuu lul s le S pajiun ay uo JepJo ue Jo esneoeg Appendix B DSP56852EVM Bill of Material DSP56852EVM User Manual Rev 3 Freescale Semiconductor 1 1 1 2 1 3 2 1 2 2 2 3 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 LIST OF FIGURES Block Diagram of the 508 S2EVM 1 2 56F3801EVM Jumper BEN KONTE a ass qu dined AAA ARA 1 3 Connecting the 56852EVM LADO res 1 4 Schematic Diagram of the External CSO Memor
8. 2 pin terminal block TB1 5 Apply power to the external power supply The green Power On LED LED7 will illuminate when power is correctly applied DSP56852EVM User Manual Rev 3 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D 1 4 Freescale Semiconductor Chapter 2 Technical Summary The 56852EVM is designed as a versatile controller development card for developing real time software and hardware products to support a new generation of applications in digital and wireless messaging digital answering machines feature phones modems and digital cameras The power of the 16 bit 56852 combined with the on board 128K x 16 bit external program data static RAM SRAM 128K x 16 bit external data program SRAM RS 232 interface stereo 16 bit codec interface Daughter Card Expansion interface and parallel JTAG interface makes the 56852EVM ideal for developing and implementing many audio and voice algorithms as well as for learning the architecture and instruction set of the 56852 processor The main features of the 56852EVM with board and schematic reference designators include 56852 16 bit 1 8V 3 3V Digital Signal Processor operating at 120MHz U1 External fast static RAM FSRAM memory configured as
9. Chip Emulation a debug bus and port created by Freescale to enable a designer to create a low cost hardware interface for a professional quality debug environment Evaluation Module a hardware platform which allows a customer to evaluate the silicon and develop his application General Purpose Input and Output port on Freescale s family of controllers does not share pin functionality with any other peripheral on the chip and can only be set as an input output or level sensitive interrupt input Integrated Circuit Improved Synchronous Serial Interface port on Freescale s family of controllers Joint Test Action Group a bus protocol interface used for test and debug Light Emitting Diode MAP Ball Grid Array package Multi Purpose Input and Output port on Freescale s family of controllers shares package pins with other peripherals on the chip and can function as a GPIO Printed Circuit Board Phase Locked Loop Random Access Memory Read Only Memory Serial Communications Interface port on Freescale s family of controllers Preface Rev 3 Freescale Semiconductor ix Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D SPI Serial Peripheral Interface port on Freescale s family of controllers SRAM Stati
10. Operating Mode Selection Operating Mode S5 ON Comment 0 1 2 3 4 8 5 6 Bootstrap from External byte wide memory 1 3 4 8 5 6 Bootstrap from SPI 2 1 2 amp 5 6 Normal Expanded mode 3 5 6 Development Expanded mode 2 7 Debug LEDs Six on board Light Emitting Diodes LEDs are provided to allow real time debugging for user programs These LEDs will allow the programmer to monitor program execution without having to stop the program during debugging refer to Figure 2 6 Table 2 4 describes the control of each LED Table 2 4 LED Control Controlled by User LED Signal LED1 Port A PA2 LED2 Port C PC4 LED3 Port C PC5 LED4 Port C PC3 LED5 Port E PE1 LED6 Port E PEO Setting PA2 PC4 PCS PC3 PEI or PEO to a Logic One value will turn on the associated LED DSP56852EVM User Manual Rev 3 2 8 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D INVERTING BUFFER RED LED i AK GREEN LED AN RED CS YELLOW LED w GREEN LED gt L gt gt gt Figure 2 6 Schematic Diagram of the Debug LED Interface 2 8 Debug Suppo
11. an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D C INNWAAZS89SdSC 3dAZS89SdSd 0L0Z Jequieydes 0 joud sejejs PAUN ay u ejes Jo podui Joj BJeosees4 WOY ajqejiene jou eje Anu uino eJeu peyeolpul siequinu ped pue saul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju s8jejs paun ay woy JepJo Ue jo esne eg c o 2 x D G o a Q a la la la la la lala Q SS Saa EC EE s0 n an O O o O O IO jo o o a o c c o O c O JO O o O IN oO Y O O ell xL NN E o ES ESN G t g la 5 E E E Ww 9 o 2 5 e Y 5 8 a Z lt s u F IE A la gt z lt To He il ull i h L S Ilo 11016 _ a Z 1lElE e ele Ole Z F Z L x IL IX 5 x x o e oO 19 S lo lle 15 19 O E O a a a a a a O S a Q N ei elle n o lo o o IE 9 a 2 2 G DSP56852EVM User Manual Rev 3 Freescale Semiconductor 2 12 2 9 External Interrupts Two on board push button switches are provided for external interrupt generation as shown in Figure 2 8 S1 allows the user to generate a hardware interrupt for signal line IRQA S2 allows the user to generate a hardware interrupt for signa
12. 2 O Asenuep Aepsiny leq g vi eu NSQWAZZSE9ASO wl 78 s031 ONG Pue 108889014 2G89GdS ML 0LGZ Lp 08h Xv4 060S Lp 08h 782G8 euozuy edwaj peoy 101113 1583 0012 UOISIAIG S ONPOld psepuels dSa 0213AcS89SdSQ EN 13838 gg 13938 L e Yssa 30 30 SI SWL z z regen VOGA 1881 1SYL avroovrzon ME MOL 391 ou dat NERO oal y 001 101 b ET Odd lt axu gt So 218 gan ISSA YM E EM avin SSSA Y HS 4 YSSA ESSA Dud Ho 289 QVr00VrLOW ZSSA Waff py 1891 oz GHT MOTTA ISSA 0vd 0 9 75 089 La FN y TT mL 900A 9300W S10 sy y sa M san Saga 8300 10 y Ya avin YODA v300W 1 ha S cia eaaa zia LS zia z00 HO ho 110 avroovoLON ner 1QQA ora 53 010 oz qal quu 60 HS 60 80 HS 0 t y s ss id y a Sun van 0 RIO avin EISSA sa HS sa ZISSA ra HS va e LOSSA 0 HS ea QVP0OVPZON 20 gg F ou ann NERAD 10 H ta 9004 90 730 t y y s 1SOM Z900A HH 031 ram 1900 100319 02V xg hv orn s9 61Y gg 6 iv 1011 81 so 399v 0011 21 w LS LM CEO ZEN 91v Kasi oz ANT E A LION sty SH siv SY 03d 0XH riy HS viv t 7 7 33 osi axe sty Lae v elu 2031 ziy He tv arin ISON q Sod S4US ISOW Hy RS iv osin 9d MOUS OSIN oiy Ly tv SS p 9d S418 8S sv HS EN QVt00VPON X98 Ly 20d ND1S NOS 8V ko ev 0 2 GI AR axus LOd 0X8S Y HS LY 09d QXLS IV
13. 50 GND 51 5 0V 2 14 Test Points The 56852EVM board has a total of seven test points Three digital GND test points are located in corners of the board The 5 0VA and AGND test points are located in the analog corner of the board The 1 8V and 3 3V test points are located in the power supply section of the board DSP56852EVM User Manual Rev 3 2 22 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D C INNWAAZS89SdSC 3dAZS89SdSd 0L0Z Jequieydes 0 joud sejejs PAUN ay u ejes Jo podui Joj BJeosees4 WOY ajqejiene jou eje Anu uino eJeu peyeolpul siequinu ped pue saul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju s8jejs paun ay woy JepJo Ue jo esne eg DSP56852EVM Schematics Appendix A DSP56852EVM Schematics Rev 3 Appendix A 1 Freescale Semiconductor C NNWAAZS89SdSC 3dAZS89SdSd 0102 Jeqwajdas 0 joud sejejs Dour ay ur ejes JO WOU Joj aje9seai4 WOY ajqejiene jou eje Anu uino eley peyeoipur siequinu ped pue saul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju s8jejs paun ey woy JepJo ue jo aesnesag sq31 Bnqegq pue 10sse ougd 268985 L y nBij 3 a 9 8 v DL JO jeous ubiseq ddSd jeuBiseg 200
14. 8 U16 Dallas Semiconductor DS1818 Resistors 1 243 Q 1 R1 SMEC RC73L2430HMFT 1 107 Q 1 R2 SMEC RC73L1070HMFT 12 2700 R3 R8 R72 R77 SMEC RC73L2A2700HMJT 2 510 R10 R11 SMEC RC73L2A510HMJT DSP56852EVM Bill of Material Rev 3 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Freescale Semiconductor Appendix B 1 Qty Description Ref Designators Vendor Part s Resistors Continued 5 5 1KQ R9 R12 R14 R48 SMEC RC73L2A5 1KOHMJT 6 47K Q R15 R17 R18 R78 R83 R84 SMEC RC73L2A47KOHMJT 1 10M Q R16 SMEC RC73L2A10MOHMJT 4 5 62K Q 1 R19 R20 R23 R25 SMEC RC73L2A5 62KOHMFT 23 10K O R21 R22 R24 R26 R29 SMEC RC73L2A10KOHMJT R31 R34 R36 R38 R58 R61 R64 R70 R71 R79 R82 R85 2 39 2K Q 1 R27 R28 SMEC RC73L2A39 2KOHMFT 13 1KQ R32 R33 R50 R57 R62 R63 SMEC RC73L2A1KOHMJT R65 4 20 0K Q 1 R37 R39 R42 R44 SMEC RC73L20 0KOHMFT 3 470K Q R41 R43 R86 SMEC RC73L2A470KOHMJT 0 10K Q R45 SMEC RC73L2A10KOHMJT 2 00 R66 R67 SMEC RC73JP2A 0 00 R68 SMEC RC73JP2A Inductors 4 1 0mH FERRITE BEAD L1 L4 Panasonic EXC ELSA35V LEDs 2 Red LED LED1 LED4 Hewlett Packard HSMS C650 2 Yellow LED L
15. 89SdSC 3dAZS89SdSd 0L0Z Jeqwajdas 0 joud sejejs PAUN ay ul ejes Jo podui Joj BJeosees4 WOY ajqejiene jou eje Anu uino eJeu peyeolpul siequinu ped pue seul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju s8jejs paun ay woy JepJo Ue jo esneo eg C INNWAAZS89SdSC 3dAZS89SdSd 0L0Z Jeqwajdas 0 joud sejejs PAUN ay ul ejes Jo podui Joj BJeosees4 WOY ajqejiene jou eje Anu uino eJeu peyeolpul siequinu ped pue seul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju s8jejs paun ay woy JepJo Ue jo esneo eg How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support a
16. A DSP56852EVM User Manual Rev 3 Freescale Semiconductor 2 20 2 13 2 Peripheral Daughter Card Expansion Connector Daughter Card Connectors The controller s peripheral port signals are connected to the Peripheral Daughter Card Expansion connector J2 Table 2 12 shows the port signal to pin assignments Table 2 12 Peripheral Daughter Card Connector Description J2 Pin Signal Pin Signal 1 CSO PAO 2 CS1 PA1 3 A20 CLKO 4 CS2 PA2 5 A17 TIOO 6 A18 TIO1 7 GND 8 GND 9 GND 10 GND 11 GND 12 GND 13 GND 14 GND 15 SRXD 16 CSO PAO 17 MOSI SRFS 18 CS1 PA1 19 SCK SCLK 20 CS2 PA2 21 GND 22 GND 23 MOSI 24 GND 25 MISO 26 GND 27 GND 28 GND 29 ss 30 GND 31 MISO SRCK 32 GND 33 SS STFS 34 GND 35 RESET 36 GND 37 GND 38 GND 39 STXD 40 GND 41 SCK STCK 42 GND Technical Summary Rev 3 Freescale Semiconductor 2 21 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Table 2 12 Peripheral Daughter Card Connector Description Continued J2 Pin Signal Pin Signal 43 IRQB 44 RXD 45 IRQA 46 TXD 47 3 3V 48 3 3V 49 GND
17. A WNNWAFZS899gSA 3JAZS89SdSd 010Z Jaqwajdes 0 joud sejejs pajiun ayy ul ejes yo Podu 104 ajeosaes4 WOY alqejiene jou eje nueuuno eJeu pejeorpui siequinu jed pue saul jonpoud peBexyoed yog UOISSIWIWOD apes euoneula u s le S pajiun ay Wouj JepJo ue jo esneoeg semiconductor Z freescale 16 bit Digital Signal Controllers gt UI N LO oo LO Q 09 a freescale com Evaluation Module User Manual 56F850 96852 C INNWAAZS89SdSC 3dAZS89SdSd 0L0Z Jeqwajdas 0 joud sejejs PAUN ay ul ejes Jo podui Joj BJeosees4 WOY ajqejiene jou eje Anu uino eJeu peyeolpul siequinu ped pue seul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju s8jejs paun ay woy JepJo Ue jo esneo eg TABLE OF CONTENTS Preface vii Chapter 1 Introduction hl 30852EVM EE rr A 1 1 1 2 56852EVM Configuration IO u IATA 1 2 13 56652BVNM COCO 1a ank k k AAA CERA AEE ORO SEES 1 4 Chapter 2 Technical Summary KN WER ore 2 2 22 Program and Data Memory 2 3 2 2 1 SRAM Dank du 2 3 2 2 2 SRAM o ciaaa tei aske ate ER dolsborde n dA GS Edeka EE 2 3 2 3 SPI Serial BEPROM Data FLASH Memory 2 5 24 R5 232 Serial CorminicatloliBi wa k br a k kk EN riera 2 6 A A DR OR kus ba ce Ed d eee GROW Ee d 2 7 20 Operatie Do TET 2 8 S 045 5 A 2 8 a Deon SUPP Pm 2 9 2 8 1 ITA O C OME AAA 2 10 2 8 2 Parallel JTAG Interface Connector
18. AItowaw ered 3T1G 9TXM8ZT 080 Azowen werborg 3TG 9TXM8ZT Freescale Semiconductor DSP56852EVM User Manual Rev 3 Appendix A 4 G INNWAAZS89SdSC 3JAZS89SdSd 010Z Jequieides oj Joud sajejs payun Y ul ajes Jo podu Joj ajeoseai4 WO e qe re e jou eje Anu uino eley peyeoipur siequinu ped pue saul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju s8jejs paun ey woy JepJo ue jo aesnesag IOWA NOtId33 leues YA INL eas Ids Y Y inBij 0L JO p 1eeus ubisaq ddSd ueuBiseq 2002 O Asenuer Aepsinul ejeq y JequinN ezi NSQ INA32S89SdSGQ iu unood IS AdON3N NOYdA33 WL Blas IdS out OLlSc ELv 08v XV4 060S ELv 08 8Z68 euozuy aedwaj peoy 101113 1583 00 Le UOISIAIG SIINPOIA pJepuels asa dM XOL 694 1SY EI SCH AE ET 9S g8ll08QSr1V oTqQPeUH WoO dHud O AE EI 3 q 8 DSP56852EVM Schematics Rev 3 Appendix A 5 Freescale Semiconductor G INnINA32S89SdSG 3JAZS89SdSd 0102 Jeqwajdas 0 Joud sejejs payun 94 ul ejes Jo podu Joj je9s 14 WOJ ajqejiene jou eje Anu uino eley peyeoipur siequinu ped pue saul jonpoud peBeyxoed yog UOISSILIWOD apei jeuoneuJeju see paun ey woy JepJo ue jo esneo eg 40 99UU0D pue ZEZ SY od IOS s V aunbiy a a 2 a v 2 Ol JO S jeous ubiseq
19. Active Low Signals Noted with an WE In schematic drawings Logic Zero overbar in text and in OE Active Low Signals may be most figures noted by a backslash WE Hexadecimal Values Begin with a sym 0FFO bol 80 Decimal Values No special symbol 10 attached to the 34 number Binary Values Begin with the letter b1010 b attached to the b0011 number Numbers Considered positive 5 Voltage is often shown as unless specifically 10 positive 3 3V noted as a negative value Blue Text Linkable on line refer to Chapter 7 License Bold Reference sources See paths emphasis www freescale com DSP56852EVM User Manual Rev 3 viii Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Definitions Acronyms and Abbreviations Definitions acronyms and abbreviations for terms used in this document are defined below for reference Codec DSP EEPROM EOnCE EVM GPIO IC ISSI JTAG LED MBGA MPIO PCB PLL ROM SCI COder DECoder a part used to convert analog signals to digital coder and digital signals to analog decoder Digital Signal Processor or Digital Signal Processing Electrically Erasable Programmable Read Only Memory Enhanced On
20. ED2 LED5 Hewlett Packard HSMY C650 3 Green LED LED3 LED6 LED7 Hewlett Packard HSMG C650 Diode 1 S2B FM401 D1 Vishay DL4001DICT 1 50V 1A BRIDGE RECT D2 DIODES DF02S DSP56852EVM User Manual Rev 3 Appendix B 2 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Qty Description Ref Designators Vendor Part s Capacitors 1 470uF 16V DC C1 ELMA RV 16V471MH10R 21 O 1uF C2 C4 C6 C20 C30 C32 C34 C36 C38 C40 C42 C44 C46 C48 C50 C51 C53 C54 C56 C58 SMEC MCCE104K2NR T1 6 47uF 16V DC C3 C5 C7 C19 C22 C24 ELMA RV2 16V470M R 2 0 33uF C8 C13 SMEC MCCE334K3NR T1 2 470pF C9 C11 SMEC MCCE471J2NO T1 9 1 0uF 25V DC C10 C12 C21 C23 C25 C29 SMEC MCCE105K3NR T1 2 0 0022uF C14 C15 SMEC MCCE222K2NR T1 3 0 47 uF C16 C18 SMEC MCCE474K3NR T1 12 0 01uF C33 C35 C37 C39 C41 C43 SMEC MCCE103K2NR T1 C45 C47 C49 C52 C55 C57 Jumpers 3 1 x 2 2mm Header JG2 JG7 JG8 SAMTEC TMM 102 02 S S 2 3 x 1 2mm Header JG3 JG4 SAMTEC TMM 103 02 S S 1 4 x 2 2mm Header JG6 SAMTEC TMM 104 02 S D 2 2 x 2 2mm Header JG1 JG5 SAMTEC TMM 102 02
21. FO 1NOA LNOA i 100A I 1NOA NO G v 1004W4 1004W4 La ed DW DAAZI L LAENI AAMOd TYNYAALXA DSP56852EVM User Manual Rev 3 Freescale Semiconductor Appendix A 10 A WNWAFZS9899dSA0 3dJAZS89SdSd 010Z Jeqwajdas 0 1oud sejejs PAUN ay ur ejes JO podui Joj aje9seai4 WOY ajqejiene jou eje Anu uino eley peyeoipur siequinu ped pue saul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju s8jejs paun ey woy JepJo ue jo esne eg sde9 ssed g ot anbi4 Ol JO OF 198ys ubiseq qdsq ueuDiseg 2002 OL Menuer kepsinyj ejed NSQ WAazs89sdsa Jequnw ezis jueunooq i SdVO SSVdAG UL 0LSZ Lp 087 XV4 0606 Lr 08v L v8258 Buozuy adwaj peoy 101113 1587 0013 UOISIAIG SIIMPOIA pJepuels ASA Appendix A 11 LNIOd LSH L DSP56852EVM Schematics Rev 3 7 LNIOd LSAL R LNTOd LSwWL dl AO S Um a m T L Lawd T Sdl tdl t foal dl anto jnio o anro jnio o E 899 459 959 399 F i D T l TT dNa tal VAO S Ag e AE EI AE e INIOd LSHL LNIOd SAL AS I NE et aNnNO0AD aNNOAD OO IVNV VAO S 088VWI j ISO j 8STCVSO ooo M wa j chi J xus I m I ae j HE J ms J m a j P ESO 250 199 059 670 89 Lv ID Svo NE E i AE EI AE EI AE ET AE EI AE ET AE E AE ET AE e AE ET MWEXDIPL SVCtXVW BISISA 000DVvL PODWHL Ll0HdSTLV 9I1ICLSD 9T1ICLSD VGGA IBSN TN j 3n10 0
22. H Memory Atmel AT45DB011B SC is provided on the 56852EVM reference Figure 2 3 This memory connects directly to the SPI Port through a header on the 56852 It can be used to load program code and data into the 56852 s internal or external memory spaces Jumper block JG6 is provided to allow the user to disconnect the on board SPI EEPROM Data FLASH from the SPI port and allow him to connect his own SPI port peripheral Since the SPI port and ISSI port are multiplexed on the 56852 the SPI port jumpers need to be removed to use the ISSI port The header details are shown in Table 2 1 Data FLASH Enable Serial EEPROM 56852 SPI Port Connector Data FLASH MOSI SRFS SDI MISO SRCK SDO SCLK STCK SS STFS PC3 Figure 2 3 SPI EEPROM Memory Block Diagram Table 2 1 SPI Port Connector Description JG6 Pin Signal Pin Signal 1 SS STFS PC3 2 cs 3 MISO SRCK 4 SDO 5 MOSI SRFS 6 SDI 7 SCLK STCK 8 SCK Technical Summary Rev 3 Freescale Semiconductor 2 5 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D 2 4 RS 232 Serial Communications The 56852EVM provides an RS 232 interface by the use of an RS 232 level conve
23. J anyo L anoo A anto le 3nto 0 L anyo En anoo L anyo D DER JE anyo ae 3n10 0 L l bro evo evo yo 079 6 9 8 9 LED OCH seo veo ECO ME ET AE e AB Ir AB Ir AB L AB L Ag et Ag e Ag e Ag et Ag e AE e Oe ete E r EE E ere po cuU9udb s s dae Dae eee ee Bae te bd eee re ee ado d 3 a 5 a Freescale Semiconductor A WNNWAFZS899gSA 3JAZS89SdSd 0102 Jequiajdas 0 joud sejejs pajiun ay ul ejes Jo Podu 104 ejeosesuy WOY 9 qejreAe jou eje nueuno eJeu pejeorpui siequinu jed pue saul jonpoud peBexyoed yog UOISSIWIWOD epeJ euoneula u sejejs pajiun ey Wou JepJo ue jo esneoeg DSP56852EVM User Manual Rev 3 Freescale Semiconductor Appendix A 12 Appendix B DSP56852EVM Bill of Material Qty Description Ref Designators Vendor Part s Integrated Circuits 1 DSP56852 U1 Freescale DSP56852VF120 2 GS72116 U2 U3 GSI GS72116ATP 7 1 AT45DB011 U4 Atmel AT45DB011B SC 1 CS4218 U5 Crystal Semiconductor CS4218 KQ 1 MAX3245 U6 Maxim MAX3245EEAI 1 3 3V Voltage Regulator U7 ON Semiconductor MC33269DT 3 3 1 1 8V Voltage Regulator U8 ON Semiconductor MC33269DT ADJ 1 TALCX244 U9 ON Semiconductor MC74LCX244ADW 1 74AC00 U10 Fairchild 74ACOOSC 1 12 288MHz OSC U11 Epson SG 531P 12 288MC 1 LM4880 U12 National Semiconductor LM4880M 1 5 0V Voltage Regulator U13 ON Semiconductor MC33269DT 5 1 74AC04 U14 ON Semiconductor MC74ACO4AD 1 DS181
24. MUM D 2 12 Stereo Codec A 16 bit audio quality stereo codec Crystal Semiconductor CS4218 is connected to the 56852 s ISSI port to support audio voice and signal analysis applications The codec is clocked with a 12 288MHz oscillator This allows the codec to operate between a sample frequency of 8KHz and 48KHz The sample rate can be manually set by setting the appropriate switch positions on DIP switch S4 The sample rate selections possible using this three position DIP switch are detailed in Table 2 8 The codec supports 3 3V digital levels eliminating the need for voltage level translation circuitry Additionally a set of zero ohm resistors are provided on the EVM to allow a user to disconnect the on board codec from the ISSI port and allow him to connect his own codec to the ISSI port see Figure 2 12 The on board codec has analog signal conditioning logic allowing direct connection to its line level input and line level output signals through two 1 8 stereo jacks reference Figure 2 11 Table 2 8 Codec Sample Rate Selector SW 4 SW 4 SW 4 Position 3 Position 2 Position 3 Sample Rate MF6 MF7 MF8 ON ON ON 48 00KHz ON ON OFF 32 00KHz ON OFF ON 24 00KHz ON OFF OFF 19 20KHz OFF ON ON 16 00KHz OFF ON OFF 12 00KHz OFF OFF ON 9 60KHz OFF OFF OFF 8 00KHz DSP56852EVM User Manual Rev 3 2 16 Freescale Semiconductor Because of an order from the United States Inter
25. Reference Table 2 6 for this jumper s selection options Table 2 6 Parallel JTAG Interface Disable Jumper Selection JG7 Comment No jumpers On board Parallel JTAG Interface Enabled 1 2 Disable on board Parallel JTAG Interface DSP56852EVM User Manual Rev 3 2 10 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Debug Support 2 8 2 Parallel JTAG Interface Connector The Parallel JTAG Interface Connector P1 allows the 56852 to communicate with a Parallel Printer Port on a Windows PC reference Figure 2 7 Using this connector the user can download programs and work with the 56852 s registers Table 2 7 shows the pin out for this connector When using the parallel JTAG interface the jumper at JG7 should be removed as shown in Table 2 6 DB 25 Connector Parallel JTAG Interface TDI IN OUT TDO OUT IN P_TRST OUT TMS OUT TCK OUT P_RESET OUT P_DE OUT Jumper Removed JG7 Enable JTAG I F i Jumper Pin 1 2 Disable JTAG I F Figure 2 7 Block Diagram of the Parallel JTAG Interface Technical Summary Rev 3 Freescale Semiconductor 2 11 Because of
26. S D 1 5 x 2 2mm Header JG9 SAMTEC TMM 105 02 S D 1 3 x 2 2mm Header JG10 SAMTEC TMM 103 02 S D Test Points 4 Black Test Point TP1 TP3 TP6 TP7 Keystone 5001 1 Red Test Point TP2 Keystone 5000 1 White Test Point TP4 Keystone 5002 1 Yellow Test Point TP5 Keystone 5004 Crystals 1 4 00MHz Crystal Y1 CTS ATSO4ASM T DSP56852EVM Bill of Material Rev 3 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Qty Description Ref Designators Vendor Part s Connectors 1 DB25M Connector P1 AMPHENOL 617 C025P AJ121 1 2 1mm coax P2 Switchcraft RAPC 722 Power Connector 3 1 8 Stereo Jack P3 P5 Switchcraft 35RAPC4BHN2 1 DE9S Connector P6 AMPHENOL 617 C009S AJ120 2 51 Pin HD Connector J1 J2 BERG 91930 21151 1 7 x 2 Bergstick J3 SAMTEC TSW 107 07 S D 1 2 Pin Terminal Block TB1 On Shore Technology ED500 2DS Switches 3 SPST Pushbutton S1 S3 Panasonic EVQ PADO5R 2 3 Position DIP SW S4 S5 CTS 209 3LPST Transistors 1 2N2222A Q1 ZETEX FMMT2222ACT Miscellaneous 19 2mm Shunt SH1 SH19 Samtec 2SN BK G 4 Rubber Feet REI RF4 3M SJ5018BLKC DSP56852EVM User Manual Re
27. SA va H T 61 x ve SR SE 84 o a muy el INE oO is ISUI 1804 re S ae Oar ar PE PVE Le d 101 1804 s ol uoi SAL Evi y w X91 140d y ol se HO gp SWI 1804 ki yo es i mA EVE TZ fiz 13538 1804 apo 6n em SH k ld oz IN3d 1809 vu D D 9eoegieQquI OWLE T TTeTed El a 9 E v Appendix A 8 A WNWAFZS9899dSA0 3dJAZS89SdSd 010Z Jeqwajdas 0 1oud sejejs PAUN ay ur ejes JO podui Joj aje9seai4 WOY ajqejiene jou eje Anu uino eley peyeolpul siequinu ped pue saul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju seyejs paun ey Wouj JepJo ue jo esneJeg 10 D9UUOD uoisuedx3 pleg Jajy6neqg gv 9 614 0L 40 8 19ays ubiseq qdsq eubiseg Z002 O Asenuer Aepsinul ejeq V JequinN ezis jueuinooq SHOLO3NNOO NOISNVdX3 QHVO HALHONVG enu NSQ INA3cS89S8dSG OLSZ ELH 087 XvJ 0606 Lr 08v v8258 Buozuy adwaj peoy 101113 1587 0013 UOISIAIG S12NpOug PAEPUEIS dsa ds XO30euuop 2104 Terzeydtzseq 1zoaiubneag 10798UUO0D ejed ssezppy Zaire Appendix A 9 e onst ACEN aNd aNd Ag et axl vOul GNO ZS ESD IK ONG qxu gou vv ev TU IFs 39S NOLS Sv ov taxa a axis Iiv ano Laa N 7 lt 13938 qu 0v 9d ou SS SALS Sia 0S9 sa sad qaN OSIN xous vid q vdd gt SS GNO ZIV 8iv ON eid 9d tid gn OSIW vla sa zaa Ann 1 ISOW Ha va IN old eq tad cSO Gen AIS ATIS Hans oad 1S9 Twa ISON saus 6d za LHd 0S9 ova axus e L
28. WAFZ9899dSA 3JAZS89SdSd 0102 Jeqwajdas 0 joud sejejs payun 94 ul ejes Jo podu Joj je9sS 14 WOJ e qe eAe jou eje Anu uino eley peyeoripur siequinu ped pue saul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju s8jejs paun ey Wouj JepJo ue jo esne eg MiowawW NVYS 289 1809 234g exe a 3 089 p30M WesBolg e y ain614 a a 5 Wi Ok JO Jesus ubisag ddSd ueubiseq 2002 90 18q0190 Aepuns ejeq y A NSG WAdzS89SdSa sta 9zIS AHON3N WWVUS 259 1809 3148 v1va pue 059 GHOM NvHSOHd enu 016z Lp 089 Xv3 060G ELH 08p 78298 euozuy edwaj peoy 101113 1883 0017 UOISIAIG Sionpo4d pJepuels dsa AARS TC EE yol ON ATAVSIA Wwas ATAVNA ALAJ AAMOT NVAS H ISVNH ALAJ NHdd MAS ent TENE Huds e e WTIHVNH NOM WWAS Zan NOIldO CENE d3dNnr 318VN3 0S0 YIdWAP 318VN3 2S9 IS9 m P EN H pe D 11 D 298 L d1V9112 89 998 L d1V9112 89 SSA an v 289 SSA an z SSA 81 z ra SSA 81 c 39 39 z 3M Far 3M um 0993 B lt 089 er GA 30 aan 30 qu zor Agero aan aan 91V 91V 91v 9100 SLY 9100 SLY SIY TEEN Sioa viv 3100 bly viv 20 tr 100 ELV ELY k de ta Hitch ev zv za SE LIV Ha EH Oly old TE 6Y AE tae sa Be ev Ta LY d 9d ST 9v Sq FT SV v va ET vv ev v q OT ev n Ly o ov en EN 7SO TSD
29. a aN9 Y sa 98d UND EIN um UND and 61V 02v ONS vad dNS viv LY UND 81V oii LIY ON SIV ev zaa ZS9 Kana 02V To sa Le 6V tag 180 4 amp pre 0S9 oga LIV H DSP56852EVM Schematics Rev 3 Freescale Semiconductor G INnINA32S89SdSG 3JAZS89SdSd 0102 Jeqwajdas 0 Joud sejejs payun 94 ul ejes Jo podu Joj je9s 14 WOJ e qe eAe jou eje Anu uino eley peyeoipur siequinu ped pue seul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju s8jejs paun ey Wouj JepJo ue jo esne eg saijddns 1amog 6 V ain614 3 I q I 5 8 I V OF 40 6 leous ubiseg qdsa ueuDiseq 2002 0 Menuer Aepsinul ajeg IM D Ce aes vi Ort dOOO HHMOd 69TECON NSQ WAa3cS8d9SdSG JequinN 8ZIS au jueuinooq K eni A SINMdans H3MOd WL E 2031 OlSc ELv 08h XV4 0605 Lp 08v v8258 euozuy edwaj peoy 101113 1583 0012 HJOLWINDHYA E UOISIAIG SIDNPOIH puJepuels dsa py 9 AEE Ans Ag et A6 TI 103 T ZT MOTA AS Z TOF T ETZ MOTA MOTH ASI 203 s T LOI MOTE zl ORO qv38 3119834 z 101 ML dns VA AA UBTUA MOTA T GZ I MOA eu 19 v1 e anro 99 q Se g i qvas 3114434 Sanar Ee VAU S O AA O A0 S 302y lH POV 1OG9ZEEON e 39 avag 3118433 ticle AS I O RARI r 15 za 4 an Loop za DAOL TT T T 302p E 10692E8 OW 9 10692EtON gou 0v38 3118433 zech NEE
30. adsa j uBis q 2002 01 Menuer Aepsinul ajeg y NSQ INA3cS89S8dSG Jequnw 9zIS AY jueuinooq HOLO3NNOO QNV ZEZ SY 1HOd IOS epu t L 01sz Lp 087 XV4 0605 Lp 08v v8298 euozuy edwaj peoy 101113 1583 0012 UOISIAIG SJONPO1d pJepuels dsa TO V NISH e en inn z AY Zeit NIE Yh r AL NI H KR z 4d ISVSIA cec sa PTI Wr gt gt L KA IVIISHZEXYN AY You NIEL 34030403 YOLIOHNNOO Bes z GIYANI A 318VN3 2 2 SH AY Now NIZI cec sa NO039404 NISH 1nosu V Tos NISH 3 Nivy 1noru 5 XT Ned N3 MIER 1noseu Nice Inocuy E Ap ES NILH 1notu ki ana ginocu SLU axa LNOEL NIEL SLO LNOZL NIZL 2 axy axi LNOLL NILL lt axi asa ava ano z9 A 20 9 A 09 10 v 9n v a q 9 8 v Freescale Semiconductor DSP56852EVM User Manual Rev 3 Appendix A 6 dq oH OH Od on od oO oO od o o o o eo oa oa o Appendix A 7 L atone ono d DSP56852EVM Schematics Rev 3 Freescale Semiconductor C INNWAAZS89SdSC 3dAZS89SdSd 0L0Z Jeqwajdas 0 joud sejejs PUN ay ur ejes JO odu Joj eje2seeJ4 WOY ajqejiene jou eje Anu uino eley p
31. anual Rev 3 Freescale Semiconductor iv 1 1 2 1 2 2 2 3 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 LIST OF TABLES S6F801EVM Default Jumper Options 1 3 SPI Port Connector DENIA A 2 5 RS 232 Serial Connector Description win s ees vare ER Ee 2 6 Operating Mode Seleolol EE eg e t a eT Oe HOW CAE REP FON 2 8 LED EOM ace dicio ER pz UE p Roe d D ion dos EEN 2 8 JTAG Connector Description soria te EAR AAA 846 264 2 10 Parallel JTAG Interface Disable Jumper Selection 2 10 Parallel JTAG Interface Connector Description 2 12 Codec Sample Rate SAA ON AAA 2 16 S91 Part Connector L t at kai a ka EE dri Pa 2d ek adr 405 2 18 GPIO Port Connector Description Za da ka aa kai aa kwak kane ERE ERR 2 19 Memory Daughter Card Connector Description 2 19 Peripheral Daughter Card Connector Description 2 21 List of Tables Rev 3 Freescale Semiconductor V Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D A WNNWAFZS899gSA 3JAZS89SdSd 0102 Jequiajdas 0 joud sejejs pajiun ay ul ejes Jo Podu 104 ejeosesuy WOY 9 qejreAe jou eje nueuno eJeu pejeorpui siequinu jed pue saul jonpoud peBexyoed yog
32. c Random Access Memory SSI Synchronous Serial Interface port on Freescale s family of controllers WS Wait State References The following sources were referenced to produce this manual 1 DSP56800E Reference Manual Freescale Semiconductor 2 DSP56852 Digital Signal Processor User s Manual Freescale Semiconductor 3 DSP56852 Digital Signal Processor Technical Data Freescale Semiconductor DSP56852EVM User Manual Rev 3 x Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Chapter 1 Introduction The 56852EVM is used to demonstrate the abilities ofthe 56852 and to provide a hardware tool allowing the development of applications that use the 56852 The 56852EVM is an evaluation module board that includes a 56852 part 16 bit stereo codec external memory and a daughter card expansion interface The daughter card expansion connectors are for signal monitoring and user feature expandability The 56852EVM is designed for the following purposes Allowing new users to become familiar with the features of the 56800E architecture The tools and examples provided with the 56852EVM facilitate evaluation of the feature set and the benefits of the family Serving as a platform for real t
33. ency the 56852 uses its internal PLL to multiply the input frequency by 30 An external oscillator source can be connected to the controller by using the oscillator bypass connectors JG3 and JG4 see Figure 2 5 If the input frequency is above 4MHz then the EXTAL input should be jumpered to ground by adding a jumper between JG4 pins 1 and 2 The input frequency would then be injected on JG3 s pin 2 If the controller needs to be synchronized to the codec s sample frequency then the controller s input frequency should be jumpered using the 12 2280MHz codec frequency If the input frequency is below 4MHz then the input frequency can be injected on JG4 s pin 2 EXTERNAL OSCILLATOR HEADERS JG4 L 4 00Mhz 12 2880MHz Figure 2 5 Schematic Diagram of the Clock Interface Technical Summary Rev 3 Freescale Semiconductor 2 7 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D 2 6 Operating Mode The 56852EVM provides a boot up MODE selection switch S5 This switch is used to select the operating mode of the controller as it exits RESET Refer to the DSP56852 User s Manual for a complete description of the chip s operating modes Table 2 3 shows the two operation modes available on the 56852 Table 2 3
34. eyeoipur siequinu ped pue saul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju s8jejs paun ey woy JepJo ue jo sne5 g J0j28uuo2 IVLF pue e ejioju 396 18 ISOH DVLF 9 Ie1ed V ounbBiy Freescale Semiconductor DSP56852EVM User Manual Rev 3 3 a 9 El v vi DL JO jeous ubiseq ddSd jeuBiseg 2002 O Asenuep Aepsinyj leq g JequnN ezi ae ney NSQ WA3eS89SdSQ iueuinood S i HOLIINNO9 9V1f ANY 39Y4431NI LADYVL LSOH 9Y1f 1311VdVd L h Se O162 ELb 085 XV4 0605 EL 08 E 48258 euozuy adwaj 2 peogiou3ise3 0012 O MOS mom s mon UOISIAIQ Sjonpo4d pJepuelS de mo 000v ES TSUI TI XO102UUOD DWLC isu n L gt ai 8 siu oal AUS i Nt vii N AU GE EECH ooowre 10 13539 d SWL it 13538 7 onee 80d HS TSUI N EL gt gt 3a EE or 13530 Tj 13530 Tj ars z eld T Ag s yr wwe yy sur Mr rqesra AA L vey Tou socjaz qur 396181 3S0H VW pzeog uo EES O yrs wszaa pan NIL MAYPZXO 1401 zu Ls eer DH a Co qhi 103NNO9 1HOd od ar an9 97 La E EI wyo 18 na HK 99 o r c A OGL 180d T 8 EI o x ke i ES Nees Og PVE M idi 99A 1409 LTE 1 A is eve EAZ i Ho Y su q r y A SAL OUI A diz
35. ho t rar K 289 axis KW sv LoS sv zz iam goul soul a Sv vem sos vost oy PES tv Y ez D ev y Ets wi 1v1X3 WL u tv Wx J wix ov HS ov In 3 a DSP56852EVM User Manual Rev 3 Freescale Semiconductor Appendix A 2 G INnINA32S89SdSG 3JAZS89SdSd 0102 Jeqwajdas 0 Joud sejejs payun 94 ul ejes Jo podu Joj je9s 14 WOJ e qe eAe jou eje Anu uino eley peyeoipur siequinu ped pue saul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju see paun ey Wouj JepJo ue jo sne5 g SONI 8 poN 300g 542012 Josey Z Y onbiy 3 q E Mi 0L jo Z jeeus ubiseq qdSq ueuBiseq 2002 O Menuer Aepsinyj ajeg y NSQ WA3eS89S8dSG Jequinw ezis ney juewnooq SOHI 8 300N 1009 YOOT70D LISFY OWL L 8T8TSA OlSc ELP 087 XV4 0605 Lp 08v v8258 euoziuy adwaj peoy 101119 1583 001c UOISIAIG sl9npoid pJepuels dsa HOLY 818 Sa EE qoeTes YOd T HGOW 3008 z Sta ria E E NE E ELO Z gt T ss NE E T _ anyo zed E woud NOLLAGHSNG LASTA T anyo CS leo L dNa you YOL gou lt lt e o O Gry zs ZIDDA Y YOL NOLLNGHSNd HO WI Ag 148 YOL 6 8 9 Ager lt ZHN88Z ZL 1V1X lt Agee anyo 2 089 o WOL ZHW00 4 voul lt T 2 2 914 L LA d YOL NOLLNEHSNa VOUI qwixa lt B 00 DSP56852EVM Schematics Rev 3 Appendix A 3 Freescale Semiconductor A WN
36. ime software development The tool suite enables the user to develop and simulate routines download the software to on chip or on board RAM run it and debug it using a debugger via the JTAG Enhanced OnCE EOnCE port The breakpoint features of the EOnCE port enable the user to easily specify complex break conditions and to execute user developed software at full speed until the break conditions are satisfied The ability to examine and modify all user accessible registers memory and peripherals through the EOnCE port greatly facilitates the task of the developer Serving as a platform for hardware development The hardware platform enables the user to connect external hardware peripherals The on board peripherals can be disabled providing the user with the ability to reassign any and all of the controller s peripherals The EOnCE port s unobtrusive design means that all memory on the board and on the chip is available to the user 1 1 56852EVM Architecture The 56852EVM facilitates the evaluation of various features present in the 56852 part The 56852EVM can be used to develop real time software and hardware products based on the 56852 The 56852EVM provides the features necessary for a user to write and debug software Introduction Rev 3 Freescale Semiconductor 1 1 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available fro
37. ited States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D 1 2 Freescale Semiconductor 56852EVM Configuration Jumpers DSP56852EVM RE10520B REV SO gt s5 3G10 ss LEDS u7 BE B E ain Figure 1 2 56F801EVM Jumper Reference Table 1 1 56F801EVM Default Jumper Options lan Gomment Cenanta JG1 Enable on board Byte selectable SRAM via CS1 CS2 U3 1 2 3 4 JG2 Enable on board Word selectable SRAM via CS0 U2 1 2 JG3 Use on board XTAL crystal input for oscillator 1 2 JG4 Use on board EXTAL crystal input for oscillator 2 3 JG5 Enable SCI Port to RS 232 transceiver 1 2 3 4 JG6 Enable SPI Port to Serial EEPROM Data FLASH 1 2 3 4 5 6 amp 7 8 JG7 Enable on board Parallel JTAG Host Target Interface NC JG8 Enable RS 232 output NC JG9 Enable SSI Port for CODEC data 1 2 3 4 5 6 7 8 9 10 JG10 Enable GPIO for CODEC control 1 2 3 4 5 6 Introduction Rev 3 Freescale Semiconductor 1 3
38. l Clock pin STCK provides the serial bit rate clock for the ISSI interface It is connected to the CODEC s Serial Port Clock pin SCLK Data is transmitted on the rising edge of SCLK and is received on the falling edge of SCLK The controller s GPIO PORT C Bit 4 pin PC4 is programmed to control the codec s Active Low Reset signal RESET The Serial Transmit Frame Sync pin STFS is programmed to control the codec s Frame Sync signal FSYNC This signal is sampled by SCLK with a rising edge indicating a new frame is about to start The FSYNC frequency is always the system s sample rate It may be an input to the codec or it may be an output from the codec in data mode Technical Summary Rev 3 Freescale Semiconductor 2 17 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D The basic codec digital connections are shown in Figure 2 12 Table 2 9 and Table 2 10 The codec s MODE is set by the three MODE selection resistors R66 R68 In the factory default setting of MODE 4 the codec is set to be the Master of the ISSI bus with its data word set at 32 bits per frame i e 16 bits Left channel and 16 bits Right channel The sample rate is selected on the Sample Rate Selector switch S4 see Table 2 8 for selection optio
39. l line IRQB These two switches allow the user to generate interrupts for his user specific programs Figure 2 8 3 3V 56852 10K S1 5 IRQA 0 1yF lt 3 3V O 10K S2 BE o O e IRQB 0 1uF lt Schematic Diagram of the User Interrupt Interface Technical Summary Rev 3 External Interrupts Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D 2 10 Reset Logic is provided on the 56852 to generate an internal Power On RESET Additional reset logic is provided to support the RESET signals from the JTAG connector the Parallel JTAG Interface and the user RESET push button refer to Figure 2 9 RESET PUSHBUTTON d JTAG_RESET MANUAL RESET L O JTAG_TAP_RESET Figure 2 9 Schematic Diagram of the RESET Interface DSP56852EVM User Manual Rev 3 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Power Supply 2 11 Power Supply The main power input
40. le Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Z freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST Freescale Semiconductor Inc 2005 All rights reserved DSP56827EVMUM Rev 3 07 2005 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Free
41. m Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D demonstrate the functionality of that software and interface with the customer s application specific device s The 56852EVM is flexible enough to allow a user to fully exploit the 56852 s features to optimize the performance of their product as shown in Figure 1 1 SPI Data RESET SPI FLASH LOGIC RESET 1M bit IRQ IRQ Interface MODE RS 232 DSub LOGIC MODE scl Interface 9 Pin CSO Address Program Memory Data amp 128Kx16 bit SRAM Control Peripheral CS1 CS2 Daughter Data Memory Card 128Kx16 bit SRAM Connector Memory Daughter Card Connector Stereo 16 bit Stereo Line In JTAG ISSI Connector JTAG EOnCE Codec Stereo Line Out Amp Headphone Jack Parallel DSub h JTAG Debug SEN Interface GPIO LEDs 1 8V Power Supply Ken XTAL EXTAL 43 8V 1 8V 3 3V amp 8 GND 5 0V Figure 1 1 Block Diagram of the 56852EVM 1 2 56852EVM Configuration Jumpers Ten jumper groups JG1 JG10 shown in Figure 1 2 are used to configure various features on the 56852EVM board Table 1 1 describes the default jumper group settings DSP56852EVM User Manual Rev 3 Because of an order from the Un
42. n from an optional 5V DC supplied power input TB 1 Light Emitting Diode LED power indicator LED7 Six on board real time user debugging LEDs LED 1 6 Boot MODE selector S5 Manual RESET push button S3 Manual interrupt push button for IRQA S1 e Manual interrupt push button for IRQB S2 2 1 56852 The 56852EVM uses a Freescale DSP56852VF120 part designated as U1 on the board and in the schematics This part will operate at a maximum speed of 120MHz A full description of the 56852 including functionality and user information is provided in these documents DSP56852 Technical Data DSP56852 Provides features list and specifications including signal descriptions DC power requirements AC timing requirements and available packaging DSP56852 User s Manual DSP56852UM Provides an overview description of the controller and detailed information about the on chip components including the memory and I O maps peripheral functionality and control status register descriptions for each subsystem DSP56800E Reference Manual DSP56800ERM Provides a detailed description of the core processor including internal status and control registers and a detailed description of the family instruction set Refer to these documents for detailed information about chip functionality and operation They can be found on this URL www freescale com DSP56852EVM User Manual Rev 3 2 2 Freescale Semiconductor
43. national Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Stereo Codec 2 12 1 Analog Input Output The 56852EVM uses jacks for line level stereo input line level stereo output and stereo headphone output A National Semiconductor LM4880 provides the drive required for the use of headphones This device offers a THD which is superior by a factor of two to the CS4218 s on chip headphone drive circuitry The basic Analog codec connections are shown in Figure 2 11 CS4218 RIN1 LOUTL Line Level Line Level Input LIN1 LOUTR Output LM4880 Headphone Output Figure 2 11 Codec Analog Connections 2 12 2 Digital Interface The serial interface of the codec transfers digital audio data and control data into and out of the device The ISSI port which is multiplexed with the SPI port consists of independent transmitter and receiver sections and is used for serial communication with the codec On the controller side the Serial Transmit Data pin STXD is an output when data is being transmitted to the codec The Serial Receive Data pin SRXD is an input when data is being received from the codec These two pins are connected to the codec s Serial Data Input SDIN and Serial Data Output SDOUT pins The controller s Transmit Seria
44. ns Codec control information is sent over a separate serial port using PCS as the Control Chip Select signal CCS PEO as the Control Data Input signal CDIN and PEI as the Control Clock signal CCLK CODEC Enable Logic CS4218 SDIN SDOUT SCLK FSYNC RESET Figure 2 12 CS4218 Stereo Audio Codec Table 2 9 SSI Port Connector Description JG9 Pin Controller Signal Pin Codec Signal 1 STXD 2 SDIN 3 SRXD 4 SDOUT 5 STCK 6 SCLK 7 STFS 8 FSYNC 9 PC4 10 RESET DSP56852EVM User Manual Rev 3 2 18 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Table 2 10 GPIO Port Connector Description JG10 Pin Controller Signal Pin Codec Signal 1 PC5 2 CCS 3 PEO 4 CDIN 5 PE1 6 CCLK 2 13 Daughter Card Connectors The EVM board contains two daughter card expansion connectors One connector J1 contains the controller s external memory bus signals The other connector J2 contains the controller s peripheral port signals 2 13 1 Memory Daughter Card Expansion Connector Daughter Card Connectors The controller s ex
45. rt Debug Support The 56852EVM provides an on board Parallel JTAG Host Target Interface and a JTAG interface connector for external Target Interface support Two interface connectors are provided to support each of these debugging approaches These two connectors are designated the JTAG connector and the Host Parallel Interface Connector Technical Summary Rev 3 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D 2 8 1 JTAG Connector The JTAG connector on the 56852EVM allows the connection of an external Host Target Interface for downloading programs and working with the 56852 s registers This connector is used to communicate with an external Host Target Interface which passes information and data back and forth with a host processor running a debugger program Table 2 5 shows the pin out for this connector Table 2 5 JTAG Connector Description J3 Pin Signal Pin Signal 1 TDI 2 GND 3 TDO 4 GND 5 TCK 6 GND 7 NC 8 KEY 9 RESET 10 TMS 11 3 3V 12 NC 13 DE 14 TRST When this connector is used with an external Host Target Interface the parallel JTAG interface should be disabled by placing a jumper in jumper block JG7
46. rter Maxim MAX3245EEAI designated as U6 Refer to the RS 232 schematic diagram in Figure 2 4 The RS 232 level converter transitions the SCI UART s 3 3V signal levels to RS 232 compatible signal levels and connects to the host s serial port via connector P6 Flow control is not provided but could be implemented using uncommitted GPIO signals The pinout of connector P6 is listed in Table 2 2 The RS 232 level converter transceiver can be disabled by placing a jumper at JG8 Jumper Removed Enable RS 232 Jumper Pin 1 2 Disable RS 232 RS 232 Level Converter Interface T1in R1out T1out FORCEOFF JG8 R1in Figure 2 4 Schematic Diagram of the RS 232 Interface Table 2 2 RS 232 Serial Connector Description P6 Pin Signal Pin Signal 1 Jumper to 6 amp 4 6 Jumper to 1 amp 4 2 TXD 7 Jumper to 8 3 RXD 8 Jumper to 7 4 Jumper to 1 amp 6 9 N C 5 GND DSP56852EVM User Manual Rev 3 2 6 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Clock Source 2 5 Clock Source The 56852EVM uses a 4 00MHz crystal Y 1 connected to its External Crystal Inputs EXTAL and XTAL To achieve its 120MHz maximum operating frequ
47. scale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D
48. sia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freesca
49. sing CS1 and CS2 this memory bank can be configured as byte 8 bit or word 16 bit accessable program memory data memory or both Additionally CS1 and CS2 can be configured to assign this memory s size and starting address to any modulo address space Technical Summary Rev 3 Freescale Semiconductor 2 3 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D This memory bank will operate with one wait state access while the 56852 is running at 120MHz and can be disabled by removing the jumpers at JG1 GS72116 Jumper Pin 1 2 A0 A16 DQO DQ15 OE WE LB HB CE Enable SRAM Low Byte Jumper Pin 3 4 Enable SRAM High Byte Figure 2 2 Schematic Diagram of the External CS1 CS2 Memory Interface DSP56852EVM User Manual Rev 3 2 4 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D SPI Serial EEPROM Data FLASH Memory 2 3 SPI Serial EEPROM Data FLASH Memory A 1M bit 3 3V SPI serial EEPROM Data FLAS
50. ternal memory bus signals are connected to the Memory Daughter Card Expansion connector J1 Table 2 11 shows the port signal to pin assignments Table 2 11 Memory Daughter Card Connector Description J1 Pin Signal Pin Signal 1 A10 2 A11 3 A9 4 CS1 5 A8 6 A15 7 A7 8 A14 9 A20 10 A19 11 WR 12 A13 13 D0 14 A12 15 D1 16 D8 17 D2 18 D9 Technical Summary Rev 3 Freescale Semiconductor 2 19 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D Memory Daughter Card Connector Description Continued Table 2 11 C INNWAAZS89SdSC 3dAZS89SdSd 0L0Z Jeqwajdas 0 joud sejejs PAUN ay ur ejes Jo podui Joj eje seeJ4 WOL ajqejiene jou eje Anu uino eley peyeolpul siequinu ped pue saul jonpoud peBeyxoed yog UOISSILUWOD apei jeuoneuJeju s8jejs paun ay woy JepJo ue jo esne eg 8 lalo N o sco a a lz la a 19 19 n A lt n O O o c O N sx lolo a T le lo s lo o o g S SN S S G A acta S jF s T Q e S lle x le fele le lela o l Z 121383 i 121091010 lt 2 l lt lt I lt lt lt 9 G o lt c gt IN leiwt la leit lt ag Y N S S G G co jo
51. v 3 Appendix B 4 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D C Clock Source 2 7 Codec Preface ix Codec sample rate selector 2 2 Connecting the DSP56852EVM Cables 1 4 Connectors D Memory Daughter Card Expansion 2 19 Daughter Card Connectors 2 19 Daughter Card Expansion interface 2 1 Debugging 2 8 DSP Preface ix DSP56852EVM E 1 M bit Serial EEPROM Data FLASH 2 1 12 0V DC power supply 2 15 128Kx16 bit of data memory U3 2 1 128Kx16 bit of memory U2 2 1 16 bit 1 8V 3 3V Digital Signal Processor 2 1 16 bit stereo codec interface 2 1 4 00MHz crystal oscillator 2 1 external oscillator frequency input 2 1 FSRAM 2 1 ISSI compatible peripheral 2 2 JTAG port interface 2 1 On board power regulation 2 2 Parallel JTAG Host Target Interface 2 1 real time debugging 2 8 RS 232 interface 2 1 SCI compatible peripheral 2 2 test points 2 22 EEPROM Preface ix EOnCE Preface ix EVM Preface ix F FSRAM 2 3 G GPIO Preface ix 2 2 INDEX H Host Parallel Interface Connector 2 9 Host Target Interface 2 9 IC Preface ix ISSI Preface ix J JTAG Preface ix 1 1 2 1 connector 2 10 Jumper Group 1 3 JGI 1 3 JG10 1 3 JG2 1 3 JG3 1 3 JG4
52. y Interface 2 3 Schematic Diagram of the External CS1 CS2 Memory Interface 2 4 SPI EEPROM Memory Block Diagram 2 5 Schematic Diagram of the RS 232 Interface Q Q c 2 6 Schematic Diagram of the Clock Interface 2 7 Schematic Diagram of the Debug LED Interface 2 9 Block Diagram of the Parallel JTAG Interface 2 11 Schematic Diagram of the User Interrupt Interface 2 13 Schematic Diagram of the RESET Interface 2 14 Schematic Diagram of the Power Supply 2 15 Codec Analog Connecti0fiS Ae k kan kaa e idad 2 17 CS4218 Stereo Audio Codec 2 18 List of Figures Rev 3 Freescale Semiconductor iii Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 DSP56852VFE DSP56852EVMUM D A WNNWAFZS899gSA 3JAZS89SdSd 0102 Jequiajdas 0 joud sejejs pajiun ay ul ejes Jo Podu 104 ejeosesuy WOY 9 qejreAe jou eje nueuno eJeu pejeorpui siequinu jed pue saul jonpoud peBexyoed yog UOISSIWIWOD epeJ euoneula u sejejs pajiun ey Wou JepJo ue jo esneoeg DSP56852EVM User M
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