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ABEL-HDL Reference Manual

1. module bjack bjack abl ackJack state machine controller Adder clock Input Mux control Ace Memory lse ShowHit System clock A Score less than 17 and 22 Card is ace Restart game Card present switches CardIn CardOut 0 1 li de li r 0 li istype com istype reg D invert istype reg D invert istype reg D invert istype red D invert 1 0 Tp X uus Lest vector characters Add10 Sub10 02 01 00 1 1 Ly Iy TI Sd 1 d 0 30 E apo T of 05 205410 ae N24 Oo og M ou Ug 05 0 16 Teo Xe 0520602 1 2 5 Tou gb x05 REO 26 qu tor ai apo nO bm ds 27 Loop kE abe 09 28 qo wo ue v3 29 Tou Qe 05 0 1 17 Or ae s AO Qus 07 O lk Ena AddClk ICIKIN Ace Low if Restart Low then Clear AddClk Low Ace Ace if CardIn Low then AddCard else ShowHit Input Mux control Combined Logic Descriptions Figure 4 23 Source File State Machine Controller ABEL HDL Reference Manual 146 State AddCard State Add_10 State Wt State Test 17 State Test 22 State Sub 10 State ShowBust page test vectors edited State ShowStand State Zero ShowBust AddClk CIlkI Ace Ace if is Ace amp Ace AddClk C1kI Ace High goto Wt AddClk Low Ace Ace if CardOut Low AddClk Low Ace Ace if GT16 then ShowH
2. ABEL HDL Module TITLE The title statement can be used to Module source3 give a title or description for the Title Example of a Source File module DECLARATIONS DO CLORO Declarations declare lower level a Te vir PIN ES modules and associate names all none other PIN ISTYPE reg with functional block instances in inl in3 devices pins nodes constants out c atiy nene other macros and sets They also assign attributes with istype Equations out clk clk EQUATIONS all inl amp in2 amp in3 You can use Equations State none link 1n2 amp 1103 Diagrams or Truth Tables to other inl in2 f in3 amp describe your logic design inl in2 in3 Test Vectors TEST VECTORS Lin cik gt Tout Test Vectors are used as Cb Te Ve eed s stimulus for Functional Simulator L 3 c ee de or Timing Simulator End source3 END The end statement ends the module Bold denotes ABEL HDL keywords Figure 1 1 ABEL HDL Module Structure ABEL HDL Reference Manual 44 Basic Structure Logic Description You can use one or more of the following elements to describe your design Equations Truth Tables State Diagrams Fuses XOR Factors Test Vectors Section Test vectors are used for Functional or Timing Simulation A Test Vectors section can consist of the following elements Test Vectors Trace Statement Test Script End Statement A module is closed with the end statement
3. ABEL HDL Reference Manual 28 Basic Syntax The equivalent functionality can be expressed in equations DCSET F A amp B A amp B on set F lA amp B dc set Specifying both the on set and the don t care set conditions enhances optimization A CAUTION With equations Dcset or Istype dc must be specified or the equations are ignored Expressions Expressions are combinations of identifiers and operators that produce one result when evaluated Any logical arithmetic or relational operators may be used in expressions Expressions are evaluated according to the particular operators involved Some operators take precedence over others and their operation is performed first Each operator has been assigned a priority that determines the order of evaluation Priority 1 is the highest priority and priority 4 is the lowest Table 1 7 summarizes the logical arithmetic and relational operators presented in groups according to their priority ABEL HDL Reference Manual 29 Table 1 7 Operator Priority Priority Operator Description 1 negate 1 NOT 2 amp AND 2 lt lt shift left 2 gt gt shift right 2 il multiply 2 unsigned division 2 modulus 3 add 3 subtract 3 OR 3 XOR exclusive OR 3 I XNOR exclusive NOR 4 m equal 4 l not equal 4 lt less than 4 lt less than or equal 4 gt greater than 4 gt greater than or equal
4. Async_reset keyword 198 Asynchronous preset 158 Attribute and polarity control 77 Attributes buffer 224 collapse 224 com 224 dc 225 invert 224 keep 224 neg 225 pos 225 reg d 225 reg g 225 reg jk 226 reg sr 226 reg t 226 Teg 225 retain 226 xor 226 architecture independence 65 collapsing nodes 64 in lower level sources 62 inherited by higher level sources 208 istype 222 B b 22 Base numbers binary octal hexadecimal decimal 22 changing 194 bcd7 abl 130 Bidirectional 3 state buffer example 122 Binary 22 binbcd abl 140 bjack abl 146 Blackjack machine 134 Blocks 19 Buffer 224 and polarity control 77 example 70 Buried nodes declaring 233 C Case keyword 199 Chained if then else 215 Clock enable 159 Clocked memory element istype reg 225 ABEL HDL Reference Manual 262 Index Clocked memory element Istype reg 225 Closing a module 205 Collapse attribute 224 Collapsing combinational nodes istype collapse 224 istype keep 224 Collapsing nodes 64 selective 65 Com attribute 224 Combinational nodes 62 Combinatorial device attribute for 224 Comments 21 comp4a abl 127 Complement operator 31 Constants declarations 169 declared in macros 176 intermediate expressions 170 Counter example 118 counter abl 209 D d 22 D flip flop clocked memory element 225 dot extensions 161 gated clocked memory element 225 unsatisfied transition condition 92 Dangling
5. Node Node Syntax node id node_id NODE node node ISTYPE attributes Purpose The NODE keyword declares signals assigned to buried nodes Use node id An identifier used for reference to a node in a logic design nodes The node number on the real device attributes A string that specifies node attributes for devices with programmable nodes Any number of attributes can be listed separated by commas Attributes are listed in Table 1 9 under Attribute Assignment in Chapter 1 Language Structure n NOTE Using the Node keyword does not restrict a signal to a buried node A signal declared with NODE can be assigned to a device I O pin by a device fitter You can use the range operator to declare sets of nodes The ending semicolon is required after each declaration When lists of node_id and node are used in one node declaration there is a one to one correspondence between the identifiers and numbers The following example declares three nodes A B and C A B C NODE The node attribute string Istype attributes should be used to specify node attributes Since a node declaration is only required in a detailed description use detailed attributes not pin to pin attributes The ISTYPE statement and attributes are discussed under Istype The node declaration B NODE istype reg specifies that node B is a buried flip flop ABEL HDL Referenc
6. Basic Syntax Operations of the same priority are performed from left to right Use parentheses to change the order in which operations are performed The operation in the innermost set of parentheses is performed first The following examples of supported expressions show how the order of operations and the use of parentheses affect the evaluated result ABEL HDL Reference Manual 30 Expression 2 3 2 2 3 2 2 3 2 2 3 4 2 3 4 2 4 2 2 4 2 MA 14 ME Equations Result Basic Syntax Comments operators with same priority spaces are OK fraction is truncated multiply first add first OR first XOR first Equations assign the value of an expression to a signal or set of signals in a logic description The identifier and expression must follow the rules for those elements You can use the complement operator to express negative logic The complement operator precedes the signal name and implies that the expression on the right of the equation is to be complemented before it is assigned to the signal Use of the complement operator on the left side of equations is provided as an option equations for negative logic parts can just as easily be expressed by complementing the expression on the right side of the equation You can use Lattice Semiconductor LSC macros directly ABEL HDL Reference Manual 31 Basic Syntax Equation Blocks Equation blocks let you specify more complex functions and impr
7. Cycle Syntax CYCLE signal_name logic_value integer logic_value integer 1ogic value integer Use logic_value The logic 1fsvalue can be either 0 or 1 This keyword specifies the signal to repeat until the end of simulation The default time unit is nano second Example cycle clk1 0 3 1 5 See Also Test vectors Wait flicker abl ABEL HDL Reference Manual 201 Constant Declarations Constant Declarations See Constant Declarations ABEL HDL Reference Manual 202 Declarations Declarations Syntax DECLARATIONS declarations Purpose The declarations keyword allows you to declare declarations such as sets or other constants in any part of the ABEL HDL source file Use declarations You can use any declarations after the DECLARATIONS keyword The DECLARATIONS keyword is not necessary for declarations immediately following the module and or title statement s Examples An example of declared equations is shown below module castle moat device P16V8C declarations implied A B pin 1 2 Outl pin 15 istype com Equations Outl A amp B Declarations declarations keyword required C D E F pin 3 4 5 6 Out2 pin 16 istype com Templ C amp D Temp2 E amp F Equations Out2 Templ Temp2 end ABEL HDL Reference Manual 203 Device Syntax Purpose Use Device device_id DEVICE real_device The device declarat
8. Equations module unicnt interface d3 d0 clk rst ld ud gt q3 q0 title 4 bit universal counter with parallel load constants Xu A cm Xu iu usus cy inputs d3 d0 pin Data inputs 4 bits wide clk pin Clock input rst pin Asynchronous reset cnten pin Count enable id pin Load counter with input data value ud pin Up Down selector HIGH selects up outputs q3 q0 pin istype reg Counter outputs sets data d3 d0 Data set count q3 q0 Counter set mode equations MODE cnten 1d u d Mode set composed of control pins LOAD MODE X 1 X Various modes are defined by HOLD MODE 0 0 X values applied to control pins UP MODE 0 1 Symbolic name may be defined as DOWN MODE 0 0 a set equated to a value equations when LOAD then count data Load counter with data else when UP then count count 1 Count up else when DOWN then count count 1 Count down else when HOLD then count count Hold count count clk clk Counter clock input count ar rst Counter reset input test_vectors edited end Figure 4 8 Source File 4 bit Universal Counter n NOTE Youcan also see the advantages of set notation in the test vector section which has been edited in this manual but can be seen in the actual ab1 file In the test vectors the input data is ap
9. GA YA RA CLK Clk S3 S0 AP PR S3 S0 CLK Clk Use Complement Array to initialize or restart S3 S0 R COMP amp 1 1 1 1 GreenA YellowA RedA COMP amp On Off Off GreenB YellowB RedB COMP amp Off Off On Figure 2 14 State Machines with Conflicting Logic ABEL HDL Reference Manual 94 state_diagram Count State 0 Late Late n mun n w 0 B WN ER Late State 5 State 8 end if SenA amp SenB then O with COMP 1 if SenA amp SenB then 4 with COMP 1 if SenA SenB then 1 with COMP 1 goto 2 with COMP 1 goto 3 with COMP 1 goto 4 with COMP 1 GreenA Off YellowA On goto 5 with COMP 1 YellowA Off RedA On RedB Off GreenB On goto 8 with COMP 1 YellowB On goto 13 with COMP 1 if SenA amp SenB then 8 with COMP 1 if SenA amp SenB then 12 with COMP 1 if SenA SenB then 9 with COMP 1 goto 10 with COMP 1 goto 11 with COMP 1 goto 12 with COMP 1 GreenB Off YellowB Off RedB On RedA Off GreenA On goto 0 with COMP 1 State Machines Figure 2 14 State Machines with Conflicting Logic Continued If you use the Dcset directive the equation that specifies this transition 83 82 81 80 R ICOMP
10. Istype req OE ELR ACLR COM CLK SET LASET FB PIN Figure 5 1 Pin to pin Dot Extensions in an Inverted Output Architecture ABEL HDL Reference Manual 163 ext Dot Extensions stype req OE SET ASET OOM CLK CLA ACLA Figure 5 2 Pin to pin Dot Extensions in a Non inverted Output Architecture Istype reg_d invert DE SP AP D CLK SR AR Q PIN Figure 5 3 Detailed Dot Extensions for a D type Flip flop Architecture ABEL HDL Reference Manual 164 ext Dot Extensions Istype reg t invert JOE AP AP PRESET CLK SR AR Q PIN Figure 5 4 Detailed Dot Extensions for a T type Flip flop Architecture Istype reg sr invert JOE SP AP PRESET S 5 SH AR Q PIN Figure 5 5 Detailed Dot Extensions for an RS type Flip flop Architecture ABEL HDL Reference Manual 165 ext Dot Extensions Istype reg_jk invert PRESET J Figure 5 6 Detailed Dot Extensions for a JK type Flip flop Architecture lstype reg inen JOE SP CAP PRESET D c LH SR LAR D PIN LH 1 1 Lesi Q Figure 5 7 Detailed Dot extensions for a Latch with active High Latch Enable ABEL HDL Reference Manual 166 ext Dot Extensions Istype reg _Linvert OE SP AP PRESET D LE SA AH LE PIN IE D O 0 D 1 1 X Lest Figure 5 8 Detailed Dot Extensions for a Latch with Active L
11. count FB 1 amp reset does not result in the preservation of top level XOR operators since the amp operator is the top level operator Using XORs for Flip flop Emulation Another way to use XOR gates is for flip flop emulation If you are using an XOR device that has outputs featuring an XOR gate and D type flip flops you can write your design as if you were going to be implementing it in a device with T type flip flops The XOR gates and D type flip flops emulate the specified T type flip flops When using XORs in this way you should not use the xor attribute for output signals unless the target device has XOR gates JK Flip Flop Emulation You can emulate JK flip flops using a variety of circuitry found in programmable devices When a T type flip flop is available you can emulate JK flip flops by ANDing the Q output of the flip flop with the K input The Q output is then ANDed with the J input ABEL HDL Reference Manual 87 Exclusive OR Equations Figure 2 9 illustrates the circuitry and the Boolean expression Preset Q J amp IQ amp K amp Q Figure 2 9 JK Flip flop Emulation Using T Flip flop You can emulate a JK flip flop with a D flip flop and an XOR gate The circuitry and Boolean expression is shown below in Figure 2 10 Preset Clear D FF 1 5 Q XOR nas d m Q i 3 3 e a 6 Clock Q T Q Figure 2 10 T Flip flop Emulation Using D Flip flop Finall
12. on page 80 or ext Dot Extensions on page 158 for more information Pin to pin vs Detailed Descriptions for Registered Designs You can use ABEL HDL assignment operators when you write high level equations The operator specifies a combinational assignment where the design is written with only the circuit s inputs and outputs in mind The assignment operator specifies a registered assignment where you must consider the internal circuit elements such as output inverters presets and resets related to the memory elements typically flip flops The semantics of these two assignment operators are discussed below Using for Pin to pin Descriptions The implies that a memory element is associated with the output defined by the equation For example the equation Q1 Q1 4 Preset implies that Q1 will hold its current value until the memory element associated with that signal is clocked or unlatched depending on the register type This equation is a pin to pin description of the output signal Q1 The equation describes the signal s behavior in terms of desired output pin values for various input conditions Pin to pin descriptions are useful when describing a circuit that is completely architecture independent Language elements that are useful for pin to pin descriptions are the assignment operator and the CLK OE FB CLR ACLR SET ASET and COM dot extensions described in Chapter 5 Lan
13. 4 k a e k O O c 300 0U O0 0 S 00 o oo koe mh eh 717 Z 19 Alternate directive 174 disabling 197 Carry directive 175 Const directive 176 Dcset directive 177 disabling 192 example 85 overrides dc net and pos 225 precautions 84 with state machines 94 Dcstate directive 178 Directive 173 Exit directive 179 Expr directive 180 lf directive 181 lfb directive 182 lfdef 183 lfiden 184 lfnb 185 lfndef 186 lfniden 187 Include 188 N ABEL HDL Reference Manual 261 Index irp 189 Irpc 190 Message 191 Onset 192 Page 193 Radix 194 Repeat 195 Setsize 196 Standard 197 b 22 d 22 h 22 o 22 Numerics 12 to 4 multiplexer example 114 3 state outputs 62 3 state sequencer example 131 4 bit comparator example 125 4 bit universal counter example 118 7 segment display decoder example 128 A ABEL HDL introduction to 15 structure 43 syntax 15 Active levels for devices 76 Active low declarations 74 actlow1 abl 75 actlow2 abl 74 Addition 25 Alternate flip flop types 72 Ambiguities 67 AND alternate operator for 174 Architecture independence attributes 65 dot extensions 66 dot extensions example 80 resolving ambiguities 67 Arguments defining in module statement 232 Arithmetic operators 25 ASCII supported characters 16 Assignment operators 28 Assignments device 204 multiple to same identifier 32 node 233 pin 235
14. ABEL HDL Reference Manual 7 Flip flop Equations Flip flop Equations Pin to pin equations using the assignment operator are only supported for D flip flops ABEL HDL does not support the assignment operator for T SR or JK flip flops and has no provision for specifying a particular output pin value for these types If you write an equation of the form Ol 1 and the output Q1 has been declared as a T type flip flop the ABEL HDL compiler will give a warning and convert the equation to Ol T 1 Since the T input to a T type flip flop does not directly correspond to the value you observed on the associated output pin this equation will not result in the pin to pin behavior you want To produce specific pin to pin behavior for alternate flip flop types you must consider the behavior of the flip flop you used and write detailed equations that stimulate the inputs of that flip flop A detailed equation to set and hold a T type flip flop is shown below Q1 T QL O ABEL HDL Reference Manual 78 Feedback Considerations Using Dot Extensions Feedback Considerations Using Dot Extensions The source of feedback is normally set by the architecture of the target device If you do not specify a particular feedback path the design may operate differently in different device types Specifying feedback paths with the FB Q or PIN dot extensions eliminates architectural ambiguities Specifying feedback paths als
15. For truth tables Don t Care optimization is almost always the best method For state machines however you may not want undefined transition conditions to result in ABEL HDL Reference Manual 85 Exclusive OR Equations unknown states or you may want to use a default state determined by the type of flip flops used for the state register for state diagram simplification When using don t care optimization be careful not to specify overlapping conditions specifying both the on set and dc set for the same conditions in your truth tables and state diagrams Overlapping conditions result in an error message For state diagrams you can perform additional optimization for design outputs if you specify the Dcstate attribute If you enter Dcstate in the source file all state diagram transition conditions are collected during state diagram processing These transitions are then complemented and applied to the design outputs as don t cares You must use Dcstate in combination with Dcset or the dc attribute Exclusive OR Equations Designs written for exclusive OR XOR devices should contain the xor attribute for architecture independence Optimizing XOR Devices You can use XOR gates directly by writing equations that include XOR operators or you can use implied XOR gates XOR gates can minimize the total number of product terms required for an output or they can emulate alternate flip flop types Using XOR Operators in Equations
16. If you need a specific dot extension across a source boundary to resolve feedback ambiguities for example you must introduce an intermediate signal into the lower level module to provide the connection to the higher level source All dot extension equations for a given output signal must be located in the ABEL HDL module in which the signal is defined No references to that signal s dot extensions can be made outside of the ABEL HDL module Functional block Statement Keyword functional_block Declarations instance name Functional block module name Equations instance name port name signal name Use a FUNCTIONAL BLOCK declaration to instantiate a declared source within a higher level ABEL HDL source You must declare a source with an INTERFACE declaration before instantiating it with FUNCTIONAL BLOCK ABEL HDL Reference Manual 48 Declarations Example of Functional Block Instantiation To declare the two ABEL HDL sources shown in Figure 1 2 would require the following syntax module FUNC modl INTERFACE il gt o1 A FUNCTIONAL BLOCK modl mod2 INTERFACE il gt ol B FUNCTIONAL BLOCK mod2 I pin O pin istype com Equations O B ol B il A ol A il I end Func MODULE MOD 1 MODULE MOD2 gt _ il 01 i1 01 0 Figure 1 2 Functional Block Instantiation The output of an equ
17. If you implement this design in a device with a different architecture the resulting circuit could be quite different But because this is a pin to pin design description the circuit behavior is the same Dot Extensions and Detail Design Descriptions You may need to be more specific about how you implement a circuit in a target device More complex device architectures have many configurable features and you may want to use these features in a particular way You may want a precise powerup and preset operation or in some cases you may need to control internal elements The circuit previously described using architecture independent dot extensions could be described for example using detailed dot extensions in the following ABEL HDL source file Figure 2 6 module detaill Clk pin 1 Toggle pin 2 Ena pin 11 Qout pin 19 istype reg D equations Qout D Qout Q amp Toggle f Qout CLK Clk Qout OE Ena test_vectors C1k Ena Toggle gt Qout ie nous ud gt 0 SO gt Ls ds HOS s gt 0 e O og gt 1e Oe SOS ay gt 0 Nee uM ba gt aZ Op Q gt Ts xcov gt TZ D xh dr gt 0 end Figure 2 6 Detail One bit Synchronous Circuit with Inverted Qout This version of the design will result in exactly the same fuse pattern as indicated in Figure 2 5 As written this design assumes the existence of an inverted output for the signal Qout This
18. If you want to write design equations that include XOR operators you must either specify a device that features XOR gates in your ABEL HDL source file or specify the xor attribute for all output signals that will be implemented with XOR gates This preserves one top level XOR operator for each design output For example module X1 O1 pin istype com xor a b c pin equations Ql aSb amp qoq end Also when writing equations for XOR PALs you should use parentheses to group those parts of the equation that go on either side of the XOR This is because the XOR operator and the OR operator have the same priority in ABEL HDL ABEL HDL Reference Manual 86 Exclusive OR Equations Using Implied XORs in Equations High level operators in equations often result in the generation of XOR operators If you specify the XOR attribute these implied XORs are preserved decreasing the number of product terms required For example module X2 q3 q2 q1 q0 pin istype reg xor clock pin count q3 q0 equations count count Clk clock count FB 1 end This design describes a simple four bit counter Since the addition operator results in XOR operators for the four outputs the xor attribute can reduce the amount of circuitry generated n NOTE The high level operator that generates the XOR operators must be the top level lowest priority operation in the equation An equation such as count
19. State un amp 0 Lave Lave Lave Cate NNnNNN State un amp 0 uv Cate tate_diagram Count 0 if SenA amp SenB then 0 if SenA amp SenB then 4 if SenA 1 goto 2 goto 3 35 goto 4 N 4 GreenA YellowA goto 5 on YellowA RedA RedB GreenB goto 8 6 goto 0 dis goto 0 8 if SenA if SenA if SenA 9s goto 10 10 goto 11 goto 12 T1253 GreenB YellowB goto 13 ES YellowB RedB RedA GreenA goto 0 14 goto 0 L5 Power up RedA YellowA GreenA RedB YellowB GreenB goto 0 E SenB then 1 Off On OFf On Off On amp SenB then 8 amp SenB then 12 SenB then 9 ORE On Off On Off On and preset state Off Off On State Machines Figure 2 15 Dcset compatible State Machine Description Continued ABEL HDL Reference Manual 97 State Machines Number Adjacent States for One bit Change You can reduce the number of product terms produced by a state diagram by carefully choosing state register bit values Your state machine should be described with symbolic names for the states as described above Then if you assign the numeric constants to these names so the state register bits change by only one bit at a time as the state machine goes from state
20. Using Symbolic State Descriptions iscc0 ieee decd cedee rene hx RERO 99 Chapter 3 Designing with CPLDs 2 000 cece eee eee 102 OPLE Desig MSI face ed resinas da ala awe 102 Fe A 102 Using Intermediate Signals erre A a AA 103 Chapter 4 Source File Examples ssuuuuuuu 111 EDEN a odaszes indc danna rep decuseenaneeereapenesendesesmdseeeueen lt 112 Memory Address Decoder 22022284 ieeesun ca rd ii 112 Design Specification uad ded dc beet RARA fe c e o ee 112 od Manod H 113 TESI E E hes A T ET 114 Ta Multiplexer AA a a a E 114 Design Specification sunan aeaee 115 E ECL 116 A doi 4333 0 4 4093 945 CR Oh IDE ORAE Eo di qe de Ux SEC wh i d ed e 117 4 Bit Universal Counter AA T vn 118 Using Sets to Create 05 ITE 118 LOU RESET RN bx d qudd 119 Using Range Operators y oi aani udaa uad OR UR aa ed a 119 Design Description ceased ER annae 119 Bidirectional 3 state BUNT rr AA a Ac 122 COSINA is AAA do e OR C CREAR eed de de n 122 Design MENOJ AA E a A E EE E A A a 123 PO Ome 12a itaqae naea d cedros de ridad da 125 a AA 125 Br AA 125 o A A 127 Tuih Table AM A IN RS ek een eed 128 seven segment Display Deopdet issues kk set cere race 128 Design Specification 2 2 6000 50260002 eeeeeeesaeeee tenes RR mmm red dep 128 BL PETIT mrT 128 TOS VOUS AA 130 ABEL HDL Reference Manual 7 Slat
21. With trans stmt state exp WITH equation equation The WITH statement is used in the STATE DIAGRAM section When used in conjunction with the IF THEN or CASE statement it allows output equations to be written in terms of transitions trans stmt The IF THEN ELSE GOTO or CASE statement state exp The next state equation An equation for state machine outputs You can use the WITH statement in any transition statement in place of a simple state expression The WITH statement is also useful when you are describing output behavior for registered outputs since registered outputs written only for a current state would lag by one clock cycle To specify that a set of registered outputs should contain a specific value after one particular transition specify the equation using a WITH statement similar to the one shown below STATE SO IF reset THEN S9 WITH ErrorFlag 1 ErrorAddress ELSE IF address lt hE100 THEN S2 ELSE S0 oe los address Examples See Also State 5 IF a 1 then 1 WITH x 1 ELSE 2 WITH x 0 State diagram Case Goto If then else ABEL HDL Reference Manual 257 XOR factors Syntax Purpose Use XOR_factors XOR_factors signal name xor factors j Use XOR_FACTORS to specify a Boolean expression to be factored out of and XORed with the sum of products reduced equations Factors can dramatically reduce the reduce
22. for Alternative Flip flop Types In ABEL HDL you can specify a variety of flip flop types using attributes such as istype reg D and reg JK However these attributes do not enforce the use of a specific type of flip flop when a device is selected and they do not affect the meaning of the z assignment operator You can think of the z assignment operator as a memory operator The type of register that most closely matches the assignment operator s behavior is the D type flip flop The primary use for attributes such as istype reg D reg JK and reg SR is to control the generation of logic Specifying one of the reg attributes for example istype reg D instructs the AHDL compiler to generate equations using the D extension regardless of whether the design was written using D or some other method for example state diagrams ABEL HDL Reference Manual 72 Pin to pin vs Detailed Descriptions for Registered Designs NOTE You also need to specify istype invert or buffer when you use detailed syntax Using for flip flop types other than D type is only possible if register synthesis features are available to convert the generated equations into equations appropriate for the alternative flip flop type specified Since the use of register synthesis to convert D type flip flop stimulus into JK or SR type stimulus usually results in inefficient circuitry the use of for these flip flop types is dis
23. gt 2 ge xU sus 30 ce 3 0 31 gt 3o HR TS This truth table could be replaced with the following macro Y clear binary repeat 32 i binary binary 10 binary 10 inc binary The test vectors will demonstrate the use of the macro test vectors score gt bcd2 bcdl clear binary repeat 32 binary gt binary 10 binary 10 inc binary end Figure 4 21 Source File 4 bit Counter with 2 input Mux Continued ABEL HDL Reference Manual 141 Combined Logic Descriptions Design Specification BJACK BJACK the blackjack controller is technically a state machine a circuit capable of storing an internal state reflecting prior events State machines use sequential logic branching to new states and generating outputs on the basis of both the stored states and external inputs In the case of the controller the state machine stores states that reflect the following blackjack machine conditions m The value of Score in one of the decimal value ranges 0 to 16 17 to 21 or 22 m The status of the card reader card in or card out m The presence of an ace in the card reader On the basis of these stored states and input from each new card the controller decides whether or not a 10 or 10 value is sent to the adder Design Method BJACK Developing a bubble diagram is the first step in describing a state machine Figure 4 22 shows a bubble diagram pictorial stat
24. then y a when select 1 then y b when select 2 then y c when select 3 then y c test vectors select a b c gt y 0 1 X X gt 1 select 0 gates lines 0 LIO Hj Ll gt I0 0 p Ow Gd Xp 5 5 T H 3 H gt 3 select 1 gates lines 1 lQ0 Wd 1 L 15 L gt 15 2 L L 8 gt 8 select 2 gates lines 2 po Hy Hp SO gt 9 2 7t Ee hee dp oc 3 3 H H 0 0 select 3 gates lines 3 p duedei 9 2 95 3 7 He 2 o0 end Figure 4 6 Source File 12 to 4 Multiplexer 117 Equations 4 Bit Universal Counter The following design describes the implementation of a 4 bit up down counter with parallel load and count enable The design is described using high level ABEL HDL equations Figure 4 7 shows a block diagram of the counter and its signals Figure 4 8 shows the source file for this design UNICNT Figure 4 7 Block Diagram 4 bit Universal Counter The outputs q3 q2 q1 and q0 contain the current count The least significant bit LSB is q0 the most significant bit MSB is q3 Using Sets to Create Modes The counter has four different modes of operation Load Data From Inputs Count Up Count Down and Hold Count You select the modes by applying various combinations of values to the inputs cnten Id and u d as described below The four modes have different priorities which are defined in the ABEL HDL description The Load mode has the highest priori
25. 02 fb ELSE State2 Using Blocks for State Diagram Transitions Blocks can be used to nest IF THEN and IF THEN ELSE statements in state diagram descriptions simplifying the description of complex transition logic Blocks for Transition Logic Without Blocks F Hold Reset THEN Statel If Hold Error THEN State2 f Hold THEN State3 With Blocks If Hold THEN IF Reset THEN Statel IF Error THEN State2 ELSE State3 Comments Comments are another way to make a source file easy to understand Comments explain what is not readily apparent from the source code itself and do not affect the code Comments cannot be imbedded within keywords You can enter comments two ways m Begin with a double quotation mark and end with either another double quotation mark or the end of line m Begin with a double forward slash and end with the end of the line This is useful for commenting out lines of ABEL source that contain quote delineated comments ABEL HDL Reference Manual 21 Basic Syntax Examples of comments are shown in boldface below gives the module a name MODULE Basic_Logic TITLE ABEL HDL design example simple gates title The information inside single quotation marks apostrophes are required strings not comments and are part of the statement Numbers All numeric operations in ABEL
26. Change Use State Register Outputs to Identify States Use Symbolic State Descriptions Use Identifiers Rather Than Numbers for States A state machine has different states that describe the outputs and transitions of the machine at any given point Typically each state is given a name and the state machine is described in terms of transitions from one state to another In a real device such a state machine is implemented with registers that contain enough bits to assign a unique number to each state The states are actually bit values in the register and these bit values are used along with other signals to determine state transitions As you develop a state diagram you need to label the various states and state transitions If you label the states with identifiers that have been assigned constant values rather than labeling the states directly with numbers you can easily change the state transitions or register values associated with each state When you write a state diagram you should first describe the state machine with names for the states and then assign state register bit values to the state names ABEL HDL Reference Manual 90 State Machines For an example see Figure 2 12 which lists the source file for a state machine named sequence This state machine is also discussed in the design examples Identifiers A B and C specify the states These identifiers are assigned a constant decimal value in the declaration sec
27. Clock Hello Busy brings the text in the block associated with NANDS into the code with Clock substituted for A Hello for B and Busy for C This results in D Clock amp Hello amp Busy which is the three input NAND The macro NAND3 has been specified by a Boolean equation but it could have been specified using another ABEL HDL construct such as the truth table shown here NAND3 MACRO A B C Y TRUTH TABLE A B C gt Y OF poke pee EE D E LUNETTES c E ls SCR Ur i SS ie LL doc 07 In this case the line NAND3 Clock Hello Busy D causes the text TRUTH TABLE Clock Hello Busy gt D Ee Qe opc XR tpe oom ub L Xo Qo dds S MASA veces A L oB A o DES to be substituted into the code This text is a truth table definition of D specified as the function of three inputs Clock Hello and Busy This is the same function as that given by the Boolean equation above The truth table format is discussed under TRUTH_TABLE ABEL HDL Reference Manual 230 Macro Other examples of macros macro with no dummy arguments nodum macro W S1 amp S2 amp S3 onedum MACRO d d macro with 1 dummy argument and when macros are called in logic descriptions nodum X W onedum inp Y W onedum C note the blank actual argument resulting in note leading space from block in nodum W S1 amp S2 am
28. End Statement Other Elements Directives can be placed anywhere you need them m Directives ABEL HDL Reference Manual 45 Header Module Header Keyword module The MODULE statement is required It defines the beginning of the module and must be paired with an END statement The MODULE statement also indicates whether any module arguments are used Interface Keyword interface The INTERFACE statement is used in lower level sources to indicate signals used in upper level files The interface statement is optional Title Keyword title The title is optional The title appears as a header in some output files Declarations The declarations section of a module specifies the names and attributes of signals used in the design defines constants macros and states declares lower level modules and schematics and optionally declares a device Each module must have at least one declarations section and declarations affect only the module in which they are defined There are several types of declaration statements m Constant see Device Hierarchy Library Macro Signal see Pin Node and Istype State State register The syntax and use of each of these types is presented in Chapter 5 Language Reference Some are discussed briefly below ABEL HDL Reference Manual 46 Declarations Declarations Keyword Keyword declarations This keyword allows declarations Such as sets or other constants in any pa
29. Ll Pe og ON pa O cy O O gt A 0 0O 0 SG VINE OT 0 0 gt Je oA O0 0O 0 ay Du ho s O0 B empor ay 0 1 0 o 0 O0 y 0 D Jeep Iu 0 0O ub Ou af Quer xbox O0 Bas Aay 0 0 0 SG Qu 4 j 0 o Reb Bi D ge 1 0 neu y ow Oc mo ub ow Dope cue CMS ug ONG 0 SG vy Duo Gg OQ 5 O gt ped AR s Oe s S y Di sus a lus D y 0 Beeg SOV ew GG 0 Ephes MO Oe t LUE Sous cabo oes Bow c wu D uw o1 Ce y O Q D ue ut de Buys PO lue ey Oi s ug G Grp o Doo we Qu X9 ew o MER end Figure 2 12 Using Identifiers for States Continued Powerup Register States If a state machine has to have a specific starting state you must define the register powerup State in the state diagram description or make sure your design goes to a known state at powerup Otherwise the next state is undefined Unsatisfied Transition Conditions D type Flip flops For each state described in a state diagram you specify the transitions to the next state and the conditions that determine those transitions For devices with D type flip flops if none of the stated conditions are met the state register shown in Figure 2 13 is cleared to all Os on the next clock pulse This action causes the state machine to go to the state that corresponds to the cleared state register This can either cause problems or you can use it to your advantage depending on your design ABEL HDL Reference Manual 92 State Machines
30. MUXADD The test vectors shown in Figure 4 20 verify operation of MUXADD by first clearing the adder so Score is zero then adding card reader values 7 and 10 The test vectors then input an ace 1 from the card reader Card to produce a Score of 1 and pull the is Ace output high Subsequent vectors verify the 10 function of the input multiplexer and adder The trace statement lets you observe the carry signals in simulation ABEL HDL Reference Manual 137 module MuxAdd title AddClk Clr Add10 Sub10 is Ace pin 1 9 8 7 14 V4 VO pin S4 S0 pin C4 C1 pin E gt gos ds Card V4 V0 Score S4 S0 CarryIn C4 Cl 0 CarryOut X C4 C1 ten Oj Ls 0 5 Is minus ten T1305 Shey gos S4 S0O istype reg Input Multiplexer Data Addl10 amp Sub10 amp Card Add10 amp Sub10 amp ten Add10 amp Sub10 amp minus ten QDISP MARG equations Score Data Score FB CarryIn CarryOut Data amp Score FB Data 4 Score FB amp CarryIn Score ar Clr 4 Clr Score clk AddClk is_Ace Card 1 test vectors edited end MuxAdd 5 pit ripple adder with input multiplex Combined Logic Descriptions Figure 4 20 Source File Multiplexer Adder Comparator ABEL HDL Reference Manual 138 Combined Logic Descriptions Design Specification BINBCD To display the Score appearing at the output of MUXADD a binary to bcd conve
31. Table Examples bed led Figure 4 16 Simplified Block Diagram Seven segment Display Decoder The design is described in two sections an equations section and a truth table section The decoding function is described with a truth table that specifies the outputs required for each combination of inputs The truth table header names the inputs and outputs In this example the inputs are contained in the set named bcd and the outputs are in led The body of the truth table defines the input to output function Because the design decodes a number to a seven segment display values for bcd are expressed as decimal numbers and values for led are expressed with the constants ON and OFF that were defined in the declarations section of the source file This makes the truth table easy to read and understand the incoming value is a number and the outputs are on and off signals to the LED The input and output values could have just as easily been described in another form Take for example the line in the truth table 5 gt ON OFF ON ON OFF ON ON This could have been written in the equivalent form 0 1 0 1 36 In this second form 5 was simply expressed as a set containing binary values and the LED set was converted to decimal Remember that ON was defined as 0 and OFF was defined as 1 Either form is supported but the first is more appropriate for this design The first form can be read as the number five turns on the f
32. a registered output Equations state diagrams and truth tables will generate logic for a D type flip flop but you must specify if the output is inverted in the target device with attribute invert or buffer Write equations and truth tables using the D and CE dot extensions when you use this attribute ABEL HDL Reference Manual 225 reg jk reg sr reg t retain xor Examples See Also Istype Attribute Declarations The signal specified is a JK type registered output State diagrams generate logic for this register type but you must specify if the output is inverted in the target device with attribute invert or buffer Write Equations and truth tables using the J and K dot extensions when you use this attribute The signal specified is an SR type registered output State diagrams will generate logic for this register type but you must specify if the output is inverted in the target device with attribute invert or buffer Write equations and truth tables using the s and R dot extensions when you use this attribute The signal specified is a T type registered output State diagrams will generate logic for this register type but you must specify if the output is inverted in the target device with attribute invert or buffer Write equations and truth tables using the T dot extension when you use this attribute Do not minimize this output Preserve redundant product terms for the s
33. argument An actual argument can be any text including identifiers numbers strings operators sets or any other element of ABEL HDL Dummy arguments are specified in macro declarations and in the bodies of macros modules and directives The dummy argument is preceded by a question mark in the places where an actual argument is to be substituted The question mark distinguishes the dummy arguments from other ABEL HDL identifiers occurring in the source file Take for example the following macro declaration arguments see Macro Declarations on page 53 OR_EM MACRO a b c a b c This defines a macro named OR_EM that is the logical OR of three arguments These arguments are represented in the definition of the macro by the dummy arguments a b and c In the body of the macro which is surrounded by braces the dummy arguments are preceded by question marks to indicate that an actual argument is substituted The equation D OR EM x y z amp 1 invokes the OR EM macro with the actual arguments x y and z amp 1 This results in the equation D x t y t z amp 1 Arguments are substituted into the source file before checking syntax and logic so if an actual argument contains unsupported syntax or logic the compiler detects and reports the error only after the substitution ABEL HDL Reference Manual 41 Basic Syntax Spaces in Arguments Actual arguments are substituted exactly as they appear so a
34. argument substituted for A is identical to abcd ABEL HDL Reference Manual 184 lfnb If Not Blank Directive lfnb If Not Blank Directive Syntax IFNB arg block Use arg An actual argument or a dummy argument name preceded by a block A block of text lfnb includes the text contained within the block if the argument is not blank if it contains more than O characters Examples IFNB ABEL HDL source here is not included with the rest of the source file IFNB hello this text is included IFNB A this text is included if a value is substituted for A ABEL HDL Reference Manual 185 lfndef If Not Defined Directive lfndef If Not Defined Directive Syntax IFNDEF id block Use id An identifier block A block of text lfndef includes the text contained within the block if the identifier is undefined Thus if no declaration pin node device macro or constant has been made for the identifier the text in the block is inserted into the source file Examples ifndef A Base hE000 if A is not defined the block is inserted in the text ABEL HDL Reference Manual 186 lfniden If Not Identical Directive lfniden If Not Identical Directive Syntax IFNIDEN argl arg2 block Use arg1 2 Actual arguments or dummy argument names preceded by a block A block of text The text in the block is i
35. clocked memory element 226 dot extensions 161 Tabular truth table 251 Test vectors test_vectors keyword 247 trace keyword 250 Test_vectors keyword 247 Then keyword 214 Times 25 Title keyword 249 Trace keyword 250 traffic abl 94 traffic1 abl 96 Transferring designs 65 Transition conditions 92 Transition statements 241 Transitions case keyword 199 if then else keyword 214 Truth tables 7 segment display decoder example 128 truth_table keyword 251 Truth_table keyword 251 tsbuffer abl 124 U unicnt abl 118 Unlisted pins in hierarchy declarations 221 Unspecified logic values istype dc pos neg 225 W When then else 206 keyword 255 With keyword 257 X x1 abl 86 x2 abl 87 XNOR alternate operator for 174 XOR alternate operator for 174 attribute for 226 XOR_Factors example 259 summary 57 XOR factors keyword 258 xorfact abl 259 XORs and operator priority 87 equations 86 example 86 87 flip flop emulation 87 implied in equations 87 optimization of 86 ABEL HDL Reference Manual 268
36. combine compare or perform operations on the items they include to produce a single result The operations to be performed addition and logical AND are two examples are indicated by operators within the expression You can use the set operator in expressions and equations ABEL HDL operators are divided into four basic types logical arithmetic relational and assignment Each of these types are discussed separately followed by a description of how they are combined into expressions Following the descriptions is a summary of all the operators and the rules governing them and an explanation of how equations use expressions ABEL HDL Reference Manual 24 Basic Syntax Logical Operators Logical operators are used in expressions ABEL HDL incorporates the standard logical operators listed in Table 1 3 Logical operations are performed bit by bit For alternate operators refer to the Alternate Alternate Operator Set on page 174 Table 1 3 Logical Operators Operator Description NOT ones complement amp AND OR XOR exclusive OR I XNOR exclusive NOR Arithmetic Operators Arithmetic operators define arithmetic relationships between items in an expression The shift operators are included in this class because each left shift of one bit is equivalent to multiplication by 2 and a right shift of one bit is the same as division by 2 Table 1 4 lists the arithmetic operators Tab
37. design What appear to be unresolvable equations are written for A and B with both sets appearing as inputs and outputs The enable equations however enable only one set at a time as outputs the other set functions as inputs to the buffer Test vectors are written to test the buffer when either set is selected as the output set and for the case when neither is selected The test vectors are written in terms of the previously declared sets so the element values do not need to be listed separately ABEL HDL Reference Manual 123 module tsbuffer title bidirectional 3 state buffer S1 S0 Pin 1 2 Select S1 S0 A3 A2 A1 A0 Pin 12 13 14 15 A A3 A2 A1 A0 B3 B2 B1 B0 Pin Ley 11 187 4 97 B s B3 B2 B1 B0 X E as equations A B B A A oe Select 1 B oe Select 2 test_vectors Select A B A B 0 y 0 0 Ley Z 9 0 PEESI 5 V Aly X 5 gt Sy X X 0 10 X 2 i 5 X X 5 2 10 X X OT 3 0 01 gt Z 3 15 15 gt Zy Z end Figure 4 11 Source file Bidirectional 3 state Buffer ABEL HDL Reference Manual Equations 124 Equations 4 Bit Comparator This is a design for a 4 bit comparator that provides an output for equal to less than not equal to and greater than as well as intermediate outputs The design is i
38. device declarations and pin number declarations require more comprehensive descriptions than their architecture specific counterparts Assumptions that can be made when a particular device is specified are not possible when no device is specified See the section Device independence vs Architecture independence on page 65 Basic Syntax Each line in an ABEL HDL source file must conform to the following syntax rules and restrictions m Aline can be up to 150 characters long m Lines are ended by a line feed hex OA by a vertical tab hex OB or by a form feed hex 0C Carriage returns in a line are ignored so common end of line sequences such as carriage return line feed are interpreted as line feeds In most cases you can end a line by pressing Return m Keywords identifiers and numbers must be separated by at least one space Exceptions to this rule are lists of identifiers separated by commas expressions where identifiers or numbers are separated by operators or where parentheses provide the separation m Neither spaces nor periods can be imbedded in the middle of keywords numbers operators or identifiers Spaces can appear in strings comments blocks and actual arguments For example if the keyword MODULE is entered as MOD ULE itis interpreted as two identifiers MOD and ULE Similarly if you enter 102 05 instead of 10205 it is interpreted as two numbers 102 and 5 Keywords can be uppercase lowercase or mix
39. dus A HO 3 minus_ten l Oy Xp S4 S83 S2 S1 S0 istype reg Input Multiplexer Data Addl10 amp Subl0 amp Card Add10 Sub10 amp ten Add10 Sub10 amp minus ten equations Score Data Score CarryIn CarryOut Data amp Score Data Score Score ar Clr Score c AddClk is_Ace Card 1 end module binbcd title comparator and binary to bcd decoder for The 5 bit binary 0 31 The interger division Score is converted into two and the modulus operator Hierarchy Examples amp Carryl Blackjack Machine BCD outputs are used to outputs are for the state machine controller extract the individual digits from the two digit score Score 10 will yield the units and Score 10 will yield the tens The GT16 and LT22 4 83 82 81 S80 pin score 84 83 82 81 380 LT22 GT16 pin istype com D5 D4 pin istype com bcd2 D5 D4 D3 D2 D1 D0 pin istype com bedl D3 D2 D1 D0 Digit separation macros binary 0 Scratch variable clear macro a const a 0 inc macro a const a a 1 ABEL HDL Reference Manual 152 Hierarchy Examples equations LT22 score lt 22 Bust GT16 score gt 16 Hit Stand test vectors score gt GT16 LT22 1 OF ud cp 6 gt 0 5 E 8 gt Qr tur AL f 16 gt 0o e ub
40. eC 7 0 gt 1 cerne WO gt Or 100 Tu se 0 gt A A EE LE uw in gt Oj Oh ale end ABEL HDL Reference Manual 74 Using Active low Declarations Design 2 Explicit Pin to Pin Active low module act_lowl q0 al pin istype reg clock pin reset pin equations qd1 q0 clk clock q1 q0 q1l q0 FB 1 amp reset test vectors clock reset gt qi q0 VG unc de d e Or nr fus Qu uu DA wile mE Q eee pes A gt do gens us Our oF 0 gt Tc dyes ve cn SO gt Des SOE ps Og 0 gt A E dein ocu gt Q Os Ts end Design 3 Explicit Detailed Active low module act low3 qo ql pin istype reg d buffer clock pin reset pin equations qd1 q0 clk clock q1 q0 D ql q0 Q 1 amp reset test vectors clock reset gt qi q0 CN Um O mE Ov un Qo s sC 75 00 gt 0r des Sor 0 gt qd ee O ps se 0 gt pod UE a 0 gt Oz 00 los y 0 gt 0 E Era UL gt Oly Ones end Both of these designs describe an up counter with active low outputs The first example inverts the signals explicitly in the equations and in the test vector header while the second example uses an active low declaration to accomplish the same thing ABEL HDL Reference Manual 75 Polarity Control Polarity Control Automatic polarity control is a powerful feature in ABEL HDL where a logic function is con
41. inputs simple outputs Figure 2 16 Symbolic State Description Symbolic state descriptions use the same syntax as non symbolic state descriptions the only difference is the addition of the State register and State declarations and the addition of symbolic synchronous and asynchronous reset statements ABEL HDL Reference Manual 100 State Machines Symbolic Reset Statements In symbolic state descriptions the SYNC_RESET and ASYNC_RESET statements specify synchronous or asynchronous state machine reset logic For example to specify that a state machine must asynchronously reset to state Start when the Reset input is true you write ASYNC_RESET Start Reset Symbolic Test Vectors You can also write test vectors to refer to symbolic state values by entering the symbolic state register name in the test vector header in the output sections and the symbolic state names in the test vectors as output values ABEL HDL Reference Manual 101 Chapter3 Designing with CPLDs ABEL HDL allows you to generate source files with efficient logic for CPLDs including ispLSI devices CPLD Design Strategies The following design strategies are helpful when designing for CPLDs You will find more detailed information in later sections m Define external and internal signals with PIN and NODE statements respectively m Forstate machines and truth tables include Dcset or dc attributes if possible since it usually reduce
42. internal logic design necessary to keep the card count to control the play sequence and to show the count on the digital display or the state on the Hit and Bust LEDs Neither the card reader nor the physical design is discussed here Assume that the card reader provides a binary value that is representative of the card read The design has eight inputs four of which are the binary encoded card values VO V3 The remaining four inputs are signals that indicate the following m Restart the machine is to be restarted Cardin a card is in the reader CardOut no card is in the reader CLK a clock signal to synchronize the design to the card reader Cardln CardOut and CIk are provided by the card reader Restart is provided by a switch on the exterior of the machine Module Function in the Blackjack Machine MUXADD Multiplexer Adder Comparator BINBCD Binary BCD converter BJACK State machine ABEL HDL Reference Manual 135 Combined Logic Descriptions Design Specification MUXADD MUXADD consists of an input multiplexer an adder and a comparator The multiplexer determines what value is added to the current score by the adder The added value consists of the contents of the external card reader VO V1 declared as Card a numeric value of 10 or a numeric value of 10 The inputs Add10 and Sub10 from the controller state machine BJACK determine which of the three values the multiplexer selects for application to the a
43. make a 3 bit counter out of a 4 bit counter in the upper level source you might use the following wiring equations q2 q0 pin upper level signals Equations q2 q0 CNT A q2 q0 See Also Interface top level Hierarchy in ABEL HDL in Chapter 2 Design Considerations ABEL HDL Reference Manual 210 Fuses Syntax Purpose Use Fuses FUSES fuse_number fuse_value or FUSES fuse number set fuse value The FUSES section explicitly declares the state of any fuse in the targeted device fuse number The fuse number obtained from the logic diagram of the device fuse number set The set of fuse numbers contained in square brackets fuse value The number indicating the state of fuse s The FUSES statement provides device specific information and precludes changing devices without editing the statement in the source file Fuse values that appear on the right side of the symbol can be any number If a single fuse number is specified on the left side of the symbol the least significant bit LSB of the fuse value is assigned to the fuse A 0 indicates an intact fuse and a 1 indicates a blown fuse In the case of multiple fuse numbers the fuse value is expanded to a binary number and truncated or given leading zeros to obtain fuse values for each fuse number A CAUTION When fuse states are specified using the fuses section the resulting fuse values supersede the fuse values
44. off key code key pnd key code key str key code key pnd key code key str Figure 3 9 Intermediate Signal Declarations and Equations Continued For large designs using intermediate signals can be essential An expression such as IF input code 1 generates a product term AND gate If the input is 8 bits wide so is the AND gate If the expression above is used 10 times the amount of logic generated will cause long run times during compilation and fitting or may cause fitting to fail If you write the expression as an intermediate equation code 1 found node equations code 1 found input code 1 you can use the intermediate signal many times without creating an excessive amount of circuitry IF code 1 found Another way to create intermediate equations is to use the 2 Carry directive The Carry directive causes comparators and adders to be generated using intermediate equations for carry logic This results in an efficient multilevel implementation ABEL HDL Reference Manual 109 OTHER FUNCTIONAL BLOCK implemented by lower level schematics OTHER FUNCTIONAL BLOCK Implemented by lower level schematics STATE MACHINE Implemented by ABEL STATE MACHINE Implemented OTHER FUNCTIONAL BLOCK Implemented by lower level schematics Figure 3 10 Typical CPLD Design ABEL HDL Reference Manual CPLD Design Strategies V VV U uuu
45. pin 14 15 16 istype com Yl macro B C Y2 B 4 C equations XL A amp Yl x2 A amp Y1 X3 A amp Y2 Note Because Y1 is a text replacement macro the equation for X1 will expand to A amp B C If the desired function was A amp B C use parentheses around the macro or use a subexpression Y1 B C instead of the macro in the declarations A A F 0X The macro could also be written Yl macro B C test vectors LA Bye gt X1 X2 X3 0 0 0 gt 0 0 0 0 0 1 gt f 0 09 0 1 0 gt 0 0 0 0 1 gt l 419 QU y gt 0 0 0 r gt Ly 1 rO gt ror gt end Figure 5 11 Differences Between MACRO and Declared Equations ABEL HDL Reference Manual 229 Macro Examples The dummy arguments used in the MACRO declaration allow different actual arguments to be used each time the macro is referenced Dummy arguments are preceded by a to indicate that an actual argument is substituted for the dummy by the compiler The equation NAND3 MACRO A B C A B C declares a macro named NAND3 with the dummy arguments A B and C The macro defines a three input NAND gate When the macro identifier occurs in the source actual arguments for A B and C are supplied For example the equation D NAND3
46. positions of the set with O being the least significant left most element in the set So Set1 7 4 is Set1 values f8 to f11 ABEL HDL Reference Manual 33 Basic Syntax If you are indexing into a set to access a single element then you can use the following syntax declarations outl pin istype com Setl f15 f0 equations outl Set1 4 1 In this example a comparator operator was used to convert the single element set Set1 4 into a bit value equivalent to f4 See also Setsize Set Indexing Set Operations Most operators can be applied to sets with the operation performed on each element of the set sometimes individually and sometimes according to the rules of Boolean algebra Table 1 8 lists the operators you can use with sets Set Operations on page 34 describes how these operators are applied to sets Two set Operations For operations involving two or more sets the sets must have the same number of elements The expression a b c d e is not supported because the sets have different numbers of elements For example the Boolean equation Chip Sel A15 amp A14 amp A13 represents an address decoder where A15 A14 and A13 are the three high order bits of a 16 bit address The decoder can easily be implemented with set operations First a constant set that holds the address lines is defined so the set can be referenced by name This definition is done in the consta
47. shows the truth table created from the macro The BINBCD design also provides the outputs LT22 and GT16 to control the Bust and Hit LEDs A pair of equations generate an active high LT22 signal to turn off the Bust LED when Score is less than 22 and an active high GT16 signal to turn off the Hit LED when Score is greater than 16 Test Vectors BINBCD The test vectors shown in Figure 4 21 verify operation of the LT22 and GT16 outputs of the converter by assigning various values for Score and checking for the corresponding outputs The test vectors for the binary to bcd converter are defined by means of the following macro test vectors score bcd2 bcd1 clear binary repeat 32 binary binary 10 binary 10 inc binary ABEL HDL Reference Manual 139 Combined Logic Descriptions This macro generates a test vector with the variable binary set to 0 by the macro a const a 0 in the binbcd abl source file shown in Figure 4 21 followed by 31 vectors provided by the repeat directive The 31 vectors are generated by incrementing the value of the variable binary by a factor of 1 for each vector Refer to the inc macro a const a a 1 line in Figure 4 22 On the output side of the test vectors division is used to create the output for bcd2 tens display digit while the remainder modulus operator is used to create the output for bcd1 units display digit module BINBCD title c
48. specified for pins in a lower level module are propagated to the higher level source For example a lower level pin with an invert attribute affects the higher level signal wired to that pin it affects the pin s preset reset preload and power up value Output Enables OE Connecting a lower level tri state output to a higher level pin results in the output enable being specified for the higher level pin If another OE is specified for the higher level pin it is flagged as an error Since most tri state outputs are used as bidirectionals it might be important to keep the lower level OE Buried Nodes Buried nodes in lower level sources are handled as follows Dangling Nodes Lower level nodes that do not fanout are propagated to the higher level module and become dangling nodes Optimization may remove dangling nodes Combinational nodes Combinational nodes in a lower level module become collapsible nodes in the higher level module Registered nodes Registered nodes are preserved with hierarchical names assigned to them Declaring Lower level Modules in the Top level Source To declare a lower level module you match the lower level module s interface statement with an interface declaration For example to declare the lower level module given above you would add the following declaration to your upper level source declarations lower interface a d3 d0 gt z0 z7 You could specify different default valu
49. to state you will reduce the number of product terms required to describe the state transitions As an example take the states A B C and D which go from one state to the other in alphabetical order The simplest choice of bit values for the state register is a numeric sequence but this is not the most efficient method To see why examine the following bit value assignments The preferred bit values cause a one bit change as the machine moves from state B to C whereas the simple bit values cause a change in both bit values for the same transition The preferred bit values produce fewer product terms Simple Preferred State Bit Values Bit Values A 00 00 B 01 01 C 10 11 D 11 10 If one of your state register bits uses too many product terms try reorganizing the bit values so that state register bit changes in value as few times as possible as the state machine moves from state to state Obviously the choice of optimum bit values for specific states can require some tradeoffs you may have to optimize for one bit and in the process increase the value changes for another The object should be to eliminate as many product terms as necessary to fit the design into the device ABEL HDL Reference Manual 98 State Machines Use State Register Outputs to Identify States Sometimes it is necessary to identify specific states of a state machine and signal an output that the machine is in one of these states Fewer equations and outputs a
50. we will provide you with instructions on returning your defective software to us The cost of returning the software to the Lattice Semiconductor Service Center shall be paid by the purchaser Limitations on Warranty Any applicable implied warranties including warranties of merchantability and fitness for a particular purpose are hereby limited to ninety days from the date of purchase and are subject to the conditions set forth herein In no event shall Lattice Semiconductor Corporation be liable for consequential or incidental damages resulting from the breach of any expressed or implied warranties Purchaser s sole remedy for any cause whatsoever regardless of the form of action shall be limited to the price paid to Lattice Semiconductor for the Lattice Semiconductor software The provisions of this limited warranty are valid in the United States only Some states do not allow limitations on how long an implied warranty lasts or exclusion of consequential or incidental damages so the above limitation or exclusion may not apply to you This warranty provides you with specific legal rights You may have other rights which vary from state to state ABEL HDL Reference Manual 3 Table of Contents PIBIIOB i ese A 10 What is in this Manual 4040002e0c ens eee eedbaeeee mrs ee mnes 11 Where to Look for Information uci ede edd d Rb he RR CR Ree E ed t dei e d dee 11 Doc mentalion OIDO caricia ROO COEPI EGER ROCCO DECR KEEPER CR
51. 1 1 results in sigset being assigned the value 0 1 0 The set assignment a b 6 08 d is the same as the two assignments a C amp d b c amp d Numbers in any representation can be assigned or compared to a set The preceding set equation could have been written as sigset 6 amp 3 ABEL HDL Reference Manual 35 Basic Syntax When numbers are used for set assignment or comparison the number is converted to its binary representation and the following rules apply m the number of significant bits in the binary representation of a number is greater than the number of elements in a set the bits are truncated on the left m lIfthe number of significant bits in the binary representation of a number is less than the number of elements in a set the number is padded on the left with leading zeroes Thus the following two assignments are equivalent UJ a b B101011 bits truncated to the left a b B11 And so are these two d c BOT d c Bl compiler will add leading zero Table 1 8 Supported Set Operations Operator Example Description A 5 combinational assignment A 1 0 1 registered assignment IA NOT ones complement amp A amp B AND A B OR A B XOR exclusive OR I A SB XNOR exclusive NOR A negate A B subtraction A B addition B equal l A B not equal lt A lt B less than lt A lt B less than or
52. 1 1 Q1 pin istype reg Clock Preset pin equations QOl clk Clock Q1 Q1 fb 4 Preset test vectors Clock Preset gt Q1 wu F t 1 gt Iz Cs 5 0 gt 0 SOR j gt 1 Cs gr O gt 0 xe y gt 1 Cn gt 1 end ABEL HDL Reference Manual 69 Pin to pin vs Detailed Descriptions for Registered Designs Detailed Module Description module Q1 2 Q1 pin istype Clock Preset pin equations Q1 CLK Clock Q1 D Q1 Q Preset test_vectors reg D buffer end Clock Preset gt Q1 SG Ly E r Mo 0 gt 0 SQ 0 gt 15 o 0 gt 05 Es Eoi C y gt Ny The first description can be targeted into virtually any device if register synthesis and device fitting features are available while the second description can be targeted only to devices featuring D type flip flops and non inverting outputs To implement the second detailed module in a device with inverting outputs the source file would need to be modified in the following manner Detailed Module with Inverted Outputs module Q1 3 Clock 1 0 Preset ol Clock Preset equations Q1 CLK Q1 D n test_vectors Clock end C C C Q pin pin Preset 1 0 0 gt istype reg_D invert Q1 In this version of the module the existence of an inverter between the output of the D type flip flop and th
53. 12 Related Documentation iu i dca oic iG de ee 4e exo bem PO beo SEER EKG Oe RRS ede AAA 13 Chapter 1 Language Structure LLLL uuuuuusss 14 o A EE EI E T IO T T 0 TTL TT OTI 14 ies da e AAA 15 o errara as kh AAW Pek DE UT TTL 15 Supported ASCII Characters nc drm i dnd ede as dade Ri ord dde ox d d ed e 16 A de Sale e cide Se heete bora encase dake ke eesdeti oi casa dage se 16 Reserved Identifiers Keywords llle 18 LIBE MENUS iii Cod oor OR de nC C GR EX OR ao ews 18 A eee aha os T TES eas eR E 19 aie EEEE O EE EEE E E S E A E E E EE E E 19 Using Blocks in Logic Descriptions s saaana aaee 20 Using Blocks for State Diagram Transitions oooooocccrnrconno o 21 Sung AM RPM 21 FII 0 pde E Ae p E AO IRR E ks EE et MCA n ae Ce 22 CNG me TTC rrr 24 Operators Expressions and EquationS ccccncn ohh hh 24 El Doi 2 MDC e de rn 25 Arithmetic Operators 0 0 0 00 nn 25 uc deis E AAA 26 its Le 2 a doi 3d p RR CECI FOU HERE rare are ORO d ed CR 27 o Ma A E A EEEE ET EET 29 A eaa Bad RR Roo b a aa EE E 31 Eguation BIOK o od pect AED bee cede de rd A ra 32 EE A E OE A 33 Set Indexing A 33 SPOP A A ee a bina een aod eels 34 Set Assignment and Comparison 6 060k sok RA OE eee ee 35 cl E a decora eae ae he ee o Robo ef e Pedo eic pd RC ee 37 Example o cuan beseech pd i keL RA dh aA a ad wa MR 38 Set OBa aion RUES A 38 Limitations Restrictio
54. 17 gt 13 18 gt pod Lis 20 gt eM Ju 2 1 gt pol T 22 gt lei le 23 gt li ue lo 24 gt IL CN truth table score gt bcd2 bcd1 0 gt oou o0 Iie 1 Dep il Ta 2 gt Qu Em 3a gt O gt 3 ls 4 gt Qu CTS 5 5 Ol sy 5 6 gt Oy ls 7 Oo xoc MP 8 gt Qc S 9 O y 9 10 Loge Oo 13 LE gt Ls Ts TA gt Us 2 13 Le ve 33x 14 gt T3 4 1 50 gt TJ 3 xs 16 gt gt L 6 I ie JT s 7 18 gt 1 8 19 gt 1 3 o elus 20 gt 2 7 21 gt Dope Q2 de 22 va 2 Qe Vs 23 gt 2 ge aie 24 gt 2 He tss 25 E 2 u 5 qu 26 gt 2 mw 16 271 2 AAN 28 gt 2a x39 29 gt 2 yu 9 Is 30 A gt Sire OFS 31 gt Som EC ABEL HDL Reference Manual 153 Hierarchy Examples This truth table could be replaced with the following macro clear binary L repeat 32 binary gt binary 10 binary 10 inc binary The test vectors will demonstrate the use of the macro test vectors score gt bcd2 bcdl1 clear binary repeat 32 binary gt binary 10 binary 10 inc binary end ABEL HDL Reference Manual 154 ABEL and ispEXPEHT System Projects ABEL and ispEXPERT System Projects The following ABEL HDL source p6top ab1 Figure 4 24 instantiates variable module p6top title OOo QOU co prep ACC co re ACC i equati ACC OS end i
55. 235 Outputs using istype for 222 P Pin assignments 235 istype 222 keyword 235 using the range operator in 235 pin2pin abl 81 Pin to pin descriptions 66 67 example 69 Pin to pin descriptions and flip flops 78 Plus 25 Polarity control 76 77 active levels 76 77 istype 77 Ports declaring lower level 61 63 Pos attribute 225 Post linked optimization 64 Powerup register states 92 Powerup state 92 Preset built in example 71 Priority of operators 29 ABEL HDL Reference Manual 266 Index Product terms reducing 98 reducing with intermediate expressions 170 Programmable polarity active levels for devices 76 Property keyword 237 Q Q11 abl 69 Q12 abl 70 Q13 abl 70 Q15 abl 71 Q17 abl 72 R Range operators example 119 in hierarchy declarations 208 in node declarations 233 in pin declarations 235 using 119 Reduction XOR factors 258 Redundant nodes 63 Redundant product terms retaining 226 Reg attribute 225 Reg d attribute 225 Heg g attribute 225 Heg jk 226 attribute 226 Reg sr attribute 226 Reg t attribute 226 Register load input 159 Registered design descriptions 66 Registered nodes 62 Registers bit values in state machines 99 cleared state in state machines 93 dot extensions 158 161 powerup states 92 Relational operators 26 Repeat irp directive 189 irpc directive 190 Reset example inverted architecture 72 example non inverted architecture 71 resolving ambiguities 71 Retain attribu
56. 49 trace 250 truth_table 251 when then else 255 with 257 XOR_factors 258 L Latch enable 158 Less than 26 Library keyword 227 Linking modules 64 merging feedbacks 64 post linked optimization 64 Logic descriptions 53 Lower level sources 61 instantiating 208 L type latch dot extensions 161 M mac abl 229 Macro keyword 228 keyword example 229 ABEL HDL Reference Manual 265 Index Macros vs declared equations 228 Memory address decoder example 112 Merging feedbacks 64 Minus 25 Module beginning 232 defined 46 ending 205 keyword 232 Modulus 25 Multiplication 25 mux12t4 abl 117 muxadd abl 138 N Neg 225 attribute 225 No connects in hierarchy declarations 210 No dot extension 79 Node collapsing 64 combinational 62 dangling 62 istype 222 keyword 233 registered 62 removing redundant 63 selective collapsing 65 using the range operator in 233 Non inverting outputs attribute for 224 NOT 25 alternate operator for 174 Numbers 22 changing base 194 O g 22 Octal 22 octalf abl 259 Off set 84 One bit changes 98 On set 84 Operators alternate set of 174 arithmetic 25 assignment 28 complement 31 logic 25 overview 24 priority 29 30 relational 26 standard set 197 Optimization and dcset 88 of XORs 86 post linked 64 reducing product terms 98 Optimization and dcset 85 Optimization of XORs 86 OR 25 alternate operator for 174 Other flip flops 93 Output enables 62 Output pin
57. BEL HDL Reference Manual 150 dceset state_diagram State State State State State State State State State State State Zero end Hierarchy Examples Ostate Clear AddClk ICIkIN Ace Low if Restart Low then Clear else ShowHit ShowHit AddClk Low Ace Ace if CardIn Low then AddCard else ShowHit AddCard AddClk C1kIN Ace Ace if is_Ace amp Ace then Add_10 else Wait Add_10 AddClk IC1KIN Ace High goto Wt Wt AddClk Low Ace Ace if CardOut Low then Test_17 else Wait Test 17 AddClk Low Ace Ace if GT16 then ShowHit else Test 22 Test 22 AddClk Low Ace Ace case LT22 ShowStand LT22 amp Ace ShowBust LT22 amp Ace Sub_10 endcase Sub_10 AddClk C1kIN Ace Low goto Test 17 ShowBust AddClk Low Ace Ace if Restart Low then Clear else ShowBust ShowStand AddClk Low Ace Ace if Restart Low then Clear else ShowStand goto Clear ABEL HDL Reference Manual 151 module muxadd title 5 bit ripple adder with input multiplex AddClk Clr Add10 Sub10 is Ace pin V4 V3 V2 V1 VO pin S4 S83 S2 S1 S0 pin C4763 C2 reL pin P SNINA TS AS A gt A O POD Card V4 V3 V2 V1 VO Score S4 S83 S82 S1 S0 CarryIn c 9G4 C3 C 2 Cl 0 CarryOut X C4 C3 C2 C1 ten Oye
58. BJ Q2 Ace BJ Ace Describe inter module connections MA Sub10 BJ Sub10 MA Add10 BJ Add10 AddClk BJ AddClk MA AddC1k AddClk BB S0 S1 S2 83 S4 MA S0 S1 S2 S83 S4 BJ is Ace MA is Ace BJ GT16 BB GT16 BJ LT22 BB LT22 end ABEL HDL Reference Manual Hierarchy Examples 149 module bjack title Outputs Inputs BlackJack state Clk C1kIN GT16 LT22 is_Ace Restart Cardin CardOut Ena Sensor _In InOut Out AddClk Add10 Sub10 Q2 01 00 Ace High Low H L C X Ostate Clear ShowHit AddCard Add_10 Wt Test 17 Test 22 ShowStand ShowBust Sub 10 Zero equations Ostate Ace c Ostate Ace oe machine controller pin System clock pin Score less than 17 and 22 pin Card is ace pin Restart game pin Card present switches pin CardIn CardOut ade o 1 l 1 1 ly cul 0 1 pin Adder clock pin Input Mux control pin Input Mux control pin pin Ace Memory 1 0 1 0 C X test vector charactors Add10 Sub10 02 01 00 bap 1 1 pohly dens MaL 1L pe oly Spe 39 E 0 0 0 24 0 po Op LOR Ou NEG 1 0 r 1 25 T 2 Ope dg AS 1 0 1 27 tj jos diae AO Os T28 Te oy e Alege We Too 829 Ti ye 0P pe Ong 205 dor RT Oe exo 0D apn 70 Os Ope oW Clk Ena Hierarchy Examples A
59. D type Register with False Inputs Other NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM m LOGICO FO NO PRODUCT TERM NO PRODUCT TERM Figure 2 13 D type Register with False Inputs You can use the clearing behavior of D type flip flops to eliminate some conditions in your state diagram and some product terms in the converted design by leaving the cleared register state transition implicit If no specified transition condition is met the machine goes to the cleared register state This behavior can also cause problems if the cleared register state is undefined in the state diagram because if the transition conditions are not met for any state the machine goes to an undefined state and stays there To avoid problems caused by this clearing behavior always have a state assigned to the cleared register state Or if you do not assign a state to the cleared register state define every possible condition so some condition is always met for each state You can also use the automatic transition to the cleared register state by eliminating product terms and explicit definitions of transitions You can also use the cleared register state to satisfy illegal conditions Flip flops If none of the state conditions is met in a state machine that employs JK RS and T type flip flops the state machine does not advance to the next state but ho
60. HDL are performed to 128 bit accuracy which means the supported numeric values are in the range 0 to 2128 minus 1 Numbers are represented in any of five forms The four most common forms represent numbers in different bases The fifth form uses alphabetic characters to represent a numeric value When one of the four bases other than the default base is chosen to represent a number the base used is indicated by a symbol preceding the number Table 1 2 lists the four bases supported by ABEL HDL and their accompanying symbols The base symbols can be upper or lowercase Table 1 2 Number Representation in Different Bases Base Name Base Symbol Binary 2 b Octal 8 o Decimal 10 d default Hexadecimal 16 h When a number is specified and is not preceded by a base symbol it is assumed to be in the default base numbering system The normal default base is base 10 Therefore numbers are represented in decimal form unless they are preceded by a symbol indicating that another base is to be used You can change the default number base See Radix Default Base Numbering Directive on page 194 for more information Examples of supported number specifications are shown below The default base is base ten decimal ABEL HDL Reference Manual 22 Basic Syntax Specification Decimal Value T4 75 75 h75 117 b101 5 o17 15 hOF 15 n NOTE Thecarat is a keyboard character It is not part o
61. HOA 0 B A results in B 1 B HOA B 0 5 which is inserted into the source file at the location of the Irp directive Note that multiple assignments to the same identifier result in an implicit OR Note that if the directive is specified like this IRP A 1 H0A 0 B A the resulting text would be B 1 B HOA B 0 The text appears all on one line because the block in the Irp definition contains no end of lines Remember that end of lines and spaces are significant in blocks ABEL HDL Reference Manual 189 Qlrpc Indefinite Repeat Character Directive Irpc Indefinite Repeat Character Directive Syntax IRPC dummy_arg arg block Use dummy_arg A dummy argument arg An actual argument or a dummy argument name preceded by a block A block lrpc causes the block to be repeated in the source file n times where n equals the number of characters contained in arg Each time the block is repeated the dummy argument takes on the value of the next character Examples IRPC A Cat B A results in B C B aj B tj which is inserted into the source file at the location of the Irpc directive ABEL HDL Reference Manual 190 Message Message Directive Message Message Directive Syntax MESSAGE string Use string Any string Message sends the message specified in string to your monitor You can use this directive to moni
62. Lattice sr Semiconductor aaa aaa Corporation ABEL HDL Reference Manual Version 7 0 Technical Support Line 1 800 LATTICE or 408 428 6414 EXPSYS ABL RM Rev 7 0 1 Copyright This document may not in whole or part be copied photocopied reproduced translated or reduced to any electronic medium or machine readable form without prior written consent from Lattice Semiconductor Corporation The software described in this manual is copyrighted and all rights are reserved by Lattice Semiconductor Corporation Information in this document is subject to change without notice The distribution and sale of this product is intended for the use of the original purchaser only and for use only on the computer system specified Lawful users of this product are hereby licensed only to read the programs on the disks cassettes or tapes from their medium into the memory of a computer solely for the purpose of executing them Unauthorized copying duplicating selling or otherwise distributing this product is a violation of the law Trademarks The following trademarks are recognized by Lattice Semiconductor Corporation Generic Array Logic ISP ispANALYZER ispATE ispCODE ispDCD ispDOWNLOAD ispDS ispDS ispEXPERT ispGDS ispGDX ispHDL ispJTAG isoSmartFlow ispStarter isoSTREAM ispTA ispTEST isoTURBO ispVECTOR ispVerilog ispVHDL Latch Lock LHDL pDS RFT and Twin GLB are trademarks of Lattice Semiconductor Corpo
63. Logic Descriptions Restart Low Or Power Up Restart Low Restart High Cardin High Cardin Low is ce E Ice Add Card l jg Ace amp lane CardQut High ILT22 amp Ape Figure 4 22 Pictorial State Diagram Blackjack Machine ABEL HDL Reference Manual 144 Combined Logic Descriptions Note that in Figure 4 23 each of the state identifiers for example ShowHit is defined as sets having binary values These values were chosen to minimize the number of product terms Operation of the state machine proceeds as follows if no aces are drawn m l a card is needed from the reader the state machine goes to state ShowHit m When Cardin goes low meaning that a card has been read a transition to state AddCard is made The card value is added to the current score The machine goes to Wait state until the card is withdrawn from the reader The machine goes to Test17 state If the score is less than 17 another card is drawn If the score is greater than or equal to 17 the machine goes to state Test22 If the score is less than 22 the machine goes to the ShowStand state If the score is 22 or greater a transition is made to the ShowBust state In either ShowStand or ShowBust state a transition is made to Clear to clear the state register and adder when Restart goes low m When Restart goes back to high the state machine returns to ShowHit and the cycle begins again Operation of
64. Reference Manual 227 Macro Syntax Purpose Use Macro macro_id MACRO dummy_arg dummy_arg block The MACRO declaration statement defines a macro Macros are used to include ABEL HDL code in a source file without typing or copying the code everywhere it is needed macro id An identifier naming the macro dummy arg A dummy argument block A block A macro is defined once in the declarations section of a module and then used anywhere within the module as frequently as needed Macros can be used only within the module in which they are declared Wherever the macro id occurs the text in the block associated with that macro is substituted With the exception of dummy arguments all text in the block including spaces and end of lines is substituted exactly as it appears in the block When debugging your source file you can use the list expand option to examine macro statements The list expand option causes the parsed and expanded source code and the macros and directives that caused code to be added to the source to be written to the listing file Macros and Declared Equations Use declared equations for constant expressions instead of macros for faster processing The file mac ab1 in Figure 5 11 demonstrates the difference ABEL HDL Reference Manual 228 Macro module mac title Demonstrates difference between MACRO and declared equations mac device P16H8 A B C pii 1 2 95 X1 X2 X3
65. Select A15 A0 hD000 A15 50 h1000 which is not the intended equation Assignment Operators Assignment operators are used in equations rather than in expressions Equations assign the value of an expression to output signals For more information see the Equations on page 31 ABEL HDL Reference Manual 27 Basic Syntax There are four assignment operators two combinational and two registered Combinational or immediate assignment occurs without any delay as soon as the equation is evaluated Registered assignment occurs at the next clock pulse from the clock associated with the output Refer to Chapter 2 Design Considerations Table 1 6 shows the assignment operators Table 1 6 Assignment Operators Operator Set Description ON 1 Combinational or detailed assignment ON 1 Implied registered assignment DC X Combinational or detailed assignment DC X Implied registered assignment A CAUTION The and assignment operators are used only when writing pin to pin registered equations Use the and assignment operators for registered equations using detailed dot extensions These assignment operators allow you to fully specify outputs in equations For example in the following truth table the output F is fully specified TRUTH_TABLE A B F 1 1 gt 0 off set 1 0 gt on set 0 1 gt on set
66. The state machine shown below operates the same in terms of the behavior seen on its outputs no matter what type of register is substituted for reg in the signal declarations To allow this flexibility the specification of buffer or invert is required when a state diagram is written for a register type other than reg module statema title State machine example clock hold reset pin P1 P0 pin istype reg buffer CQ uu equations P1 P0 clk clock P1 P0 ar reset state declarations declarations tatema tateA 0 teB 1 1 P1 PO tateC tateD 0 1 Qo oou amp P 0 0 state diagram statema state stateA goto stateB state stateB goto stateC State stateC goto stateD state stateD goto stateA Lest vectors edited end Figure 5 12 Architecture independent State Machine ABEL HDL Reference Manual 243 State_diagram See Also Async_reset Case Dcset Equations Goto If then else Module State State_register Sync_reset Truth_table With Symbolic State Declarations in Chapter 1 Language Structure ABEL HDL Reference Manual 244 State_register State_register Syntax statereg_id STATE_REGISTER Purpose For symbolic state diagrams the STATE_REGISTER is used to declare a symbolic state ma
67. Toggle Ea D Q Qout Clk Figure 2 3 Dot Extensions and Architecture Independence Circuit 1 The following simple ABEL HDL design Figure 2 4 describes this simple one bit synchronous circuit The design description uses architecture independent dot extensions to describe the circuit in terms of its behavior as observed on the output pin of the target device Since this design is architecture independent it will operate the same disregarding initial powerup state irrespective of the device type ABEL HDL Reference Manual 80 module pin2pin Clk Toggle Ena Qout equations Qout Qout OE end Qout CLK OQ Onna QA QQ Figure 2 4 pin 1 pin pin pin test vectors Clk Ena Toggle Es p Q 00 0 C Feedback Considerations Using Dot Extensions 2 11 19 istype Qout FB amp Clk Ena p 0 reg Toggle gt Qout gt 0 gt T3 gt 0 gt T gt 0 gt x gt ds gt Ms gt 0 Pin to Pin One bit Synchronous Circuit If you implement this circuit in a simple GAL16LV8 device the result will be a circuit like the one illustrated in Figure 2 5 Since the features inverted outputs the design equation is automatically modified to take the feedback from Q bar instead of Q Figure 2 5 Dot Extensions and Architecture independence Circuit 2 ABEL HDL Reference Manual 81 Feedback Considerations Using Dot Extensions
68. ailable directives are given on the following pages Some of the directives use arguments to determine how the directive is processed The arguments can be actual arguments or dummy arguments preceded by question marks The rules applying to actual and dummy arguments are presented in Chapter 1 Language Structure ABEL HDL Reference Manual 173 QAlternate Alternate Operator Set Alternate Alternate Operator Set Syntax ALTERNATE Use Alternate enables an alternate set of operators If you are more familiar with the alternate set you may want to use this directive The alternate operators remain in effect until the Standard directive is used or the end of the module is reached Using the alternate operator set precludes use of the ABEL HDL addition multiplication and division operators because they represent the OR AND and NOT logical operators in the alternate set The standard operators amp and still work when Alternate is in effect The alternate operator set is listed in Table 5 4 Table 5 4 Alternate Operator Set Alternate ABEL HDL Operator Operator Description NOT amp i AND OR D XOR I dup XNOR See Also Standard ABEL HDL Reference Manual 174 Carry Maximum Bit width for Arithmetic Functions Carry Maximum Bit width for Arithmetic Functions Syntax Use CARRY expression expression A numeric expression The Carry directive allow
69. amp 1 1 1 1 ABEL HDL Reference Manual 95 State Machines Figure 2 15 Dcset compatible State Machine Description will conflict with the dc set generated by the state diagram for S83 R S2 R S1 n and SO R If equations are defined for state bits the Dcset directive is incompatible This conflict would result in an error and failure when the logic for this design is optimized To correct the problem you must remove the Dcset directive so the implied dc set equations are folded into the off set for the resulting logic function Another option is to rewrite the module as shown in Figure 2 15 module TRAFFICI title Traffic Signal Controller C1k SenA SenB pin Il 9 T7 PR pin 16 Preset control GA YA RA pin Uca GB YB RB pim 4 95 S350 node 31 34 istype reg sr buffer H L Ck X Sit Jp dicio SA Count S3 S0 Define Set and Reset inputs to traffic light flip flops GreenA GA S GA R YellowA YA S YA R RedA RA S RA R GreenB GB S GB R YellowB YB S YB R RedB RB S RB R On 1 0j Off SO p daly test vectors edited equations GB YB RB AP PR GA YA RA AP PR GB YB RB CLK Clk GA YA RA CLK Clk S3 S0 AP PR S3 S0 CLK Clk Figure 2 15 Dcset compatible State Machine Description ABEL HDL Reference Manual 96 end co Dcset n State un w 0
70. ant declarations into the equations section Declarations TMP1 TMP2 pin 18 19 Equations TMP1 A3 A0 B3 B0 TMP2 A7 A4 B7 B4 F TMP1 TMP2 the compiler implements the equations as three discrete product terms with the result TMP1 A3 B3 amp A2 B2 TMP2 A7 S B7 amp A6 B6 F TMP1 amp TMP2 Al S Bl A5 B5 AO S BO A4 B4 amp amp amp amp The first example using intermediate expressions requires one output with 16 product terms the second example using equations requires three outputs with less than 8 product terms per output In some cases the number of product terms required for both methods can be reduced during optimization n NOTE As an alternate method for specifying multi level circuits such as this you can use the Q2 Carry directive See Directive Directives on page 173 See Also Declarations Equations Constants in Chapter 1 Language Structure ABEL HDL Reference Manual 171 attr Signal Attributes attr Signal Attributes See Istype ABEL HDL Reference Manual 172 Directive Directives Directive Directives Purpose Use Directives control the contents or processing of a source file You can use directives to conditionally include sections of ABEL HDL source code bring code in from another file and print messages during processing The av
71. as follows neg Istype neg optimizes the circuit for negative polarity Unspecified logic in truth tables and state diagrams becomes a 0 pos Istype pos optimizes the circuit for positive polarity Unspecified logic in truth tables and state diagrams becomes a 1 dc Istype dc uses polarity for best optimization Unspecified logic in truth tables and state diagrams becomes don t care X Using invert and buffer to Control Programmable Inversion An optional method for specifying the desired state of a programmable polarity output is to use the invert or buffer attributes These attributes ensure that an inverter gate either does or does not exist between the output of a flip flop and its corresponding output pin When you use the invert and buffer attributes you can still use automatic polarity selection if the target architecture features programmable inverters located before the associated flip flop These attributes are particularly useful for devices where the reset and preset behavior is affected by the programmable inverter n NOTE The invert and buffer attributes do not actually control device or equation polarity they only enforce the existence or nonexistence of an inverter between a flip flop and its output pin The polarity of devices that feature a fixed inverter in this location and a programmable inverter before the register cannot be specified using invert and buffer
72. atements or combinations of these different statements GOTO Syntax GOTO state exp The GOTO statement unconditionally jumps to a different state When GOTO is used it is the only transition for the current state Example STATE SO GOTO S1 unconditional branch to state S1 CASE Syntax CASE expression state exp expression state exp ENDCASE The CASE statement is used to list a sequence of mutually exclusive transition conditions and corresponding next states Example STATE SO CASE sel 0 SO sel 1 S1 ENDCASE CASE statement conditions must be mutually exclusive No two transition conditions can be true at the same time or the resulting next state is unpredictable IF THEN ELSE Syntax IF expression THEN state exp ELSE state exp IF THEN ELSE statements specify mutually exclusive transition conditions ABEL HDL Reference Manual 241 State_diagram Example STATE S0 IF address gt hE100 THEN S1 ELSE S2 You can use blocks in IF THEN ELSE statements for example IF Hold THEN Statel WITH o1 ol fb 02 02 fb ELSE State2 The ELSE clause is optional A sequence of IF THEN statements with no ELSE clauses is equivalent to a sequence of CASE statements IF THEN ELSE statements can be chained and nested See If Then Else for more information WITH Syntax state exp WITH equation
73. ation must always be on the left side of the equations y NOTE See Also Hierarchy in ABEL HDL on page 61 ABEL HDL Reference Manual 49 Declarations Signal Declarations The PIN and NODE declarations are made to declare signals used in the design and optionally to associate pin and or node numbers with those signals Actual pin and node numbers do not have to be assigned until you want to map the design into a device Attributes can be assigned to signals within pin and node declarations with the ISTYPE statement Dot extensions can also be used in equations to precisely describe the signals see Dot Extensions on page 53 NOTE Assigning pin numbers defines the particular pin outs necessary for the design Pin numbers only limit the device selection to a minimum number of input and output pins Pin number assignments can be changed later by the compiler Pin Declarations Keyword pin pzn id pin id Pin pin pin ISTYPE attributes See Also Attribute Assignment on page 51 Using Active low Declarations on page 74 Node Declarations Keyword node node_id node id Node node node ISTYPE attributes See Also Attribute Assignment on page 51 Using Active low Declarations on page 74 ABEL HDL Reference Manual 50 Declarations Attribute Assignment Keyword istype signal sig
74. by using a STATE DIAGRAM section in the source file Figure 4 19 shows the source file for the sequencer In the source file the design is given a title the device type is specified and pin declarations are made Constants are declared to simplify the state diagram notation The two state registers are grouped into a set called sreg and the three states A B and C are declared with appropriate values specified for each The state values chosen for this design allow the use of register preload to ensure that the machine starts in state A For larger state machines with more state bits careful numbering of states can dramatically reduce the logic required to implement the design Using constant declarations to specify state values saves time when you make changes to these values The state diagram begins with the STATE DIAGRAM statement that names the set of signals to use for the state register In this example sreg is the set of signals to use ABEL HDL Reference Manual 131 State Diagram Examples default with halt 0 A hold amp lreset reset with halt 1 with halt 0 with halft 0 default with halt 0 start amp reset with halt 0 hold amp reset with halt Figure 4 18 State Diagram 3 state Sequencer Within the STATE_DIAGRAM IF THEN ELSE statements are used to indicate the transitions between states and the input conditions that cause each transition In addition equations are written in ea
75. ce Manual 216 Interface top level Interface top level Syntax module name INTERFACE input set value output set gt bidir set Purpose The INTERFACE keyword declares lower level modules and their ports signals that are used in the current source This declaration is used in conjunction with a FUNCTIONAL_BLOCK declaration for each instantiation of the module Use module_name The name of the module being declared inputs A list of signals in the lower level module used in the gt outputs gt bidirs current source Signal names are separated by commas Use gt and gt to indicate the direction of each port of a functional block value An optional default value for an input that overrides defaults in the lower level module If the lower level module uses the INTERFACE keyword to declare signals the upper level source interface statement must exactly match the signal listing A CAUTION INTERFACE declarations cannot contain dot extensions If you need a specific dot extension across a source boundary to resolve feedback ambiguities for example you must introduce an intermediate signal into the lower level module to provide the connection to the higher level source All dot extension equations for a given output signal must be located in the ABEL HDL module in which the signal is defined No references to the signal s dot extensions can be made outside of the ABEL HDL module n NOTE W
76. ch state that indicate the required outputs for each state or transition For example state A reads State A in 0 in_C 0 if start amp reset then B with halt 0 else A with halt halt This means that if the machine is in state A and start is high but reset is low it advances to state B In any other input condition it remains in state A The equations for in_B and in_C indicate those outputs should remain low while the machine is in state A The equations for halt specified with the with keyword indicate that halt should go low if the machine transitions to state B but should remain at its previous value if the machine stays in state A ABEL HDL Reference Manual 132 Test Vectors State Diagram Examples The specification of the test vectors for this design is similar to other synchronous designs The first vector is a preload vector to put the machine into a known state state A and the following vectors exercise the functions of the machine The A B and C constants are used in the vectors to indicate the value of the current state improving the readability of the vectors module sequence title State machine example qi q0 pin 14 15 istype reg invert clock enab start hold reset pin 111 423 halt pin 17 in B in C pin 12 13 sreg ql 001 State Values A Oe Boc C 2 equations ql q0 halt cl
77. ch transition statement Use state diagram syntax to define a state machine and the IF THEN ELSE CASE GOTO and WITH statements to determine the operation of the state machine Symbolic state machines machines for which the actual state registers and state values are unspecified require additional declarations for the symbolic state register and state names see Symbolic State Declarations on page 52 The syntax for the IF THEN ELSE CASE GOTO WITH SYNC RESET and ASYNC RESET statements are presented here briefly and are discussed further in their respective sections ABEL HDL Reference Manual 240 State_diagram A state machine starts in one of the states defined by state_exp The equations listed after that state are evaluated and the transition statement trans stmt is evaluated after the next clock causing the machine to advance to the next state Equations associated with a state are optional however each state must have a transition statement If none of the transition conditions for a state is met the next state is undefined For some devices undefined state transitions cause a transition to the cleared register state Transition Statements Transition statements describe the conditions that cause transition from one state to the next Each state in a state diagram must contain at least one transition statement Transition statements can consist of GOTO statements IF THEN ELSE conditional statements CASE st
78. chine name Use statereg_id An identifier naming the state register See Also State State_diagram Symbolic State Declarations in Chapter 1 Language Structure Using Symbolic State Descriptions in Chapter 2 Design Considerations ABEL HDL Reference Manual 245 Sync_reset Sync_reset See Async_reset ABEL HDL Reference Manual 246 Test_vectors Test_vectors Syntax Purpose Use TEST_VECTORS note input input gt output output invalues outvalues TEST VECTORS specify the expected functional operation of a logic device by explicitly defining the device outputs as functions of the inputs note An optional string that describes the test vectors inputs An identifier or set of identifiers specifying the names of the input signals or feedback output signals outputs An identifier or set of identifiers specifying the output signals invalues An input value or set of input values outvalues A pin to pin output value or set of output values resulting from the given inputs Test vectors are used for simulation of an internal model of the device and functional testing of the design and device The number of test vectors is unlimited The format of the test vectors is determined by the header Each vector is specified in the format described within the parentheses in the header statement An optional note string can be specified in the header to describe what the ve
79. clared as active low in the declaration section then constant values specified in the test vectors are inverted accordingly interpreted pin to pin See Also Module Trace ABEL HDL Reference Manual 248 Title Title Syntax TITLE string Purpose The TITLE statement gives a module a title that appears as a header in both the programmer load file and documentation file created by the language processor Use The title is specified in the string following the TITLE keyword The string is opened and closed by an apostrophe and is limited to 324 characters The TITLE statement is optional Asterisks in the title string do not appear in the programmer load file header in order to conform with the JEDEC standard Examples An example of a TITLE statement that spans two lines and describes the logic design is shown below module m6809a title 6809 memory decode Jean Designer See Also Module ABEL HDL Reference Manual 249 Trace Trace Syntax TRACE inputs gt outputs Purpose The TRACE statement controls which inputs and outputs are displayed in the simulation output Use TRACE statements can be placed before a test vector section or embedded within a sequence of test vectors Examples TRACE A B gt C Bite TEST_VECTORS A B gt C D 0 3 i ald gt 2 TRACE A B gt D 2 gt 1 3 gt 0 i See Also Test_vectors ABEL HDL Reference Manual 250 T
80. couraged Instead you should use the J and K extensions for JK type flip flops or the S and R extensions for SR type flip flops and use a detailed description method including invert or buffer attributes to describe designs for these register types There is no provision in the language for directly writing pin to pin equations for registers other than D type State diagrams however may be used to describe pin to pin behavior for any register type ABEL HDL Reference Manual 73 Using Active low Declarations Using Active low Declarations In ABEL HDL you can write pin to pin design descriptions using implied active low signals Active low signals are declared with a operator as shown below 101 pin istype reg If a signal is declared active low it is automatically complemented when you use it in the subsequent design description This complementing is performed for any use of the signal itself including as an input as an output and in test vectors Complementing is also performed if you use the FB dot extension on an active low signal The following three designs for example operate identically Design 1 Implied Pin to Pin Active low module act low2 q0 q1 pin istype reg clock pin reset pin equations qd1 q0 clk clock 31 90 ql q0 FB 1 reset test vectors clock reset gt al q0 LE ap de RA Desp T es 4 us la eos De pru SC 32 O gt T v0 su
81. ctors test and is included as output in the simulation output file the document output file and the JEDEC programmer load file The table lists input combinations and their resulting outputs All or some of the possible input combinations can be listed All values specified in the table must be constants either declared numeric or a special constant for example x and C Each line of the table each input output listing must end with a semicolon Test vector output values always represent the pin to pin value for the output signals ABEL HDL Reference Manual 247 Test_vectors Test vectors must be sequential for state machines Test vectors must go through valid state transitions The TRACE keyword can be used to control simulator output from within the source file Functional testing of the physical device is performed by a logic programmer after a device has been programmed The test vectors become part of the programmer load file Examples Following is a simple test vectors section TEST_VECTORS TABI gt Ie Dp 0 0 gt p 0 1 2 1 0 T9 gt POIL 1 1 2 0 0 The following test vectors are equivalent to those specified above because values for sets can be specified with numeric constants IEST VECTORS A B gt C D 0 gt 3 H 1 gt 2 A 2 gt 1 3 gt 0 H If the signal identifiers in the test vector header are de
82. cuceckniasaddeeiedeanst cues sadi a d NA 62 Boned Nodes 2d ez prandiero adas 62 Declaring Lower level Modules in the Top level Source ooooo oooo 62 Instantiating Lower level Modules in Top level Source oooooococoooo 63 Hierarchy and Retargeting and Fitting 0 0 00 cee es 63 Mine oc ri aa a es 63 Merging Feedbacks ooocooccccoccnr eee 64 Postiinked LENS uias daquea de une arrancada edades Es 64 HEURE SD ea e Pod deo UR RU CODE Ede dde Or d OA A eden il d eA 64 cloro 155 oo METTE 65 Pin to pin Language PORTES iid icio oc donde o abdo OR A 65 Device independence vs Architecture independence llsssususss 65 incid PD eee we 65 Signal Dot Extensions ooococccooco enn 66 Pin to pin vs Detailed Descriptions for Registered DesignS ooooooooo 66 Using for Pin to pin Descriptions 22414414464 ob eee ee bend lO RC Ro CR 66 Resolving OS uic dca a ae Kd Fog do op DR op ER RC e Fe ede de cu CPC ede 67 Detailed Circuit Descriptions aua bap kcu emnes eus du Eee x a E a 67 Detailed Descriptions Designing for MacrocellS oooooooooooo 68 Examples of Pin to pin and Detailed Descripti0NS oooooooooo 69 Pin to pin Module Description a ica dioe bbe eee ed ee hee ew ee do dol acea 69 Detailed Module Description ct ace aca a RR RC TR CE AA E EHE d a ac Re ES 70 Detailed Module with Inverted Outputs
83. d equations if you use a device featuring XOR gates XOR_FACTORS converts a sum of products SOP equation into an exclusive OR XOR equation The resulting equation contains the sum of product functions that when exclusive ORed together have the same function as the original The XOR_FACTORS equation is divided into the original equation with the factor or its complement on one side of the XOR and the remainder on the other After deciding the best xor_factors remember to revise the source file to use an XOR device for the final design n NOTE The assignment operator you use in XOR FACTORS equations must match the assignment operator in the EQUATIONS section Examples Q16 Ad cV ID do AS B amp C B amp C amp D lA C amp D Reordering the product terms indicates that A amp B and C amp D are good candidate factors as shown below 1016 A amp B amp IC D IA IB amp C amp D ABEL HDL Reference Manual 258 XOR_factors If we process the following source file the program reduces the equations according to the XOR_Factors A amp B module xorfact xorfact device P20X10 C1k OE pin 1 13 Ay By Ey D pin 2 3 4 5 O16 pin 16 istype reg xor XOR Factors 016 A amp B equations Q16 ACE B amp ID IB amp C amp D lA C amp D AS B amp C end Using A amp B as the XOR Factors the reduced equa
84. d module statement signal set Signals or sets in the lower level module used as ports to higher level sources Use gt and gt to indicate the direction of each port of a functional block Use commas to separate groups of signals port value The default value for the port for input signals only Default values do not apply to output and bidirectional signals Declared Signals Declared signals can be a list of lower level pins sets or a combination of both The following constraints apply to the different signal types ABEL HDL Reference Manual 219 Interface lower level Signal Type Constraints Input Default values must be binary if applied to an individual bit or any positive integer applied to a set All inputs must be listed Output Unlisted outputs are interpreted as No connects NC Unlisted fed back outputs are interpreted as nodes in the upper level source following the naming convention instance name node name Bidirectional Listing bidirectional signals is optional except for those with output enable OE If you specify bidirectional signals the compiler checks for invalid wire connections A CAUTION INTERFACE declarations cannot contain dot extensions If you need a specific dot extension across a source boundary to resolve feedback ambiguities for example you must introduce an intermediate signal into the lower level module to provide the connection to the higher level source A
85. dback considerations and polarity control Chapter 3 Designing with CPLDs Discusses issues to consider when designing for CPLD devices Chapter 4 Source File Examples Contains ABEL HDL module examples These examples are representative of programmable logic applications and illustrate significant ABEL features They also help you create your own source files Chapter 5 Language Heference Gives detailed information about ABEL HDL language elements ABEL HDL Reference Manual 11 Documentation Conventions Documentation Conventions This user manual follows the typographic conventions listed here Convention Definition and Usage Italics Italicized text represents variable input For example project wd1 This means you must replace project with the file name you used for all the files relevant to your design Valuable information may be italicized for emphasis Book titles also appear in italics The beginning of a procedure appears in italics For example To see the waveform output of a vector simulation Bold Valuable information may be boldfaced for emphasis Commands are shown in boldface For example Select the Source New menu item from the ispEXPERT System Project Navigator Courier Monospaced Courier font indicates file and directory names and text that the Font system displays For example The C ISPTOOLS ISPSYS CONFIG subdirectory contains Bold Bold Courier fon
86. dder Card is applied to the adder when Add10 and Sub10 are active high as generated by the BJACK controller When Add10 becomes active low 10 is added to the current score to count an ace as 11 instead of 1 and when Sub10 is active low 10 is added to the current score to count an ace as 1 instead of 11 The adder provides an output named Score S0 S4 which is the sum of the current adder contents and the value selected by the input multiplexer the card reader contents 10 or 10 The comparator monitors the contents of the external card reader Card and generates an output is Ace to the BJACK controller that signifies that an ace is present in the card reader Design Method MUXADD MUXADD consists of a three input multiplexer a five bit ripple adder and a five bit comparator These circuit elements are defined in the equations shown in Figure 4 20 For the multiplexer inputs a set named Card defines inputs VO through V4 as the value of the card reader while inputs Add10 and Sub10 are used directly in the following equations to define the multiplexer The multiplexer output to the adder is named Data and is defined by the equations Data Add10 amp Subl10 amp Card Add10 amp Subl10 amp ten Add10 amp Sub10 amp minus ten The adder MUXADD is a five bit binary ripple adder that adds the current input from the multiplexer to the current score with carry The adder is clocked by a signal AddCIk f
87. design easier to interpret The sections are as follows Constants Constant values are defined Inputs Design inputs are declared Outputs The output pin list contains an Istype declaration for retargetability Sets The names data and count are defined as sets groups containing the inputs d3 d2 d1 and dO and the outputs q3 q2 q1 and q0 respectively Modes The Mode equations are actually more constant declarations First MODE is defined as the set containing cnten Id and u_d in that order Next LOAD is defined as being true when the members of MODE are equal to X 1 and X respectively HOLD UP and DOWN are defined similarly ABEL HDL Reference Manual 119 Equations Equations The design of the counter equations enables you to easily define modes and your actual register equations will be easily readable The counter equation uses WHEN THEN ELSE syntax The first line when LOAD then count data uses the symbolic name LOAD defined earlier in the source file as LOAD MODE X 1 X and MODE itself is a set of inputs in a particular order defined previously as MODE cnten ld u_d The first line of the equation could have been written as follows when cnten X amp ld 1 amp ud X then count data which is functionally the same but the intermediate definitions used instead makes the source file more readable and easier to modify ABEL HDL Reference Manual 120
88. device architectures These dot extensions are therefore referred to as pin to pin or architecture independent Other dot extensions are intended for specific classes of device architectures or require specific device configurations These dot extensions are referred to as detailed or architecture dependent or device specific dot extensions In most cases you can describe a circuit using either pin to pin or detailed dot extensions Which form you use depends on the application and whether you want to implement the application in a variety of architectures The advantages of each method are discussed later in this section Table 5 1 lists the ABEL HDL dot extensions Pin to pin dot extensions are indicated with a check in the Pin to Pin column ABEL HDL Reference Manual 158 ext Dot Extensions Table 5 1 Dot Extensions Dot Ext Pin to pin Description ACLRS 4 A device independent asynchronous register reset equivalent to AR with Istype buffer or AP with Istype invert AP Asynchronous register preset AR Asynchronous register reset ASET 4 A device independent asynchronous register preset equivalent to AP with Istype buffer or AR with Istype invert CE Clock enable input to a gated clock flip flop CLK 4 Clock input to an edge triggered flip flop CLR S Y A device independent synchronous register reset equivalent to SR with Istype buffer o
89. do not support these dot extensions ABEL HDL Reference Manual 160 ext Dot Extensions Detailed Design Dot Extensions Table 5 2 shows the dot extensions that are supported and which of those are required for different register types in detailed design descriptions The required dot extensions are indicated with a check in the Extension Required column Table 5 2 Dot Extensions for Device specific detailed Designs Extension Supported Register Type Required Extensions Definition combinational no register oe output enable pin pin feedback com combinational feedback D type flip flop V clk clock V na data input ste flip flop mode control oe output enable q flip flop feedback SP synchronous preset S synchronous reset ap asynchronous preset ar asynchronous reset pin pin JK type flip flop Y ELE clock Y j j input Y ak k input JC flip flop mode control oe output enable q flip flop feedback SP synchronous reset SEP synchronous reset ap asynchronous preset ar asynchronous reset spin pin feedback SR type flip flop Y elk clock Y S set input V xr reset input oe output enable iG flip flop feedback SP synchronous preset ST synchronous reset ap asynchronous preset ar asynchronous preset pin pin feedback ABEL HDL Reference Manual 161 ext Dot Extensions Table 5 2 Dot Extensions for Device specific detailed Designs Continued Register Type T
90. e Diagrami ERAS asta aed Gro daa aoa ceca cd do e pb ara m ACER RR HR RR 131 DOMO SoU criar rd ir Ada 131 pe oc poc rr I c 131 Design ro PCT nm 131 o A he oe he ed be ih be Reh ee ed aes 133 Combined Logic Descriptions uan oiled maa Resa on deu eden Ed aa aa ERR ARR A 134 Design Specification MUXADD ssessseeeee nh 136 Design Method MUAADO oig dedu disp dos d RR RO Rn pueda Rd RR qd 136 Tesi VEAS MAA dci dci cd xo RCA e AAA dee eod ge ed 137 Design Specification BIMBOD 1 2 24 rasa kukxu kae kk rre 139 Design Method BINBC i23 3d Go Cao ed hoe e OR eR OOS elc os 139 Test Vectors PINEDO asd duda doge whip ua de de dra qae de wa ded C 139 Design Specification BJACK duacauca tosta kun A E RWE RR 142 Design Method BJACK 0 000 cee enn 142 Test Vectors BJACK A CR CR at e Xd Qood Eos CR RAN ARR ERS 145 Hierarchy BOUE LL 434 FOE TAE REDE EX ERR DR cb qe d EC olor slope d 148 ABEL and ispEXPERT System Projects 603 dae qo ea Can RC CRGO e RC Ro ER ence RR RR EU 155 Lower o AMM 156 Chapter 5 Language Reference L usuuuuues s 157 EXE o 4210 4 4004 d CER ROS OCIO WO Rod OE DR COHON ECCE e Re E ol ede 158 Constant Declarations amp uiaseake kw n Y red da x dU Ca OR CR CR COR OCC AE REC 169 ar Signal AHMDUTES 143 ad eu ed EORR RORNC XC Re dea eol io pio oC oce fob d dod 172 Directive Directives 6 ok iid oO de Shedd do
91. e Ge duo eves dei bes Gawd eee Re bese debi arden 246 Test DB ce db eoe ele iacere eode ane Ooh VE ERI RARE 247 goo fer A a aaa a e a D 249 WN EE E d ded ET Uh OA AE AI ee 250 ji 18 Se TIT 251 RM tk hn e e i eth Shetek ly a Ta ot MA a nt Ses c a tb hl 254 loca ix oe od tT TOT ET T T LITT 255 SOM ne 4E RE CX WR A Pod od 257 XOR RUNS eesse RPE As VA CR JUR EE Re ei A OUR CUR He A IA 258 ABEL HDL Reference Manual 9 Preface ABEL HDL is a hierarchical logic description language ABEL HDL design descriptions are contained in an ASCII text file in the ABEL Hardware Description Language ABEL HDL The requirements for ABEL HDL are described in this manual ABEL HDL Reference Manual What is in this Manual What is in this Manual This manual contains the following information Basic syntax and structure of ABEL HDL Hierarchy in ABEL HDL Node collapsing Pin to pin language features Pin to pin vs detailed descriptions for registered designs Equations Combined logic descriptions Dot extensions Constant declarations Signal attributes Directives Design keywords syntax and examples Where to Look for Information Chapter 1 Language Structure Provides the basic syntax and structure of an ABEL HDL design description Chapter 2 Design Considerations Discusses issues to consider when creating an ABEL HDL module such as architecture independent language features active low declarations flip flop equations fee
92. e Manual 233 Node Example a0 a3 node 22 25 assigns a0 a1 a2 and a3 to nodes 22 23 24 and 25 respectively See Also Istype Pin Module Attribute Assignment Attribute Assignment in Chapter 1 Language Structure ABEL HDL Reference Manual 234 Pin Pin Syntax pin_id pin_id PIN pin pin ISTYPE atctr ol Purpose The PIN keyword declares input and output signals that must be available on a device I O pin Use pin id An identifier that refers to a pin in a module pins The pin number on the physical device attr A string that specifies pin attributes for devices with programmable pins Attributes are listed in ISTYPE When lists of pin ids and pin s are used in a pin declaration statement there is a one to one correspondence between the identifiers and numbers given There must be one pin number associated with each identifier listed You can use the range operator to declare sets of pins The ending semicolon is required after each declaration gt NOTE Assigning pin numbers defines the particular pin outs necessary for the design Pin numbers only limit the device selection to a minimum number of input and output pins Pin number assignments can be changed later by a fitter The operator in pin declarations indicates that the pin is active low and is automatically negated when the source file is compiled The pin attribute string Istype attribut
93. e STATE declaration is made to declare a symbolic state name and optionally associate it with a state register Use state_id A symbolic state name to be referenced in a symbolic state description statereg id An identifier for a state register If your design includes more than one symbolic state machine use the IN keyword to associate each state with the corresponding state register Each state you declare corresponds to one flip flop in a one hot machine See Also Async reset State register Sync reset Symbolic State Declarations and Using Symbolic State Descriptions in Chapter 2 Design Considerations ABEL HDL Reference Manual 238 State in State_diagram State in State_diagram Syntax Purpose Use See Also STATE state exp equation equation trans stmt The STATE keyword and the associated section describes one state of a state diagram It includes a state value or a symbolic state name a state transition statement and optional state output equations stale exp An expression value or symbolic state name giving the current state equation An equation that defines the state machine outputs trans stmt IF THEN ELSE CASE or GOTO statements optionally followed by WITH transition equations The specification of a state description requires the use of the state diagram syntax which defines the state machine and the IF THEN ELSE CASE GOTO and WITH statements which determ
94. e diagram for the controller This bubble diagram indicates state transitions and the conditions that cause those transitions Transitions are represented by arrows and the conditions causing the transitions are written alongside the arrow You must express the bubble diagram in the form shown in the state_diagram in Figure 4 23 There is a one to one correlation between the bubble diagram and the state diagram described in the source file Figure 4 23 The table below describes the state identifiers state machine states illustrated in the bubble diagram and listed in the source file ABEL HDL Reference Manual 142 State Identifier Clear ShowHit AddCard Add10 Wt Test17 Test22 Sub10 ShowBust ShowStand Combined Logic Descriptions Description Clear the state machine adder and displays Indicate that another card is needed Hit indicator is lit Add the value at the adder input to the current count Add the fixed value 10 to the current count effectively giving an ace a value of 11 Wait until a card is taken out of the reader Test the current count for a value less than 17 Test the current count for a value less than 22 Add the fixed value 10 to the current count effectively subtracting 10 and restoring an ace to 1 Indicate that no more cards are needed Bust indicator is lit Indicate that no more cards are needed Neither Hit nor Bust indicators are lit ABEL HDL Reference Manual 143 Combined
95. e output pin specified with the invert attribute has necessitated a change in the equation for Q1 D ABEL HDL Reference Manual 70 Pin to pin vs Detailed Descriptions for Registered Designs As this example shows device independence and pin to pin description methods are preferable since you can describe a circuit completely for any implementation Using pin to pin descriptions and generalized dot extensions such as FB CLK and OE as much as possible allows you to implement your ABEL HDL module into any one of a particular class of devices For example any device that features enough flip flops and appropriately configured I O resources However the need for particular types of device features such as register preset or reset might limit your ability to describe your design in a completely architecture independent way If for example a built in register preset feature is used in a simple design the target architectures are limited Consider this version of the design module Q1 5 O1 pin istype reg buffer Clock Preset pin equations Q1 CLK Clock Q1 AP Preset Q1 lQ1 fb test_vectors Clock Preset gt Q1 Es ep Tt J gt 1 RI o 0 gt 0 26 ur O doe 2 SG a 0 gt 0 LES y 1 gt JL oM 1 end The equation for Q1 still uses the assignment operator and FB for a pin to pin description of Q1 s behavior but the use of AP to describe the reset function requir
96. e table defines the values of inputs and the resulting output values Examples This example shows a truth table description of a simple state machine with four states and one output The current state is described by signals A and B which are put into a set The next state is described by the registered outputs C and D which are also collected into a set The single combinational output is signal E The machine simply counts through the different states driving the output E low when A equals 1 and B equals 0 TRUTH TABLE A B C D E 0 gt 1 LORI 1 gt 2 gt 0 2 gt 3 P EM 3 gt 0 gt 1 Note that the input and output combinations are specified by a single constant value rather than by set notation This is equivalent to 0 gt 0 E 0 0 1 V Lo 0 0 1 1 0 1 1 gt 0 1 gt cl gt 1 1 0 0 V Se Se 5 Na 0 gt 1 ABEL HDL Reference Manual 252 See Also Truth_table When writing truth tables in ABEL HDL particularly when describing registered circuits follow the same rules for dot extensions attributes and pin to pin detailed descriptions described earlier for writing equations The only difference between equations and truth tables is the ordering of the inputs and outputs The following two fragments of source code for example are functionally equivalent Fragment 1 equations q a a
97. e this option in combination with Dcset or with the dc attribute See Also Dcset Istype dc ABEL HDL Reference Manual 178 Exit Exit Directive Exit Exit Directive Syntax QEXIT Use The QExit directive stops processing of the source file with error bits set Error bits allow the operating system to determine that a processing error has occurred ABEL HDL Reference Manual 179 Expr Expression Directive Expr Expression Directive Syntax EXPR block expression Use block A block expression An expression Expr evaluates the given expression and converts it to a string of digits in the default base numbering system This string and the block are then inserted into the source file at the point where the Expr directive occurs The expression must produce a number Expr can contain variable values and you can use it in loops with Repeat Examples expr ABC Bl11 Assuming that the default base is base ten this example causes the text ABC3 to be inserted into the source file ABEL HDL Reference Manual 180 lf If Directive Dif If Directive Syntax IF expression block Use expression An expression block A block of text If includes or excludes sections of code based on the value of an expression If the expression is non zero logical true the block of code is included Dummy argument substitution is supported in the expression Exampl
98. eat Directive ua suae ed hon ee kek eR EWR ER EEA n EO ORC RR OR ERS 195 Setsize Set MUON uiuis a dudas a 4o Ro db e SERED CP CCCo e ca Cd 196 Standard Standard Operators Directive ccs 197 ABEL HDL Reference Manual 8 A ccd qaae adu dd bane dad dedi du qd dtd d dde qd duos Gurd dcodud d afe aar d 199 CORN e tiie Rh AGERE ADAN REESE UE da UPC E Pea dob a eee 201 Constant ere irradia 202 A Rn 203 E Leser O c Re as DE i NOR Mean DIR eee Qr ate a meat cae a aed dc e Cl Vp qud 204 A n9 205 cops A 206 Pe BERE rri RA UPC UK EORR CR RARA e eed de OR 208 EI i aque op pon qb LEEA irai opa A e os ee Funde ome Rol Ke ERROR Edo 211 A dd diced bx dad d Ghee eps doc ke ee qut eod qox A Sol Sepe oa d ad 213 ITE IB uideor dox d we deu d dob doe Ea dowd vios E E d REB sawed da dud dati 214 interlace CBBSBVBI sisipara ar daras Eh RE du oam ARE md iro 217 Interface lower level ooooooooococcocor RR Ic 219 Istype _ Attribute Declarations uiua dc e REA E Or Re COR Re Red ed ded AAA 222 EB aeu oo eh eh ee RETE EXC RE JN EP Bd qa C ada 227 ENSE E EE A ox E E WA ee ou E A 228 ilr c TIC A E EE aA 232 Are ae aaa E E da barras E E E do dedos a 233 A A a ai aw hore EAT E T e qe E iua Qus Mio e es 235 PO i oras aida 237 State Le nno PP 238 zu OD Sle A ed edd ERROR UR RC Role RECORDER RO Flea al do SRS 239 State_diagram MA 240 A A eA Reeders ceded dee bude ndas eed eae AEETI 245 PNG TI sa qe t
99. ed case m Identifiers user supplied names and labels can be uppercase lowercase or mixed case but they are case sensitive The identifier output typed in all lowercase letters is not the same as the identifier Output ABEL HDL Reference Manual 15 Basic Syntax Supported ASCII Characters All uppercase and lowercase alphabetic characters and most other characters on common keyboards are supported Valid characters are listed or shown below lt space AZ Li 9 a A 0 lowercase alphabet uppercase alphabet digits gt lt tab gt identifiers S 6 amp Identifiers are names that identify the following items devices device pins or nodes functional blocks sets input or output signals constants macros dummy arguments All of these items are discussed later in this chapter The rules and restrictions for identifiers are the same regardless of what the identifier describes The rules governing identifiers are listed below Identifiers can be up to 31 characters Longer names are flagged as an error Identifiers must begin with an alphabetic character or with an underscore Other than the first character identifiers can contain upper and lowercase characters digits tildes and underscores You cannot use spaces in an identifier Use underscores or uppercase letters to separate words Except for Reserved Identifiers Keywords identifiers are case sensitive upp
100. eed for extensive documentation m Choose identifiers that match their function For example the pin you are going to use as the carry in on an adder could be named Carry in For a simple OR gate the two input pins might be given the identifiers INT and IN2 and the output might be named OR m Avoid large numbers of similar identifiers For example do not name the outputs of a 16 bit adder ADDER OUTPUT BIT 1 ADDER OUTPUT BIT 2 and so on m Useunderscores or mixed case characters to separate words in your identifier IHIS IS AN IDENT FIER IhisIsAnIdentifier is much easier to read than IHISISANIDENT F ER ABEL HDL Reference Manual 18 Basic Syntax Constants Blocks You can use constant values in assignment statements truth tables and test vectors You can assign a constant to an identifier and then use the identifier to specify that value throughout a module see Declarations and Module later in this chapter Constant values can be either numeric or one of the non numeric special constant values The special constant values are listed in Table 1 1 Table 1 1 Special Constants Constant Description Clocked input low high low transition Clock down edge high low transition Floating input or output signal Clocked input high low high transition va m D Register preload SVn n 2 through 9 Drive the input to su
101. equal gt A gt B greater than gt A gt B greater than or equal ABEL HDL Reference Manual 36 Set Evaluation Basic Syntax How an operator is performed with a set may depend on the types of arguments the operator uses When a set is written a b c d 1 a is the MOST significant bit and a is the LEAST significant bit The result when most operators are applied to a set is another set The result of the relational operators gt gt lt lt is a value TRUE all ones or FALSE all zeros which is truncated or padded to as many bits as needed The width of the result is determined by the context of the relational operator not by the width of the arguments The different contexts of the AND amp operator and the semantics of each usage are described below signal amp signal a amp b signal amp number a amp 4 signal amp set a 4 x y z set set a b amp x y set amp number a b c amp 5 number amp number 9 amp 5 This is the most straightforward use The expression is TRUE if both signals are TRUE The number is converted to binary and the least significant bit is used The expression becomes a amp 0 then is reduced to 0 FALSE The signal is distributed over the elements of the set to become a amp x a amp y a amp z The sets are ANDed bit wise resulting in a amp x b amp y An error is displayed if the set width
102. equation You can use the WITH statement in any of the above transition statements the GOTO IF THEN ELSE or CASE statements in place of a simple state expression For example to specify that a set of registered outputs are to contain a specific value after one particular transition specify the equation using a WITH statement similar to the one shown below STATE SO IF reset THEN S9 WITH ErrorFlag 1 ErrorAddress address LSE F address lt hE100 THEN S2 ELSE SOF The WITH statement is also useful when you describe output behavior for registered outputs since registered outputs written only for a current state would lag by one clock cycle SYNC RESET and ASYNC RESET Syntax In symbolic state descriptions the SYNC RESET and ASYNC RESET statements are used to specify synchronous or asynchronous state machine reset logic in terms of symbolic states For example to specify that a state machine must asynchronously reset to state Start when the Reset input is true you would write ASYNC RESET Start Reset See Symbolic State Declarations on page 52 and State Machines on page 90 ABEL HDL Reference Manual 242 State_diagram State Descriptions and Pin to pin Descriptions Sequential circuits described with ABEL HDL s state diagram language are normally written with a pin to pin behavior in mind regardless of the flip flop type specified
103. equired for an incompletely specified function The Dcset directive used for logic description sections and Istype attribute dc used for signals specify don t care values for unspecified logic Consider the following ABEL HDL truth table truth table 13 12 11 10 gt f3 f2 f1 f0 LEO 07 0 Q T Qu 0 0 1 05 0 0 lie E Op Qj XI 0O 0 1 1 gt 0 1 1 1 O 1 1 1 gt 1 1 1 1 1 1 1 1 gt 1 1 1 0 dey sl ls Ll 439 0 lis dy dos Oey OA E O Oye ls dey Oy Oy O xL 0 0 O0 QI This truth table has four inputs and therefore sixteen 2 possible input combinations The function specified however only indicates eight significant input combinations For each of the design outputs f3 through f0 the truth table specifies whether the resulting value should be 1 or 0 For each output then each of the eight individual truth table entries can be either a member of a set of true functions called the on set or a set of false functions called the off set Using output f3 for example the eight input conditions can be listed as on sets and off sets as follows maintaining the ordering of inputs as specified in the truth table above on set of f3 off set of f3 011 0000 1 1 0001 0 0011 0 0 1000 The remaining eight input conditions that do not appear in either the on set or off set are said to be membe
104. ercase letters and lowercase letters are not the same You cannot use periods in an identifier except with a supported dot extension ABEL HDL Reference Manual 16 Basic Syntax Some supported identifiers are listed below HELLO hello _K5input P_h This_is_a_long_identifier AnotherLongIdentifier Some unsupported identifiers are listed below Ta Does not begin with a letter or underscore 4 Does not begin with a letter or underscore HEL LO Contains a period LO is not a valid dot extension b6 kj Contains a space interpreted as two identifiers b6 and kj ABEL HDL Reference Manual 17 Reserved Identifiers Keywords Basic Syntax The keywords listed below are reserved identifiers Keywords cannot be used to name devices pins nodes constants sets macros or signals If a keyword is used in the wrong context an error is flagged async_reset case cycle declarations device else enable obsolete end endcase endwith equations external flag obsolete functional_ block Choosing Identifiers fuses goto if in interface istype library macro module node options pin property state state_diagram state_register sync_reset test_vectors then title trace truth_table wait when with Choosing the right identifiers can make a source file easy to read and understand The following suggestions can help make your logic descriptions self explanatory eliminating the n
105. ere a single equation is supported You can use blocks in simple equations WHEN THEN ELSE IF THEN ELSE CASE and WITH statements When you use equation blocks within a conditional expression such as If then Case or When then the logic functions are logically ANDed with the conditional expression Blocks in Equations The following expressions written without blocks are limited by the inability to specify more than one output in a When then expression without using set notation Without Blocks WHEN Mode S Data THEN Out data S in ELSE WHEN Mode T Data THEN Out data T in WHEN Mode S Data THEN S Valid 1 ELSE WHEN Mode T Data THEN T Valid 1 With blocks delimited with braces the syntax above can be simplified The logic specified for Out data is logically ANDed with the WHEN clause With Blocks WHEN Mode S Data THEN Out data S in S Valid 1 ELSE WHEN Mode T Data THEN Out data T in T Valid 1 ABEL HDL Reference Manual 20 Basic Syntax Blocks in State Diagrams Blocks also provide a simpler way to write state diagram output equations For example the following two state transition statements are equivalent Without Blocks IF Hold THEN Statel WITH ol ol fb 02 02 fb ENDWITH ELSE State2 With Blocks IF Hold THEN Statel WITH o1 ol fb 02
106. es should be used to specify pin attributes The ISTYPE statement and attributes are discussed under Istype Istype attribute statements are recommended for all pins ABEL HDL Reference Manual 235 Pin Examples Clock Reset S1 PIN 1 15 3 Clock is assigned to pin 1 Reset to pin 15 and S1 to pin 3 a0 a3 PIN 2 5 istype reg buffer Assigns a0 a1 a2 and a3 to pins 2 3 4 and 5 respectively See Also Istype Node Module ABEL HDL Reference Manual 236 Property Property Syntax property id PROPERTY string Purpose The PROPERTY declaration statement allows you to specify additional design o associated with an external processing module such as a device Refer to the ispEXPERT System User Manual for more information on Properties of the ispEXPERT System Use property id Identifies properties relevant to specific external modules such as fitters string Argument containing the actual property data A CAUTION Property IDs and strings can be case sensitive A CAUTION Property Information will not be present in pre route functional simulation Consider using schematics to access property features that affect simulation Example PLSI property SCP N1 PATH 1 PLSI property ECP N1 PATH ABEL HDL Reference Manual 237 State Declaration State Declaration Syntax state_id state_id STATE IN statereg_id Purpose Th
107. es if A gt 17 que De ABEL HDL Reference Manual 181 lfb If Blank Directive lfb If Blank Directive Syntax IFB arg block Use arg An actual argument or a dummy argument preceded by a block A block of text lfb includes the text contained within the block if the argument is blank if it contains O characters Examples IFB text here is included with the rest of the source file QIFB hello this text is not included IFB A this text is included if no value is substituted for A See Also Arguments and Argument Substitution in Chapter 1 Language Structure ABEL HDL Reference Manual 182 lfdef If Defined Directive lfdef If Defined Directive Syntax IFDEF id block Use id An identifier block A block of text lfdef includes the text contained within the block if the identifier is defined Examples A pin 5 ifdef A Base hE000 the above assignment is made because A was defined ABEL HDL Reference Manual 183 lfiden If Identical Directive lfiden If Identical Directive Syntax IFIDEN argi arg2 block Use arg1 2 Actual arguments or dummy argument names preceded by a block A block of text The text in the block is included if arg1 and arg2 are identical Examples ifiden A abcd A device P16R4 A device declaration for a P16R4 is made if the actual
108. es consideration of different device architectures The AP extension like the D and Q extensions is associated with a flip flop input not with a device output pin If the target device has inverted outputs the design will not reset properly so this ambiguous reset behavior is removed by using the buffer attribute which reduces the range of target devices to those with non inverted outputs ABEL HDL Reference Manual 71 Pin to pin vs Detailed Descriptions for Registered Designs Versions 5 and 7 of the design above and below are unambiguous but each is restricted to certain device classes module Q1 7 Q1 pin istype reg invert Clock Preset pin equations Q1 CLK Clock Q1 AR Preset Q1 lQ1 fb test_vectors Clock Preset gt Q1 EA pi de 0 gt 0 0o i gt 1 0 1 We Qc o o end When to Use Detailed Descriptions Although the pin to pin description is preferable there will frequently be situations when you must use a more detailed description If you are unsure about which method to use for various parts of your design examine the design s requirements If your design requires specific features of a device such as register preset or unusual flip flop configurations detailed descriptions are probably necessary If your design is a simple combinational function or if it matches the generic macrocell in its requirements you can probably use simple pin to pin descriptions Using
109. es if you want to override the values given in the instantiated module otherwise the instantiated module must exactly match the lower level interface statement See Interface top level on page 217 for more information ABEL HDL Reference Manual 62 Hierarchy in ABEL HDL Instantiating Lower level Modules in Top level Source Use a FUNCTIONAL_BLOCK declaration in an top level ABEL HDL source to instantiate a declared lower level module and make the ports of the lower level module accessible in the upper level source You must declare sources with an INTERFACE declaration before you instantiate them To instantiate the module declared above add an interface declaration and signal declarations to your top level declarations and add port connection equations to your top level equations as shown in the source fragment below DECLARATIONS lowl FUNCTIONAL BLOCK lower zed0 zed7 pin upper level inputs atop pin istype reg buffer upper level output d3 d0 pin istype reg buffer upper level outputs EQUATIONS atop lowl a wire this source s outputs d3 d0 lowl d3 d0 to lower level inputs lowl z0 z7 zed0 zed7 wire this source s inputs to lower level outputs See Functional block on page 208 for more information Hierarchy and Retargeting and Fitting Redundant Nodes When you link multiple sources some unreferenced nodes may be generated These nodes usuall
110. evel source 217 overriding default values 210 supported default values 221 unlisted pins 221 unused outputs 210 wiring lower level signals 209 ABEL HDL Reference Manual 264 Index Identifiers 16 choosing 18 in state machines 90 multiple assignments to 32 reserved 18 If blank 182 If defined 183 If identical 184 If not blank 185 If not defined 186 If not identical 187 If then else keyword 214 Illegal state in state machines 93 Include files 227 Indefinite repeat 189 character 190 Input pin 235 Instantiation 61 interface lower level 219 interface top level 217 of lower level source 61 208 Interface lower level keyword 219 Interface top level keyword 217 Interface submodule 61 Intermediate expressions 170 Invert attribute 224 example 70 Inverter polarity control 77 Inverting outputs attribute for 224 Istype and polarity control 77 Istype keyword 222 J JK flip flop clocked memory element 226 dot extensions 161 emulation of 88 JK flip flops 73 K Keep attribute 224 Keywords async_reset 198 case 199 declarations 203 device 204 end 205 equations 206 functional_block 208 fuses 211 goto 213 if then else 214 interface lower level source 219 interface top level source 217 istype 222 library 227 macro 228 module 232 node 233 pin 235 property 237 state declaration 238 state in state_diagram 239 state_diagram 240 state_register 245 sync_reset 198 test_vectors 247 title 2
111. f a control key sequence You can also specify numbers by strings of one or more alphabetic characters using the numeric ASCII code of the letter as the value For example the character a is decimal 97 and hexadecimal 61 in ASCII coding The decimal value 97 is used if a is specified as a number ABEL HDL Reference Manual 23 Strings Basic Syntax Sequences of alphabetic characters are first converted to their binary ASCII values and then concatenated to form numbers Some examples are shown below Specification Hex Value Decimal Value a h61 97 b h62 98 abc h616263 6382203 Strings are series of ASCII characters including spaces enclosed by apostrophes Strings are used in the TITLE MODULE and OPTIONS statements and in pin node and attribute declarations as shown below Hello Text with a space in front The preceding line is an empty string Punctuation is allowed You can include a single quote in a string by preceding the quote with a backslash It s easy to use ABEL You can include backslashes in a string by using two of them in succession He she can use backslashes in a string 0 NOTE The grave accent is also accepted as a string delimiter and can be used interchangeably with the apostrophe Operators Expressions and Equations Items such as constants and signal names can be brought together in expressions Expressions
112. f product terms In a similar manner the equation LT A gt B A B uses the same product terms as equations EO A B GT A gt B whereas the equation LT A E in the second set of equations requires the use of additional product terms Sharing product terms in devices that allow this type of design architecture can serve to fit designs into smaller and less expensive logic devices ABEL HDL Reference Manual 126 Equations module comp4a title 4 bit look ahead comparator A3 A0 pin 1 4 A A3 A0 B3 B0 pin Di 8 B B3 B0 NE EQ GT LT pin 16 19 istype com No Yes 0 1 equations EQ A B NE I A B GT A gt B LT A gt B A B test vectors deleted end Figure 4 14 Source File 4 bit Comparator Test Vectors Three separate test vectors sections are written to test three of the four possible conditions The fourth and untested condition of NOT EQUAL TO is simply the inverse of EQUAL TO Each test vectors table includes a test vector message that helps make report output from the compiler and the simulators easier to read The three tested conditions are not mutually exclusive so one or more of them can be met by a given A and B In the test vectors table the constants YES and NO rather than 1 and 0 are used for ease of reading YES and NO are declared in the declaration section o
113. f the ISTYPE statement are applied to each signal specified on the left side Declarations of the pin and node names used in the ISTYPE statement must be made before or with the ISTYPE statement Table 5 5 summarizes the available attributes A CAUTION Ifyou do not specify signal attributes with Istype the compiler makes assumptions about signal attributes that may or may not be what you intended See Also ext Dot Extensions ABEL HDL Reference Manual 222 Istype _ Attribute Declarations Table 5 5 Attributes Dot Ext Arch Indep Description buffer No Inverter in Target Device collapse Collapse remove this signal com Combinational output tac 4 Unspecified logic is don t care invert Inverter in Target Device keep Do not collapse this signal from equations neg Y Unspecified logic is 1 pos Y Unspecified logic is 0 retain Y Do not minimize this output Preserve redundant product terms reg 4 Clocked Memory Element reg d D Flip flop Clocked Memory Element reg_g D Flip flop Gated Clock Memory Element reg_jk JK Flip flop Clocked Memory Element reg sr SR Flip flop Clocked Memory Element PEG OR T Flip flop Clocked Memory Element xor XOR Gate in Target Device Vf neither keep nor collapse is specified the optimization or fitter programs can keep or collapse the signal as needed to optimize the circuit The dc ne
114. f the source file ABEL HDL Reference Manual 127 Truth Table Examples Truth Table Examples Seven segment Display Decoder This display decoder decodes a four bit binary number to display the decimal equivalent on a seven segment LED display The design incorporates a truth table Design Specification Figure 4 15 shows a block diagram for the design of a seven segment display decoder and a drawing of the display with each of the seven segments labeled to correspond to the decoder outputs To light a segment the corresponding line must be driven low Four input lines DO D3 are decoded to drive the correct output lines The outputs are named a b c d e f and g corresponding to the display segments All outputs are active low An enable ena is provided When ena is low the decoder is enabled when ena is high all outputs are driven to high impedance D 01 r e d Da el E a T p3 1 Figure 4 15 Block Diagram Seven segment Display Decoder Design Method Figure 4 16 and Figure 4 17 show the simplified block diagram and the source file for the ABEL HDL implementation of the display decoder The binary inputs and the decoded outputs are grouped into the sets bcd and led The constants ON and OFF are declared so the design can be described in terms of turning a segment on or off To turn a segment on the appropriate line must be driven low thus we declare ON as 0 and OFF as 1 ABEL HDL Reference Manual 128 Truth
115. fb SR T5 lk Rst pin instances of prep6 ap1 Figure 4 25 rep Variable instances of PREP6 rep message exit DO pin Q0 pin istype Must specify arg N reg Q15 Q0 DS DOT nst N rep 1 Dl5 D0 interface macro i expr ACC i nst i 0 peat rep functional_block prep6 const i i 1 ons 0 D15 D0 D const i 0 repeat rep ACC i Clk Rst const i itl Clk Rst const i 0 repeat rep 1 ACC i 1 D15 D0 ACC i 015 00 const i itl ACC N Q15 Q0 Clk Rst gt Q15 00 Figure 4 24 Top level ABEL HDL Source ABEL HDL Reference Manual 155 ABEL and ispEXPEHT System Projects Lower level Sources Figure 4 25 shows the lower level ABEL HDL file instantiated by p6top ab1 This file does not contain an interface statement which is optional in lower level files module prep6 title 16 Bit Accumulator D15 D0 pin Q15 Q0 pin istype reg Clk Rst pin Q 015 00 B D15 D0 carry 2 equations Q D Q Q C Clk Q AR Rst end Figure 4 25 Lower level ABEL HDL Source ABEL HDL Reference Manual 156 Chapter5 Language Reference This chapter provides detailed information about each of the language elements in ABEL HDL It assumes you are familiar with the basic syntax discussed in Chapter 1 Lan
116. feedback path will be used If the specified device does not feature pin feedback an error will be generated Output enables frequently affect the operation of fed back signals that originate at a pin Q Extension Signals specified with the o extension for example count d count q 1 will originate at the Q output of the associated flip flop The fed back value may or may not correspond to the value you observe on the associated output pin if an inverter is located between the Q output of the flip flop and the output pin as is the case in most registered PAL type devices the value of the fed back signal will be the complement of the value you observe on the pin D Extension Some devices allow feedback of the input to the register To select this feedback use the D extension Some device kits also support COM for this feedback ABEL HDL Reference Manual 79 Feedback Considerations Using Dot Extensions Dot Extensions and Architecture independence To be architecture independent you must write your design in terms of its pin to pin behavior rather than in terms of specific device features such as flip flop configurations or output inversions For example consider the simple circuit shown in Figure 2 3 This circuit toggles high when the Toggle input is forced high and low when the Toggle is low The circuit also contains a three state output enable that is controlled by the active low Enable input
117. g and pos attributes are mutually exclusive The retain attribute only controls optimization performed by ABEL HDL Compile Logic To preserve redundant product terms you must also specify no reduction for the Reduce Logic and fitting place and route programs ABEL HDL Reference Manual 223 Istype _ Attribute Declarations buffer The target architecture does not have an inverter between the associated flip flop if any and the actual output pin invert The target architecture has an inverter between the associated flip flop if any and the actual output pin Control of output inversion in devices is accomplished through the use of the invert or buffer attributes These attributes enforce the existence invert or non existence buffer of a hardware inverter at the device pin associated with the output signal specified In registered devices the invert attribute ensures that an inverter is located between the output pin and its associated register output n NOTE Ensuring an inverter is important for both pin to pin and detailed design descriptions because the location of the inverter affects a register s reset preset preload and powerup behavior as observed on the associated output pin collapse Collapse remove this combinational node If neither keep nor collapse is specified the compiler will keep or collapse the node for best optimization In the following example signal b is gi
118. guage Reference These dot extensions help resolve circuit ambiguities when describing architecture independent circuits ABEL HDL Reference Manual 66 Pin to pin vs Detailed Descriptions for Registered Designs Resolving Ambiguities In the equation above Q1 Q1 Preset there is an ambiguous feedback condition The signal Q1 appears on the right side of the equation but there is no indication of whether that fed back signal should originate at the register come directly from the combinational logic that forms the input to the register or come from the I O pin associated with Q1 There is also no indication of what type of register should be used although register synthesis algorithms could theoretically map this equation into virtually any register type The equation could be more completely specified in the following manner Q1 CLK Clock Register clocked from input Q1 Q1 FB Preset Reg feedback normalized to pin value This set of equations describes the circuit completely and specifies enough information that the circuit will operate identically in virtually any device in which you can fit it The feedback path is specified to be from the register itself and the CLK equation specifies that the memory element is clocked rather than latched Detailed Circuit Descriptions In contrast to a pin to pin description the same circuit can be specified in a detailed form of design description in the following
119. guage Structure Each entry contains the following sections if applicable Syntax is the required syntax for the element Purpose is a brief description of the intended use of the element m Use is a discussion of the potential uses of the element including any special considerations m Examples are examples of the element as it is used in a design description See Also refers to other elements and discussions and to design examples that demonstrate the use of an element Basic syntax information on subjects such as blocks strings sets and arguments is provided in Chapter 1 Language Structure ABEL HDL Reference Manual 157 ext Dot Extensions ext Dot Extensions Syntax Purpose Use signal name ext Dot extensions provide a way to refer specifically to internal signals and nodes that are associated with a primary signal in your design Signal dot extensions describe more precisely the behavior of signals in a logic description and remove the ambiguities in equations You can use ABEL HDL dot extensions in complex language constructs such as nested sets or complex expressions Using Pin to Pin Vs Detailed Dot Extensions Dot extensions allow you to refer to various circuit elements such as register clocks presets feedback and output enables that are related to a primary signal Some dot extensions are general purpose and are intended for use with a wide variety of
120. hem with a FUNCTIONAL_BLOCK statement instance_name A unique identifier for this instance of the functional block in the current source source_name The name of the lower level module that is being instantiated signal attributes explicit or implied are inherited by the upper level source signals Therefore you do not need to specify ISTYPEs in higher level sources for instantiated signals Creating Multiple Instances You can use the range operator to instantiate multiple instance names of the module For example CNTO CNT3 functional_block cnt4 creates 4 instances of the lower level module cnt4 ABEL HDL Reference Manual 208 Functional_block Mapping Ports to Signals Signal names are mapped to port names using equations similar to wiring the signals on a schematic You need to specify only the signals used in the upper level source if default values have been specified in the lower level module interface statement See Interface lower level in this chapter for more information on setting default values To specify the signal wiring map signal names to the lower level module port names with dot extension notation There are three kinds of wire input output and interconnect Input Wire Connects lower level module inputs to upper level source inputs Instance port input Output Wire Connects upper level source outputs to lower level module outputs output instance port Interco
121. hen you instantiate a lower level module in an upper level source any signal attributes either explicit or implicit are inherited by the higher level source signals that map to the lower level signals Do not specify ISTYPEs for instantiated signals ABEL HDL Reference Manual 217 Interface top level Examples module top cnt4 interface ce ar clk gt q3 q0 Map port names to signal names with equations See Functional block See Also Functional block Hierarchy in ABEL HDL in Chapter 2 Design Considerations ABEL HDL Reference Manual 218 Interface lower level Interface lower level Syntax Purpose Use MODULE module_name INTERFACE input set port value gt output set gt bidir set The INTERFACE declaration is optional for lower level modules Use the INTERFACE declaration in lower level modules to assign a default port list and input values for the module when instantiated in higher level ABEL HDL sources If you use the interface statement in an instantiated module you must declare the signals and sets in the upper level source in the same order and grouping as given in the INTERFACE statement in the lower level module Interface lower level source Declaring signals in the lower level module although optional does allow the compiler to check for signal declaration mismatches and therefore reduces the possibility of wiring errors module name The standar
122. iagram Examples State Diagram Examples 3 state Sequencer The following design is a simple sequencer that demonstrates the use of ABEL HDL state diagrams The number of State Diagram states that can be processed depends on the number of transitions and the path of the transitions For example a 64 state counter uses fewer terms and smaller equations than a 63 state counter For large counter designs use the syntax CountA CountA 1 to create a counter rather than using a state machine See also example COUNT116 abl for further information on counter implementation Design Specification Figure 4 18 shows the sequencer design with a state diagram that shows the transitions and desired outputs The state machine starts in state A and remains in that state until the start input becomes high It then sequences from state A to state B from state B to state C and back to state A It remains in state A until the start input is high again If the reset input is high the state machine returns to state A at the next clock cycle If this reset to state A occurs during state B a halt synchronous output goes high and remains high until the machine is again started During states B and C asynchronous outputs in B and in C go high to indicate the current state Activation of the hold input will cause the machine to hold in state B or C until hold is no longer high or reset goes high Design Method The sequencer is described
123. ier naming a signal or set of signals or an actual set to which the value of the expression is assigned expression Any valid expression and Combinational and registered pin to pin assign ment operators Equations use the Assignment Operators and combinational and and registered described in Chapter 1 Language Structure The complement operator expresses negative logic The complement operator precedes the signal name and implies that the expression on the right of the equation is to be complemented before it is assigned to the signal Using the complement operator on the left side of equations is also supported equations for negative logic parts can just as easily be expressed by complementing the expression on the right side of the equation A CAUTION WHEN THEN ELSE is only supported in equations Use IF THEN ELSE in STATE DIAGRAM descriptions Equation blocks in conditional expressions such as WHEN THEN result in logic functions that are logically ANDed with the conditional expression that is in effect ABEL HDL Reference Manual 255 When Then Else Examples WHEN Mode S_Data THEN Out_data S_in S Valid 1 ELSE WHEN Mode T Data THEN Out data T in T Valid 1 See Also Equations in Chapter 1 Language Structure ABEL HDL Reference Manual 256 With Syntax Purpose Use
124. ignal The signal specified will be implemented using an XOR gate fed by two sum of products logic circuits If you use XOR operators in the design equations for this output or if you use high level operators that result in XOR operations then one XOR operator is retained through optimization Use this attribute if you are implementing your design in an architecture featuring XOR gates FO A istype invert reg This declaration statement defines FO and A as inverted registered outputs You must define both FO and A earlier in the module The following signal declarations are all supported q3 q2 q1 q0 NODE ISTYPE reg SR Clk a b c PIN 1 2 3 4 reset PIN reset ISTYPE com Output PIN 15 ISTYPE reg invert ext Pin Node Dot Extensions Attribute Assignment and XOR Factors in Chapter 1 Language Structure ABEL HDL Reference Manual 226 Library Library Syntax LIBRARY name Purpose The LIBRARY statement causes the contents of the indicated file to be inserted in the ABEL HDL source file The insertion begins at the LIBRARY statement Use name A string that specifies the name of the library file excluding the file extension The file extension of inc is appended to the name specified and the resulting file name is searched for If no file is found the abelblib inc library file is searched See Also Module Include ABEL HDL
125. ignal M which is declared as a node and named but is used only inside the subcircuit as a component of other more complex signals Figure 3 5 shows the declarations and equations that would generate the logic shown in Figure 3 6 ABEL HDL Reference Manual 104 CPLD Design Strategies declarations A B C D E pin X Y pin M node equations intermediate signal equations M A amp B amp C X M BSC Y A amp D A amp E M Figure 3 5 Declarations and Equations FUNCTIONAL BLOCK B c X 4 B C A D Y A E Figure 3 6 Schematic with Intermediate Signal M Both design descriptions are functionally the same Without the intermediate signal compilation generates the AND gate associated with A amp B amp C twice and the device compiler must filter out the common term With the intermediate signal this sub signal is generated only once as the intermediate signal M and the compiler has less to do Using intermediate signals in a large design targeted for a complex PLD can save compiler optimization effort and time It also makes the design description easier to interpret As another example compare the state machine descriptions in Figure 3 7 and Figure 3 8 Note that Figure 3 8 is easier to read ABEL HDL Reference Manual 105 CPLD Design Strategies CASE which_code_enter from_disarmed_ready CASE sens_code sens_off amp key_code key_pound amp key_code key_star am
126. igure 3 8 State Machine Description with Intermediate Signals ABEL HDL Reference Manual 107 CPLD Design Strategies The declarations and equations required to create the intermediate signals used in Figure 3 8 are shown in Figure 3 9 pin and node declarations sens code 0 sens code 1 sens code 2 sens code 3 pin key code 0 key code 1 key code 2 key code 3 pin which code enter O0 which code enter 1l which code enter 2 node istype reg set declarations which code enter which code enter O0 which code enter 2 sens code sens code O0 sens code 3 key code key code O0 key code 3 code entry sub states from disarmed ready 1 0 0 from armed 0 0 0 sens off 0 0 0 0 key encoding key pnd Gb 303 005 key str zB 0g Tp Ll key non 0 0 0 0 intermediate signals enter from disarmed ready node enter from armed node sensors off node key numeric node key none node key pound star node Figure 3 9 Intermediate Signal Declarations and Equations ABEL HDL Reference Manual 108 equal aspe tions CPLD Design Strategies en en rmediat quations ter from disarmed ready ter from armed which code enter from armed sens key numeric amp amp key code key non key none key code key non key pound star which code enter from disarmed ready ors off sens code sens
127. in that base that begin with an alphabetic character must begin with leading zeroes Examples radix 2 change default base to binary radix 1010 change from binary to decimal ABEL HDL Reference Manual 194 Repeat Repeat Directive Repeat Repeat Directive Syntax REPEAT expr block Use expr A numeric expression block A block Repeat causes the block to be repeated n times where n is specified by the constant expression Examples The following use of the repeat directive repeat 5 H results in the insertion of the text H H H H H into the source file The Repeat directive is useful in generating long truth tables and sets of test vectors Examples of 9 Repeat can be found in the example files ABEL HDL Reference Manual 195 Setsize Set Indexing Setsize Set Indexing Syntax SETSIZE expression Purpose The Setsize directive generates a number corresponding to the number of elements in the expression which must be a set This directive is useful for set indexing operations Example SETSIZE a b c generates the number 3 For set indexing you can use the setsize directive in macros in the following manner high macro s S SETSIZE S 1 SETSIZE S 2 1 The high macro returns the upper half of a set of any size the high 4 bits of an 8 bit set for example n NOTE The terminating semicolons are req
128. ine the operation of the state machine Symbolic state machines machines for which the actual state registers and state values are unspecified require additional declarations for the symbolic state register and state names See Symbolic State Declarations on page 52 A semicolon is required after each transition statement Async reset State diagram Case Sync reset Dcset Truth_table Equations With Goto Chapter 2 Design Considerations If then else Module State ABEL HDL Reference Manual 239 State_diagram State_diagram Syntax STATE DIAGRAM state reg gt state out STATE state exp equation equation trans stmt Purpose The state description describes the operation of a sequential state machine implemented with programmable logic Use state reg An identifier or set of identifiers specifying the signals that determine the current state of the machine For symbolic state diagrams this identifier is a symbolic state register name that has been declared with a State register declaration slate out An identifier or set of identifiers that determines the next state of the machine for designs with external registers state exp An expression or symbolic state name giving the current state equation An equation that defines the state machine outputs trans stmt IF THEN ELSE CASE or GOTO statements optionally followed by WITH transition equations A semicolon is required after ea
129. ion statement associates the device name used ina module with an actual programmable logic device on which designs are implemented device_id An identifier used for the programmer to load file names real_device A string describing the architecture name of the real device represented by device_id The device declaration is optional You should give device identifiers used in device declarations valid file names since JEDEC files are created by appending the extension jed to the identifier The architecture name of the programmable logic device is indicated by the string real_device The ending semicolon is required ABEL HDL Reference Manual 204 End End Syntax END module_name Purpose The end statement denotes the end of the module Use The end statement can be followed by the module name For multi module source files the module name is required ABEL HDL Reference Manual 205 Equations Syntax Purpose Use Equations EQUATIONS element condition element condition when then else statement inst name LSC macro name port definition The equations statement defines the beginning of a group of equations associated with a device condition An expression element An identifier naming a signal set of signals or actual set to which the value of the expression is assigned expression An expression and Combinational and registered pin to pin on set and dc set as
130. irst segment turns off the second whereas the second form cannot be so easily translated into meaningful terms ABEL HDL Reference Manual 129 module titl bed seven segment display decoder El el D3 D2 D1 D0 1 a b c d e f g b Ko segment identification Ena pin 2 3 4 pin 13 14 1 3 6 1 15 16 17 18 19 istype bed D3 D2 D1 D0 led a b c d e f g ON OFF 0 1 Tn O GS Dg To T a equations led oe Ena dcset truth table bcd apos G 0 ON ON ON 1 OFF ON ON 2 gt ON ON OFF 3 ON ON ON 4 gt OFF ON ON 5 ON OFF ON 6 ON OFF ON IET ON ON ON 8 ON ON ON 9 ON ON ON test vectors edited end Lor common anode LI d e f g ON ON ON OF OFF OFF OFF OE ON ON OFF O ON OFF OFF O OFF OFF ON O ON OFF ON O ON ON ON O OFF OFF OFF OF ON ON ON O ON OFF ON O FJ F y HZZZZ Truth Table Examples BCD to seven segment decoder similar to the 7449 com EDs Figure 4 17 Source File 4 bit Counter with 2 input Mux Test Vectors The test vectors for this design test the decoder outputs for the ten valid combinations of input bits The enable is also tested by setting ena high for the different combinations All outputs should be at high impedance whenever ena is high ABEL HDL Reference Manual 130 State D
131. is why the Qout D and Qout o signals are reversed from the architecture independent version of the design presented earlier ABEL HDL Reference Manual 82 Feedback Considerations Using Dot Extensions NOTE The inversion operator applied to Qout D does not correspond directly to the inversion found on each output of a GAL16LV8 The equation for Qout D actually refers to the D input of one of the GAL 16LV8 s flip flops the output inversion found in a GAL16LV8 is located after the register and is assumed rather than specified To implement this design in a device that does not feature inverted outputs the design description must be modified The following example Figure 2 7 shows how to write this detailed design for the device that does not feature inverted outputs module detail2 Clk pin 1 Toggle pin 2 Ena pin 11 Qout pin 19 istype reg D equations Qout D Qout Q amp Toggle Qout CLK Clk Qout OE Ena test_vectors Clk Ena Toggle gt Qout ij TOU iO js gt 0 Que y gt 1 Ss gt 0 Ss qo gt ds SQ eu gt 0 Cap Ob n gt Lies O O gt 1 cg Sz gt a Le 0 0 gt 0 end Figure 2 7 Detail One bit Synchronous Circuit with Non inverted Qout ABEL HDL Reference Manual 83 Using Don t Care Optimization Using Don t Care Optimization Use Don t Care optimization to reduce the amount of logic r
132. it else Test_22 AddClk Low Ace Ace case LT22 ShowStand LT22 amp Ace ShowBust LT22 amp Ace Sub_10 endcase AddClk C1kIN Ace Low goto Test_17 AddClk Low Ace Ace if Restart Low then Clear els AddClk Low Ace Ace if Restart Low then Clear else ShowStand goto Clear Combined Logic Descriptions N then Add 10 else Wait N then Test 17 else Wait Figure 4 23 Source File State Machine Controller Continued ABEL HDL Reference Manual 147 Hierarchy Examples Hierarchy Examples The following ABEL HDL source files show how to combine the three blackjack examples into one top level source for implementation in a larger device The three lower level modules are unchanged from the non hierarchical versions The test vectors have been removed module bjacktop title instantiating bjack muxadd binbcd Sub module prototypes bjack interface Clk CLkIN GT16 LT22 1is Ace Restart Cardin CardOut Ena gt AddClk Add10 Sub10 02 00 Ace muxadd interface VO V4 AddClk Clr Add10 Sub10 gt S0 S4 gt is Ace binbcd interface S0 S4 LT22 GT16 gt DO D5 Sub module instantiations BJ functional block bjack MA functional block muxadd BB functional block binbcd Top level inputs Clk pin System clock bjack CardIn CardO
133. k clock q1 q0 halt oe enab state_diagram sreg State A Hold in state A until start is active in_B 0 in_C 0 IF start amp reset THEN B WITH halt 0 ELSE A WITH halt halt fb State B Advance to state C unless reset is active in_B 1 or hold is active Turn on halt indicator in_C 0 if reset IF reset THEN A WITH halt 1 ELSE IF hold THEN B WITH halt 0 ELSE C WITH halt 0 State C Go back to A unless hold is active in_B 0 Reset overrides hold in_C 1 IF hold amp reset THEN C WITH halt 0 ELSE A WITH halt 0 test vectors edited end Figure 4 19 Source File 3 state Sequencer ABEL HDL Reference Manual 133 Combined Logic Descriptions Combined Logic Descriptions This section contains an advanced logic design and builds on examples and concepts presented in the earlier sections of this manual This design a blackjack machine is the combination of more than one basic logic design Design specification methods and complete source files are given for all parts of the blackjack machine example which contains the following logic designs Multiplexer 5 bit adder Binary to BCD converter State machine This example is a classic blackjack machine based on C R Clare s design in Designing Logic Systems Using State Machines McGraw Hill 1972 The blackjack machine plays
134. lable directives are listed below See 9 in Chapter 5 Language Reference for complete information QALTERNATE CARRY CONST DCSET DCSTATE EXPR EXIT IF IFB IFDEF IFIDEN IFNB IFNDEF IFNIDEN INCLUDE IRP IRPC MESSAGE ONSET PAGE RADIX REPEAT SETSIZE STANDARD ABEL HDL Reference Manual 59 Chapter 2 Design Considerations This chapter discusses issues you need to consider when you create a design with ABEL HDL The topics covered are listed below m Hierarchy in ABEL HDL m Pin to Pin Architecture independent Language Features m Pin to Pin vs Detailed Descriptions for Registered Designs m Using Active low Declarations m Polarity Control m Istypes and Attributes m Flip flop Equations m Feedback Considerations Using Dot Extensions m Dcset Considerations and Precautions m Exclusive OR Equations m State Machines m Using Complement Arrays m Accessing Device specific and Complex Architectural Elements ABEL HDL Reference Manual 60 Hierarchy in ABEL HDL Hierarchy in ABEL HDL You use hierarchy declarations in an upper level ABEL HDL source to refer to instantiate an ABEL HDL module To instantiate an ABEL HDL module in the lower level module optional 1 Identify lower level I O Ports signals with an INTERFACE statement To instantiate an ABEL HDL module in the top level source 2 Declare the lower level module with an Interface declaration 3 Instantiate the
135. larations Logic Description Test Vectors End The elements of the source file are shown in the template in Figure 1 1 There are also directives that can be included in any of the middle three sections The sections are presented briefly then each element is introduced You can find complete information in Chapter 5 Language Reference The following rules apply to module structure m A module must contain only one header composed of the Module statement and optional Title and Options statements m All other sections of a source file can be repeated in any order Declarations must immediately follow either the header or the Declarations keyword m Nosymbol identifier can be referenced before it is declared The Header Section can consist of the following elements Module required Interface lower level optional Title Declarations A Declarations Section can consist of the following elements m Declarations Keyword Interface and Functional Block Declarations Signal Declarations pin and node numbers optional Constant Declarations Macro Declarations Library Declarations Device Declaration one per module ABEL HDL Reference Manual 43 Basic Structure Logic Description Test End Vectors Header Declarations MODULE The module statement names the module and indicates if dummy arguments are used In lower level modules it can be followed by an interface declaration
136. lds its present state due to the low input to the register from the OR array output In such a case the state machine can get stuck in a state You can use this holding behavior to your advantage in some designs If you want to prevent the hold you can use the complement array provided in some devices to detect a no conditions met situation and reset the state machine to a known state ABEL HDL Reference Manual 93 State Machines Precautions for Using Don t Care Optimization When you use don t care optimization you need to avoid certain design practices The most common design technique that conflicts with this optimization is mixing equations and state diagrams to describe default transitions For example consider the design shown in Figure 2 14 module TRAFFIC title Traffic Signal Controller C1k SenA SenB pin LB Ws PR pin 16 Preset control GA YA RA pin ESTA 3s GB YB RB pin 11 9 Node numbers are not required if fitter is used 3 50 node 31 34 istype reg sr buffer COMP node 43 H L Ck X Ts Oy xQuu uy Count S3 S0 Define Set and Reset inputs to traffic light flip flops GreenA GA S GA R YellowA YA S YA R RedA RA S RA R GreenB GB S GB R YellowB YB S YB R RedB RB S RB R On 1 Qus Off epe 1 test_vectors edited equations GB YB RB AP PR GA YA RA AP PR GB YB RB CLK Clk
137. le 1 4 Arithmetic Operators Operator Examples Description twos complement negation subtraction addition multiplication unsigned integer division modulus remainder from lt lt shift A left by B bits gt gt shift A right by B bits ABEL HDL Reference Manual 25 Basic Syntax o NOTE A minus sign has a different significance depending on its usage When used with one operand it indicates that the twos complement of the operand is to be formed When the minus sign is found between two operands the twos complements of the second operand are added to the first Division is unsigned integer division the result of division is a positive integer Use the modulus operator 96 to get the remainder of a division The shift operators perform logical unsigned shifts Zeros are shifted in from the left during right shifts and in from the right during left shifts Relational Operators Relational operators compare two items in an expression Expressions formed with relational operators produce a Boolean true or false value Table 1 5 lists the relational operators Table 1 5 Relational Operators Operators Description equal l not equal lt less than lt less than or equal gt greater than gt greater than or equal All relational operations are unsigned For example the expression 0 gt 4 is true since the complement of 0 is 1111 as
138. lect 0 amp a Assume select is equal to 0 s1 0 and sO 0 so a true value is produced The true is then ANDed with the set a on a bit by bit basis which in effect sets the product term to a If select were not equal to 0 the relational expression inside the parentheses would produce a false value This value when ANDed with anything would give all zeroes ABEL HDL Reference Manual 116 Equations The other product terms in the equation work in the same manner Because select takes on only one value at a time only one of the product terms pass the value of an input set along to the output set The others contribute O bits to the ORs Test Vectors The test vectors for this design are specified in terms of the input output and select sets Note that the values for a set can be specified by decimal numbers and by other sets The constants H and L used in the test vectors were declared as four bit sets containing all ones or all zeroes module Mux12T4 ABEL HDL Reference Manual ou tput to to ou ou ou tput tput title 12 to 4 multiplexer a0 a3 pin 13 245 b0 63 pin 552385 c0 c3 pin Ou 18 s1 s0 pin Tes LO yOcia pin 14 17 H LET I Ts L 0 0 0 0 X VOCE select sl sO y y3 y0 a a3 a0 b D3 50 al 3 2 COG equations when select 0
139. ll dot extension equations for a given output signal must be located in the ABEL HDL module in which the signal is defined No references to the signal s dot extensions can be made outside of the ABEL HDL module n NOTE When you instantiate a lower level module in a higher level source any signal attributes explicit or implicit are inherited by the higher level source signals that map to the lower level signals Do not specify ISTYPEs for instantiated signals ABEL HDL Reference Manual 220 Interface lower level Unlisted Signals If you do not list some signals of the lower level module in the interface statement the following rules apply Unlisted Pins Are The Compiler Interprets Them As Inputs or Errors Bidirectionals with OE Outputs No Connects NC and they can be removed Feedback outputs Nodes in the upper level source following the naming convention instance_name node_name Examples The following interface statement declares inputs ce ar and clk giving default values for two of them and outputs q3 through q0 module cnt4 interface ce 1 ar 1 c1k gt q3 q0 Specifying default values allows you to instantiate cnt4 without declaring the ce and ar inputs in the upper level source If you do not declare these inputs they are replaced with the constants 1 and 0 respectively Since these constants may affect optimization you may need to re optimize the lower level mod
140. lower level module with Functional_block declarations NOTE Hierarchy declarations are not required when instantiating an ABEL HDL module in an ispEXPERT System schematic For instructions on instantiating lower level modules in schematics refer to your Schematic Entry Reference Manual Instantiating a Lower level Module in an ABEL HDL Source Identifying I O Ports in the Lower level Module The way to identify an ABEL HDL module s input and output ports is to place an INTERFACE statement immediately following the MODULE statement The INTERFACE statement defines the ports in the lower level module that are used by the top level source You must declare all input pins in the ABEL HDL module as ports and you can specify default values of 0 1 or Don t care You do not have to declare all output pins as ports Any undeclared outputs become No Connects or redundant nodes Redundant nodes can later be removed from the designs during post link optimization The following source fragment is an example of a lower level INTERFACE statement module lower interface a 0 d3 d0 7 gt z0 z7 title example of lower level interface statement This statement identifies input a d3 d2 d1 and dO with default values and outputs z0 through z7 For more information see Interface lower level on page 219 ABEL HDL Reference Manual 61 Hierarchy in ABEL HDL Specifying Signal Attributes Attributes
141. manner Q1 CLK Clock Register clocked from input Q1 D QI1 Q Preset D type f f used for register In this form of the design specifying the D input to a D type flip flop and specifying feedback directly from the register restricts the device architectures in which the design can be implemented Furthermore the equations describe only the inputs to and feedback from the flip flop and do not provide any information regarding the configuration of the actual output pin This means the design will operate quite differently when implemented in a device with inverted outputs versus a device with non inverting outputs To maintain the correct pin behavior using detailed equations one additional language element is required a buffer attribute or its complement an invert attribute The buffer attribute ensures that the final implementation in a device has no inversion between the specified D type flip flop and the output pin associated with Q1 For example add the following to the declarations section Ol pin istype buffer ABEL HDL Reference Manual 67 Pin to pin vs Detailed Descriptions for Registered Designs Detailed Descriptions Designing for Macrocells One way to understand the difference between pin to pin and detailed description methods is to think of detailed descriptions as macrocell specifications A macrocell is a block of circuitry normally but not always associated with a device s I O pin Fig
142. mp load q fb amp load Fragment 2 truth_table a q fb load gt q o OF 9g uy ee ahs Doo deg Ul ee 05 Lor OOF Qs gt As gs 1 0 gt 0 0r Oris Tv Oe L y D ur sn ls Or ay dg T gt 0 ELE gt Ey Ly ie tS ES As an example the following truth table defines an exclusive OR function with two inputs A and B one enable en and one output C TRUTH TABLE gt C gt X don t care w enab off e gt 0 1 A en 5024 1 0 La D D ON ON oS e n Module Equations State diagram Dcset led1 abl led7 abl ABEL HDL Reference Manual 253 Wait Wait Syntax WAIT lt integer gt Use This keyword presents the relative time delay which effects the test vectors directly following the WAIT statement It can be used in the MACRO block only when this Macro is used in the Test_vectors block The default time unit is nano second Example wait 10 LO 0 0 gt 0 wait 40 1 1 0 gt 0 See Also Test vectors Cycle flicker abl ABEL HDL Reference Manual 254 When Then Else When Then Else Syntax WHEN condition THEN element expression ELSE equation Or WHEN condition THEN equation ELSE equation Purpose Use The WHEN THEN ELSE statement is used in equations to describe a logic function condition Any valid expression element An identif
143. mplemented with high level equations Design Specification The comparator as shown in Figure 4 12 compares the values of two four bit inputs A0 A3 and BO B3 and determines whether A is equal to not equal to less than or greater than B The result of the comparison is shown on the output lines EQ GT NE and LT AD Al A2 A3 po EQ B1 GT B2 NE B3 LT Figure 4 12 Block Diagram 4 bit Comparator Design Method Figure 4 13 and Figure 4 14 show the simplified block diagram and source file listing for the comparator The inputs A0 A3 and BO B3 are grouped into the sets A and B YES and NO are defined as 1 and 0 to be used in the test vectors The equations section of the source file contains the following equations ABEL HDL Reference Manual EQ A B NE A B GT A gt B LT A gt B A B 125 Equations A EQ GT B HE LT Figure 4 13 Simplified Block Diagram 4 bit Comparator You could also use the following equations for the design of this comparator However many more product terms are used EQ A B NE A B GT A gt B LT A lt B The first set of equations takes advantage of product term sharing while the latter set requires a different set of product terms for each equation For example the equation NE A B uses the same 16 product terms as the equation EQ A B thereby reducing the number o
144. n or block identifying the next state optionally followed by WITH transition equations A CAUTION IF THEN ELSE is only supported within a STATE DIAGRAM description Use WHEN THEN ELSE for equations ABEL HDL Reference Manual 214 If Then Else n NOTE Equation Blocks used within a conditional expression such as IF THEN CASE or WHEN THEN results in logic functions that are logically ANDed with the conditional expression that is in effect The expression following the IF keyword is evaluated and if the result is true the machine goes to the state indicated by the state exp following the THEN keyword If the result of the expression is false the machine jumps to the state indicated by the ELSE keyword Any number of IF statements may be used in a given state and the ELSE clause is optional The indenting and formatting of an IF THEN ELSE statement is not significant breaking a complex transition statement across many lines and indenting improves readability IF THEN ELSE statements can be nested with GOTO CASE and WITH statements IF THEN ELSE and CASE statements can also be combined and nested Chained IF THEN ELSE Statements Any number of IF THEN ELSE statements can be chained but the final statement must end with a semicolon The chained IF THEN ELSE statement is intended for situations where the conditions are not mutually exclusive The CASE statement more clearly expresses the same functi
145. nal Istype attributes The ISTYPE statement defines attributes characteristics of signals for devices with programmable characteristics or when no device and pin node number has been specified for a signal Even when a device has been specified using attributes will make it more likely that the design operates consistently if the device is changed later ISTYPE can be used after pin or node declarations Attributes may be entered in uppercase lowercase or mixed case letters Table 1 9 summarizes the attributes Each attribute is discussed in more detail in Chapter 5 Language Reference under Istype Table 1 9 Attributes Arch Dot Ext Indep Description butter No Inverter in Target Device collapse Collapse remove this signal com Y Combinational output de V Unspecified logic is don t care invert Inverter in Target Device keep Do not collapse this signal from equations 1 neg Y Unspecified logic is 1 pos Y Unspecified logic is 0 retain V Do not minimize this output Preserve redundant product terms 3 reg V Clocked Memory Element tregua D Flip flop Clocked Memory Element reg g D Flip flop Gated Clock Memory Element reg JE JK Flip flop Clocked Memory Element reg sr SR Flip flop Clocked Memory Element reg_t T Flip flop Clocked Memory Element xor XOR Gate in Target Device ABEL HDL Reference Manual 51 Declarations 1 If neither kee
146. nce Manual 113 Equations module decode decode abl title memory decode A15 A14 A13 A12 A11 A10 pin ROM1 IO ROM2 DRAM pin istype com H L X er qoo Xs Address A15 A14 A13 A12 A11 A10 X X X X X X X X X X equations DRAM Address lt hDFFF IO Address gt hE000 amp Address lt hE7FFP ROM2 Address gt hF000 amp Address lt hF7FFP ROM1 Address gt hF800 test vectors Address gt ROMI1 ROM2 IO DRAM h0000 gt tl d d L l h4000 gt H H H L h8000 gt H H H L hc000 H H H L hE000 gt e Ate T H 1 hE800 gt H H H H 1 hF000 gt E Ep H H J hF800 gt b die E H J end Figure 4 3 Memory Address Decoder Source File Test Vectors In this design the test vectors are a straightforward listing of the values that must appear on the output lines for specific address values The address values are specified in hexadecimal notation 12 to 4 Multiplexer The following describes the implementation of a 12 input to 4 output multiplexer using high level equations ABEL HDL Reference Manual 114 Equations Design Specification Figure 4 4 shows the block diagram for this design The multiplexer selects one of the four inputs and routes that set to the output The inputs are a0 a3 b0 b3 and c0 c3 The outputs are yO y3 The routi
147. ncluded in the source file if arg1 and arg2 are not identical Examples ifniden A abcd A device P16R8 A device declaration for a P16R8 is made if the actual argument substituted for A is not identical to abcd ABEL HDL Reference Manual 187 Include Include Directive Include Include Directive Syntax INCLUDE filespec Use filespec A string specifying the name of a file Include causes the contents of the specified file to be placed in the ABEL HDL source file The inclusion begins at the location of the Include directive The file specification can include an explicit drive or path specification that indicates where the file is found If no drive or path specification is given the default drive or path is used Examples INCLUDE macros abl file specification INCLUDE incs macros inc DOS paths require 2 slashes See Also Library ABEL HDL Reference Manual 188 Irp Indefinite Repeat Directive Irp Indefinite Repeat Directive Syntax IRP dummy arg arg arg block Use dummy_arg A dummy argument arg An actual argument or a dummy argument name preceded by a block A block of text rp causes the block to be repeated in the source file n times where n equals the number of arguments contained in the parentheses Each time the block is repeated the dummy argument takes on the value of the next successive argument Examples QIRP A 1
148. nd required declarations section The Const directive defines internal constants inside macros Constants defined with Const override previous constant declarations You cannot use Const to redefine an identifier that was used earlier in the source file as something other than a constant for example a macro or pin Examples CONST count count 1 See Also Constant Declarations Constants in Chapter 1 Language Structure ABEL HDL Reference Manual 176 Dcset Don t Care Set Dcset Don t Care Set Syntax DCSET Use ABEL HDL uses don t care conditions to help optimize partially specified logic functions Partially specified logic functions are those that have less than 2n significant input conditions where nis the number of input signals The Dcset directive allows the optimization to use either 1 or O for don t cares to optimize these functions A CAUTION The Dcset directive overrides Istype attributes dc neg and pos See Also Onset Istype dc and Assignment Operators Truth_table Precautions for Using Don t Care Optimization in Chapter 2 Design Considerations ABEL HDL Reference Manual 177 QDcstate State Output Don t Cares Dcstate State Output Don t Cares Syntax DCSTATE Use When Dcstate is specified all unspecified state diagram states and transitions are applied to the design outputs as don t cares You must us
149. ng of inputs to outputs is straightforward a0 or bO or CO is routed to the output yO a1 or b1 or c1 is routed to the output y1 and so on with the remaining outputs The select lines sO and s1 control the decoding that determines which set is routed to the output ao al az ad bo y bi yl ba yz b3 v c cl cz od s s0 Figure 4 4 Block Diagram 12 to 4 Multiplexer ABEL HDL Reference Manual 115 Equations Design Method Figure 4 5 shows a block diagram for the same multiplexer after sets have been used to group the signals All of the inputs have been grouped into the sets a b and c The outputs and select lines are grouped into the sets y and select respectively This grouping of signals into sets takes place in the declaration section of the source file listed in Figure 4 6 When the sets have been declared specification of the design is made with the following four equations that use WHEN THEN statements when select 0 then y a when select 1 then y b when select 2 then y c when select 3 then y c The relational expression inside the parentheses produces an expression that evaluates to true or false value depending on the values of sO and s1 select Figure 4 5 Simplified Block Diagram 12 to 4 Multiplexer In the first equation this expression is then ANDed with the set a which contains the four bits a0 a3 and could be written as y se
150. nnect Wire Connects the outputs of one instance of a lower level module to another instance s inputs InstanceO port instance port Examples module counter cnt4 interface ce ar clk q0 q3 cnt4 s top level interface declaration CNTO CNT3 functional block cnt4 Four instances of cnt4 Clk AR CE pin Q0 03 pin equations CNTO clk ar ce Clk AR CE Connecting to Clk AR and CE inputs CNTO q0 q3 00 03 Connecting to Q0 03 outputs end Figure 5 10 shows how the above ABEL HDL file wires the upper level source s signals to the lower level module s ports Note that the above file instantiates four instances of cnt4 but only one CNTO is wired ABEL HDL Reference Manual 209 Functional_block Overriding Default Values You can override the default values given in a lower level module s interface statement by specifying default equations in the higher level source For example if you have specified a default value of 1 for the signal ce in interface cnt4 but in instance CNTO you want ce to be 0 you would write CNTO ce 0 This equation overrides the 1 with a O If you override the default values you may want to re optimize the post linked design Figure 5 10 Wiring of CNTO Unused Outputs No Connects If you do not want to use a lower level module s outputs specify them as No Connects NC by not wiring up the port to a physical pin For example to
151. nodes 62 Dc 225 attribute 225 dc abl 85 Dc set 84 and optimization 85 Decimal 22 Declarations active low 74 constants 169 device 204 fuses 211 keyword 203 macro 228 node 233 pin 235 signal 50 structure 46 Declared equations vs macros 228 decode abl 114 Default values for lower level source signals 217 supported values 221 Design considerations 60 Detail descriptions designing for macrocells 68 example dot extensions 83 example inverting 70 example non inverting 70 when to use 72 detail1 abl 82 detail2 abl 83 Device keyword 204 Device kits passing information to 237 Devices radix 194 changing base numbering system 194 declaring fuse states 211 programmable polarity 76 Directives alternate 174 carry 175 const 176 dcset 177 dcstate 178 exit 179 Qexpr 180 if 181 ifb 182 ifdef 183 ifiden 184 ifnb 185 ifndef 186 ifniden 187 include 188 irp 189 irpc 190 message 191 onset 192 page 193 repeat 195 setsize 196 standard 197 if blank 182 if defined 183 if identical 184 if not blank 185 if not defined 186 if not identical 187 Division 25 ABEL HDL Reference Manual 263 Index Don t cares dcset 177 Dot extension example detail 83 Dot extensions 158 COM 79 D 79 ext 158 FB 79 PIN 79 Q 79 and architecture independence example 80 and detail descriptions 82 and feedback 79 drawings of 167 example detail 82 for flip flo
152. ns on Sets wc ssc aussa aeaaaee 39 ABEL HDL Reference Manual 4 Arguments and Argument Substitution 0 000 eee 41 Spaces n AJUMOSE carga ni eaea A Ada 42 Argument Guidelines ia A A A A dog Ro PC E 42 Basie A A aii Ree c id dd 43 ONE X co eas ka en a ee sk UK ORCI AUDIAT E E E a Ute pU A 43 dor DIE CP ENTRE ET E T E T TT TT QUO UT T TTL PIQUE CLP mee ee ae 43 Logic Description caesum Rm mE RRRE Rm RR AAA E 45 Test VACIO SECON sica rar ds de A ed ia aa aa ei 45 NA eee eae E ERR 45 Other Ee ek ak hn kph ba Oh ee bok ONS Re ee eee eo OS one eRe oes 45 Gur AAA CU A a A Ghee BO AAA IA Oe eas 46 e EMI oe S II TITIUS ean once anaes 46 OG E E MENTRE E TS oh dudes TOT TUTTI TU A A EE E E E 46 Su salina aa aues Lon daban id e a i dora dd E mauus C Ree orita anus eae drap do di d 46 EE LN scum bh A AS E apa HO Rie A deae e OUR 46 Declarations FOP Kk qd alc Ph be eee RARA EDGE IER e hdd RR a 47 Device Lun EN usui ud ae d oC OR de da COUR GTC o Ra RE der KEE ded D ae D ee e a 47 aa DSC ETC 47 iterace Declarations 144 a9 xb bpra dua kuke CR xd E RR RC qa uds rau dd acu 4 47 Functional_block Statement io dee ee ck oh chek xS Au Rm ober A RE RE E 48 Example of Functional Block Instantiation iss s Rr RR RC 49 coup e er nm FPE 50 o Li d dA cp ER DEO Cw edet d Ed ORC OR ER a do etd o e UR 50 Node Declarations ille RR RR RR RR Rr 50 PIES ASSIM usen daas da d End aded ER Rhet da
153. nt 1 is converted to a set in the second the 1 is treated as a single bit Equation 1 The first operation is a b amp 1 so 1 is converted to a set 0 1 x1 yl a b 1 amp d su Tar I e 1 amp d sube b amp 0 1 itla e Bro TN evd Du b od o 0 amp d bow d be xl 0 yl b d Equation 2 The first operation is 1 amp d so 1 is treated as a single bit x2 y2 1 8 d la b equ e ar b d amp Ta b d amp a d amp b x2 a id yv2 b d If you are unsure about the interpretation of an equation try the following m Fully parenthesize your equation Errors can occur if you are not familiar with the precedence rules in Table 1 7 m Write out numbers as sets of 1s and Os instead of as decimal numbers If the width is not what you expected you will get an error message ABEL HDL Reference Manual 40 Basic Syntax Arguments and Argument Substitution Variable values can be used in macros modules and directives These values are called the arguments of the construct that uses them In ABEL HDL a distinction must be made between two types of arguments actual and dummy Their definitions are given here Dummy argument An identifier used to indicate where an actual argument is to be substituted in the macro module or directive Actual argument The argument value used in the macro directive or module The actual argument is substituted for the dummy
154. nt declaration section of a module The declaration is Addr A15 A14 A13 which declares the constant set Addr The equation Chip_Sel Addr 1 0 1 is functionally equivalent to Chip Sel A15 A14 A13 ABEL HDL Reference Manual 34 Basic Syntax If Addr is equal to 1 0 1 meaning that A15 1 A14 0 and A13 1 then Chip Sel is set to true The set equation could also have been written as Chip_Sel Addr 5 because 101 binary equals 5 decimal In the example above a special set with the high order bits of the 16 bit address was declared and used in the set operation The full address could be used and the same function arrived at in other ways as shown below Example 1 declare some constants in declaration section Addr a15 a0 X X Simplify notation for don t care constant Chip Sel Addr 1 0 1 X X X X X X X X X X X X Example 2 declare some constants in declaration section Addr al5 a0 X X Chip Sel Addr gt HAO000 Addr lt HBFFF Both solutions presented in these two examples are functionally equivalent to the original Boolean equation and to the first solution in which only the high order bits are specified as elements of the set Addr a15 a14 a13 Set Assignment and Comparison Values and sets of values can be assigned and compared to a set Supported set operations are given in Table 1 8 For example sigset 1 1 0 amp 0
155. ny spaces blanks in actual arguments are passed to the expression In most cases spaces do not affect the interpretation of the macro The exception is in functions that compare character strings such as IFIDEN and IFNIDEN For example the macro iden macro a b ifiden a b message they are the same compares the actual arguments and prints the message if they are identical If you enter the macro with spaces in the actual arguments iden 01 01 The value is false because the space is passed to the macro Argument Guidelines m Dummy arguments are place holders for actual arguments m A question mark preceding the dummy argument indicates that an actual argument is to be substituted m Actual arguments replace dummy arguments before the source file is checked for correctness m Spaces in actual arguments are retained Further discussion and examples of argument use are given in Chapter 5 Language Reference under Module Macro and Directive Directives ABEL HDL Reference Manual 42 Basic Structure Basic Structure Header ABEL HDL source files can contain independent modules Each module contains a complete logic description of a circuit or subcircuit Any number of modules can be combined into one source file and processed at the same time This section covers the basic elements that make up an ABEL HDL source file module A module can be divided into five sections m Header Dec
156. o allows you to use architecture independent simulation The following rules should be kept in mind when you are using feedback No Dot Extension A feedback signal with no dot extension for example count count 1 results in pin feedback if it exists in the target device If there is no pin feedback register feedback is used with the value of the register contents complemented normalized if needed to match the value observed on the pin FB Extension A signal specified with the FB extension for example count count fb 1 results in register feedback normalized to the pin value if a register feedback path exists If no register feedback is available pin feedback is used and the fuse mapper checks that the output enable does not conflict with the pin feedback path If there is a conflict an error is generated if the output enable is not constantly enabled COM Extension A signal specified with the com extension for example count count com 1 results in OR array pre register feedback normalized to the pin value if an OR array feedback path exists If no OR array feedback is available pin feedback is used and the fuse mapper checks that the output enable does not conflict with the pin feedback path If there is a conflict an error is generated if the output enable is not constantly enabled PIN Extension If a signal is specified with the PIN extension for example count count pin 1 the pin
157. o oococccoocccnrnr 70 When to Use Detailed Descriptions 0 000 eee 72 Using for Alternative Flip flop Types Liisensua akku RR dE 72 Using Aclve ow DonargoliB asace ce beeen Sh srda ddad ir 74 xo R9 A ew Tp RS 76 ala Gomrol wiih IDA La idco doro deor ded Ebo Rob GR HES decal ded rR ORS 77 A A O EEEE he eR Obs EER 78 Feedback Considerations Using Dot Extensions 020 00 cee eee 79 Dot Extensions and Architecture independence 000 eee eee tees 80 Dot Extensions and Detail Design Descripti0NS oo ooooooocooonono 82 Eee e AS 84 Exclusive OR ES a qa dede dea RED Ge OR A AAA A A ARA AAA 86 COMA OTI cierra Ed Cue de oi di 86 Using XOR Operators in Equations lt ci cecce cher eecd rra 86 Using Implied XORs in Equations naana aaan 87 Using XORs for Flip flop Emulation n a annaa anaa 87 ABEL HDL Reference Manual 6 uie qu cR TN wee TOT OT CERRO DP 90 Use Identifiers Rather Than Numbers for States oooooccoocococnono 90 Powerup Register States a ics ee depen Ai OR I EROR Ah A UR RC CU di 92 Unsatisfied Transition Conditions ce quedo d dC EORR RR Ce e Reo GE Eo c e 92 o Re ee kee edie teense hh 92 Jihar MIP das eed A A ale de Rid e qi 93 Precautions for Using Don t Care Optimization llli 94 Number Adjacent States for One bit Change 2c cee ee ees 98 Use State Register Outputs to Identify States ooooooommoooo 99
158. obtained through the use of equations truth tables and state diagrams and affect device simulation accordingly ABEL HDL has a limit of 128 fuses per statement due to the set size limitations ABEL HDL Reference Manual 211 Fuses Examples FUSES 3552 1 3478 3491 Hff ABEL HDL Reference Manual 212 Goto Goto Syntax GOTO state_exp Purpose The GOTO statement is used in the state_diagram section to cause an unconditional transition to the state indicated by state_exp Use state_exp An expression identifying the next state optionally followed by WITH transition equations GOTO statements can be nested with IF THEN ELSE and CASE statements Examples GOTO 0 goto state 0 GOTO x y goto the state x y See Also State diagram Case If then else With ABEL HDL Reference Manual 213 If Then Else If Then Else Syntax IF exp THEN state_exp ELSE state_exp Chained IF THEN ELSE IF expr THEN state_exp ELSE IF exp THEN state_exp ELSE state_exp Nested IF THEN ELSE IF exp THEN state_exp ELSE IF exp THEN IF exp THEN state_exp ELSE state_exp ELSE state_exp Nested IF THEN ELSE with Blocks IF exp THEN IF exp THEN state_exp IF exp THEN state_exp ELSE state_exp Purpose The if then else statements are used in the state_diagram section to describe the progression from one state to another Use exp An expression state exp An expressio
159. of the newly drawn card to the existing hand and indicates an ace to the state machine 2 Abinary to binary coded decimal BCD converter which takes in the five bit binary score and converts it to two digits of BCD for the digital display 3 The blackjack controller a state machine that contains the game logic This logic includes instructions that determine when to add a card value when to count an ace as 1 and when to count an ace as 11 ABEL HDL Reference Manual 134 Combined Logic Descriptions Circuits that are a straightforward function of a set of inputs and outputs are often most easily expressed in equations the adder is such a circuit The subdesign MUXADD for the adder function includes three elements a multiplexer the adder itself and a comparator The multiplexer selects either the value of the newly dealt card or one of the two fixed values used for the ace ADD10 or SUB10 The adder adds the value selected by the multiplexer to the previous score when triggered by the clock signal ADDCLK The comparator detects when an ace is present and passes this information on to the blackjack controller BJACK Outputs that do not follow a specific pattern are most easily expressed as truth tables This is the case with the binary to BCD converter that is identified in the schematic as BINBCD This subdesign converts five bits of binary input to BCD output for two digital display elements The following text describes the
160. omparator and binary to bcd decoder for Blackjack Machine The 5 bit binary 0 31 Score is converted into two BCD outputs The integer division an d the modulus operator are used to extract the individual digits from the two digit score Score 10 will yield the units and Score 10 will yield the tens The GT16 and LT22 outputs are for the state machine controller S4 S0 pin score S4 S0 LT22 GT16 pin istype com D5 D4 pin istype com bed2 D5 D4 D3 D0 pin istype com bedl D3 D0 Digit separation macros binary 0 scratch variable clear macro a const a 0 inc macro a const a a 1 equations LT22 score lt 22 Bust GT16 score gt 16 Hit Stand test vectors edited truth table score gt bcd2 bcdl O gt oram MC 000 1001 C0 P2 2S I d VV OO QU QC CO o 000 1001 WN ES Figure 4 21 Source File 4 bit Counter with 2 input Mux ABEL HDL Reference Manual 140 Combined Logic Descriptions 10 0 TIY gt y 1 J 12 gt 2u s 13 gt y 3 J 14 gt 4 TI lt gt y 0 16 gt j 6 que cu 7 18 gt 1 8 1 19 gt T y 91s 20 2 4 Oe Ji 2J 2 ED 22 cx 2 ip 52 its 23 gt Da SI 24 gt 2 4 25 gt Zw s DRG 26 2 7 6 27 gt Las Ob 28 gt 2p Be E 29
161. on as chained mutually exclusive IF THEN ELSE statements Chained IF THEN ELSE statements can provide multiway branching transition logic For example multiple IF THEN ELSE statements can be chained to describe a three way branch in the following manner STATE SO IF address lt h0400 THEN SO ELSE IF address lt hE100 THEN S2 ELSE Sl Examples if A B then 2 if A equals B goto state 2 if x y then j else k if x y is not 0 goto j else goto k if A then b c if A is true non zero goto state b c ABEL HDL Reference Manual 215 See Also Chained IF THEN ELSE ifa else if b else xf then 1 then 2 then 3 else 0 Nested IF THEN ELSE with Blocks ELSE IF Hold THEN TF EUR State3 ES ET IF Error IH TH EN S EN S ta tel ta Nested IF THEN ELSE Statements A complex state transition could be written with nested transitions in the following manner STATI E SO CASE select seleci selec ct ct select ENDCASE State diagram Case Goto With I W N G2 If Then Else IF address h0100 THEN S16 LSE address gt hE100 THEN S17 ELSE S07 S2 IF address hE100 THEN IF reset THEN 5S3 ELSE S0 ELSE S17 S0 ABEL HDL Referen
162. on with the signals surrounded by brackets and separated by commas see Sets in Chapter 1 Language Structure ABEL HDL Reference Manual 251 Truth_table The syntax shown in the first form defines the format of a truth table with simple combinational outputs The values of the inputs determine the values of the outputs The second form describes a format for a truth table with registered outputs The symbol preceding the outputs distinguishes these outputs from the combinational outputs Again the values of the inputs determine the values of the outputs but now the outputs are registered or clocked they will contain the new value as determined by the inputs after the next clock pulse The third form is more complex defining a table with both combinational and registered outputs It is important in this format to make sure the different specification characters and are used for the different types of outputs Truth Table Format The truth table is specified according to the form described within the parentheses in the header The truth table is a list of input combinations and resulting outputs All or some of the possible input combinations may be listed All values specified in the table must be constants either declared numeric or the special constant x Each line of the table each input output listing must end with a semicolon The header defines the names of the inputs and outputs Th
163. ou to specify a Boolean expression that is to be factored out of and XORed with the sum of products reduced equations This factoring can result in smaller reduced equations when the design is implemented in a device featuring XOR gates ABEL HDL Reference Manual 57 Test Vectors Section Test Vectors Section Test Vectors Keyword test_vector Test_vectors note inputs outputs invalues gt outvalues Test vectors specify the expected operation of a logic device by defining its outputs as a function of its inputs Trace Statement Keyword trace Trace inputs gt outputs The TRACE statement limits which inputs and outputs are displayed in the simulation report End Statement Keyword end End module name The END statement ends the module and is required ABEL HDL Reference Manual 58 Other Elements Other Elements Directives Keyword directive directive options Directives provide options that control the contents or processing of a source file Sections of ABEL HDL source code can be included conditionally code can be brought in from another file and messages can be printed during processing Some directives take arguments that determine how the directive is processed These arguments can be actual arguments or dummy arguments preceded by a question mark The rules applying to actual and dummy arguments are presented under Arguments and Argument Substitution on page 41 Avai
164. outputs is designed for implementation in a simple PLD A15 ROM1 A14 ROM2 A13 10 A12 DRAM A11 A10 FFFF F800 F000 E800 E000 0000 Figure 4 1 Block Diagram Memory Address Decoder The address ranges associated with each section of memory are shown below These address ranges can also be seen in the source file in Figure 4 3 Memory Section Address Range hex DRAM 0000 DFFF I O E000 E7FF ROM2 F000 F7FF ROM1 F800 FFFF ABEL HDL Reference Manual 112 Equations Design Method Figure 4 2 shows a simplified block diagram for the address decoder The decoder is implemented with equations employing relational and logical operators as shown in Figure 4 3 Significant simplification is achieved by grouping the address bits into a set named Address The ten address bits that are not used for the address decode are given no connect values in the set indicating that the address in the overall design that beyond the decoder contains 16 bits but that bits 0 to 9 do not affect the decode of that address and are not monitored In contrast defining the set as Address A15 A14 A13 A12 A11 A10 ignores the existence of the lower order bits Specifying all 16 address lines as members of the address set allows full 16 bit comparisons of the address value against the ranges shown above ROM1 ROM2 Address y DRAM TT Iq Figure 4 2 Simplified Block Diagram Memory Address Decoder ABEL HDL Refere
165. ove the readability of your equations An equation block is enclosed in braces and is supported wherever a single equation is supported When used within a conditional expression such as IF THEN CASE or WHEN THEN the logic functions are logically ANDed with the conditional expression that is in effect See Also If Then Else on page 214 When Then Else on page 255 and Case on page 199 Multiple Assignments to the Same Identifier When an identifier appears on the left side of more than one equation the expressions assigned to the identifier are first ORed together and then the assignment is made If the identifier on the left side of the equation is complemented the complement is performed after all the expressions have been ORed Equations Found Equivalent Equation A B A C A BHC A B A C amp D A B C amp D A IB A IC A IB C IA B IA C A WB C IA B A IC A C IB IA B IA C A ID A IE A ID IE B C When the complement operator appears on the left side of multiple assignment equations the right sides are ORed first and then the complement is applied ABEL HDL Reference Manual 32 Basic Syntax Sets A set is a collection of signals and constants Any operation applied to a set is applied to each element in the set Sets simplify ABEL HDL logic descriptions and test vectors b
166. ow Latch Enable Isbype Teg g irivert DE SP CAP PRESET D D a CLK CE SA AR Q PIN CE CLK D Q X 0 0 0 o 1 1 1 1 A Last Figure 5 9 Detailed Dot Extensions for a Gated clock D Flip flop ABEL HDL Reference Manual 167 ext Dot Extensions Examples These equations precisely describe the desired circuit as a toggling D type flip flop that is clocked by the input Clock assuming ISTYPE reg D buffer Ol clk Ol D Clock 101 0 Preset Register preset 02 PR S amp IT Register reset O2 RE R amp T The same circuit can be described without ISTYPE buffer as Ql clk Clock Q1 Q1 FB Preset Q2 SET S amp T Q2 CLR R T 3 state Output Enables Output enables are described in ABEL HDL with the oe dot extension applied to an output signal name For example Ol oe enab The equation specifies that the input signal enab controls the output enable for an output signal named Q1 Za NOTE If you explicitly state the value of a fixed output enable you restrict the device fitters ability to map the indicated signal to a simple input pin instead of a three state I O pin See Also Istype Attribute Assignment in Chapter 1 Language Structure Feedback Considerations Using Dot Extensions in Chapter 2 Design Considerations ABEL HDL Reference Manual 168 Constant Declarations Constant Declarations S
167. p key code key none code entry X WITH which code enter which code enter key code sens off key code key none code entry Y WITH which code enter which code enter key code key pound key code key star error sens code sens off error ENDCASE which code enter from armed CASE key code key pound amp key code key star amp key code key none code entry X WITH which code enter which code enter key code key pound key code key star armed WITH which code enter which code enter key code key none code entry Y WITH which code enter which code enter ENDCASE ENDCASE Figure 3 7 State Machine Description without Intermediate Signals ABEL HDL Reference Manual 106 CPLD Design Strategies CASE enter_from_disarmed_ready CASE sensors_off amp key_numeric code entry X WITH which code enter sensors off amp key none code entry Y WITH which code enter key pound star error sensors off error ENDCASE enter from armed EN CASE key_numeric code_entry_ X WITH which code enter key pound star armed WITH which code enter key none code entry Y WITH which code enter ENDCASE DCASE which code enter which code enter which code enter which code enter which code enter F
168. p S3 X W inp Y WHt C Recursive macro references when a macro definition refers to itself are not supported and the compiler halts abnormally If errors appear after the first use of a macro and the errors cannot be easily explained otherwise check for a recursive macro reference by examining the listing file See Also Constant Declarations Arguments and Argument Substitution in Chapter 1 Language Structure ABEL HDL Reference Manual 231 Module Module Syntax MODULE modname dummy arg dummy arg Purpose The MODULE statement defines the beginning of a module and must be paired with an END statement that defines the module s end Use modname An identifier naming the module dummy arg Dummy arguments The optional dummy arguments allow actual arguments to be passed to the module when it is processed The dummy argument provides a name to refer to within the module Anywhere in the module where a dummy argument is found preceded by a the actual argument value is substituted Examples MODULE MY EXAMPLE A B C B In the module named MY EXAMPLE C takes on the value of A B where A and B contain actual arguments passed to the module when the language processor is invoked See Also Title Interface submodule End Arguments and Argument Substitution in Chapter 1 Language Structure ABEL HDL Reference Manual 232
169. p nor collapse is specified the compiler program can keep or collapse the signal as needed to optimize the circuit 2 The dc neg and pos attributes are mutually exclusive 3 The retain attribute only controls optimization performed by ABEL HDL Compile Logic To preserve redundant product terms you must also specify no reduction for the Reduce Logic and fitting place and route programs Constant Declarations Keyword id id expr expr A constant is an identifier that retains a constant value in a module and is specified with the sign Constant declarations must be in a declarations section or after a Const directive See Also Constants on page 19 Symbolic State Declarations The STATE_REGISTER and STATE declarations are made to declare a symbolic state machine name and to declare symbolic state names See Also State Descriptions on page 56 State_register Declarations Keyword state_register statereg_id State register Istype attributes State Declarations Keyword state state id state id State state value state value l ABEL HDL Reference Manual 52 Logic Description Macro Declarations Keyword macro macro id Macro dummy arg dummy arg block The MACRO declaration statement defines a macro Use macros to include functions in a source file without repeating the code Library Declaration Keyword library Librar
170. p types 161 no 79 not allowed across sources 217 pin to pin 163 Dummy arguments defining in module statement 232 E Else keyword 214 Emulation of flip flop 87 End keyword 205 Endcase 199 Equation polarity 77 Equations keyword 206 overview 31 when then else 206 255 XORs 86 Equations for flip flops 78 Equations of XORs 86 Examples 12 to 4 multiplexer using equations 114 3 state sequencer state machine 131 4 bit comparator equations 125 4 bit universal counter 118 5 bit adder 134 7 segment display decoder truth tables 128 adder 134 bidirectional 3 state buffer equations 122 binary to BCD converter 134 blackjack machine state machine 134 memory address decoder equations 112 multiplexer 134 Expressions 29 directive for 180 F Factors XOR 258 Feedback and dot extensions 79 merging 64 referencing across sources 217 Files including in source file 227 Files including in source file 188 Flip flops 93 and dot extensions 78 79 detail descriptions 72 D type 92 emulations with XORs 87 state diagrams 73 using for alternative flip flop types 72 Form feed 193 Functional block keyword 208 Fuses keyword 211 G Gated clock D flip flop dot extensions 161 Goto keyword 213 Greater than 25 H h 22 Header 46 249 Hexadecimal 22 Hierarchy 61 Hierarchy declarations creating multiple instances of a source 208 functional block 208 inheriting attributes 208 interface lower level 219 interface top l
171. per voltage 2 through 9 c Clock up edge low high transition Don t care condition Z Tri state value When you use a special constant it must be entered as shown in Table 1 1 Without the periods c is an identifier named C You can enter special constants in upper or lowercase Blocks are sections of text enclosed in braces and Blocks are used in equations state diagrams macros and directives The text in a block can be on one line or it can span many lines Some examples of blocks are shown below this is a block this is also a block and it spans more than one line A B C 0 1 1 0 ABEL HDL Reference Manual 19 Basic Syntax Blocks can be nested within other blocks as shown below where the block D A is nested within a larger block A BSC A C H g Blocks and nested blocks can be useful in macros and when used with directives See Macro Declarations on page 53 and in Chapter 5 Language Reference If you need a brace as a character in a block precede it with a backslash For example to specify a block containing the characters write MEL AF Using Blocks in Logic Descriptions Using blocks can simplify the description of output logic in equations and state diagrams and allow more complex functions than possible without blocks Blocks can improve the readability of your design Blocks are supported anywh
172. plied as a decimal value and the output count is a decimal value rather than a set of binary bits ABEL HDL Reference Manual 121 Equations Bidirectional 3 state Buffer A four bit bidirectional buffer with tri state outputs is presented here Simple Boolean equations are used to describe the function Design Specification Figure 4 9 shows a block diagram for this four bit buffer Signals AO A3 and BO B3 function both as inputs and outputs depending on the value on the select lines SO S1 When the select value the value on the select lines is 1 A0 A3 are enabled as outputs When the select value is 2 BO B3 are enabled as outputs The choice of 1 and 2 for select values is arbitrary For any other values of the select lines both the A and B outputs are at high impedance Output polarity for this design is positive B3 B El BO Ad AZ A AU Figure 4 9 Block Diagram Bidirectional 3 state Buffer ABEL HDL Reference Manual 122 Equations Design Method A simplified block diagram for the buffer is shown in Figure 4 10 The A and B inputs outputs are grouped into two sets A and B The select lines are grouped into the select set Figure 4 11 shows the source file that describes the design Select Figure 4 10 Simplified Block Diagram Bidirectional 3 state Buffer High impedance and don t care values are declared to simplify notation in the source file The equations section describes the full function of the
173. qadE RE Eds RR Re d dd 51 Constant Declarations ca cir Seen deta owe ed doe bb irud A sd dd e 52 Symbolic State Declarations iss EA RARA e CR OR RI D ee ee 52 State_register Declarations i ado oid bti aci HERE OC eRe ea 52 atate DE OI ua aisi KR Rd RC edits dca cod acaba e Je os 52 MISMO DESDE nnd eee avi eb Ed Read daba tow ted e iO hr a a es a i e Ide 53 Library Declaration 2 cauae nuire mma cak den Re poema dancers m dox a on 53 Looe eI currada ese dnd dowd redes a ee 53 LEER EE bade i X E XOU EAR OREL e IET GT ea Re UR Coe Ede od a 53 PAGS Lb A O O EA 55 pU Be feed dosh bk oe Ga a Rk AA 56 Stale Dos DNO rozar e dar de ae 56 e A A A 57 XOR FactorS 2i uua ace darn doo doe nan nde cie ba der Mee dead onan hme do db d d e ws Df Test Veciors OPIDO uota nox dece p der dg doe E ok dco a on aeq o dee D CR HC E DR SO Te n 58 D d c fea cea hed tee TETUR 58 Trace Statement uiis hos Roa C COR ra o ne GRAAL Ce p er o ROCA HER CC 58 Se cna radar betas dada ratas delia TCI 58 cher EII rra aa ARA a dd 59 e A II A 59 ABEL HDL Reference Manual 5 Chapter 2 Design Considerations 00 c cece eee eens 60 PIENO NE ASBLOMDL i ick dd d C b ihe ee yd tee ee heed Coo cb uoa bacca d 61 Instantiating a Lower level Module in an ABEL HDL Source ooooooooooo 61 Identifying I O Ports in the Lower level Module oooooooooo 61 Specifying Signal Attributes 0 00 2 ee 62 SUE Enables OE ciatesutaedp
174. r SP with Istype invert COM 4 A combinational feedback from the flip flop data input normalized to the pin value and used to distinguish between pin PIN and internal logic array COM feedback JB When on the left side of an equation D is the data input to a D type flip flop on the right side D is combinational feedback FB Y Register feedback FC Flip flop mode control Eu J input to a JK type flip flop B K input to a JK type flip flop ED Register load input LE Latch enable input to a latch LH Latch enable high to a latch mou J Output enable PIN 4 Pin feedback PR Register preset Synchronous or asynchronous Q Register feedback R R input to an SR type flip flop RE Register reset synchronous or asynchronous ABEL HDL Reference Manual 159 ext Dot Extensions Table 5 1 Dot Extensions Continued Dot Ext Pin to pin Description E S input to an SR type flip flop sere 4 A device independent synchronous register preset equivalent to SP with Istype buffer or SR with Istype invert SP Synchronous register preset SR Synchronous register reset am T input to a T type toggle flip flop 1 Example follows f Istype buffer or invert is specified the compiler converts these dot extensions to the equivalent detailed dot extension 3 Some fitters
175. r provides the basic syntax and structure of a design description in ABEL HDL For information on specific elements refer to Chapter 5 Language Reference You can write a source file using any editor that produces ASCII files you are not limited to the ABEL or ispEXPERT System Text Editor Summary This chapter contains information on the following topics m Introduction to ABEL HDL and to the idea of architecture independent and architecture specific logic descriptions m Basic syntax of a source file including Supported ASCII characters Identifiers and keywords Constants Blocks Comments Numbers Strings Operators expressions and equations Sets and set operation Arguments and argument substitution m Basic Structure of a design description including Header Declarations Logic description Test vectors End ABEL HDL Reference Manual 14 Introduction to ABEL HDL Introduction to ABEL HDL ABEL HDL is a hardware description language that supports a variety of behavioral input forms including high level equations state diagrams and truth tables The ABEL and the ABEL HDL compiler and supporting software functionally verify ABEL HDL designs through simulation The compilers then implements the designs in PLDs or CPLDs You can enter designs in ABEL HDL and verify them with little or no concern for the architecture of the target device Architecture independent design descriptions those that do not include
176. ration E CMOS GAL ispGAL ispLSI pDS pLSI Silicon Forest and UltraMOS are registered trademarks of Lattice Semiconductor Corporation Project Navigator is a trademark of Data I O Corporataion ABEL HDL is a registered trademark of Data I O Corporation Microsoft Windows and MS DOS are registered trademarks of Microsoft Corporation IBM is a registered trademark of International Business Machines Corporation Lattice Semiconductor Corporation 5555 NE Moore Ct Hillsboro OR 97124 503 681 0118 September 1998 ABEL HDL Reference Manual 2 Limited Warranty Lattice Semiconductor Corporation warrants the original purchaser that the Lattice Semiconductor software shall be free from defects in material and workmanship for a period of ninety days from the date of purchase If a defect covered by this limited warranty occurs during this 90 day warranty period Lattice Semiconductor will repair or replace the component part at its option free of charge This limited warranty does not apply if the defects have been caused by negligence accident unreasonable or unintended use modification or any causes not related to defective materials or workmanship To receive service during the 90 day warranty period contact Lattice Semiconductor Corporation at Phone 1 800 LATTICE Fax 408 944 8450 E mail applications latticesemi com If the Lattice Semiconductor support personnel are unable to solve your problem over the phone
177. re needed if you organize the state register bit values so one bit in the state register determines if the machine is in a state of interest Take for example the following sequence of states in which identification of the Cn states is required State Register Bit Values State Name Q3 Q2 Q1 A 0 0 0 B 0 0 1 C1 1 0 1 C2 1 1 1 C3 1 1 0 D 0 1 0 This choice of state register bit values allows you to use Q3 as a flag to indicate when the machine is in any of the Cn states When Q3 is high the machine is in one of the Cnstates Q3 can be assigned directly to an output pin on the device Notice also that these bit values change by only one bit as the machine cycles through the states as is recommended in the section above Using Symbolic State Descriptions Symbolic state descriptions describe a state machine without having to specify actual state values Symbolic state descriptions A symbolic state description is shown in Figure 2 16 ABEL HDL Reference Manual 99 a b clock pin N a reset s reset pin n X y pin istype com bs sregl state register S0 S3 state equations sregl clk clock state_diagram sregl state SO goto S1 with x a amp b y Oy state S1 if a amp b then S2 with x 0 state S2 x a amp b y 1 if a then Sl else S2 state 5S3 goto SO with x 1 y Say async reset S0 a reset sync reset S0 s reset end module SM State Machines inputs reset
178. rom the BJACK controller and is described with the following equations Score Data Score FB CarryIn CarryOut Data amp Score FB Data Score FB amp CarryIn Reset Clr In the above equations Score is the sum of Data the card reader output value of ten or value of minus ten Score the current or last calculated score and Carryln the shifted value of CarryOut described below The new value of Score appears at the SO through S4 outputs of MUXADD at the time of the AddClk pulse generated by the BJACK controller state machine ABEL HDL Reference Manual 136 Combined Logic Descriptions Before the occurrence of the AddClk clock pulse an intermediate adder output appears at combinatorial outputs labeled CO through C4 and defined as the set named CarryOut shown below A second set named Carryln defines the same combinatorial outputs as CarryOut but the outputs are shifted one bit to the left as shown below CarryIn C4 Cl 0 CarryOut X C4 C1 The set declarations define Carryln as CarryOut with the required shift to the left for application back to adder input At the time of the AddClk pulse from the BJACK controller CarryIn is added to Score and Data by an exclusive or operation The comparator portion of MUXADD is defined with is Ace Card 1 which provides an input to the BJACK controller whenever the value provided by the card reader is 1 Test Vectors
179. rs of the dc set as follows for f3 dc set of 3 00 1 o 1 JADE 0 0 0 0 1 G9 0 1 RO 1 C O ABEL HDL Reference Manual 84 Using Don t Care Optimization Expressed as a Karnaugh map the on set off set and dc set would appear as follows with ones indicating the on set zeroes indicating the off set and dashes indicating the dc set If the don t care entries in the Karnaugh map are used for optimization the function for f3 can be reduced to a single product term f3 i2 instead of the two f3 i3 amp i2 amp liO i2 amp i1 amp 10 otherwise required The ABEL HDL compiler uses this level of optimization if the Dcset directive or Istype dc is included in the ABEL HDL source file as shown in Figure 2 8 module dc 13 12 11 10 pin 3 EZ EL 50 pin istype dc com truth table i13 12 11 10 f3 f2 f1 f0 0 0 0 0 gt 0 0 0 1 0 0 0 1 gt 0 0 1 5 0 O 1 1 gt 0 1 1 1 0 r 1 gt A pos r 1 1 1 gt 1 1 1 O0 j s 0 gt 1 0 0 1 0 0 gt 1 0 0 Ol 0 0 0 gt 0 0 0 O end Figure 2 8 Source File Showing Don t Care Optimization This example results in a total of four single literal product terms one for each output The same example with no istype dc results in a total of twelve product terms
180. rt of the source file Device Declaration Keyword device device_id Device real_device The DEVICE declaration is optional and only one can be made per module It associates a device identifier with a specific programmable logic device Hierarchy Declarations Interface Declarations Top level Interface Declarations Keyword interface low level module name Interface inputs value outputs gt bidirs sse The INTERFACE keyword declares lower level modules that are used by the current module This declaration is used in conjunction with a FUNCTIONAL BLOCK declaration for each instantiation of a module When you instantiate a functional block you must map port names to signal names with equations See Functional block on page 208 for more information Lower level Interface Declarations Keyword interface Module module name Interface input set value output set bidir set Use the INTERFACE declaration in lower level modules to assign a default port list and input values for the module when instantiated in higher level ABEL HDL sources In the higher level source you must declare signals and sets in the same order and grouping as given in the interface statement in the instantiated module The and delimiters are used to indicate the direction of each port of a functional block ABEL HDL Reference Manual 47 Declarations A CAUTION Interface declarations cannot contain dot extensions
181. rter is implemented It is the function of the converter to accept the four lines of binary data generated by MUXADD and provide two sets of binary coded decimal outputs for two bcd display devices one to display the units of the current score and the other to display the tens The four bit output bcd1 DO D3 contains the units of the current score and is connected to the high order display digit The two bit output bcd2 D4 and D5 contains the tens and is fed to the low order display digit BINBCD also provides a pair of outputs to light the Bust and Hit LEDs Bust is lit whenever Score is 22 or greater while Hit is lit whenever Score is 16 or less Design Method BINBCD The design of BINBCD is shown in the source file of Figure 4 21 The design of the converter is easily expressed with a truth table that lists the value of Score inputs SO through S4 are declared as Score for values of bcd1 and bcd2 bcd1 and bcd2 are sets that define the outputs that are fed to the two digital display devices The truth table lists Score values up to decimal 31 The truth table represents a method of expressing the design manually You could use a macro to create a truth table in the following manner clear binary repeat 32 binary binary 10 binary 10 inc binary As indicated in Figure 4 21 and described in Test Vectors BINBCD this macro is used to generate the test vectors for the converter The generated Ist file
182. ruth_table Truth_table Syntax TRUTH_TABLE in ids gt out ids inputs gt outputs Or TRUTH TABLE in ids gt reg ids inputs reg outs or TRUTH_TABLE in_ids 1 gt reg ds gt out_ids inputs gt reg outs gt outputs Purpose Truth tables specify outputs as functions of input combinations in a tabular form Use in_ids Input signal identifiers out_ids Output signal identifiers reg_ids Registered signal identifiers inputs The inputs to the logic function outputs The outputs from the logic function reg_outs The registered clocked outputs gt gt Indicates the input to output function for combinational gt and registered gt outputs Truth tables are another way to describe logic designs with ABEL HDL and may be used in lieu of or in addition to equations and state diagrams A truth table is specified with a header describing the format of the table and with the table itself A semicolon is required after each line in the truth table The truth table header can have one of the three forms shown above depending on whether the device has registered or combinational outputs or both The inputs and outputs both registered and combinational of a truth table are either single signals or more frequently sets of signals If only one signal is used as either the input or output its name is specified Sets of signals used as inputs or outputs are specified in the normal set notati
183. s do not match The number is converted to binary and truncated or padded with zeros to match the width of the set The sequence of transformations is la b c 1 O 1 a amp 1 b amp 0 c amp 1 Lay 0 El The numbers are converted to binary ANDed together then truncated or padded ABEL HDL Reference Manual 37 Basic Syntax Example Equations select al5 a0 H80FF select signal is TRUE when the 16 bit address bus has the hex value 80FF Relational operators always result in a single bit sell sel0 a3 a0 gt 2 The width of sel and a are different so the 2 is expanded to four bits of binary to match the size of the a set Both sel1 and sel2 are true when the value of the four a lines taken as a binary number is greater than 2 The result of the comparison is a single bit result which is distributed to both members of the set on the output side of the equation out3 out0 in3 in0 amp enab If enab is TRUE then the values on inO through in3 are seen on the outO through out3 outputs If enab is FALSE then the outputs are all FALSE Set Operation Rules Set operations are applied according to Boolean algebra rules Uppercase letters are set names and lowercase letters are elements of a set The letters k and n are subscripts to the elements and to the sets A subscript following a set name uppercase letter indicates how many elements the set contains So A indicates that
184. s logic m Useonly dot extensions that are appropriate for CPLD designs You can find information about using dot extensions in the specific CPLD fitter user manuals m Use intermediate signals to create multi level logic to match CPLD architectures Declaring Signals The first step in creating a logic module for a CPLD is to declare the signals in your design In ABEL HDL you do this with PIN and NODE statements Pin PIN statements indicate external signals used as inputs and outputs to the functional block Pin numbers are optional in ABEL HDL and are not recommended for CPLDs since pin statements do not actually generate pins on the device package If you declare an external signal as a node instead of a pin the compiler may interpret the signal incorrectly and delete it Node NODE statements indicate internal signals not accessible by circuitry outside the functional block Signals declared as nodes are expected to have a source and loads For example Figure 3 1 shows a state machine as a functional block State bits S1 through S7 are completely internal all other signals are external ABEL HDL Reference Manual 102 CPLD Design Strategies FUNCTIONAL BLOCK ID 02 11 01 2 I3 State bits used internally only CLOCK RESET Figure 3 1 Hypothetical State Machine as a Functional Block Figure 3 2 shows the corresponding signal declarations The CLOCK RESET input and output signals must connect with circuitry out
185. s you to reduce the amount of logic required for processing large arithmetic functions by specifying how adders counters and comparators are generated The number generated by the expression indicates the maximum bit width to use when performing arithmetic functions For example for an 8 bit adder a Carry statement with an expression which results in 2 would divide the 8 bit adder into four 2 bit adders creating intermediate nodes This would reduce the amount of logic generated The statement carry 1 generates chains of one bit adders and comparators for all subsequent adder and comparator equations instead of the full look ahead carry equations normally generated This directive automatically generates additional combinational nodes Use different values for the Carry statement to specify the types of adders and comparators required for the design To specify that full lookahead carry should be generated the default if no Carry has been specified use the statement carry 0 Examples See Also carry 2 generate adder chain s8 s0 x a7 a0 x b7 b0 Constant Declarations Constants in Chapter 1 Language Structure ABEL HDL Reference Manual 175 Const Constant Declarations Const Constant Declarations Syntax CONST id expression Use id An identifier expression An expression Const allows new constant declarations to be made in a source file outside the normal a
186. set A contains k elements a 4 is the k 1 th element of set A a is the first element of set A ABEL HDL Reference Manual 38 Expression IAk Ak Ax OE Ak amp Bk Ak Bk Ak Bk Ax Bk Ak Bk Ak Bk Ak Bk Ak Bk Ak Bk Limitations Restrictions on Sets Basic Syntax Is Evaluated As ak lax 1 la1 IAk 1 ax OE ax 1 0E a1 OE ax amp bk ak 1 amp bici a1 amp bi ak bk ax 1 bici a1 b1 ax bx ax 1 bx 1 a1 b1 ax bx ax 1 bici a1 bi ak bk 8 ak 1 bici amp 8 a1 b1 ak bk ak 1 bk 1 4 a1 b1 Dk where dn is evaluated as an bn cn 1 cn is evaluated as an bn an amp Cn 1 bn amp Cn 1 CO is evaluated as 0 Ak Bk Ck where Cn is evaluated as lan bn cn 1 an amp bn amp cn 1 l 0 CO is evaluated as 0 If you have a set assigned to a single value the value will be padded with Os and then applied to the set For example A1 A2 A3 is equivalent to Al A2 A3 0 0 1 which may not be the intended result If you want 1 assigned to each member of the set you would need binary 111 or decimal 7 ABEL HDL Reference Manual 39 Basic Syntax The results of using an operator depend on the sequence of evaluation Without parentheses operations are performed from left to right Consider the following two equations In the first the consta
187. side the functional block so they are declared as pins The state bits are not used outside the functional block so they are declared as nodes CLOCK RESET Pin 0 11 12 13 Pin 01 02 Pin 87 56 85 94 83 92 81 Node Figure 3 2 Signal Declarations Using Intermediate Signals An intermediate signal is a combinatorial signal that is declared as a node and used as a component of other more complex signals in a design Intermediate signals minimize logic by forcing it to be factored Creating intermediate signals in an ABEL HDL logic description has the following benefits m Reduces the amount of optimization a compiler has to perform m Increases the chances of a fit m Simplifies the ABEL HDL source file Figure 3 4 shows a schematic of combinational logic Signals A B C D and E are inputs X and Y are outputs There are no intermediate signals every declared signal is an input or an output to the subcircuit ABEL HDL Reference Manual 103 CPLD Design Strategies Figure 3 3 shows the ABEL HDL declarations and equations that would generate the logic shown in Figure 3 4 declarations A B C D E pin Xp Y pin equations X A amp B amp C BSC Y A amp D A amp E A amp B amp C Figure 3 3 Declarations and Equations FUNCTIONAL BLOCK r3 07 oo C m x Figure 3 4 Schematic without Intermediate Signal Figure 3 6 shows the same logic using an intermediate s
188. signment operators when then else When then else statements Equations specify logic functions with an extended form of Boolean algebra A semicolon is required after each equation The equations following the equation statement are equations as described in Chapter 1 Language Structure A CAUTION Use the and operators only when writing pin to pin registered equations Use the and assignment operators for registered equations with detailed dot extensions ABEL HDL Reference Manual 206 Equations Examples A sample equations section follows equations A B amp C A W Y 3 IP B C Output D In1 In2 bl eubul2 q0 ql x ik ed See Also When then else Module State diagram Truth table Operators Expressions and Equations in Chapter 1 Language Structure ABEL HDL Reference Manual 207 Functional_block Functional_ block Syntax Purpose Use NOTE When a module is instanced by an upper level source any DECLARATIONS instance_name FUNCTIONAL BLOCK source_name EQUATIONS instance_name port_name signal_name You can use a FUNCTIONAL_BLOCK declaration in an upper level ABEL HDL source to instantiate a declared lower level module and make the ports of the lower level module accessible in the upper level source You must declare modules with an interface declaration before you can instantiate t
189. specified with a particular device in mind You may still have to understand the differences between for example a GAL16LV8 and an ispLSI1032E but you do not have to specify a particular device when describing your design Attributes and dot extensions help you refine your design to work consistently when moving from one class of device architecture to another for example from devices having inverted outputs to those with a particular kind of reset preset circuitry However the more you refine your design using these language features the more restrictive your design becomes in terms of the number of device architectures for which it is appropriate Signal Attributes Signal attributes remove ambiguities that occur when no specific device architecture is declared If your design does not use device related attributes either implied by a DEVICE statement or expressed in an ISTYPE statement it may not operate the same way when targeted to different device architectures See Pin on page 235 Node on page 233 and Istype Attribute Declarations on page 222 ABEL HDL Reference Manual 65 Pin to pin vs Detailed Descriptions for Registered Designs Signal Dot Extensions Signal dot extensions like attributes enable you to more precisely describe the behavior of a circuit that may be targeted to different architectures Dot extensions remove the ambiguities in equations Refer to Dot Extensions and Architecture independence
190. stant Declarations Examples ABC 3 TT ABC is assigned the value 51 Y Bc Y h42603 X X X means don t care ADDR 1 0 15 ADDR is a set with 3 elements A B C 5 1 0 6 3 constants declared her D pin 6 see next line E S LSDIS signal names can be included G 352 55 3 4 set operations are legal A B amp C operations on identifiers are valid A B C set and identifiers on right Using Intermediate Expressions You can use intermediate constant expressions in the declarations section to reduce the number of output pins required to implement multi level functions Intermediate expressions can be useful when a module has repeated expressions In general intermediate expressions m decrease the number of output pins required but m increase the amount of logic required per output A constant expression is interpreted as a string of characters not as a function to be implemented For example for the following Declarations and Equations Declarations TMP1 A3 A0 B3 B0 TMP2 A7 A4 B7 B4 Equations F TMP1 TMP2 the compiler substitutes the declarations into the equations creating F A7 B7 AG B6 amp A5 B5 A4 B4 A3 S B3 A2 B2 amp Al B1 amp AO BO ABEL HDL Reference Manual 170 Constant Declarations In contrast if you move the const
191. suming 4 bits of data which is 15 in unsigned binary and 15 is greater than 4 In this example a four bit representation was assumed in actual use 0 the complement of 0 is 128 bits all set to 1 ABEL HDL Reference Manual 26 Basic Syntax Some examples of relational operators in expressions are listed below Expression Value 2 3 False 2l 3 True 3 lt 5 True 1 gt 2 True The logical values true and false are represented by numbers Logical true is 1 in twos complement so all 128 bits are set to 1 Logical false is 0 in twos complement so all 128 bits are set to 0 This means that an expression producing a true or false value a relational expression can be used anywhere a number or numeric expression could be used and 1 or 0 will be substituted in the expression depending on the logical result For example A D B C means that m A equals the complement of D if B equals C m Aequals D if B does not equal C When using relational operators always use parentheses to ensure the expression is evaluated in the order you expect The logical operators amp and have a higher priority than the relational operators see the priority table later in this chapter The following equation Select A15 A0 hD000 4 A15 A0 h1000 needs parentheses to obtain the desired result Select A15 A0 hD000 A15 A0 h1000 Without the parentheses the equation would have the default grouping
192. t terms that will not fit to any programmable logic device Node collapsing allows you to describe equations in terms of multi level combinational nodes then collapse the nodes into the output until it reaches the product term you specify The result is an equation that is optimized to fit the device constraints ABEL HDL Reference Manual 64 Pin to pin Language Features Selective Collapsing In some instances you may want to prevent the collapsing of certain nodes For example some nodes may help in the simulation process You can specify nodes you do not want collapsed as Istype keep and the optimizer will not collapse them Pin to pin Language Features ABEL HDL is a device independent language You do not have to declare a device or assign pin numbers to your signals until you are ready to implement the design into a device However when you do not specify a device or pin numbers you need to specify pin to pin attributes for declared signals Because the language is device independent the ABEL HDL compiler does not have predetermined device attributes to imply signal attributes If you do not specify signal attributes or other information such as the dot extensions which are described later your design might not operate consistently if you later transfer it to a different target device Device independence vs Architecture independence The requirement for signal attributes does not mean that a complex design must always be
193. t defines the beginning of a group of equations that specify the logic functions of a device See Also Operators Expressions and Equations on page 24 When Then Else on page 255 ABEL HDL Reference Manual 55 Logic Description Truth Tables Keyword truth_table Truth table inputs gt outputs inputs gt outputs or Truth_table inputs gt registered outputs gt outputs Truth tables specify outputs as functions of input combinations in tabular form See Also Dcset Don t Care Set on page 177 State Descriptions Keyword state_diagram State diagram state reg gt state out STATE state exp equation equation trans stmt P The STATE DIAGRAM section contains state descriptions that describe the logic design The specification of a state description requires the use of the STATE DIAGRAM syntax which defines the state machine and the IF THEN ELSE CASE and GOTO statements that determine the operation of the state machine See Also With on page 257 ABEL HDL Reference Manual 56 Logic Description Fuse Declarations Keyword fuses Fuses fuse_number fuse value or fuse_number_set fuse value The FUSES section explicitly declares the state of fuses in the associated device A device must be declared before a fuses declaration XOR Factors Keyword XOR_Factors XOR_factors signal name xor_factors The XOR_FACTORS section allows y
194. t indicates text you type in response to system prompts For Courier example SET YBUS YO Y6 BA Vertical bars indicate options that are mutually exclusive you can select only one For example INPUTJOUTPUT BIDI Quotes Titles of chapters or sections in chapters in this manual are shown in quotation marks For example See Chapter 1 Introduction amp NOTE Indicates a special note A CAUTION Indicates a situation that could cause loss of data or other problems TIP Indicates a special hint that makes using the software easier ES Indicates a menu option leading to a submenu option For example File gt New ABEL HDL Reference Manual 12 Related Documentation Related Documentation In addition to this manual you might find the following reference material helpful Schematic Entry User Manual Schematic Entry Reference Manual 5K 8K Macro Library Supplement Macro Library Reference Manual ABEL Design Manual Library Manager Tools Manual ispEXPERT System User Manual ispEXPERT System Simulation User Manual Waveform Tools Manual ispEXPERT System Getting Started Manual VHDL and Verilog Simulation User Manual These books provide technical specifications for the ispEXPERT System and ispLSI device families for Lattice Semiconductor Corp LSC They give helpful information on device use and design development ABEL HDL Reference Manual 13 Chapter 1 Language Structure This chapte
195. te 226 S Selective collapsing 65 sequence abl 91 133 Set 37 Set operations 34 Sets 33 118 assignment and comparison 35 evaluation of 37 indexing 33 limitations 39 using to create modes 118 Shift 25 Signals nodes 233 pin 235 Simulation test vectors 247 trace keyword 250 Source files beginning 232 declarations 46 design considerations 60 directives 59 header 46 logic descriptions 53 structure of 43 test vectors 58 Special constants 19 SR flip flop 73 clocked memory element 226 dot extensions 161 State declarations 238 in descriptions 239 keyword 238 State in State_diagram keyword 239 State machine example 91 243 dcset 96 3 state sequencer 131 blackjack machine 134 no dcset 94 ABEL HDL Reference Manual 267 Index State machines and dcset 86 94 case keyword 199 cleared register state 93 design considerations 90 goto 213 identifiers in 90 identifying states 99 if then else 214 illegal states 93 powerup register states 92 reducing product terms 98 state in state_diagram 239 state_diagram 240 test vectors for 248 transition statements 241 using state register outputs 99 with 257 State registers 99 State_diagram keyword 240 State diagram dcstate 178 State register keyword 245 statema abl 243 Subtraction 25 Sum of products XOR factors 258 Symbolic state descriptions 99 specifying reset logic 198 Sync reset keyword 198 Synchronous preset 160 Syntax 15 T T flip flop and equations 78
196. ter feedback OE Output enable PIN Pin feedback SET Synchronous set Detailed Syntax Device specific AP Asynchronous register preset AR Asynchronous register reset SCE Clock enable input to a gated clock flip flop zB Data input to a D type flip flop ES Flip flop mode control J J input to a JK type flip flop K K input to a JK type flip flop LD Register load input LE Latch enable input to a latch LH Latch enable high to a latch PR Register preset Register feedback JE R input to an SR type flip flop RE Register reset S S input to an SR type flip flop SP Synchronous register preset ABEL HDL Reference Manual 54 Logic Description Table 1 10 Dot Extensions Continued Dot Extensions Description SR Synchronous register reset cl T input to a T type toggle flip flop The CLR ACLR SET ASET and COM dot extensions are not recognized by device fitters released prior to ABEL 5 0 If you are using a fitter that does not support these reset preset dot extensions specify istype invert or istype buffer and the compiler converts the new dot extensions to SP AP SR AR and D respectively Equations Keyword equations Equations WHEN condition THEN element expression ELSE equation Or WHEN condition THEN equation ELSE equation inst name LSC macro name port definition The EQUATIONS statemen
197. the dealer s hand using typical dealer strategies to decide after each round of play whether to draw another card or to stand The blackjack machine consists of these functions a card reader that reads each card as it is drawn control logic that tells it how to play each hand based on the total point value of the cards currently held and display logic that displays scores and status on the machine s four LEDs For this example we are assuming that the two digital display devices used to display the score have built in seven segment decoders To operate the machine insert the dealer s card into the card reader The machine reads the value and in the case of later card draws adds it to the values of previously read cards for that hand Face cards are valued at 10 points non face cards are worth their face value and aces are counted as either 1 or 11 whichever count yields the best hand If the point total is 16 or less the GT16 line will be asserted active low and the Hit LED will light up This indicates that the dealer should draw another card If the point total is greater than 16 but less than 22 no LEDs will light up indicating that the dealer should draw no new cards If the point total is 22 or higher LT22 will be asserted active low and the Bust LED will light indicating that the dealer has lost the hand The blackjack machine is implemented in three subdesigns 1 A multiplexer adder comparator which adds the value
198. the state machine when an ace is drawn is essentially the same A card is drawn and the score is added If the card is an ace and no ace has been drawn previously the state machine goes to state Add10 and ten is added to the count in effect making the ace an 11 Transitions to and from Test17 and Test22 proceed as before However if the score exceeds 21 and an ace has been set to 11 the state machine goes to state Sub10 10 is subtracted from the score and the state machine goes to state Test17 Test Vectors BJACK Figure 4 23 shows three sets of test vectors each set represents a different hand of play as described above the set of vectors and tests the different functions of the design The Restart function is used to set the design to a known state between each hand and the state identifiers are used instead of the binary values which they represent ABEL HDL Reference Manual 145 title Bl Inputs Clk C1kI GT16 LT2 is_Ace Restart Ena Sensor in InOut Out Outputs AddClk Add10 Sub10 02 01 QO Ace High Low H L C X Ostate Clear ShowHit AddCard Add 10 Wt Test 17 Test 22 ShowStan ShowBust Sub 10 Zero equations Ostate Ace Ostate Ace QGdcset state diagram Qstate State Clear N 2 d Cardin CardoOut C oe pin pin pin pin pin pin pin pin pin pin pin C State ShowHit
199. tion that identifies the bit values in the state register for each state A B and C are only identifiers they do not indicate the bit pattern of the state machine Their declared values define the value of the state register sreg for each state The declared values are 0 1 and 2 module Sequence title State machine example qi qO pin 14 15 istype reg clock enab start hold reset pin T4 24 2 35 halt pin 17 istype reg in B in C pin 12 13 istype com sreg q1 q0 State Values A 0 B 1 C 2 equations qd1 q0 halt clk clock qd1 q0 halt oe enab state_diagram sreg State A Hold in state A until start is active in_B 0 in_C 0 IF start amp reset THEN B WITH halt 0 ELSE A WITH halt halt fb State B Advance to state C unless reset is active in B 1 or hold is active Turn on halt indicator in_C 0 if reset IF reset THEN A WITH halt 1 ELSE IF hold THEN B WITH halt 0 ELSE C WITH halt 0 State C Go back to A unless hold is active in B 0 Reset overrides hold in_C 1 IF hold amp reset THEN C WITH halt 0 ELSE A WITH halt 0 Figure 2 12 Using Identifiers for States ABEL HDL Reference Manual 91 State Machines test_vectors clock enab start reset hold gt sreg halt in_B in_C
200. tions You can nest CASE statements with lf Then Else GOTO and other CASE statements and you can use equation blocks n NOTE Equation blocks used within a conditional expression such as IF THEN CASE or WHEN THEN result in logic functions that are logically ANDed with the conditional expression that is in effect The state machine advances to the state indicated by state exp following the expression that produces a true value If no expression is true the result is undefined and the resulting action depends on the device being used For devices with D flip flops the next state is the cleared register state For this reason you should be sure to cover all possible conditions in the CASE statement expressions If the expression produces a numeric rather than a logical value O is false and any non zero value is true The expressions contained within the CASE ENDCASE keywords must be mutually exclusive only one of the expressions can be true at any given time If two or more expressions within the same CASE statement are true the resulting equations are undefined ABEL HDL Reference Manual 199 Case Examples Mutually exclusive Case statement case a 0 1 a 2 a 2 3 a 3 0 endcase Not mutually exclusive Case statement case a 0 1 a 0 amp B 0 0 endcase See Also State_diagram Goto If then else With ABEL HDL Reference Manual 200 Cycle
201. tions are Q16 A amp B Example 2 C amp D The example octalf ab1 uses a more complex high level equation module OCTALF title Octal counter with xor factoring octalf device P20X8 DO D7 07 00 CLK I0 I1 0C CarryOut pin 3 210 pin 15 22 istype reg xor CarrylIn pin 1 2 11 13 23 pin 14 istype com Leeper Rs vp UO oe ule x gus Data D7 D0 Count Q7 00 Mode I1 10 Clear 0 02 Hold Os XI Load Lee 0 13 Inc ly dls xor_factor Count FB Count amp I0 comments removed ABEL HDL Reference Manual 259 XOR_factors equations Count Count FB 1 amp Mode Inc amp CarryIn Count FB amp Mode Inc amp CarryIn Count FB amp Mode Hold Data amp Mode Load 0 amp Mode Clear CarryOut CarryIn Count FB hFF Count C CLK Count OE OC test vectors removed comments removed end OCTALF ABEL HDL Reference Manual 260 Symbols ALCR 159 AP 159 AR 159 ASET 159 C 19 CE 159 CLK 159 CLR 159 COM 79 159 constant 19 D 79 159 example 168 D 19 ext dot extension 158 example 168 P 19 PIN 79 80 159 assignment 235 istype 222 pin keyword 235 using the range operator in 235 PR 159 example 168 Q 79 159 R 159 RE 159 example 168 Index a e m
202. tor the progress of the parsing step of the compiler or as an aid to debugging complex sequences of directives Examples message Includes completed ABEL HDL Reference Manual 191 Onset No Don t Care s Onset No Don t Care s Syntax ONSET Use The Onset directive disables the use of don t care input conditions for optimization See Also Dcset Istype dc ABEL HDL Reference Manual 192 Page Page Directive Page Page Directive Syntax PAGE Use Send a form feed to the listing file If no listing is being created Page has no effect ABEL HDL Reference Manual 193 Radix Default Base Numbering Directive Radix Default Base Numbering Directive Syntax Use RADIX expr expr An expression that produces the number 2 8 10 or 16 to indicate a new default base numbering The Radix directive changes the default base The default is base 10 decimal This directive is useful when you need to specify many numbers in a base other than 10 All numbers that do not have their base explicitly stated are assumed to be in the new base See Numbers in Chapter 1 Language Structure The new specified default base stays in effect until another Radix directive is issued or until the end of the module is reached Note that when a new Radix is issued the specification of the new base must be in the current base format When the default base is set to 16 all numbers
203. ty If the Id input is high then the q outputs reflect the value on the d inputs after the next clock edge The Hold mode has the next highest priority Provided Id is low then when the cnten input is low the q outputs maintain their current values upon subsequent clock edges ignoring any other inputs The Up and Down modes have the same priority and by definition are mutually exclusive Provided cnten is high and Id is low then when u d is high the counter counts up and when u d is low the counter counts down ABEL HDL Reference Manual 118 Equations Counter Reset The counter is reset asynchronously by assertion of the input rst Using Range Operators Because this design uses range operators and sets you can modify the counter to be any width by making changes in the declarations section You could create a 9 bit counter by changing the lines which read d3 d0 and q3 q0 to d8 d0 and q8 qO respectively The range expressions are expanded out and create register sets of corresponding width Design Description Hierarchical Interface Declaration Directly after the module name the design contains a hierarchical interface declaration which is used by the ABEL HDL compiler and linker if another ABEL HDL source instantiates this source The interface list shows all of the input output and bidirectional signals if any in the design Declarations The declarations contain sections that make the
204. type flip flop L type latch Gated clock D flip flop Y Y Extension Required Supported Extensions clk E oe q Sp Sr ap ar pin d le 1h oe q pin Clk Of ce oe pin ABEL HDL Reference Manual Definition clock toggle input output enable flip flop feedback synchronous preset synchronous reset asynchronous preset asynchronous reset pin feedback data input latch enable input to a latch latch enable high input to a latch output enable flip flop feedback pin feedback clock or clock enable data input output enable flip flop feedback pin feedback 162 ext Dot Extensions Pin to Pin Design Dot Extensions Table 5 3 shows the dot extensions that are allowable and which of those are required for pin to pin design descriptions The required dot extensions are indicated with a check in the Required column Table 5 3 Dot Extensions for Architecture independent pin to pin Designs Allowable Register Type Required Extensions Definition combinational no register none output oe output enable pin pin feedback registered logic QUe synchronous preset aclr asynchronous preset set synchronous set aset asynchronous set V clk clock com combinational feedback Eb registered feedback pin pin feedback Figure 5 1 through Figure 5 8 show the effect of each dot extension The actual source of the feedback may vary from that shown
205. uired See Also Set Indexing in Chapter 1 Language Structure ABEL HDL Reference Manual 196 Standard Standard Operators Directive Syntax STANI Use DARI Standard Standard Operators Directive The Standard option resets the operators to the ABEL HDL standard The alternate set is chosen with the Alternate directive ABEL HDL Reference Manual 197 Async_reset and Sync_reset Async_reset and Sync_reset Syntax SYNC_RESET symbolic_state_id input_expression ASYNC_RESET symbolic_state_id input_expression Purpose In symbolic state descriptions the SYNC_RESET and ASYNC_RESET statements specify synchronous or asynchronous state machine reset logic in terms of symbolic states Use symbolic_state_id An identifier used for reference to a symbolic state input_expression Any expression Examples ASYNC_RESET Start Reset SYNC_RESET Start Reset See Also State State_diagram Using Symbolic State Descriptions in Chapter 2 Design Considerations ABEL HDL Reference Manual 198 Case Syntax Purpose Use Case CASE expression state_exp expression state exp ENDCASE Use the CASE statement in a state diagram to indicate transitions of a state machine when multiple conditions affect the state transitions expression An expression state exp An expression identifying the next state optionally followed by WITH transition equa
206. ule with the constants n NOTE Supported default values are 1 0 or X don t care You can give default values for a set with a positive integer and each digit of the integer s binary form supplies the default value for the corresponding signal in the set See Also Interface top level Functional block Hierarchy in ABEL HDL in Chapter 2 Design Considerations ABEL HDL Reference Manual 221 Istype _ Attribute Declarations Istype Attribute Declarations Syntax Purpose Use signal signal PIN NODE s ISTYPE attr atea idw The ISTYPE statement defines attributes characteristics of signals pins and nodes You should use signal attributes to remove ambiguities in architecture independent designs Even when a device has been specified using attributes ensures that the design operates consistently if the device is changed later signal A pin or node identifier attr A string that specifies attributes for the signal s Supported attributes are described below Signal attributes are specified with the ISTYPE statement which can be combined with pin or node declarations in a single declaration The attributes defined with ISTYPE specify the architectural constraints for signals that have not been assigned to a specific device pin or node number or a specified device and or pin number that has programmable characteristics All attributes listed on the right side o
207. ure 2 1 illustrates a typical macrocell associated with signal Q1 Detailed descriptions are written for the various input ports of the macrocell shown in Figure 2 1 with dot extension labels Note that the macrocell features a configurable inversion between the Q output of the flip flop and the output pin labeled Q1 If you use this inverter or select a device that features a fixed inversion the behavior you observe on the Q1 output pin will be inverted from the logic applied to or observed on the various macrocell ports including the feedback port Q1 q Q1 ap Q1 d Q1 Q1 clk CLK Q1 ar n NEC S IQ1 pin Figure 2 1 Detail Macrocell Pin to pin descriptions on the other hand allow you to describe your circuit in terms of the expected behavior on an actual output pin regardless of the architecture of the underlying macrocell Figure 2 2 illustrates the pin to pin concept ABEL HDL Reference Manual 68 Pin to pin vs Detailed Descriptions for Registered Designs l CH rem Figure 2 2 Pin to pin Macrocell When pin to pin descriptions are written in ABEL HDL the generic macrocell shown above is synthesized from whatever type of macrocell actually exists in the target device Examples of Pin to pin and Detailed Descriptions Two equivalent module descriptions one pin to pin and one detailed are shown below for comparison Pin to pin Module Description module Q
208. ut pin Card present switches bjack Restart pin Restart game bjack V4 VO pin muxadd Ace pin Card V4 V0 Sensor CardIn CardOut _In 0 r 1 1 InOut x 1 les Out Al r 0 l Top level outputs D5 D0 pin istype com binbcd BCD D3 D0 BCD2 D5 D4 ABEL HDL Reference Manual 148 Top 1 Q2 Q0 Add10 Sub AddClk Ostate Clear ShowHit AddCard Add 10 Wt Test 17 Test 22 ShowStand ShowBust Sub 10 Zero Hit Bust Ei equations level pins for observing state machine pin istype com pin istype com node istype com keep 10 Add10 Sub10 02 01 00 1 1 pow ipo lip 3l E 1 1 r 1 1 0 30 T ag que Ore Or OT 124 Ora dk S pe TOR Oa E EG 1 1 0 p dd 25 1 0 01 26 1 0 11 27 F 1 1 0 0 28 m r 0 11 29 1 0 0 Os decl Or eo Or su Di De QT eNO BB GT16 BB LT22 OV uo 0 d Describe the input connections MA V4 V3 V2 V1 V0 Card MA Clr Restart BJ Clk Clk BJ ClkIN Clk BJ Restart Restart BJ CardIn CardIn BJ CardOut CardOut BJ Ena 0 Describe the output connections D5 D4 D3 D2 D1 D0 BB D5 D4 D3 D2 D1 D0 Add10 BJ Add10 Sub10 BJ Sub10 00 BJ Q0 O1 BJ Ql Q2
209. v wv wv MW 110 Chapter 4 Source File Examples The following examples are representative of programmable logic applications and serve to illustrate significant ABEL HDL features You can use these examples to get started creating your own source files For complete information on creating a source file refer to Chapter 1 Language Structure and Chapter 5 Language Reference All the examples in this section are installed with your software and you can use them without making any changes or modify them in your designs The examples are divided into sections that demonstrate how to use the following programmable logic applications Equations State Diagrams Truth Tables Combined Logic Descriptions Hierarchy ABEL or Synario Projects ABEL HDL Reference Manual 111 Equations Equations Memory Address Decoder Address decoding is a typical application of programmable logic devices and the following describes the ABEL HDL implementation of such a design Design Specification Figure 4 1 shows the block diagram for this design and a continuous block of memory divided into sections containing dynamic RAM DRAM I O IO and two sections of ROM ROM 1 and ROM2 The purpose of this decoder is to monitor the 6 high order bits A15 A10 of a sixteen bit address bus and select the correct section of memory based on the value of these address bits To perform this function a simple decoder with six inputs and four
210. ven the collapse attribute module coll b a c d e pin b node istype collapse equations a b amp 6 b c amp dqd end The resulting equation collapses b out of the equations a c amp dad e keep Do not collapse this combinational node from equations In the example under collapse b would be retained com Specifies a combinational symbol ABEL HDL Reference Manual 224 Istype _ Attribute Declarations dc neg and pos These attributes control the value of unspecified logic in your design and are mutually exclusive The values they specify are shown below Istype Attribute Unspecified Logic is de X don t care neg 1 pos 0 The dc attribute is equivalent to the Dcset directive except it operates on signals instead of applying to a whole section y NOTE The neg or pos attribute is implied if a device is specified For example neg is implied if the device output is inverted reg d reg g The signal specified is a registered output Equations state diagrams and truth tables will generate logic for a D type flip flop normalized to take into account any inverters in the target device The signal specified is a registered output Equations state diagrams and truth tables will generate logic for a D type flip flop but you must specify if the output is inverted in the target device with attribute invert or buffer The signal specified is
211. verted for both non inverting and inverting devices A single logic function may be expressed with many different equations For example all three equations below for F1 are equivalent 1 Fl A amp B 2 Fl A amp B 3 F1 A B In the example above equation 3 uses two product terms while equation 1 requires only one This logic function will use fewer product terms in a non inverting device than in an inverting device The logic function performed from input pins to output pins will be the same for both polarities Not all logic functions are best optimized to positive polarity For example the inverted form of F2 equation 3 uses fewer product terms than equation 2 1 F2 A B C D 2 F2 A amp C A amp D B amp C B amp D 3 F2 A amp IB 4 C D Programmable polarity devices are popular because they can provide a mix of non inverting and inverting outputs to achieve the best fit ABEL HDL Reference Manual 76 Polarity Control Polarity Control with Istype In ABEL HDL you control the polarity of the design equations and target device in the case of programmable polarity devices in two ways m Using Istype neg pos and dc m Using Istype invert and buffer Using Istype neg pos and dc to Control Equation and Device Polarity The neg pos and dc attributes specify types of optimization for the polarity
212. wd xad dd dod OR ER rede eec o en 173 Alternate Alternate Operator Set 2 2 eens 174 Carry Maximum Bit width for Arithmetic Functions 000 cee eee 175 Const Constant Declarations seca dida ro oe CX CR we eee Ed t AA 176 Dceset Don t Care Set hi oR qq ea boy A Edo ede ed E CORR 177 Dcstate State Output Don t Cares eens 178 DEN EXT Deye darian dada deed aia A RE E Coa A a dU 179 Expr Expression DIGUIIUO ada xa decd ciel cdeieeed GRRRPPOxGGI rA en dude n P 180 cj PR SI e TERM ELTE TRU O DOR doe aes 181 comb Jr Blank Directive iud do dod do 9e ORC GC Ree EORR Oe CAO ER ER C 182 lfdef If Defined Directive soon xag OC ee CR Re e D Rs 183 miden Jr Identical Directive cir EO EY Ee REOR CR OR RO CECI RA RR 184 lfnb If Not Blank Directive ssee ee ee 185 lfndef If Not Defined Directive llleee nn RR 186 lfniden If Not Identical Directiva oocooococociociaia nia cri Piet ad 187 include Include Directive iiisua oaa sey bee RH ORE AER 188 Irp Indefinite Repeat Directive 0 eee 189 lrpc Indefinite Repeat Character Directive o oooooooooooomoooo 190 Message Message Directive 0 eee 191 Onset No Don t Care s 0 0 ee eee ees 192 Crags Page DIO AA 193 Radix Default Base Numbering Directive 0 00 eee eens 194 Repeat Rep
213. y name The LIBRARY statement extracts the contents of the indicated file from the ABEL HDL library and inserts it into your file Logic Description One or more of the following elements can be used to describe your design m Equations Truth Tables State Descriptions Fuses XOR Factors In addition dot extensions like Istype attributes in the Declarations section enable you to more precisely describe the behavior of a circuit in a logic description that may be targeted to a variety of different devices Dot Extensions Syntax signal name ext Dot extensions can be specific for certain devices device specific or generalized for all devices architecture independent Device specific dot extensions are used with detailed syntax architecture independent dot extensions are used with pin to pin syntax Detailed and pin to pin syntax is described in more detail in Chapter 2 Design Considerations Dot extensions can be applied in complex language constructs such as nested sets or complex expressions The ABEL HDL dot extensions are listed in Table 1 10 ABEL HDL Reference Manual 53 Logic Description Table 1 10 Dot Extensions Dot Extensions Description Pin to Pin Syntax Architecture independent ACLR Asynchronous clear ASET Asynchronous set CLK Clock input to an edge triggered flip flop CLR Synchronous clear COM Combinational feedback normalized to the pin value FB Regis
214. y you can also emulate a JK flip flop by combining the D flip flop emulation of a T flip flop in Figure 2 9 with the circuitry of Figure 2 10 Figure 2 11 illustrates this concept ABEL HDL Reference Manual 88 Exclusive OR Equations Preset 1 AND2 Clear K i XOR 2 Q OR2 1 m pan yi onn 1 3 2 4 RES Q Q J amp IQ K amp Q Figure 2 11 JK Flip flop Emulation D Flip flop with XOR ABEL HDL Reference Manual 89 State Machines State Machines A state machine is a digital device that traverses a predetermined sequence of states State machines are typically used for sequential control logic In each state the circuit stores its past history and uses that history to determine what to do next This section provides some guidelines to help you make state diagrams easy to read and maintain and to help you avoid problems State machines often have many different states and complex state transitions that contribute to the most common problem which is too many product terms being created for the chosen device The topics discussed in the following subsections help you avoid this problem by reducing the number of required product terms The following subsections provide state machine considerations Use Identifiers Rather Than Numbers for States Powerup Register States Unsatisfied Transition Conditions D type Flip flops Unsatisfied Transition Conditions Other Flip flops Number Adjacent States for a One bit
215. y allowing groups of signals to be referenced with one name For example you could collect the outputs BO B7 of an eight bit multiplexer into a set named MULTOUT and the three selection lines into a set named SELECT You could then define the multiplexer in terms of MULTOUT and SELECT rather than individual input and output bits A set is represented by a list of constants and signals separated by commas or the range operator and surrounded by brackets The sets MULTOUT and SELECT would be defined as follows MULTOUT B0 B1 B2 B3 B4 B5 B6 B7 SELECT 2 381 380 The above sets could also be expressed by using the range operator for example MULTOUT B0 B7 SELECT S2 S0 Identifiers used to delimit a range must have compatible names they must begin with the same alphabetical prefix and have a numerical suffix Range identifiers can also delimit a decrementing range or a range which appears as one element of a larger set as shown below A7 A0 decrementing range Q1 Q2 X A10 A7 range within a larger set The brackets are required to delimit the set ABEL HDL source file sets are not mathematical sets Set Indexing Set indexing allows you to access elements within a set The following example uses set indexing to assign four elements of a 16 bit set to a smaller set declarations Seti f15 f0 Set2 q3 q0 equations Set2 Set1 7 4 The numeric values used for defining a set index refer to the bit
216. y originate from lower level outputs that are not being used in the top level source For example when you use a 4 bit counter as a 3 bit counter The most significant bit of the counter is unused and can be removed from the design to save device resources This step also removes trivial connections In the following example if out1 is a pin and t1 is a node outl tl tl a86 would be mapped to outl a86 ABEL HDL Reference Manual 63 Node Collapsing Merging Feedbacks Linking multiple modules can produce signals with one or more feedback types such as FB and Q You can tell the optimizer to combine these feedbacks to help the fitting process Post linked Optimization If your design has a constant tied to an input you can re optimize the design Re optimizing may further reduce the product terms count For example if you have the equation out i0 amp il iO amp i2 and 0 is tied to 1 the resulting equation would be simplified to out il Node Collapsing All combinational nodes are collapsible by default Nodes that are to be collapsed or nodes that are to be preserved are flagged through the use of signal attributes in the language The signal attributes are Istype keep Do not collapse this node collapse Collapse this node Collapsing provides multi level optimization for combinational logic Designs with arithmetic and comparator circuits generally generate a large number of produc
217. yntax id Xd lese expr 5 expr Purpose A constant declaration that defines constants used in a module Use id An identifier naming a constant to be used within a module expr An expression defining the constant value n NOTE The equal sign 2 used for constant declarations in the Declarations section is also used for equations in the Equations section See Operators Expressions and Equations in Chapter 1 Language Structure A constant is an identifier that retains a constant value throughout a module The identifiers on the left side of the equals sign are assigned the values listed on the right side There is a one to one correspondence between the identifiers and the expressions listed There must be one expression for each identifier The ending semicolon is required after each declaration Constants are helpful when you use a value many times in a module especially when you may be changing the value during the design process Constants allow you to change the value once in the declaration of the constant rather than changing the value throughout the module Constant declarations may not be self referencing The following examples will cause errors X X a b b a An include file constant inc in the ABEL HDL library file contains definitions for the most frequently used ABEL HDL constants To include this file enter Library constant ABEL HDL Reference Manual 169 Con

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