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SPW-RTC User Manual - ESA Microelectronics Section

1. Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Logical Addr Protocol ID Command amp Type Dest Device Key Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Logical Addr Transaction ID MS Transaction ID LS Extended Addr Addr MS Addr Addr Addr LS Data length MS Data length Data length LS Header CRC8 Data Data Data Data Data Data Data Data Data Data CRC8 EOP Figure 10 7 RMAP transfer protocol packet structure for Write command Note that the shaded fields are optional and or can contain a variable number of bytes E g the amount of Destination Path Address bytes may be any number from 0 to 12 Note that Header CRC8 is the last byte of the header Note that the Data CRC8 byte is not optional Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG 121 GAISLER Aerospace Defence Technology 10 5 9 4 2 RMAP Write Response format The write command response Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source P
2. Address Register 0x90000000 DSU control register 0x90000004 Trace buffer control register 0x90000008 Time tag counter 0x90000010 AHB break address 1 0x90000014 AHB mask 1 0x90000018 AHB break address 2 0x9000001C AHB mask 2 0x90010000 0x90020000 Trace buffer 0 Trace bits 127 96 4 Trace bits 95 64 8 Trace bits 63 32 C Trace bits 31 0 0x90020000 0x90040000 IU FPU register file Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 44 EROFLEX GAISLER TABLE 13 DSU address space RUAG Aerospace Defence Technology Address Register 0x90080000 0x90100000 IU special purpose registers 0x90080000 Y register 0x90080004 PSR register 0x90080008 WIM register 0x9008000C TBR register 0x90080010 PC register 0x90080014 NPC register 0x90080018 FSR register 0x9008001C DSU trap register 0x90080040 0x9008007C ASR16 ASR31 when implemented 0x90100000 0x90140000 Instruction cache tags 0x90140000 0x90180000 Instruction cache data 0x90180000 0x901C0000 Data cache tags 0x901C0000 0x90200000 Data cache data The addresses of the IU FPU registers depends on how many register windows has been implemented and if and FPU is present The registers can be accessed at the following addresses NWINDOWS nu
3. Ce Code 0 0 0 0 0 0 0 0 LSB Function Contains the interrupts related to the link itself Timing All the link specific interrupts are issued as soon as detected by the Space Wire codec Note that LinkAbort is issued together with any link specific interrupt if the error occurred while SPW CODEC Status Register LinkState was in Run state Note also that when the user disconnects the link by writing the SPW CODEC Configuration Register LinkDis the resulting LinkAbort interrupt will be issued up to 2 us later All the time code specific interrupts are issued on either the successful reception or transmission of the time code The PktRej interrupt is issued either directly when an error is detected during protocol identification i e discarded without writing to memory or when the last byte has been written to memory Constraints Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG 164 GAISLER Aerospace Defence Technology Field Description DisErr Link interface disconnection error detected ParErr Link interface parity error detected ESCErr Link interface ESC error detected CrErr Link interface credit error detected RxTime Code Time code received TxTime Code Time code transmitted PktRej A packet has been rejected and been discarded First Failing Packet Register has been trigger
4. Trace Buffer LEON SPARC V8 Debug I F Integer unit LeonLeonDsuEn Debug LeonDsuBre gt Support Unit LeonDsuAct l Cache D Cache AHB interface AMBA AHB Debug LeonDsuTx gt i Figure 46 Debug support unit and comm link LeonDeuRx Comm Link igure 8 supp 3 5 2 Debug support unit 3 5 2 1 Overview The debug support unit is used to control the trace buffer and the processor debug mode The DSU is attached to the AHB bus as slave occupying a 2 Mbyte address space Through this address space any AHB master can access the processor registers and the contents of the trace buffer The DSU control registers can be accessed at any time while the processor registers and caches can only be accessed when the processor has entered debug mode The trace buffer can be accessed only when tracing is disabled completed In debug mode the processor pipeline is held and the processor state can be accessed by the DSU Entering the debug mode can occur on the following events e executing a breakpoint instruction ta 1 e integer unit hardware breakpoint watchpoint hit trap Oxb e rising edge of the external break signal LeonDsuBre e setting the break now BN bit in the DSU control register e atrap that would cause the processor to enter error mode e occurrence of any or a selection of traps as defined in the DSU control register e after a single step operation e DSU breakpoint hit
5. SPW RxVC Packet Counter Register SPW_RxPR R W 31 8 7 0 z PktCntTrig 0 LSB Function This register is used for configuring the number of packets to be received for a block transfer Timing Constraints Field Value Description virtual channel does not receive any further packets until triggered by software again PktCntTrig The packet counter is not enabled Any number of packets can be received 1 255 Number of SpaceWire packets to be received on the Rx VC until the packet trigger CntTrig interrupt is issued After this the SPW RxVC DMA Page Register SPW_RxDPage R W 31 4 3 0 R DMA Page 0 MSB LSB Function This register defines the page address for the virtual receive channel Timing Constraints Field Description DMA Page Extended Address for a DMA access corresponding to A35 A32 which allow a total of 64 Gbyte addressing space SPW RxVC DMA Base Address Register SPW_RxDBAR R W 31 0 DMA Base Address 0 MSB LSB Function This register defines the base address for the virtual receive channel Timing Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG 176 GAISLER Aerospace Defence Technology Constraints Fi
6. Timing Constraints Field Description DestKey RMAP Destination key Any incoming hardware supported RMAP command must have matching Destination Key in order to be accepted If not the complete packet is rejected during header check SPW Transmit Time Code Register SPW_TTCR R W 31 8 1 6 5 0 TxTimeCtrl TxTimeCnt 0 MSB LSB Function This registers is used for initiating the Time Code transmission counter Timing Writes are ignored while a time code transmission is taking place Written values should thus be validated by a read Constraints Values written to the TxTimeCtrl field are only visible if followed by an assertion of the SpwTxTick Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX ie RUAG GAISLER Aerospace Defence Technology Field Description TxTimeCnt New TxTimeCnt start value TxTimeCnt 1 will be transmitted at the next SpwTxTick TxTimeCtrl When read TxTimeCtrl value transmitted due to a previous SPWTxTick or SPW_SWTTCR write When written TxTimeCtrl value to be transmitted SPW VC Transfer Protocol ID Register SPW_VCTPIDR R W 31 8 7 0 7 VCTPID F016 MSB LSB Function This register configures the SpaceWire Virtual Channel Transfer Protocol Identifier Timing Constraints See RMAPID for constraints on Protocol ID usage Note that RMAP in th
7. Figure 73 Timer latch configuration register 31 0 Specifies what bits of the AMBA APB interrupt bus shall cause the Timer Latch Register to latch the timer values 31 0 LTCV Figure 74 Timer latch register 31 0 Latched Timer Counter Value LTCV Value latch from corresponding timer Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 A EROFLEX RUAG GAISLER Aerospace Defence Technology 8 24 BIT GENERAL PURPOSE INPUT OUTPUT 8 1 Overview The General Purpose Input Output interface is assumed to operate in an AMBA bus system where the APB bus is present The AMBA APB bus is used for control and status handling The General Purpose Input Output interface provides a configurable number of channels Each channel is individually pro grammed as input or output Additionally a configurable number of the channels are also programma ble as pulse command outputs The default reset configuration for each channel is as input The default reset value each channel is logical zero The pulse command outputs have a common counter for establishing the pulse command length The pulse command length defines the logical one active part of the pulse It is possible to select which of the channels shall generate a pulse command The pulse command outputs are generated simulta neously in phase with each other and with the same length or duration It is not possible to gene
8. 200 EROFLEX RUAG GAISLER Aerospace Defence Technology TABLE 97 Revision control Revision Date Sections Comment 1 7 2007 Feb 1 4 Source references added 2 1 2 2 3 3 4 LEON2 timers extended to 32 bit 3 1 LEON2 multiplier specified 3 2 LEON cache section adapted to SpaceWire RTC implementation 3 3 1 Write protection registers added 3 3 2 2 3 3 6 13 4 New PIO interrupts added 3 4 LEON memory controller updates added 3 5 LEON DSU section adapted to SpaceWire RTC implementation 9 4 GRHCAN TxLoss interrupt explained 1 6 2006 Dec 2 2 Memory interface address width corrected 7 4 13 3 5 Timer 2 registers added 10 4 13 3 8 13 3 9 Time code transmission revised 1 5 2006 May 13 3 5 Added Timer 1 registers 1 4 2006 Mar 2 2 8 13 3 6 13 4 2 Interrupts added to GRGPIO 6 ADC timing extended 1 3 2006 Feb 5 GRCHAN timing configuration constrained 1 2 2006 Feb 5 GRFIFO size specified 7 4 Timer configuration register corrected 9 10 GRCHAN TSEG2 configuration constrained 11 SpwClk configuration pins changed 1 1 2006 Feb Added MEIKO FPU 1 0 2006 Jan All New document Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4
9. Figure 11 Interrupt clear register Field Definitions 15 1 Interrupt clear ICLEAR 15 1 if written with a 1 will clear the corresponding bit s in the interrupt pending register A read returns zero 31 16 0 Reserved No effect when written to Undefined when read 3 3 3 Secondary interrupt controller The secondary interrupt controller is used add up to 32 additional interrupts to be used by on chip units in system on chip designs Figure 7 shows a block diagram of the interrupt controller IRQ Pending Priority encoder Filtering 32 5 IRQ 31 0 2 4 b gt 1 IRL 4 0 a IRQIO IRQ mask Figure 12 Secondary interrupt controller block diagram 3 3 3 1 Operation The incoming interrupt signals are filtered The filtering condition is positive edge triggered When the condition is fulfilled the corresponding bit is set in the interrupt pending register The pending bits are ANDed with the interrupt mask register and then forwarded to the priority selector If at least one unmasked pending interrupt exists the interrupt output will be driven generating interrupt 10 by default The highest unmasked pending interrupt can be read from the interrupt status register see below Interrupts are not cleared automatically upon a taken interrupt the interrupt handler must reset the pending bit by writing a 1 to the corresponding bit in the interrup
10. Figure 10 14 Space Wire link state diagram The SpaceWire link is always if implemented in the system accordingly able to start up at a 10 Mbit second rate without the need for any configuration by software This makes it possible to configure or initialise a destination node after reset using RMAP commands without the destination node being operational 10 6 2 2 Link transfer and receive rates The SpaceWire Module supports full data bandwidth on the receiver and transmitter for the following clock frequency relations between BusClk and SpwClk SpwClk has a frequency not higher than 2 5 times the BusClk frequency If this relation is not fulfilled the SPW2 will still be functionally correct but the full nominal data bandwidth can not be maintained Occasional NULL tokens will be interspersed with the data Since the SPW2 implements double data rate DDR this corresponds to a maximum SpaceWire transmit bit rate of 5 BusClk Mbit second The nominal transmit data rate is configured via the SPW Clock Division Register The input SpwClk frequency can be divided by a denominator in the range of 0 5 to 32 to produce the nominal transmit data rate Note that the DDR implementation only gives a 50 50 duty cycle when an even value is written in SPW Clock Division Register i e for division rates 0 5 1 5 2 5 3 5 etc thus affecting signal timing The transmit data rate of 10 Mbit second 10 which is required for a reliable lin
11. Figure 50 DSU breakpoint registers BADDR breakpoint address bits 31 2 EX break on instruction BMASK Breakpoint mask see text LD break on data load address ST beak on data store address 3 5 2 6 DSU trap register The DSU trap register is a read only register that indicates which SPARC trap type that caused the processor to enter debug mode When debug mode is force by setting the BN bit in the DSU control register the trap type will be Oxb hardware watchpoint trap 31 13 12 11 4 3 0 RESERVED EM TRAP TYPE 0000 Figure 51 DSU trap register 31 12 Reserved No effect when written to Undefined when read 11 4 8 bit SPARC trap type 12 Error mode EM Set if the trap would have cause the processor to enter error mode 3 0 Reserved No effect when written to Undefined when read Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER 3 5 3 DSU communication link 3 5 3 1 Operation 46 RUAG Aerospace Defence Technology The DSU communication link consists of a UART connected to the AHB bus as a master figure 52 A simple communication protocol is supported to transmit access parameters and data A link command consist of a control byte followed by a 32 bit address followed by optional write data If the LR bit in the DSU control register is set a response byte will be sent after each AHB transf
12. 31 10 9 0 ADDR 31 10 ADDR Base address for circular buffer 9 0 Reserved No effect when written to Undefined when read All bits are cleared to 0 at reset 9 10 8 Transmit Channel Size Register CanTxSIZE R W TABLE 65 Transmit Channel Size Register 31 21 20 6 5 0 SIZE 31 21 Reserved No effect when written to Undefined when read 20 6 SIZE The size of the circular buffer is SIZE 4 messages 5 0 Reserved No effect when written to Undefined when read All bits are cleared to 0 at reset Valid SIZE values are between 0 and 16384 Note that each message occupies four 32 bit words Note that the resulting behavior of invalid SIZE values is undefined Note that only SIZE 4 1 messages can be stored simultaneously in the buffer This is to simplify wrap around condition checking 9 10 9 Transmit Channel Write Register CanTxWR R W TABLE 66 Transmit Channel Write Register 31 20 19 4 3 0 WRITE 31 20 Reserved No effect when written to Undefined when read 19 4 WRITE Pointer to last written message 1 3 0 Reserved No effect when written to Undefined when read All bits are cleared to 0 at reset The WRITE field is written to in order to initiate a transfer indicating the position 1 of the last mes sage to transmit Note that it is not possible to fill the buffer There is always one message position in buffer unused Software is responsible for not over writing the bu
13. _ Application C Node 2 3 Node 3 Figure 10 1 System overview 10 2 Functions e SPW2 SpaceWire Interface Each SPW2 module handles a bi directional non redundant SpaceWire link In reception the module optionally supports VCTP SPW Virtual Channel Transfer Protocol basic RMAP Remote Memory Access Protocol commands and redirects non supported commands and protocols to the software The module supports multiple independent transmit send lists with dual pointers for header and data 10 3 Interfaces The SpaceWire SPW2 Module interfaces one SpaceWire link The SpaceWire link encodes data using one signal pair of data and strobe in each direction The SpaceWire link provides full duplex operation which means the SpaceWire Module may transmit and receive data simultaneously The SpaceWire link handled by the SpaceWire Module is non redundant Two SpaceWire SPW2 Modules could be used each with its own SpaceWire link if redundancy is required Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX T RUAG GAISLER Aerospace Defence Technology 10 4 Module overview This section provides an introduction to the functions implemented by the SpaceWire SPW2 Module 10 4 1 SpaceWire Link SpaceWire is a bi directional serial point to point data link The SpaceWire link is used for transferring data from one node to another node The
14. GAISLER Aerospace Defence Technology 5 7 17 Data Input Register FifoDIN R TABLE 33 Data Input Register 31 16 15 0 DIN 31 16 RESERVED No affect when written to Undefined when read 15 0 DIN Input data FIFOI Din 15 0 All bits are cleared to 0 at reset Note that only the part of FIFOI Din 15 0 not used by the FIFO can be used as general purpose input output see FifoCONF DW Note that only bits dwidth 1 to 0 are implemented 5 7 18 Data Output Register FifoDOUT R W TABLE 34 Data Output Register 31 16 15 0 DOUT 31 16 RESERVED No affect when written to Undefined when read 15 0 DOUT Output data FIFOO Dout 15 0 All bits are cleared to 0 at reset Note that only the part of FIFOO Dout 15 0 not used by the FIFO can be used as general purpose input output see FifoCONF DW Note that only bits dwidth 1 to 0 are implemented 5 7 19 Data Register FifoDDIR R W TABLE 35 Data Direction Register 31 16 15 0 DDIR 31 16 RESERVED No affect when written to Undefined when read 15 0 DDIR Direction FIFOO Dout 15 0 Ob input high impedance 1b output driven All bits are cleared to 0 at reset Note that only the part of FIFOO Dout 15 0 not used by the FIFO can be used as general purpose input output see FifoCONF DW Note that only bits dwidth 1 to 0 are implemented Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009
15. 2009 Aeroflex Gaisler and RUAG RUAG Aerospace Defence Technology 16 Instruction burst fetch IB This bit enables burst fill during instruction fetch 15 Instruction cache flush pending IP This bit is set when an instruction cache flush operation is in progress 14 Data cache flush pending DP This bit is set when a data cache flush operation is in progress 13 12 Instruction cache tag error counter ITE This field is incremented every time an instruction cache tag parity error is detected 11 10 Instruction cache data error counter IDE This field is incremented each time an instruction cache data sub block parity error is detected 9 8 Data cache tag error counter DTE This field is incremented every time a data cache tag parity error is detected 7 6 Data cache data error counter DDE This field is incremented each time an instruction cache data sub block parity error is detected 5 Data Cache Freeze on Interrupt DF If set the data cache will automatically be frozen when an asynchronous interrupt is taken 4 Instruction Cache Freeze on Interrupt IF If set the instruction cache will automatically be frozen when an asynchronous interrupt is taken 3 2 Data Cache state DCS Defines the current data cache state according to the following X0 disabled 01 frozen 11 enabled Set to 00 at reset 1 0 Instruction Cache state ICS Defines the current data cache s
16. AHB master interface Each CAN message occupies 4 consecutive 32 bit words in memory Each CAN message is aligned to 4 words address boundaries i e the 4 least significant byte address bits are zero for the first word in a CAN message The size of the buffer is defined by the CanRxSIZE SIZE field specifying the number of CAN mes sages 4 that fit in the buffer E g CanRxSIZE SIZE 2 means 8 CAN messages fit in the buffer Note however that it is not possible to fill the buffer completely leaving at least one message position in the buffer empty This is to simplify wrap around condition checking E g CanRxSIZE SIZE 2 means that 7 CAN messages fit in the buffer at any given time 9 6 2 Write and read pointers The write pointer CanRxWR WRITE indicates the position 1 of the last CAN message written to the buffer The write pointer operates on number of CAN messages not on absolute or relative addresses The read pointer CanRxRD READ indicates the position 1 of the last CAN message read from the buffer The read pointer operates on number of CAN messages not on absolute or relative addresses The difference between the write and the read pointers is the number of CAN message positions avail able in the buffer for reception The difference is calculated using the buffer size specified by the Can RxSIZE SIZE field taking wrap around effects of the circular buffer into account Examples e There are 2 CAN _ messages availa
17. December 2009 Version 2 4 EROFLEX i RUAG GAISLER 3 5 Aerospace Defence Technology 3 4 13 3 Generation of write protection The results from the two write protection schemes is combined together according to the following scheme If all enabled units operate in block protect mode then a write protect error will be generated if any of the enabled units signal a write protection hit If at least one of the enabled units operates in segment mode then a write protect error will be generated only if all units operating in segment mode signal a write protection hit A write protection error will result in that the AHB write cycle is ended with an AHB error response and the data is not written to the memory The ROM area can be write protected by clearing the write enable bit MCFG1 3 4 14 Using IoBrdyN The IoBrdyN signal can be used to stretch access cycles to the I O area The accesses will always have at least the pre programmed number of waitstates as defined in memory configuration registers 1 amp 2 but will be further stretched until IoBrdyN is asserted IoBrdyN should be asserted in the cycle preceding the last one If bit 29 in memory configuration register 1 is not set then BRDYN is sampled synchronously on the rising edge if the system clock and should be asserted in the cycle preceding the last one If bit 29 is set the BRDYN can be asserted asynchronously with the system clock In this case the read data must be kept
18. RDY non tri state The DAC interface is intended for amongst others the following devices Name Width Type ADS561 10 bit Parallel Data in Analogue out AD565 12 bit Parallel Data in Analogue out AD667 12 bit Parallel Data in Analogue out CS AD767 12 bit Parallel Data in Analogue out CS DAC08 8 bit Parallel Data in Analogue out 6 2 Operation 6 2 1 Interfaces The internal interface on the on chip bus towards the core is a common AMBA APB slave for data access configuration and status monitoring used by both the ADC interface and the DAC interface The ADC address output and the DAC address output signals are shared on the external interface The address signals are possible to use as general purpose input output channels This is only realized when the address signals are not used by either ADC or DAC The ADC data input and the DAC data output signals are shared on the external interface The data input and output signals are possible to use as general purpose input output channels This is only real ized when the data signals are not used by either ADC or DAC Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER RUAG Aerospace Defence Technology Each general purpose input output channel shall be individually programmed as input or output This applies to both the address bus and the data bus The default reset configuration for each general pur p
19. SPW_FFPR Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX 162 RUAG GAISLER Aerospace Defence Technology Register byte address Register name Acronym 0000_OMN0 SPW RxVC Config Register SPW_RxCnf MN 16 4 0 lt lt RxVC 0000_0MN416 SPW RxVC Packet Counter Register SPW_RxPR MN 16 4 5 0 lt lt RxVC 0000_0MN816 SPW RxVC DMA Page Register SPW_RxDPage MN 16 4 S 0 lt lt RxVC 0000_OMNCi SPW RxVC DMA Base Address Register SPW_RxDBAR MN 16 4 3 0 lt lt RxVC 0000_OMN0 SPW RxVC DMA Block SizeRegister SPW_RxDBSR MN 16 4 S 1 0 lt lt RxVC 0000_OMN41 SPW RxVC DMA Offset Register SPW_RxDOR M 16 4 1 0 lt lt RxvC 0000_0MN816 SPW RxVC Status Register SPW_RxSR MN 16 4 S 1 0 lt lt RxVC 0000_OMNC SPW RxVC Current Packet Status Register SPW_RxCPSR MN 16 4 S 1 0 lt lt Rxvc 0000_OMN0j SPW RxVC Interrupt Status Registe
20. Unused No affect when written to Undefined when read 3 0 Valid V When set the corresponding sub block of the cache line contains valid data These bits is set when a sub block is filled due to a successful cache miss a cache fill which results in a memory error will leave the valid bit unset V 0 corresponds to address 0 in the cache line V 1 to address 1 V 2 to address 2 and V 3 to address 3 3 2 4 Cache flushing The instruction and data cache is flushed by executing the FLUSH instruction setting the FI bit in the cache control register or by writing to any location with ASI 0x5 The flushing will take one cycle per cache line and set during which the IU will not be halted but during which the instruction cache will be disabled When the flush operation is completed the cache will resume the state disabled enabled or frozen indicated in the cache control register 3 2 5 Diagnostic cache access Tags and data in the instruction and data cache can be accessed through ASI address space OxC OxD OxE and OxF by executing LDA and STA instructions Address bits making up the cache offset will be used to index the tag to be accessed while the least significant bits of the bits making up the address tag will be used to index the cache set Diagnostic read of tags is possible by executing an LDA instruction with ASI 0xC for instruction cache tags and ASI OxE for data cache tags A cache line and set are indexed by the address bi
21. Version 2 4 EROFLEX A RUAG GAISLER Aerospace Defence Technology 10 6 11 8 Time Codes 10 6 11 8 1 Time Code transmission Time code transmission can be triggered either by the internal SpwTxTick signal which is asserted by an interrupt on the common SpaceWire RTC interrupt bus not being masked by the SPW Transmit Time Code Mask Register hardware triggered time code or by writing the SPW SW Transmit Time Code Register software triggered time code When triggered by SpwTxTick the control part of the time code is defined by the SPW Transmit Time Code Register and when triggered by a register write it is defined by the register write data The counter part of the time code is defined using the SPW Transmit Time Code Register which when read yields the last transmitted time code both control and counter part The TxTime Code link interrupt is issued when a time code is transmitted 10 6 11 8 2 Time Code reception Time codes are received using the SPW Receive Time Code Status Register The RxTime Code link interrupt is issued when a time code has been received and also the internal SpwRxTick signal is asserted which in turn is connected to the SpaceWire RTC common interrupt bus 10 6 12 Error Handling 10 6 12 1 CODEC Status The overall status of the SpaceWire codec can be observed via the SPW CODEC Status Register Note that all fields except LinkState are included for debug purposes only and should not be used in no
22. but the progress should still be observed as above No message transmission is started while the channel is not enabled 9 5 8 Interrupts During transmission several interrupts can be generated e TxLoss Message arbitration lost for transmit could be caused by communcations error as indicated by other interrupts as well e TxErrCntr Error counter incremented for transmit e TxSync Synchronization message transmitted Tx Successful transmission of one message e TxEmpty Successful transmission of all messages in buffer e TxIrq Successful transmission of a predefined number of messages e TxAHBErr AHB access error during transmission e Off Bus off condition e Pass Error passive condition The Tx TxEmpty and TxIrq interrupts are only generated as the result of a successful message trans mission after the CanTxRD READ pointer has been incremented Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 9 6 Reception The receive channel is defined by the following parameters e base address e buffer size e write pointer e read pointer The receive channel can be enabled or disabled 9 6 1 Circular buffer The receive channel operates on a circular buffer located in memory external to the CAN controller The circular buffer can also be used as a straight buffer The buffer memory is accessed via the AMBA
23. e 2 0A which considers 29 bit ID messages as an error e 2 0B Passive which ignores 29 bit ID messages e 2 0B Active which handles 11 and 29 bit ID messages Only 2 0B Active is implemented Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 9 4 95 Status and monitoring The CAN interface provides status and monitoring functionalities including e Transmitter active indicator e Bus Off condition indicator e Error Passive condition indicator e Over run indicator e 8 bit Transmission error counter e 8 bit Reception error counter The status is available via a register and is stored in a circular buffer for each received message Transmission The transmit channel is defined by the following parameters e base address e buffer size e write pointer e read pointer The transmit channel can be enabled or disabled 9 5 1 Circular buffer The transmit channel operates on a circular buffer located in memory external to the CAN controller The circular buffer can also be used as a straight buffer The buffer memory is accessed via the AMBA AHB master interface Each CAN message occupies 4 consecutive 32 bit words in memory Each CAN message is aligned to 4 words address boundaries i e the 4 least significant byte address bits are zero for the first word in a CAN message The size of the buffer is defined by t
24. e OFF Bus off condition e PASS Error passive condition The Rx RxFull and RxIrq interrupts are only generated as the result of a successful message reception after the CanRxWR WRITE pointer has been incremented The OR interrupt is generated when a message is received while a previously received message is still being stored A full circular buffer will lead to OR interrupts for any subsequently received messages The last message stored which fills the circular buffer will not generate an OR interrupt The overrun is reported with the CanSTAT OR bit which is cleared when reading the register The error behavior of the HurriCANe codec is according to the CAN standard which applies to the error counter buss off condition and error passive condition Global reset and enable When the CanCTRL RESET bit is set to 1b a reset of the core is performed The reset clears all the register fields to their default values Any ongoing CAN message transfer request will be aborted potentially violating the CAN protocol When the CanCTRL ENABLE bit is cleared to Ob the HurriCANe core is reset and the configuration bits CanCONF SCALER CanCONF PS1 CanCONF PS2 CanCONE RSJ and CanCONF BPR may be modified When disabled the CAN controller will be in sleep mode not affecting the CAN bus by only sending recessive bits Note that the HurriCANe core requires that 10 recessive bits are received before any reception or transmission can be initiated This can
25. link and performing related synchronisation The state machine determines its next state by monitoring receiver signals that indicate the type of characters received and any receiver errors The state machine enables the transmitter to send NULL characters FCT characters and N char characters 10 6 9 2 Receiver The receiver is responsible for decoding the received data strobe encoded bit stream into SpaceWire characters The receiver reports the type of characters received and any errors encountered to the initialisation state machine The receiver is implemented in two parts a decoder that decodes characters in the receiver clock domain and a synchroniser that synchronises receiver signals to the BusClk clock domain This method ensures all receiver outputs are synchronous to the BusClk clock 10 6 9 3 Receiver Credit Count The receiver credit counter keeps a record of the buffer space available in the receiver RxFIFO and the number of characters that have been requested from the link This allows the SpaceWire CODEC to implement flow control 10 6 9 4 Receiver Error Recovery The receiver error recovery block recovers the receiver credit counters and the receiver RxFIFO after an error occurs After an error an EEP marker is added to the receiver RxFIFO The receiver credit counter must be updated because all previously transmitted FCT characters are discarded at the other end of the link due to error recovery Copyright 2006 2007 20
26. tracing is suspended The size of the trace buffer is 512 lines The trace buffer is 128 bits wide the information stored is indicated in table 11 and table 12 below TABLE 11 Trace buffer data allocation AHB tracing mode Bits Name Definition 127 AHB breakpoint hit Set to 1 if a DSU AHB breakpoint hit occurred 126 Unused 125 9 Time tag The value of the time tag counter 6 95 92 IRL Processor interrupt request input 91 88 PIL Processor interrupt level psr pil 87 80 Trap type Processor trap type psr tt 79 Hwrite AHB HWRITE 78 77 Htrans AHB HTRANS 76 74 Hsize AHB HSIZE 73 71 Hburst AHB HBURST 70 67 Hmaster AHB HMASTER 66 Hmastlock AHB HMASTLOCK 65 64 Hresp AHB HRESP 63 32 Load Store data AHB HRDATA or HWDATA 31 0 Load Store address AHB HADDR TABLE 12 Trace buffer data allocation Instruction tracing mode Bits Name Definition 127 Instruction breakpoint hit Set to 1 if a DSU instruction breakpoint hit occurred 126 Multi cycle instruction Set to 1 on the second and third instance of a multi cycle instruction LDD ST or FPOP 125 9 Time tag The value of the time tag counter 6 95 64 Load Store parameters Instruction result Store address or Store data 63 34 Program counter Program counter 2 Isb bits removed since they are always zero 33 Instruction trap Set to 1 if traced instruction tr
27. 0012 December 2009 Version 2 4 EROFLEX i RUAG GAISLER Aerospace Defence Technology e a successfully prefetched message is copied from the local prefetch buffer to the local fetch buffer when that buffer is freed after a successful transmission An AHB error response occurring on the AMBA AHB bus while a CAN message is being fetched will result in a TxAHBErr interrupt If the CanCONF ABORT bit is set to Ob the channel causing the AHB error will skip the message being fetched from memory and will increment the read pointer No message will be transmitted If the CanCONF ABORT bit is set to 1b the channel causing the AHB error will be disabled CanTx CTRL ENABLE is cleared automatically to 0 b The read pointer can be used to determine which message caused the AHB error Note that it could be any of the four word accesses required to read a message that caused the AHB error If the CanCONF ABORT bit is set to 1b all accesses to the AMBA AHB bus will be disabled after an AMBA AHB error occurs as indicated by the CanSTAT AHBErr bit being 1b The accesses will be disabled until the CanSTAT register is read and automatically clearing bit CanSTAT AHBErr An AHB error response occurring on the AMBA AHB bus while a CAN message is being prefetched will not cause an interrupt but will stop the ongoing prefetch and further prefetch will be prevented temporarily The ongoing transmission of a CAN message from the fetch buffer will not be af
28. 0x80060030 SPW VC Transfer Protocol ID Register 0x80060034 SPW SW Transmit Time Code Register 0x80060040 SPW Status Register 0x80060044 SPW CODEC Status Register 0x80060048 SPW Receive Time Code Status Register 0x80060050 SPW Transmit Time Code Mask Register 0x80060080 SPW First Failing Packet Register 0x80060100 SPW RxVC Config Register 0 0x80060104 SPW RxVC Packet Counter Register 0 0x80060108 SPW RxVC DMA Page Register 0 0x8006010C SPW RxVC DMA Base Address Register 0 0x80060110 SPW RxVC DMA Block SizeRegister 0 0x80060114 SPW RxVC DMA Offset Register 0 0x80060118 SPW RxVC Status Register 0 0x8006011C SPW RxVC Current Packet Status Register 0 0x80060120 SPW RxVC Interrupt Status Register 0 0x80060124 SPW RxVC Interrupt Status Set Register 0 0x80060128 SPW RxVC Interrupt Status Clear Register 0 0x80060140 SPW RxVC Config Register 1 0x80060144 SPW RxVC Packet Counter Register 1 0x80060148 SPW RxVC DMA Page Register 1 0x8006014C SPW RxVC DMA Base Address Register 1 0x80060150 SPW RxVC DMA Block SizeRegister 1 0x80060154 SPW RxVC DMA Offset Register 1 0x80060158 SPW RxVC Status Register 1 0x8006015C SPW RxVC Current Packet Status Register 1 0x80060160 SPW RxVC Interrupt Status Register 1 0x80060164 SPW RxVC Interrupt Status Set Register 1 0x80060168 SPW RxVC Interrupt Status Clear Register 1 0x80060320 SPW TxVC SendList Pointer Register 1 0x80060324 SPW TxVC SendList Size Register 1 0x8006032
29. 12 bit down counting scaler to generate the desired baud rate The scaler is clocked by the system clock and generates a UART tick each time it underflows The scaler is reloaded with the value of the UART scaler reload register after each underflow The resulting UART tick frequency should be 8 times the desired baud rate If the EC bit is set the scaler will be clocked by the LeonPio 3 input rather than the system clock In this case the frequency of LeonPio 3 must be less than half the frequency of the system clock 3 3 5 4 Loop back mode If the LB bit in the UART control register is set the UART will be in loop back mode In this mode the transmitter output is internally connected to the receiver input and the RTSN is connected to the CTSN It is then possible to perform loop back tests to verify operation of receiver transmitter and associated software routines In this mode the outputs remain in the inactive state in order to avoid sending out data 3 3 5 5 Interrupt generation The UART will generate an interrupt under the following conditions when the transmitter is enabled the transmitter interrupt is enabled and the transmitter holding register moves from full to empty when the receiver is enabled the receiver interrupt is enabled and the receiver holding register moves from empty to full when the receiver is enabled the receiver interrupt is enabled and a character with either parity framing break or overrun error is receiv
30. 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 3 PROCESSOR AND PERIPHERALS 3 1 LEON integer unit The LEON integer unit IU implements SPARC integer instructions as defined in SPARC Architecture Manual version 8 It is a new implementation not based on any previous designs The implementation is focused on portability and low complexity 3 1 1 Overview The LEON integer unit has the following features e 5 stage instruction pipeline e Separate instruction and data cache interface e Support for 8 register windows e Multiplier 16x16 e Radix 2 divider non restoring Figure 2 shows a block diagram of the integer unit call branch address I cache X A data address i Impaa A E SS T P S TI E ENE E Piet Meg T es Se E E E A A SS Ne E E A A E SS es amp Fetch em eo SR se et Bod inst 1 epee GPG se es ela Se Se SR Se SOR See See ee See SS ee eS ee ee ee Decode imm tbr wim psr I 1 T Be er ease ee ey BJINSh oS S P Epe j FI rst operan iS SN AS ee eh Se SE he ST I ea Execute m aeni mul div y 32 ex pc 5 P 30 jmpl address Re SS S
31. 31 20 Reserved No effect when written to Undefined when read 19 4 IRQ Interrupt is generated when CanRxWR WRITE IRQ as a consequence of a message reception 3 0 Reserved No effect when written to Undefined when read All bits are cleared to 0 at reset Note that this indicates that a programmed number of messages have been received The field is implemented as relative to the buffer base address scaled with the SIZE field 9 10 18 Receive Channel Mask Register CanRxMASK R W TABLE 75 Receive Channel Mask Register 31 3 9 28 0 ft AM 31 29 Reserved No effect when written to Undefined when read 28 0 AM Acceptance Mask bits set to 1b are taken into account in the comparison between the received message ID and the CanRxCODE AC field All bits are set to 1 at reset Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 9 10 19 Receive Channel Code Register CanRxCODE R W TABLE 76 Receive Channel Code Register 31 30 29 28 0 ag 31 29 Reserved No effect when written to Undefined when read 28 0 AC Acceptance Code used in comparison with the received message All bits are cleared to Oat reset Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0 A message ID is matched when Received ID XOR C
32. 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 3 3 4 Timer unit The timer unit implements two 32 bit timers one 32 bit watchdog and one 10 bit shared prescaler figure 17 timer1 reload prescaler reload timer2 reload Vv prescaler value timeri value gt irq 8 timer2 value gt irq 9 1 ti k gt watchdog gt wDoG A4 1 Figure 17 Timer unit block diagram 3 3 4 1 Operation The prescaler is clocked by the system clock and decremented on each clock cycle When the prescaler underflows it is reloaded from the prescaler reload register and a timer tick is generated for the two timers and watchdog The effective division rate is therefore equal to prescaler reload register value 1 The operation of the timers is controlled through the timer control register A timer is enabled by setting the enable bit in the control register The timer value is then decremented each time the prescaler generates a timer tick When a timer underflows it will automatically be reloaded with the value of the timer reload register if the reload bit is set otherwise it will stop at Oxffffffff and reset the enable bit An interrupt will be generated after each underflow The timer can be reloaded with the value in the reload register at any time by writing a one to th
33. 4 1 for details are forwarded to RxVC 0 for further software processing Note that if the RMAP command support in hardware is not enabled or implemented then all RMAP commands can still be forwarded to RxVC 0 When enabled all RMAP responses are forwarded to RxVC 0 for further software processing Software handling is by default disabled at reset If neither hardware nor software RMAP support is enabled the Spw2 will auto generate responses when required giving Authorisation Error Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX 13 RUAG GAISLER Aerospace Defence Technology Enabling of support for unknown transfer protocols is done in the same way as for software support for RMAP commands and responses using the same resources 10 6 3 2 Identification of received protocol The SpaceWire SPW2 Module identifies an incoming packet using the first bytes of the packet The identification is only performed when four bytes have been received No identification will take place if an EOP or EEP has been detected before this and the packet will be rejected with a header error being reported Packets with no data containing only a single EOP or EEP do not trigger the identification process and are discarded without any error being reported The following steps are performed during the identification Check exact match of the first byte DLA with the internally programm
34. 512 1 ADCONF ADCWS The ADCONE DACWS field defines the number of system clock periods ranging from 1 to 32 for the following timing relationships between the DAC control signals e ADData 15 0 stable before ADWR period e ADWR asserted period e ADData 15 0 stable after ADWR period 6 3 2 Status Register ADSTAT R TABLE 38 Status register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAC DAC DAC ADC ADC ADC ADC NO RDY ON TO NO RDY ON 1 7 RESERVED No affect when written to Undefined when read DACNO DAC conversion request rejected due to ongoing DAC or ADC conversion DACRDY DAC conversion completed DACON DAC conversion ongoing ADCTO ADC conversion timeout ADCNO ADC conversion request rejected due to ongoing ADC or DAC conversion ADCRDY ADC conversion completed ADCON ADC conversion ongoing When the register is read the following sticky bit fields are cleared e DACNO DACRDY e ADCTO ADCNO and ADCRDY Note that the status bits can be used for monitoring the progress of a conversion or to ascertain that the interface is free for usage Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 6 3 3 ADC Data Input Register ADIN R W TABLE 39 ADC Data Input Register 31 16 15 0 ADCIN 31 1
35. Channel Write Register 0x80050030 Transmit Channel Read Register 0x80050034 Transmit Channel Interrupt Register 0x80050038 Receive Channel Control Register 0x80050040 Receive Channel Status Register 0x80050044 Receive Channel Address Register 0x80050048 Receive Channel Size Register 0x8005004C Receive Channel Write Register 0x80050050 Receive Channel Read Register 0x80050054 Receive Channel Interrupt Register 0x80050058 Data Input Register 0x80050060 Data Output Register 0x80050064 Data Direction Register 0x80050068 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER 189 13 3 4 ADC DAC Interface TABLE 88 ADC DAC Interface registers RUAG Aerospace Defence Technology 13 3 5 32 bit Timers Register Address Configuration Register 0x80040000 Status Register 0x80040004 ADC Data Input Register 0x80040010 DAC Data Output Register 0x80040014 Address Input Register 0x80040020 Address Output Register 0x80040024 Address Direction Register 0x80040028 Data Input Register 0x80040030 Data Output Register 0x80040034 Data Direction Register 0x80040038 TABLE 89 32 bit Timers registers Register Address Scaler value 0x80030000 Scaler reload value 0x80030004 Configuration register 0x80030008 Timer latch configuration register 0x8003000C Timer 1 counter value register 0x80030010 Ti
36. Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 RUAG EROFLEX GAISLER Aerospace Defence Technology 6 3 5 Address Input Register ADAIN R TABLE 41 Address Input Register 31 8 7 0 AIN 31 8 RESERVED No affect when written to Undefined when read 7 0 AIN Input address ADAdadr 7 0 All bits are cleared to 0 at reset Note that only bits 7 to 0 are implemented 6 3 6 Address Output Register ADAOUT R W TABLE 42 Address Output Register 31 8 7 0 AOUT 31 8 RESERVED No affect when written to Undefined when read 7 0 AOUT Output address ADAdadr 7 0 All bits are cleared to 0 at reset Note that only bits 7 to 0 are implemented 6 3 7 Address Direction Register ADADIR R W TABLE 43 Address Direction Register 31 8 7 ADIR 31 8 RESERVED No affect when written to Undefined when read 7 0 ADIR Direction ADAddr 7 0 Ob input high impedance 1b output driven All bits are cleared to 0 at reset Note that only bits 7 to 0 are implemented Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX P RUAG GAISLER Aerospace Defence Technology 6 3 8 Data Input Register ADDIN R TABLE 44 Data Input Register 31 16 15 0 DIN 31 16 RESERVED No affect when written to Undefined when read 15 0 DIN Input data ADData 15 0 All bits are cleared to 0 at rese
37. DMA handler channel with this content The data fetched is directly passed on to the TxFIFO for transmission Note that both the DMA start address and size can be misaligned and only the portion starting from DMA start address and the exact number of bytes is transmitted A null size is also possible in which case no bytes are fetched During data fetch the CRC8 checksum is calculated over the full data transmission The result is added after the last data byte transmitted when the Data Type field is set to an RMAP write command Finally an EOP is transmitted The SPW TxVC Send List Size Register is decremented by one The SPW TxVC Send List Pointer Register is incremented by 16 The SPW TxVCStatus Register ChAct is then cleared i e allowing the TxVC arbiter to reassign another channel At send list completion When the last send list entry is completed the TxEOB interrupt is issued and the SPW TxVC Status Register ChTrig is disabled Note that this applies even for zero length send lists Note that there is no automatic generation of the CRC checksum for the header 10 6 6 4 Status Each virtual transmit channel Tx VC provides the following status monitoring e A TxVC Send List Size Register which indicates the number of remaining packets in the send list e A TxVC Send List Pointer Register which points to the current send list element e A TxVC Status Register indicating if the channel is t
38. HurriCANe CAN Controller core The CAN controller supports transmission and reception of sets of messages by use of circular buffers located in memory external to the core Separate transmit and receive buffers are assumed Reception and transmission of sets of messages can be ongoing simultaneously After a set of message transfers has been set up via the AMBA APB interface the DMA controller ini tiates a burst of read accesses on the AMBA AHB bus to fetch messages from memory which are per formed by the AHB master The messages are then transmitted by the ESA HurriCANe CAN Controller When a programmable number of messages have been transmitted the DMA controller issues an interrupt After the reception has been set up via the AMBA APB interface messages are received by the ESA HurriCANe CAN Controller To store messages to memory the DMA controller initiates a burst of write accesses on the AMBA AHB bus which are performed by the AHB master When a programma ble number of messages have been received the DMA controller issues an interrupt The CAN controller can detect a SYNC message and generate an interrupt The SYNC message iden tifier is programmable via the AMBA APB interface The CAN controller supports the draft ECSS high resolution time distribution protocol The CAN controller can transmit and receive messages on either of two CAN busses but only on one at a time The selection is programmable via the AMBA APB interface Note
39. Interrupt registers 31 30 29 28 27 42 2 24 23 2 21 2 19 18 17 46 Tx Loss 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Miss Er Er Sync Syme em Fur ima ima ane ane O OF P Cntr Cntr ty Err Err 31 17 Reserved No effect when written to Undefined when read 16 TxLoss Message arbitration lost during transmission could be caused by communcations error as indicated by other interrupts as well 15 RxMiss Message filtered away during reception 14 TxErrCntr Transmission error counter incremented 13 RxErrCntr Reception error counter incremented 12 TxSyne Synchronization message transmitted 11 RxSync Synchronization message received 10 Tx Successful transmission of message 9 Rx Successful reception of message 8 TxEmpty Successful transmission of all messages in buffer T RxFull Successful reception of all messages possible to store in buffer 6 TxIRQ Successful transmission of a predefined number of messages 5 RxIRQ Successful reception of a predefined number of messages 4 TxXAHBErr AHB error during transmission 3 RxAHBErr AHB error during reception 2 OR Over run during reception 1 OFF Bus off condition 0 PASS Error passive condition All bits in all interrupt registers are reset to Ob after reset Note that the TxAHBErr interrupt is generated in such way that the corresponding read and write pointers are valid for failure anal
40. Module If the SpaceWire SPW2 Module receives such a packet it will be discarded without any side effects 10 5 9 3 SpaceWire Transfer Protocol Packet Structure The structure of the Space Wire Transfer Protocol is defined in RMAPID and it is used for RMAP and other transfer protocol packets The SPW2 module supports structures using non extended protocol identification as shown in the figures below Destination Protocol ID Remaining Data cargo EOP Logical Address Header Header Data 1 byte 1 byte 0 253 bytes 0 16 MiB 1 Figure 10 3 Transfer Protocol packet structure using logical addressing Destination Destination Protocol ID Remaining Data cargo EOP Path Address Logical Address Header Header Data 1 12 bytes 1 byte 1 byte 0 253 0 16 MiB 1 Path Address Length bytes Figure 10 4 Transfer Protocol packet structure using path addressing Where e The path address consists of a list of zero or more bytes called path address lt path address gt lt id 0 gt lt id I gt lt id N 1 gt they are stripped of the packet during its path through a routed network and only the logical address remains when the packet arrives at its destination node e The Logical Address consists of one byte e The Protocol ID consists of one byte e The cargo contains zero or more bytes of header and or data The SPW2 receiver limits the minimum packet size
41. Non matching Destination Logical Address Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX in RUAG GAISLER Aerospace Defence Technology HeadErr One of the following errors was detected while receiving the packet header EOP or EEP detected before the first four bytes could be received For RMAP commands supported by hardware there was a header CRC error or an unexpected number of header bytes in the received packet For VCTP packets the received Virtual Channel Identifier was not within the implemented RxVC range PtclIDErr Protocol Identifier not supported ones FFB3 0 First Failing Packet Byte 3 255 If RMAP this field represents the Command byte If VCTP this field is a dummy byte which is recommended to contain a copy of VCID 255 This field represents the Protocol ID byte First Failing Packet Byte 1 255 Destination Logical Address DLA Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX m RUAG GAISLER Aerospace Defence Technology 10 7 1 6 SpaceWire RxVC registers The virtual receive channels have each a register set as defined below Rx VC 0 is dedicated to RMAP commands and responses and unknown protocols to be processed in software The RMAP hardware supported commands that are executed directly on reception do not use the Rx VC 0 register set except for the confi
42. Ox15 0x84 Oxf6 0x67 0x38 Oxa9 Oxdb Ox4a Ox3f Oxae Oxdc O0x4d 0x36 Oxa7 Oxd5 0x44 0x31 Oxa0 Oxd2 0x43 0x24 Oxb5 Oxc7 0x56 0x23 Oxb2 OxcO 0x51 Ox2a Oxbb Oxc9 0x58 Ox2d Oxbc Oxce Ox5f 0x70 Oxel 0x93 0x02 Ox77 Oxe6 0x94 0x05 0x76 Oxef Ox9d Ox0c Ox79 Oxe8 Ox9a OxO0b Ox6c Oxfd Ox8f Oxle Ox6b Oxfa 0x88 0x19 0x62 Oxf3 Ox81 0x10 0x65 Oxf4 0x86 0x17 0x48 Oxd9 Oxab Ox3a Ox4f Oxde Oxac O0x3d 0x46 Oxd7 Oxa5 0x34 0x41 Oxd0 Oxa2 0x33 0x54 Oxc5 Oxb7 0x26 0x53 Oxc2 Oxb0 0x21 Ox5a Oxch Oxb9 0x28 Ox5d Oxcc Oxbe Ox2f OxeO 0x71 0x03 0x92 Oxe7 0x76 0x04 0x95 Oxee Ox7f 0x0d Ox9c Oxe9 0x78 0x0a 0x9b Oxfc Ox6d Oxlf Ox8e Oxfb Ox6a 0x18 0x89 Oxf2 0x63 0x11 Ox80 Oxf5 0x64 0x16 Ox87 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG 137 G A l S L E R Aerospace Defence Technology Oxd8 0x49 0x3b Oxaa Oxdf 0x4e 0x3c Oxad Oxd6 0x47 0x35 Oxa4 Oxdl 0x40 0x32 0xa3 Oxc4 0x55 0x27 Oxb6 Oxc3 0x52 0x20 Oxbl Oxca Ox5b 0x29 Oxb8 Oxcd Ox5c Ox2e Oxbf 0x90 0x01 0x73 Oxe2 0x97 0x06 0x74 Oxe5 Ox9e 0x0f Ox7d Oxec 0x99 0x08 0x7a Oxeb Ox8c Oxld Ox6f Oxfe Ox8b Oxla 0x68 Oxf9 0x82 0x13 Ox61 Oxf0 0x85 0x14 0X66 Oxf7 Oxa8 0x39 Ox4b Oxda Oxaf Ox3e Ox4c Oxdd Oxa6 0x37 0x45 Oxd4 Oxal 0x30 0x42 Oxd3 Oxb4 0x25 0x57
43. Oxc6 Oxb3 0x22 0x50 Oxcl Oxba Ox2b 0x59 Oxc8 Oxbd Ox2c Ox5e Oxcf hi Computation of the CRC of Data 1 to M should be done as follows CRC 0 0 CRC N RMAP_CRCTable CRC N 1 xor Data N for N 1 to M 10 6 4 3 1 When the hardware support is enabled the SpaceWire SPW2 Module automatically verifies the command header and data CRC according to RMAP for all hardware supported commands as follows Check header CRC checksum for RMAP command Check data CRC checksum for RMAP command Reject the RMAP command if the header CRC checksum is erroneous Reject the RMAP command if the data CRC checksum is erroneous for a Verified Write command Reject superfluous write data in case of late EOP or EEP Hardware supported RMAP commands When the hardware support is enabled the SpaceWire SPW2 Module automatically generates the RMAP response header and data CRCs according to RMAP for the hardware supported commands only 10 6 4 3 2 The SpaceWire SPW2 Module automatically verifies the combined command header and data CRCs for non hardware supported commands as follows Check CRC for the complete RMAP command as calculated over header header checksum and data Issue the CRCDataErr Interrupt if the total checksum is not correct and RMAP software handling is enabled The interrupt is issued after all data have been stored to memory Remove the data CRC checksum byte before the command is store
44. Plug amp play information for APB slaves Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 RUAG Aerospace Defence Technology EROFLEX GAISLER 13 3 Registers 13 3 1 Processor and peripherals TABLE 85 LEON2 FT registers Address Register Address 0x80000000 Memory configuration register 1 0x800000B0 Secondary interrupt mask register 0x80000004 Memory configuration register 2 0x800000B4 Secondary interrupt pending register 0x80000008 Memory configuration register 3 Ox800000B8 Secondary interrupt status register 0x8000000C AHB Failing address register Ox800000B8 Secondary interrupt clear register 0x80000010 AHB status register 0x80000014 Cache control register 0x800000C4 DSU UART status register 0x80000018 Power down register 0x800000C8 DSU UART control register 0x8000001C Write protection register 1 Ox800000CC DSU UART scaler register 0x80000020 Write protection register 2 0x80000024 LEON configuration register 0x800000D0 Write protect start address 1 0x80000040 Timer 1 counter register 0x800000D4 Write protect end address 1 0x80000044 Timer 1 reload register 0x800000D8 Write protect start address 2 0x80000048 Timer 1 control register 0x800000DC Write protect end address 2 0x8000004C Watchdog register 0x80000050 Timer 2 counter register 0x80000054 T
45. Register 0x80050020 Transmit Channel Status Register 0x80050024 Transmit Channel Address Register 0x80050028 Transmit Channel Size Register 0x8005002C Transmit Channel Write Register 0x80050030 Transmit Channel Read Register 0x80050034 Transmit Channel Interrupt Register 0x80050038 Receive Channel Control Register 0x80050040 Receive Channel Status Register 0x80050044 Receive Channel Address Register 0x80050048 Receive Channel Size Register 0x8005004C Receive Channel Write Register 0x80050050 Receive Channel Read Register 0x80050054 Receive Channel Interrupt Register 0x80050058 Data Input Register 0x80050060 Data Output Register 0x80050064 Data Direction Register 0x80050068 RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 5 7 1 Configuration Register FifoCONF R W TABLE 17 Configuration Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Abor DW Par WS t ity Field Description 31 7 RESERVED No affect when written to Undefined when read 6 ABORT Abort transfer on AHB ERROR 5 4 DW Data width 00b none 01b 8 bitFIFOO Dout 7 0 FIFOI Din 7 0 10b 16 bitFIFOO Dout 15 0 FIFOI Din 15 0 11b spare none 3 PARITY Parity type Ob even 1b odd 2 0 WS Number of wait states 0 to 7 All bits are cleared to 0 at reset Note that the transmit or receive
46. Timers Purpose I O Ctrl I F FIFO CAN SpaceWire On Chip Ctrl I F Controller Link Memory Discrete signals ADC DAC FIFO CAN SpaceWire Network Network Figure 1 SpaceWire Remote Terminal Controller RTC block diagram The block diagram shows the functional modules that constitute the SpaceWire RTC The SpaceWire RTC is based on the following on chip buses AMBA AHB bus AMBA APB bus The on chip bus selection is based on the ESA baseline directive for using the open standard AMBA Specification Rev 2 0 as a standard bus See AMBA for details Although not directly shown in the block diagram several of the modules on the AMBA AHB bus also have secondary AMBA APB interfaces for configuration and control purposes These AMBA APB interfaces are logically connected to the AMBA APB bus shown in the block diagram For the modules that are shown in the block diagram as only connected to the AMBA APB bus there are no other hid den connections to the AMBA AHB bus The AMBA AHB bus is controlled by an AHB controller with plug amp play support The controller implements the AMBA AHB bus with the following sideband information e cacheability information e interrupt bus e configuration information e diagnostic information The AMBA APB bus is controlled by an AHB APB bridge with plug amp play support The bridge imple ments the AMBA APB bus with the following sideband information e interrupt bus e configuration information e diag
47. affect when written to Undefined when read 10 8 RxByteCntr Number of bytes in local buffer 6 RxOnGoing Access ongoing 5 RxParity Parity error during reception 4 RxIrq Successful reception of block of data 3 RxFull Reception buffer has been filled 2 RxError AMB AHB access error during reception 1 EF FIFO Empty Flag 0 HF FIFO Half Full Flag Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology All bits are cleared to 0 at reset The following sticky status bits are cleared when the register has been read RxParity RxIrg RxFull and RxError The circular buffer is considered as full when there are two words or less left in the buffer 5 7 12 Receive Channel Address Register FifoRxA DDR R W TABLE 28 Receive Channel Address Register 31 10 9 0 ADDR 31 10 ADDR Base address for circular buffer 9 0 RESERVED No affect when written to Undefined when read All bits are cleared to 0 at reset 5 7 13 Receive Channel Size Register FifoRxSIZE R W TABLE 29 Receive Channel Size Register 31 17 16 6 5 0 SIZE 31 17 RESERVED No affect when written to Undefined when read 16 6 SIZE Size of circular buffer in number of 64 byte blocks 5 0 RESERVED No affect when written to Undefined when read All bits are cleared to 0 at reset Valid SIZE values are 0 and between 1 and 1024 Not
48. and when a predefined number of messages have been transmitted successfully The TxLoss interrupt is issued whenever transmission arbitration has been lost could also be caused by a communications error The TxSync interrupt is issued when a message matching the SYNC Code Filter Register SY NC and SYNC Mask Filter Regis ter MASK registers is successfully transmitted Additional interrupts are provided to signal error con ditions on the CAN bus and AMBA bus 9 5 5 Straight buffer It is possible to use the circular buffer as a straight buffer with a higher granularity than the 1kbyte address boundary limited by the base address CanTxADDR ADDR field While the channel is disabled the read pointer CanTxRD READ can be changed to an arbitrary value pointing to the first message to be transmitted and the write pointer CanTxWR WRITE can be changed to an arbitrary value When the channel is enabled the transmission will start from the read pointer and continue to the write pointer 9 5 6 AMBA AHB error Definition e a message fetch occurs when no other messages is being transmitted e a message prefetch occurs when a previously fetched message is being transmitted e the local fetch buffer holds the message being fetched e the local prefetch buffer holds the message being prefetched e the local fetch buffer holds the message being transmitted by the HurriCANe codec Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100
49. at module instantiation Note that RMAP responses automatically generated when RMAP hardware support is enabled utilize a virtual transfer channel that is not under the control of the software The RMAP response is included in the arbitration of the SpaceWire link and has the highest priority Note that TxVC and RxVC are independent and there is no connection between e g TxVC 3 and Rx VC 3 All read memory accesses of the Tx VC are on word format When possible the SPW2 will perform burst reads in order to preserve internal bus bandwidth 10 6 6 1 Configuration Each virtual transmit channel TxVC provides the following configurability TxVC Send List Pointer Register a pointer to the first word in the send list entry called current position during transmission TxVC Send List Size Register the size of send list counted in number of send list entries indicating the remaining size during transmission TxVC Enable Disable bit The number of send lists is equal to the number of TxVC channels The SpaceWire Module supports send lists containing from 0 element up to 255 elements and send list locations within a 32 bit addressing range Note that extended addressing cannot be used when defining a send list location i e page address equal to zero is assumed A send list entry consists of four words the first word being the Header Size Type and Page word The fields and usage of the fields is defined in 10 5 9 6 N
50. be caused either by no unit sending on the CAN bus or by random bits in message transfers Interrupt Three interrupts are implemented by the CAN interface Name Description IRQ Common output from interrupt handler TxSYNC Synchronization message transmitted RxSYNC Synchronization message received Vendor and device id The module has vendor id 0x01 Gaisler Research and device id 0x34 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 RUAG Aerospace Defence Technology EROFLEX GAISLER 9 10 Registers The GRHCAN is programmed through registers mapped into APB address space TABLE 57 GRHCAN registers Register Address Configuration Register 0x80080000 Status Register 0x80080004 Control Register 0x80080008 SYNC Mask Filter Register 0x80080018 SYNC Code Filter Register 0x8008001C Pending Interrupt Masked Status Register 0x80080100 Pending Interrupt Masked Register 0x80080104 Pending Interrupt Status Register 0x80080108 Pending Interrupt Register 0x8008010C Interrupt Mask Register 0x80080110 Pending Interrupt Clear Register 0x80080114 Transmit Channel Control Register 0x80080200 Transmit Channel Address Register 0x80080204 Transmit Channel Size Register 0x80080208 Transmit Channel Write Register 0x8008020C Transmit Channel Read Register 0x80080210 Transmit Channel Interrupt Register 0x80080
51. can be routed to a dedicated virtual receive channel RxVC 0 for further processing As an additional service any RMAP command or response received on RxVC 0 is also checked for combined header and data checksum errors which are reported as an interrupts to software Any failure is logged in the First Failing Packet Register described in 10 6 8 The transmitter comprises one or more Virtual Transmit Channels TxVC Any type of packets can be transmitted using these channels The transmitters provide support for data checksum generation for RMAP commands and responses The SpaceWire SPW2 Module is able to perform simultaneous transfers as described hereafter Transmit an RMAP command and simultaneously receive an RMAP response Receive verify and execute an RMAP command and simultaneously start transmitting an RMAP response if so required by the command Transmit an RMAP command and simultaneously receive a Virtual Channel Transfer Protocol packet VCTP Receive verify and start executing an RMAP command and simultaneously transmit a Virtual Channel Transfer Protocol packet VCTP Transmit a Virtual Channel Transfer Protocol packet VCTP and simultaneously receive an RMAP response Transmit an RMAP response and simultaneously receive a Virtual Channel Transfer Protocol packet VCTP Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX m RUAG GAISLER A
52. counter 31 30 Reserved No effect when written to Undefined when read The trace buffer control register contains two counters that contain the next address of the trace buffer to be written Since the buffer is circular it actually points to the oldest entry in the buffer The counters are automatically incremented after each stored trace entry 31 26 25 24 23 12 11 FA TA TI AHB INDEX INST INDEX 31 27 Reserved No effect when written to Undefined when read 11 0 Instruction trace index counter 23 12 AHB trace index counter 24 Trace instruction enable 25 Trace AHB enable Figure 48 Trace buffer control register 26 AHB trace buffer freeze If set the AHB trace buffer will be frozen when the processor enters debug mode When both instructions and AHB transfers are traced mixed mode tracing the buffer is divided on two halves Instructions are stored in the lower half and AHB transfers in the upper half of the buffer The MSB bit of the AHB index counter is then automatically kept high while the MSB of the instruction index counter is kept low When the AF bit in the trace control register is set AHB tracing is stopped when the processor is in debug mode When AF is cleared tracing continues until the AHB trace enable bits are cleared 3 5 2 3 DSU memory map DSU memory map can be seen in table 13 below TABLE 13 DSU address space
53. detected during the reception of the rest of the packet After the identification the incoming packet is handled by one of the following Remote Memory Access Protocol RMAP handler implemented in hardware or Virtual Receive Channel RxVC or Other protocols which are redirected to software The Remote Memory Access Protocol RMAP protocol is implemented in hardware with some constraints as described in 10 6 4 1 Each received command that has passed the identification process is checked for header checksum consistency and for a matching Destination Key Also the data checksum is checked for write commands that require verification before the command is executed For all other write commands the data is checked in parallel with the execution and a potential error is reported in the RMAP response if required by the incoming command Data are read or written from and to the internal bus using directed memory accesses An RMAP response is generated for all read commands and for write commands if so required by the incoming command No software support is required for these operations Any failures logged in the First Failing Packet Register described in 10 6 8 The Virtual Channel Transfer Protocol VCTP protocol implements one or more virtual receive channels RxVC The Virtual Channel Identifier in the VCTP header is used for routing the packet to the corresponding RxVC Note that unknown protocols and RMAP commands and responses
54. executed automatically in hardware is configured using the SPW RMAP Destination Key Register Note that the destination key is not checked by hardware for RMAP commands or responses that are forwarded to software for further processing 10 6 10 5 RMAP software support configuration The SpaceWire SPW2 Module implements software support for the reception of Remote Memory Access Protocol RMAP commands and header The software support is enabled and disabled using the SPW RxVC Config Register 0 The virtual receive channel Rx VC 0 can be configured individually whether received packets should be stored contiguously in memory or whether the end of each packet is to be padded up to the closest 32 bit word boundary Padding is done with unknown arbitrary content The configuration is done in the SPW RxVC Config Register 0 10 6 10 6 Unknown protocol support configuration The SpaceWire SPW2 Module implements software support for the reception of unknown transfer protocols The software support is enabled and disabled using the SPW RxVC Config Register 0 The user can configure the SPW2 to interpret all incoming messages of four bytes or more as being of an unknown protocol by setting SPW RxVC Config Register 0 ForceUnk Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 10 6 11 Operation Usage 10 6 11 1 Li
55. header Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX m RUAG GAISLER Late EOP Early EEP Late EEP 10 5 8 AHB AMBA APB ASIC BPS CMOS CRC DMA EEP EOP EOM EOB ESA FFPR FPGA HW Id IO IP LS LSB LSW LVDS MS MSB MSW MTBF NA PROM RAM SPW RMAP RxVC SRAM SW TBC TBD TxVC VC VCID Aerospace Defence Technology EOP has been received after more data than expected from the RMAP command header EEP has been received after less data than expected from the RMAP command header EEP has been received after more data than expected from the RMAP command header Abbreviations Advanced High performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Application Specific Integrated Circuit Bit Per Second Complementary Metal Oxide Semiconductor Cyclic Redundancy Code Direct Memory Access Error End of Packet End Of Packet End Of Message End Of Block European Space Agency First Failing Packet Register Field Programmable Gate Array Hardware Identifier Input Output Intellectual Property Least Significant Least Significant Bit Least Significant Word Low Voltage Differential Signalling Most Significant Most Significant Bit Most Significant Word Mean Time Between Failures Not Applicable Programmable Read Only Memory Random Access Memory SpaceWire Remote Memory Access Protocol Virtu
56. header or data field of an RMAP command or response both intended to be processed by software Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX i RUAG GAISLER Aerospace Defence Technology 10 7 1 7 SpaceWire TxVC registers The Tx channels each has a register set as defined below TxVC 0 is dedicated to RMAP read and responses and uses the same structure but need no register accesses to execute a transmission The TxVC 0 registers with the exception of SPW TxVC Status Register 0 are included for debug and test purposes only and should not be used in normal operation SPW _TxVC SendList Pointer Register SPW_TxSLPR R W 31 0 SendList Pointer 0 MSB LSB Function This register is used to define the position of the send list for the virtual transmit channel and for monitoring the transmit progress by indicating the current sent list entry The SendList Pointer field points to the first word in the send list entry called current position during transmission The pointer is incremented by 16 after the send list entry has been successfully transmitted Timing Constraints This register must not be written to during transmission The pointer must be word aligned For TxVC 0 writes to this register have no effect Field Description Send List Address to the present element in t
57. implemented as relative to the buffer base address scaled with SIZE field The READ field is written to in order to release the receive buffer indicating the position 1 of the last byte that has been read out Note that it is not possible to fill the buffer There are always at least two word positions unused in the buffer Software is responsible for not over reading the buffer on wrap around i e setting WRITE READ Note that the LSB may be ignored for 16 bit wide FIFO devices 5 7 16 Receive Channel Interrupt Register FifoRxIRQ R W TABLE 32 Receive Channel Interrupt Register 31 16 15 0 IRQ 31 16 RESERVED No affect when written to Undefined when read 15 0 IRQ Pointer 1 to a byte address to which the write of received data shall result in an interrupt All bits are cleared to 0 at reset Note that this indicates that a programmed amount of data has been received The field is implemented as relative to the buffer base address scaled with SIZE field Note that the LSB may be ignored for 16 bit wide FIFO devices Note that by setting the IRQ field to match the value of the Receive Channel Write Regis ter WRITE field plus the value of the Receive Channel Status Register RxByteCntr field an emp tying to the external memory is forced of any data temporarily stored in the local buffer Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG
58. input provides the data to the DSU communication link receiver LeonDsuBre I DSU break A low to high transition on this active high input will generate break condition and put the processor in debug mode LeonDsuAct O DSU active This active high output is asserted when the processor is in debug mode and controlled by the DSU LeonPio 15 0 IO LEON Parallel Input Output These bi directional signals can be used as inputs or outputs to control external devices Gpio 23 0 IO General Purpose Input Output TimeClk I External timer clock TimeTrig 2 1 O External timer trigger Asserted for 8 system clock periods CanTx 1 0 O CAN transmit CanRx 1 0 I CAN receive CanEn 1 0 O CAN transmit enable ADData 15 0 IO ADC DAC data ADAddr 7 0 IO ADC DAC address ADWr O DAC write strobe ADCs O ADC chip select ADRc O ADC read convert ADRdy I ADC ready ADTrig I ADC trigger MemA 22 0 O Memory interface address These active high outputs carry the address during accesses on the memory bus When no access is performed the address of the last access is driven also internal cycles MemD 31 0 IO Memory interface data MemD 31 0 carries the data during transfers on the memory bus The processor only drives the bus during write cycles During accesses to 8 bit areas only MemD 31 24 are used RTC 100 0012 December 2009 Version 2 4 k RUAG EROFLEX GAISLER Aero
59. is configured Ifthe packet Protocol ID does not correspond to neither RMAP nor VCTP and no software handling is enabled for Rx VC 0 Ifthe packet belongs to the VCTP protocol and has a virtual channel address that is outside the implemented or allowed range or if the virtual channel is disabled Ifthe RMAP command byte is either illegal or not supported in hardware and no software handling is enabled for Rx VC 0 Errors are reported in the First Failing Packet Register and SPW Link Interrupt Status Register described in detail in 10 6 8 and 10 7 1 1 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX r RUAG GAISLER Aerospace Defence Technology Note that the identification process is always performed even if no hardware support for RMAP commands is implemented or enabled The continued checking of the full RMAP header is done by the RMAP handler in either hardware or software E g the Destination Key is checked by hardware in hardware supported commands and by software in software supported commands see 10 6 4 The identification is considered finished after the four first bytes have been examined Note that the RMAP command header CRC checksum need not be correct during the identification The CRC checksum is checked subsequently by the RMAP handler in either hardware or software Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012
60. is read Reading the Pending Interrupt Masked Register yields the contents of the Pending Interrupt Register masked with the contents of the Interrupt Mask Register Selected bits can be cleared by writing ones to the bits that shall be cleared to the Pending Interrupt Clear Register Forcing interrupts When the Pending Interrupt Register is written the resulting value is the original contents of the register logically OR ed with the write data This means that writing the register can force set an interrupt bit but never clear it Reading interrupt status Reading the Pending Interrupt Status Register yields the same data as a read of the Pending Interrupt Register but without clearing the contents Reading interrupt status of unmasked bits Reading the Pending Interrupt Masked Status Register yields the contents of the Pending Interrupt Register masked with the contents of the Interrupt Mask Register but without clearing the contents The interrupt registers comprise the following e Pending Interrupt Masked Status Register CanPIMSR R e Pending Interrupt Masked Register CanPIMR R e Pending Interrupt Status Register CanPISR R e Pending Interrupt Register CanPIR R W e Interrupt Mask Register CanIMR R W e Pending Interrupt Clear Register CanPICR W Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER RUAG Aerospace Defence Technology TABLE 77
61. multi cycle instruction the IU is halted until the line fill is completed If the IU executes a control transfer instruction branch CALL JMPL RETT TRAP during the line fill the line fill will be terminated on the next fetch If instruction burst fetch is enabled instruction streaming is enabled even when the cache is disabled In this case the fetched instructions are only forwarded to the IU and the cache is not updated If a memory access error occurs during a line fill with the IU halted the corresponding valid bit in the cache tag will not be set If the IU later fetches an instruction from the failed address a cache miss will occur triggering a new access to the failed address If the error remains an instruction access error trap tt 0x1 will be generated 3 2 2 2 Instruction cache tag A instruction cache tag entry consists of several fields as shown in figure 4 Tag for 4 kbyte set 16bytes line 31 2 ou 8 7 0 ATAG 0000 VALID Figure 4 Instruction cache tag layout Field Definitions 31 12 Address Tag ATAG Contains the tag address of the cache line 11 8 Unused No affect when written to Undefined when read 7 0 Valid V When set the corresponding sub block of the cache line contains valid data These bits are set when a sub block is filled due to a successful cache miss a cache fill which results in a memory error will leave the valid bit unset A FLUSH instruction will clear all valid
62. nominal transmit data rate is changed immediately when a write access is made to the SPW Clock Division Register The nominal data rate can be changed without disrupting the link even after link start up 10 6 2 3 Link status The SPW CODEC Status Register reflects the state of the CODEC Note that all fields except LinkState TxParked and RxParked are included for debug purposes only and should not be used in normal operation The detected link interface errors are issued as interrupts after the corresponding events are reported from the SpaceWire CODEC and are reported in the SPW Link Interrupt Status Register See 10 7 1 1 for details 10 6 3 SpaceWire transfer protocol support in the receiver The receiver in the SpaceWire SPW2 Module supports the Protocol Identification process defined in RMAPID The identification is performed on all data received over the SpaceWire link and the result is used for routing the incoming data to the corresponding protocol handler Note that the SpaceWire SPW2 Module does not support any type of protocol based on other kinds of protocol identification concepts However the Protocol Identification process can be bypassed by setting the SPW Rx VC Config Register 0 ForceUnk thus causing all packets of four bytes or more to be treated as an unknown transfer protocol see 10 6 5 The following SpaceWire Transfer Protocols are explicitly identified by the hardware Virtual Channel Transfer P
63. not supported 10 6 4 2 Software supported RMAP commands and responses Since the protocol identification described in 10 6 3 2 is performed only on the four first bytes of a packet only the Type and Command field byte is used for determine which commands can be handled in hardware and which should be forwarded to memory for further software processing provided that this support is enabled The following RMAP commands are therefore forwarded to software when hardware support is enabled Read commands with No Increment Address setting Write and Verified Write commands with No Increment Address setting All Read Modify Write commands The following RMAP commands are therefore not forwarded to software when hardware support is enabled and are thus rejected during header verification Any otherwise hardware supported command with and Extended Address value larger than OF j Verified Write commands with any other block size than 4 bytes or with a non word aligned address RMAP commands and responses with the Reserved bit of the Command amp Type field set and RMAP responses with the Ack bit cleared are rejected and thus not forwarded to software Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX ee RUAG GAISLER Aerospace Defence Technology 10 6 4 3 Header and data verification The SpaceWire SPW2 Module supports command header and data field ve
64. of a successful data transmission after the FifoTxRD READ pointer has been incremented 5 5 Reception The receive channel is defined by the following parameters e base address e buffer size e write pointer e read pointer The receive channel can be enabled or disabled 5 5 1 Circular buffer The receive channel operates on a circular buffer located in memory external to the FIFO controller The circular buffer can also be used as a straight buffer The buffer memory is accessed via the AMBA AHB master interface The size of the buffer is defined by the FifoRxSIZE SIZE field specifying the number 64 byte blocks that fit in the buffer E g FifoRxSIZE SIZE 1 means 64 bytes fit in the buffer Note however that it is not possible for the hardware to fill the buffer completely leaving at least two words in the buffer empty This is to simplify wrap around condition checking E g FifoRxSIZE SIZE 1 means that 56 bytes fit in the buffer at any given time 5 5 2 Write and read pointers The write pointer FifoRxWR WRITE indicates the position 1 of the last byte written to the buffer The write pointer operates on number of bytes not on absolute or relative addresses The read pointer FifoRxRD READ indicates the position 1 of the last byte read from the buffer The read pointer operates on number of bytes not on absolute or relative addresses The difference between the write and the read pointers is the number of bytes availa
65. play information GRLIB devices contain a number of plug amp play information words which are included in the AHB records they drive on the bus see the GRLIB user s manual for more information These records are combined into an array which is connected to the AHB controller unit The plug amp play information is mapped on a read only address area mapped on address OxFFFFFO0O OXFFFFFFFF The master information is placed on the first 2Kbyte of the block while the slave information id placed on the second 2Kbyte block Each unit occupies 32 bytes which means that the area has place for 64 masters and 64 slaves Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 A R RUAG wIEROFLEX GAISLER Aerospace Defence Technology 31 24 23 1211109 5 4 0 Identification Register 00 VENDOR ID DEVICE ID 00 VERSION IRQ 04 USER DEFINED 08 USER DEFINED oc USER DEFINED BARO 10 ADDR 00 P C MASK TYPE BAR1 14 ADDR 00 P C MASK TYPE Bank Address Registers BAR2 18 ADDR 00 P C MASK TYPE BAR3 1C ADDR 00 P C MASK TYPE 31 20 19 18 17 16 15 4 3 0 TYPE P Prefetchable C Cacheable Figure 77 AHB plug amp play information record Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG 0001 APB I O space 0010 AHB Memory space 0011 AHB I O space RTC 100 0012 December 2009 Version 2 4 EROFLEX 7 RUAG GAISLER Aerospace Defe
66. register 0x800000A4 T O port direction register 0x800000A8 T O port interrupt config register 1 0x800000AC T O port interrupt config register 2 3 3 2 Interrupt controller The LEON interrupt controller is used to prioritize and propagate interrupt requests from internal or external devices to the integer unit In total 15 interrupts are handled divided on two priority levels Figure 7 shows a block diagram of the interrupt controller Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX i RUAG GAISLER Aerospace Defence Technology IRQ Pending DSU trace it Pani riority 10 15 encoder 32 2nd IRQ pay gt Lo y controller D gt 4 Timer 2 gt IRL 3 0 Timer 1 aS IR IRQ Priority 16 Irq amp trig 4 5 6 7 RO mask select LeonPio 15 6 select 10 12 13 15 UART 1 Ja UART 2 2y AHB error ato Figure 7 Interrupt controller block diagram 3 3 2 1 Operation When an interrupt is generated the corresponding bit is set in the interrupt pending register The pending bits are ANDed with the interrupt mask register and then forwarded to the priority selector Each interrupt can be assigned to one of two levels as programmed in the interrupt level register Level 1 has higher priority than level 0 The interrupts are prioritised within each
67. stable until the de assertion of IoOeN The use of IoBrdyN can be enabled separately for the I O area 3 4 15 Access errors An access error can be signalled by asserting the MemBExcN signal which is sampled together with the data If the usage of MemBEXcN is enabled in memory configuration register 1 an error response will be generated on the internal AMBA bus MemBEXxcN can be enabled or disabled through memory configuration register 1 and is active for all areas PROM I O an RAM datal data2 lead out Mend ya T p MemCsN nn T ToOeN nn Coa Coe T MemD MemBExcN _ ES Figure 45 Read cycle with MemBExcN Hardware debug support 3 5 1 Overview The LEON processor includes hardware debug support to aid software debugging on target hardware The support is provided through two modules a debug support unit DSU and a debug communication link DCL The DSU can put the processor in debug mode allowing Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology read write access to all processor registers and cache memories The DSU also contains a trace buffer which stores executed instructions and or data transfers on the AMBA AHB bus The debug communications link implements a simple read write protocol and uses standard asynchronous UART communications RS232C LEON processor
68. this time WR Write The result of any ALU logical shift or cache read operations are written back to the register file Table 1 lists the cycles per instruction assuming cache hit and no load interlock TABLE 1 Instruction timing Instruction Cycles JMPL 2 Double load 2 Single store 2 Double store 3 SMUL UMUL 5 SDIV UDIV 35 Taken Trap 4 Atomic load store 3 All other instructions 1 3 1 3 Multiply instructions The LEON processor supports the SPARC integer multiply instructions UMUL SMUL UMULCC and SMULCC These instructions perform a 32x32 bit integer multiply producing a 64 bit result SMUL and SMULCC performs signed multiply while UMUL and UMULCC eee unsigned multiply UMULCC and SMULCC also set the condition codes to reflect the result 3 1 4 Divide instructions Full support for SPARC V8 divide instructions is provided SDIV UDIV SDIVCC UDIVCC The divide instructions perform a 64 by 32 bit divide and produce a 32 bit result Rounding and overflow detection is performed as defined in the SPARC V8 standard 3 1 5 Register file SEU protection To prevent erroneous operations from SEU errors in the main register file each word is protected using a 7 bit EDAC checksum Checking of the EDAC bits is done every time a fetched register value is used in an instruction If a correctable error is detected the erroneous data is corrected before being used At the same time the corr
69. used for observing if the channel is triggered and if the channel is active transmitting a message The overall progress of transmission can be observed using the SPW Status Register which indicates which channel is active transmitting a message During nominal transmission interrupts are issued to indicate that a send list has been completed TxEOB interrupt If an error is detected which un triggers the channel then this is reported by issuing an error interrupt FlushAbort and DmaRdErr interrupts This information can be observed using the SPW TxVC Interrupt Status Register To disable or prematurely un trigger a virtual transmit channel the complete SpaceWire link needs to be disconnected and the Tx flushed using the SPW CODEC Configuration Register 10 6 11 4 RMAP command reception in hardware Reception of RMAP commands that are executed in hardware does not require any software support more than the enabling of this support as described in 10 6 10 4 The progress of the reception of RMAP commands can be observed using the SPW First Failing Packet Register indicating if an error has occurred This is also indicated by the issuing of the PktRej link interrupt For hardware supported RMAP commands responses are generated and transmitted automatically when required by the protocol New packets of all protocol types can be received and handled in parallel with the response transmission The only limitation is that
70. 0 0x80070108 SPW RxVC DMA Page Register 0 0x8007010C SPW RxVC DMA Base Address Register 0 0x80070110 SPW RxVC DMA Block SizeRegister 0 0x80070114 SPW RxVC DMA Offset Register 0 0x80070118 SPW RxVC Status Register 0 0x8007011C SPW RxVC Current Packet Status Register 0 0x80070120 SPW RxVC Interrupt Status Register 0 0x80070124 SPW RxVC Interrupt Status Set Register 0 0x80070128 SPW RxVC Interrupt Status Clear Register 0 0x80070140 SPW RxVC Config Register 1 0x80070144 SPW RxVC Packet Counter Register 1 0x80070148 SPW RxVC DMA Page Register 1 0x8007014C SPW RxVC DMA Base Address Register 1 0x80070150 SPW RxVC DMA Block SizeRegister 1 0x80070154 SPW RxVC DMA Offset Register 1 0x80070158 SPW RxVC Status Register 1 0x8007015C SPW RxVC Current Packet Status Register 1 0x80070160 SPW RxVC Interrupt Status Register 1 0x80070164 SPW RxVC Interrupt Status Set Register 1 0x80070168 SPW RxVC Interrupt Status Clear Register 1 0x80070320 SPW TxVC SendList Pointer Register 1 0x80070324 SPW TxVC SendList Size Register 1 0x80070328 SPW TxVC Status Register 1 0x8007032C SPW TxVC Interrupt Status Register 1 0x80070330 SPW TxVC Interrupt Status Set Register 1 0x80070334 SPW TxVC Interrupt Status Clear Register 1 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX e RUAG GAISLER Aerospace Defence Technology 13 4 Interrupts 13 4 1 Inte
71. 0 OxFFFFFO7F 32 Space Wire Interface 0 Rx SPW2 OxFFFFFO080 OxFFFFFO9F 32 Space Wire Interface 0 Tx SPW2 OxFFFFFOAO OxFFFFFOBF 32 Space Wire Interface 1 Rx SPW2 OxFFFFFOCO OxFFFFFODF 32 Space Wire Interface 1 Tx SPW2 OxFFFFFOEO 0xFFFFFOFF 32 CAN interface GRHCAN Table 82 Plug amp play information for AHB masters The Space Wire RTC plug amp play information for the slaves on the internal AMBA AHB bus is shown in the table below Address range Size Mapping Module OxFFFFF800 OxFFFFF8 1F 32 APB Controller APB Controller OxFFFFF820 OxFFFFF83F 32 Memory controller LEON2 FT OxFFFFF840 OxFFFFF85F 32 DSU LEON2 FT OxFFFFF860 0OxFFFFF87F 32 On Chip Memory FTAHBRAM Table 83 Plug amp play information for AHB slaves The SpaceWire RTC plug amp play information for the slaves on the internal AMBA APB bus is shown in the table below Address range Size Mapping Module Ox800FFO000 0x800FF007 8 LEON2 FT registers LEON2 FT 0x800FF008 Ox800FFOOF 8 On Chip Memory registers FTAHB 0x800FF010 Ox800FFO17 8 24 bit GPIO GPPULSE Ox800FFO18 Ox8OOFFO1F 8 32 bit Timers GRTIMER Ox800FFO020 0x800FF027 8 ADC DAC interface GRADCDAC Ox800FF028 0x800FF02F 8 FIFO interface GRFIFO Ox800FF030 Ox800FF037 8 SpaceWire Interface 0 SPW2 Ox800FF038 Ox800FFO3F 8 SpaceWire Interface 1 SPW2 Ox800FF040 Ox800FF047 8 CAN interface GRHCAN Table 84
72. 0 6 10 Initialisation 10 6 10 1 Space Wire link configuration The SpaceWire link is configured at reset to automatically start up It is possible to configure the link not to automatically start up after a link disconnection This is done with the SPW CODEC Configuration Register See 10 6 2 10 6 10 1 1 SpaceWire transmit Clock configuration The SpaceWire link nominal data transfer rate is configured with the SPW Clock Division Register The default nominal transfer rate after reset matches the link start up transfer data rate which is configured with configuration inputs After successful start up the link will use the nominal transfer data rate The nominal data transfer rate can be changed during nominal operation In the case of a link disconnection the following link start up will take place using the link start up transfer data rate See 10 6 2 10 6 10 2 SpaceWire logical address configuration A SpaceWire node in a SpaceWire network has dedicated logical address when logical addressing is used After a typical network start up all nodes have a default logical address of FE16 and explicit path addressing is used to reach each node The logical address can then be programmed for each node When completed path addressing is not longer required in the network and only logical addressing is used The SpaceWire SPW2 Module logical address is stored in SPW RxVC Config Register 0 Note that although this register is dedicated
73. 009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX i RUAG GAISLER Aerospace Defence Technology Incoming packets are inspected as their header reaches the end of the second level reciver FIFO I e if the first packet to arrive is directed to an enabled but not triggered channel it will remain in the first two FIFOs blocking the following packets And if the first packet to arrive is directed to a disabled or not implemented channel it will be flushed out immediately letting the next packets through On the transmitter side three levels of buffering are used The first buffer is used to allow multiple words to be read from memory before being transferred to the second FIFO The second FIFO is a word to byte re formatter used to transfer words between the BusClk and SpwClk clock domains The third FIFO the TxFIFO is directly controlled by the CODEC and has byte width The SpaceWire Credit Count is defined using this Note that there is additional protocol dependent data buffering on both the receiver and transmitter side before reaching the internal bus The buffer size figures above should thus be regarded as estimates and should never be used for computing exactly the amount of data located in various buffers at a given time Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX 151 RUAG GAISLER Aerospace Defence Technology 1
74. 08 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX m RUAG GAISLER Aerospace Defence Technology 10 6 9 5 Transmitter The transmitter is responsible for transmitting L Chars and N chars over a link using data strobe encoding The interface state machine determines which type of character the transmitter can send over the link The transmitter accepts N char characters and end of packet markers from the transmitter TxFIFO N char characters are transmitted when there is data in the TxFIFO and the transmitter has credit to send at least one more N char The transmitter sends an FCT character for each block of space for eight N chars in the receive RxFIFO As the host system reads out data from the receive RxFIFO the transmitter sends more FCT characters to indicate that the receiver has room to receive eight more N chars The transmitter sends NULL characters when there is no other information to send 10 6 9 6 Transmitter Clock Generator The transmitter clock enable generator is responsible for generating the variable transmitter bit rate and default data signalling rate dependent on the configuration 10 6 9 7 Transmitter Credit Counter The transmitter credit counter holds a count register that indicates the number of SpaceWire N char characters that can be sent along the link 10 6 9 8 Transmitter Error Recovery The transmitter error recovery module recovers the transmitter TxFIFO after an error o
75. 113 SE 10 5 11 Reference Documents ESA_DMR ESA ASIC Design and Manufacturing Requirements WDN PS 700 Issue 2 October 1994 CODEC_Desc SpaceWire CODEC VHDL Functional Description Issue 1 2 3 March 2004 CODEC SpaceWire CODEC VHDL User Manual Issue 1 1 19 April 2004 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX m RUAG GAISLER Aerospace Defence Technology 10 6 Functional behaviour This section describes the SpaceWire SPW2 Module software interface The description is divided into subsections which treats different parts of the SpaceWire SPW2 Module The description is divided into General Short introductory description of the SPW2 module SpaceWire link Describes the low level handling of the SpaceWire link SpaceWire transfer protocol support in the receiver Describes protocol identification and support enabling Remote Memory Access Protocol RMAP Describes the handling of incoming RMAP commands Virtual Receive Channels RxVC Describes the handling of incoming VCTP packets Virtual Transmit Channels TxVC Describes the handling of send lists and transmission of VCTP packets and RMAP commands Time Codes Describes the handling of time codes First Failing Packet Register Describes the handling of the First Failing Packet Register SpaceWire CODEC Describes the handling of the SpaceWire CODEC Initialisation Describes the initi
76. 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology A data transmission will begin with a fetch of the data from the circular buffer to a local buffer in the FIFO controller After a successful fetch a write access will be performed to the FIFO The read pointer FifoTxRD READ is automatically incremented after a successful transmission tak ing wrap around effects of the circular buffer into account If there is at least one byte available in the circular buffer a new fetch will be performed If the write and read pointers are equal no more prefetches and fetches will be performed and trans mission will stop Interrupts are provided to aid the user during transmission as described in detail later in this section The main interrupts are the TxError TxEmpty and TxIrq which are issued on the unsuccessful trans mission of a byte due to an error condition on the AMBA bus when all bytes have been transmitted successfully and when a predefined number of bytes have been transmitted successfully Note that 32 bit wide read accesses past the address of the last byte or halfword available for transmis sion can be performed as part of a burst operation although no read accesses are made beyond the cir cular buffer size All accesses to the AMBA AHB bus are performed as two consecutive 32 bit accesses in a burst or as a single 32 bit access in case of an AMBA AHB bus error 5 4 5 Straight buffer It is possible to use the ci
77. 214 Receive Channel Control Register 0x80080300 Receive Channel Address Register 0x80080304 Receive Channel Size Register 0x80080308 Receive Channel Write Register 0x8008030C Receive Channel Read Register 0x80080310 Receive Channel Interrupt Register 0x800803 14 Receive Channel Mask Register 0x80080318 Receive Channel Code Register 0x8008031C Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG Any blank register is considered as reserved and has no effect when writen to and returns undefined data when read RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 9 10 1 Configuration Register CanCONF R W TABLE 58 Configuration Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SCALER PS1 Ps2 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 RSJ BPR Silen Sele Ena Ena Abor t ction ble ble t 1 0 31 24 SCALER _ Prescaler setting 8 bit system clock SCALER 1 23 20 PS1 Phase Segment 1 4 bit valid range 1 to 15 19 16 PS2 Phase Segment 2 4 bit valid range 2 to 8 14 12 RSJ ReSynchronization Jumps 3 bit valid range 1 to 4 9 8 BPR Baud rate 2 bit 00b system clock SCALER 1 1 01b system clock SCALER 1 2 10b system clock SCALER 1 4 11b system clock SCALER 1 8 SILENT Listen only to the CAN bus send recessive bits SELECTIONSelection receiver input and transm
78. 28 27 I O bus width Defines the data with of the I O area 00 8 10 32 29 Asynchronous bus ready ABRDYN If set the IoBrdyN input can be asserted without relation to the system clock Reset to 0 at power up 30 PROM area bus ready enable PBRDYN If set a PROM access will be extended until IoBrdyN is asserted Reset to 0 at power up 18 24 31 Reserved No effect when written to Undefined when read During power up the prom width bits 9 8 are set with value on LeonPio 1 0 inputs The PROM waitstates fields are set to 30 maximum External bus error and bus ready are disabled All other fields are undefined Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX j RUAG GAISLER Aerospace Defence Technology 3 4 11 Memory configuration register 2 MCFG2 Memory configuration register 2 is used to control the timing of the SRAM 31 12 9 8 7 6 5432 10 SRAM bank sz IoBrdyN enable Read mod write Ram width Write waitstates Read waitstates Figure 41 Memory configuration register 2 1 0 Ram read waitstates Defines the number of waitstates during ram read cycles 00 0 01 1 10 2 11 3 3 2 Ram write waitstates Defines the number of waitstates during ram write cycles 00 0 01 1 10 2 11 3 5 4 Ram with Def
79. 31 24 Reserved No effect when written to Undefined when read 23 0 CNTR Pulse counter value All bits are cleared to 0 at reset The pulse counter is decremented each clock period and does not wrap after reaching zero Command pulse channels with the corresponding output data and pulse enable bits set are asserted while the pulse counter is greater than zero Setting CNTR to 0 does not give a pulse Setting CNTR to 1 does give a pulse with of 1 Clk period Setting CNTR to 255 does give a pulse with of 255 Clk periods Note that only bits 19 to 0 are implemented 8 2 6 Interrupt Mask Register GpioMASK R W TABLE 54 Interrupt Mask Register 31 24 23 16 15 0 MASK 31 24 Reserved No effect when written to Undefined when read 23 16 MASK Interrupt enable Ob disable 1b enable 15 0 Reserved No effect when written to Undefined when read All bits are cleared to 0 at reset Note that only bits 23 to 16 are implemented and are mapped on interrupts 31 to 24 8 2 7 Interrupt Polarity Register GpioPOL R W TABLE 55 Interrupt Polarity Register 31 24 23 16 15 0 POL 31 24 Reserved No effect when written to Undefined when read 23 16 POL Interrupt polarity Ob active low or falling edge 1b active high or rising edge 15 0 Reserved No effect when written to Undefined when read All bits are cleared to 0 at reset Note that only bits 23 to 16 are implemented and are mapped on inter
80. 4 D15 D24 D25 D26 D27 D28 D29 D30 D31 CB6 D0 D1 D2 D3 D4 D5 D6 D7 D24 D25 D26 D27 D28 D29 D30 D31 If the memory is configured in 8 bit mode the EDAC checkbit bus CB 7 0 is not used but it is still possible to use EDAC protection Data is always accessed as words 4 bytes at a time and the corresponding checkbits are located at the address acquired by inverting the word address address 27 2 and using it as a byte address The same chip select is kept active A word written as four bytes to addresses 0 1 2 3 will have its checkbits at address OXOFFFFFFF addresses 4 5 6 7 at OXOFFFFFFE and so on All the bits up to the maximum banksize will be Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology inverted while the same chip select is always asserted This way all the banksize can be supported and no memory will be unused except for a maximum of 4 B in the gap between the data and checkbit area The 8 bit mode applies to RAM and PROM Only byte writes should be performed to ROM with EDAC enabled In this case only the corresponding byte will be written The operation of the EDAC can be tested trough the Error control register see below If the WB write bypass bit is set the value in the TCB field will replace the normal checkbits during memory write cycles If the RB read
81. 6 RESERVED No affect when written to Undefined when read 15 0 ADCIN ADC input data ADData 15 0 A write access to the register initiates an analogue to digital conversion provided that no other ADC or DAC conversion is ongoing otherwise the request is rejected A read access that occurs before an ADC conversion has been completed returns the result from a pre vious conversion Note that any data can be written and that it cannot be read back since not relevant to the initiation of the conversion Note that only the part of ADData 15 0 that is specified by means of bit ADCONF ADCDW is used by the ADC The rest of the bits are read as zeros Note that only bits 15 to 0 are implemented 6 3 4 DAC Data Output Register ADOUT R W TABLE 40 DAC Data Output Register 31 16 15 0 DACOUT 31 16 RESERVED No affect when written to Undefined when read 15 0 DACOUT DAC output data ADData 15 0 A write access to the register initiates a digital to analogue conversion provided that no other DAC or ADC conversion is ongoing otherwise the request is rejected Note that only the part of ADData 15 0 that is specified by means of ADCONF DACDW is driven by the DAC The rest of the bits are not driven by the DAC during a conversion Note that only the part of ADData 15 0 which is specified by means of ADCONF DACDW can be read back whilst the rest of the bits are read as zeros Note that only bits 15 to 0 are implemented
82. 6 and 7 to be written as well These bits can thus be controlled via the augmented register instead of being input via discrete inputs to the SPW core Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX ao RUAG GAISLER Aerospace Defence Technology 10 6 8 First Failing Packet Register The SPW First Failing Packet Register is used for recording failure events during reception of SpaceWire packets It is used for all types of transfer protocols and provides failure information that is either common to all transfer protocols or specific to a particular transfer protocol Most of the failure causes are detected during the Protocol Identification described in 10 6 3 2 the RMAP command header CRC verification described in 10 6 4 3 and other failure causes are detected during the data reception as described in 10 6 4 3 As soon as a failure cause is detected the remains of the packet are discarded Note that only one unique error code is set per packet if more than one error is found in a packet only the first detected one is recorded The SPW First Failing Packet Register is triggered if cleared and ready when a packet has been rejected and then records the three first bytes of the packet and the cause of the failure Note that the three first bytes of every packet received correct or not are continuously saved and further saving is stopped when a failure occurs If l
83. 8 SPW TxVC Status Register 1 0x8006032C SPW TxVC Interrupt Status Register 1 0x80060330 SPW TxVC Interrupt Status Set Register 1 0x80060334 SPW TxVC Interrupt Status Clear Register 1 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER 192 13 3 9 SpaceWire Link Interface 1 TABLE 93 SpaceWire Link 1 registers RUAG Aerospace Defence Technology Address Register 0x80070000 SPW Pending Interrupt Masked Status Register 0x80070008 SPW Pending Interrupt Status Register 0x80070010 SPW Interrupt Mask Register 0x80070014 SPW Link Interrupt Status Register 0x80070018 SPW Link Interrupt Status Set Register 0x8007001C SPW Link Interrupt Status Clear Register 0x80070020 SPW CODEC Configuration Register 0x80070024 SPW Clock Division Register 0x80070028 SPW RMAP Destination Key Register 0x8007002C SPW Transmit Time Code Register 0x80070030 SPW VC Transfer Protocol ID Register 0x80070034 SPW SW Transmit Time Code Register 0x80070040 SPW Status Register 0x80070044 SPW CODEC Status Register 0x80070048 SPW Receive Time Code Status Register 0x80070050 SPW Transmit Time Code Mask Register 0x80070080 SPW First Failing Packet Register 0x80070100 SPW RxVC Config Register 0 0x80070104 SPW RxVC Packet Counter Register
84. A0000000 Ox AOOOFFFF 64k On chip RAM Yes On chip RAM Table 80 Effective memory address map with cacheability The SpaceWire RTC global register map is shown in the table below The global register address map is defined by the addresses on the internal AMBA APB bus Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG Address range Size Mapping Module 0x80000000 Ox800000FF 256 LEON2 FT registers LEON2 FT 0x80010000 0x800100FF 256 On Chip Memory FTAHBRAM 0x80020000 0x800200FF 256 24 bit GPIO GPPULSE 0x80030000 0x800300FF 256 32 bit Timers GRTIMER 0x80040000 0x800400FF 256 ADC DAC interface GRADCDAC 0x80050000 Ox800500FF 256 FIFO interface GRFIFO 0x80060000 Ox80060FFF 4096 SpaceWire Interface 0 SPW2 0x80070000 0x80070FFF 4096 SpaceWire Interface 1 SPW2 0x80080000 0x800803FF 1024 CAN interface GRHCAN Table 81 Global register address map AMBA APB bus RTC 100 0012 December 2009 Version 2 4 e RUAG Aerospace Defence Technology AEROFLEX GAISLER 13 2 Plug amp Play information The SpaceWire RTC plug amp play information for the masters on the internal AMBA AHB bus is shown in the table below Address range Size Mapping Module OxFFFFF000 OxFFFFFO1F 32 LEON2 FT Caches LEON2 FT OxFFFFFO20 OxFFFFFO3F 32 LEON2 FT DSU UART LEON2 FT OxFFFFF040 OxFFFFFOSF 32 FIFO interface GRFIFO OxFFFFF06
85. AG GAISLER Aerospace Defence Technology 9 10 2 Status Register CanSTAT R TABLE 59 Status register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TxErrCntr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RxErrCntr Activ AHB OR Off Pass e Err 31 24 Reserved No effect when written to Undefined when read 23 16 TxErrCntr Transmission error counter 8 bit 15 8 RxErrCntr Reception error counter 8 bit ee ACTIVE Transmission ongoing AHBErr AMBA AHB master interface blocked due to previous AHB error OR Overrun during reception OFF Bus off condition PASS Error passive condition All bits are cleared to 0 at reset The OR bit is set if a message with a matching ID is received and cannot be stored via the AMBA AHB bus this can be caused by bandwidth limitations or when the circular buffer for reception is already full The OR and AHBErr status bits are cleared when the register has been read Note that TxErrCntr and RxErrCntr are defined according to CAN protocol Note that the AHBErr bit is only set to 1b if an AMBA AHB error occurs while the Can gt CONF ABORT bit is set to 1b 9 10 3 Control Register CanCTRL R W TABLE 60 Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Ena et ble 31 2 Reserved No effect when written to Undefined when r
86. Asynchronous interrupt 11 interrupt_level_12 Ox1C 20 Asynchronous interrupt 12 interrupt_level_13 0Ox1D 19 Asynchronous interrupt 13 interrupt_level_14 Ox1E 18 Asynchronous interrupt 14 interrupt_level_15 Ox1F 17 Asynchronous interrupt 15 trap_instruction 0x80 OxFF 16 Software trap instruction TA 3 1 8 Hardware breakpoints The integer unit can be configured to include up to four hardware breakpoints Each breakpoint consists of a pair of application specific registers Yoasr24 25 Yasr26 27 Yasr28 30 and asr30 31 registers one with the break address and one with a mask 31 2 1 0 asr24 Yoasr26 asr28 Yoasr30 WADDR 31 2 IF 31 2 0 asr25 Yoasr27 asr29 asr3 1 WMASK 31 2 DLI DS Figure 3 Watch point registers Any binary aligned address range can be watched the range is defined by the WADDR field masked by the WMASK field WMASK x 1 enables comparison On a breakpoint hit trap Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER 3 2 Aerospace Defence Technology OxOB is generated By setting the IF DL and DS bits a hit can be generated on instruction fetch data load or data store Clearing these three bits will effectively disable the breakpoint function 3 1 9 Floating point unit The Meiko FPU is attached using an integrated interface inside the IU pipeline The integ
87. December 2009 Version 2 4 EROFLEX 134 RUAG GAISLER Aerospace Defence Technology Packet IDentification All channels Inactive Remove NewPacket EOP EEP Req from RXFifo A singe EOP EEP ___ EOP EEP in first word Exact Match DLA register Check DLA 254 default No ie il l Lo o o o o o No Match Match and ID 1 DLAErr ID 1 gt RMAP transfer protocol FFPR HeadErr ID 240 gt VC transfer protocol Flush Check ID ID other gt To SW if enabled ID Other 2 NoSW IBA 4 ID 240 PtcllDErr FFPR aa Flush Virtual Channel VC VC not a ID Other RMAP to SW RMAP Resp Resp a No HW AuthErr support Cmd HW FFPR HeadErr type or supported legal or Flush enabled neither HW nor SW support Header Check RMAP Cmd header E Read all bytes in g header Activate Activate RxVC 0 RxVC VC Execute Strip DLA ID amp VC No Strip At least 1 data byte 4 WriteData l No No Transfer byte Transfer byte No FFPR Flush Transfer byte Generate Response Blockend Yes Error Yes v Figure 10 15 Receiver packet identification and qualification flow diagram Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012
88. December 2009 Version 2 4 EROFLEX m RUAG GAISLER Aerospace Defence Technology 10 6 4 Remote Memory Access Protocol RMAP 10 6 4 1 Hardware supported RMAP commands The SpaceWire SPW2 Module supports in hardware the Remote Memory Access Protocol RMAP with the following constraints Increment Address setting only with no support for No Increment Address setting Extended Address support using the 4 least significant bits only thus limiting the address range to 2 64 GiB Verified Write commands only for 4 byte block sizes and with word aligned addressing No Read Modify Write command support The following RMAP commands are handled in hardware when enabled Read commands with Incrementing Address an Extended Address less or equal to OF 6 and a mandatory acknowledge request Write commands with Incrementing Address an Extended Address less or equal to OF js and with or without an acknowledgement request Verified Write commands with Incrementing Address an Extended Address less or equal to OF js with exactly a 4 byte block size with word aligned addressing and with or without an acknowledgement request The SpaceWire SPW2 Module supports in hardware only Big Endian Byte and HalfWord to from Word conversions I e first byte at address zero is written to bit positions 31 24 in a Word and fourth byte at address 3 is written to bit positions 7 0 in the same Word Little Endian conversion is
89. E DDE DF IF DCS Ics Figure 6 Cache control register 31 30 Data cache replacement policy DREPL 00 no replacement policy direct mapped cache 01 random 10 least recently replaced LRR 11 least recently used LRU 29 28 Instruction cache replacement policy IREPL 00 no replacement policy direct mapped cache 01 random 10 least recently replaced LRR 11 least recently used LRU 27 26 Instruction cache associativity SETS Number of sets in the instruction cache 1 00 direct mapped 01 2 way associative 10 3 way associative 11 4 way associative 25 24 Data cache associativity DSETS Number of sets in the data cache 1 00 direct mapped 01 2 way associative 10 3 way associative 11 4 way associative 23 Data cache snoop enable DS if set will enable data cache snooping 22 Flush data cache FD If set will flush the data cache Always reads as zero 21 Flush Instruction cache FI If set will flush the instruction cache Always reads as zero 20 19 Cache parity bits CPC Indicates how many parity bits are used to protect the caches 00 none 01 1 10 2 18 17 Cache parity test bits CPTE These bits are XOR ed to the data and tag parity bits during diagnostic writes Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER 3 3 Copyright 2006 2007 2008
90. E E E E E 182 12 AMBA AHB APB BRIDGE scossiancimesaateseneiasvonssaansimdcdaaonerzaaemeastiomeianenizaaions 184 12 1 OVEIVIEW cesis ien acted leo beens hive iain io EEEa ie a aE 184 12 2 Operati ON is ses sc acs sdecsepess anes teczcescaencoscesJcencatees vesstesinecseesteanesccusstacs E E A 184 12 3 Vendor and device id ccccccessscecsssececsscecessecesecaecesncesesaeecseaaeeecseeeceseeecesueceseeseceseeesenes 184 13 MEMORY AND REGISTER MAP INTERRUPT ASSIGNMENT 5 185 13 1 Addressing formatio iis cos cacsdccssessececcsecedeusieccdegseseis sds eipig tunes s e arase Eese EEN EEEE ENEE 185 13 2 Plug amp Play iLormattOn iss s secscscancseihesssatevenedonsessectvsancsenssseeseayesttonsrenestevcsenscsvenbedersoeredss 186 13 3 Registers aececi nro nen a Wi cael Seer E Ga ai ad Tansee Sack R 187 13 4 TIMLGKEUPUS P EE E cases itess ivesdusesbsentede canes ecenseancpaveasntberaace 193 14 INTERFACES AND SIGNALS sscsdsccinnssaxeciehsvencdunnesseoniacdneseegadyacsasuencdenecduennieesane 195 15 REVISION CONTROL knnen nn E a ia 198 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 1 INTRODUCTION 1 1 Scope 1 2 1 3 1 4 1 5 This document establishes the User s Manual for the SpaceWire Remote Terminal Controller RTC device developed in the scope of the TopNet SpaceWire Controller Remote User Interface activity i
91. E field 5 7 9 Transmit Channel Interrupt Register FifoTxIRQ R W TABLE 25 Transmit Channel Interrupt Register 31 16 15 0 IRQ 31 16 RESERVED No affect when written to Undefined when read 15 0 IRQ Pointer 1 to a byte address from which the read of transmitted data shall result in an interrupt All bits are cleared to 0 at reset Note that this indicates that a programmed amount of data has been sent Note that the LSB may be ignored for 16 bit wide FIFO devices The field is implemented as relative to the buffer base address scaled with the SIZE field 5 7 10 Receive Channel Control Register FifoRxCTRL R W TABLE 26 Receive Channel Control Register 31 2 1 0 Ena ble 31 1 RESERVED No affect when written to Undefined when read 0 ENABLE Enable channel All bits are cleared to 0 at reset Note that in the case an AHB bus error occurs during an access while storing receive data and the FifoConf ABORT bit is 1b then the ENABLE bit will be reset automatically At the time the ENABLE is cleared to Ob any ongoing data reads from the FIFO are not aborted 5 7 11 Receive Channel Status Register FifoRxSTAT R TABLE 27 Receive Channel Status Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 RxByteCntr RxO RxP Rxir RxF RxEr EF HF nGo arity q ull ror ing 31 11 RESERVED No
92. EA EE 57 5 5 Reception eaaa eE E E E E A Reaceae 59 5 6 Operation sss 5 cs sade eveptes en e E R EATR E S 61 5 7 RGGISLOES oirein eroare aerar Ea Er OEE PEE OaE EE NEEE EE E sbeddevebs a EREE E EENE 62 6 ADC DAC INTERFACE cata tceete cau enc beats iiinis teskis aE anie i aTe aaa 70 6 1 QV CR VNC Wooten cca tees E a e ET 70 6 2 Operation sieer eee anae rarioa ER EEEE Ea EE EEA EOE EE EE EErEE E aE VEREER 71 6 3 REGISTERS eraen arn Ee E EEEE EEE EEEE A E 74 7 SAO WIVES vecera eee a r E E EEE EA 80 7 1 ON SEVIS W ese N E E OAE EESE EEES EE EEE ON EE EEEE EEE r 80 7 2 Operaio xi soos bes seen airne E E EE ETENEE E E E E E 80 7 3 Vendor and device 10 rsrsrsrs sirae Ene ES EEEE EEE EE ES TEE OEE EE EEE OKEE E EEEE EE 80 71 4 REGISTERS aroraa aod a E E E EE d a EEA E ele 81 8 24 BIT GENERAL PURPOSE INPUT OUTPUT astessasccosccacesesseadecsesesticrissacceseis 84 8 1 OVENS W ea E E E a E E EREE E coca etre rarer 84 8 2 RESISLCES ooie a E E E OEE A R EAE E 84 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX j RUAG GAISLER iercnpette Defend tedenlagy 9 CAN INTERFACE irnia le acdsee i n E E guiendiaidundiaas 88 9 1 OVETVIEW e E E ey E E E EE 88 9 2 MING TRACC mote e a A etect fon Voss h at fan bec Saves steht ieee nectar 89 9 3 Protocol neierens cegecuesahdea chaasesags RE EEE E ANTEE E RE 89 9 4 Status and Monitoring sneren nna E E E E E E S E S E EEEE 90 9 5 MEETS O a E 90 9 6 RGCEPUON ie
93. EAD 7 e There are 2 CAN messages available for transmit when CanTxSIZE SIZE 2 CanTxWR WRITE 5 and CanTxRD READ 3 When a CAN message has been successfully transmitted the read pointer CanTxRD READ is auto matically incremented taking wrap around effects of the circular buffer into account Whenever the Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology write pointer CanTxWR WRITE and read pointer CanTxRD READ are equal there are no CAN mes sages available for transmission 9 5 3 Location The location of the circular buffer is defined by a base address CanTXADDR ADDR which is an absolute address The location of a circular buffer is aligned on a 1kbyte address boundary 9 5 4 Transmission procedure When the channel is enabled CanTxCTRL ENABLE 1 as soon as there is a difference between the write and read pointer a message transmission will be started Note that the channel should not be enabled if a potential difference between the write and read pointers could be created to avoid the message transmission to start prematurely A message transmission will begin with a fetch of the complete CAN message from the circular buffer to a local fetch buffer in the CAN controller After a successful data fetch a transmission request will be forwarded to the HurriCANe codec If there is at least an additional CAN message ava
94. IOICFG1 EN LE PL ISEL3 IRQ7 EN LE PL ISEL2 IRQ6 EN LE PL ISEL1 IRQ5 EN LE PL ISELO IRQ4 31 30 29 28 24 23 22 21 20 16 15 14 13 12 8 765 4 0 IOICFG2 EN LE PL ISEL7 IRQ15 EN LE PL ISEL6 IRQ13 EN LE PL ISELS5 IRQ12 EN LE PL ISEL4 IRQ 10 Figure 31 I O port interrupt configuration register 1 amp 2 ISELn I O port select The value of this field defines which I O port 0 31 should generate parallel I O port interrupt n PL Polarity If set the corresponding interrupt will be active high or edge triggered on positive edge Otherwise it will be active low or edge triggered on negative edge LE Level edge triggered If set the interrupt will be edge triggered otherwise level sensitive EN Enable If set the corresponding interrupt will be enabled otherwise it will be masked To save pins I O pins are shared with other functions according to the table below TABLE 9 UARTYIO port usage T O port Function Type Description Enabling condition LeonPio 15 TXD1 Output UART transmitter data UART transmitter enabled LeonPio 14 RXD1 Input UARTI receiver data LeonPio 13 RTS1 Output UART request to send UART flow control enabled LeonPio 12 CTS1 Input UART clear to send LeonPio 11 TXD2 Output UART2 transmitter data UART2 transmit
95. MAP RMAP is used for remotely accessing resources on the local AMBA bus The RMAP implementation can receive commands and generate responses utilizing the aforementioned RxFIFO and the TxFIFO and the two AMBA AHB masters RMAP has priority over any TxVC The SpaceWire Module is configured controlled and monitored via an AMBA APB bus slave interface accessing all module internal registers The SpaceWire CODEC uses a separate clock the SpwClk as its clock while the rest of the SpaceWire Module uses the BusClk The SpaceWire CODEC requires a clock frequency that is a multiple of 10 MHz to produce a data rate of 10 Mbit s required for reliable start up procedures The SpaceWire CODEC clock is also used for sending data at high transfer rates Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX X RUAG GAISLER Aerospace Defence Technology 10 5 Definitions This section and the following subsections define the typographic and naming conventions used throughout this document 10 5 1 Bit Numbering The following conventions are used for bit numbering e The Most Significant Bit MSB of a vector has the leftmost position e The Least Significant Bit LSB of a vector has the rightmost position e Unless otherwise indicated the MSB of a vector has the highest bit number and the LSB the lowest bit number 10 5 2 Names The following conventions are used for all names fo
96. MAP commands using the same virtual receive channel 10 4 3 3 Additional protocols Other protocols than the VCTP and RMAP protocols can be implemented with software support The commands are relayed to the software using a dedicated virtual receive channel This relaying to software can be controlled automatically using the Transfer ID field of the packet header but it can also be enforced by configuring the SPW2 to route all incoming packets to the software 10 4 4 Block Diagram BusClk clock zone SpwClk clock zone RxVC and RMAP handling Ee KE SpaceWire link RMAP response AMBA AHB bus TxVC sendlist handling and Y Tx FIFO l arbiter Register I F AMBA APB bus TimeCode I F A Figure 10 2 SpaceWire functional block diagram The SpaceWire SPW2 Module is used for transmitting and receiving data over a Space Wire link It provides support for transmitting any type of protocol or data structure using SpaceWire packets It provides hardware support for receiving two types of SpaceWire Transfer Protocols and can relay packets of other protocols to software The SpaceWire Virtual Channel Transfer Protocol VCTP implements multiple virtual channels on a single SpaceWire link The Remote Memory Access Protocol RMAP implements remote memory access
97. MASK MASK 0 A TxSYNC message ID is matched when Transmitted ID XOR CanCODE SYNC AND CanMASK MASK 0 9 10 6 Transmit Channel Control Register CanTxCTRL R W TABLE 63 Transmit Channel Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sin Ong Ena gle oing ble 31 3 Reserved No effect when written to Undefined when read 2 SINGLE Single shot mode 1 ONGOING Transmission ongoing 0 ENABLE Enable channel All bits are cleared to 0 at reset Note that if the SINGLE bit is 1b the channel is disabled i e the ENABLE bit is cleared to Ob if the arbitration on the CAN bus is lost Note that in the case an AHB bus error occurs during an access while fetching transmit data and the CanCONF ABORT bit is 1b then the ENABLE bit will be reset automatically Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX h RUAG GAISLER Aerospace Defence Technology At the time the ENABLE is cleared to Ob any ongoing message transmission is not aborted unless the CAN arbitration is lost or communication has failed Note that the ONGOING bit being 1b indicates that message transmission is ongoing and that configu ration of the channel is not safe 9 10 7 Transmit Channel Address Register CanTxADDR R W TABLE 64 Transmit Channel Address Register
98. MBA AHB meen 24bit General ADC DAC AHB I F AHB I F AHB I F AHB I F 32bit Timers Purpose 1 0 Ctrl I F FIFO CAN SpaceWire On Chip Ctrl I F Controller Link Memory Discrete signals ADC DAC FIFO CAN Space Wire Network Network Aeroflex Gaisler AB i Kungsgatan 12 tel 46 31 7758650 411 19 G teborg fax 46 31 421407 Sweden www Aeroflex com Gaisler Company confidential material and document This document may not be distributed under any circumstances All information is provided as is There is no warranty that it is correct or suitable for any purpose neither implicit nor explicit Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology Table of contents 1 INTRODUCTION ienn cia eee ee 4 1 1 SCOPC E E T E E EEEE 4 1 2 TCE SINE eenn S EE EEE ENT E seen Wale S ERN 4 1 3 Reference dJOcUmeMiS psor sec ccvecs vere vacesnepesccecstteascatssvazestert Soames vaes becheseasteearnseecknemnieaes 4 1 4 Source TELEPEM CE asses se sa nni a eth ob SG 0s gs eo nd aana anina a esas teach aaeei iias 4 1 5 Systemi OVERVIEW cacedeesdecoscessessscseyisesiecestesieasceavesticsdes deoteutads seesdcgsaeuscausasaecedveueced EE EE ea i 4 1 6 Block diagramen n Ghee E E eed E EE E EE 5 1 7 Description of typical systems using the device esseeseseesrrrsrreesreetsrrererrererrnserrsrrrrsee 6 2 FUNCTIONAL OVERVIEW ais csastessnuctonetsvaaicntoasettvasu
99. R and SPW_LISCR SPW_RxISSR and Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology SPW_RxISCR or SPW_TxISSR and SPW_TxISCR registers See 10 6 15 Timing Constraints Field Description DisErr Link interface disconnection error detected ParErr Link interface parity error detected ESCErr Link interface ESC error detected CrErr Link interface credit error detected RxTime Code Time code received TxTime Code Time code transmitted PktRej A packet has been rejected and discarded First Failing Packet Register has been triggered LinkAbort SPW CODEC Status Register LinkState has made a transition from Run to Error Reset Tx TxVC interrupt see SPW TxVC interrupt registers for details Rx RxVC interrupt see SPW RxVC interrupt registers for details SPW Link Interrupt Status Register SPW_LISR SPW Link Interrupt Status Set Register SPW_LISSR SPW Link Interrupt Status Clear Register SPW_LISCR QLR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Link Pkt Tx Rx Cr ESC Par Diss Abat Rej Tne Time Err Err Err Err
100. SpaceWire EROFLEX RUAG am GAI S LER Aerospace Defence Technology User s Manual Features e SPARC V8 integer unit with 7 stage pipeline 4 kbyte instruction and 4 kbyte data cache e Double precision IEEE 754 floating point unit e EDAC protected interface to multiple 8 32 bits PROM SRAM memory banks and I O e Advanced on chip debug support unit Description e UARTs Timers Watchdog GPIO Digital ADC DAC interfaces Interrupt controller The SpaceWire Remote Terminal Controller Two SpaceWire links with RMAP RTC is a bridge between the SpaceWire network and the CAN bus providing a fully integrated system Additional features are provided to carter for autonomy of remote e Redundant CAN 2 0 interface with DMA e FIFO interface with DMA Up to 50 MHz system frequency terminals and to relieve the central processing e Up to 200 Mbit s SpaceWire data rate chain of repetitive standard acquisitions and e 349 pin MCGA with 50 mil pin spacing management duties SRAM PROM RS232 422 EEPROM FLASH PROM Debug Debug E MEIKO AHB Memory Serial Link Support le EON2 FT SPARC Vek Floating arbiter Controller UART Unit Integer Hnit Point decoder Unit AHB I F AHB I F AHB I F l Cache D Cache AHB I F AMBA AHB N IRQ AHB APB Q TIMER bridge 5 9 s SpaceWire RTC AMBA APB A
101. Status Register See 10 7 1 6 for details Further reception is halted for the virtual channel until re triggered by software Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX Ml RUAG GAISLER Aerospace Defence Technology 10 6 6 Virtual Transmit Channels Tx VC The SpaceWire SPW2 Module implements Virtual Transmit Channels TxVC Each virtual channel allows transfers from memory to the SpaceWire link Each transmitter virtual channel has a uniquely defined send list stored in memory The send list entries define what data is to be sent from memory Each send list entry specifies the position and size of the header and the position and size of the data to be transmitted The SpaceWire SPW2 Module performs direct memory accesses to read the send list header and data to be transmitted Each virtual transmit channel features a set of DMA handling registers which are used for configuring controlling and monitoring the channel All TxVC are handled by a common DMA handler The selection of the virtual channel from which data are to be transmitted on the SpaceWire link is performed by round robin arbitration for each send list entry Note that for the SPW2 module receiver a virtual channel identifier of zero is not allowed for the virtual channel transfer protocol VCTP as explained hereafter neither are virtual channel identifiers above 7 or less if so configured
102. The debug mode can only be entered when the debug support unit is enabled through an external pin LeonLeonDsuEn When the debug mode is entered the following actions are taken e PC and nPC are saved in temporary registers accessible by the debug unit e an output signal LeonDsuAct is asserted to indicate the debug state e the timer unit is optionally stopped to freeze the LEON timers and watchdog The instruction that caused the processor to enter debug mode is not executed and the processor state is kept unmodified Execution is resumed by clearing the BN bit in the DSU control register or by de asserting LeonDsuEn The timer unit will be re enabled and execution will continue from the saved PC and nPC Debug mode can also be entered after the processor has entered error mode for instance when an application has terminated and halted the processor The error mode can be reset and the processor restarted at any address Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 3 5 2 2 Trace buffer The trace buffer consists of a circular buffer that stores executed instructions and or AHB data transfers A 30 bit counter is also provided and stored in the trace as time tag The trace buffer operation is controlled through the DSU control register and the Trace buffer control register see below When the processor enters debug mode
103. TrPtclSW are disabled I e either hardware or software support or both are disabled for the specific RMAP command Or if a command was supposed to be handled by hardware based on the Command amp Type field but was later found to be not supported e g verified write to a mis aligned address Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX es RUAG GAISLER Aerospace Defence Technology Invalid destination logical address If header CRC decoded correctly but non matching DLA The SpaceWire SPW2 Module generates RMAP responses as follows The common Tx DMA channel which is shared with the virtual transmit channels is used for RMAP responses Incase a DMA error occurs when reading data via the Tx DMA an EFP is inserted and the DMA is released No RxVC interrupts are issued when an RMAP command is rejected since it is up to the RMAP source to handle this situation using the RMAP response information The PktRej interrupt is issued though every time the SPW First Failing Packet Register is triggered 10 6 5 Virtual Receive Channels Rx VC The Virtual Channel Transfer Protocol VCTP implements Virtual Receive Channels RxVC Each virtual channel allows transfers from the SpaceWire link to its own programmable area in memory This area constitutes a memory buffer and can be located anywhere in memory Access to the memory area is performed by me
104. UART 2 AHB error el ee ees rene el NHN wy BR nm a AN oc 3 3 2 3 Control registers The operation of the interrupt controller is programmed through the following registers 31 17 16 15 1 0 ILEVEL 15 1 R IMASK 15 1 R Figure 8 Interrupt mask and priority register Field Definitions 31 17 Interrupt level LEVEL 15 1 indicates whether an interrupt belongs to priority level 1 ILEVEL n 1 or level 0 C LEVEL n 0 15 1 Interrupt mask MASK 15 1 indicates whether an interrupt is masked IMASK n 0 or enabled TMASK n 1 16 0 Reserved No effect when written to Undefined when read 31 16 15 1 0 RESERVED IPEND 15 1 R Figure 9 Interrupt pending register Field Definitions 15 1 Interrupt pending IPEND 15 1 indicates whether an interrupt is pending IPEND n 1 31 16 0 Reserved No effect when written to Undefined when read 31 16 15 1 0 RESERVED IFORCE 15 1 R Figure 10 Interrupt force register Field Definitions 15 1 Interrupt force IFORCE 15 1 indicates whether an interrupt is being forced IFORCE n 1 31 16 0 Reserved No effect when written to Undefined when read Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 31 16 15 1 0 RESERVED ICLEAR 15 1 R
105. Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 6 ADC DAC INTERFACE 6 1 Overview The block diagram shows a partitioning of the combined analogue to digital converter ADC and dig ital to analogue converter DAC interface The combined analogue to digital converter ADC and digital to analogue converter DAC interface is assumed to operate in an AMBA bus system where an APB bus is present The AMBA APB bus is used for data access control and status handling The ADC DAC interface provides a combined signal interface to parallel ADC and DAC devices The two interfaces are merged both at the pin pad level as well as at the interface towards the AMBA bus The interface supports simultaneously one ADC device and one DAC device in parallel Address and data signals unused by the ADC and the DAC can be used for general purpose input out put providing 0 8 16 or 24 channels The ADC interface supports 8 and 16 bit data widths It provides chip select read convert and ready signals The timing is programmable It also provides an 8 bit address output The ADC conversion can be initiated either via the AMBA interface or by internal or external triggers An interrupt is gener ated when a conversion is completed The DAC interface supports 8 and 16 bit data widths It provides a write strobe signal The timing is programmable It also provides an 8 bit address output The DAC conversion is initiated via the AMBA
106. a response word when the processor enters debug mode 19 Reset error mode RE if set will clear the error mode in the processor 31 20 Trace buffer delay counter DCNT Note that the number of bits actually implemented depends on the size of the trace buffer 3 5 2 5 DSU breakpoint registers The DSU contains two breakpoint registers for matching either AHB addresses or executed processor instructions A breakpoint hit is typically used to freeze the trace buffer but can also put the processor in debug mode Freezing can be delayed by programming the DCNT field in the DSU control register to a non zero value In this case the DCNT value will be decremented for each additional trace until it reaches zero after which the trace buffer is frozen If the BT bit in the DSU control register is set the DSU will force the processor into debug mode when the trace buffer is frozen Note that due to pipeline delays up to 4 additional instruction can be executed before the processor is placed in debug mode A mask register is associated with each breakpoint allowing breaking on a block of addresses Only address bits with the corresponding mask bit set to 1 are compared during breakpoint detection To break on executed instructions the EX bit should be set To break on AHB load or store accesses the LD and or ST bits should be set 31 2 1 0 Break address reg BADDR 31 2 0 EX 31 2 1 0 Break mask reg BMASK 31 2 LD ST
107. a when read 31 10 9 0 000 0 SCALER Value Figure 67 Scaler value 31 10 Reserved No effect when written to Undefined when read 31 10 9 0 000 0 SCALER Reload Value Figure 68 Scaler reload value 31 10 Reserved No effect when written to Undefined when read 31 11 10 9 8 7 3 2 0 000 0 EL EE DF SI IRQ TIMERS Figure 69 GRTIMER Configuration register 31 12 Reserved No effect when written to Undefined when read Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX j RUAG GAISLER Aerospace Defence Technology 11 Enable latching EL If set on the next matching interrupt the latches will be loaded with the corresponding timer values The bit is then automatically cleared not to load a timer value until set again 10 Enable external clock source EE If set the prescaler is clocked from the external clock source 9 Disable timer freeze DF If set the timer unit cannot be freezed otherwise DSU freezes the timer unit 8 Separate interrupts SI Reads 1 if the timer unit generates separate interrupts for each timer otherwise 0 Read only 7 3 APB Interrupt Timer n will drive APB Interrupt IRQ n Read only 2 0 Number of implemented timers Read only 31 0 TIMER COUNTER VALUE Figure 70 Timer counter value regist
108. access When possible the SPW2 will perform burst writes in order to preserve internal bus bandwidth 10 6 5 1 Configuration The Virtual Channel Transfer Protocol VCTP uses a Protocol Identifier equal to the SPW VC Transfer Protocol ID Register the default value being F016 Each virtual receive channel Rx VC provides the following configurability through a set of registers see 10 7 1 6 for details An RxVC Enable Disable bit An RxVC Word Alignment Enable Disable bit An RxVC DMA Base Address and an RxVC DMA Page Address supporting up to 64 Gbyte addressing space An RxVC DMA Block Size and a counter Rx VC DMA Offset supporting blocks of up to 16 Mbytes 1 An RxVC Packet Count Trigger configuring the number of packets to be received before finalising a block transfer 10 6 5 2 Status Each virtual receive channel Rx VC provides the following status monitoring An RxVC Current Packet Status Register that holds the present packet start address which can be used for recovery purposes if packet reception fails An RxVC Status Register indicating the present packet count position whether the RxVC channel is triggered started and whether the channel is active transfer ongoing 10 6 5 3 Interrupts When a valid Rx VC has been identified and the selected channel has started the handling of the received packet the Rx VC when triggered can issue interrupts as defined in SPW Rx VC Interrupt
109. access was a read cycle otherwise it is cleared 6 3 HMASTER AHB master This field contains the HMASTER 3 0 of the failed access 2 0 HSIZE transfer size This field contains the HSIZE 2 0 of the failed transfer 31 9 Reserved No effect when written to Undefined when read Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER 3 4 External memory access 3 4 1 Memory interface RUAG Aerospace Defence Technology The memory bus provides a direct interface to PROM memory mapped I O devices asynchronous static ram SRAM Chip select decoding is done for two PROM banks one I O bank and four SRAM banks Figure 34 shows how the connection to the different device types is made RomCsN 1 0 loOeN ToWrN IoCsN SpaceWire RTC MemCsN 4 0 MemOeN 4 0 MemWrN 3 0 MemA 22 0 MemD 31 0 Figure 34 Memory device interface 3 4 2 Memory controller The external memory bus is controlled by a programmable memory controller The controller acts as a slave on the AHB bus The function of the memory controller is programmed through memory configuration registers 1 2 amp 3 MCFG1 MCFG2 amp MCFG3 through the APB bus The memory bus supports various types of devices prom sram and local I O The memory bus can also be configured in 8 bit mode for applications with low memory and performance demands The controller decodes a 2 Gbyte addre
110. al Receive Channel Static Random Access Memory Software To Be Confirmed To Be Determined Virtual Transmit Channel Virtual Channel Virtual Channel Identifier Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX ir RUAG GAISLER Aerospace Defence Technology VCTP SPW Virtual Channel Transfer Protocol VCTPID SPW Virtual Channel Transfer Protocol Identifier VHDL VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuits 10 5 9 Data Structures 10 5 9 1 SPW2 Data Structure Definitions Destination Path Address is a SpaceWire path address which defines the route to a destination node by specifying for each router encountered on the way to the destination the output port that a packet is to be forwarded through A path address comprises one byte for each router on the path to the destination Once a path address byte has been used to specify an output port of a router it is deleted to expose the next path address byte for the next router All path address bytes will have been deleted by the time the packet reaches the destination Destination Logical Address DLA byte is the logical address of the destination This may be used to route the packet to the destination or if path addressing is being used to simply confirm that the final destination is the correct one i e that the logical address of the destination matches the logical address in the packet I
111. al is pro grammable in terms of Rising edge or Falling edge The Ready input signaling is protected by means of a programmable time out period to assure that every conversion terminates It is also possible to perform an ADC conversion without the use of the Ready signal by means of a programmable conver sion time duration This can be seen as an open loop conversion The Chip Select output signal is programmable in terms of e Polarity e Number of assertions during a conversion either Pulsed once during Start Conversion phase only Pulsed once during Start Conversion phase and once during Read Result phase or Asserted at the beginning of the Start Conversion phase and de asserted at the end of the Read Result phase The duration of the asserted period is programmable in terms of system clock periods for the Chip Select signal when pulsed in either of two phases The Read Convert signal is de asserted during the Start Conversion phase and asserted during the Read Result phase The Read Convert output signal is programmable in terms of Polarity The setup timing from Read Convert signal being asserted till the Chip Select signal is asserted is programmable in terms of sys Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology tem clock periods Note that the programming of Chip Select and Read Convert timing
112. alisation sequence for the module Operation Usage Describes how the module shall be used during normal operation Error Handling Describes how to handle internal errors in the module e g address error Usage Constraints Describes actions that are not allowed and the resulting consequences Examples Gives a few examples how to perform different tasks using the module Interrupt Handling Describes the interrupt handling of the module 10 6 1 General The SpaceWire SPW2 Module comprises receive and transmit capabilities supporting several protocols The core of the module is the SpaceWire link codec described in CODEC which implements the low level SpaceWire protocol receive and transmit handling On packet level the receiver implements two transfer protocols in hardware and provides support for processing of other unknown protocols in software Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX re RUAG GAISLER Aerospace Defence Technology The receiver comprises an identification stage which identifies the different transfer protocols and routes the data to the corresponding handler The identification is based on the Protocol Identifier concept described in RMAPID During the identification several types of error conditions can be detected and are reported in the First Failing Packet Register described in 10 6 8 This register is also used for reporting errors
113. anRxCODE AC AND CanRxMASS AM 0 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 f EROFLEX e RUAG GAISLER Aerospace Defence Technology 9 10 20 Interrupt registers The interrupt registers give complete freedom to the software by providing means to mask interrupts clear interrupts force interrupts and read interrupt status When an interrupt occurs the corresponding bit in the Pending Interrupt Register is set The normal sequence to initialize and handle a module interrupt is e Set up the software interrupt handler to accept an interrupt from the module e Read the Pending Interrupt Register to clear any spurious interrupts e Initialise the Interrupt Mask Register unmasking each bit that should generate the module interrupt e When an interrupt occurs read the Pending Interrupt Status Register in the software interrupt handler to determine the causes of the interrupt e Handle the interrupt taking into account all causes of the interrupt e Clear the handled interrupt using Pending Interrupt Clear Register Masking interrupts After reset all interrupt bits are masked since the Interrupt Mask Register is zero To enable generation of a module interrupt for an interrupt bit set the corresponding bit in the Interrupt Mask Register Clearing interrupts All bits of the Pending Interrupt Register are cleared when it is read or when the Pending Interrupt Masked Register
114. and receive input i e 0 and 1 The active pair i e O or 1 is bselectable by means of a configuration reg ister bit Note that all reception and transmission is made over the active pair For each pair there is one enable output i e 0 and 1 each being individually programmable Note that the enable outputs can be used for enabling an external physical driver Note that both pairs can be enabled simultaneously Note that the polarity for the enable inhibit inputs on physical interface driv ers differs thus the meaning of the enable output is undefined Redundancy is implemented by means of Selective Bus Access as specified in CANWG Note that the active pair selection above provides means to meet this requirement Protocol The CAN protocol is based on the ESA HurriCANe CAN bus controller core described in CANESA The CAN controller complies with CANSTD except for the overload frame generation Note that the ESA HurriCANe CAN bus controller core does not implement overload frame generation Version 5 1 dated 18 May 2005 has been used No other CAN protocol capabilities than those implement by the ESA HurriCANe CAN bus controller core are provided The Remote Frame Response function implemented by the ESA HurriCANe CAN bus controller is no implemented The remote frame response is instead envisaged to be implemented by means of proces sor support and software Note that there are three different CAN types generally defined
115. and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 31 20 13 12 109 8 76 0 RESERVED SEC MEMSIZE wB RB EN TCB Figure 59 Configuration register bit fields 31 21 Reserved Write access has no effect Read data is undefined 20 13 Single error counter Incremented each time a single error is corrected includes errors on checkbits Each bit can be set to zero by writing a one to it 12 10 Log2 of the current memory size 9 Write Bypass WB When set the TCB field is stored as check bits when a write is performed to the memory 8 Read Bypass RB When set during a read or subword write the check bits loaded from memory are stored in the TCB field 7 EDAC Enable When set the EDAC is used otherwise it is bypassed during read and write operations 6 0 Test Check Bits TCB Used as checkbits when the WB bit is set during writes and loaded with the check bits during a read operation when the RB bit is set Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 5 FIFO INTERFACE 5 1 Overview The FIFO interface is assumed to operate in an AMBA bus system where both the AMBA AHB bus and the APB bus are present The AMBA APB bus is used for configuration control and status han dling The AMBA AHB bus
116. ans of direct memory access Each virtual receive channel features a set of DMA handling registers which are used for configuring controlling and monitoring the virtual channel A channel is individually enabled and triggered by software via the DMA handling registers The selection of the virtual channel to which the received data from the Space Wire link is to be routed is made using the Virtual Channel Identifier VCID An incoming packet is matched to fit into any of the triggered and enabled channels and if a match occurs a data transfer to memory starts The matching is done during the identification of the packet as previously described For each incoming packet the four first bytes are stripped and the remainder of the packet is stored in the memory buffer consecutively until a halt event occurs i e a predefined number of packets are received an upper buffer boundary is reached or an error occurs The channel then has to be re triggered to continue its operation The concept of triggering is essential as incoming packets otherwise could stall the Space Wire network from the source to the destination including any pending RMAP commands A virtual channel identifier of zero is not allowed for the virtual channel transfer protocol VCTP as explained below neither are virtual channel identifiers above 7 or less if so configured at module instantiation An additional virtual receive channel Rx VC 0 is provided for the handling o
117. apped 32 Processor error mode Set to 1 if the traced instruction caused processor error mode 31 0 Opcode Instruction opcode During instruction tracing one instruction is stored per line in the trace buffer with the exception of multi cycle instructions Multi cycle instructions are entered two or three times in the trace buffer For store instructions bits 63 32 correspond to the store address on the first entry and to the stored data on the second entry and third in case of STD Bit 126 is set on the second and third entry to indicate this A double load LDD is entered twice in the trace buffer with bits 63 32 containing the loaded data Multiply and divide instructions are entered twice but only the last entry contains the result Bit 126 is set for the second entry For FPU operation Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER 43 RUAG Aerospace Defence Technology producing a double precision result the first entry puts the MSB 32 bits of the results in bit 63 32 while the second entry puts the LSB 32 bits in this field When a trace is frozen interrupt 11 is generated The DSU time tag counter is incremented each clock as long as the processor is running The counter is stopped when the processor enters debug mode and restarted when execution is resumed 31 29 00 DSU TIME TAG VALUE Figure 47 Time tag
118. are associated with the operation of the I O port the combined I O input output register and I O direction register When read the input output register will return the current value of the I O port when written the value will be driven on the port signals if enabled as output The direction register defines the direction for each individual port bit O input 1 output Direction D Q Output A Value D Q KY PAD Input Value Q D lt q Figure 29 I O port block diagram 31 18 17 0 IODIR 17 0 Figure 30 I O port direction register IODIRzn I O port direction The value of IODIR 15 0 defines the direction of I O ports 15 0 If bit n is set the corresponding I O port becomes an output otherwise it is an input IODIR 16 controls D 15 8 while IODIR 17 controls D 7 0 The I O ports can also be used as interrupt inputs from external devices A total of eight interrupts can be generated corresponding to interrupt levels 4 5 6 7 10 12 13 and 15 The I O port interrupt configuration register 1 and 2 define which port should generate each interrupt and how it should be filtered 31 18 Reserved No effect when written to Undefined when read Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 31 30 29 28 24 23 22 21 20 16 15 14 13 12 8 765 4 0
119. asconranthertevecstoncedacnansnstesoietes 7 2 1 General functionality g23 32 ccds iad asks a E E E E aaa 7 2 2 General interfac S morera rekonis ae enrere ie r ste Sen r EN SEESE SEESE EEEE EE RN Ei 8 3 PROCESSOR AND PERIPHERALS ccdscossidsdaisoensaticetanssduntesssanescoantnussestacndsedn nenss 9 3 1 LEON integer Unitesi e Sisk Gel ets Rie E E EE E EE E 9 3 2 CACHE s b sySteM ieron errer iri ar E E EE EEEE E a ie 13 3 3 On chip peripherals escroto oririorar oneens enr E EEEE EE EEE ENa E EEEE E 17 3 4 External memory ACCOSS sic sicsseiis scubsaavecsacbastesassndeatvectensqaca rehevdedsia seeveeivaassViecbeassvdaeeubeace te 33 3 5 Hardware debug Support vascciccessnsoes ccese cosesesnssbesseccagessegutercessegunesqeude slveracusecnenersoused egoeseseutess 40 3 6 Vendor and d vice idies eaa es Gee cebu tac stad b os need cebu dane aia 48 4 ON CHIP MEMORY scscavsesiteattasiandusasicend bastuaced ak EERE EERE E EERE 49 4 1 OVETVIEW epo O E stasis E E TE AA R A RE 49 4 2 Operationen nei EE E E E R A Seas 49 4 3 Vendor and device id urise rnern nenn EEE KERESE n EA EEA E TEE EEKi 50 4 4 ROGISTCES eE E EE E E E E saeuth bobbasenstssdbavensveoueed ye 50 5 FIFO INTERFACE oi sicssstsicnasdaostuadedsnapegacdenshnateadasteaad saonaudetaanaded veoheoastiageeadeasneniabess 52 5 1 OVERVIEW EET E E E E E E E E 52 5 2 MIM CTT ACE E E E E A A E E E cas 54 5 3 Waveforms nrerin irn dei anei TE A E E EEE E EE ER EEES 55 5 4 MA ANS MISSION enn ee e e E R EEE AE S A
120. asie ee edee aerer orra rira E PEE EE ES EE VES EEI EEEE EEE EE CEES EES 93 9 7 Globalteset and enable sesnnennronren eee EEEE oartexdivderseedticde 95 9 8 Tnterr pt eeror i seie rarr eE E E E EEE SEEE OE EEEE E E E E EE EEEE 95 9 9 Vendor and device Iderien iarann aea AEEA EAEI E Eia nS E 95 9 10 RECISTEIS ssc Facendes dioneo ee A E tings 0250s O EE T E NR E E E E EE 96 9 11 Memory Mapping maias a aii E E E E E REESE 107 10 SPACEWIRE LINK INTERFACE sssseessseeessseseesssseesssseesssseeeessoeeessoseesssseesssseee 108 10 1 System OVERVIEW aspras ae no cere Errr sce vscnegevbsgancsesceadecueadetecesnt cdusentouenesetscapaten 108 10 2 FUMCtlONS e nnenee eb hee As E E O dA a dw Ai A 108 10 3 WINGS TRACES cea SosF sto rote oven N e a adssfoec ities a lws ean eee 108 10 4 Module OVVIE W cesan retenis reee rere EAEE EE Ee E E EEE NE EEEN EEEE EEE EEES 109 10 5 MES PINT EL ONS sense n E E E R ee Meee 113 10 6 Functional behaviour ssesseseeeseseeeeeeeetessseessesestssetesssteesttessreesetessetessetessersteeesseeesseeese 126 10 7 Register definition SUMMALY 00 0 eee eee esses ceeeceeeeeeeeeeeseecaeesaecaecsaesaecaeeseseseeeeeeeseaeeees 161 10 8 Vendor and device id ceccccesscecesecessececessecesseaecesnceessaeecsesaeeceeecesseeecseseeesnseeeusneeesenaes 181 11 AMBA AHB CONTROLLER vrccsussnecsanceorsenascatveneancennd eE a EE EESE 182 11 1 COVEIVIEW apene eE a A es AE EEEE EEA a E e E E 182 11 2 OOP CLAUD doers ete oeenn e E A E Ea E E E e E
121. at automatically generated RMAP responses have higher priority than packets defined in the virtual channel send lists thus bypassing the round robin priority scheme Each send list entry specifies the position and size of the header and the position and size of the data to be transmitted The header and data to be transmitted as well as the send lists can be located anywhere in memory The SpaceWire Module performs direct memory accesses to read data to be transmitted from a memory area 10 4 3 Receive protocols The SpaceWire SPW2 module supports the reception of several protocols as explained hereafter The SpaceWire Link operates on packets A packet includes an optional destination path address a destination logical address a protocol identifier a cargo and an end of packet marker as defined in 10 5 9 2 The basic packet structure is used for implementing the more advanced structures discussed hereafter Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX a RUAG GAISLER Aerospace Defence Technology The SpaceWire Virtual Channel Transfer Protocol VCTP as defined in 10 5 9 5 is used to implement virtual channels on a single SpaceWire link The Remote Memory Access Protocol RMAP as defined in RMAP and in 10 5 9 4 is used to implement remote memory access to resources in the node via the SpaceWire link Both the VCTP and the RMAP protocols can coexist on the
122. ath Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Logical Addr Protocol ID Command amp Type Status Dest Logical Addr Transaction ID MS Transaction ID LS Header CRC8 EOP Figure 10 8 RMAP transfer protocol packet structure for Write response Note that the shaded fields are optional and or can contain a variable number of bytes E g the amount of Source Path Address bytes may be any number from 0 to 12 Note that there is no data cargo and thus no data CRC in this packet 10 5 9 4 3 The read command RMAP Read Command format Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Path Addr Dest Logical Addr Protocol ID Command amp Type Dest Device Key Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Logical Addr Transaction ID MS Transaction ID LS Extended Addr Addr MS Addr Addr Addr LS Data length MS Data length Data length LS Header CRC8 EOP Figure 10 9 RMAP transfer protocol packet structure for Read command Note that the shaded fields are optional and or can contain a variable number of byt
123. bits V O corresponds to address 0 in the cache line V 1 to address 1 V 2 to address 2 and so on 3 2 3 Data cache 3 2 3 1 Operation The data cache is configured as a direct mapped cache The set size is 4 kbyte and divided into cache lines of 16 bytes Each line has a cache tag associated with it consisting of a tag field valid field with one valid bit for each 4 byte sub block On a data cache read miss to a cachable location 4 bytes of data are loaded into the cache from main memory The write policy for stores is write through with no allocate on write miss In a multi set configuration a line to be replaced on read miss is chosen according to the replacement policy If a memory access error occurs during a data load the corresponding valid bit in the cache tag will not be set and a data access error trap tt 0x9 will be generated 3 2 3 2 Write buffer The write buffer WRB consists of three 32 bit registers used to temporarily hold store data until it is sent to the destination device For half word or byte stores the stored data replicated into proper byte alignment for writing to a word addressed device before being loaded into one of the WRB registers The WRB is emptied prior to a load miss cache fill sequence to avoid any stale data from being read in to the data cache Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Te
124. ble for read out when CanRxSIZE SIZE 2 CanRxWR WRITE 2 and CanRxRD READ 0 e There are 2 CAN messages available for read out when CanRxSIZE SIZE 2 CanRxWR WRITE 0 and CanRxRD READ 6 e There are 2 CAN messages available for read out when CanRxSIZE SIZE 2 CanRxWR WRITE 1 and CanRxRD READ 7 e There are 2 CAN messages available for read out when CanRxSIZE SIZE 2 CanRxWR WRITE 5 and CanRxRD READ 3 When a CAN message has been successfully received and stored the write pointer Can RxWR WRITE is automatically incremented taking wrap around effects of the circular buffer into account Whenever the read pointer CanRxRD READ equals CanRxWR WRITE 1 modulo Can RxSIZE SIZE 4 there is no space available for receiving another CAN message The error behavior of the HurriCANe codec is according to the CAN standard which applies to the error counter buss off condition and error passive condition 9 6 3 Location The location of the circular buffer is defined by a base address CanRxADDR ADDR which is an absolute address The location of a circular buffer is aligned on a 1kbyte address boundary Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 9 6 4 Reception procedure When the channel is enabled CanRxCTRL ENABLE 1 and there is space available for a message in the circular buffer as defined by the write and read p
125. ble in the buffer for reception The difference is calculated using the buffer size specified by the FifoRxSIZE SIZE field taking wrap around effects of the circular buffer into account Examples e There are 2 bytes available for read out when FifoRxSIZE SIZE 1 FifoRxWR WRITE 2 and FifoRxRD READ 0 e There are 2 bytes available for read out when FifoRxSIZE SIZE 1 FifoRxWR WRITE 0 and FifoRxRD READ 62 e There are 2 bytes available for read out when FifoRxSIZE SIZE 1 FifoRxWR WRITE 1 and FifoRxRD READ 63 e There are 2 bytes available for read out when FifoRxSIZE SIZE 1 FifoRxWR WRITE 5 and FifoRxRD READ 3 When a byte has been successfully received and stored the write pointer FifoRxWR WRITE is auto matically incremented taking wrap around effects of the circular buffer into account Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX 7 RUAG GAISLER Aerospace Defence Technology 5 5 3 Location The location of the circular buffer is defined by a base address FifoRxADDR ADDR which is an absolute address The location of a circular buffer is aligned on a 1kbyte address boundary 5 5 4 Reception procedure When the channel is enabled FifoRxCTRL ENABLE 1 and there is space available for data in the circular buffer as defined by the write and read pointer a read access will be started towards the FIFO and then an AMBA AHB store access will be starte
126. bypass is set the memory checkbits of the loaded data will be stored in the TCB field during memory read cycles NOTE when the EDAC is enabled the RMW bit in memory configuration register 2 must be set 3 4 10 Memory configuration register 1 MCFG1 Memory configuration register 1 is used to program the timing of rom and local I O accesses 31 30 29 28 27 26 25 24 23 20 19 18 17 12 1110 9 8 7 4 3 0 AR PR T O waitstates Prom write ws Prom read ws VO width S T O enable T O ready enable MemBExcN c Prom write enable enable s Prom width Figure 40 Memory configuration register 1 3 0 Prom read waitstates Defines the number of waitstates during prom read cycles 0000 0 0001 2 0010 4 1111 30 7 4 Prom write waitstates Defines the number of waitstates during prom write cycles 0000 0 0001 2 0010 4 1111 30 9 8 Prom width Defines the data with of the prom area 00 8 10 32 10 Reserved 11 Prom write enable If set enables write cycles to the prom area 17 12 Reserved 19 I O enable If set the access to the memory bus I O area are enabled 23 20 I O waitstates Defines the number of waitstates during I O accesses O000 0 00017 1 0010 2 1111 15 25 Bus error MemBExcN enable 26 Bus ready IoBrdyN enable
127. ccurs In a network situation the first byte of a packet is interpreted as the packet address therefore the error recovery block reads from the transmitter TxFIFO until the next end of packet marker is read from the TxFIFO The transmitter is allowed to start up when error recovery is taking place but the transmitter is prevented from reading from the transmit TxFIFO until error recovery is complete 10 6 9 9 CODEC interconnections The SpaceWire SPW2 Module includes the University of Dundee SpaceWire CODEC The CODEC is connected internally to the rest of the SpaceWire SPW2 Module using buffer memory On the receiver side four levels of buffering are used The first FIFO the RxFIFO is directly controlled by the CODEC and has byte width The SpaceWire Credit Count is defined using this RxFIFO The second FIFO is a byte to word re formatter used to transfer words between the SpwClk to BusClk clock domains with room for 8 bytes Byte transfers would limit the throughput Also note that a transfer is initiated at packet end even if a word has not been filled yet The third buffer is used for storing RMAP command headers and four bytes of data cargo allowing them to be verified and is also used for other types of transfer storing multiple words before transfer The fourth buffer is used for allowing multiple words to be written to memory while still receiving more data from the previous FIFOs Copyright 2006 2007 2008 2
128. ceived data CRC checksum This information can be observed using the SPW RxVC Interrupt Status Register 0 10 6 11 6 RMAP command and response transmission from software Any virtual transmit channel TxVC can be used to transmit RMAP commands or responses from software The transmit handling is similar to what has been described for the Virtual Transmit Channels TxVC in 10 6 11 3 The only difference is that an additional service is provided which calculates the RMAP data CRC checksum byte and adds it to the end of the data field before adding the EOP This service is enabled in the send list entry Note that the RMAP header CRC checksum byte must be calculated by software 10 6 11 7 Reception of unknown protocols in software When transfer protocol support is enabled for Rx VC 0 using the SPW RxVC Config Register 0 any unknown transfer protocols will be stored in the memory buffer allocated to this channel Note that the identification of an unknown protocol is made either by the Protocol ID byte or forcedly for all packets of four bytes or more by setting the SPW RxVC Config Register 0 ForceUnk bit The reception handling is similar to what has been described for the Virtual Receive Channels Rx VC in 10 6 11 2 The only difference is that the first four bytes of a received packet are not deleted before the packet is saved to memory Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009
129. ceiver operation The receiver is enabled for data reception through the receiver enable RE bit in the UART control register The receiver looks for a high to low transition of a start bit on the receiver serial data input pin If a transition is detected the state of the serial input is sampled a half bit clocks later If the serial input is sampled high the start bit is invalid and the search for a valid start bit continues If the serial input is still low a valid start bit is assumed and the receiver continues to sample the serial input at one bit time intervals at the theoretical centre of the bit until the proper number of data bits and the parity bit have been assembled and one stop bit has been detected The serial input is shifted through an 8 bit shift register where all bits have to have the same value before the new value is taken into account effectively forming a low pass filter with a cut off frequency of 1 8 system clock During reception the least significant bit is received first into the receiver shift register RSR The data is then transferred to the receiver holding register RHR and the data ready DR bit is set in the UART status register If RHR was not empty when a character was received the transfer from RSR and setting of DR will not occur until RHR has been emptied by a read access to the UART data register The parity framing break and overrun error bits are set at the received character boundary at the same ti
130. ception is ongoing and that configura tion of the channel is not safe 9 10 13 Receive Channel Address Register CanRxADDR R W TABLE 70 Receive Channel Address Register 31 10 9 0 ADDR 31 10 ADDR Base address for circular buffer 9 0 Reserved No effect when written to Undefined when read All bits are cleared to 0 at reset 9 10 14 Receive Channel Size Register CanRxSIZE R W TABLE 71 Receive Channel Size Register 31 21 20 6 5 0 SIZE 31 21 Reserved No effect when written to Undefined when read 20 6 SIZE The size of the circular buffer is SIZE 4 messages 5 0 Reserved No effect when written to Undefined when read All bits are cleared to 0 at reset Valid SIZE values are between 0 and 16384 Note that each message occupies four 32 bit words Note that the resulting behavior of invalid SIZE values is undefined Note that only SIZE 4 1 messages can be stored simultaneously in the buffer This is to simplify wrap around condition checking 9 10 15 Receive Channel Write Register CanRxWR R W TABLE 72 Receive Channel Write Register 31 20 19 4 3 0 WRITE 31 20 Reserved No effect when written to Undefined when read 19 4 WRITE Pointer to last written message 1 3 0 Reserved No effect when written to Undefined when read All bits are cleared to 0 at reset The field is implemented as relative to the buffer base address scaled with the SIZE field The WRITE field
131. cesses an I O device on a 8 bit bus LDUB STB instructions should be used 3 4 9 Memory EDAC The memory controller in LEON2 FT is provided with an EDAC that can correct one error and detect two errors in a 32 bit word For each word a 7 bit checksum is generated according to the equations below Correction is done on the fly and no timing penalty occurs during correction If an un correct able error double error is detected an memory exception is signalled to the IU If a correctable error occurs no exception is generated but the event is registered in the failing address and memory status register and interrupt 1 is generated The interrupt can then be attached to a low priority interrupt han dler that scrubs the failing memory location The EDAC can be used during access to PROM or RAM areas by setting the corresponding EDAC enable bits in the Error control register see below The equations below show how the EDAC checkbits are generated CBO D0 D4 D6 D7 D8 D9 D11 D14 D17 D18 D194 D21 D26 D28 D29 D31 CB1 D0 D1 D2 D4 D6 D8 D10 D12 D16 D17 D18 D20 D22 D24 D26 D28 CB2 D0 D3 D4 D7 D9 D10 D13 D15 D16 D19 D20 D23 D25 D26 D29 D31 CB3 D0 D1 D5 D6 D7 D11 D12 D13 D16 D17 D21 D22 D23 D27 D28 D29 CB4 D2 D3 D4 D5 D6 D7 D14 D15 D18 D19 D20 D21 D22 D23 D30 D31 CB5 D8 D9 D10 D11 D12 D13 D1
132. cessible Register Names The following convention is used for externally accessible registers e Register names are underlined e g RegisterName e Fields of a register are indicated by the name of the register and the field separated by a period and underlined e g RegisterName Field Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER 10 5 6 RUAG Aerospace Defence Technology 114 Graphics legend Standard graphics for state and mode graphs State or modes are pictured as circulars Double circle indicates the Reset Initial state or mode Single circle indicates State or modes Normal transition Exceptional transition 10 5 7 10 5 7 1 ASIC Module Issue an Interrupt Reset Assertion Terminology General An ASIC internal module The corresponding bit has been set in the pending interrupt register in the ASIC FPGA module An internal reset activation as seen by ASIC FPGA modules GoStop Assertion An internal go stop activation as seen by ASIC FPGA modules 10 5 7 2 Basic Data Types Byte 8 bits of data HalfWord 16 bits of data Word 32 bits of data 10 5 7 3 Registers Register Read A read access to a ASIC external accessible register Register Write A write access to a ASIC external accessible register Set Indicates that the bit in the register is 1 Clear Indicates that the field or bit in the regist
133. channel active during the AMBA AHB error is disabled if the ABORT bit is set to 1b Note that all accesses on the affected channel will be disabled after an AMBA AHB error occurs while the ABORT bit is set to 1b The accesses will be disabled until the affected channel is re enabled setting the FifoTxCTRL ENABLE or FifoRxCTRL ENABLE bit respectively Note that a wait states corresponds to an additional clock cycle added to the period when the read or write strobe is asserted The default asserted width is one clock period for the read or write strobe when WS 0 Note that an idle gap of one clock cycle is always inserted between read and write accesses with neither the read nor the write strobe being asserted Note that an additional gap of one clock cycle with the read or write strobe de asserted is inserted between two accesses when WS is equal to or larger than 100b 5 7 2 Control Register FifoCTRL R W TABLE 18 Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res et 31 2 RESERVED No affect when written to Undefined when read 1 RESET Reset complete FIFO interface all registers 0 RESERVED No affect when written to Undefined when read All bits are cleared to 0 at reset Note that RESET is read back as Ob Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace De
134. chnology Since the processor executes in parallel with the write buffer a write error will not cause an exception to the store instruction Depending on memory and cache activity the write cycle may not occur until several clock cycles after the store instructions has completed If a write error occurs the currently executing instruction will take trap 0x2b Note the 0x2b trap handler should flush the data cache since a write hit would update the cache while the memory would keep the old value due the write error 3 2 3 3 Data cache snooping The data cache can optionally perform snooping on the AHB bus When snooping is enabled the data cache controller will monitor write accesses to the AHB bus performed by other AHB masters DMA When a write access is performed to a cacheable memory location the corresponding cacheline will be invalidated 1n the data cache if present Cache snooping has no overhead and does not affect performance It can be dynamically enabled disabled through bit 23 in the cache control register Cache snooping requires the target technology to implement dual port memories which will be used to implement the cache tag RAM 3 2 3 4 Data cache tag A data cache tag entry consists of several fields as shown in figure 5 31 12 ou 4 3 0 ATAG 00000000 VALID Figure 5 Data cache tag layout Field Definitions 31 12 Address Tag ATAG Contains the address of the data held in the cache line 11 4
135. clarified 7 1 Incorrect text about prescaler and timer relation removed All timers are decremented each timer tick 7 2 Incorrect text about prescaler and timer relation removed All timers are decremented each timer tick 8 2 8 It has been clarified that interrupts on GPIO can only be used in edge detection operation to ensure no list interrupts 9 11 Corrected CAN message memory format 10 Restructured to include SpaceWire SPW2 module information 10 6 2 2 10 2 1 2 Updates regarding external SpwClk1OMBit and SpwClkMul signals 10 6 3 1 10 2 1 6 Defined reset value for RMAPEn 10 6 7 1 10 6 11 8 1 10 7 1 2 Defined HW triggered time code transmission 10 6 7 2 10 6 11 8 2 Defined HW supported time code reception 10 6 7 3 Added information on alternative time code handling 10 6 16 Added information on interrupts 10 7 12 Added SPW Transmit Time Code Mask Register 13 2 Corrected CAN controller plug amp play address 13 3 1 Updated LEON2 on chip register map Ox800000A8 I O port interrupt config register 1 Ox800000AC I O port interrupt config register 2 13 4 2 Added notes on interrupt usage see 3 3 3 3 14 SpwClkPllCnfg 2 pin added Appendix A Space Wire SPW2 module information moved to section 10 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4
136. controller is accessed using an AHB burst request These includes instruction cache line fills double loads and double stores The timing of a burst cycle is identical to the programmed basic cycle with the exception that during read cycles the lead out cycle will only occurs after the last transfer 3 4 7 8 bit PROM and SRAM access To support applications with low memory and performance requirements efficiently it is not necessary to always have full 32 bit memory banks The SRAM and PROM areas can be individually configured for 8 bit operation by programming the ROM and RAM size fields in the memory configuration registers Since read access to memory is always done on 32 bit word basis read access to 8 bit memory will be transformed in a burst of four read cycles Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology During writes only the necessary bytes will be writen Figure 39 shows an interface example with 8 bit PROM and 8 bit SRAM 8 bit PROM Space Wire RTC MemCsN 0 MemOeN 0 MemWrN 0 MemA 22 0 MemD 31 24 Figure 39 8 bit memory interface example 3 4 8 8 bit I O access Similar to the PROM RAM areas the I O area can also be configured to 8 bit mode However the I O device will NOT be accessed by multiple 8 bits accesses as the memory areas but only with one single access just as in 32 bit mode To ac
137. d The received data will be temporarily stored in a local store buffer in the FIFO controller Note that the channel should not be enabled until the write and read pointers are configured to avoid the data reception to start prematurely After a datum has been successfully stored the FIFO controller is ready to receive new data The write pointer FifoRxWR WRITE is automatically incremented taking wrap around effects of the circular buffer into account Interrupts are provided to aid the user during reception as described in detail later in this section The main interrupts are the RxError RxParity RxFull and RxIrq which are issued on the unsuccessful reception of data due to an AMBA AHB error or parity error when the buffer has been successfully filled and when a predefined number of data have been received successfully All accesses to the AMBA AHB bus are performed as two consecutive 32 bit accesses in a burst or as a single 32 bit access in case of an AMBA AHB bus error 5 5 5 Straight buffer It is possible to use the circular buffer as a straight buffer with a higher granularity than the 1kbyte address boundary limited by the base address FifoRxADDR ADDR field While the channel is disabled the write pointer FifoRxWR WRITE can be changed to an arbitrary value pointing to the first data to be received and the read pointer FifoRxRD READ can be changed to an arbitrary value When the channel is enabled the reception will sta
138. d Address field The Extended Address field as supported by the RMAP hardware implementation in the SpaceWire SPW2 Module Extended Address 7 6 5 4 3 2 1 0 DMA Page LSB MSB Value DMA page 00002 Extended Address range i e address bits A35 A32 above the 1111 normal 32 bit range Note that the SpaceWire SPW2 Module does not support an Extended Address value above F16 This gives a total address range of 64 GiB 10 5 9 5 SpaceWire Virtual Channel Transfer Protocol packet structure VCTP The virtual channel transfer protocol is a legacy SpaceWire packet protocol where the last byte before the data cargo of a packet contains the virtual channel identification information Logical Protocol Dummy Virtual Data cargo EOP Address ID Channel ID 1 byte lbyte l byte 1 byte 0 16 MiB Figure 10 11 VCTP transfer protocol packet structure using logical addressing Path Logical Protocol Dummy Virtual Data cargo EOP Address Address ID Channel ID 1 12 bytes 1 byte 1 byte l byte 1 byte 0 16 MiB Figure 10 12 VCTP transfer protocol packet structure using path addressing The Protocol ID used for identifying a VCTP packet is defined in the SPW VC Transfer Protocol ID Register The default value is F016 The Virtual Channel ID indicates on which virtual channel the data shall be stored The SPW2 supports a configurable number of independent virtual
139. d in memory for further software processing Note that the header CRC is not removed even in read commands Software supported RMAP commands and responses The SpaceWire SPW2 Module automatically verifies the combined response header and data CRCs as follows Check CRC for the complete RMAP responses as calculated over header header checksum and data Issue the CRCDataErr Interrupt if the total checksum is not correct and RMAP software handling is enabled The interrupt is issued after all data have been stored to memory Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX a RUAG GAISLER Aerospace Defence Technology Remove the data CRC checksum byte before the response is stored in memory for further software handling Note that the RMAP response headers cannot be checked explicitly as the position of the checksum is unknown to the hardware Note that verification of the data consistency for other transfer protocol cannot be performed since the protection algorithms are unknown 10 6 4 4 Destination Key verification When the hardware support is enabled the SpaceWire SPW2 Module supports the RMAP command Destination Key for hardware supported command as follows An exact match between the RMAP command Destination Key field and the SPW RMAP Destination Key Register default 0016 must occur for an RMAP command to be executed Ifan incoming RMAP c
140. d the first cycle after it arrives from the memory and appears on the bus the next cycle if no uncorrectable error is detected The decoding is done by comparing the stored checksum with a new one which is calculated from the stored data This decoding is also done during the read phase for a subword write A so called syndrome is generated from the comparison between the checksum and it determines the number of errors that occurred One error is automatically corrected and this situation is not visible on the bus Two or more detected errors cannot be corrected so the operation is aborted and the required two cycle error response is given on the AHB bus see the AMBA manual for more details If no errors are detected data is passed through the decoder unal tered As mentioned earlier the AHB RAM provides read and write diagnostics when EDAC is enabled When write diagnostics are enabled the calculated checksum is not stored in memory during the write phase Instead the TCB field from the configuration register is used In the same manner if read diag nostics are enabled the stored checksum from memory is stored in the TCB field during a read and also during a subword write This way the EDAC functionality can be tested during run time Note that checkbits are stored in TCB during reads and subword writes even if a multiple error is detected An additional feature is the single error counter A single error counter SEC field is present in the c
141. dated to implementation 3 4 5 Maximum SRAM area corrected 3 4 9 SDRAM reference removed 10 6 7 4 Restructured 10 8 ESA removed as vendor identifier Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 o RUAG EROFLEX GAISLER Aerospace Defence Technology TABLE 97 Revision control Revision Date Sections Comment 1 8 2008 May 3 3 1 Updated LEON on chip register map 0x800000A8 I O port interrupt config register 1 Ox800000AC I O port interrupt config register 2 3 3 3 3 Updated secondary interrupt controller assignment list adding GPIO interrupts Added notes on interrupt usage 5 5 1 Clarified that the hardware not the software cannot fill the receiver buffer completely 5 7 11 The incorrect RxEmpty was changed to RxFull The buffer full condition has been increased from less than two words to two words or less 5 7 13 The number of bytes that can be stored in the buffer has been reduced by 4 5 7 15 The number of unused words in the buffer has been increased by one 6 1 1 It has been clarified that simultaneous ADC and DAC conversion is not possible 6 2 2 It has been clarified that triggering events are ignored if conversion already in progress 6 3 2 The cause of a conversion rejection has been clarified 6 3 3 The cause of a conversion rejection has been clarified 6 3 4 The cause of a conversion rejection has been
142. de is enabled the register checksum is XORed with the TCB field before written to the register file The CNT field is incremented each time a register correction is performed but saturates at 111 3 1 6 Processor reset operation The processor is reset by asserting the RESET input for at least one clock cycle The following table indicates the reset values of the registers which are affected by the reset All other registers maintain their value or are undefined TABLE 2 Processor reset values Register Reset value PC program counter 0x0 nPC next program counter 0x4 PSR processor status register ET 0 S 1 CCR cache control register 0x0 Execution will start from address 0 3 1 7 Exceptions LEON adheres to the general SPARC trap model The table below shows the implemented traps and their individual priority When PSR processor status register bit ET 0 an exception trap causes the processor to halt execution and enter error mode and the external error signal will then be asserted TABLE 3 Trap allocation and priority Trap TT Pri Description reset 0x00 1 Power on reset write error Ox2b 2 write buffer error instruction_access_error 0x01 3 Error during instruction fetch illegal_instruction 0x02 5 UNIMP or other un implemented instruction privileged_instruction 0x03 4 Execution of privileged instruction in user mode fp_disabled 0x04 6 FP instruction wh
143. e SpaceWire SPW2 Module has a Protocol ID value of 0116 and this is thus not a valid value for VCTPID Field Description VCTPID Configuration of SpaceWire Transfer protocol ID for the VCTP protocol SPW SW Transmit Time Code Register SPW_SWTTCR W 31 8 7 6 5 0 TxTimeCtrl MSB i LSB Function This registers is used for triggering a Time Code transmission Timing Writes are ignored while a time code transmission is taking place A minimum separation of 10 us between writes is recommended Constraints Field Description TxTimeCtrl New TxTimeCtrl value to be transmitted when written SPW Transmit Time Code Mask Register SPW_TTCMR R W 31 0 Select 0 MSB LSB Function This registers is used for selecting interrupts for Time Code transmission Timing Constraints Field Description Select Specifies what bits of the AMBA APB interrupt bus shall cause a tick on the SpwTxTick input to the SpaceWire module Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX e RUAG GAISLER Aerospace Defence Technology 10 7 1 3 Status register SPW Status Register SPW_SR R 31 24 23 16 ActiveRxVC MSB 15 8 7 2 1 0 ActiveTxVC RxVC TxVc Act Act 0 0 0 0 LSB Function This register provides status information
144. e Technology 8 2 1 Input Register GpioIN R TABLE 49 Input Register 31 24 23 0 n 31 24 Reserved No effect when written to Undefined when read 23 0 IN Input Data Note that only bits 23 to 0 are implemented 8 2 2 Output Register GpioOUT R W TABLE 50 Output Register 31 24 23 0 OUT 31 24 Reserved No effect when written to Undefined when read 23 0 OUT Output Data All bits are cleared to 0 at reset Note that only bits 23 to 0 are implemented 8 2 3 Direction Register GpioDIR R W TABLE 51 Direction Register 31 24 23 0 DIR 31 24 Reserved No effect when written to Undefined when read 23 0 DIR Direction Ob input 1b output All bits are cleared to 0 at reset Note that only bits 23 to 0 are implemented 8 2 4 Pulse Register GpioPULSE R W TABLE 572 Pulse Register 31 8 7 0 PULSE 31 24 Reserved No effect when written to Undefined when read 23 0 PULSE Pulse enable Ob output 1b pulse command output All bits are cleared to 0 at reset Only channels configured as outputs are possible to enable as command pulse outputs Note that only bits 7 to 0 are implemented Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 8 2 5 Pulse Counter Register GpioCNTR R W TABLE 53 Pulse Counter Register 31 200 49 0 CNTR
145. e load bit in the control register The watchdog operates similar to the timers with the difference that it is always enabled and upon underflow asserts the external signal WDOG This signal can be used to generate a system reset To minimise complexity the two timers and watchdog share the same decrementer This means that the minimum allowed prescaler division factor is 4 reload register 3 3 3 4 2 Registers Figures 18 to 22 shows the layout of the timer unit registers 31 0 TIMER WATCHDOG VALUE Figure 18 Timer 1 2 and Watchdog counter registers Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX g RUAG GAISLER Aerospace Defence Technology TIMER RELOAD VALUE Figure 19 Timer 1 2 reload registers 31 3 2 10 RESERVED LD RL JEN Figure 20 Timer 1 2 control registers 2 Load counter LD when written with one will load the timer reload register into the timer counter register Always reads as a zero 1 Reload counter RL if RL is set then the counter will automatically be reloaded with the reload value after each underflow 0 Enable EN enables the timer when set 31 3 Reserved No effect when written to Undefined when read 31 10 9 0 RESERVED RELOAD VALUE Figure 21 Prescaler reload register 31 10 Reserved No effect when written to Undefined whe
146. e that the resulting behavior of invalid SIZE val ues is undefined Note that only SIZE 64 8 bytes can be stored simultaneously in the buffer This is to simplify wrap around condition checking 5 7 14 Receive Channel Write Register FifoRxWR R W TABLE 30 Receive Channel Write Register 31 16 15 0 WRITE 31 16 RESERVED No affect when written to Undefined when read 15 0 WRITE Pointer to last written byte 1 All bits are cleared to 0 at reset The field is implemented as relative to the buffer base address scaled with SIZE field The WRITE field is written to automatically when a transfer has been completed successfully indicat ing the position 1 of the last byte received Note that the WRITE field can be used to read out the progress of a transfer Note that the WRITE field can be written to in order to set up the starting point of a transfer This should only be done while the transmit channel is not enabled Note that the LSB may be ignored for 16 bit wide FIFO devices Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 5 7 15 Receive Channel Read Register FifoRxRD R W TABLE 31 Receive Channel Read Register 31 16 15 0 READ 31 16 RESERVED No affect when written to Undefined when read 15 0 READ Pointer to last read byte 1 All bits are cleared to 0 at reset The field is
147. ead RESET Reset complete core when 1 ENABLE Enable HurriCANe controller when 1 Reset HurriCANe controller when 0 All bits are cleared to 0 at reset Note that RESET is read back as Ob Note that ENABLE should be cleared to Ob while other settings are modified ensuring that the Hurri CANe core is properly synchronized Note that when ENABLE is cleared to Ob the CAN interface is in sleep mode only outputting reces sive bits Note that the HurriCANe core requires that 10 recessive bits be received before receive and transmit operations can begin Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 9 10 4 SYNC Code Filter Register CanCODE R W TABLE 61 SYNC Code Filter Register 31 30 29 28 0 SYNC 31 29 Reserved No effect when written to Undefined when read 28 0 SYNC Message Identifier All bits are cleared to 0 at reset Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0 9 10 5 SYNC Mask Filter Register CanMASK R W TABLE 62 SYNC Mask Filter Register 31 30 29 28 0 MASK 31 29 Reserved No effect when written to Undefined when read 28 0 MASK Message Identifier All bits are set to 1 at reset Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0 A RxSYNC message ID is matched when Received ID XOR CanCODE SYNC AND Can
148. ead accesses are performed as incremental bursts except when close to the location specified by the interrupt pointer register at which point the last bytes might be fetched by means of single accesses Data transferred via the FIFO interface can be either 8 or 16 bit wide The handling of the transmit channel is however the same All transfers performed by the AMBA AHB master are 32 bit word based No byte or half word transfers are performed To handle the 8 and 16 bit FIFO data width a 32 bit read access might carry less than four valid bytes In such a case the remaining bytes are ignored When additional data are available in the circu lar transmit buffer the previously fetched bytes will be re read together with the newly written bytes to form the 32 bit data Only the new bytes will be transmitted to the FIFO not to transmit the same byte more than once The aforementioned write address pointer indicates what bytes are valid An interrupt is generated when the circular transmit buffer is empty The status of the external FIFO is observed via the AMBA APB slave interface indicating Full Flag and Half Full Flag 5 1 3 Reception Data received via the FIFO interface are stored via the AMBA AHB master interface to on chip or off chip memory This is performed by means of direct memory access DMA implementing a circular receive buffer in the memory The receive channel is programmable via the AMBA APB slave inter face which is also u
149. eak The best scaler value for manually programming the baudrate can be calculated as follows scaler system_clk 10 baudrate 8 5 10 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 31 14 13 0 RESERVED SCALER RELOAD VALUE Figure 57 DSU UART scaler reload register 31 14 Reserved No effect when written to Undefined when read 3 5 4 Common operations 3 5 4 1 Instruction breakpoints Instruction breakpoints can be inserted by writing the breakpoint instruction ta 1 to the desired memory address software breakpoint or using any of the four integer unit hardware breakpoints Since cache snooping is only done on the data cache the instruction cache must be flushed after the insertion or removal of software breakpoints To minimize the influence on execution it is enough to clear the corresponding instruction cache tag valid bit which is accessible through the DSU The two DSU hardware breakpoints should only be used to freeze the trace buffer and not for software debugging since there is a 4 instruction delay from the breakpoint hit before the processor enters the debug mode 3 5 4 2 Single stepping By setting the SS bit and clearing the BN bit in the DSU control register the processor will resume execution for one instruction and then automatically return to debug mode 3 5 4 3 Booti
150. ebug mode Block transfers can be performed be setting the length field to n 1 where n denotes the Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology number of transferred words For write accesses the control byte and address is sent once followed by the number of data words to be written The address is automatically incremented after each data word For read accesses the control byte and address is sent once and the corresponding number of data words is returned The UART receiver is implemented with same glitch filtering as the nominal UARTs 3 5 3 2 DSU UART control register 31 2 1 0 RESERVED BL EN Figure 55 UART control register 31 2 Reserved No effect when written to Undefined when read 0 Receiver enable RE if set enables both the transmitter and receiver 1 Baud rate locked BL is automatically set when the baud rate is locked 3 5 3 3 DSU UART status register 31 765 4 3 2 10 RESERVED FE OV TH TS DR Figure 56 UART status register 0 Data ready DR indicates that new data has been received and not yet read out by the AHB master interface 1 Transmitter shift register empty TS indicates that the transmitter shift register is empty 2 Transmitter hold register empty TH indicates that the transmitter hold register is empty 3 Re
151. ected register value is also written back to the register file A correction operation incurs a delay 4 clock cycles but has no other T aa impact If an un correctable error is detected a register error trap tt 0x20 is generated The implemented protection scheme has an impact on double store instructions the write buffer will delay the request of the memory bus one clock cycle in order to not start any memory store cycle before the second store data word has been checked and potentially corrected Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX i RUAG GAISLER Aerospace Defence Technology The register file protection operation is controlled using application specific register 16 asr16 The register is accessed using the RDASR WRASR instructions 31 12 11109 8 765 4 3 2 1 0 RESERVED CNT 2 0 TCB 6 0 TE DI Figure 1 Register file protection control register asr16 0 DI disable checking If set will disable the register file checking function 1 TE Test enable 8 2 TCB 6 0 Test checkbits 11 9 CNT 2 0 Error counter This field will be incremented for each corrected error The protection can be disabled by clearing the DI bit this bit is set to 1 after reset By setting the TE bit errors can be inserted in the register file to test the protection function Since a 7 bit EDAC is used when the test mo
152. ed LinkAbort SPW CODEC Status Register LinkState has made a transition from Run to Error Reset 10 7 1 2 SPW CODEC Configuration Register SPW_CCR Configuration registers 31 5 4 3 2 1 0 Tx Rx Auto Link Link Fifo Fifo Start Dis Start Flush Flush 0 0 I 0 0 MSB LSB Function This register configures the start up behaviour of the SpaceWire CODEC controlling the Link Interface Control State Machine The link can be disconnected during normal operation by setting the LinkDis bit Timing Constraints Note that one node on the link must be configured to LinkStart for NULL tokens to start to flow and to thus get a link connection The other node should be configured to AutoStart lest the nodes send NULL tokens while the opposite node is in ErrorReset or ErrorWait The RxFifoFlush and TxFifoFlush bits shall only be used when the link is not in the Run state To ensure this the user shall use one of the methods described in 10 6 11 1 1 Field Value Description LinkStart 0 SpaceWire link cannot proceed to Started state unless AutoStart is set l SpaceWire link can proceed to Started state if the link has the LinkDis bit cleared See 10 6 2 LinkDis SpaceWire link is enabled 1 SpaceWire link is disabled i e the LICSM proceeds directly to the ErrorReset state when reaching the Run state See 10 6 2 AutoStart No Auto s
153. ed Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX r RUAG GAISLER Aerospace Defence Technology 3 3 5 6 UART registers 31 8 7 0 RESERVED DATA Figure 25 UART data register 7 0 Receiver holding register read access 7 0 Transmitter holding register write access 31 8 Reserved No effect when written to Undefined when read 31 8 765 4 3 2 10 RESERVED ec LB FL PE Ps T1 R1 TE RE Figure 26 UART control register Receiver enable RE if set enables the receiver Transmitter enable TE if set enables the transmitter Receiver interrupt enable RI if set enables generation of receiver interrupt Transmitter interrupt enable TT if set enables generation of transmitter interrupt Parity select PS selects parity polarity 0 even parity 1 odd parity Parity enable PE if set enables parity generation and checking Flow control FL if set enables flow control using CTS RTS Loop back LB if set loop back mode will be enabled External Clock EC if set the UART scaler will be clocked by LeonPio 3 31 9 Reserved No effect when written to Undefined when read OCANIKDN FPWN KY CO 31 765 4 3 2 10 RESERVED FE PE OV BR TH TS DR Figure 27 UART status register 0 Data ready DR indicates that new data is available in the receiver h
154. ed DLA Check the second byte Protocol ID Check the third byte if applicable for a valid RMAP command Check fourth byte if applicable for a valid VCID Reject and discard the packet and issue an interrupt if no enabled RxVC RxVC 0 or RMAP hardware handler could be identified ld a a The identification process results in one of the following The received packet belongs to the VCTP protocol and is forwarded to the corresponding Rx VC channel when it is implemented and enabled The received packet is a hardware supported RMAP command and is forwarded to the RMAP handler when it is enabled The received packet is a RMAP command not supported in hardware or the hardware is disabled and is forwarded to Rx VC 0 when it is enabled The received packet belongs to an unknown protocol or forced unknown protocol interpretation is configured through SPW RxVC Config Register 0 ForceUnk and is forwarded to RxVC 0 when it is enabled The received packet is rejected and all data is discarded until the next EOP or EEP The SpaceWire SPW2 Module rejects packets Ifthe packet DLA does not match the corresponding programmable field in the SPW RxVC Config Register 0 Note that for RMAP commands a response will be generated if the packet is otherwise correct and an ackowledge is requested and a received RMAP response will be stored if enabled for Rx VC 0 DLA is not checked if forced unknown protocol interpretation
155. ee o MI SS Se MPA Ela Re oe H result 5s lt gt gt Pe yiMpe i Se ee a eee a Memory o D cache 32_ address dataout 32 lt datain bare sa kre ae Se W e oS 4 es SS W pE je e pe eee SS owres aime se Se eoi sa er oe Ne dS eee eee a Write 39 l tbr wim psr rd regfile rst rs2 Figure 2 LEON integer unit block diagram 3 1 2 Instruction pipeline The LEON integer unit uses a single instruction issue pipeline with 5 stages 1 FE Instruction Fetch If the instruction cache is enabled the instruction is fetched from the instruction cache Otherwise the fetch is forwarded to the memory controller The instruction is valid at the end of this stage and is latched inside the IU Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 2 DE Decode The instruction is decoded and the operands are read Operands may come from the register file or from internal data bypasses CALL and Branch target addresses are generated in this stage EX Execute ALU logical and shift operations are performed For memory operations e g LD and for JMPL RETT the address is generated ME Memory Data cache is accessed For cache reads the data will be valid by the end of this stage at which point it is aligned as appropriate Store data read out in the execution stage is written to the data cache at
156. eld Description DMA Base Byte base address for a DMA access Address SPW _RxVC DMA Block Size Register SsPW_RxDBSR R WT 31 24 23 0 DMA Block Size 0 MSB LSB Function This register is used for configuring the maximum number of bytes to be received for a block transfer Writing to this register is used as an automatic start of a DMA block transfer The RxVC is triggered by software when a write access is made to the this register unless the SPW RxVC Config Register 0 RxEn bit is cleared or any RxVC or TxVC FlushAbort interrupt is pending All relevant counters are automatically cleared for the virtual receive channel and any previous halt condition is released The SPW RxVC Status Register ChTrig bit is automatically set Timing Constraints This register should not be written if the channel is already triggered The block size should never be written with the value 0 Field Description DMA Block Total number of bytes to be received during a DMA block transfer Size SPW RxVC DMA Offset Register SPW_RxDOR R W 31 24 23 0 DMA Offset 0 MSB LSB Function This register indicates the next byte address to be written relative to the DMA Base Address Timing This register is reset automatically when the channel is triggered and is incremented automatically as the reception progresses Constraints This register must not be written to during reception The writability of this register is implemented
157. eld otherwise it will be rejected The handling of transfer protocols through RxVC 0 is summarised as follows Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG 174 GAISLER Aerospace Defence Technology Detailed SPW RxVC Config Register 0 bit usage RMAPEn Enabled RxEn 1 Enabled RxEn 0 Disabled TrPtcISW 1 TrPtcISW 0 TrPtcLSW 1 TrPtcISW 0 Enabled Disabled Enabled Disabled RMAP HW supported OK OK OK OK RMAP not HW supported WrMem Reject Reject Reject RMAP Response WrMem WrMem Reject Reject Unknown protocol WrMem Reject Reject Reject RMAPEn 0 Disabled RxEn 1 Enabled RxEn 0 Disabled TrPtcISW 1 TrPtcISW 0 TrPtcLSW 1 TrPtclISW 0 Enabled Disabled Enabled Disabled RMAP HW supported WrMem Reject Reject Reject RMAP not HW supported WrMem Reject Reject Reject RMAP Response WrMem WrMem Reject Reject Unknown protocol WrMem Reject Reject Reject Legend OK means RMAP command executed by hardware WrMem means that the packet is written to memory using RxVC 0 channel and Reject means that the full packet is rejected RMAP not HW supported means that the RMAP command byte content is not supported by the handler implemented in hardware If a command is considered to be RMAP HW supported but the address alignment or block size is not supported the c
158. ely emptied This is observable through the TxParked and or RxParked bits in SPW CODEC Status Register 5 Clear the TxFifoFlush RxFifoFlush and LinkDis bits and set the AutoStart or LinkStart bit in SPW CODEC Configuration Register 6 Wait until the link is connected This is observable through SPW CODEC Status Register LinkState 7 Re trig the relevant channels Note that all FlushAbort interrupt status bits for both Rx and Tx must be cleared before any Rx or Tx channel can be triggered 10 6 11 2 Virtual Receive Channels RxVC The SpaceWire SPW2 Module implements zero or more not counting Rx VC 0 which is always present Virtual Receive Channels RxVC adhering to the SpaceWire Virtual Channel Transfer Protocol VCTP To setup reception on RxVC the following steps need to be performed Setup the word padding option and enable the channel using the SPW RxVC Config Register Setup up the location in memory for the buffer to which packets are to be received The location is defined using the SPW Rx VC DMA Page Register and the SPW Rx VC DMA Base Address Register Setup optionally the maximum number of packets that should be received using the SPW RxVC Packet Counter Register Setup the size of the buffer limiting the amount of data that should be received using the SPW RxVC DMA Block SizeRegister This also triggers the channel which is now ready to receive packets The progr
159. er If the LR bit is not set a write access does not return any response while a read access only returns the read data Data is sent on 8 bit basis as shown in figure 54 Through the communication link a read or write transfer can be generated to any address on the AHB bus LeonDsukx _ Receiver shift register t AHB master interface DSU Write Command Send Receive Send Receive 11 Length 1 Addr 31 24 Addr 23 16 Addr 15 8 Addr 7 0 Data 31 24 Data 23 16 Data 15 8 Data 7 0 Resp byte optional Response byte encoding DSU Read command bit 7 3 00000 bit 2 DMODE 10 Length 1 Addr 31 24 Addr 23 16 Addr 15 8 Addr 7 0 bit 1 0 AHB HRESP Data 31 24 Data 23 16 Data 15 8 Data 7 0 Resp byte optional Baud rate generator 8 bitclk Serial port Controller _ AMBA APB Transmitter shift register gt K LeonDsuTx AHB data response AMBA AHB Figure 52 DSU communication link block diagram Start DO D1 D2 D3 D4 D5 D6 D7 Stop Figure 53 DSU UART data frame Figure 54 DSU Communication link commands A response byte can optionally be sent when the processor goes from execution mode to d
160. er is 0 Reset Indicates that the field or bit in the register is set to its default Value indicated in the Register definition chapter 10 5 7 4 Register Access Read R Register read where the register is read as is the read has no effect on the register Read and Clear Register read where the register is read as is and the register content RC is cleared Read Masked Register read where the register is read and masked with the content RM of the corresponding mask register Read and Clear Register read where the register is read and masked with the content Masked RCM of the corresponding mask register and unmasked register bits are Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG cleared RTC 100 0012 December 2009 Version 2 4 EROFLEX i RUAG GAISLER Aerospace Defence Technology Read Masked and Register read where the register is read and masked with the content Clear RMC of the corresponding mask register and the register content is cleared Write W Register write where the register content is updated according to the provided parameter Write and Trigger Register write where the register content is updated according to the WT provided parameter and hardware processing is triggered activated Set S Register write where the bits that are set in the provided parameter is also set in the register bits that are cleared in the provided parameter is unaffected in the register Clear C Regi
161. eroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX l RUAG GAISLER Aerospace Defence Technology 2 FUNCTIONAL OVERVIEW 2 1 General functionality The SpaceWire RTC ASIC implements the following functions Processor e The SpaceWire RTC ASIC includes the LEON2 FT SPARC V8 Integer Unit featuring an instruction cache of 4 kbytes and a data cache of 4 kbytes and a Meiko Floating Point Unit Debug Support Unit e The SpaceWire RTC ASIC includes the LEON2 FT Debug Support Unit DSU with a Trace Buffer of 512 lines of 16 bytes Debug Serial Link UART e The SpaceWire RTC ASIC includes the LEON2 FT serial debug interface for AMBA AHB The SpaceWire RTC ASIC includes the LEON2 FT peripherals e Interrupt Controller and Secondary Interrupt Controller e 32 bit Timers three e UART Serial Links two e 16 bit General Purpose Input Output Memory Interface e The SpaceWire RTC ASIC includes the LEON2 FT Memory Controller including EDAC protection and support for SRAM PROM EEPROM and a memory mapped I O area On Chip Memory e The SpaceWire RTC ASIC includes 64 kbytes EDAC protected on chip memory FIFO Interface e The SpaceWire RTC ASIC can simultaneously interface two FIFO devices one for input and one for output The interface features one DMA channel in either direction ADC DAC Interface e The SpaceWire RTC ASIC can simultaneously interface ADC and DAC devices 32 bit Timers e The SpaceWire RTC ASIC
162. erospace Defence Technology Simultaneously receive and transmit Virtual Channel Transfer Protocol packets VCTP Receive verify and execute an RMAP command and simultaneously transmit an RMAP command to another node Transmit an RMAP response and simultaneously receive an RMAP response to a previously transmitted RMAP command There are no known limitations to the simultaneous receive and transmit capabilities of the SpaceWire SPW2 Module 10 6 2 SpaceWire Link The SpaceWire link is implemented using the University of Dundee SpaceWire CODEC which implements low level transmission and reception over the SpaceWire link The SpaceWire CODEC contains a Link Interface Control State Machine referred to as LICSM that controls the overall operation of the link interface The LICSM provides link initialisation normal operation and error recovery services The SpaceWire CODEC contains status and configuration signals that are read and set via the internal register bus Time codes to be received or transmitted by the SpaceWire CODEC are read or written via registers The detailed description of the SpaceWire CODEC can be found in CODEC 10 6 2 1 Link configuration and start up Link start up works as seen in the figure below Link start and disable is controlled by the SPW CODEC Configuration Register Note that when reset this register enables the auto start mode This means that the CODEC at start up will remain in the Ready sta
163. error is detected which un triggers the channel then this is reported by issuing an error interrupt CRCDataErr FlushAbort DmaWrErr and RxEEP interrupts This information can be observed using the SPW RxVC Interrupt Status Register When reception has been halted due to an error e g DmaWrErr SPW RxVC Status Register PktCnt will indicate the number of received error free packets and SPW RxVC Current Packet Status Register will point to the start of the faulty packet Note that due to system behaviour DmaWr Err may be detected after the SPW RxVC DMA Offset Register has been incremented The current offset decremented by one will point to the packet with the faulty access but not necessarily to the faulty address The progress of the reception can also be observed using the SPW First Failing Packet Register indicating if an error has occurred in the first four bytes of a VCTP When a packet is stored to memory the first four bytes of the received packet are stripped removing the protocol header with the virtual channel routing information To disable or prematurely un trigger a virtual receive channel do the following Clear SPW RxVC Config Register RxEn Check SPW RxVC Status Register ChAct to see if the channel had started to receive a packet before before being disabled If that is the case wait and if necessary re trigger the channel until the entire packet has been received To disable or prematurely
164. ers 31 0 Timer Counter value Decremented by 1 for each prescaler tick 31 0 TIMER RELOAD VALUE Figure 71 Timer reload value registers 31 0 Timer Reload value This value is loaded into the timer counter value register when 1 is written to load bit in the timers control register 31 7 6 5 4 3 2 1 0 000 0 DH CH IP IE LD RS EN Figure 72 Timer control registers 31 7 Reserved No effect when written to Undefined when read 6 Debug Halt DH Value of GPTI DHALT signal which is used to freeze counters e g when a system is in debug mode Read only 5 Chain CH Chain with preceding timer If set for timer n decrementing timer n begins when timer n 1 underflows 4 Interrupt Pending IP Sets when an interrupt is signalled Remains 1 until cleared by writing 0 to this bit 3 Interrupt Enable IE If set the timer signals interrupt when it underflows 2 Load LD Load value from the timer reload register to the timer counter value register 1 Restart RS If set the value from the timer reload register is loaded to the timer counter value register and decrementing the timer is restarted 0 Enable EN Enable the timer Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX j RUAG GAISLER Aerospace Defence Technology 31 0 SELECT
165. es E g the amount of Destination Path Address bytes may be any number from 0 to 12 Note that there is no data cargo and thus no data CRC in this packet 10 5 9 4 4 RMAP Read Response format The read command response Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Path Addr Source Logical Addr Protocol ID Command amp Type Status Dest Logical Addr Transaction ID MS Transaction ID LS Reserved 0 Data Length MS Data Length DataLength LS Header CRC8 Data Data Data Data Data Data Data Data Data Data CRC8 EOP Figure 10 10 RMAP transfer protocol packet structure for Read response Note that the shaded fields are optional and or can contain a variable number of bytes E g the amount of Source Path Address bytes may be any number from 0 to 12 Note that Header CRC8 is the last byte of the header Note that the Data CRC8 byte is not optional Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX 12 RUAG GAISLER Aerospace Defence Technology 10 5 9 4 5 Command and Type field The Command amp Type field used in the RMAP command and response headers Command amp Type Packet Type Command 6 5 Reserved Command Write Verify Data Increment Source Path Addr Le
166. espectively Write Write Read Read Write Write Read Read Idle Idle Idle WS WS WS WS WS WS WS WS SysClk FifoWrN A a E E FifoRdN E A 7 e GITO OTHE FifoEmpN 7 FifoFullN AS FifoHalfN 7 Sample Sample Sample Sample Sample Sample Sample FifoFullN FifoFullN FifoEmpN FifoEmpN FifoFullN FifoFullN FifoEmpN Settings WS 0 Figure 61 FIFO read and write access waveform O wait states WS Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology Write Gap Idle Read Gap Idle Write WS WS WS WS WS WS WS WS WS WS WS WS WS SysClk FifoWrN FifoRdN j FifoD FifoP K DX KO FifoEmpN Fa FifoFullN FifoHalfN Sample Sample FifoFullN FifoEmpN Settings WS 4 with additional gap between accesses Figure 62 FIFO read and write access waveform 4 wait states WS Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 5 4 Transmission The transmit channel is defined by
167. ess of the reception can be observed using the following registers The address of the next data to be stored relative to the SPW Rx VC DMA Base Address Register can be observed using the SPW RxVC DMA Offset Register The start address of the currently received packet can be observed using the SPW RxVC Current Packet Status Register Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX P RUAG GAISLER Aerospace Defence Technology The number of packets received since the channel was last trigger can be observed using the SPW RxVC Status Register SPW RxVC Status Register can also be used for observing if the channel is triggered and if the channel is active receiving a message Note that if ChAct is set but not ChTrig then there is a packet in the Rx FIFOs waiting to be handled The decision to handle this packet has already been made so if the RxVC is disabled at this point the packet will remain in the Rx FIFOs until the channel is triggered thus blocking the reception of the next packets The overall progress of reception can be observed using the SPW Status Register which indicates which channel is active receiving a message During nominal reception interrupts are issued to indicate that the pre set number of packets has been received CntTrig interrupt or that the allocated memory buffer has been filled RxEOB interrupt If an
168. ess than three bytes have been received due to an EOP or EEP the type of exit character will be stored after the data bytes EOP 0 EEP 1 and the possible remaining byte in the SPW First Failing Packet Register will be cleared to zero and the HeadErr failure cause will be recorded The SPW First Failing Packet Register keeps its value after a detected failure until a read access has been performed to the register After a read access the function is ready to once again capture on a failure event The SPW First Failing Packet Register contains the following information Destination Logical Address 1 st received byte Protocol Identifier 2 nd received byte Protocol dependent information 3 rd received byte Failure Type which caused the trigger event see below The contents of the 3 rd received byte is protocol dependent For RMAP commands and RMAP responses it comprises the Packet Type Command and Source Path Address Length fields For VCTP it comprises the Dummy field For unknown protocols it comprises the contents of the 3 rd received byte Once the protocol identification has succeeded i e the first bytes of a packet were correct then erroneous VCTP data transfers or protocol handled by software RMAP or unknown do not trigger the SPW First Failing Register as hardware cannot distinguish where the header checksum is located or if a data CRC exists Neither do EOP or EEP in these cases cause a triggerin
169. f the RMAP transfer protocol and for any future transfer protocols The RxVC 0 virtual receive channel is treated in the same way as the virtual channels described above except that the first four bytes of a packet are not stripped The dedicated RxVC 0 is used for the following purposes For all RMAP responses For any RMAP command not supported in hardware or for all RMAP commands when hardware support is not enabled For all unknown transfer protocols Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX ua RUAG GAISLER Aerospace Defence Technology Note that RMAP commands that are supported by hardware do not use Rx VC 0 When SPW RxVC Config Register 0 WordAlign is cleared the first byte of a packet is written at the address directly after the last byte of the previous one Bytes outside a packet with mis aligned start or end will not be modified When the bit is set the end of every packet is padded with arbitrary content up to the closest 32 bit word boundry i e the first byte of a packet will always be word aligned The last byte of a packet will always be written before and never simultaneously with the first byte of the next I e if a packet ends in mid word and the next packet arrives directly after the word will still be accessed at least twice Four consecutive bytes of the same packet will if word aligned be written in a single word
170. f the FIFO is empty To determine when the FIFO is not empty the Empty Flag is re synchronized with Clk The external interface provides a Full Flag input signal which is used for flow control during the writ ing of data to the external FIFO not writing any data while the external FIFO is full Note that the Full Flag is sampled at the end of the write access to determine if the FIFO is full To determine when the FIFO is not full the Full Flag is re synchronized with Clk The external interface provides a Half Full Flag input signal which is used as status information only The data input and output signals are possible to use as general purpose input output channels This need is only realized when the data signals are not used by the FIFO interface Each general purpose input output channel is individually programmed as input or output The default reset configuration for each general purpose input output channel is as input The default reset value each general purpose input output channel is logical zero Note that protection toward spurious pulse commands during power up shall be mitigated as far as possible by means of I O cell selection from the target technol ogy Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 5 3 Waveforms The following figures show read and write accesses to the FIFO with 0 and 4 wait states r
171. f the logical address of the destination is unknown then the default logical address of 254 may be used The destination may choose to accept or reject packets with a logical address of 254 The SPW2 requires a perfect DLA match for accepting a packet but its DLA reset value is 254 Note also that for received RMAP responses and when configured to forced unknown protocol interpretation the SPW2 does not check the DLA Protocol ID byte identifies the particular protocol being used for communication For the Remote Memory Access protocol RMAP the protocol identifier has the value 1 0116 For Virtual Channel Transfer Protocol VCTP the default protocol identifier is 240 Command amp Type byte determines the type of the packet i e a command a response or an acknowledgement This byte also includes two bits that determine the length in words of the Source Path Address field For example if these bits are set to the value two then the Source Path Address will consist of eight bytes If they are set to zero then there is no Source Path Address field at all Destination Key provides a one byte key which must be matched by the destination application in order for the RMAP command to be accepted Source Path Address bytes provide the destination path address for the response or acknowledgement of a command The source path address is not needed if logical addressing is being used The Source Path Address if used is normally set to the address fr
172. fected When the fetch buffer is freed after a successful transmission a new fetch will be initiated and if this fetch results in an AHB error response occurring on the AMBA AHB bus this will be handled as for the case above If no AHB error occurs prefetch will be allowed again 9 5 7 Enable and disable When an enabled transmit channel is disabled CanTxCTRL ENABLE 0b any ongoing CAN mes sage transfer request will not be aborted until a CAN bus arbitration is lost or the message has been sent successfully If the message is sent successfully the read pointer CanTxRD READ is automati cally incremented Any associated interrupts will be generated The progress of the any ongoing access can be observed via the CanTxCTRL ONGOING bit The CanTxCTRL ONGOING must be Ob before the channel can be re configured safely i e changing address size or read write pointers It is also possible to wait for the Tx and TxLoss interrupts described hereafter The channel can be re enabled again without the need to reconfigure the address size and pointers Priority inversion is handled by disabling the transmitting channel ie setting CanTxC TRL ENABLE 0 b as described above and observing the progress i e reading via the CanTxC TRL ONGOING bit as described above When the transmit channel is disabled it can be re configured and a higher priority message can be transmitted Note that the single shot mode does not require the channel to be disabled
173. fence Technology 5 7 3 Transmit Channel Control Register FifoTxCTRL R W TABLE 19 Transmit Channel Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Ena ble 31 1 RESERVED No affect when written to Undefined when read 0 ENABLE Enable channel All bits are cleared to 0 at reset Note that in the case of an AHB bus error during an access while fetching transmit data and the Fifo Conf ABORT bit is 1b then the ENABLE bit will be reset automatically At the time the ENABLE is cleared to Ob any ongoing data writes to the FIFO are not aborted 5 7 4 Transmit Channel Status Register FifoTxSTAT R TABLE 20 Transmit Channel Status Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TxO Txlrq TxE TxEr FF HF nGo mpty ror ing 31 7 RESERVED No affect when written to Undefined when read 6 TxOnGoing Access ongoing 5 RESERVED No affect when written to Undefined when read 4 TxIrq Successful transmission of block of data 3 TxEmpty Transmission buffer has been emptied 2 TxError AMB AHB access error during transmission 1 FF FIFO Full Flag 0 HF FIFO Half Full Flag All bits are cleared to 0 at reset The following sticky status bits are cleared when the register has been read e TxIrg TxEmpty and TxError 5 7 5 Transmit Channel Address Re
174. ffer on wrap around i e setting WRITE READ The field is implemented as relative to the buffer base address scaled with the SIZE field Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX i RUAG GAISLER Aerospace Defence Technology 9 10 10 Transmit Channel Read Register CanTxRD R W TABLE 67 Transmit Channel Read Register 31 20 19 4 3 0 READ 31 20 Reserved No effect when written to Undefined when read 19 4 READ Pointer to last read message 1 3 0 Reserved No effect when written to Undefined when read All bits are cleared to 0 at reset The READ field is written to automatically when a transfer has been completed successfully indicat ing the position 1 of the last message transmitted Note that the READ field can be use to read out the progress of a transfer Note that the READ field can be written to in order to set up the starting point of a transfer This should only be done while the transmit channel is not enabled Note that the READ field can be automatically incremented even if the transmit channel has been dis abled since the last requested transfer is not aborted until CAN bus arbitration is lost When the Transmit Channel Read Pointer catches up with the Transmit Channel Write Register an interrupt is generated TxEmpty Note that this indicates that all messages in the buffer have been transmitted The field is impleme
175. figure 24 The least significant bit of the data is sent first Data frame no parity Start DO D1 D2 D3 D4 D5 D6 D7 Stop Data frame with parity Start Do D1 D2 D3 D4 D5 D6 D N Parity Stop Figure 24 UART data frames Following the transmission of the stop bit if a new character is not available in the transmitter holding register the transmitter serial data output remains high and the transmitter shift register empty bit TSRE will be set in the UART control register Transmission resumes and the TSRE is cleared when a new character is loaded in the transmitter holding register If the transmitter is disabled it will continue operating until the character currently being transmitted is completely sent out The transmitter holding register cannot be loaded when the transmitter is disabled If flow control is enabled the CTSN input must be low in order for the character to be transmitted If it is deasserted in the middle of a transmission the character in the shift register is transmitted and the transmitter serial output then remains inactive until CTSN is asserted again If the CTSN is connected to a receivers RTSN overrun can effectively be prevented Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 3 3 5 2 Re
176. for test and debug purposes only Field Description DMA Offset Byte address pointer relative to DMA Base Address The DMA access address is DMA Base Address DMA Offset Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG 177 GAISLER Aerospace Defence Technology SPW RxVC Status Register SPW_RxSR R 31 9 8 7 0 Ch Ch PktCnt Trig Act 0 0 0 MSB LSB Function This register is used for monitoring the activity of the virtual receive channel Timing The PktCnt field is reset to zero when the SPW Rx VC DMA BlockSize Register register is written Constraints Field Value Description PktCnt Number of packets received on RxVC The PktCnt field is incremented if the value is below the value in the SPW RxVC Packet Count Register when an EOP control character is received the packet reception was correctly finalised and the last data has been written to memory If an error is encountered the packet counter will remain unchanged and indicate the number of packets correctly received excluding the failing packet o ee RxVC is inactive nee is active This indicates that a SpaceWire packet is being received on pi channel See 10 6 11 2 0 Rx VC is not triggered RxVC is triggered SPW DMA Block Size Register written Note that the channel will not be tri
177. foremen tioned write address pointer indicates what bytes are valid An interrupt is generated when the circular receive buffer is full If more FIFO data are available they will not be moved to the circular receive buffer The status of the external FIFO is observed via the AMBA APB slave interface indicating Empty Flag and Half Full Flag 5 1 4 General purpose input output Data input and output signals unused by the FIFO interface can be used as general purpose input out put providing 0 8 or 16 individually programmable channels Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 5 2 5 1 5 Interfaces The core provides the following external and internal interfaces FIFO interface e AMBA AHB master interface with sideband signals as per GLRIB including cachability information e interrupt bus configuration information diagnostic information e AMBA APB slave interface with sideband signals as per GLRIB including e interrupt bus configuration information diagnostic information The interface is intended to be used with the following FIFO devices from ATMEL Name Type M67204H 4K x 9 FIFO ESA SCC 9301 049 SMD 5962 89568 M67206H 16K x 9 FIFO ESA SCC 9301 048 SMD 5962 93177 M672061H 16K x 9 FIFO ESA SCC 9301 048 SMD 5962 93177 Interface The external interface supports one or m
178. g store cycles when WB is set TCB is also loaded with the memory checkbits during load cycles when RB is set Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 3 4 13 Write protection Write protection is provided to protect the RAM area against accidental over writing It is imple mented with two methods the address mask method as implemented in the original LEON2 model and an extended version using start end addressing 3 4 13 1 Address mask write protection The address mask write protection is implemented with two block protect units capable of dis abling or enabling write access to a binary aligned memory block in the range of 32 Kbyte 1 Gbyte Each block protect unit is controlled through a control register figure 44 The units operate as follows on each write access to RAM address bits 29 15 are xored with the tag field in the control register and anded with the mask field A write protection hit is generated if the result is zero and the corresponding unit is enabled in block protection mode BP 1 or if the result is not zero and the unit is enabled in segment mode BP 0 31 30 29 15 14 0 EN BP TAG 14 0 MASK 14 0 Figure 43 Write protection register 1 amp 2 14 0 Address mask MASK this field contains the address mask 29 15 Address tag TAG this field is compared a
179. g to occur Note that a disconnection of the Space Wire Link does not trigger the SPW First Failing Packet Register Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX m RUAG GAISLER Aerospace Defence Technology 10 6 9 SpaceWire CODEC The SpaceWire SPW2 Module is based on the University of Dundee SpaceWire CODEC The CODEC implements the SpaceWire link protocol The SpaceWire CODEC is responsible for making a connection with the SpaceWire interface at the other end of a link and managing the flow of data across the link The interface transmits and receives SpaceWire characters which can be link characters L Chars or normal characters N Chars L Chars are characters that are used to manage the flow of data across a link NULL and FCT N Chars are the characters that are used to pass information across the link data characters EOP EEP and time codes The following subsections define the functional blocks that constitute the SpaceWire interface The SpaceWire CODEC is completely encapsulated by the SpaceWire Module and all communication with the SpaceWire CODEC goes through registers and data structures defined for the SpaceWire Module Note that the TxFIFO and the RxFIFO are located outside the SpaceWire CODEC as shown in 10 4 4 10 6 9 1 Initialisation State Machine The SpaceWire CODEC state machine is responsible for initiating a connection on the
180. gainst address 29 15 30 Block protect BP if set selects block protect mode 31 Enable EN if set enables the write protect unit 3 4 13 2 Start end address write protection The start end address write protect scheme contains two identical units that compare the AHB write address against a start and an end address If operated in block protect mode BP 1 and the AHB write address is equal or higher than the start address and lower or equal to the end address a write protect hit is generated If operated in segment mode BP 0 a write protect hit is generated when the write address is lower than the START address or higher than the END address 31 29 1 0 00 START 29 2 BP 0 00 END 29 2 US SU 00 START2 29 2 BP 0 00 END 29 2 US SU Figure 44 Start end address Write protection registers 31 30 Reserved No effect when written to Undefined when read START 29 2 Contains the first address in the protected block END 29 2 Contains the last address in the protected block BP Block protect If set selects block protect mode US User mode If set write protection is enabled for user mode accesses SU Supervisor mode If set write protection is enabled for supervisor mode access The start address is calculated as 0x40000000 START 4 The end address is calculated as 0x40000000 END 4 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012
181. ggered in the case all FlushAbort interrupt bits have not been cleared SPW RxVC Current Packet Status Register SPW_RxCPSR R 31 24 23 0 CurPktStart 0 MSB LSB Function This register is used to indicate the start byte address of the packet currently being received relative to the DMA base address The register contents can be used for setting up anew DMA block transfer after e g a link disconnect error I e if the truncated packet is going to be resent after reconnection then the SPW RxVC DMA Base Address Register can be incremented with the value in SPW RxVC Current Packet Status Register in order to overwrite the faulty packet Timing The CurPktStart field is reset to zero when the SPW Rx VC DMA Block Size Register is written Constraints Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX n RUAG GAISLER Aerospace Defence Technology Field Value Description CurPktStart Any The current packet s start offset The CurPktStart field is set to SPW RxVC DMA Offset Register when an EOP control character is received the packet reception is correctly finalised and the last data has been written to memory I e if an error is encountered the current packet start address remains unchanged and indicates the failing packet SPW RxVC Interrupt Status Register SPW_RxISR SPW RxVC Interrup
182. gher granularity than the 1kbyte address boundary limited by the base address CanRxADDR ADDR field While the channel is disabled the write pointer CanRxWR WRITE can be changed to an arbitrary value pointing to the first message to be received and the read pointer CanRxRD READ can be changed to an arbitrary value When the channel is enabled the reception will start from the write pointer and continue to the read pointer 9 6 6 AMBA AHB error An AHB error response occurring on the AMBA AHB bus while a CAN message is being stored will result in an RxAHBErr interrupt If the CanCONF ABORT bit is set to Ob the channel causing the AHB error will skip the received message not storing it to memory The write pointer will be incremented If the CanCONF ABORT bit is set to 1b the channel causing the AHB error will be disabled CanRx CTRL ENABLE is cleared automatically to 0b The write pointer can be used to determine which message caused the AHB error Note that it could be any of the four word accesses required to writ a message that caused the AHB error If the CanCONF ABORT bit is set to 1b all accesses to the AMBA AHB bus will be disabled after an AMBA AHB error occurs as indicated by the CanSTAT AHBErr bit being 1b The accesses will be disabled until the CanSTAT register is read and automatically clearing bit CanSTAT AHBErr 9 6 7 Enable and disable When an enabled receive channel is disabled CanRxCTRL ENABLE 0b any ong
183. gister 0x800000C4 DSU UART status register 0x80000018 Power down register 0x800000C8 DSU UART control register 0x8000001C Write protection register 1 0x800000CC DSU UART scaler register 0x80000020 Write protection register 2 0x80000024 LEON configuration register 0x800000D0 Write protect start address 1 0x80000040 Timer 1 counter register 0x800000D4 Write protect end address 1 RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology TABLE 6 On chip registers Address Register Address 0x80000044 Timer 1 reload register 0x800000D8 Write protect start address 2 0x80000048 Timer 1 control register 0x800000DC Write protect end address 2 0x8000004C Watchdog register 0x80000050 Timer 2 counter register 0x80000054 Timer 2 reload register 0x80000058 Timer 2 control register 0x80000060 Prescaler counter register 0x80000064 Prescaler reload register 0x80000070 UART 1 data register 0x80000074 UART status register 0x80000078 UART 1 control register 0x8000007C UART 1 scaler register 0x80000080 UART 2 data register 0x80000084 UART 2 status register 0x80000088 UART 2 control register 0x8000008C UART 2 scaler register 0x80000090 Interrupt mask and priority register 0x80000094 Interrupt pending register 0x80000098 Interrupt force register 0x8000009C Interrupt clear register 0x800000A0 T O port input output
184. gister FifoTxA DDR R W TABLE 21 Transmit Channel Address Register 31 10 9 0 ADDR 31 10 ADDR Base address for circular buffer 9 0 RESERVED No affect when written to Undefined when read All bits are cleared to 0 at reset Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX j RUAG GAISLER Aerospace Defence Technology 5 7 6 Transmit Channel Size Register FifoTxSIZE R W TABLE 22 Transmit Channel Size Register 31 17 16 6 5 0 SIZE 31 17 RESERVED No affect when written to Undefined when read 16 6 SIZE Size of circular buffer in number of 64 byte blocks 5 0 RESERVED No affect when written to Undefined when read All bits are cleared to 0 at reset Valid SIZE values are 0 and between 1 and 1024 Note that the resulting behavior of invalid SIZE val ues is undefined Note that only SIZE 64 4 bytes can be stored simultaneously in the buffer This is to simplify wrap around condition checking 5 7 7 Transmit Channel Write Register FifoTxWR R W TABLE 23 Transmit Channel Write Register 31 16 15 0 WRITE 31 16 RESERVED No affect when written to Undefined when read 15 0 WRITE Pointer to last written byte 1 All bits are cleared to 0 at reset The WRITE field is written to in order to initiate a transfer indicating the position 1 of the last byte to transmit Note that it is not possible to fill the b
185. gister are used for observing setting and clearing the interrupts belonging to the group When an interrupt is issued it is propagated to the top layer set of register for further propagation outside the module The interrupt registers give complete freedom to the software by providing means to mask interrupts clear interrupts force interrupts and read interrupt status All of the interrupt registers are listed in Table 10 1 along with the effect of reading and writing them Register Acronym Read Write SPW Pending Interrupt Masked Status SPW_PIMSR Reads PISR Register and IMR SPW Pending Interrupt Status Register SPW _PISR Reads SPW Link Interrupt Status Register SPW_LISR corresponding SPW RxVC Interrupt Status Register SPW_RxISR ISR SPW TxVC Interrupt Status Register SPW_TxISR SPW Interrupt Mask Register SPW Link Interrupt Status Set Register SPW_LISSR Sets selected bits in SPW RxVC Interrupt Status Set Register SPW_RxISSR corresponding ISR SPW TxVC Interrupt Status Set Register SPW_TxISSR SPW Link Interrupt Clear Register SPW_LISCR Clears selected bits SPW RxVC Interrupt Status Clear Register SPW_RxISCR in corresponding SPW TxVC Interrupt Status Clear Register SPW_TxISCR ISR Table 10 1 Interrupt Register Summary When an interrupt occurs the corresponding bit in the Interrupt Status Register is set The norma
186. guration fields DLA and RMAPEn Thus the RMAP hardware command execution is not visible as seen from the application software SPW RxVC Config Register 0 SPW_RxCnf 0 R W 31 15 8 4 3 2 1 0 DLA Force TrPtcl RMAP Word Rx Unk SW En Align En FEh 0 0 1 0 0 MSB LSB Function This register configures some common resources used by all reception channels and the reception of packets with other Protocol IDs than configured for the SpaceWire Virtual Channel Transfer Protocol in the SPW VC Transfer Protocol ID Register Timing Constraints The word alignment function assumes that the Rx VC DMA Base Address is programmed with a word aligned start address Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX r RUAG GAISLER Aerospace Defence Technology Field Value Description The virtual receive channel is disabled No packets are received on this virtual receive channel and no data are stored to memory Note that this bit is only used during the identification process described in 5 5 3 2 I e when disabled any ongoing packet will be completed Except for RMAP commands supported in hardware all packets are rejected If the RMAPEn bit is not set then RMAP commands supported in hardware are also rejected RMAP commands intended for further software processing are thus discarded All RMAP respon
187. h external trigger signal UART Serial Links e Two Universal Asynchronous Receiver and Transmitters UART supporting optional parity internal or external clock source hardware handshake and programmable baud rate 16 bit General Purpose Input Output e Programmable input output channels shared with the interrupt controller inputs and the UART serial links Memory Interface e Supports two PROM banks four SRAM banks and one memory mapped I O Features 23 byte address bits 32 data bits and 8 check bits Unused data bits can be used as general purpose input output FIFO Interface e Supports one input and one output external FIFO device with 8 or 16 bit wide data Unused data bits can be used as general purpose input output ADC DAC Interface e Supports one ADC and one DAC device with 8 or 16 bit wide data and 8 bit address Unused address and data bits can be used as general purpose input output 32 bit Timers e Supports external clock source and external triggers 24 bit General Purpose Input Output e Dedicated programmable input output channels with input interrupts CAN Interface e Supports nominal and redundant transmit and receive pair with non simultaneously operation SpaceWire Link Interface e Supports nominal and redundant SpaceWire links with simultaneously operation JTAG Interface e Supports standard TAP signal interface Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December
188. he CanTxSIZE SIZE field specifying the number of CAN mes sages 4 that fit in the buffer E g CanTxSIZE SIZE 2 means 8 CAN messages fit in the buffer Note however that it is not possible to fill the buffer completely leaving at least one message position in the buffer empty This is to simplify wrap around condition checking E g CanTxSIZE SIZE 2 means that 7 CAN messages fit in the buffer at any given time 9 5 2 Write and read pointers The write pointer CanTxWR WRITE indicates the position 1 of the last CAN message written to the buffer The write pointer operates on number of CAN messages not on absolute or relative addresses The read pointer CanTxRD READ indicates the position 1 of the last CAN message read from the buffer The read pointer operates on number of CAN messages not on absolute or relative addresses The difference between the write and the read pointers is the number of CAN messages available in the buffer for transmission The difference is calculated using the buffer size specified by the CanTx SIZE SIZE field taking wrap around effects of the circular buffer into account Examples e There are 2 CAN messages available for transmit when CanTxSIZE SIZE 2 CanTxWR WRITE 2 and CanTxRD READ 0 e There are 2 CAN messages available for transmit when CanTxSIZE SIZE 2 CanTxWR WRITE 0 and CanTxRD READ 6 e There are 2 CAN messages available for transmit when CanTxSIZE SIZE 2 CanTxWR WRITE 1 and CanTxRD R
189. he send list Pointer SPW TxVC SendList Size Register SPW_TxSLSR R WT 31 8 7 0 z SendList Size 0 MSB LSB Function The SendList Size field indicates the size of the send list counted in number of send list entries It can be used for monitoring the progress by indicating the remaining number of entries in the send list A write access to the SPW TxVC Sendlist Size register triggers the TxVC send list fetch operation The TxVC channel will participate in the arbitration and eventually start the transmission on the SpaceWire link The size is decremented by one after the send list entry has been successfully transmitted Timing Constraints This register must not be written to during transmission For TxVC 0 writes to this register have no effect Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX m RUAG GAISLER Aerospace Defence Technology Field Description Send List Number of remaining send list entries Size SPW TxVC Status Register SPW_TxSR R 31 2 l 0 Ch Ch Trig Act 0 0 MSB LSB Function This register is used for monitoring the activity of the virtual transmit channel Timing Constraints Field Value Description a TxVC is inactive wo TxVC is active i e is currently transmitting o TC is not started TxVC is started SPW TxVC Send List Size wri
190. header data to 4 bytes and the SPW2 transmitter limits the maximum header size to 255 bytes e The end of packet is either an EOP indicating a normal termination of a packet or an EEP which might appear before the nominal EOP position indicating a packet in which an error has occurred Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER 10 5 9 4 120 RUAG Aerospace Defence Technology SpaceWire Transfer Protocol RMAP packet structure The supported packet structures for the RMAP SpaceWire transfer protocol using Protocol ID equal to 0116 are shown in the paragraphs below Destination Protocol ID Remaining Optional RMAP EOP Logical RMAP Data and Data Address Header CRC Header Data 1 byte 1 byte Command or 0 16 MiB 1 Response specific size 6 26 bytes Figure 10 5 RMAP Transfer Protocol packet structure using logical addressing Destination Destination Protocol ID Remaining Optional RMAP EOP Path Address Logical RMAP Data and Data Address Header CRC Header Data 1 12 bytes 1 byte 1 byte Command or 0 16 MiB 1 Response specific size 6 26 bytes Figure 10 6 RMAP Transfer Protocol packet structure using path addressing Note that a zero byte data cargo for read or write commands is allowed 10 5 9 4 1 The write command RMAP Write Command format
191. hip select Ob active low 1b active high 6 RDYMODE Mode of ADC ready Ob unused i e open loop 1b used with time out 5 RDYPOL Polarity of ADC ready Ob falling edge 1b rising edge 4 TRIGPOL Polarity of ADC triggers Ob falling edge 1b rising edge 3 2 TRIGMODE ADC trigger source 00b none 01b ADTrig 10b 32 bit Timer 1 11b 32 bit Timer 2 1 0 ADCDW ADC data width 00b none Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology See ee Oe 01b 8 bitADData 7 0 10b 16 bitADData 15 0 11b none spare The ADCDW field defines what part of ADData 15 0 is read by the ADC The DACDW field defines what part of ADData 15 0 is written by the DAC Parts of the data input output signals used neither by ADC nor by DAC are available for the general purpose input output functionality Note that an ADC conversion can be initiated by means of a write access via the AMBA APB slave interface thus not requiring an explicit ADC trigger source setting The ADCONF ADCWS field defines the number of system clock periods ranging from 1 to 32 for the following timing relationships between the ADC control signals e ADRC stable before ADCS period e ADCS asserted period when pulsed e ADTrig 2 0 event until ADCS asserted period e Time out period for ADRdy 2048 1 ADCONF ADCWS e Open loop conversion timing
192. his means that writing the register can force set an interrupt bit but never clear it Reading interrupt status Reading the Interrupt Status Register yields the data without clearing the contents Reading interrupt status of unmasked bits Reading the SPW Pending Interrupt Masked Status Register yields the contents of the SPW Pending Interrupt Status Register masked with the contents of the SPW Interrupt Mask Register without clearing the contents 10 6 16 Interrupt bus In the SpaceWire RTC all interrupts from the peripheral units such as CAN and SPW are routed through a 32 bit wide interrupt bus This bus is an input and an output to all cores in the design The bus is also connected to the secondary interrupt controller in the LEON2FT core The interrupt bus is used for example in the Timer core which takes the full bus and combines it with a local mask register to form a latch signal This latch signal is used to latch the timer values on the occurrence of the filtered interrupt Thus any interrupt in the system excluding specific LEON2FT peripheral interrupts only connected to the primary interrupt controller can be used to latch the timers Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 RUAG Aerospace Defence Technology EROFLEX 16 GAISLER 10 7 Register definition summary This chapter contains all commands and registers available for the SpaceWi
193. igured to be separate for each timer timer 1 reload prescaler reload timer 2 reload l y prescaler value timer 1 value gt pirq 4 timer 2 value gt pirq 1 A tick 5 1 Figure 66 General Purpose Timer Unit block diagram Operation The prescaler is clocked by the system clock and decremented on each clock cycle When the prescaler underflows it is reloaded from the prescaler reload register and a timer tick is generated Timers share the decrementer to save area The operation of each timers is controlled through its control register A timer is enabled by setting the enable bit in the control register The timer value is then decremented on each prescaler tick When a timer underflows it will automatically be reloaded with the value of the corresponding timer reload register if the restart bit in the control register is set otherwise it will stop at 1 and reset the enable bit Since configured to signal interrupt for each timer the timer unit will signal an interrupt on appropriate line when a timer underflows if the interrupt enable bit for the current timer is set The interrupt pending bit in the control register of the underflown timer will be set and remain set until cleared by writing 0 To minimize complexity timers share the same decrementer This means that the minimum allowed prescaler division factor is 3 rel
194. ilable in the circular buffer a prefetch of this CAN message from the circular buffer to a local prefetch buffer in the CAN controller will be performed The CAN controller can thus hold two CAN messages for transmis sion one in the fetch buffer which is fed to the HurriCANe codec and one in the prefetch buffer After a message has been successfully transmitted the prefetch buffer contents are moved to the fetch buffer provided that there is message ready The read pointer CanTxRD READ is automatically incremented after a successful transmission i e after the fetch buffer contents have been transmitted taking wrap around effects of the circular buffer into account If there is at least an additional CAN message available in the circular buffer a new prefetch will be performed If the write and read pointers are equal no more prefetches and fetches will be performed and trans mission will stop If the single shot mode is enabled for the transmit channel CanTxCTRL SINGLE 1 any message for which the arbitration is lost or failed for some other reason will lead to the disabling of the channel CanTxCTRL ENABLE 0 and the message will not be put up for re arbitration Interrupts are provided to aid the user during transmission as described in detail later in this section The main interrupts are the Tx TxEmpty and TxIrq which are issued on the successful transmission of a message when all messages have been transmitted successfully
195. ile FPU disabled cp_disabled 0x24 6 CP instruction while Co processor disabled Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 GAISLER RUAG EROFLEX Aerospace Defence Technology TABLE 3 Trap allocation and priority Trap TT Pri Description watchpoint_detected 0x0B 7 Hardware breakpoint match window_overflow 0x05 8 SAVE into invalid window window_underflow 0x06 8 RESTORE into invalid window register_hadrware_error 0x20 9 register file EDAC error LEON FT only mem_address_not_aligne 0x07 10 Memory access to un aligned address d fp_exception 0x08 11 FPU exception cp_exception 0x28 11 Co processor exception data_access_exception 0x09 13 Access error during load or store instruction tag_overflow Ox0A 14 Tagged arithmetic overflow divide_exception Ox2A 15 Divide by zero interrupt_level_1 0x11 31 Asynchronous interrupt 1 interrupt_level_2 0x12 30 Asynchronous interrupt 2 interrupt_level_3 0x13 29 Asynchronous interrupt 3 interrupt_level_4 0x14 28 Asynchronous interrupt 4 interrupt_level_5 0x15 27 Asynchronous interrupt 5 interrupt_level_6 0x16 26 Asynchronous interrupt 6 interrupt_level_7 0x17 25 Asynchronous interrupt 7 interrupt_level_8 0x18 24 Asynchronous interrupt 8 interrupt_level_9 0x19 23 Asynchronous interrupt 9 interrupt_level_10 OxlA 22 Asynchronous interrupt 10 interrupt_level_11 Ox1B 21
196. imer 2 reload register 0x80000058 Timer 2 control register 0x80000060 Prescaler counter register 0x80000064 Precaler reload register 0x80000070 Uart 1 data register 0x80000074 Uart 1 status register 0x80000078 Uart 1 control register 0x8000007C Uart 1 scaler register 0x80000080 Uart 2 data register 0x80000084 Uart 2 status register 0x80000088 Uart 2 control register 0x8000008C Uart 2 scaler register 0x80000090 Interrupt mask and priority register 0x80000094 Interrupt pending register 0x80000098 Interrupt force register 0x8000009C Interrupt clear register Ox800000A0_ T O port input output register 0x800000A4 T O port direction register 0x800000A8 T O port interrupt config register 1 Ox800000AC I O port interrupt config register 2 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX s RUAG GAISLER Aerospace Defence Technology 13 3 2 On Chip Memory TABLE 86 On Chip Memory registers Register Address Configuration Register 0x80010000 13 3 3 FIFO Interface TABLE 87 FIFO Interface registers Register Address Configuration Register 0x80050000 Control Register 0x80050008 Transmit Channel Control Register 0x80050020 Transmit Channel Status Register 0x80050024 Transmit Channel Address Register 0x80050028 Transmit Channel Size Register 0x8005002C Transmit
197. immediately The send list pointer and the send list size remain unchanged in the case an error occurs while reading a send list entry FlushAbort An SPW CODEC Configuration Register TxFifoFlush was commanded while the channel was active or triggered The channel is untriggered and the ongoing transmission is stopped 10 8 Vendor and device id The module has vendor id 0x04 and device id 0x12 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX h RUAG GAISLER Aerospace Defence Technology 11 AMBA AHB CONTROLLER 11 1 Overview The AHB controller is a combined AHB arbiter bus multiplexer and slave decoder The controller sup ports up to 16 AHB masters and 16 AHB slaves MASTER MASTER ry x AHBCTRL vv ARBITER ZA DECODER x v Y SLAVE SLAVE Figure 76 AHB Controller block diagram 11 2 Operation 11 2 1 Arbitration The AHB controller supports a round robin arbitration algorithm In round robin mode priority is rotated one step after each AHB transfer If no master requests the bus the last owner will be granted bus parking During incremental bursts the AHB master should keep the bus request asserted until the last access or it might loose bus ownership 11 2 2 Decoding Access to unused addresses will cause an AHB error response 11 2 3 Plug amp
198. includes two additional 32 bit timers being cascadable and with optional external clock input 24 bit General Purpose Input Output e The SpaceWire RTC ASIC includes 24 additional general purpose input output channels supporting input output and pulse generation CAN Interface e The SpaceWire RTC ASIC includes the ESA HurriCANe CAN controller The interface features one DMA channel in either direction and is compatible with the CANopen application layer protocol SpaceWire Link Interface e The SpaceWire RTC ASIC includes two University of Dundee SpaceWire links The interface implements DMA channels and Remote Memory Access Protocol RMAP JTAG Interface e The SpaceWire RTC ASIC includes a JTAG interface with TAP controller for boundary scan testing Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER 2 2 Aerospace Defence Technology General interfaces The SpaceWire RTC ASIC provides the following external and internal interfaces Debug Serial Link UART e A simple communication protocol is provided to transmit access parameters and data on the internal AMBA bus A command comprises a control byte followed by and a 32 bit address followed by optional write data Interrupt Controller e External interrupts can be selected from the 16 bit General Purpose Input Output or the data bus of the Memory Interface 32 bit Timers e Watchdog wit
199. ines the data with of the ram area 00 8 1X 32 6 Read modify write Enable read modify write cycles on sub word writes to 32 bit areas with common write strobe no byte write strobe 7 Bus ready enable If set will enable IoBrdyN for ram area Unused 12 9 Ram bank size Defines the size of each ram bank 0000 8 Kbyte 0001 16 Kbyte 1111 256 Mbyte 8 31 13 Reserved No effect when written to Undefined when read 3 4 12 Memory configuration register 3 MCFG3 MCFG3 contains the control and monitor the memory EDAC It also contains the configuration of the register file EDAC 31 30 27 11 10 9 8 7 0 RFC ME WB RB RE PE TCB 7 0 Figure 42 Memory configuration register 3 31 30 Regfile check bits RFC Indicates how many checkbits are used for the register file 00 none 01 1 10 2 11 7 EDAC Fixed 29 28 Reserved No effect when written to Undefined when read 27 Memory EDAC ME Indicates if a memory EDAC is present 26 12 Unused No effect when written to Undefined when read 11 WB EDAC diagnostic write bypass 10 RB EDAC diagnostic read bypass 9 RAM EDAC enable RE Enable EDAC checking of the RAM area 8 PROM EDAC enable PE Enable EDAC checking of the PROM area At reset this bit is initialised with the value of LeonPio 2 7 0 TCB Test checkbits This field replaces the normal checkbits durin
200. ing before the time code has been transmitted will be ignored This also applies if the subsequent event is of the same type as the preceding one 10 6 7 4 1 Alternative Time code transmission through software control The time code is transmitted as soon as a write access is performed to the SPW SW Transmit Time Code Register SPW _SWTTCR The SPW _SWTTCR TxTimeCtrl field defines the value of the corresponding time code control flags bits T6 and T7 to be transmitted 10 6 7 4 2 Alternative Time code transmission through hardware control The time code is transmitted when an interrupt occurs on the interrupt bus and the corresponding interrupt is not masked by the SPW Transmit Time Code Mask Register SPW_TTCMR The TxTimeCtrl field of the SPW Transmit Time Code Register SPW_TTCR defines the value of the time code control flags bits T6 and T7 to be transmitted The mask register SPW Transmit Time Code Mask Register SPW_TTCMR can be written and read via the APB bus A time code is sent only when an edge is detected on the filtered interrupt Any interrupt in the system can be used for initiating time code transmission Note The SPW2 core TxTimeTick input signal is generated from the interrupt bus The time code information to be transmitted can be written and read via the APB bus through the SPW Transmit Time Code Register SPW_TTCR Note The SPW_TTCR register has been augmented to allow the SPW_TTCR TxTimeCtrl field i e bits
201. interface An interrupt is generated when a conversion is completed A 3 0 AD667 AMBA APB Interface STS Figure 63 Block diagram of the GRADCDAC environment 6 1 1 Function The core implements the following functions ADC interface conversion ready feed back or timed open loop DAC interface conversion timed open loop e General purpose input output Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 j EROFLEX RUAG GAISLER Aerospace Defence Technology unused data bus and unused address bus Status and monitoring on going conversion completed conversion e timed out conversion Note that it is not possible to perform ADC and DAC conversions simultaneously On only one con version can be performed at a time 6 1 2 Interfaces The core provides the following external and internal interfaces e Combined ADC DAC interface programmable timing programmable signal polarity programmable conversion modes AMBA APB slave interface The ADC interface is intended for amongst others the following devices Name Width Type AD574 12 bit R C CE CS RDY tri state AD674 12 bit R C CE CS RDY tri state AD774 12 bit R C CE CS RDY tri state AD670 8 bit R W CE CS RDY tri state AD571 10 bit Blank Convert RDY tri state AD1671 12 bit Encode RDY non tri state LTC1414 14 bit Convert
202. is implemented as a common parameter At the end of the Read Result phase an interrupt is generated indicating that data is ready for readout via the AMBA APB slave interface The status of an on going conversion is possible to read out via the AMBA APB slave interface The result of a conversion is read out via the AMBA APB slave inter face Note that this is independent of what trigger started the conversion An ADC conversion is non interruptible It is possible to perform at least 1000 conversions per sec ond Start conversion Read result WS WS WS WS SysClk ADCs ADRc ADTrig Ff ADRdy f x ADData K gt ADAddr X X Settings RCPOL 0 Sample data CSPOL 0 RDYPOL 1 TRIGPOL 1 RDYMODE 1 CSMODE 00 ADCWS 0 Figure 64 Analogue to digital conversion waveform 0 wait states WS 6 2 3 Digital to analogue conversion The DAC interface supports 8 and 16 bit wide output data The data output signal is driven during the conversion and is placed in high impedance state after the conversion The DAC interface provides an 8 bit address output shared with the ADC interface Note that the address timing is independent of the acquisition timing The DAC interface provides the following control signal Write Strobe Note that the Write Strobe sig nal can also be used as a chip se
203. is used for retrieving and storing FIFO data in memory external to the FIFO interface This memory can be located on chip or external to the chip The FIFO interface supports transmission and reception of blocks of data by use of circular buffers located in memory external to the core Separate transmit and receive buffers are assumed Reception and transmission of data can be ongoing simultaneously After a data transfer has been set up via the AMBA APB interface the DMA controller initiates a burst of read accesses on the AMBA AHB bus to fetch data from memory that are performed by the AHB master The data are then written to the external FIFO When a programmable amount of data has been transmitted the DMA controller issues an interrupt After reception has been set up via the AMBA APB interface data are read from the external FIFO To store data to memory the DMA controller initiates a burst of write accesses on the AMBA AHB bus that are performed by the AHB master When a programmable amount of data has been received the DMA controller issues an interrupt The block diagram shows a possible usage of the FIFO interface D 8 0 RD AMBA FIFO ATMEL lt AHB Interface FULL M6720X EMPTY gt HALF gt lt lt D ATMEL M6720X __ Figure 60 Block diagram of the GRFIFO environment 5 1 1 Function The core implements the following functions e data transmission t
204. is written to automatically when a transfer has been completed successfully indicat ing the position 1 of the last message received Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX e RUAG GAISLER Aerospace Defence Technology Note that the WRITE field can be use to read out the progress of a transfer Note that the WRITE field can be written to in order to set up the starting point of a transfer This should only be done while the receive channel is not enabled 9 10 16 Receive Channel Read Register CanRxRD R W TABLE 73 Receive Channel Read Register 31 20 19 4 3 0 READ 31 20 Reserved No effect when written to Undefined when read 19 4 READ Pointer to last read message 1 3 0 Reserved No effect when written to Undefined when read All bits are cleared to 0 at reset The field is implemented as relative to the buffer base address scaled with the SIZE field The READ field is written to in order to release the receive buffer indicating the position 1 of the last message that has been read out Note that it is not possible to fill the buffer There is always one message position in buffer unused Software is responsible for not over reading the buffer on wrap around i e setting WRITE READ 9 10 17 Receive Channel Interrupt Register CanRxIRQ R W TABLE 74 Receive Channel Interrupt Register 31 20 19 4 3 0 IRQ
205. ister in the secondary interrupt controller This limitation does not exist for the primary interrupt controller Interrupts 31 down to 24 are connected to the inputs of the 24 bit General Purpose Input Output interface The secondary interrupt controller uses edge detection The 24 bit General Purpose Input Output interface must therefore only be programmed for edge detection not for level to ensure that multiple interrupts can be detected RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER 195 14 INTERFACES AND SIGNALS RUAG Aerospace Defence Technology Table 96 SpaceWire RTC signals Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG Signal Type Description Comment LeonErrorN IO LEON Error This active low output is asserted when open drain the processor has entered error state and output is halted This happens when traps are disabled and an synchronous un maskable trap occurs LeonWDN IO LEON watchdog This active low output is asserted when open drain the watchdog times out output LeonDsuEn I DSU enable The active high input enables the DSU unit If de asserted the DSU trace buffer will continue to operate but the processor will not enter debug mode LeonDsuTx O DSU UART transmit This active high output provides the data from the DSU communication link transmitter LeonDsuRx I DSU UART receive This active high
206. itter output Select receive input 0 as active when Ob Select receive input 1 as active when 1b Select transmit output 0 as active when Ob Select transmit output 1 as active when 1b ENABLEI Set value of output 1 enable ENABLEO Set value of output 0 enable ABORT Abort transfer on AHB ERROR All bits are cleared to 0 at reset Note that constraints on PS1 PS2 and RSJ are defined as e PS1 1 gt PS2 e PS2 gt RSJ Note that CAN standard TSEG1 is defined by PS1 1 Note that CAN standard TSEG2 is defined by PS2 Note that the SCALER setting defines the CAN time quantum together with the BPR setting system clock SCALER 1 BPR where SCALER is in range 0 to 255 and the resulting division factor due to BPR is 1 2 4 or 8 Note that the resulting bit rate is system clock SCALER 1 BPR 1 PS1 1 PS2 where PS1 is in the range 1 to 15 and PS2 is in the range 2 to 8 Note that RSJ defines the number of allowed re synchronization jumps according to the CAN stan dard being in the range 1 to 4 Note that the transmit or receive channel active during the AMBA AHB error is disabled if the ABORT bit is set to 1b Note that all accesses to the AMBA AHB bus will be disabled after an AMBA AHB error occurs while the ABORT bit is set to 1b The accesses will be disabled until the CanSTAT register is read Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RU
207. ize field MCFG2 12 9 and can be set in binary steps from 8 kbyte to 32 Mbyte A read access to SRAM consists of two data cycles and between zero and three waitstates On non consecutive accesses a lead out cycle is added after a read cycle to Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology prevent bus contention due to slow turn off time of memories or I O devices Figure 37 shows the basic read cycle waveform zero waitstate datal data2 lead out Moma MemCsN MemOeN Memb Figure 37 Static ram read cycle 0 waitstate For read accesses to MemCsN 3 0 a separate output enable signal MemOeN n is provided for each RAM bank and only asserted when that bank is selected A write access is similar to the read access but takes a minimum of three cycles lead in data lead out MemA MemCsN MemWrN MemD Figure 38 Static ram write cycle Each byte lane has an individual write strobe to allow efficient byte and half word writes If the memory uses a common write strobe for the full 32 bit data the read modify write bit MCFG2 should be set to enable read modify write cycles for sub word writes 3 4 6 Burst cycles To improve the bandwidth of the memory bus accesses to consecutive addresses can be performed in burst mode Burst transfers will be generated when the memory
208. k start up is possible to derive after reset from the SpwClk clock and the clock prescaler controlled by the configuration inputs SpwClkIOMBit and SpwClkMul The reset value of the SPW Clock Division Register corresponds to the link start up bit rate The SpwClkMul configuration input allows for divisions by 1 4 1 3 1 2 1 1 The SpwClkIOMBit configuration input allows for divisions by 1 10 1 8 1 6 1 5 1 4 1 3 1 2 1 1 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX a RUAG GAISLER Aerospace Defence Technology The configuration inputs SpwClk1OMBit and SpwClkMul support the following SpwClk frequency values 10 20 30 40 50 60 80 90 100 120 150 160 180 200 240 300 and 320 MHz Note that 1 4 1 10 1 40 which would give a SpwClk value of 400 MHz is not a legal value since the SPW Clock Division Register can t be programmed to a division rate higher than 32 A variance of 10 of the above values is allowed still meeting the SpaceWire link start up frequency requirement A switch to the nominal transmit data rate is automatically performed when the link start up has been completed After a link disconnection the link start up transmit data rate is automatically used again until the link start up has been completed Note that NULL characters are sent with the nominal transmit data rate after the completion of the link start up The
209. ksum 0l 11 Illegal values Will be handled as 00 by the SPW2 LAA Size e 255 Header size in bytes Eea Z 4 GiB 1 Header start address byte address Address Data Page 0 15 Data Page Address i e address bits A35 A32 enabling 64 Gbyte addressing space Data Type Nominal or RMAP read command puts EOP at the end No data CRC RMAP write command CRC checksum is generated over the data and is put at the end followed by EOP Ilegal values Will be handled as 00 by the SPW2 Data Address 0 4 GiB 1 Data start address byte address Figure 10 13 Send list entry structure Note that the send list elements must be word aligned 10 5 10 Applicable Documents DERATE Derating Requirements applicable to electronic electrical and electro mechanical components for ESA space systems ESA PSS 01 301 Issue 2 ESA_DAR ESA ASIC Design and Assurance Requirements QC 172 RdM Issue 1 June 1992 CCSDS Packet Telemetry Standard PSS 04 106 Issue 1 SPW ECSS E STD 50 12C Space Engineering SpaceWire Links Nodes Routers and Networks RMAPID ECSS E ST 50 50C SpaceWire protocol identification RMAP ECSS E ST 50 51C SpaceWire Remote memory access protocol AMBA AMBA Specification Rev 2 0 SPW2 SpaceWire SPW2 Module Specification Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX P RUAG GAISLER Aerospace Defence Technology P ASIC SPC 00
210. l Circular reception buffer full 9 FIFO RxIrq Successful reception of data block 8 FIFO TxError AHB access error during transmission 7 FIFO TxEmpty Circular transmission buffer empty 6 FIFO TxIrq Successful transmission of data block 5 ADC DAC DAC conversion ready 4 ADC DAC ADC conversion ready 3 32 Bit Timer Timer 2 Timer expired 2 32 Bit Timer Timer 1 Timer expired 1 GPIO PULSE Pulse command completed 0 Unused Note Interrupt 17 15 and 13 are available in primary interrupt controller and should therefore be used restrictively in the secondary interrupt controller The secondary interrupt controller uses edge detection whereas the aforementioned interrupt sources use level The interrupt handling software must thus ensure that the sources for the aforementioned interrupts do not have an additional pending interrupt when clearing the corresponding bit in the pending interrupt register in the secondary interrupt controller This limitation does not exist for the primary interrupt controller Note Interrupts 31 down to 24 are connected to the inputs of the 24 bit General Purpose Input Output interface The secondary interrupt controller uses edge detection The 24 bit General Purpose Input Output interface must therefore only be programmed for edge detection not for level to ensure that multiple interrupts can be detected Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2
211. l Controller RTC device is a bridge between the SpaceWire network backbone and the CAN bus providing a fully integrated system Additional features are provided to carter for autonomy of remote terminals and to relieve the central processing chain of repetitive stan dard acquisitions and management duties The SpaceWire RTC device can be used both in non intelli gent nodes and in nodes with local intelligence The SpaceWire RTC device includes an embedded microprocessor a CAN bus controller ADC DAC interfaces for analogue acquisition conversion standard interfaces and resources UARTs timers gen eral purpose input output Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 1 6 Block diagram SpaceWire Remote Terminal Controller RTC block diagram is shown hereafter SRAM PROM RS232 422 EEPROM FLASH PROM Debug Debug f MEIKO AHB pen Serial Link Support a EONA FT SPARG Vele Floating arbiter OntroTe UART Unit g Point decoder Unit AHB I F AHB I F AHB I F l Cache D Cache AHB I F AMBA AHB GPIO IRQ_ AHB APB RS232 422 bridge a UARTs TIMERs 9 SpaceWire RTC AMBA APB AMBA APB AMBA AHB Tj 24bit General ADC DAC AHB I F AHB I F AHB I F AHB I F 32bit
212. l force a cache miss update the cache if the data was previously cached or allocated a new line if the data was not in the cache and the address refers to a cacheable location TABLE 5 Default cache table Address range Area Cached 0x00000000 0x 1 FFFFFFF PROM Cacheable 0x20000000 Ox3 FFFFFFF VO Non cacheable 0x40000000 0x7FFFFFFF RAM Cacheable 0x80000000 0x9FFFFFFF Internal AHB Non cacheable 0xA0000000 Ax7FFFFFFF On Chip RAM Cacheable 0xB0000000 0xFFFFFFFF Internal AHB Non cacheable Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 3 2 2 Instruction cache 3 2 2 1 Operation The instruction cache is configured as a direct mapped cache The set size is 4 kbyte and divided into cache lines of 32 bytes Each line has a cache tag associated with it consisting of a tag field valid field with one valid bit for each 4 byte sub block On an instruction cache miss to a cachable location the instruction is fetched and the corresponding tag and data line updated If instruction burst fetch is enabled in the cache control register CCR the cache line is filled from main memory starting at the missed address and until the end of the line At the same time the instructions are forwarded to the IU streaming If the IU cannot accept the streamed instructions due to internal dependencies or
213. l sequence to initialise and handle a module interrupt is e Set up the software interrupt handler to accept an interrupt from the module e Read the SPW Pending Interrupt Status Register and clear any spurious interrupts by writing the corresponding Interrupt Status Clear Register e Initialise the SPW Interrupt Mask Register unmasking each bit that should generate the module interrupt e When an interrupt occurs read the SPW Pending Interrupt Status Register in the software interrupt handler to determine the causes of the interrupt e Handle the interrupt taking into account all causes of the interrupt e Clear the handled interrupt using the corresponding Interrupt Status Clear Register Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX a RUAG GAISLER Aerospace Defence Technology Masking interrupts After reset all interrupt bits are masked since the SPW Interrupt Mask Register is zero To enable generation of a module interrupt for an interrupt bit set the corresponding bit in the SPW Interrupt Mask Register Clearing interrupts Selected bits can be cleared by writing ones to the bits that shall be cleared to the corresponding Interrupt Status Clear Register Forcing interrupts When an Interrupt Status Set Register is written the resulting value is the original contents of the corresponding Interrupt Status Register logically OR ed with the write data T
214. lect signal The Write Strobe output signal is programmable in terms of Polarity The Write Strobe signal is asserted during the conversion The duration of the asserted period of the Write Strobe is programmable in terms of system clock periods At the end the conversion an interrupt is generated The status of an on going conversion is possible to read out via the AMBA APB slave interface A DAC conversion is non interruptible Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology Conversion WS WS WS SysClk ADWr ADData K ADAddr x gt Settings WRPOL 0 DACWS 0 Figure 65 Digital to analogue conversion waveform 0 wait states WS 6 2 4 Interrupt Two interrupts are implemented by the ADC DAC interface Name Description ADC ADC conversion ready DAC DAC conversion ready 6 2 5 Vendor and device id The module has vendor id 0x01 Gaisler Research and device id 0x36 6 3 Registers The GRADCDAC is programmed through registers mapped into APB address space TABLE 36 GRADCDAC registers Register Address Configuration Register 0x80040000 Status Register 0x80040004 ADC Data Input Register 0x80040010 DAC Data Output Register 0x80040014 Address In
215. level with interrupt 15 having the highest priority and interrupt 1 the lowest The highest interrupt from level 1 will be forwarded to the IU 1f no unmasked pending interrupt exists on level 1 then the highest unmasked interrupt from level 0 will be forwarded When the IU acknowledges the interrupt the corresponding pending bit will automatically be cleared Interrupt can also be forced by setting a bit in the interrupt force register In this case the IU acknowledgement will clear the force bit rather than the pending bit After reset the interrupt mask register is set to all zeros while the remaining control registers are undefined Note that interrupt 15 cannot be maskable by the integer unit and should be used with care most operating system do safely handle this interrupt 3 3 2 2 Interrupt assignment Table 7 shows the assignment of interrupts TABLE 7 Interrupt assignments Interrupt Source 15 Parallel I O 7 14 SpaceWire 1 13 SpaceWire 0 Parallel I O 6 12 CAN interface Parallel I O 5 11 DSU trace buffer 10 Second interrupt controller Parallel I O 4 9 Timer 2 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology TABLE 7 Interrupt assignments Interrupt Source Timer 1 Parallel I O 3 Parallel I O 2 Parallel I O 1 Parallel I O 0 UART 1
216. mber of SPARC register windows on ln e in 0x90020000 psr cwp 64 32 n mod NWINDOWS 64 0x90020000 psr cwp 64 64 n mod NWINDOWS 64 0x90020000 psr cwp 64 96 n mod NWINDOWS 64 e Jgn fn 0x90020000 NWINDOWS 64 128 FPU present 0x90020000 NWINDOWS 64 Meiko 3 5 2 4 DSU control register The DSU is controlled by the DSU control register 31 20 19 18 17 16 15 14 13 12 11 10 9 8 DCNT 765 4 3 2 10 RE DR LR ss PE EE EB DMDE Bz BX BB BN BS BW BE Ft BT DMTE Figure 49 DSU control register 0 Trace enable TE Enables the trace buffer l Delay counter mode DM In mixed tracing mode setting this bit will cause the delay counter to decrement on AHB traces If reset the delay counter will decrement on instruction traces 2 Break on trace BT if set will generate a DSU break condition on trace freeze 3 Freeze timers FT if set the scaler in the LEON timer unit will be stopped during debug mode to preserve the time for the software application 4 Break on error BE if set will force the processor to debug mode when the processor would have entered error condition trap in trap 5 Break on IU watchpoint if set debug mode will be forced on a IU watchpoint trap Oxb 6 Break on S W breakpoint BS if set debug mode will be forced when an breakpoint instruction ta 1 is executed T Break now BN Force proce
217. me as the data ready DR bit would have been set but no new character is transferred to RHR The parity error PE bit is set or cleared for each received character The parity error PE bit is also cleared when a 0 is written to it via the UART status register The break BR bit is set when all zero bits have been received and the stop bit is zero The break BR bit is not cleared when a new character has been received it is cleared when a 0 is written to it via the UART status register The framing error FE bit is set when any non zero bits have been received and the stop bit is zero The framing error FE bit is not cleared when a new character has been received it is cleared when a 0 is written to it via the UART status register If both receiver holding RHR and shift RSR registers contain an un read character when a new Start bit is detected then the character held in the receiver shift register RSR will be lost and the overrun OV bit will be set in the UART status register The overflow bit OV is not cleared when a new character has been received it is cleared when a 0 is written to it via the UART status register If flow control is enabled then the RTSN will be negated high when a valid start bit is detected and the receiver holding register contains an un read character When the holding register is read the RTSN will automatically be reasserted again 3 3 5 3 Baud rate generation Each UART contains a
218. mer 1 reload value register 0x80030014 Timer 1 control register 0x80030018 Timer 1 latch register 0x8003001C Timer 2 counter value register 0x80030020 Timer 2 reload value register 0x80030024 Timer 2 control register 0x80030028 Timer 2 latch register 0x8003002C Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 190 EROFLEX GAISLER 13 3 6 24 bit General Purpose Input Output RUAG Aerospace Defence Technology TABLE 90 24 bit General Purpose Input Output registers 13 3 7 CAN Interface Register Address Input Register 0x80020000 Output Register 0x80020004 Direction Register 0x80020008 Interrupt Mask Register 0x8002000C Interrupt Polarity Register 0x80020010 Interrupt Edge Register 0x80020014 Pulse Register 0x80020018 Pulse Counter Register 0x8002001C TABLE 91 CAN Controller registers Register Address Configuration Register 0x80080000 Status Register 0x80080004 Control Register 0x80080008 SYNC Mask Filter Register 0x80080018 SYNC Code Filter Register 0x8008001C Pending Interrupt Masked Status Register 0x80080100 Pending Interrupt Masked Register 0x80080104 Pending Interrupt Status Register 0x80080108 Pending Interrupt Register 0x8008010C Interrupt Mask Register 0x80080110 Pending Interrupt Clear Register 0x80080114 Transmit Channel Control Regi
219. minated and the integer unit re enabled when an unmasked railed with higher level than the current processor interrupt level PIL becomes pending All other functions and peripherals operate as nominal during the power down mode A suitable power down routine could be struct pwd_reg type volatile int pwd power down struct pwd_reg type lreg struct pwd_reg type 0x80000018 while 1 lreg gt pwd lreg gt pwd In assembly a suitable sequence could be power down set 0x80000000 13 st g0 13 0x18 ba power_down ld 13 0x18 g0 3 3 9 AHB status register Any access triggering an error response on the AHB bus will be registered in two registers AHB failing address register and AHB status register The failing address register will store the address of the access while the AHB status register will store the access and error types The registers are updated when an error occur and the EV error valid is not set When the EV bit is set interrupt is generated to inform the processor about the error After an error the EV bit has to be reset by software Figure 33 shows the layout of the AHB status register 31 9 8 7 6 a 2 0 RESERVED EE EV RW HMASTER HSIZE Figure 33 AHB status register 9 EE EDAC correctable error Set when a correctable EDAC error is detected 8 EV error valid Set when an error occurred 7 RW Read Write This bit is set if the failed
220. n cr a ee Source Path Addr No Source Path Addr Words Len One Source Path Addr Word Two Source Path Addr Words Three Source Path Addr Words Leading bytes equal to zero are removed But if Source Path Addr Len 0 and all bytes of the Source Path Address are zero a single byte is kept Increment Increment Address Data are written to consecutive addresses Non Incrementing Address Data are written to the same address Not supported by protocol handler Acknowledge Send Response NoAcknowledge Don t send a Response NoAcknowledge is only possible for write commands Verify Data Check data CRC before writing Only supported for 4 bytes word aligned by hardware protocol handler Commands of other sizes or with mis aligned addresses are rejected Don t check data CRC before write Write Write command Command The header is a command header Me IG epee ee aiteroectonaiiae Reserved O0 Mustalwaysbe O o O Note that commands of formats not supported by the RMAP hardware implementation in the SpaceWire SPW2 Module like e g Non Incrementing Address are passed on to the software if the RMAP hardware support is turned off provided that software support for transfer protocols is enabled For more details on RMAP see 10 6 4 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX i RUAG GAISLER Aerospace Defence Technology 10 5 9 4 6 Extende
221. n of single errors during reads Figure below shows a block diagram of the internals of the RAM AHB Bus AHB Slave l Interface AHB SRAM x AHB APB Bridge data t Mux 74 47 f f error Configuration Register A Ae Mux j Configbits TCB E ncoding x cb APB Bus l Decoding l i A A Mux Vv Vv data cb Syncram Figure 58 The FT AHB RAM block diagram Operation The on chip fault tolerant RAM is accessed through an AHB slave interface Run time configuration is done by writing to a configuration register accessed through an APB inter face The fields of the configuration register are shown in detail later in this section The following can be configured during run time EDAC can be enabled and disabled Read and write diagnostics can be controlled through separate bits The single error counter can be reset If EDAC is disabled EN bit in configuration register set to 0 write data is passed directly to the RAM area and read data will appear on the AHB bus immediately after it arrives from memory If EDAC is enabled write data is passed to an encoder which outputs a 7 bit checksum The checksum is stored together with the data in memory and the whole operation is performed without any added waitstates This applies to word sto
222. n read 31 10 9 0 RESERVED COUNTER VALUE Figure 22 Prescaler counter register 31 10 Reserved No effect when written to Undefined when read Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX s RUAG GAISLER Aerospace Defence Technology 3 3 5 UARTs Two identical UARTs are provided for serial communications The UARTs support data frames with 8 data bits one optional parity bit and one stop bit To generate the bit rate each UART has a programmable 12 bits clock divider Hardware flow control is supported through the RTSN CTSN hand shake signals Figure 23 shows a block diagram of a UART lt _k _ CTSN Serial port Baud rate B bitok Controller _ ky_ RTSN generator RXD K Receiver shift register Transmitter shift register gt K TXD t Receiver holding register Transmit holding register Internal I O Bus Figure 23 UART block diagram 3 3 5 1 Transmitter operation The transmitter is enabled through the TE bit in the UART control register When ready to transmit data is transferred from the transmitter holding register to the transmitter shift register and converted to a serial stream on the transmitter serial output pin TXD It automatically sends a start bit followed by eight data bits an optional parity bit and one stop bits
223. n the SpaceWire CODEC Timing Constraints All fields of this register except LinkState RxParked and TxParked are included for test and debug purposes only Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX m RUAG GAISLER Aerospace Defence Technology Field Value Description DisErr ParErr EscErr RxCredErr Receiver credit error status The receiver has received more data characters then requested TxCredErr Transmitter credit error status The transmitter has credit to send more than the LinkState 000 CODEC link state machine in ErrorReset state 1 1 1 1 1 000 InfRun l GotNull l GotFCT l GotNChar l GotTime l TxCred1 l SeqErrNChar_ 1 SegErrTime 1 RxEmpty 10 The receive buffer is not empty 1 The receive buffer is empt TxEmpty O The transmit buffer is not empty The transmit buffer is empty RxParked 0 Rx not parked 1 No data in Rx pipe all reception mechanisms idle and link is disconnected TxParked o0 Tx not parked No data in Tx pipe all transmission mechanisms idle and link is disconnected i SPW Receive Time Code Status Register SPW_RTCSR R 31 8 7 6 5 0 RxTimeCtrl RxTimeCnt 0 0 MSB LSB Function This register is used for Time Code reception Timing Due to module implementation limitations a time code received less than 1 4
224. nce Technology 12 AMBA AHB APB BRIDGE 12 1 Overview 12 2 The APB bridge is a APB bus master The controller supports up to 16 slaves AHB BUS APB Bridge APBO O e 0 APB SLAVE AHB Slave APBO n Interface 4 4 APB SLAVE _ APBI Figure 78 APB Bridge block diagram Operation 12 2 1 Decoding A slave can occupy any binary aligned address space with a size of 256 bytes 1 Mbyte 12 2 2 Plug amp play information GRLIB APB slaves contain two plug amp play information words which are included in the APB records they drive on the bus see the GRLIB User s manual for more information These records are com bined into an array which is connected to the APB bridge The plug amp play information is mapped on a read only address area at the top 4 kbytes of the bridge address space Each plug amp play block occupies 8 bytes The plug amp play information is mapped on a read only address area mapped on address 0x800FF000 Ox800FF1FF 31 24 23 1211109 5 4 0 APB Plug amp play record 0x00 VENDOR ID DEVICE ID 00 VERSION IRQ Configuration word 12 3 0x04 ADDR c P MASK TYPE BAR 31 20 19 16 15 4 3 0 Figure 79 APB plug amp play information Vendor and device id The module has vendor id 0x01 Gaisler Research and device id 0x06 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Ver
225. nded Address byte is used to extend the 32 bit memory address to 40 bits allowing a 1 Terabyte address space to be accessed directly in each node Note that the SPW2 RMAP protocol handler supports only 4 bits of extended addressing i e a 64 GiB address space and thus bits 7 4 of the Extended Address in commands directed to the SPW2 should always be zero Memory Address bytes form the bottom 32 bits of the memory address to which the data in a write command is to be written or from where data is to be read for a read command Input output registers and control status registers are assumed to be memory mapped Data Length bytes form the 24 bit length of the data that is to be written or read The length is the length in bytes with the most significant byte of the length sent first Header CRC byte is an 8 bit Cyclic Redundancy Check CRC used to confirm that the header is correct before executing the command The header CRC is formed using the CRC 8 code used in ATM Asynchronous Transfer Mechanism CRC 8 has the following polynomial x x x 1 with a starting value of 0016 Each byte in the header starting with the destination logical address and ending with the byte before the header CRC itself is used in the calculation of the CRC The CRC is implementing a Galois version Linear Feedback Shift Register Data bytes are the data that is to be written in a write command or the data that is read in a read response Data CRC is an 8 bi
226. ng from DSU By asserting LeonDsuEn and LeonDsuBre at reset time the processor will directly enter debug mode without executing any instructions The system can then be initialised from the communication link and applications can be downloaded and debugged Additionally external flash proms for standalone booting can be re programmed 3 6 Vendor and device id The AMBA AHB master of the LEON2 caches has vendor id 0x04 ESA and device id 0x002 The AMBA AHB slave of the LEON2 memory controller has vendor id 0x04 ESA and device id OxOOF The AMBA AHB slave of the LEON2 DSU has vendor id 0x01 Gaisler Research and device id 0x002 The AMBA AHB master of the LEON2 DSU AHB UART has vendor id 0x04 ESA and device id 0x013 The AMBA APB slave of the LEON2 peripherals has vendor id 0x04 ESA and device id 0x003 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 4 ON CHIP MEMORY 4 1 Overview 4 2 The On Chip Memory is implemented with the FTAHBRAM core The FTAHBRAM is a version of the normal AHBRAM core with added Error Detection And Correction EDAC One error is cor rected and two errors are detected which is done by using a 32 7 BCH code Configuration is possi ble through an APB interface Some of the features available are single error counter diagnostic reads and writes and autoscrubbing automatic correctio
227. nitiated by the European Space Agency Licensing Note that the CAN protocol is developed by Robert Bosch GmbH and protected by patents For licens ing issues please contact Dr Gerhard Holfelder Corporate Licensing Department Robert Bosch GmbH AE EIS T binger Str 123 72762 Reutlingen Germany Phone 49 711 811 33150 Fax 49 711 811 33182 EmailGerhard Holfelder de bosch com Reference documents AMBA AMBA Specification Rev 2 0 ARM IHI 0011A 13 May 1999 Issue A first release ARM Limited GRLIB GRLIB IP Library User s Manual Version 1 0 7 Gaisler Research SPARC The SPARC Architecture Manual Version 8 Revision SAVO80SI9308 SPARC International Inc SPWSTD SpaceWire Links Nodes Routers and Networks ECSS E ST 50 12C CANSTD CAN Specification Version 2 0 Part B BOSCH S011898 ISO 11898 1993 and Amendment 1 ISO 11898 1995 Road Vehicles Interchange of Digital Information Controller Area Network CAN for high speed communi cation First Edition 1993 ISO ISO11898E ISO 11898 1993 E and Amendment 1 1995 ISO Source reference TheSpaceWire Remote Terminal Controller RTC design is based on the following sources LEON2FT SRC LEON 2 FT VHDL model version 1 0 9 16 1 r85 2007 GRLIB SRC GRLIB VHDL source code version 1 0 7 2006 CANESA SRC HURRICANE source code version 5 1 6 dated 21 Nov 2006 DUNDEE SRC SPWB source code version 2 0 System overview The SpaceWire Remote Termina
228. nk Abort handling If SPW CODEC Status Register LinkState makes a transition from the Run state e g due to an Rx error a credit count error etc see 10 6 2 for details this is called a link abort event and the LinkAbort link interrupt is issued The CODEC will at this point insert an EEP after the last received byte and discard the remainder of the packet currently being transmitted The TxVCs and Rx VCs will retain their trigging status i e once the link is up again the Rx VCs will continue to receive packets except for the eventual channel being untriggered due to the EEP in the truncated packet and the TxVCs will only experience the link abort as a temporary link congestion Note that if there was data left in the Rx FIFO when the link was disconnected this will be handled by the RxVCs and written to memory while the link is still down Note that this pretend that nothing happened handling of link abort is the one recommended by the standard The host system should employ an acknowledge protocol or read back written values to ensure that a packet reached the recipient and not assume that every transmitted packet reaces the recipient as long as the link stays up Note also that the FCT Flow Control Token needed for the other node of the link to go the the Run state see 10 6 2 1 will only be transmitted if there is room for at least 8 more bytes in the Rx FIFO This means that if the Rx FIFO was flooded when the link abo
229. nodes may be part of a network or work stand alone In a network routers are needed to direct transmitted packets to the correct destinations In this case a transmitted packet contains a header that indicates to the router s which destination the packet is targeted for The SpaceWire Module implements a single SpaceWire link This link can be used for either transmitting data in both directions on one or more virtual channels or to implement a remote memory access protocol Both transmission and reception are supported by direct memory access to the on chip bus on which the SpaceWire Module is implemented The SpaceWire Module only locally implements the buffering resources that are strictly necessary for its functionality all other data storage is performed via the on chip bus 10 4 2 Transmit protocols The SpaceWire SPW2 module supports the transmission of any type of SpaceWire packets not limited to any type of higher protocols It implements virtual channels that allow transfer from one or many dedicated areas in memory The virtual channels allow multiple communication channels over a single SpaceWire link The selection of the virtual channel from which data are to be transmitted on the SpaceWire link is performed by round robin arbitration Each virtual transmit channel has a separate send list stored in memory The send list entries define what data is to be sent from memory The send list entry structure is shown in 10 5 9 6 Note th
230. nostic information Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 1 7 Description of typical systems using the device The SpaceWire Remote Terminal Controller RTC device can be integrated in the instrument control ler Unit ICU that acts as the payload data processor and mainly receives payload data from instru ments and produces processed data to be down linked The main data communication is performed via the SpaceWire network The ICU is however controlled and monitored via the CAN network from the On Board Computer OBC The CAN controller in the SpaceWire RTC device acts as a remote termi nal that is being managed by the OBC Alternatively the SpaceWire RTC device can be integrated in the On Board Computer OBC Since the OBC acts as the network manager on the CAN network the CAN controller carters capability such as node management and time distribution The OBC also communicates or manages the Space Wire network via SpaceWire links As can be seen from the above application scenarios the capabilities of the SpaceWire RTC device are not limited only to support the CAN bus in the ICU but also allows it to be used in an OBC This reduces future development costs since the same device is used in both payload and avionics This also promotes the usage of hybrid SpaceWire and CAN networks and the TopNet concept To bring
231. ns of DMA over the AMBA AHB bus No new write accesses to the FIFO will be started Any ongoing FIFO access will be completed If the data is written successfully the read pointer FifoTxRD READ is automatically incremented and the FifoTx STAT TxOnGoing bit will be cleared Any associated interrupts will be generated Any other fetched or pre fetched data from the circular buffer which is temporarily stored in the the local buffer will be discarded and will be fetched again when the transmit channel is re enabled The progress of the any ongoing access can be observed via the FifoTxSTAT TxOnGoing bit The FifoTxSTAT TxOnGoing must be Ob before the channel can be re configured safely i e changing address size or read write pointers It is also possible to wait for the TxEmpty interrupt described hereafter The channel can be re enabled again without the need to re configure the address size and pointers No data transmission is started while the channel is not enabled Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 5 4 8 Interrupts During transmission several interrupts can be generated e TxEmpty Successful transmission of all data in buffer e TxIrq Successful transmission of a predefined number of data e TxError AHB access error during transmission The TxEmpty and TxIrq interrupts are only generated as the result
232. nted as relative to the buffer base address scaled with the SIZE field 9 10 11 Transmit Channel Interrupt Register CanTxIRQ R W TABLE 68 Transmit Channel Interrupt Register 31 20 19 4 3 0 IRQ 31 20 Reserved No effect when written to Undefined when read 19 4 IRQ Interrupt is generated when CanTxRD READ IRQ as a consequence of a message transmission 3 0 Reserved No effect when written to Undefined when read All bits are cleared to 0 at reset Note that this indicates that a programmed number of messages have been transmitted The field is implemented as relative to the buffer base address scaled with the SIZE field 9 10 12 Receive Channel Control Register CanRxCTRL R W TABLE 69 Receive Channel Control Register 31 2 1 0 OnG Ena oing ble 31 2 Reserved No effect when written to Undefined when read 1 ONGOING Reception ongoing read only 0 ENABLE Enable channel Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX 7 RUAG GAISLER Aerospace Defence Technology All bits are cleared to 0 at reset Note that in the case an AHB bus error occurs during an access while fetching transmit data and the CanCONF ABORT bit is 1b then the ENALBE bit will be reset automatically At the time the ENABLE is cleared to 0b any ongoing message reception is not aborted Note that the ONGOING bit being 1b indicates that message re
233. o external FIFO e circular transmit buffer e direct memory access for transmitter e data reception from external FIFO e circular receive buffer e direct memory access for receiver e automatic 8 and 16 bit data width conversion e general purpose input output Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 5 1 2 Transmission Data to be transferred via the FIFO interface are fetched via the AMBA AHB master interface from on chip or off chip memory This is performed by means of direct memory access DMA implement ing a circular transmit buffer in the memory The transmit channel is programmable via the AMBA APB slave interface which is also used for the monitoring of the FIFO and DMA status The transmit channel is programmed in terms of a base address and size of the circular transmit buffer The outgoing data are stored in the circular transmit buffer by the system A write address pointer reg ister is then set by the system to indicate the last byte written to the circular transmit buffer An inter rupt address pointer register is used by the system to specify a location in the circular transmit buffer from which a data read should cause an interrupt to be generated The FIFO interface automatically indicates with a read address pointer register the location of the last fetched byte from the circular transmit buffer R
234. o parity bits per tag and per 4 byte data sub block The tag parity is generated from the tag value and the valid bits Similarly the data sub block parity is derived from the sub block data The parity bits are written simultaneously with the associated tag or sub block and checked on each access Two parity bits are configured with the bits corresponding to the parity of odd and even data tag bits If a tag parity error is detected during a cache access a cache miss will be generated and the tag and data will be automatically updated All valid bits except the one corresponding to the newly loaded data will be cleared If a data sub block parity error occurs a miss will also be generated but only the failed sub block will be updated with data from main memory 3 2 7 Cache Control Register The operation of the instruction and data caches is controlled through a common Cache Control Register CCR figure 5 Each cache can be in one of three modes disabled enabled and frozen If disabled no cache operation is performed and load and store requests are passed directly to the memory controller If enabled the cache operates as described above In the frozen state the cache is accessed and kept in sync with the main memory as if it was enabled but no new lines are allocated on read misses 31 3029 2827 26 25 24 23 22 2120 19 18 17 16 15 14 13 12 11 109 8 765432410 DREPL IREPL ISETS DSETS DS FD FI cec CPTE 1B ie r ITE IDE DT
235. oad register 2 where 2 is the number of implemented timers By setting the chain bit in the control register timer n can be chained with preceding timer n 1 Decre menting timer n will start when timer n 1 underflows Each timer can be reloaded with the value in its reload register at any time by writing a one to the load bit in the control register Vendor and device id The module has vendor id 0x01 Gaisler Research and device id 0x38 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 7 4 Registers Table 47 shows the timer unit registers The number of implemented registers depend on number of implemented timers TABLE 47 GRTIMER unit registers Register Address Scaler value 0x80030000 Scaler reload value 0x80030004 Configuration register 0x80030008 Timer latch configuration register 0x8003000C Timer 1 counter value register 0x80030010 Timer 1 reload value register 0x80030014 Timer 1 control register 0x80030018 Timer 1 latch register 0x8003001C Timer 2 counter value register 0x80030020 Timer 2 reload value register 0x80030024 Timer 2 control register 0x80030028 Timer 2 latch register 0x8003002C Figures 67 to 72 shows the layout of the timer unit registers Any blank register is considered as reserved and has no effect when writen to and returns undefined dat
236. oing CAN mes sage storage on the AHB bus will not be aborted and no new message storage will be started Note that only complete messages can be received from the HurriCANe codec If the message is stored success fully the write pointer CanRxWR WRITE is automatically incremented Any associated interrupts will be generated The progress of the any ongoing access can be observed via the CanRxCTRL ONGOING bit The CanRxCTRL ONGOING must be 0b before the channel can be re configured safely i e changing address size or read write pointers It is also possible to wait for the Rx and RxMiss interrupts described hereafter The channel can be re enabled again without the need to reconfigure the address size and pointers Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER 9 7 9 8 9 9 Aerospace Defence Technology No message reception is performed while the channel is not enabled 9 6 8 Interrupts During reception several interrupts can be generated e RxMiss Message filtered away for receive e RxErrCntr Error counter incremented for receive e RxSync Synchronization message received e Rx Successful reception of one message e RxFull Successful reception of all messages possible to store in buffer e RxIrq Successful reception of a predefined number of messages e RxAHBErr AHB access error during reception e OR Over run during reception
237. ointer as soon as a message is received by the HurriCANe codec an AMBA AHB store access will be started The received message will be tempo rarily stored in a local store buffer in the CAN controller Note that the channel should not be enabled until the write and read pointers are configured to avoid the message reception to start prematurely After a message has been successfully stored the CAN controller is ready to receive a new message The write pointer CanRxWR WRITE is automatically incremented taking wrap around effects of the circular buffer into account Interrupts are provided to aid the user during reception as described in detail later in this section The main interrupts are the Rx RxFull and RxIrq which are issued on the successful reception of a mes sage when the message buffer has been successfully filled and when a predefined number of messages have been received successfully The RxMiss interrupt is issued whenever a message has been received but does not match a message filtering setting i e neither for the receive channel nor for the SYNC message described hereafter The RxSync interrupt is issued when a message matching the SYNC Code Filter Register SYNC and SYNC Mask Filter Register MASK registers has been successfully received Additional interrupts are provided to signal error conditions on the CAN bus and AMBA bus 9 6 5 Straight buffer It is possible to use the circular buffer as a straight buffer with a hi
238. olding register 1 Transmitter shift register empty TS indicates that the transmitter shift register is empty 2 Transmitter hold register empty TH indicates that the transmitter hold register is empty 3 Break received BR indicates that a BREAK has been received 4 Overrun OV indicates that one or more character have been lost due to overrun 5 Parity error PE indicates that a parity error was detected 6 Framing error FE indicates that a framing error was detected 31 7 Reserved No effect when written to Undefined when read Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX P RUAG GAISLER Aerospace Defence Technology 31 12 11 0 RESERVED SCALER RELOAD VALUE Figure 28 UART scaler reload register 31 12 Reserved No effect when written to Undefined when read 3 3 6 Parallel I O port A partially bit wise programmable 32 bit I O port is provided on chip The port is split in two parts the lower 16 bits are accessible via the LeonPio 15 0 signal while the upper 16 bits uses D 15 0 and can only be used when all areas rom ram and I O of the memory bus are in 8 bit mode See 8 bit PROM and SRAM access on page 35 The lower 16 bits of the I O port can be individually programmed as output or input while the high 16 bits of the I O port only be configures as outputs or inputs on byte basis Two registers
239. om the destination node back to the source node which sent the command Leading all zero bytes of the return address are ignored If a packet is to be sent to address zero then this is done by setting the entire Source Path Address to zero This will result in a single zero path address byte being sent in front of the logical address Source Logical Address byte is the destination logical address to be used in a response or acknowledgement to a command The Source Address is normally set to the logical Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX i RUAG GAISLER Aerospace Defence Technology address of the source node that is sending the command The Source Address byte may be set to 254 0FE16 which is the default logical address if the command source node does not have a logical address Transaction Identifier bytes are used to identify command response and acknowledge transactions that make up a particular read or write operation The source of the command gives the command a unique transaction identifier This transaction identifier is returned in the response or acknowledgement to the command This allows the command source to send many commands without having to wait for a response to each command before sending the next command When a response or acknowledge comes in it can be quickly associated with the command that caused it by the transaction identifier Exte
240. ommand will be rejected instead of transferred to software for further processing See 10 6 4 1 and 10 6 4 2 for details SPW RxVC Config Register SPW_RxCnf R W 31 2 1 0 Word Rx Align En 0 0 MSB LSB Function This register configures the reception of SpaceWire Virtual Channel Transfer Protocol packets Timing Constraints Valid index range is 1 lt lt RxVC_G The word alignment function assumes that the RxVC DMA Base Address is programmed with a word aligned start address Note that all RxVC use the DLA configured in SPW RxVC Config Register 0 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX r RUAG GAISLER Aerospace Defence Technology Field Value Description RxEn 0 The virtual receive channel is disabled All packets are discarded No packets are received on this virtual receive channel and no data are stored to memory Note that this bit is only used during the identification process described in 5 5 3 2 I e when disabled any ongoing packet will be completed WordAlign 0 No padding takes place and a packet will start at the byte address following the previous packet The end of each packet is padded up to the closest 32 bit word boundary Padding is done with arbitrary content The first byte of a packet will thus always be aligned to a 32 bit word address
241. ommand with a non matching Destination Key arrives the RMAP command is rejected during the header check and the Invalid Destination Key error response is generated when a reply is requested by the incoming RMAP command 10 6 4 5 RMAP responses The SpaceWire Module generates automatically RMAP responses according to RMAP for commands executed by the hardware Responses are only generated if an acknowledgement is requested in the received RMAP command The SpaceWire Module generates the following errors in accordance with RMAP RMAP Command not supported RMAP Command field combination unused according to RMAP Invalid destination key If there is not an exact match of the destination key field General error code If error during data transfer to internal bus e g due to illegal address or data protection error detected on internal bus Invalid data CRC If RMAP data CRC error Early EOP If early EOP in data i e EOP has been received with less data than expected from the RMAP command header Cargo Too Large If late EOP or EEP in data i e EOP or EEP has been received with more data than expected from the RMAP command header Early EEP If early EEP in data i e EEP has been received with less data than expected from the RMAP command header Authorisation error If RxVC Config Register 0 RMAPEn and RxVC Config Register 0 RXEn are disabled or if RxVC Config Register 0 RMAPEn and RxVC Config Register 0
242. on active virtual receive and transmit channels Timing Constraints The ActiveTxVC and ActiveRxVC values are limited by the number of implemented virtual channels An ActiveTxVC value of 0 indicates that the hardware supported RMAP is transmitting an RMAP response An ActiveRxVC value of 0 indicates that a command or reply is received for further software processing Field Value Description TxVCAct o au Tx VCs are inactive A a becomes active EOS ARVE E ehe DEBERSE VET All Rx VCs are inactive T becomes active ActiveTxVC 0 7 The last selected TxVC This field is set to indicating which virtual channel TxVC is the active one The value is only valid while the TxVCAct bit is set ActiveRxVC 0 7 The last selected RxVC This field is set to indicating which virtual channel Rx VC is the active one The value is only valid while the RxVCAct bit is set 10 7 1 4 CODEC Status register SPW CODEC Status Register SPW_CSR R 31 20 19 18 17 16 Tx Rx Tx Rx Parked Parked Empty Empty 1 1 1 1 MSB 15 14 13 12 11 10 9 8 7 5 4 3 2 1 0 Seq Seq TxCr Got Got Got Got Inf LinkState Tx Rx Esc Par Dis Err ErrN ed Time N FCT Null Run Cred Cred Err Err Err Time Char 1 Char Err Err 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB Function This register provides status information o
243. onfiguration register It is incremented each time a single databit error is encountered reads or sub word writes The number of bits of this counter is 8 It is accessed via the configuration register Each bit can be reset to zero by writing a one to it The counter saturates at the value 255 Autoscrubbing is an error handling feature and cannot be controlled through the configuration register Every single error encountered during a read results in the word being written back with the error cor rected and new checkbits generated It is not visible externally except for that it can generate an extra waitstate This happens if the read is followed by an odd numbered read in a burst sequence of reads or if a subword write follows These situations are very rare during normal operation so the total timing impact is negligible 4 3 Vendor and device id The module has vendor id 0x01 Gaisler Research and device id 0x50 4 4 Registers Table 15 shows the FTAHBRAM registers TABLE 15 FT AHB RAM unit registers Register Address Configuration Register 0x80010000 Figure 59 below shows the register bit fields All fields except TCB are initialised at reset The EDAC is initially disabled EN 0 which also applies to diagnostics RB and WB are zero Additionally if the single error counter is enabled the error counter SEC is set to zero and interrupts are disabled IE 0 Copyright 2006 2007 2008 2009 Aeroflex Gaisler
244. ore FIFO devices for data output transmission and or one or more FIFO devices for data input reception The external interface supports FIFO devices with 8 and 16 bit data width Note that one device is used when 8 bit and two devices are used when 16 bit data width is needed The data width is programmable Note that this is performed commonly for both directions The external interface supports one parity bit over every 8 data bits Note that there can be up to two parity bits in either direction The parity is programmable in terms of odd or even parity Note that odd parity is defined as an odd number of logical ones in the data bits and parity bit Note that even parity is defined as an even number of logical ones in the data bits and parity bit Parity is generated for write accesses to the external FIFO devices Parity is checked for read accesses from the external FIFO devices and a parity failure results in an internal interrupt The external interface provides a Write Enable output signal The external interface provides a Read Enable output signal The timing of the access towards the FIFO devices is programmable in terms of wait states based on system clock periods The external interface provides an Empty Flag input signal which is used for flow control during the reading of data from the external FIFO not reading any data while the external FIFO is empty Note that the Empty Flag is sampled at the end of the read access to determine i
245. ose input output channel is as input The default reset value each general purpose input output chan nel is logical zero Note that protection toward spurious pulse commands during power up shall be mitigated as far as pos sible by means of I O cell selection from the target technology 6 2 2 Analogue to digital conversion The ADC interface supports 8 and 16 bit wide input data The ADC interface provides an 8 bit address output shared with the DAC interface Note that the address timing is independent of the acquisition timing The ADC interface shall provide the following control signals e Chip Select e Read Convert e Ready The timing of the control signals is made up of two phases e Start Conversion e Read Result The Start Conversion phase is initiated by one of the following sources provided that no other conver sion is ongoing e Event on one of three separate trigger inputs e Write access to the AMBA APB slave interface Note that the trigger inputs can be connected to internal or external sources to the ASIC incorporating the core Note that any of the trigger inputs can be connected to a timer to facilitate cyclic acquisition The selection of the trigger source is programmable The trigger inputs is programmable in terms of Rising edge or Falling edge Triggering events are ignored if ADC or DAC conversion is in progress The transition between the two phases is controlled by the Ready signal The Ready input sign
246. ote that send list sizes of zero and send list entries with header and or data sizes being zero are supported If both header and data sizes are set to zero only a single EOP will be transmitted If both header and data sizes are set to zero and CRC checksum generation is enabled an all zero byte followed by an EOP will be transmitted Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX 142 RUAG GAISLER Aerospace Defence Technology Direct memory access using word based data width is always used to fetch header or data An example of a send list structure is shown below SendList Handling SendList Stored in memory Header Example Stored in memory gE A E AA E S A ETS 1 Path Path Path SendListPointer 1 st SendList Entry x Stored in TxVC Current R Te CRCS TavC s SenaList Pointer Reg _ S2ndList e HeaderSize Page Type ee ocean eee Pie Ste en ee Pointer TxVC 3 SendList Size Reg HeaderAddress Example _DataSize Page Type Stored in memory EER E EA A A eee same Figure 10 17 TxVC send list handling 10 6 6 2 Arbitration The arbitration between virtual transmit channels is performed as follows A new TxVC is arbitrated after each completed transmission of a send list entry The arbitration only takes into account the TxVC that have been triggered The arbitration uses a round robin activation algorithm fo
247. put Register 0x80040020 Address Output Register 0x80040024 Address Direction Register 0x80040028 Data Input Register 0x80040030 Data Output Register 0x80040034 Data Direction Register 0x80040038 Any blank register is considered as reserved and has no effect when writen to and returns undefined data when read Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX g RUAG GAISLER Aerospace Defence Technology 6 3 1 Configuration Register ADCONF R W TABLE 37 Configuration register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DACWS WR DACDW POL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCWS RCP CSMODE CSP RDY RDY TRI TRIGMODE ADCDW OL OL MO POL GPO DE L 31 24 RESERVED No affect when written to Undefined when read 23 19 DACWS Number of DAC wait states O to 31 5 bits 18 WRPOL Polarity of DAC write strobe Ob active low 1b active high 17 16 DACDW DAC data width 00b none 01b 8 bitADData 7 0 10b 16 bitADData 15 0 11b none spare 15 11 ADCWS Number of ADC wait states O to 31 5 bits 10 RCPOL Polarity of ADC read convert Ob active low read 1b active high read 9 8 CSMODE Mode of ADC chip select 00b asserted during conversion and read phases 01b asserted during conversion phase 10b asserted during read phase 11b asserted continuously during both phases T CSPOL Polarity of ADC c
248. quest 1b for Remote Frame Ob for Data Frame bID Base Identifier eID Extended Identifier DLC Data Length Code according to CAN standard 0000b 0 bytes 0001b 1 byte 0010b 2 bytes 0011b 3 bytes 0100b 4 bytes 0101b 5 bytes 0110b 6 bytes O111b 7 bytes 1000b 8 bytes OTHERS illegal TxErrCntr Transmission Error Counter RxErrCntr Reception Error Counter AHBErr AHB interface blocked due to AHB Error when 1b OR Reception Over run when 1b OFF Bus Off mode when 1b PASS Error Passive mode when 1b Byte 00 to 07 Transmit Receive data Byte 00 first Byte 07 last Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX T RUAG GAISLER Aerospace Defence Technology 10 SPACEWIRE LINK INTERFACE This chapter gives an overview of the functions of the SpaceWire SPW2 Module It is written as a descriptive text used to increase the understanding of the functions 10 1 System overview The SpaceWire SPW2 Module is intended to fit into systems where there is a need for communication via SpaceWire links The figure below shows how the SpaceWire Module would fit into a typical application Note that the routers are optional and direct SpaceWire links may be used instead ASIC SpaceWire SpaceWire CPU SSS feats 4 Rotter 51 Application A Node 1 RAM SpaceWire l SpaceWire Application B lt 4 M 2
249. r SPW_RxISR M 16 4A S 2 0 lt lt RxVC 0000_0MN4 SPW RxVC Interrupt Status Set Register SPW_RxISSR M 16 A S 2 0 lt lt RxvCc 0000_OMN81i SPW RxVC Interrupt Status Clear Register SPW_RxISCR MN 16 4 2 0 lt lt RxVC 0000_O3N0i SPW TxVC SendList Pointer Register SPW_TxSLPR N 2 0 lt lt TxVC 0000_03N4 SPW TxVC SendList Size Register SPW_TxSLSR N 2 S 0 lt lt TxVC 0000_03N8i SPW TxVC Status Register SPW_TxSR N 2 S 0 lt lt TxVC 0000_03NCi SPW TxVC Interrupt Status Register SPW_TxISR N 2 0 lt lt TxVC 0000_03N0 SPW TxVC Interrupt Status Set Register SPW_TxISSR N 2 1 0 lt lt TxVC 0000_03N4i SPW TxVC Interrupt Status Clear Register SPW_TxISCR N 2 1 0 lt lt TxVC 10 7 1 SpaceWire SPW2 Module Registers 10 7 1 1 Interrupt registers SPW Pending Interrupt Masked Status Register SPW_PIMSR RM SPW Pending Interrupt Status Register SPW_PISR R SPW Interrupt Mask Register SPW_IMR R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Rx7 Rx6 Rx5 Rx4 Rx3 Rx2 Rx Rx0 Tx7 Tx6 Tx5 Tx4 Tx3 Tx2 Tx1 Txo 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Link Pkt Tx Rx Cr ESC Par Diss Abat Rej Tne Time Err Err Err Err Code Code 0 0 0 0 0 0 0 0 LSB Function Note that the individual bits in the register group are set and cleared using the corresponding SPW_LISS
250. r TxCtrl field The SPW Tx Time Code Register TxTimeCnt is increased by one modulo 64 before the new value is transmitted on the SpaceWire Link It is possible to configure the start value of the time information T0 T5 to be transmitted by writing to the SPW Tx Time Code Register TxTimeCnt field The SPW Tx Time Code Register TxCtrl field only reflects the status of the input signal SpwTxTimeCtrl of the SpaceWire Module and contains the control flags T6 T7 The TxTime Code interrupt is issued when the time code is transmitted 10 6 7 2 Time code reception The received time code can be read from the SPW Rx Time Code Status Register comprising the time information T0 T5 and the control flags T6 T7 The register is updated for every time code received independently of the value When time information that has been received with a value exactly one higher modulo 64 than the previously received time information which is locally stored in the SPW Rx Time Code Register RxCnt field a pulse is generated on the SpaceWire Module output signal SpwRxTick which in turn is connected to the SpaceWire RTC common interrupt bus and the RxTime Code interrupt is issued Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX re RUAG GAISLER Aerospace Defence Technology Destination SPW Node Module Rd Wr Rd T
251. r signals and registers some extra conventions are defined below e A name may never start with a digit e g 1553 could instead be M1553 e A dollar sign in a name is used as a wildcard representing a number If the dollar sign is used in a context it must then be defined somewhere else in the document e An asterisk in a name is used as a wildcard representing one or more characters 10 5 3 Radix The following conventions is used for writing numbers e Binary numbers are indicated by the subscript 2 e g 12 1011_1010 1011 1110 010010 etc e Decimal numbers are indicated by the subscript 10 e g 67 8723 10 4786010 e Hexadecimal numbers are indicated by the subscript 16 e g E16 BABE 16 e Unless the Radix is explicitly declared as above the number should be considered to be decimal number 10 5 4 Signal Names The following conventions are used for signal names e Signal names are written in italics e g SignalName Active low signals have a capital N appended to their name e g SignalNameN Bus indices are indicated with brackets e g SignalName 12 3 Signals maybe grouped into subsignals e g SignalName SubSignal Signals with two functions are named with the name and then the first functionality followed by the second function e g SignalName Function Function2N The second function is the valid when the signal is deasserted thus the suffix N in the name 10 5 5 Externally Ac
252. r the TxVC channels except for the RMAP response sent on Tx VC 0 which always has the highest priority 10 6 6 3 Transmission The transmission on a virtual transmit channel adheres to the following procedure At start of send list After a write access to the SPW _TxVC Send List Size Register the SPW Tx VC Status Register ChTrig is set indicating that the transmission is triggered This is only needed when a new send list is started For each send list entry Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX T RUAG GAISLER Aerospace Defence Technology TxVC arbiter defines when an atomic send list entry handling can start by setting SPW TxVC Status Register ChAct The TxVC uses the SPW TxVC Send List Pointer Register as address and fetches the first two words of the send list entry i e header address size type and page and loads and starts the common DMA handler with this content The header bytes fetched are directly passed on to the TxFIFO for transmission Note that both the DMA start address and size can be misaligned and only the portion starting from DMA start address and the exact number of bytes are transmitted A null size is also possible in which case no bytes are fetched Next the second part of the send list entry i e data address size type and page are fetched followed by a reload and start of the common
253. rate pulse commands out of phase with each other Each channel can generate a separate internal interrupt The interrupt are individually programmed as enabled or disabled as active high or low level sensitive or as rising or falling edge sensitive 8 1 1 Function The core implements the following functions e Input and input interrupts e Output and output pulse commands e Status and monitoring 8 1 2 Interfaces The core provides the following external and internal interfaces e Discrete input and output interface e AMBA APB slave interface with sideband signals as per GRLIB including e interrupt bus configuration information diagnostic information 8 1 3 Vendor and device id e The module has vendor id 0x01 Gaisler Research and device id 0x37 8 2 Registers The GRPULSE is programmed through registers mapped into APB address space TABLE 48 GRPULSE registers Register Address Input Register 0x80020000 Output Register 0x80020004 Direction Register 0x80020008 Interrupt Mask Register 0x8002000C Interrupt Polarity Register 0x80020010 Interrupt Edge Register 0x80020014 Pulse Register 0x80020018 Pulse Counter Register 0x8002001C Any blank register is considered as reserved and has no effect when writen to and returns undefined data when read Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX j RUAG GAISLER Aerospace Defenc
254. rated FPU interface does not implement a floating point queue and the processor is stopped during the execution of floating point instructions This means that QNE bit in the fsr register always is zero and any attempts of executing the STDFQ instruction will generate a FPU exception trap Cache sub system 3 2 1 Overview The LEON processor implements a Harvard architecture with separate instruction and data buses connected to two independent cache controllers In addition to the address a SPARC processor also generates an 8 bit address space identifier ASI providing up to 256 separate 32 bit address spaces During normal operation the LEON processor accesses instructions and data using ASI 0x8 OxB as defined in the SPARC standard Using the LDA STA instructions alternative address spaces can be accessed The table shows the ASI usage for LEON Only ASI 3 0 are used for the mapping ASI 7 4 have no influence on operation TABLE 4 ASI usage ASI Usage 0x0 0x1 0x2 0x3 Forced cache miss replace if cacheable 0x4 0x7 Forced cache miss update on hit 0x5 Flush instruction cache 0x6 Flush data cache 0x8 0x9 OxA OxB Normal cached access replace if cacheable OxC Instruction cache tags OxD Instruction cache data OxE Data cache tags OxF Data cache data Access to ASI 4 and 7 will force a cache miss and update the cache if the data was previously cached Access with ASI 0 3 wil
255. rcular buffer as a straight buffer with a higher granularity than the 1kbyte address boundary limited by the base address FifoTxADDR ADDR field While the channel is disabled the read pointer FifoTxRD READ can be changed to an arbitrary value pointing to the first byte to be transmitted and the write pointer FifoTxWR WRITE can be changed to an arbitrary value When the channel is enabled the transmission will start from the read pointer and continue to the write pointer 5 4 6 AMBA AHB error An AHB error response occurring on the AMBA AHB bus while data is being fetched will result in a TxError interrupt If the FifoCONF ABORT bit is set to Ob the channel causing the AHB error will re try to read the data being fetched from memory till successful If the FifoCONF ABORT bit is set to 1b the channel causing the AHB error will be disabled FifoTx CTRL ENABLE is cleared automatically to 0 b The read pointer can be used to determine which data caused the AHB error The interface will not start any new write accesses to the FIFO Any ongoing FIFO access will be completed and the FifoTxSTAT TxOnGoing bit will be cleared When the channel is re enabled the fetch and transmission of data will resume at the position where it was disabled without losing any data 5 4 7 Enable and disable When an enabled transmit channel is disabled FifoTxCTRL ENABLE 0b the interface will not start any new read accesses to the circular buffer by mea
256. re SPW2 Module The registers of the SpaceWire SPW2 Module are addressed according to the tables below The external address of each unique register is its register address added to the external base address of the module or to the external address of each of the DMA channels which is implementation specific Unused register bits are zero on register reads and don t care on register writes Register byte Register name Acronym address 0000_ 000016 SPW Pending Interrupt Masked Status Register SPW_PIMSR 0000_0008 16 SPW Pending Interrupt Status Register SPW_PISR 0000_0010i6 SPW Interrupt Mask Register SPW_IMR 0000_001416 SPW Link Interrupt Status Register SPW_LISR 0000_001816 SPW Link Interrupt Status Set Register SPW_LISSR 0000_001Cj SPW Link Interrupt Status Clear Register SPW_LISCR 0000 002016 SPW CODEC Configuration Register SPW_CCR 0000_002416 SPW Clock Division Register SPW_CDR 0000 002816 SPW RMAP Destination Key Register SPW_RDKR 0000 _002Cj SPW Transmit Time Code Register SPW_TTCR 0000 003016 SPW VC Transfer Protocol ID Register SPW_VCTPIDR 0000 _003416 SPW SW Transmit Time Code Register SPW_SWTTCR 0000_ 004016 SPW Status Register SPW_SR 0000_00441 SPW CODEC Status Register SPW_CSR 0000_0048 16 SPW Receive Time Code Status Register SPW_RTCSR 0000 _0080i6 SPW First Failing Packet Register
257. receive channels maximum of 7 It is strongly recommended that the dummy byte is set equal to the virtual channel identifier i e a copy This allows the dummy byte to represent the VCID if the packet is trapped in the SPW First Failing Packet Register of a SpaceWire SPW2 Module where only the first 3 bytes of a received packet are stored Note that at least one byte must be present in the data cargo If not then an early EOP error indication is generated in the receiver Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 RUAG Aerospace Defence Technology EROFLEX 124 GAISLER 10 5 9 6 Transmitter Send List entry structure The Virtual Transmit Channels TxVC use send lists to define what data is to be transmitted A send list contains one or more send list entries as defined hereafter SPW Send List entry Byte 31 28 27 26 25 24 23 8 7 0 offset O16 Header Page Header Type Header Size 416 Header Address 816 Data Page Data Type Data Size Cis Data Address MSB LSB Field Value Description Header Page 0 15 Header Page Address i e address bits A35 A32 enabling 64 Gbyte addressing space Header Type Send header and attach data without EOP in between Note that automatic RMAP checksum is not supported since the routing byte s is included in header but should not be included in the chec
258. res 32 bit To ensure correct checksum RAM locations containing data prior to enabling the EDAC must first be refreshed by reading and writing a complete word before enabling the EDAC If a byte or halfword store is performed the whole word to which the byte or half word belongs must first be read from memory read modify write A new checksum is calculated when the new data is placed in the word and both data and checksum are stored in memory This is done with 1 2 additional waitstates compared to the non EDAC case Note that autoscrubbing is only performed on read write access to a memory location thus it is recommended to read in frequently accessed memory periodically in order to reduce accumulation of SEU bit errors Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology Reads with EDAC disabled are performed with 0 or 1 waitstates while there could also be 2 waitstates when EDAC is enabled There is no difference between word and subword reads Table 14 shows a summary of the number of waitstates for the different operations with and without EDAC TABLE 14 Summary of the number of waitstates for the different operations for the AHB RAM Waitstates with EDAC Waitstates with EDAC Operation Disabled Enabled Read 0 1 0 2 Word write 0 0 Subword write 0 1 2 When EDAC is used the data is decode
259. rification according to RMAP as well as combined response header and data verification which is used for RMAP commands and responses forwarded to software 8 bit CRC checking is used for both header and data implemented as a Galois version LFSR with the least significant bit being used first The generator polynomial is g x x x x 1 The least significant bit is used first in the CRC generation algorithm as the SpaceWire protocol sends the least significant bit of a byte first on the link Note that the Galois version LFSR generates the result zero if the checksum itself is included in the generation This characteristic allows the calculation of a checksum over the header field the header checksum and the data field which should match the checksum calculated over the data field alone Note also that the checksum is only calculated for the bytes received at the destination i e the eventual Destination Path Address bytes which are stripped off along the way are not included Parallel Out after 8 shifts D7 D6 D5 D4 D3 D2 D1 DO Figure 10 16 Galois LFSR implementation of CRC8 polynomial Here is an implementation example of a CRC computation table in C static natural8 RMAP_CRCTable 256 0x00 0x91 Oxe3 0x72 0x07 0x96 Oxe4 0x75 0x0e Ox9f Oxed 0x7c 0x09 0x98 Oxea 0x7b Oxlc Ox8d Oxff 0x6e Oxlb Ox8a Oxf8 0x69 0x12 0x83 Oxfl Ox60
260. riggered started and whether the channel is active transfer ongoing 10 6 6 5 Interrupts Each TxVC while transmitting can issue interrupts as defined in SPW TxVC Interrupt Status Register See 10 7 1 7 for details Further transmission is halted for the virtual channel Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX 144 RUAG GAISLER Aerospace Defence Technology 10 6 7 Time Codes The SpaceWire Time Code is used to support the distribution of system time across a SpaceWire network The time code interface is implemented by the SpaceWire CODEC and is specified in CODEC The SpaceWire module adds a software interface for transmitting and receiving time codes as well as qualifying the generation of an internal time reference pulse The time code information is carried in a single byte Six bits of time information are held in the least significant six bits of the time code T0 T5 and the two most significant bits T6 T7 contain control flags that are distributed isochronously with the time code 10 6 7 1 Time Code transmission A time code is transmitted over the SpaceWire link when the input signal SpwTxTick of the SpaceWire Module is activated caused by an interrupt on the SpaceWire RTC common interrupt bus see 10 6 11 8 1 The time information transmitted is defined by the SPW Tx Time Code Register TxTimeCnt field and the SPW Tx Time Code Registe
261. rmal operation Error events are captured by the corresponding link interrupts 10 6 12 2 First Failing Packet The First Failing Packet Register indicates failures that can occur during reception of a packet When an error has occurred the register is not updated due to new errors until the register has been read In addition to an error code identifying the cause for the failure the register also contains the first three received bytes received in a packet 10 6 13 Usage Constraints 10 6 13 1 Functional None TBC 10 6 13 2 Timing None TBC 10 6 14 Examples None TBC Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX a RUAG GAISLER Aerospace Defence Technology 10 6 15 Interrupt Handling The interrupt handling in the SpaceWire SPW2 Module is implemented in two layers The top layer contains the SPW Pending Interrupt Masked Status Register the SPW Pending Interrupt Status Register and the SPW Interrupt Mask Register These register are used for masking or propagating the interrupts from the lower layer The lower layer contains three groups of interrupt registers One SpaceWire Link group One or more multiple Virtual Receive Channel Rx VC groups One or more multiple Virtual Transmit Channel TxVC groups Each lower group contains an Interrupt Status Register an Interrupt Status Set Register and an Interrupt Status Clear Register These re
262. rotocol VCTP the default Protocol ID being F016 RMAP Transfer Protocol Protocol ID being 0116 Note that this Protocol ID is reserved for RMAP even if RMAP support is turned off in the module and should never be used for e g VCTP Unknown protocols i e protocols not explicitly identified by hardware are redirected to softwre via Rx VC O Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX 131 RUAG GAISLER Aerospace Defence Technology The Virtual Channel Transfer Protocol supports one or more virtual channels A virtual channel identifier is used for identifying the corresponding virtual channel A virtual channel identifier of zero is not allowed as explained below neither are virtual channel identifiers above 7 A special case is the virtual channel RxVC 0 which is used for the reception of other transfer protocols than VCTP This includes RMAP commands and responses Received RMAP commands are either handled by a protocol handler in hardware or forwarded to virtual receive channel Rx VC 0 for further software processing Received RMAP responses are also forwarded to virtual receive channel RxVC 0 for further software processing Note that the virtual receive channel Rx VC 0 is always implemented even if no RMAP hardware handler is implemented Note that when the RMAP hardware handler is implemented the dedicated virtual transmit channel TxVC 0 is al
263. rovided that the RxEn and TrPtclSW bits are both set TrPtclS W Software support for transfer protocols is disabled RMAP commands are neither received on Rx VC 0 nor stored in memory If the RAMPEn bit is not set all RMAP commands are rejected otherwise only RMAP commands not supported in hardware are rejected RMAP response storage is unaffected by the value of this bit Unknown transfer protocols are neither received on Rx VC 0 nor stored Software support for transfer protocols is enabled If the RMAPEn bit is not set then RMAP commands supported in hardware are received on RxVC 0 and stored in memory provided that the RxEN bit is set else they are rejected All RMAP commands unsupported in hardware are received on Rx VC 0 and stored in memory provided that the RxEN bit is set else they are rejected RMAP response storage is unaffected by the value of this bit All unknown transfer protocols are received on RxVC 0 and stored in memory provided that the RxEN bit is set else they are rejected ForceUnk Incoming packets are interpreted tested and handled as defined by RxEn 1 TrPtclSW and RMAPEn All incoming packets of 4 bytes or more are handled like packets of unknown protocol i e they are received on RxVC 0 and stored in memory provided that TrPrtclISW and RxEN are set otherwise they are rejected DLA 0 255 SpaceWire Destination Logical Address DLA The DLA of any incoming packet must match the DLA fi
264. rrupt 23 20 Unused 19 CAN RxSync Synchronization message received 18 CAN TxSync Synchronization message transmitted 17 CAN IRQ Common output from interrupt handler 16 SpaceWire 1 Tick Synchronization received 15 SpaceWire 1 Interrupt Common output from interrupt handler 14 SpaceWire 0 Tick Synchronization received 13 SpaceWire 0 Interrupt Common output from interrupt handler 12 FIFO RxParity Parity error during reception 11 FIFO RxError AHB access error during reception 10 FIFO RxFull Circular reception buffer full 9 FIFO RxIrq Successful reception of data block 8 FIFO TxError AHB access error during transmission 7 FIFO TxEmpty Circular transmission buffer empty 6 FIFO TxIrq Successful transmission of data block 5 ADC DAC DAC conversion ready 4 ADC DAC ADC conversion ready 3 32 Bit Timer Timer 2 Timer expired 2 32 Bit Timer Timer 1 Timer expired 1 GPIO PULSE Pulse command completed 0 Unused Note Interrupt 17 15 and 13 are available in primary interrupt controller and should therefore Note Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG be used restrictively in the secondary interrupt controller The secondary interrupt controller uses edge detection whereas the aforementioned interrupt sources use level The interrupt handling software must thus ensure that the sources for the aforementioned interrupts do not have an additional pending interrupt when clearing the corresponding bit in the pending interrupt reg
265. rrupt assignment primary interrupt controller Table 94 shows the assignment of interrupts for the primary interrupt controller TABLE 94 Interrupt assignments primary interrupt controller Interrupt Source 15 Parallel I O 7 14 SpaceWire 1 13 SpaceWire 0 Parallel I O 6 12 CAN interface Parallel I O 5 11 DSU trace buffer 10 Second interrupt controller Parallel I O 4 Timer 2 Timer 1 Parallel I O 3 Parallel I O 2 Parallel I O 1 Parallel I O 0 UART 1 UART 2 AHB error N AJAJ Aalu oj Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER 194 13 4 2 Interrupt assignment secondary interrupt controller Table 95 shows the assignment of interrupts for the secondary interrupt controller TABLE 95 Secondary interrupt controller assignments RUAG Aerospace Defence Technology Interrupt Source Comment 31 GPIO Gpio 23 24 bit GPIO input interrupt 30 GPIO Gpio 22 24 bit GPIO input interrupt 29 GPIO Gpio 21 24 bit GPIO input interrupt 28 GPIO Gpio 20 24 bit GPIO input interrupt 27 GPIO Gpio 19 24 bit GPIO input interrupt 26 GPIO Gpio 18 24 bit GPIO input interrupt 25 GPIO Gpio 17 24 bit GPIO input interrupt 24 GPIO Gpio 16 24 bit GPIO input inte
266. rt from the write pointer and continue to the read pointer 5 5 6 AMBA AHB error An AHB error response occurring on the AMBA AHB bus while data is being stored will result in an RxError interrupt If the FifoCONF ABORT bit is set to Ob the channel causing the AHB error will retry to store the received data till successful If the FifoCONF ABORT bit is set to 1b the channel causing the AHB error will be disabled FifoRx CTRL ENABLE is cleared automatically to Ob The write pointer can be used to determine which address caused the AHB error The interface will not start any new read accesses to the FIFO Any ongoing FIFO access will be completed and the data will be stored in the local receive buffer The FifoRxSTAT ONGOING bit will be cleared When the receive channel is re enabled the reception and storage of data will resume at the position where it was disabled without losing any data 5 5 7 Enable and disable When an enabled receive channel is disabled FifoRxCTRL ENABLE 0b any ongoing data storage on the AHB bus will not be aborted and no new storage will be started If the data is stored success fully the write pointer FifoRxWR WRITE is automatically incremented Any associated interrupts will be generated The interface will not start any new read accesses to the FIFO Any ongoing FIFO access will be completed The channel can be re enabled again without the need to re configure the address size and pointers No data recep
267. rt occurred no FCT will be transmitted from the flooded node Thus the un flooded node will go to Connect ing time out return to ErrorReset and try to connect again In other words a congested link will remain congested after a link abort and will fail to connect This is the behaviour recommended by the standard Note also that the flooded node might reach the Run state since it can receive an FCT from the other node but will go to ErrorReset when the other node disconnects 10 6 11 1 1 RxFifoFlush and TxFifoFlush usage Some systems use legacy protocols where the reception order of packets is essential In these systems there is a need to flush all Tx and also maybe Rx data when a link abort occurs and partially restart the send lists after reconnection This can be accomplished by using the TxFifoFlush and RxFifoFlush SPW CODEC Configuration Register bits Note that using this flush functionality is a deviation from the recommendation in the standard When TxFifoFlush is set currently active Tx packets are flushed and all currently triggered Tx channels become un triggered Setting RxFifoFlush has the same effect on the Rx packets and RxVC channels If any Rx VC or TxVC except TxVC 0 channel was either active or triggered when the corresponding flush configuration bit was set the corresponding FlushAbort channel interrupt is issued As long as any FlushAbort interrupt is still pending either in an SPW RxVC Interrupt Status Regis
268. rupts 31 to 24 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 8 2 8 Interrupt Edge Register GpioEDGE R W TABLE 56 Interrupt Edge Register 31 24 23 16 15 0 EDGE 31 24 Reserved No effect when written to Undefined when read 23 16 EDGE Interrupt edge or level Ob level 1b edge 15 0 Reserved No effect when written to Undefined when read All bits are cleared to 0 at reset Note that only bits 23 to 16 are implemented and are mapped on interrupts 31 to 24 Note that the secondary interrupt controller uses edge detection The Interrupt Edge Register must therefore only be programmed for edge detection not for level to ensure that multiple interrupts can be detected from the same source Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 f EROFLEX RUAG GAISLER Aerospace Defence Technology 9 CAN INTERFACE 9 1 Overview The CAN controller is assumed to operate in an AMBA bus system where both the AMBA AHB bus and the APB bus are present The AMBA APB bus is used for configuration control and status han dling The AMBA AHB bus is used for retrieving and storing CAN messages in memory external to the CAN controller This memory can be located on chip as shown in the block diagram or external to the chip The CAN protocol is based on the ESA
269. ry mapped I O area can be terminated on the next rising clock edge MemBExcN I Memory exception This active low input is sampled simultaneously with the data during accesses on the memory bus If asserted a memory error will be generated FifoD 15 0 IO FIFO data FifoP 1 0 IO FIFO parity FifoRdN O FIFO read strobe FifoWrN O FIFO write strobe FifoFullN I FIFO full FifoEmpN I FIFO empty FifoHalfN I FIFO half full half empty SpwClkSre I SpaceWire transmitter clock source SpwClkMult 1 0 I Space Wire clock configuration SpwClk1OMbit 2 0 I SpaceWire clock configuration Table 96 Space Wire RTC signals Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 k RUAG EROFLEX GAISLER Aerospace Defence Technology Signal Type Description Comment SpwClkPlCnfg 2 0 I SpaceWire clock configuration SpwClkMuxSel I Space Wire clock External clock when 1 internal PLL configuration when 0 SpwDIn_P 1 0 I LVDS SpaceWire Data input positive positive SpwDIn_N 1 0 I LVDS SpaceWire Data input negative negative SpwSIn_P 1 0 I LVDS SpaceWire Strobe input positive positive SpwSIn_N 1 0 I LVDS Space Wire Strobe input negative negative SpwDOut_P 1 0 O LVDS SpaceWire Data output positive positive SpwDOut_N 1 0 O LVDS SpaceWire Data output negative negative SpwSOut_P 1 0 O LVDS SpaceWire Strobe outp
270. same SpaceWire link simultaneously Both protocols use the SpaceWire Transfer Protocol Packet Structure in which the Protocol Identifier is used for making the distinction between different protocols including VCTP and RMAP Additionally other protocols can also be supported but require processing support from the node in which the SPW2 module is embedded 10 4 3 1 SpaceWire Virtual Channel Transfer Protocol VCTP The SpaceWire Virtual Channel Transfer Protocol VCTP protocol allows transfer to one or many dedicated areas in memory The virtual channels allow multiple communication links over a single SpaceWire link The selection of the virtual channel to which the received data from the SpaceWire link belong is made using the Virtual Channel Identifier carried in the packet Each virtual receiver channel has a separately programmable memory area to which received data are stored This area can be located anywhere in memory The SpaceWire Module performs direct memory accesses to write received data to a memory area 10 4 3 2 Remote Memory Access Protocol RMAP The Remote Memory Access Protocol RMAP protocol is used for writing to and reading from memory registers FIFO memory mailboxes etc in a destination node on a SpaceWire network Input output registers control status registers are assumed to be memory mapped and accessed as memory All read and write operations defined in the RMAP protocol are posted operations i e the
271. sed for the monitoring of the FIFO and DMA status The receive channel is programmed in terms of a base address and size of the circular receive buffer The incoming data are stored in the circular receive buffer The interface automatically indicates with a write address pointer register the location of the last stored byte A read address pointer register is used by the system to indicate the last byte read from the circular receive buffer An interrupt address pointer register is used by the system to specify a location in the circular receive buffer to which a data write should cause an interrupt to be generated Write accesses are performed as incremental bursts except when close to the location specified by the interrupt pointer register at which point the last bytes might be stored by means of single accesses Data transferred via the FIFO interface can be either 8 or 16 bit wide The handling of the receive channel is however the same All transfers performed by the AMBA AHB master are 32 bit word based No byte or half word transfers are performed To handle the 8 and 16 bit FIFO data width a 32 bit write access might carry less than four valid bytes In such a case the remaining bytes will all be zero When additional data are received from the FIFO interface the previously stored bytes will be re written together with the newly received bytes to form the 32 bit data In this way the previously written bytes are never overwritten The a
272. served No effect when written to Undefined when read 4 Overrun OV indicates that one or more character have been lost due to overrun 5 Reserved No effect when written to Undefined when read 6 Framing error FE indicates that a framing error was detected 31 7 Reserved No effect when written to Undefined when read 3 5 3 4 Baud rate generation The UART contains a 18 bit down counting scaler to generate the desired baud rate The scaler is clocked by the system clock and generates a UART tick each time it underflows The scaler is reloaded with the value of the UART scaler reload register after each underflow The resulting UART tick frequency should be 8 times the desired baud rate If not programmed by software the baud rate will be automatically be discovered This is done by searching for the shortest period between two falling edges of the received data corresponding to two bit periods When three identical two bit periods has been found the corresponding scaler reload value is latched into the reload register and the BL bit is set in the UART control register If the BL bit is reset by software the baud rate discovery process is restarted The baud rate discovery is also restarted when a break or framing error is detected by the receiver allowing to change to baudrate from the external transmitter For proper baudrate detection the value 0x55 should be transmitted to the receiver after reset or after sending br
273. ses are discarded All unknown transfer protocols are discarded This ensures that no congestion occurs on the Space Wire link The virtual receive channel is enabled If the RMAPEn bit is not set then RMAP commands supported in hardware are received on RxVC 0 and stored in memory provided that the TrPtclSW bit is set else they are rejected All RMAP commands unsupported in hardware are received on Rx VC 0 and stored in memory provided that the TrPtclSW bit is set else they are rejected All RMAP responses are received on Rx VC 0 and stored in memory All unknown transfer protocols are received on RxVC 0 and stored in memory provided that the TrPtclS W bit is set else they are rejected WordAlign No padding takes place and a packet will start at the byte address following the previous packet The end of each packet is padded up to the closest 32 bit word boundary Padding is done with arbitrary content The first byte of a packet will thus always be aligned to a 32 bit word address RMAP hardware support is disabled RMAP commands are received on Rx VC 0 and stored in memory provided hat the RxEn and TrPtclSW bits are both set else they are rejected RMAP hardware support is enabled as well as RMAP command identification RMAP commands supported in hardware are not received on Rx VC 0 and thus not stored in memory but are handled in hardware RMAP commands unsupported in hardware are received on RxVC 0 and stored in memory p
274. sion 2 4 o RUAG Aerospace Defence Technology AEROFLEX GAISLER 13 MEMORY AND REGISTER MAP INTERRUPT ASSIGNMENT 13 1 Addressing information The SpaceWire RTC global memory map is shown in the table below The global address map is defined by the addresses on the internal AMBA AHB bus Address range Size Mapping Module 0x00000000 Ox 1FFFFFFF 512M Prom Memory controller 0x20000000 0x3FFFFFFF 512M Memory bus I O 0x40000000 0x7FFFFFFF 1G SRAM 0x80000000 Ox800FEFFF On chip registers APB controller bridge Ox800FFO00 Ox800FF1FF 512 Plug and play information 0x90000000 0x9FFFFFFF 256M Debug support unit DSU 0xA0000000 Ox AFFFFFFF 64K On chip RAM On chip RAM OxFFFFFO00 OxFFFFFFFF 4K Plug and play information AHB controller Table 79 Global address map AMBA AHB bus The SpaceWire RTC effective memory map is shown in the table below The address map is defined by the addresses on the internal AMBA AHB bus The address ranges shown correspond to a system equipped with the supported maximum number of memory devices each with the supported maximum size The constraining of the addressable memory is made by the width of the external memory address bus Address range Size Mapping Cacheable Module 0x00000000 OxOOFFFFFF 16M _ Prom Yes Memory controller 0x20000000 0x207FFFFF 8M Memory bus I O No 0x40000000 0x41 FFFFFF 32M SRAM Yes 0x
275. so implemented This virtual transmit channel is used for automatic RMAP response generation and cannot be accessed by the software In the transmit bandwidth arbitration TxVC 0 has priority over any other TxVC channel TxVC 0 can however not starve the other TxVC channels since there is always time to transmit on the other channels while an RMAP command is being received 10 6 3 1 Enabling of protocol support Enabling of the Virtual Channel Transfer Protocol VCTP support is performed individually per virtual channel and is described in more detail in 10 6 5 1 The only input used for the identification processes is whether a virtual receive channel is implemented and if it is enabled by software Enabling of the Remote Memory Access Protocol RMAP support is performed in two ways Enabling of hardware supported RMAP Enabling of software supported RMAP Enabling of RMAP command support in hardware is done by means of the SPW Rx VC Config Register 0 RMAPEn bit This enables both hardware execution of RMAP commands and hardware generation of the corresponding RMAP responses The reset value for this bit is RMAP enabled for both modules It is thus possible to disable hardware handling of RMAP commands during operation Enabling of RMAP command and response support in software is done by means of the SPW RxVC Config Register 0 When enabled all RMAP commands that are not handled by the RMAP command support in hardware see 10 6
276. source does not wait for an acknowledgement or reply to be received This means that many read and write accesses can be outstanding at any time It also means that there is no timeout mechanism implemented in RMAP for missing acknowledgements or replies If an acknowledgement or reply timeout mechanism is required it must be implemented in the source user application The RMAP protocol is realised in three ways in the SpaceWire Module with hardware support with software support or with both The hardware implements a subset of the RMAP commands A detailed list of command constraints is provided in 10 6 4 1 and 10 6 4 2 Automatic RMAP responses are generated to RMAP commands that are implemented in hardware A received packet is not stored in memory for RMAP commands that are executed in hardware Commands not supported by hardware can optionally be relayed to software for further processing If no hardware support is required all commands can be relayed to software for processing Commands are relayed to software using a dedicated virtual receive channel similar to what has been described for the VCTP protocol Responses can be generated by software using a virtual transmit channel as described in 10 4 2 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX M1 RUAG GAISLER Aerospace Defence Technology Any received RMAP responses are also relayed to software in the same way as R
277. space Defence Technology Signal Type Description Comment MemCB 7 0 IO Memory interface checkbits MemCB 6 0 carries the EDAC checkbits MemCB 7 takes the value of TB 7 in the error control register The processor only drive MemCB 7 0 during write cycles to areas programmed to be EDAC protected MemCsN 3 0 O SRAM chip select These active low signals provide an individual output enable for each SRAM bank MemOeN 3 0 O SRAM output enable These active low outputs provide the chip select signals for each SRAM bank MemWrN 3 0 O SRAM byte write strobe These active low outputs provide individual write strobes for each byte lane MemWrN 0 controls MemD 31 24 MemWrN 1 controls MemD 23 16 etc RomCsN 1 0 O PROM chip select These active low outputs provide the chip select signal for the PROM area RomCsN 0 is asserted when the lower half of the PROM area is accessed 0 0x 10000000 while RomCsN 1 is asserted for the upper half IoCsN O T O area chip select This active low output is the chip select signal for the memory mapped I O area IoOeN O T O area output enable This active low output is asserted during read cycles on the memory bus ToRead O I O area read This active high output is asserted during read cycles on the memory bus IoWrN O T O area write This active low output provides a write strobe during write cycles on the memory bus IoBrdyN I T O area ready This active low input indicates that the access to a memo
278. sponding bit s in the interrupt pending register 3 3 3 3 Interrupt assignment Table 8 shows the assignment of interrupts for the secondary interrupt controller TABLE 8 Secondary interrupt controller assignments Interrupt Source 31 GPIO Gpio 23 24 bit GPIO input interrupt 30 GPIO Gpio 22 24 bit GPIO input interrupt 29 GPIO Gpio 21 24 bit GPIO input interrupt 28 GPIO Gpio 20 24 bit GPIO input interrupt Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER TABLE 8 Secondary interrupt controller assignments RUAG Aerospace Defence Technology Interrupt Source 27 GPIO Gpio 19 24 bit GPIO input interrupt 26 GPIO Gpio 18 24 bit GPIO input interrupt 25 GPIO Gpio 17 24 bit GPIO input interrupt 24 GPIO Gpio 16 24 bit GPIO input interrupt 23 20 Unused 19 CAN RxSync Synchronization message received 18 CAN TxSync Synchronization message transmitted 17 CAN IRQ Common output from interrupt handler 16 SpaceWire 1 Tick Synchronization received 15 SpaceWire 1 Interrupt Common output from interrupt handler 14 SpaceWire 0 Tick Synchronization received 13 SpaceWire 0 Interrupt Common output from interrupt handler 12 FIFO RxParity Parity error during reception 11 FIFO RxError AHB access error during reception 10 FIFO RxFul
279. ss space divided according to table 10 TABLE 10 Memory controller address map Address range Size Mapping 0x00000000 Ox LFFFFFFF 512M Prom 0x20000000 0x3 FFFFFFF 512M I O 0x40000000 0x7FFFFFFF 1G SRAM Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 3 4 3 PROM access Accesses to PROM have the same timing as RAM accesses the differences being that PROM cycles can have up to 30 waitstates datal data2 lead out MemA RomCsN IoOeN MemD Figure 35 Prom read cycle Two PROM chip select signals are provided RomCsN 1 0 RomCsN 0 is asserted when the lower half 0 0x 10000000 of the PROM area as addressed while RomCsN 1 is asserted for the upper half 0x 10000000 0x20000000 3 4 4 Memory mapped I O Accesses to I O have similar timing to ROM RAM accesses the differences being that a additional waitstates can be inserted by de asserting the IoBrdyN signal The I O select signal IoCsN is delayed one clock to provide stable address before oCsN is asserted lead in data lead out wa ar 7 IoCsN oo T EE A S T ToOeN ooo o y T MemD IoBrdyN T AA T Figure 36 I O read cycle 3 4 5 SRAM access The SRAM area can be up to 32 MByte divided on up to four RAM banks The size of banks 1 4 MemCsN 3 0 is programmed in the RAM bank s
280. ssor into debug mode If cleared the processor will resume execution 8 Break on DSU breakpoint BD if set will force the processor to debug mode when an DSU breakpoint is hit 9 Break on trap BX if set will force the processor into debug mode when any trap occurs 10 Break on error traps BZ if set will force the processor into debug mode on all except the following traps priviledged_instruction fpu_disabled window_overflow window_underflow asynchronous_interrupt ticc_trap 11 Delay counter enable DE if set the trace buffer delay counter will decrement for each stored trace This bit is set automatically when an DSU breakpoint is hit and the delay counter is not equal to zero 12 Debug mode DM Indicates when the processor has entered debug mode read only 13 EB value of the external LeonDsuBre signal read only 14 EE value of the external LeonDsuEn signal read only Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX j RUAG GAISLER Aerospace Defence Technology 15 Processor error mode PE returns 1 on read when processor is in error mode else 0 16 Single step SS if set the processor will execute one instruction and the return to debug mode 17 Link response LR is set the DSU communication link will send a response word after AHB transfer 18 Debug mode response DR if set the DSU communication link will send
281. ster 0x80080200 Transmit Channel Address Register 0x80080204 Transmit Channel Size Register 0x80080208 Transmit Channel Write Register 0x8008020C Transmit Channel Read Register 0x80080210 Transmit Channel Interrupt Register 0x80080214 Receive Channel Control Register 0x80080300 Receive Channel Address Register 0x80080304 Receive Channel Size Register 0x80080308 Receive Channel Write Register 0x8008030C Receive Channel Read Register 0x800803 10 Receive Channel Interrupt Register 0x800803 14 Receive Channel Mask Register 0x80080318 Receive Channel Code Register 0x8008031C Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER 191 13 3 8 SpaceWire Link Interface 0 TABLE 92 SpaceWire Link 0 registers RUAG Aerospace Defence Technology Address Register 0x80060000 SPW Pending Interrupt Masked Status Register 0x80060008 SPW Pending Interrupt Status Register 0x80060010 SPW Interrupt Mask Register 0x80060014 SPW Link Interrupt Status Register 0x80060018 SPW Link Interrupt Status Set Register 0x8006001C SPW Link Interrupt Status Clear Register 0x80060020 SPW CODEC Configuration Register 0x80060024 SPW Clock Division Register 0x80060028 SPW RMAP Destination Key Register 0x8006002C SPW Transmit Time Code Register
282. ster write where the bits that are set in the provided parameter is cleared in the register bits that are cleared in the provided parameter is unaffected in the register Arm A Register write where the bits that are set in the provided parameter is set ready to receive a new value once executed Execute E Register write where the register bits that have previously been armed are updated according to the provided parameter Trigger T Register write where hardware processing is triggered activated no parameter or fixed parameter 10 5 7 5 Signals Assert To put a signal into its active state A signal is asserted when in its active state Deassert To put a signal into its inactive state A signal is deasserted when in its inactive state 10 5 7 6 Direct memory access DMA Channel A unit for accessing memory DMA Error Signal to DMA Channel for failing memory access DMA Read A transfer of data toa DMA channel from a DMA controller e g read data from memory DMA Write A transfer of data from a DMA channel to a DMA controller e g write data to memory 10 5 7 7 SPW2 Specific Active Virtual receive or transmit channel RxVC or TxVC is RxVC currently receiving or transmitting data TxVC Inactive No data is currently being received or transmitted on virtual receive RxVC J or transmit channel Rx VC or TxVC TxVC Early EOP EOP has been received after less data than expected from the RMAP command
283. t Note that only the part of ADData 15 0 not used by the ADC can be used as general purpose input output see ADCONF ADCDW Note that only bits 15 to 0 are implemented 6 3 9 Data Output Register ADDOUT R W TABLE 45 Data Output Register 31 16 15 0 DOUT 31 16 RESERVED No affect when written to Undefined when read 15 0 DOUT Output data ADData 15 0 All bits are cleared to 0 at reset Note that only the part of ADData 15 0 neither used by the DAC nor the ADC can be used as gen eral purpose input output see ADCONKDACDW and ADCONF ADCDW Note that only bits 15 to 0 are implemented 6 3 10 Data Register ADDDIR R W TABLE 46 Data Direction Register 31 16 15 0 DDIR 31 16 RESERVED No affect when written to Undefined when read 15 0 DDIR Direction ADData 15 0 Ob input high impedance 1b output driven All bits are cleared to 0 at reset Note that only the part of ADData 15 0 not used by the DAC can be used as general purpose input output see ADCONF DACDW Note that only bits 15 to 0 are implemented Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 7 32 BIT TIMERS 7 1 Overview 7 2 7 3 The Modular Timer Unit implements one prescaler and two decrementing timers The unit is capable of asserting interrupt on when timer s underflow Interrupt is conf
284. t Cyclic Redundancy Check CRC used to confirm that the data is correct before being written in a verified write command or was correctly transferred in a non verified write command or read reply The data CRC starts with the byte after the header CRC and covers all the data bytes The same CRC encoding is used as for the header CRC Note that for a zero length data field the CRC is the starting value i e 0016 EOP character is the End Of Packet marker of the SpaceWire packet EEP character is the Error End of Packet marker of an erroneous SpaceWire packet Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX T RUAG GAISLER Aerospace Defence Technology 10 5 9 2 SpaceWire Packet Structure A SpaceWire packet consists of a destination address path address logical address a cargo and an end of packet EOP or EEP marker lt destination address gt lt cargo gt lt end of packet gt where e The destination address consists of a list of one or more bytes called destination identifiers lt destination address gt lt id 0 gt lt id 1 gt lt id N 1 gt e The cargo contains zero or more bytes e The end of packet is either an EOP indicating a normal termination of a packet or an EEP indicating a packet in which an error has occurred Note that SpaceWire packets without any cargo containing only a single EOP are possible to transmit with the SpaceWire SPW2
285. t Status Set Register SPW_RxISSR SPW RxVC Interrupt Status Clear Register SPW_RxISCR QAR 31 6 5 4 3 2 1 0 CRC Flush Dma Rx Cnt Rx Data Abort Wr EEP Trig EOB Err Err 0 0 0 0 0 0 LSB Function RxVC interrupt status set and clear registers Timing An RxVC channel may issue interrupts when it is active or triggered The RxEOB CntTrig RxEEP and CRCDataErr interrupts are issued after the last access to memory The DmaWeErr interrupt is issued directly after an error has been detected on the internal bus The FlushAbort interrupt is issued directly after the flush has been commanded Constraints CRCDataErr is only available for RxVC 0 Field Description RxEOB CntTrig The configured number of packets SPW _RxVC Packet Counter Register PktCntTrig has been received and stored in memory Can only occur if the configured number of packets has been set higher than zero RxEEP An EEP has been received Error when writing to memory i e access error on internal bus e g illegal address The remainder of the packet is discarded until EOP or EEP The interrupt is issued immediately FlushAbort An SPW CODEC Configuration Register RxFifoFlush was commanded while the channel was active or triggered The remainder of the packet is discarded and the channel untriggered CRCDataErr A CRC8 checksum error has been detected on Rx VC 0 either in the
286. t clear register It must then also clear interrupt 10 in the primary interrupt controller Testing of interrupts can be done by writing directly to the interrupt pending registers Bits written with 1 will be set while bits written with 0 will keep their previous value After reset the interrupt mask register is set to all zeros while the remaining control registers are undefined Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX P RUAG GAISLER Aerospace Defence Technology 3 3 3 2 Control registers The operation of the secondary interrupt controller is programmed through the following registers 31 0 IMASK 31 0 Figure 13 Secondary interrupt mask register 31 0 Interrupt mask indicates whether an interrupt is masked IMASK n 0 or enabled IMASK n 1 IPEND 31 0 Figure 14 Secondary interrupt pending register 31 0 Interrupt pending indicates whether an interrupt is pending IPEND n 1 31 5 4 0 RESERVED I IRL 4 0 vu Figure 15 Secondary interrupt status register 4 0 Interrupt request level indicates the highest unmasked pending interrupt 5 Interrupt pending if set then IRL is valid If cleared no unmasked interrupt is pending 31 0 ICLEAR 31 0 Figure 16 Secondary interrupt clear register 31 0 Interrupt clear if written with a 1 will clear the corre
287. tart of the CODEC 1 Auto start the CODEC provided that the LinkDis bit is cleared The CODEC will wait in state Ready until the first NULL character is received See 10 6 2 RxFifoFlush Rx flush mechanism off 1 All data in Rx pipe FIFOs etc is flushed and all active and or triggered RxVC are aborted TxFifoFlush Tx flush mechanism off 1 All data in Tx pipe FIFOs etc is flushed and all active and or Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX ie RUAG GAISLER Aerospace Defence Technology triggered TxVC are aborted SPW Clock Division Register SPW_CDR R W 31 6 5 0 TxNomDiv XXi16 MSB LSB Function This register configures the transmitter baud rate Timing The data rate during a link connection is the link start up rate Constraints Field Description TxNomDiv The nominal transmitter bit rate is SowClk 0 5 TxNomDiv 1 Double Data Rate The reset value XX of the field matches the link start up data rate as configured with the configuration inputs SpwClklOMBit and SpwClkMul The reset value will be TxNomDiv 2 factorgpweikiompit factorspwcikmul 1 SPW RMAP Destination Key Register SPW_RDKR R W 31 8 7 0 z DestKey 0 MSB LSB Function This register configures the RMAP Destination Key
288. tate according to the following X0 disabled 01 frozen 11 enabled Set to 00 at reset If the DF or IF bit is set the corresponding cache will be frozen when an asynchronous interrupt is taken This can be beneficial in real time system to allow a more accurate calculation of worst case execution time for a code segment The execution of the interrupt handler will not evict any cache lines and when control is returned to the interrupted task the cache state is identical to what it was before the interrupt If a cache has been frozen by an interrupt it can only be enabled again by enabling it in the CCR This is typically done at the end of the interrupt handler before control is returned to the interrupted task On chip peripherals 3 3 1 On chip registers A number of system support functions are provided directly on chip The functions are controlled through registers mapped APB bus according to the following table TABLE 6 On chip registers Address Register Address 0x80000000 Memory configuration register 1 0x800000B0 Secondary interrupt mask register 0x80000004 Memory configuration register 2 0x800000B4 Secondary interrupt pending regis ter 0x80000008 Memory configuration register 3 0x800000B8 Secondary interrupt status register 0x8000000C AHB Failing address register Ox800000B8 Secondary interrupt clear register 0x80000010 AHB status register 0x80000014 Cache control re
289. te where the Tx remains reset until a NULL token is received from the node at the other end of the link Thus it is possible for the SpaceWire link to autonomously start up after reset and to allow RMAP commands to be executed without the need for any interaction from software in the destination node This also means that for the start up to proceed to the Run state the other node must be set in the LinkStart mode in which the transition from Ready to Started takes place without waiting for a NULL token Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX m RUAG GAISLER Aerospace Defence Technology Reset Rx error or got FCT or got N char or got Time Code 000 ErrorReset Reset Tx Reset Rx Rx error or credit erroror A LinkDis 7 101 Run Send any character or control code Enable Rx 001 ErrorWait Reset Tx Enable Rx After 6 4 us Rx error or R got FCT or got N char or got Time Code or Rx error or got N char or Got FCT got Time Code or After 12 8 us after 12 8 us Rx error of 3 after 12 8 us got FCT or S 100 got N char or 010 Connecting got Time Code Ready Send FCTs or NULLs Enable Rx Reset Tx Enable Rx 011 Started Send NULLs Enable Rx lot LinkDis and LinkStart or AutoStart and got NULL Got NULL
290. ter or an SPW TxVC Interrupt Status Register no virtual channel Rx VC or TxVC except TxVC 0 can be re triggered Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX 154 RUAG GAISLER Aerospace Defence Technology Note that this trigger blocking mechanism does not apply to hardware supported RMAP command handling once the flush configuration bits are cleared hardware supported commands will be handled and automatically generated responses will be transmitted even if there are still FlushAbort interrupts pending Since the TxFifoFlush and RxFifoFlush causes an indiscriminate discarding of data it shall only be used when the link is disconnected and should always continue until all data has been flushed from the system This shall be accomplished in the following manner 1 Ensure that the link will not connect during the flushing by one of these methods Disconnect the link by setting SPW CODEC Configuration Register LinkDis or Directly after initial connection clear the LinkStart and AutoStart bits in SPW CODEC Configuration Register thus blocking automatic reconnection 2 Await the LinkAbort interrupt 3 Set the TxFifoFlush and or RxFifoFlush bit in SPW CODEC Configuration Register As a side effect this will trigger the FlushAbort interrupts of the corresponding active or triggered channels 4 Wait until the flushed data pipe has been complet
291. ter enabled LeonPio 10 RXD2 Input UART 2 receiver data LeonPio 9 RTS2 Output UART2 request to send UART2 flow control enabled LeonPio 8 CTS2 Input UART 2 clear to send LeonPio 3 UART clock Input Use as alternative UART clock LeonPio 2 Prom EDAC Input Defines prom edac at boot time LeonPio 1 0 Prom width Input Defines prom width at boot time 3 3 7 LEON configuration register Since LEON is extensively configurable the LEON configuration register read only is used to indicate which options were enabled in the design For each option present the corresponding register bit is hardwired to 1 Figure 32 shows the layout of the register 31 30 29 28 27 26 25 24 20 19 17 16 15 14 12 11 10 9 8 7 65 4 3 2 10 NWINDOWS ICSZ ILSZ DCSZ DLSZ UMAC SMAC inst UDIV SDIV inst Number of watchpoints SMUL UMUL inst SDRAM controller Watchdog present DSU present Memory status reg FPU PCI core Write protection Figure 32 LEON configuration register 31 Reserved No effect when written to Undefined when read Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 30 Debug support unit O disabled 1 present 29 SDRAM controller present O disabled 1 present 8 26 Number of implemented
292. that it is not possible to receive a CAN message while transmitting one AMBA Redundant AHB bus CAN bus HurriCANe CAN Controller Nominal Controller CAN ban AMBA APB bus Figure 75 Block diagram of the internal structure of the GRHCAN 9 1 1 Function The core implements the following functions e CAN protocol e Message transmission e Message filtering and reception e SYNC message reception e Status and monitoring e Interrupt generation e Redundancy selection Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER 9 2 9 3 Aerospace Defence Technology 9 1 2 Interfaces The core provides the following external and internal interfaces e CAN interface e AMBA AHB master interface with sideband signals as per GRLIB including e cacheability information e interrupt bus configuration information diagnostic information e AMBA APB slave interface with sideband signals as per GRLIB including interrupt bus configuration information diagnostic information 9 1 3 Hierarchy The CAN controller core can be partitioned in the following hierarchical elements e ESA HurriCANe CAN Controller e Redundancy Multiplexer De multiplexer e Direct Memory Access controller e AMBA APB slave e AMBA AHB master Interface The external interface towards the CAN bus features two redundant pairs of transmit output
293. the automatic response generation mechanism can only handle one response at a time Thus if a second RMAP that requires an automatic response is received while an older automatic response is being transmitted then the reception mechanism will stall until the older response is finished In other words if multiple hardware supported RMAP commands that generate automatic responses are received in quick succession this might cause congestion on the Rx 10 6 11 5 RMAP command and response reception in software When transfer protocol support is enabled for RxVC 0 using the SPW RxVC Config Register 0 any RMAP command not handled by hardware as described in 10 6 11 4 and any RMAP response will be stored in the memory buffer allocated to this channel Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX o RUAG GAISLER Aerospace Defence Technology The reception handling is similar to what has been described for the Virtual Receive Channels RxVC in 10 6 11 2 The only differences are that the first four bytes of a received packet are not deleted and that the last byte in a packet containing the RMAP data CRC checksum is deleted before the packet is saved to memory As an additional service an interrupt is issued and the channel is un triggered if the combined CRC as calculated over the RMAP header the RMAP header CRC checksum byte and the RMAP data field does not match the re
294. the concept a step further one could envisage applications in which the SpaceWire RTC device actually replaces the processor in an ICU The integer processing capacity of the LEON2 pro cessor in the SpaceWire RTC device is in par with what can be expected from current monolithic pro cessor devices This provides for savings in terms of power and board area since a single device with external memory is sufficient to form the core of an ICU The main application of the SpaceWire RTC device is however in instruments or individual experi ments of the payload It provides an abundance of interfaces each with a high degree of programma bility and configurability It is able to acquire analogue and digital data generated by connected peripherals and to generate discrete commands towards the same peripherals The SpaceWire RTC device can be operated stand alone or with a number of external devices such as SRAM PROM and FIFO memories ADC and DAC converters The device can be managed locally by the on chip processor or remotely via its SpaceWire link interfaces SpaceWire RTC device can operate as a single chip system with software being uploaded to its on chip memory via the SpaceWire link interface forming a compact solution for remotely controlled applications Or it can operate in a full size system with software being decompressed from local PROM and executed from multiple fast and wide SRAM memory banks Copyright 2006 2007 2008 2009 A
295. the following parameters e base address e buffer size e write pointer e read pointer The transmit channel can be enabled or disabled 5 4 1 Circular buffer The transmit channel operates on a circular buffer located in memory external to the FIFO controller The circular buffer can also be used as a straight buffer The buffer memory is accessed via the AMBA AHB master interface The size of the buffer is defined by the FifoTxSIZE SIZE field specifying the number of 64 byte blocks that fit in the buffer E g FifoTxSIZE SIZE 1 means 64 bytes fit in the buffer Note however that it is not possible to fill the buffer completely leaving at least one word in the buffer empty This is to simplify wrap around condition checking E g FifoTxSIZE SIZE 1 means that 60 bytes fit in the buffer at any given time 5 4 2 Write and read pointers The write pointer FifoTxWR WRITE indicates the position 1 of the last byte written to the buffer The write pointer operates on number of bytes not on absolute or relative addresses The read pointer FifoTxRD READ indicates the position 1 of the last byte read from the buffer The read pointer operates on number of bytes not on absolute or relative addresses The difference between the write and the read pointers is the number of bytes available in the buffer for transmission The difference is calculated using the buffer size specified by the FifoTxSIZE SIZE field taking wrap around effec
296. the result of a successful data reception after the FifoRxWR WRITE pointer has been incremented 5 6 Operation 5 6 1 Global reset and enable When the FifoCTRL RESET bit is set to 1b a reset of the core is performed The reset clears all the register fields to their default values Any ongoing data transfers will be aborted 5 6 2 Interrupt Seven interrupts are implemented by the FIFO interface Name Description TxIrq Successful transmission of block of data TxEmpty Circular transmission buffer empty TxError AMBA AHB access error during transmission RxIrq Successful reception of block of data RxFull Circular reception buffer full RxError AMBA AHB access error during reception RxParity Parity error during reception 5 6 3 Vendor and device id The module has vendor id 0x01 Gaisler Research and device id 0x35 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER 5 7 Registers RUAG Aerospace Defence Technology The GRFIFO is programmed through registers mapped into APB address space Any blank register is considered as reserved and has no effect when writen to and returns undefined data when read Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG TABLE 16 GRFIFO registers Register Address Configuration Register 0x80050000 Control Register 0x80050008 Transmit Channel Control
297. tion is performed while the channel is not enabled The progress of the any ongoing access can be observed via the FifoRxSTAT ONGOING bit Note that the there might be data left in the local store buffer in the FIFO controller This can be observed via the FifoRxSTAT RxByteCntr field The data will not be lost if the channel is not reconfigured before re enabled Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology To empty this data from the local store buffer to the external memory the channel needs to be ren abled By setting the FifoRxIRQ IRQ field to match the value of the FifoRxWR WRITE field plus the value of the FifoRxSTAT RxByteCntr field an emptying to the external memory is forced of any data temporarily stored in the local store buffer Note however that additional data could be received in the local store buffer when the channel is re enabled The FifoRxSTAT ONGOING must be 0b before the channel can be re configured safely i e changing address size or read write pointers 5 5 8 Interrupts During reception several interrupts can be generated e RxFull Successful reception of all data possible to store in buffer e RxIrq Successful reception of a predefined number of data e RxError AHB access error during reception e RxParity Parity error during reception The RxFull and RxIrq interrupts are only generated as
298. to Rx VC 0 the Destination Logic Address field is used for all communication to the SpaceWire SPW2 Module 10 6 10 3 SpaceWire Virtual Transfer Protocol configuration The SpaceWire SPW2 Module implements the SpaceWire Virtual Channel Transfer Protocol VCTP The Protocol Identifier of this protocol is configured using the SPW VC Transfer Protocol ID Register The default reset value is such that it falls within the range of Protocol Identifiers available for general use as defined in RMAPID Each virtual receive channel RxVC can be configured individually whether received packets should be stored contiguously in memory or whether the end of each packet is to be padded up to the closest 32 bit word boundary Padding is done with unknown arbitrary content The configuration is done in the SPW RxVC Config Register 10 6 10 4 RMAP hardware support configuration The SpaceWire SPW2 Module implements hardware support for the reception and execution of Remote Memory Access Protocol RMAP commands The hardware support is enabled and disabled using the SPW RxVC Config Register 0 Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX 15 RUAG GAISLER Aerospace Defence Technology The RMAP protocol provides a Destination Key in the RMAP command header that must match that of the receiving node before the command is executed The destination key for the command
299. to resources in the node via the SpaceWire link The SpaceWire SPW2 Module implements the higher level transfer protocols whereas the SpaceWire link itself is implemented by the encapsulated University of Dundee SpaceWire CODEC Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX 11 RUAG GAISLER Aerospace Defence Technology Data to be sent are read by the SpaceWire Module from memory via direct memory access An AMBA AHB master dedicated to transmission performs this over the internal AMBA AHB bus Data are then temporarily stored in a TxFIFO when forwarded to the SpaceWire CODEC for transmission over the link Multiple Virtual Transmit Channels TxVC can be used each with its private send list stored in memory from which data are read All TxVC share the same link Round robin arbitration between the TxVC is performed to ensure fair bandwidth allocation between the channels The arbitration is performed for each packet sent Data received over the link by the SpaceWire CODEC are temporarily stored in an RxFIFO Data are then stored to memory by the SpaceWire Module via direct memory access An AHB master dedicated to reception performs this over the internal AMBA AHB bus Multiple Virtual Receive Channels RxVC can be used each with its private memory area to which data are written All RxVC share the same link The SpaceWire Module implements hardware support for the R
300. ts making up the cache offset and the least significant bits of the address bits making up the address tag Similarly the data sub blocks may be read by executing an LDA instruction with ASI OxD for instruction cache data and ASI OxF for data cache data The sub block to be read in the indexed cache line and set is selected by A 4 2 The tags can be directly written by executing a STA instruction with ASI 0xC for the instruction cache tags and ASI OxE for the data cache tags The cache line and set are indexed Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology by the address bits making up the cache offset and the least significant bits of the address bits making up the address tag D 31 10 is written into the ATAG field see above and the valid bits are written with the D 7 0 of the write data Bit D 9 is written into the LRR bit if enabled and D 8 is written into the lock bit if enabled The data sub blocks can be directly written by executing a STA instruction with ASI 0xD for the instruction cache data and ASI 0xF for the data cache data The sub block to be read in the indexed cache line and set is selected by A 4 2 Note that diagnostic access to the cache is not possible during a FLUSH operation and will cause a data exception trap 0x09 if attempted 3 2 6 Cache parity protection The caches are provided with tw
301. ts of the circular buffer into account Examples e There are 2 bytes available for transmit when FifoTxSIZE SIZE 1 FifoTxWR WRITE 2 and FifoTxRD READ 0 e There are 2 bytes available for transmit when FifoTxSIZE SIZE 1 FifoTxWR WRITE 0 and FifoTxRD READ 62 e There are 2 bytes available for transmit when FifoTxSIZE SIZE 1 FifoTxWR WRITE 1 and FifoTxRD READ 63 e There are 2 bytes available for transmit when FifoTxSIZE SIZE 1 FifoTxWR WRITE 5 and FifoTxRD READ 3 When a byte has been successfully written to the FIFO the read pointer FifoTxRD READ is auto matically incremented taking wrap around effects of the circular buffer into account Whenever the write pointer FifoTxWR WRITE and read pointer FifoTxRD READ are equal there are no bytes available for transmission 5 4 3 Location The location of the circular buffer is defined by a base address FifoTxADDR ADDR which is an absolute address The location of a circular buffer is aligned on a 1kbyte address boundary 5 4 4 Transmission procedure When the channel is enabled FifoTxCTRL ENABLE 1 as soon as there is a difference between the write and read pointer a transmission will be started Note that the channel should not be enabled if a potential difference between the write and read pointers could be created to avoid the data transmis sion to start prematurely Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version
302. tten Note that for all TxVC except TxVC 0 the channel will not be triggered in the case all FlushAbort interrupt bits have not been cleared SPW TxVC Interrupt Status Register SPW_TxISR SPW TxVC Interrupt Status Set Register SPW_TxISSR SPW TxVC Interrupt Status Clear Register SPW_TxISCR 31 4 3 2 1 0 Flush Dma Tx Abort Rd EOB QANUN Err 0 0 0 LSB Function TxVC interrupt status set and clear registers No interrupts are ever issued in TxVC O Timing A TxVC channel may issue interrupts when it is active or triggered The TxEOB interrupt is issued after the last access to memory The DmaRdErr interrupt is issued directly after an error has been detected on the internal bus The FlushAbort interrupt is issued directly after the flush has been commanded Constraints For TxVC 0 writes to these registers have no effect Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX Is RUAG GAISLER Aerospace Defence Technology Field Description TxEOB All messages transmitted the send list has been completed DmaRdErr Error when reading from memory i e access error on internal bus e g illegal address An EEP is inserted and the ongoing send list is stopped The atomic send list entry handling is released allowing the TxVC arbiter to reassign another channel The interrupt is issued
303. uffer There is always one word position in buffer unused Soft ware is responsible for not over writing the buffer on wrap around i e setting WRITE READ Note that the LSB may be ignored for 16 bit wide FIFO devices The field is implemented as relative to the buffer base address scaled with the SIZE field 5 7 8 Transmit Channel Read Register FifoTxRD R W TABLE 24 Transmit Channel Read Register 31 16 15 0 READ 31 16 RESERVED No affect when written to Undefined when read 15 0 READ Pointer to last read byte 1 All bits are cleared to 0 at reset The READ field is written to automatically when a transfer has been completed successfully indicat ing the position 1 of the last byte transmitted Note that the READ field can be used to read out the progress of a transfer Note that the READ field can be written to in order to set up the starting point of a transfer This should only be done while the transmit channel is not enabled Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology Note that the READ field can be automatically incremented even if the transmit channel has been dis abled since the last requested transfer is not aborted until completed Note that the LSB may be ignored for 16 bit wide FIFO devices The field is implemented as relative to the buffer base address scaled with the SIZ
304. un trigger a virtual receive channel in mid packet the complete SpaceWire link needs to be disconnected and the Rx flushed using the SPW CODEC Configuration Register 10 6 11 3 Virtual Transmit Channels TxVC The SpaceWire SPW2 Module implements zero or more not counting Tx VC 0 which is always present Virtual Transmit Channels TxVC To setup transmission on Tx VC the following steps need to be performed Create a send list containing send list entries each defining the size and length of a header and a data field Setup the channel s pointer to point to the location of the first send list entry This is done using the SPW TxVC SendList Pointer Register Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX k RUAG GAISLER Aerospace Defence Technology Setup the size of the send list defining the number of send list entries This is done using the SPW TxVC SendList Size Register This also triggers the channel which is now ready to transmit packets The progress of the transmission can be observed using the following registers The address to the send list entry of the latest successfully transmitted packet can be observed using the SPW TxVC SendList Pointer Register The number of remaining send list entries in the send list can be observed using the W TxVC SendList Size Register SPW TxVC Status Register can also be
305. us after a previous one may be lost Constraints Field Description RxTimeCnt The last received time code i e time information RxTimeCtrl The last received time ctrl i e control flags Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX m RUAG GAISLER Aerospace Defence Technology 10 7 1 5 Other registers SPW First Failing Packet Register SPW_FFPR RC 31 24 23 16 DLA PtcId 0 0 MSB 15 8 7 0 FFB3 ErrCode 0 0 LSB Function This register holds diagnostic information related to the reception and identification of a packet Timing DLA PtcId and FFB3 are as long as no errors have been detected updated for every subsequent packet The register is frozen when an error is detected in the four first bytes i e rejected during the identification process e g VCTP to a disabled channel of a packet or in a hardware supported RMAP command The register is not updated for any new errors until after being read Constraints Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX a RUAG GAISLER Aerospace Defence Technology Field Description ErrCode No Error No error detected since the last register read access DestErr Error while DMA accessing the internal bus e g illegal address 2 CmdErr Unused RMAP command according to RMAP 3 DKe
306. ut positive positive SpwSOut_N 1 0 O LVDS SpaceWire Strobe output negative negative Table 96 Space Wire RTC signals Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX GAISLER 15 REVISION CONTROL o RUAG Aerospace Defence Technology The table below shows changes between revisions TABLE 97 Revision control Revision Date Sections Comment 2 4 2009 Dec 3 4 10 Removed note on obsolete PROM size register field 4 2 On chip memory protection clarified 4 2 4 4 Error counter and autoscrubbing clarified for on chip memory 1 3 10 5 10 ECSS document referneces updated for SpaceWire RMAP etc 2 3 2009 Mar 3 3 5 2 Clarified that there is a receiver shift register not to be mistaken with the 8 bit serial shift register used for filtering Clarified error bit generation and handling 3 3 5 5 Clarified that a break detection can generate a receiver interrupt 2 2 2008 Dec Front page all RUAG name and logo introduced 2 1 2008 Oct Front page all Aeroflex Gaisler name address and logo introduced 2 0 2008 Oct 3 4 IoScN renamed to IoCsN 3 4 3 3 4 10 Number of PROM wait states changed from 15 to 30 1 9 2008 June General Unused bits in registers usage clarified 3 1 3 Multiplier description restricted to implementation 3 2 1 Cache information updated to implementation 3 2 2 2 Cache information up
307. watchpoints 0 4 25 UMAC SMAC instruction implemented 24 20 Number of register windows The implemented number of SPARC register windows 1 19 17 Instruction cache size The size in kbytes of the instruction cache Cache size gine 16 15 Instruction cache line size The line size in 32 bit words of each line Line size guns 14 12 Data cache size The size in kbytes of the data cache Cache size gcse 11 10 Data cache line size The line size in 32 bit words of each line Line size 9 UDIV SDIV instruction implemented 8 UMUL SMUL instruction implemented 7 Watchdog implemented 6 Memory status and failing address register present 5 4 FPU type 00 none 01 Meiko 3 2 PCI core type 00 none 01 InSilicon 1O ESA 11 other 1 0 Write protection type 00 none 01 standard N 2PLSZ Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX RUAG GAISLER Aerospace Defence Technology 3 3 8 Power down The processor can be powered down by writing an arbitrary value to the power down register Power down mode will be entered on the next load or store instruction To enter power down mode immediately a store to the power down register should be performed followed by a dummy load During power down mode the integer unit will effectively be halted The power down mode will be ter
308. xTime Code TIME_IN 7 6 Reg TIME_IN 7 0 I TXTime Data Code TIME_IN 5 0 Counter SPWTxTick En DelayTICK m TICK_IN CODEC RxTime Code TIME_OUT 7 6 Re Data e Ra j p PME UTO TIME_OUT 7 0 RXTime RXTime Code Code Counter 1 Reg TIME_OUT TICK OUT En SPWRxTick DelayTICK RXTime Interrupt Code Irq TXTime Code Irq Figure 10 18 Time Code handling block diagram Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX m RUAG GAISLER Aerospace Defence Technology 10 6 7 3 Alternative Time code reception The SPW2 core RxTimeTick signal is connected to the interrupt bus The tick can thus be used to latch the counter values in the Timer core using the above function The time code information can be readout through the SPW Receive Time Code Status Register SPW_RTCSR in the SPW2 core 10 6 7 4 Alternative Time code transmission Time code transmission can be peformed in two ways through software control using the SPW SW Transmit Time Code Register SPW SWTTCR through hardware control via the interrupt bus using the SPW Transmit Time Code Mask Register SPW_TTCMR and the SPW Transmit Time Code Register SPW_TTCR The time code information corresponding to the first of the above events occuring will be transmitted Any subsequent event occur
309. yErr Destination Key error for RMAP commands supported by hardware 4 DCRCEtrr Data CRC error for RMAP commands supported by hardware Combined header and data CRC error for RMAP commands supported by software 5 EEOP Early EOP in data for RMAP commands supported by hardware i e EOP has been received with less data than expected from the RMAP command header 6 CTL Cargo too large Late EOP or EEP in data for RMAP commands supported by hardware i e EOP EEP has been received with more data than expected from the RMAP command header 7 EEEP Early EEP in data for RMAP commands For RMAP commands supported in hardware EEP has been received with less data or exactly as much as expected from the RMAP command header 9 VBOvrR Verify Buffer Over Run A verified write of more than 4 bytes was attempted Note that a verified write with a size not divisable by 4 gives an AuthErr 10 AuthErr Authorisation error Rejected RMAP commands when hardware support enabled Read or Write with extended address exceeding OF i6 Verified Write with non word aligned address Verified Write with size 0 or size not divisable by 4 Rejected RMAP commands when software support is disabled and hardware support is enabled Read Modify Write Non Incrementing Read or Write Any RMAP command when neither software nor hardware support is enabled Rejected VCTP packet when the corresponding RxVC channel was not enabled 12 DLA Err
310. ysis The interrupt generation is independent of the CanCONF ABORT field setting Note that the RxAHBErr interrupt is generated in such way that the corresponding read and write pointers are valid for failure analysis The interrupt generation is independent of the CanCONF ABORT field setting Copyright 2006 2007 2008 2009 Aeroflex Gaisler and RUAG RTC 100 0012 December 2009 Version 2 4 EROFLEX k RUAG GAISLER Aerospace Defence Technology 9 11 Memory mapping The CAN message is represented in memory as shown in table appendix 78 TABLE 78 CAN message representation in memory AHB addr 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDE RTR E bID elD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 elD 0x4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DLC TxErrCntr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RxErrCntr Ahb OR Off Pas Err s 0x8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Byte 0 first transmitted Byte 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte 2 Byte 3 OxC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Byte 4 Byte 5 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 Byte 6 Byte 7 last transmitted Values Levels according to CAN standard 1b is recessive Ob is dominant Legend Naming and number in according to CAN standard IDE Identifier Extension 1b for Extended Format Ob for Standard Format RTR Remote Transmission Re

SPW-RTC User Manual - ESA Microelectronics Section

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