ETE-GLX User Manual
Contents
1. Signal Description Note VCC Power Supply 5 VDC 5 I external supply GND Power Ground I external supply N C Not connected n a Do not connect Signal Description of IDE signals Note PIDE DO 15 Primary IDE Databus 3V3 signal level 5 0 compliant PIDE_AO 2 Primary IDE Addressbus 3V3 signal level PIDE_CS1 Primary IDE chip select 10 3V3 signal level PIDE_CS3 Primary IDE chip select channel 3V3 signal level PIDE_DRQ Primary IDE dma request I 5V0 compliant PIDED_AK Primary IDE dma acknowledge 3V3 signal level PIDE_RDY Primary IDE ready I 5 0 compliant PIDE_IOR Primary IDE IO read 3V3 signal level PIDE_IOW Primary IDE IO write 3V3 signal level PIDE_INTRQ Primary IDE interrupt request I 5 0 compliant SIDE DO 15 Secondary IDE Databus Parallel to PIDE SIDE_AO 2 Secondary IDE Addressbus Parallel to PIDE SIDE_CS1 Secondary IDE chip select channelO Parallel to PIDE SIDE_CS3 Secondary IDE chip select channell Parallel to PIDE SIDE_DRQ Secondary IDE dma request I Parallel to PIDE SIDED_AK Secondary IDE dma acknowledge Parallel to PIDE SIDE_RDY Secondary IDE ready I Parallel to PIDE SIDE_IOR Secondary IDE IO read Parallel to PIDE SIDE_IOW Secondary IDE IO write Parallel to PIDE SIDE_INTRQ Secondary IDE interrupt request I Parallel to PIDE DASP_S Secondary IDE Drive active O OC Connected to onboard CFC PDIAG_S Secondary2. 19 3 3 2 CMOS dala Hc 19 3 3 3 BIOS Setup Default Dalai tr a det E 19 3 3 4 Force the use of CMOS default 20 Technical Specification 44 cie nara obra cni crai 21 Signal and Pin Out 23 5 1 Connector X1 PCI Bus USB 23 5 2 26 5 3 Connector X3 VGA LCD Video LPT Floppy Keyboard ae lle aia dua Quesada ease 28 5 4 Connector X4 IDE Ethernet Miscellaneous 32 System HesOUF6BS gt 35 interrupt oe rire cnet 35 6 2 IDNMDATHOSOLITOOS ect 35 6 3 Memory cuv aicut nats nar atin 36 GA E 36 6 5 Device 5 5 000 a EER 36 66 JEC DUS NUM Der 55 ED 37 POlNMSDDIFIGy
3. There is no other destination possible The file xpress rom is used from the current directory Usage Revision 0 1A Page 19 of 53 MSC ET e GLX CPU User s Manual BIOS Description 1 Update the BIOS flashrom sfffc0000 xpress rom 2 New CMOS data Use BIOS setup to configure the CMOS data 3 Patch the default data glxpatch Now the file xpress rom is updated with the new default data 4 Personalize BIOS Rename file xpress rom to your preferred file name lt file_name gt 5 Use the new BIOS flashrom sfffc0000 file name gt 3 3 4 Force the use of CMOS default data There are situations when it is useful to have the CMOS ram set with the default data when starting the BIOS This can be managed from the DOS prompt with the following program call forcdflt When the BIOS is started the next time it sets the default values to CMOS and E Prom then boots again Revision 0 1A Page 20 of 53 MSC ET e GLX CPU User s Manual Technical Specification 4 Technical Specification Technical Specification Function CPU CPU Speed Cache Chipset Super IO DRAM Socket EIDE Interface Flashdisk Floppy Parallel Interface Serial Interface Infrared Keyboard Mouse USB ports PCI Master support Video Controller Videomemory Videoresolution Display support Display Interface TV Video signals CRT configuration Flat Panel configuration Ethernet Co
4. and Cache Or lt iimization d System Clock PLL Configuration password enabling F Power Management Miscellaneous Configuration and changing Boot Order Password Setting L Load Defaults This will save all e detaults tor Values Without Exit the changed values all items Without Save and remain in Setup Values And Exit Selecting this will exit Setup Enable it Password without saving display for the highlighted item modified values and reboot the platform new values In the following all sub menus are described tabular to get a better overview Selecting this entry will load Revision 0 1A Page 12 of 53 MSC ET e GLX CPU User s Manual BIOS Description 3 1 3 Motherboard Device Configuration Menu Entering Motherboard Device Configuration Menu display the following sub menu items Item Options Comment Drive Configuration Sub Menu Set configuration for hard drive and floppy devices LPC Card Devices Sub Menu Set configuration for Onboard Super I O devices External Super I O Sub Menu Set configuration for External Super I O devices Configuration Video and Flat Panel Sub Menu Set Video and Flat Panel Configuration Configuration PCI Configuration Sub Menu Set PCI Bus Configuration Network Configuration Sub Menu Set Network Configuration Themal Configuration Sub Menu Read current CPU temperature Return to Main Menu
5. lt Manual ETE GLX MSC ETE ETX Module AMD Geode LX800 Rev 0 19 November 24 2008 MICROCOMPUTERS SYSTEMS COMPONENTS VERTRIEBS GMBH embedding excellence Preface Copyright Notice Copyright 2008 MSC Vertriebs GmbH All rights reserved Copying of this document and giving it to others and the use or communication of the contents thereof are forbidden without express authority Offenders are liable to the payment of damages All rights are reserved in the event of the grant of a patent or the registration of a utility model or design Important Information This documentation is intended for qualified audience only The product described herein is not an end user product It was developed and manufactured for further processing by trained personnel Disclaimer Although this document has been generated with the utmost care no warranty or liability for correctness or suitability for any particular purpose is implied The information in this document is provided as is and is subject to change without notice EMC Rules This unit has to be installed in a shielded housing If not installed in a properly shielded enclosure and used in accordance with the instruction manual this product may cause radio interference in which case the user may be required to take adequate measures at his or her own expense Trademarks All used product names logos or trademarks are property of their respective
6. Upper level menu Go back into Main Menu Enter External Super I O Configuration requires a base board with external SMSC C669 SIO 3 1 3 1 Drive Configuration Menu Item Options Comment IDE BIOS Support Enable Enable Disable INT 13h interface in BIOS for Disable IDE drives 80 Conductor Cable Sense None No cable sense leads to 40 conductor cable Force 40 leads to 40 conductor cable Force 80 leads to 80 conductor cable GPIO 05 auto detect cable DMA UDMA BIOS Support Enabled Enable DMA BIOS support Disabled Disable DMA BIOS support Force mode for Drive AUTO Automatically select mode Force selected mode Floppy Bios Support Enable Enable Disable all floppy support Disable External Floppy Enable Enable Disable External floppy Controller Disable CD ROM Boot Bios Support Enable Enable Disable CD ROM Boot option Disable Enabling Floppy Bios Support only enables the BIOS support for floppy devices Using a floppy requires a correct setting of LPT FLPY to low level LPT or Floppy Interface configuration input Enabling External Floppy requires a base board with external SMSC C669 SIO For some USB memory sticks it may be necessary to enable Floppy Bios Support to make Boot from USB available Revision 0 1A Page 13 of 53 MSC ET e GLX CPU User s Manual 3 1 3 2 LPC Card Devices BIOS Description Item Options Comment Seria
7. aaan ree ae aaa ee a a ana 38 6 8 System Serial Buses Eras 39 7 40 8 Display 42 8 0 Display INCH ACC DUIS eMe DUUM 42 VIDS CACC 43 8 1 2 Interfaco o e i n en de occ bh t Dou eu dr de us 45 B s e fee eec re Meer cte Fence e e 46 8 1 4 Signals ET e Module lt gt TFT Display with TTL Signalling 47 8 1 5 Signals ET e Module lt gt TFT Display with LVDS Signalling 18 Bit 48 8 2 er P o ues 49 9 Power Management and Power Control ceres 50 10 External ports and COMA eese 51 11 Windows Installation Hints nnn 51 12 Thermal management 51 13 POSEGOGdOS 2 eere Ere ee NESE 51 MSC ET e GLX CPU User s Manual General Information 1 General Information 1 1 Introduction The MSC ET e CPU modules are compatible to st
8. Note LPT FLPY LPT or Floppy Interface configuration input I Connect to VCC resistor 4K7 STB RES Strobe signal 5VO signal level AFD DENSEL Automatic feed 5VO signal level PDO INDEX Databus DO 5VO signal level PD1 TRKO Databus D1 5VO signal level PD2 WP Databus D2 IO 5VO signal level PD3 RDATA Databus D3 5VO signal level PD4 DSKCHG Databus D4 IO 5VO signal level PDS RES Databus D5 IO 5VO signal level PD6 RES Databus D6 5VO signal level PD7 RES Databus D7 IO 5VO signal level ERR HDSEL LPT error I 5VO compliant INIT DIR Initiate 5VO signal level SLIN STEP Select 5VO signal level ACK DRVI Achnowledge I 5VO compliant BUSY MOTI1 Busy I 5VO compliant PE WDATA Paper empty I 5 VO compliant Revision 0 1A Page 29 of 53 MSC ET e GLX CPU User s Manual Signal and Pin Out Description SLCT WGATE Power ON I 5V0 compliant Signal Description of LVDS flat panel signals Note BIASON Display contrast voltage ON DIGON Display Power ON BLON Display Backlight ON LCDDOO 19 LVDS channel data 0 19 Signal Description of TTL flat panel signals Note BIASON Display contrast voltage ON DIGON Display Power ON BLON Display Backlight ON 0 5 0 5 RGB Signals 0 5 Revision 0 1 Page 30 of 53 MSC ET e GLX CPU User s Manual Standard Pinning with LVDS TTL signals Signal and Pi
9. 12VDC 4 1 connect to Ground 2 connect to 5VDC or 3V3DC as required 3 connect to 12VDC if required 4 connect to the corresponding display contacts Revision 0 1A Page 48 of 53 MSC ET e GLX CPU User s Manual Display Connection 8 2 Resolution and Timings The graphics controller of the module built in the AMD Geode LX800 CPU supports the following display resolutions and timings Table 6 32 Display Modes 640x 450 8160242 o v 800 x 600 00 05 9 L 8 16072432 10 1 1024x768 7 r eom 7s vero eoma _ s awo 1m 81602 o ow o oo o va w 39 mo Revision 0 1A Page 49 of 53 MSC ET e GLX CPU User s Manual Display Connection Table 6 32 Display Modes Continued 1280 x 1024 16 or 24 32 60 108 000 200 133 500 200 135 000 157 500 289 192 000 1600 x 1200 162 000 180 000 108 000 702 500 720 500 eem 251 182 8 16 or 24 32 100 ____ 280 640 TOT 25 000 778 400 298 000 297000 341300 Television Modes 27000 27000 27000 27 000 up to 32 50 00 74 750 747 74 750 1920x1080 HD up to 32 up to 60 00i up to 148 500 400 9 Power Management and Power Control The GLX module will work in standard ATX and AT mainboards AT
10. 3 connect to 12VDC if required 4 connect to the corresponding display contacts Revision 0 1A Display Connection Page 47 of 53 MSC ET e GLX CPU User s Manual Display Connection 8 1 5 Signals ET e Module lt gt TFT Display with LVDS Signalling 18 Bit X3 LCD Interface TFT TTL Connection ET e Module Connect to Numb Net Name er Net Name Number LCD VSYNC 42 lt gt 4 LCDDOO_RO 37 lt gt LVDSO 4 LCDDO 1 35 lt gt LVDSO 4 LCD_ENVDD DIGON 46 PowerSwitch 1 LCDDO2_R2 38 lt gt LVDS1 4 LCDDO3_R3 36 lt gt LVDS1 4 LCD_HSYNC 45 lt gt 4 LCDDO4_R4 29 lt gt LVDS2 4 LCDDO5 R5 31 lt gt LVDS2 4 GND 1 lt gt GND 4 LCDDO6_GO 32 lt gt LVDSC 4 LCDDO7 G1 30 lt gt LVDSC 4 GND 1 lt gt GND 1 LCDDOS8 G2 23 lt gt LVDS3 4 LCDDO9 25 lt gt LVDS3 4 FPDDC_DAT 41 lt gt LCDDO10 G4 26 lt gt LCDDO11_G5 24 lt gt FPDDC_CLK 43 lt gt LCDDO12 BO 19 lt gt LCDDO 13 B1 17 lt gt DETECT 9 lt gt LCDDO14 B2 20 lt gt LCDDO15 B3 18 lt gt GND 1 lt gt LCDDO16 B4 11 lt gt LCDDO17_B5 13 lt gt GND 1 lt gt LCD_SHFCLK 12 lt gt LCD_EN 14 lt gt BLON 2 PowerSwitch 2 GND 1 lt gt GND 1 GND 5 lt gt GND 1 VCC via Power 5 3V3 2 PowerSwitch 1 Switch 4 VCC 12V 3 PowerSwitch 2
11. Bus Systemmonitoring BIOS Sytem BIOS VGA BIOS Boot devices Boot options Power Management USB legacy support USB Floppy Boot Flash Update Supply Voltage Standard Power Supply Voltage Batterie Power Current consumption 5VODC Current consumption Batterie Power Temperature Humidity Mechanical Dimension Dimension Thickness Bottom Top Revision 0 1A yes Board Temperature Voltage Supervision INSYDE BIOS INSYDE BIOS Floppy Harddisc CD ROM USB Stick Ethernet TBD yes yes yes via Floppy or HDD 5VODC 5 3V3DC 0 3V 0 9V 266Mhz 5V 1 1A typ max 1 4A 500Mhz 5V 1 3A typ max 1 8A 10uA typ operation 0 to 60 C storage 10 to 85 C operation 10 to 90 storage 5 to 95 non condensing 95 x 114 mm 3 7 x 4 5 lt 12mm Page 22 of 53 MSC ET e GLX CPU User s Manual 5 Signal and Description 5 1 Connector PCI Bus USB Signal and Pin Out Description Sound Signal Description Note VCC Power Supply 5 VDC 5 I external supply GND Power Ground I external supply 3V Power Supply 3 V3DC Do not use externaly N C Not connected n a Do not connect SERIRQ Serial interrupt request n c Not supported Signal Description of PCI Bus Signals Note PCICLK1 4 PCI clock output REQO 3 PCI bus request I PCI signals not 5 0 co
12. EDID 1 3 TFT Read display data from eeprom EDID 2 0 preferred Read display data from eeprom EDID 1 3 preferred Use predefined settings Resolution 320x240 640x480 800x600 1024x768 1152x864 1280x1024 1600x1200 Configures the output resolution Data BusType 9 24 bits 1ppc The only data bus type Refresh Rate 60 Hz 70 Hz 72 Hz 75 Hz 85 Hz 90 Hz 100 Hz HSYNC Polarity Active low Active high The horizontal synchronization pulse polarity VSYNC Polarity Active low Active high The vertical synchronization pulse polarity LP Active Period Active only Free running Data enable Revision 0 1A Page 15 of 53 MSC ET e GLX CPU User s Manual BIOS Description SHFCLK Active Period Active only Free running How to use pixel clock When using the BIOS in the flat panel EDID mode it is recommended to set the TFT data to the expected resolution to get a display even if there are no EDID data available 3 1 3 6 PCI Configuration Menu Item Options Comment PCI INTA Disable IRQ 1 IRQ 3 Enable Disable INTA to IRQ steering IRQ 4 IRQ 5 IRQ 6 IRQ 7 IRQ 9 IRQ 10 IRQ 11 IRQ 12 IRQ 14 IRQ 15 PCI INTB Same as above Enable Disable INTB to IRQ steering PCI INTC Same as above Enable Disable INTC and internal USB to IRQ steering PCI INTD Same as above Enable Disable INTD and on board LAN to IRQ stee
13. 9 2 5 Ethernet Controller eos casei ooo ooa oes 9 260 Palallel BISSOS 9 2 10 26 MIDE MAGI ACCS ys E bu e IINE 10 MONTON 10 2 10 VA dio Subsystem SS 10 2 11 System Serial BUSSBSu 10 BIOS DescriptioM 11 oiu RS dp SERERE RE SER HERPES SERE 11 3 1 1 General NAVIGallOl co eroe Pep arose e ebore tonus 11 3 1 2 Setup Main MOL eH ML 12 3 1 3 Motherboard Device Configuration 13 3 1 4 Memory an Cache Optimization 17 3 1 5 System Clock PLL Configuration 17 3 1 6 Power Management Meri p Pep repe 17 3 1 7 Miscellaneous 17 91402 BOOEOITIB S age MEME ME 18 3139 Password Selllligs ete i oe te i dr eee x Di da eee E t es 18 3 2 Network BOOUNIBWln tn ee fete fare eoe eor Dedi et Pe 19 s 19 39 Updater
14. on BIOS configuration 5Ah HW Monitor only if equipped 90h HW Monitor only if equipped 6 6 PC bus numbering SM Bus PC Bus EDID Bus Revision 0 1A 0 1 0 10 System Resources Page 37 of 53 MSC ET e GLX CPU User s Manual System Resources 6 7 PCI Mapping Routing PCI INT e LX800 INT A CPU Core amp PCI INT A e LX800 INT PCI INT B e LX800 INT PCI INT C e LX800 INT D LAN amp PCI INT D PCI interrupts mapping can be changed in BIOS Setup Menu Routing PCI Request Grant extended arbiter option e LX800 BREQ GNT2 55536 e LX800 BREQ GNTO PCI BREQ GNT 0 on ET e Connector supported LX800 BREQ GNTO PCI BREQ GNT 1 on ET e Connector supported LX800 BREQ GNTO PCI BREQ GNT 2 on ET e Connector supported e LX800 BREQ GNT PCI BREQ GNT 3 on ET e Connector supported e LX800 BREQ GNT local LAN controller Mapping PCI IDSEL e LAN IDSEL AD12 e PCI Slotl IDSEL tbd select on baseboard e PCI Slot2 IDSEL tbd select on baseboard e PCI Slot3 IDSEL tbd select on baseboard e PCI Slot4 IDSEL tbd select on baseboard Note The GLX ETe module implements an extended arbiter for up to four external PCI masters on REQ GNT 0 3 Revision 0 1A Page 38 of 53 MSC ET e GLX CPU User s Manual System Resources 6 8 System Serial Buses The module has 4 serial busses I C Bus like The busses are provided by the following sources SM
15. BIOS PM at Boot Disabled Turns on legacy PM before booting OS Enabled APM Available No APM interface available for use Yes ACPI Available No ACPI interface available for use Yes 51 Clock On Controls the external clock generator 51 Off CPU Clock Gating Enabled Set to Enabled for power saving Disabled Chipset Clock Gating Enabled Set to Enabled for power saving Disabled 3 1 7 Miscellaneous Configuration Item Options Comment Splash Screen Enable Enable Disable display of splash screen Disable Clear Splash Screen Enable Enable Disable clearing of splash screen after Disable display if enabled Splash Screen Timeout Milliseconds to wait 0 wait 1 65535 Enable Disable splash screen delay timeout after display if enabled Revision 0 1A Page 17 of 53 MSC ET e GLX CPU User s Manual BIOS Description Display text Enable Enable Disable display of all BIOS output texts Disable Summary Screen Enable Enable Disable display of summary screen Disable Summary Screen Timeout Milliseconds to wait O no wait 1 65535 Enable Disable summary screen delay timeout after display if enabled O disabled Power Button Disabled Enable Use ACPI Mode 4 second soft off Enabled Disable ACPI Mode is disabled after power on AT board compatible AT mode Power button is completely disabled after power on You have to remove power to activa
16. Bus System management Bus e SM GPIO14 PinG3 of CS5536 e SM DAT gt GPIO15 PinF1 of CS5536 FP DDC Bus Flat Panel Data Display Channel FP_DDC_CLK GPIO8 PinE3 of CS5536 e FP DDC DAT gt GPIO9 PinD1 of CS5536 Bus General purpose serial bus gt GP14 Pin125 of W83627HF 2 5 124 W83627HF DDC Bus Data Display Channel e DDC_CLK GPIO3 PinE1 of CS5536 DDC_DAT GPIO4 PinE2 of CS5536 Note I2C Bus pulled up with 1k to 5V SM Bus pulled up with 2k7 to 3V3 FP DDC Bus pulled up with 1k to 3V3 DDC Bus pulled up with 1k to 3V3 Revision 0 1A Page 39 of 53 Topview Bottomview Else else elles emen e 1 88 ge E HL E T rd s pm MSC ET e GLX CPU User s Manual Mechanical Specificatio 95 0 92 5 4 459 53 3 zys Printed Circuit Board Heat Spreader Component max 2 0 mm high Revision 0 1A Page 41 of 53 MSC ET e GLX CPU User s Manual Display Connection 8 Display Connection 8 1 Display Interface ET e connector X3 provides all required signal on pin 1 50 to connect flat panel TFT Displays Two different kinds of display interfaces are supported depending of the model of the ET e module LVDS Display Interface TFT display e TTL Display Interface TFT d
17. IDE Master Slave negotiation I Connected to onboard CFC HDRST HardDrive reset 3V3 signal level CSLID_P Not supported na Revision 0 1A Page 32 of 53 MSC ET e GLX CPU User s Manual Signal and Pin Out Description Signal Description of Ethernet signals Note TXD TXD Ethernet Twisted Pair transmit signal pair Twisted pair signals for external transformer RXD RXD Ethernet Twisted Pair receive signal pair I Twisted pair signals for external transformer ACTLED Ethernet activity LED 3V3 signal level LILED Ethernet link LED 3V3 signal level SPEEDLED Ethernet speed LED ON at 100Mb s 3V3 signal level Signal Description of Misc signals Note SPEAKER Speaker output 3V3 signal level Connect the speaker between SPEAKER and VCC BATT Batterie supply I External RTC_Supply Un PWGIN Power good input I 3V3 signal level Also usable as reset input Bus clock 5VO signal level 5 0 compliant 5VO signal level 5 0 compliant SMBCLK SM Bus clock 3V3 signal level 5VO compliant SMBDAT SM Bus Data 3V3 signal level 5 0 compliant SMBALRT SM Bus Event IO KBINH Keyboard inhibit I 5 0 compliant 5V SB Supply of internal suspend circuit I PS ON Power Save ON 5 0 signal level PWRBTN Power Button I 5V0 compliant OVCR Over current
18. detect for USB I 5V0 compliant ROMKBCS Do not connect n a EXT_PRG Not supported n a WDTRIG Do not connect na GPCS Not supported n a 1 Not supported na GPE2 Not supported na BATLOW Battery low alarm I EXTSMI Not supported na Revision 0 1A Page 33 of 53 MSC ET e GLX CPU User s Manual Signal and Pin Out Description Pin Signal Pin Signal Pin Signal Pin Signal 1 GND GND 51 SIDE_IOW 52 PIDE_IOR 3 5V_SB PWGIN 53 SIDE_DRQ 54 PIDE_IOW D PS ON SPEAKER 55 SIDE 115 56 PIDE DRQ 7 PWRBTN 8 BATT 57 SIDE_DO 58 PIDE_D15 9 KBINH 10 LILED 59 SIDE_D14 60 PIDE DO 11 WDTRIG 12 ACTLED 61 SIDE DI 62 PIDE 14 13 ROMKBCS 14 SPEEDLED 63 SIDE_D13 64 PIDE DI 15 EXT PRG 16 DCLK 65 GND 66 GND 17 18 VCC 67 SIDE_D2 68 PIDE_D13 19 OVCR 20 GPCS 69 SIDE_D12 70 PIDE_D2 21 EXTSMI 22 I2DAT 71 SIDE_D3 72 PIDE_D12 23 SMBCLK 24 SMBDATA 73 SIDE DII 74 PIDE_D3 25 SIDE_CS3 26 SMBALRT 75 SIDE_D4 76 PIDE_D11 27 SIDE_CS1 28 DASP_S 77 SIDE_D10 78 PIDE_D4 29 SIDE_A2 30 PIDE_CS3 79 SIDE D5 80 PIDE DI10 31 SIDE A0 32 PIDE_CS1 81 VCC 82 VCC 33 GND 34 GND 83 SIDE_D9 84 PIDE D5 35 PDIAG S 36 PIDE A2 85 SIDE D6 86 PIDE D9 37 SIDE 1 38 PIDE 0 87 SIDE D8 88 PIDE D6 39 SIDE INTRQ 40 PIDE AI 89 GPE2 90 CBLID_P 41 BATLOW 42 91 RXD 92 PIDE_D8 43 SIDE_AK 44 PIDE_INTRQ 93 RXD 94 SIDE_D7 45 SIDE_RDY 46 PIDE_AK 95 TXD 96 PIDE_D7 47
19. device if two devices one master one slave are connected 2 9 System Monitor The module is monitored by the Winbond 83627 Super IO Refer to 3 for information in detail Currently four supply voltages are monitored VCC CORE 1 2 V for the LX800 VCC CORE STANDBY 1 2 V for the LX800 VCC 3V3 3 3 V VCC MEM 2 5 V Additionally the monitoring of the CPU die Temperature and board temperature is implemented 2 10 Audio Subsystem The audio subsystem of the companion chip is AC97 compliant and works together with AC97 codec LM4549 from National Semiconductor Refer to 2 for information in detail 2 11 System Serial Busses The module has 4 serial buses like PC Bus SM Bus System Management Bus provided by companion SM Bus controller DDC Bus Data Display Channel provided by companion FP DDC Bus Flat panel Data Display Channel provided by companion Bus General purpose serial bus provided by W83627 Super IO Revision 0 1A Page 10 of 53 MSC ET e GLX CPU User s Manual BIOS Description BIOS Description 3 1 SETUP MENUS To enter Setup Press the F1 key while booting the system 3 1 1 General Menu Navigation To navigate within menus use the following keys Key Function Up Arrow Highlight the item above the currently highlighted item If on the top item will highlight the last item Down Arrow or Highlight the item below the currently highlighted i
20. order Try network only Try local drives only Show Setup Prompt Enable Enables disables if Please press CTRL 5 to Disable enter sentence is shown Setup Menu Wait Time Seconds to wait Select how long the sentence Please press 0 5 seconds CTRL 5 to enter is shown Press Space to change the highlighted value Press enter to highlight the next option Press ESC to leave menu without changes Press F4 to save configuration 3 3 BIOS Tools There are some useful tools for BIOS update and cmos data handling All tools need a DOS like MS DOS 6 22 with memory manager himem sys to run properly 3 3 1 Update Flashrom com is used to update the contents of the flash ROM of your MSC ET e GLX with a new version of the Bios Example of usage flashrom 0000 file name gt After successfully flashing the new bios contents you must perform a power cycle During the first boot you have to go into the BIOS setup and load bios defaults 3 3 2 CMOS data To save current CMOS data for later usage you may use the tool CMOS EXE Saving cmos s file name Restoring cmos r file name 3 3 3 BIOS Setup Default Data It is sometimes necessary to have special default data used in production BIOS There is a tool to patch the current setup data to the BIOS file By using the current setup stored in CMOS ram is patched to the BIOS update
21. owners Certification MSC Vertriebs GmbH is certified according to DIN EN ISO 9001 2000 standards Life Cycle Management MSC products are developed and manufactured according to high quality standards Our life cycle management assures long term availability through permanent product maintenance Technically necessary changes and improvements are introduced if applicable A product change notification and end of life management process assures early information of our customers Product Support MSC engineers and technicians are committed to provide support to our customers whenever needed Before contacting Technical Support of MSC Vertriebs GmbH please consult the respective pages on our web site at www msc ge com support boards for the latest documentation drivers and software downloads If the information provided there does not solve your problem please contact our Technical Support Email support boards msc ge com Phone 49 8165 906 200 Contents 1 General TENE RIVA OF dist ated bee odas Dele bibendi te eds ii e bu 5 Tet TIO CUI eoo cesta ORE e denied S 5 k2 Technical WATCHMAN e i e I RE REA 6 PE 7 221 dilock DIagiditlzss ou ee er E E En IH DRE 7 CPU ANC IDSC e UM 8 AEC NEN Ive pem rmm 8 244 SUDO oot aan Bb tb pe den bu nie
22. CPI Management Refer to 1 for detail information Companion features PCI to LPC Bridge System Management Bus controller GPIO interface 8259A compatible interrupt controller 8254 compatible timers 8237 compatible DMA controller Bus mastering IDE controller 1 channel 2 devices AC97 codec interface USB 2 0 serial interface Refer to 2 for detail information 2 3 Memory DDR SDRAM The module operates with one DDR SDRAM SO DIMM module Supported are 2 5 Volt modules with up to 1024 Mbyte CompactFlash One CompactFlash socket for CompactFlash Type I cards connected as master device Revision 0 1A Page 8 of 53 MSC ET e GLX CPU User s Manual Module Description BIOS Flash The GLX module supports 4MBit Firmware Hubs 2 4 Super IO The module uses the Super IO chip Winbond W83627HF with the following features Floppy Disc Controller FDC Two 16550 compatible UARTS IRDA Infrared Interface Parallel Port ECP EPP compatible APM controller Keyboard Mouse controller Real Time Clock Watchdog Timer Refer to 4 for information in detail 2 5 Ethernet Controller The Ethernet interface was built with the Intel 82551 Ethernet controller Refer to 5 for information in detail 2 6 Parallel Busses The MSC ET e GLX module provides two parallel busses the PCI bus and the ISA bus PCI Bus The PCI bus meets the PCI 2 2 specification refer to 6 for information in detail The PCI bus implementation ha
23. FFh Network Boot or Not used Yes Note 1 E0000h EFFFFh Virtual System Architecture No F0000h FFFFFh System BIOS No Note 1 If network boot is enabled D0000h DBFFFh is used for the network boot ROM 6 4 IO Mapping The MSC ET e GLX has the same IO port usage as a standard AT PC Nevertheless there are few additional ports used as specified in the following table IO address Usage Available Note range 02Eh 02Fh Configuration space for internal controller No 200h 20Fh Reserved for system use No 2E8h 2EFh COM D No Note 1 295h 296h Hardware monitor No only if equipped 330h 33Fh Reserved for system use No 370h 371h Configuration space for SMC controller No Note 1 3E8h 3EFh COM C No Note 1 6000h 60FFh SM Bus IO Base No 6100h 61FFh GPIO IO Base No 6200h 62FFh General Purpose Timers IO Base No 6300h 63FFh IRQ Mapper IO Base No 9C00h 9 ACPIIO Base No 9D00h A000h PM IO Base No Note 1 Only available reserved if the base board is equipped with a FDC37C669 SIO chip 6 5 Device Addresses The MSC ET e GLX uses the following device addresses on the SM bus The I2C bus does not occupy any address Address Usage Note ASh BIOS EEPROM Reserved AOh DDR Serial Reserved Revision 0 1A Page 36 of 53 MSC ET e GLX CPU User s Manual EEPROM Axh Winbond 83627HF Exakt address depends
24. SIDE_IOR 48 PIDE_RDY 97 TXD 98 HDRST 49 VCC 50 VCC 99 GND 100 GND Revision 0 1A Page 34 of 53 MSC ET e GLX CPU User s Manual System Resources 6 System Resources 6 1 Interrupt Resources Interrupt Usage Available Note IRQ 0 Timer0 No IRQ 1 Keyboard No IRQ 2 Cascade No IRQ 3 COM B No Note 1 IRQ 4 COM A No Note 1 IRQ 5 PCI No IRQ 6 FDC No Note 1 IRQ7 LPT1 No Note 1 IRQ 8 RTC No IRQ 9 PCI Yes IRQ 10 PCI COM D Yes Note 2 IRQ 11 PCI COM C Yes Note 2 IRQ 12 PS2 Mouse No IRQ 13 FPU No IRQ 14 IDEO No Note 1 IRQ 15 Yes 6 2 DMA Resources DMA Usage Available Note DMA 0 Not used Yes DMA 1 Sound No Note 1 DMA 2 FDC No Note 1 DMA 3 Not used Yes DMA 4 Cacade No DMA 5 Sound No Note 1 DMA 6 Not used Yes DMA 7 Not used Yes Note 1 If the device mentioned in Usage is disabled in Setup Menu this interrupt is available Note 2 Only used if the base board is equipped with a FDC37C669 SIO chip and the corresponding COM ports are enabled Revision 0 1A Page 35 of 53 MSC ET e GLX CPU User s Manual System Resources 6 3 Memory Mapping Memory address Usage Available Note range 9FCOOh 9FFFFh Enhanced BIOS Data Area No C0000h C7FFFh VGA BIOS No C8000h CFFFFh External PCI VGA Bios or Not used Yes D0000h DFF
25. al desktop PC before installing Windows XP If copying files fails try to disable USB EHCI This mostly works 12 Thermal management Environment Operating Temperature ambient 09 60 C Storage Temperature 25 C 85 C When using the GLX ETe module in high temperature environment please ensure that CPU LX800 and chipset CS5536 do not exceed the maximum case temperature of 85 C Above ambient temperatures of 55 C a specific cooling concept for the system should be developed 13 Post Codes Checkpoint Intermediate Codes Function Description FOh FOh XpressROM code execution start 80h User added code to be run first 00h 60h First SIO access Core SIO initialize LPT can be mapped to I O 80h for embedded devices to provide POST code output 01h Chipset level clock initialize 02h based Geode initialize 03h Create a 32 bit real mode descriptor 04h Memory mapped I O based Geode initialize Revision 0 1A Page 51 of 53 MSC ET e GLX CPU User s Manual Display Connection 05h Geode CPU tests 20h Test entry 28h 2Fh Test stepping ID 2Fh Test Failed 2Ah Test feature 2Eh Test passed exit 06h Autosize memory controller DIMM1 DIMMO 70h Set the clock drive strength and shift value mask the clocks 72h Set the data add
26. andard ETX modules which are available on the market These CPU modules are standardized in terms of system interfaces and mechanical dimensions An ET e module typically includes the CPU the chipset memory video controller Ethernet controller BIOS flash sometimes flash disk e g CompactFlash as well as EIDE floppy keyboard and mouse controller ET e modules are designed with different CPU cores Today the range from 266MHz x86 based 586 core e g National Geode GX1 processor to 1 8 GHz Pentium M core is available This way customers of embedded PC modules are offered scalable and price optimized solutions Use a complete PC compatible system simply as a super component In application systems the ET e module is mounted on a baseboard by means of four 100 pin SMD connectors Via these connectors the standard PC interface signals for PCI and ISA Bus USB EIDE floppy LPT COM keyboard mouse etc as well as the power supply are provided Because of the mechanical and electrical standardization of the ET e modules the system of ET e module and baseboard is scalable The flat design makes allows realizing very compact systems The baseboard provides all application specific functionalities and is typically a custom specific board developed by our customer MSC also offer the service to design and produce baseboards for your application Connect MSC for more information For evaluation and test MSC offers a special baseb
27. ation 3 Data Control 1 amp 2 LVDS or TTL Graphics Controller Power Sequencing 4 Power 5 Principle of display connection 8 1 1LVDS Interface The LVDS interface is used in applications where the distance between module and display exceeds 30 cm This interface may be used in conjunction with displays with built in LVDS interface or with TTL displays and an additional converter module converting the LVDS signals to TTL signals on the display side With LVDS displays connect the LCDDOO LCDDOI and the required supplies simply to the LVDS interface of the display It is important that the ET e GLX module only supports single channel 18 bit LVDS interfaces The 24 bit LVDS interface is not compatible with 18 bit LVDS interfaces 24 bit single channel TFT support has to be checked individually for each display Refer to the documentation of the converter module if you use an LVDS to TTL converter for information how to connect the TTL display to the signal lines The GLX module can be configured aks your MSC support for details to support a subset of dual channel 24 bit LVDS displays Currently there are two different LVDS signal mappings commonly used Some display can select one of these two signal mappings other displays use only one fixed mapping The GLX module supports the following LVDS signal mapping for dual channel 24 bit displays The same table applies to single channel 24 bit LVDS displays except that ther
28. cification For design information or any questions ask MSC or join our web site www msc ge com Revision 0 1A Page 6 of 53 VLO G JO Z X2 ISA ISA Bus Keyboard Mouse Floppy or LPT X3 CRT LVDS DFP TVout 1 2 IrDA CRT X1 PCI 4 x USB Audio PwrMgmt LAN v X4 Speaker EIDE C PwrCtrl u y 5V MSC ETe GLX Yor uonduoseqpo hpo N Z enuen 5 195 X 19 9 13 ISN MSC ET e GLX CPU User s Manual Module Description 2 2 CPU and Chipset The MSC ET e GLX module is based on the AMD processor Geode LX 800 0 9W This processor supports the MMX and AMD 3DNOW instruction sets The CPU core supports different clock rates up to 500 MHz The Northbridge is integrated in the processor chip while the Southbridge the AMD CS5536 called Companion with additional functionality is a separate device CPU features Low Power CPU with power consumption 1 6W typical at 500 MHz e CPU core with MMX and AMD 3DNOW instruction set 64 KByte Level 1 Data Cache 64KByte Level 1 Instruction Cache e 128 KByte configurable Level 2 Cache e ICE interface e Floating point unit FPU e Memory Management Unit MMU e PCI bridge e High performance 2D Graphics controller e Display controller DDR SDRAM controller e APM and A
29. e is only one channel instead of the two odd and even channels LVDS channel Signal mapping Odd Channel 0 RedOdd2 RedOdd3 RedOdd4 RedOdd5 RedOdd6 RedOdd7 GreenOdd2 Odd Channel 1 GreenOdd3 GreenOdd4 GreenOdd5 GreenOdd6 GreenOdd7 BlueOdd2 BlueOdd3 Odd Channel 2 BlueOdd4 BlueOdd5 BlueOdd6 BlueOdd7 NotUsed NotUsed DE Revision 0 1A Page 43 of 53 MSC ET e GLX CPU User s Manual Display Connection Odd Channel 3 RedOdd0 RedOdd1 GreenOdd1 BlueOdd0 BlueOdd1 NotUsed Even Channel 0 RedEven2 RedEven3 RedEven4 RedEven5 RedEven6 RedEven7 GreenEven2 Even Channel 1 GreenEven3 GreenEven4 GreenEven5 GreenEven6 GreenEven7 BlueEven2 BlueEven3 Even Channel 2 BlueEven4 5 BlueEven6 BlueEven7 HSync VSync DE Even Channel 3 RedEvenO RedEvenl GreenEvenO GreenEvenl BlueEvenO BlueEvenl1 NotUsed Identification Data Control with LVDS physics Graphics Controller Power Sequencing Principle of display connection with LVDS components Revision 0 1A Page 44 of 53 MSC ET e GLX CPU User s Manual Display Connection Identification Data Control with LVDS physics LVDS to TTL Converter Graphics Controller Power Sequencing Display Power TTL Switch Principle of display connection with LVDS controller and TTL display 8 1 2 TTL Interface The TTL interface is preferred in applications where
30. gnal and Pin Out Description 5 3 ET e Connector X3 VGA LCD Video COMx LPT Floppy Keyboard Mouse IRDA Signal Description Note VCC Power Supply 5 VDC 5 I external supply GND Power Ground I external supply N C Not connected Do not connect LTGIOO 2 General Purpose IO Signal Description of analog CRT signals Note HSYNC Horinzontal Synchronimpuls VSYNC Vertikal Synchronimpuls R Red channel RGB Analog Video Output Green channel RGB Analog Video Output Blue channel RGB Analog Video Output DDCK Display Data Channel Clock BV3 signal level 5 0 compliant DDDA Display Data Channel Data 3V3 signal level 5VO compliant Signal Description of TV signals option Note SYNC Composite sync Y Luminance for S Video or Red for SCART Chrominance for S Video or Green for SCART Composite Video or Blue for SCART Signal Description of signals Note DTR1 2 Data terminal ready of COM1 COM2 5VO signal level RI1 2 Ring indicator of COM1 COM2 I 5V0 compliant TXD1 2 Data transmit of COM1 COM2 O 5VO signal level RXDI 2 Data receive of COMI COM2 I 5V0 compliant CTS1 2 Clear to send of COM1 COM2 I 5 V0 compliant RTS1 2 Request to send of COM1 COM2 5VO signal level DCD1 2 Data carrier detect of COM1 COM2 I 5 V0 comp
31. initialize VGA BIOS D4h Initialize LCD Panel D5h Display splash screen D6h Hard Disk Drive Initialize D7h System option ROM scan and initialize PCI32 fixup DEh romCopy exit 15h Wiggle cache if MTEST enabled cache remains off 82h Additional BDA initialization CMOS initialization 17h Scan PCI bus and enumerate 18h Scan and call options ROMs from C800 EFFO 19h Reset all descriptors to real mode 1 size 81h User added code to be run right before boot 1Ah Display summary screen 1Bh Attempt boot via INT 18h then INT 19h 1Fh Boot failure system halted Revision 0 1A Page 53 of 53
32. iption of Audio Signals Note SNDL Line Level stereo output left SNDR Line Level stereo output right AUXAL Auxiliary input A left I AUXAR Auxiliary input A right I MIC Microphone input I ASGND Analog ground of sound controller I ASVCC Analog supply of sound controller I Revision 0 1A Page 24 of 53 MSC ET e GLX CPU User s Manual Signal and Pin Out Description Pin Signal Pin Signal Pin Signal Pin Signal 1 GND GND 51 VCC 52 VCC 3 PCICLK3 PCICLK4 53 PAR 54 SERR 5 GND GND 55 GPERR 56 Reserved 7 PCICLK1 8 PCICLK2 57 PME 58 USB2 9 REQ3 10 GNT3 59 LOCK 60 DEVSEL 11 GNT2 12 3V 61 TRDY 62 USB3 13 REQ2 14 GNT1 63 IRDY 64 STOP 15 1 16 3 65 FRAME 66 USB2 17 GNTO 18 RESERVED 67 GND 68 GND 19 VCC 20 VCC 69 16 70 21 RIRQ 22 REQO 71 AD17 72 USB3 23 ADO 24 3V 73 19 74 AD18 25 26 AD2 75 AD20 76 USBO 27 AD4 28 AD3 77 22 78 AD21 29 AD6 30 ADS 79 AD23 80 5 1 31 CBEO 32 AD7 81 AD24 82 CBE3 33 AD8 34 AD9 83 VCC 84 35 GND 36 GND 85 AD25 86 AD26 37 AD10 38 AUXAL 87 AD28 88 USBO 39 ADII 40 MIC 89 AD27 90 AD29 41 2 42 AUXAR 91 AD30 92 USBI 43 AD13 44 ASVCC 93 PCIRST 94 AD31 45 14 46 SNDL 95 INTC 96 INTD 47 15 48 ASGND 97 INTA 98 INTB 49 1 50 SNDR 99 GND 100 GND Revision 0 1A Page 25 of 53 MSC ET e GLX CPU User
33. isplay Note STN or DSTN displays not supported by the ET e GLX module To use D STN displays an additional converter chip is required Ask MSC support for more information LVDS Display Signals TTL Display Interface Pin Signal Pin Signal Pin Signal Pin Signal 1 GND 2 GND 1 GND 2 GND 3 4 3 4 5 6 5 7 8 7 8 9 DETECT 10 9 DETECT 10 11 LCDDO16 12 LCDDO18 11 B4 12 SHFCLK 13 LCDDO17 14 LCDDO19 13 5 14 EN 15 GND 16 GND 15 GND 16 GND 17 LCDDO13 18 LCDDOI5 17 Bl 18 B3 19 LCDDO12 20 LCDDO14 19 BO 20 B2 21 GND 22 GND 21 GND 22 GND 23 LCDDO8 24 LCDDO11 23 G2 24 G5 25 LCDDO9 26 LCDDO10 25 G3 26 G4 27 GND 28 GND 27 GND 28 GND 29 LCDDO4 30 LCDDO7 29 R4 30 Gl 31 LCDDOS5 32 LCDDO6 31 R5 32 GO 33 GND 34 GND 33 GND 34 GND 35 LCDDOI 36 LCDDO3 35 36 R3 37 LCDDOO 38 LCDDO2 37 RO 38 R2 39 VCC 40 VCC 39 VCC 40 VCC 41 FPDDC_DAT 42 LTGIOO 41 FPDDC_DAT 42 VSYNC 43 FPDDC_CLK 44 BLON 43 FPDDC_CLK 44 BLON 45 BIASON 46 DIGON 45 HSYNC 46 DIGON 47 48 47 48 49 50 49 50 Revision 0 1A Page 42 of 53 MSC ET e GLX CPU User s Manual Display Connection The signals are divided into four groups Pixel information signals Image control signals Identification Power and backlight control signals Power and ground Si eben Depending on the interface type the signals of 1 and 2 are electrically LVDS or TTL signals Identific
34. l Port 1 Serial Port 2 Disabled 3f8h 2f8h 3e8 2e8h IRQ 3 4 Disabled Configure the onboard UART Parallel Port A Disabled 378h 278h 3BCh Configure the onboard Parallel Port Address MODE Compatible PS 2 Bi directional EPP 1 7 EPP 1 9 ECP Configure the mode of the onboard Parallel Port IRQ Disabled IRQ 5 IRQ7 IRQ9 IRQ 10 IRQ 11 Configure the IRQ Used by the onboard Parallel Port DMA None Channel 1 Channel 3 Configure the DMA channel used in ECP mode ISA Bus IRQ Menu ISA disabled Configure each IRQ as ISA or disabled IRQs used by other devices in BIOS setup are grayed out Watchdog Cyclic Timeout Minutes to wait O disable 1 255 Enable disable watchdog and set cyclic timeout minutes Setting 0 disables Watchdogtimer Every other value sets delay to n minutes starting with next boot Watchdog Start Delay Minutes to wait 1 255 0 same as Watchdog Cyclic Timeout Enable disable watchdog initial timeout minutes This timeout is the value for the first WDT timeout in system Setting timeout to 0 results in delay value is used for timeout Every other value sets timeout to n minutes starting with next boot Enabling Parallel Port A only enables the chipset device Using the parallel port requires a correct setting of LPT FLPY to high level LPT or Floppy Interface configuration input If you use an IRQ for the ISA bu
35. liant DSR1 2 Data set ready of COM1 COM2 I 5 V0 compliant Signal Description of keyboard and infrared signals Note KBDAT Keyboard Data 5VO signal level KBCLK Keyboard Clock 5VO signal level MSDAT Mouse Data IO 5VO signal level MSCLK Mouse Clock 5 VO signal level IRTX Infrared Transmit 5VO signal level Revision 0 1A Page 28 of 53 MSC ET e GLX CPU User s Manual Signal and Pin Out Description IRRX Infrared Receive I Signal Description of FDC signals shared with LPT Note LPT FLPY LPT or Floppy Interface configuration input I Connect to GND STB RES AFD DENSEL density select low 250 300Kb s high 5VO signal level 500 1000Kb s PDO INDEX Index signal I 5 V0 compliant PD1 TRKO Track signal I 5 V0 compliant PD2 WP Write protect signal I 5 V0 compliant PD3 RDATA Raw data read I 5 V0 compliant PD4 DSKCHG Disc changed I 5 V0 compliant PDS5 RES PD6 RES ne PD7 RES ne ERR HDSEL Head select 5VO signal level INIT DIR Direction 5VO signal level SLIN STEP Motor step 5VO signal level ACK DRVI Drive 1 select 5VO signal level BUSY MOT1 Motor select 5VO signal level PE WDATA Raw write data 5VO signal level SLCT WGATE Write enable 5VO signal level Signal Description of LPT signals shared with FDC
36. mainboards will typically not provide a POWER BUTTON signal Ask your MSC support for details on this topic For application with extremely low power budgets the GLX module provides a Suspend To Ram Standby Mode Typical Power Consumption values for the GLX module are CPU Mode Power Consumption 5V Power Consumption 5V StandBy Windows XP Idle 4W 1W Windows XP maximum 5 W 1 5 W CPU and MEM usage Suspend To RAM OW 0 133 W Revision 0 1A Page 50 of 53 MSC ET e GLX CPU User s Manual Display Connection 10 External ports COM3 and COM4 The BIOS supports external COM ports COM3 and residing in a SMSC37C669 super IO chip These ports have to be enabled in BIOS setup before use The installation procedure is Disable ports COM3 and COM4 in the BIOS setup Install Windows with at least the hardware drivers for Ethernet Audio and Video Reboot and enter BIOS setup Enable the ports in the BIOS setup 0x3e8 IRQIO 0x2e8 Check that no PCI interrupt conflicts with any ISA interrupt Install the COM ports under Windows as new but known hardware using windows own drivers 11 Windows Installation Hints Sometimes Windows especially Windows XP cannot be installed from USB CD Rom drive to CF Card In most cases formatting the CF card or copying files fails e If formatting fails it may help to format the CF card using Windows 2000 FAT32 a norm
37. mpliant GNTO 3 PCI bus grant O ADO 31 PCI Adress Databus PCI signals not 5VO compliant CBEO 3 PCI bus command byte enables PCI signals not 5VO compliant PAR PCI bus parity IO PCI signals not 5VO compliant SERR PCI bus system error PCI signals not 5VO compliant GPERR PCI bus grant parity error IO PCI signals not 5VO compliant PME PCI bus power management event Not supported LOCK PCI bus lock PCI signals not 5VO compliant DEVSEL PCI bus device select IO PCI signals not 5VO compliant TRDY PCI bus target ready PCI signals not 5VO compliant IRDY PCI bus initiator ready PCI signals not 5VO compliant STOP PCI bus stop PCI signals not 5 0 compliant FRAME PCI bus frame PCI signals not 5 0 compliant PCIRST PCI bus reset Asserted with power on reset ext reset input and CPU reset INTA PCI bus interrupt A I PCI signals not 5VO compliant INTB PCI bus interrupt B I PCI signals not 5VO compliant Revision 0 1A Page 23 of 53 MSC ET e GLX CPU User s Manual Signal and Pin Out Description INTC PCI bus interrupt C I PCI signals not 5 0 compliant INTD PCI bus interrupt D I PCI signals not 5 0 compliant Signal Description of USB Signals Note USBO USB Port 0 USBO USB1 USB Port 1 USB 1 USB2 USB Port 2 USB2 USB3 USB Port 3 USB3 Signal Descr
38. n Out Description Pin Signal Pin Signal Pin Signal Pin Signal 1 GND GND 51 LPT FLPY 52 RESERVED 3 R B 53 VCC 54 GND 5 HSY G 55 STB RES 56 AFD DENSE L 7 VSY 8 DDCK 57 RESERVED 58 PD7 RES 9 DETECT 10 DDDA 59 IRRX 60 ERR HDSEL 11 LCDDO 6 12 LCDDO18 61 IRTX 62 PD6 RES SHFCLK 13 LCDDO17 B5 14 LCDDO19 63 RXD2 64 INIT DIR EN 15 GND 16 GND 65 GND 66 GND 17 LCDDO13 B1 18 LCDDO15 B3 67 RTS2 68 PDS RES 19 LCDDO12 20 LCDDOI 4A B2 69 DTR2 70 SLIN STEP 21 GND 22 GND 71 DCD2 72 PD4 DSKCHG 23 LCDDO8 G2 24 LCDDO11 G5 73 DSR2 74 PD3 RDATA 25 LCDDO9 G3 26 LCDDO10 04 75 CTS2 76 PD2 WP 27 GND 28 GND 77 TXD2 78 PD1 TRKO 29 LCDDO4 R4 30 LCDDO7 G1 79 RD 80 PDO INDEX 31 LCDDOS5 R5 32 LCDDO6 G0 81 VCC 82 VCC 33 GND 34 GND 83 84 ACK DRV1 35 LCDDO1 R1 36 LCDDO3 R3 85 RTS1 86 BUS Y MOT1 37 LCDDOO RO 38 LCDDO2 R2 87 DTRI 88 PE WDATA 39 VCC 40 VCC 89 DCD1 90 SLCT WGAT E 41 FPDDC_DAT 42 LTGIOO 91 92 MSCLK VSYNC 43 FPDDC_CLK 44 BLON 93 CTS1 94 MSDAT 45 BIASON 46 DIGON 95 TXDI 96 KBCLK HSYNC 47 COMP 48 Y 97 RII 98 KBDAT 49 SYNC 50 C 99 GND 100 GND Revision 0 1A Page 31 of 53 MSC ET e GLX CPU User s Manual Signal and Pin Out Description 5 4 Connector X4 IDE Ethernet Miscellaneous
39. nd ext reset input not with CPU reset DREQO 1 2 3 ISA DMA request I 5 V0 compliant 5 6 7 DACK 0 1 2 ISA DMA acknowledge 5 VO signal level 3 5 6 7 TC ISA DMA end 5VO signal level IRQO3 7 ISA Interrupt request 5VO signal level 5VO 9 15 compliant Revision 0 1A Page 26 of 53 MSC ET e GLX CPU User s Manual Signal and Pin Out Description Pin Signal Pin Signal Pin Signal Pin Signal 1 GND GND 51 VCC 52 VCC 3 SD14 SD15 53 SA6 54 5 5 SD13 NC 55 SAT 56 IRQ6 MASTER 7 SD12 8 DREQ7 57 SA8 58 IRQ7 9 SD11 10 DACK7 59 SA9 60 SYSCLK 11 SD10 12 DREQ6 61 5 10 62 REFSH 13 SD9 14 DACK6 63 SA11 64 DREQI 15 SD8 16 DREQ5 65 SA12 66 DACK1 17 MEMW 18 DACKS5 67 GND 68 GND 19 MEMR 20 DREQO 69 5 13 70 DREQ3 21 LA17 22 DACKO 71 5 14 72 DACK3 23 LA18 24 IRQ14 73 SAI5 74 IOR 25 19 26 15 75 SA16 76 IOW 27 LA20 28 IRQ12 77 5 18 78 5 17 29 LA21 30 IRQI1I 79 5 19 80 SMEMR 31 LA22 32 10 81 IOCHRDY 82 AEN 33 LA23 34 1016 83 VCC 84 VCC 35 GND 36 GND 85 SDO 86 SMEMW 37 SBHE 38 M16 87 SD2 88 SD1 39 5 0 40 OSC 89 SD3 90 NOWS 41 5 1 42 BALE 91 DREQ2 92 SD4 43 SA2 44 TC 93 SD5 94 IRQ9 45 SA3 46 DACK2 95 SD6 96 SD7 47 SA4 48 IRQ3 97 IOCHK 98 RSTDRV 49 5 5 50 4 99 GND 100 GND Revision 0 1A Page 27 of 53 MSC ET e GLX CPU User s Manual Si
40. ntroller Ethernet Interface Sound Controller Sound Interface Real Time Clock Watchdog Timer SM Bus support Revision 0 1A MSC ET e GLX AMD GEODE LX 800 0 9W BGA481 500 MHz slower speeds may be configured via BIOS 64Kbyte Level 1 I 64Kbyte Level 1 D 128Kbyte Level 2 CS5536 Geode Companion BGA208 Winbond 83627HF max 1024 MByte DDR SDRAM SO DIMM 200pin One enhanced IDE ports one channel two devices Optional CompactFlash Interface Type I using one IDE Channel Floppy Interface shared with LPT ECP EPP shared with Floppy 2x TTL 16550 compatible IrDA 1 0 compliant port currently not supported by BIOS PS 2 PS 2 4 x USB 2 0 32Bit 33MHz 3V3only Standard one external PCI Master with option Arbiter Extension up to four external PCI Master Integrated in CPU TBD CRT max 1 920x1 440x32 bpp 85Hz LCD max 1 600x1 200x32 bpp 60Hz TFT CRT option TTL 18 24 Bit TTL Level Interface option LVDS 18 Bit LVDS Interface support of 24 Bit LVDS Displays has to be checked for each display in detail option TV Out onboard TV controller with CRT DDC Display Data Channel with FPDDC Flat Panel Display Data Channel Intel 82551 10 or 100 MHz with auto detection 97 compliant with external Codec LM4549 Line level input output and Microphone via ETX header yes companion 55536 yes companion 55536 yes Page 21 of 53 MSC ET e GLX CPU User s Manual Technical Specification
41. oard a kind of motherboard including the standard PC interfaces as well as additional connectors and features The board is referred to as MSC and provides the following features e four PCI Slots three ISA Slots two EIDE channels one CompactFlash connector on secondary EIDE channel two interfaces for floppy disk drives RJ45 connector for Ethernet four USB interfaces PS 2 connectors for keyboard and mouse two parallel interfaces four serial interfaces 15 DSUB connector for VGA analogue Video Out interface FPDDC compatible to JILI JUMPtec Intelligent LVDS Interface Revision 0 1A Page 5 of 53 MSC ET e GLX CPU User s Manual General Information flex foil connector for LCD interface three 3 5mm connector for microphone line in and line out two connectors for powered audio signals one IrDA interface 16 bit general purpose Data IO Onboard Port80h display Use the MSC board as design reference for your baseboard Ask MSC for the schematics and additional information The schematics are available in PDF and OrCAD format They are free of charge 1 2 Technical Information This document is based on the following references 1 Datasheet AMD GEODE LX Processor 2 Datasheet AMD CS5536 Companion 3 Datasheet Winbond W83627HF Super IO 4 Datasheet Winbond W83626F LPC to ISA Bridge 5 Datasheet Intel 82551 Fast Ethernet Controller 6 PCI Bus Specification 7 ISA Bus Spe
42. ress and control drive clear reference timer and VGA wrap 73h Set the register to indicate no DIMMs installed 74h Default CAS latency to 3 75h or 7Fh Memory sizing 7Fh No memory located 76h Do refresh 7Eh MemSetup exit 07h Setup stack 90h or 9Fh Create stac Stac k reation failure 9Eh Stack setup exit 08h Test memory address lines BOh Test memory BEh Memory test exit BFh Memory test failed i e BOh 09h Copy ROM from F000 0000 to RAM at F000 0000 SDRAM optimization for CPU speed OBh Autosize and initialize Cache CFh Cache failed to size to 16 KB 1 OBh failed OCh Load Geode North Bridge PCI register space E8h Begin register initialize Load CS55x0 with values aka south bridge EOh Begin register initialize OEh SIO test initialize 60h SIO test entry 61h SIO present register initialize 6Eh SIO test exit OFh Various PC BIOS compatibility pieces 10h Set up generici nterrupt table 16h Set up BDA for installed hardware 1th Query memory controller for RAM size and store it 14h Wakeup the keyboard controller 12h SMI Handler video keyboard hard drives splash screen LCD DOh Get shadow ready for copy Dih Decompress all images D2h Call SMI Handler initialization code Revision 0 1A Page 52 of 53 MSC ET e GLX CPU User s Manual Display Connection D3h Return from SMI Handler
43. ring USB 2 0 OHCI Enable Enable Disable OHCI PCI header Disable USB 2 0 EHCI Enable Enable Disable EHCI PCI header Disable USB Legacy Support Enable Enable Disable USB Legacy Support after BIOS Disable starts booting to OS 3 1 3 7 Network Configuration Menu Item Options Comment Network boot Enable Enable Disable network boot Disable 3 1 3 8 Thermal Configuration Menu Item Options Comment Current CPU Temperature Current Ambient Temp Current Board Temperature Every key return reads the current temperature Revision 0 1A Page 16 of 53 MSC ET e GLX CPU User s Manual BIOS Description 3 1 4 Memory an Cache Optimization Menu Item Options Comment Cache Enable Enable Enables Disables the memory cache Disable Cache Mode Write Back Select the memory cache mode Write Through Cache Allocate Enable Disable Memory Optimization Auto for information only CAS Latency Auto for information only Refresh Rate Auto for information only Memory Latencies Auto for information only 3 1 5 System Clock PLL Configuration Menu Item Options Comment Clock Determined By Manual Settings Usage of below defined PLL settings CPU Multiplier 7 15 Multiplier 33Mhz CPU Speed GeodeLink Multiplier 7 10 Multiplier 33Mhz Geode Link Speed 3 1 6 Power Management Menu Item Options Comment
44. s 32Bit buswidth at 33MHz clock rate The ET e GLX module supports up to 4 external bus master Note The PCI bus on the Geode LX module is not 5V TTL tolerant Refer to 6 for information in detail ISA Bus The ISA bus meets the ISA bus specification with some restrictions ISA Bus Masters are not supported and 16 Bit wide I O and Memory R W accesses are split into two consecutive 8 Bit wide accesses Refer to 4 and 7 for information in detail Note The ISA bus signals are generated by the Winbond 83626 LPC to ISA Bridge Revision 0 1A Page 9 of 53 MSC ET e GLX CPU User s Manual Module Description 27 USB Ports The USB Ports are over current protected All four USB ports are supported by the GLX module The USB ports meet the USB2 0 specification Refer to 2 for information in detail 2 8 IDE Interfaces One enhanced IDE port with two devices one master one slave is supported Refer to 2 for information in detail Do not connect to primary and secondary IDE port at the same time Both ports of the ET e connector are led to the same IDE port on the module If the on board CF Card connector is used then connect the slave device CF Card is master to your baseboard s secondary IDE connector If two external IDE devices are used connect both devices to either your baseboards primary or secondary channel Do not use one device on primary one device on secondary channel Currently boot is only possible from IDE master
45. s Manual 5 2 ET e Connector X2 ISA Bus Signal and Pin Out Description Signal Description Note VCC Power Supply 5 VDC 5 I external supply GND Power Ground I external supply N C Not connected n a Do not connect Signal Description of ISA Bus Signals T O Note SDO 15 ISA Databus VO 5VO signal level 5V0 compliant SAO 19 ISA Addressbus 15 5VO signal level SBHE ISA Byte High Enable 5VO signal level BALE ISA Address Latch Enable 5VO signal level AEN ISA Address Enable 5VO signal level MEMR ISA memory read 5VO signal level SMEMR ISA memory read in lowest 1MB address range 5VO signal level MEMW ISA memory write 5VO signal level SMEMW ISA memory write in lowest 1MB address range 5VO signal level IOR ISA IO read 5VO signal level IOW ISA IO write O 5VO signal level IOCHK ISA IO check I 5 V0 compliant IOCHRDY ISA IO channel ready I 5 VO compliant M16 ISA 16Bit memory device I 5 V0 compliant IO16 ISA 16Bit IO device I 5V0 compliant REFSH ISA memory refresh cycle pending 5VO signal level NOWS ISA Now waitstates I 5 V0 compliant MASTER ISA Master supported ET e SYSCLK ISA System clock 8 MHz 5 VO signal level OSC ISA Oscilator 14 31818 MHz 5 VO signal level ISA Reset signal Asserted with power on reset a
46. s you must not use this IRQ for any PCI interrupt 3 1 3 3 External Super I O Configuration Menu Item Options Comment Serial Port C Serial Port D Disabled 3f8h 2f8h 3e8 2e8h IRQ 10 11 Disabled Configure the external UART Parallel Port B Disabled 378h 278h 3BCh Configure the onboard Parallel Port Address MODE Printer Mode SPP EPP 1 9 and SPP EPP 1 7 and SPP ECP ECP and EPP 1 9 Configure the mode of the onboard Parallel Port Revision 0 1A Page 14 of 53 MSC ET e GLX CPU User s Manual BIOS Description ECP and EPP 1 7 IRQ IRQ5 Configure the IRQ Used by the onboard Parallel IRQ7 Port DMA None Configure the DMA channel used in ECP mode Channel 2 Channel 1 Enter External Super I O Configuration requires a base board with external SMSC C669 SIO 3 1 3 4 Video and Flat Panel Configuration Menu Panel and CRT Item Options Comment Internal Adaptor Mode Disabled Configures the primary display if using a PCI Primary VGA adapter Secondary Video Memory 2 0MB 254MB Select the amount of memory to reserve for video Output Display CRT Select display type Flat Panel Driver controls init Enabled Disabled If enabled OS driver has to initialize graphics HW Flat Panel Configuration Configures the flat panel 3 1 3 5 Flat Output Configuration Item Options Comment Type EDID 2 0
47. signal is active low while the DIGON signal is active high Revision 0 1A Page 46 of 53 MSC ET e GLX CPU User s Manual 8 1 4 Signals ET e Module lt gt TFT Display with TTL Signalling X3 LCD Interface TFT TTL Connection ET e Module Connect to Net Name Number Net Name Number LCD_VSYNC 42 lt gt VSYNC 4 LCDDOO_RO 37 lt gt RO 4 LCDDO1 R1 35 lt gt 4 LCD_ENVDD DIGON 46 PowerSwitch 1 LCDDO2 R2 38 lt gt R2 4 LCDDO3_R3 36 lt gt R3 4 LCD_HSYNC 45 lt gt HSYNC 4 LCDDO4_R4 29 lt gt R4 4 LCDDO5 R5 31 lt gt R5 4 GND 1 lt gt GND 4 LCDDO6 GO 32 lt gt GO 4 LCDDO7 G1 30 lt gt G1 4 GND 1 lt gt DPS 1 LCDDOS8 G2 23 lt gt G2 4 LCDDO9 25 lt gt G3 4 FPDDC_DAT 41 lt gt LCDDO10 G4 26 lt gt G4 4 LCDDO11 G5 24 lt gt G5 4 FPDDC_CLK 43 lt gt LCDDO12 BO 19 lt gt 0 4 LCDDO 13 B1 17 lt gt B1 4 DETECT 9 lt gt LCDDO14 B2 20 lt gt B2 4 LCDDO15 B3 18 lt gt B3 4 GND 1 lt gt GND 1 LCDDO16 B4 11 lt gt 4 74 LCDDO17_B5 13 lt gt 5 4 GND 1 lt gt GND 1 LCD SHFCLK 12 lt gt CLK 4 LCD_EN 14 lt gt DE 4 BLON 2 PowerSwitch 2 GND 1 lt gt GND 1 GND 1 lt gt GND 1 VCC via Power VCC 5V 3V3 2 PowerSwitch 1 Switch 4 12 3 PowerSwitch 2 VCC 12VDC 4 1 connect to Ground 2 connect to 5VDC or 3V3DC as required
48. te the new setting AC Beeper Disabled Enables disables PC speaker Enabled CMOS Option Configuration 0 20 Number of failed boots before reset CMOS data After a number of failed boots the CMOS data becomes resetted to BIOS default values 3 1 8 Boot Order Item Options Comment l None Specifies first boot device Floppy Disk USB Floppy Disk Hard Drive Master Hard Drive Slave CD ROM Drive USB Hard Drive Flash USB CD ROM Drive 2 Same as above Specifies second boot device 3 Same as above Specifies third boot device 4 Same as above Specifies fourth boot device 5 Same as above Specifies fifth boot device 6 Same as above Specifies sixth boot device 3 9 Password Settings Item Options Comment Use Setup Password Disabled Disable Enable Call for Password Enabled Edit Password Password characters 1 64 Type in password two times Revision 0 1A Page 18 of 53 MSC ET e GLX CPU User s Manual BIOS Description 3 2 Network Boot Menu If network boot is enabled in Bios Setup it can be configured by pressing CTRL S during POST A network boot menu Intel Boot Agent FE v4 1 16 is shown with the following settings Item Options Comment Network Boot Protocol PXE Only this setting available Boot Order Try network first then local drives Select the position of the network boot in the Try local drives first then network boot
49. tem If on the Space bottom item will highlight the top item Left arrow Highlight the item to the left of the currently highlighted item If there is no item directly to the left the rightmost item on the previous line is highlighted Right Arrow Highlight the item to the right of the currently highlighted item If there is no item directly to the right the leftmost item on the next line will be highlighted Enter or a Select the currently highlighted item This will cycle through the highlighted 1 Choices for an item or bring up an entry box for direct entry of a character of an value depending on how the item is configured item F1 Will display a Long Help for the currently highlighted item It there is no Long Help for the item the Short Help will be displayed Escape Will close the current menu and return to the previous menu If there is no previous menu this key will do nothing Revision 0 1A Page 11 of 53 MSC ET e GLX CPU User s Manual BIOS Description 3 1 2 Setup Main Menu When entering Setup this is the first menu displayed Typing one of these These two entries will highlighted letters will allow you to adjust These entnes will take directly select the item the current Date and you to other menus preceded by that letter Time in the RTC L Main Menu 11 32 53 Date 86 18 2888 Motherboard Device Configuration This entry allows
50. the distance between module and display is below 30 cm because TTL displays are cheaper than LVDS displays Pay attention to lead the signal cable in distance to electro magnetic noise to ensure a proper display quality In some cases a cable shield is needed to meet the EMC requirements Identification Data Control with TTL physics Graphics Controller Power Sequencing Display TTL Principle of display connection with TTL controller and TTL display Revision 0 1A Page 45 of 53 MSC ET e GLX CPU User s Manual Display Connection 8 1 3 Power Switch Most flat panel displays need a special power sequencing For these displays a power switch is needed which is not a part of the ET e module and usually located on the carrier board the board which carries the ET e module The power switch is controlled by the ET e module via the signal DIGON The ET e module ensures that the signal voltage of the data and control signals is only applied if the display power is switched on 205 LCD ENVDD 21 11 K 00301 BC847C Example of a power switch The signal LCD ENVDD corresponds with the DIGON signal Most backlight inverter provides an enable input to control the light In this case use the BLON to control the inverter is active low If there is no enable input a similar circuit is needed for the switch of the 12VDC backlight supply Note an additional inverter is needed see power switch figure because the BLON
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