AU9412EEP USB Keyboard/Hub Controller Technical Reference
Contents
1. 5 4 0 System Architecture and Reference Design ess 10 4 1 AU9412EEP Block Diagram nennen ener enne 10 4 2 Sample Schematics cede Eee te deed ete e EE Rd 10 4 3 Sample Key Matrix Layout Table 10 5 0 Electrical 22 2 45 24 10 5 1 Maximum Ratings esses neret 10 5 2 Recommended Operating Conditions 10 5 3 Crystal Oscillator Circuit Setup for Characterization esses 10 5 4 USB Transceiver Characteristics eese nennen 10 5 5 ESD Test Results ome pete Dette cre re ORE Tee RE 10 5 6 Lateh Up Test Results 8 pee diee ten pm UIS re RI 10 6 0 Mechanical Information eccL LLL 10 TABLE OF CONTENTS 1 0 Introduction 1 1 Description The AU9412EEP is an integrated USB keyboard and 2 port hub controller chip The AU9412EEP has a built in default keyboard matrix so that it can be directly connected to an 18 x 8 keyboard matrix The keyboard matrix can be customized via an optional external 512 byte serial EEPROM Downstream ports can be used to connect various USB peripheral devices such as USB printers modems scanners cameras mice and joysticks to the system without adding external glue logic Single chip integration makes the AU9412EEP the most cost effective k2. D2 P il R14 gt RIS USB A DP2 AMAR 4 D3 15K gt 15K 1K AAA LED 1K R18 LED LED 1M E y CRYSTAL 12 Mhz R19 150 ce c7 DOUT GND 1593 66 3 eee ii SYSTEM ARCHITECTURE AND REFERENCE DESIGN 4 3 Sample Key Matrix Layout Table This table is the default key matrix The AU9412EEP can support this matrix without an external EEPROM Table 4 1 AU9412 Built in Key Matrix Kpd Home Kpd 4 SYSTEM ARCHITECTURE AND REFERENCE DESIGN 13 This Page Intentionally Left Blank 14 SYSTEM ARCHITECTURE AND REFERENCE DESIGN 5 0 Electrical Characteristics 5 1 Maximum Ratings Absolute Maximum Ratings VALUES PARAMETER MIN MAX Ambient Operating Temperatures 0 70 C Storage Temperature 40 C 185 Supply Voltage Vdd 0 3V 7 0V 5 2 Recommended Operating Conditions The following table gives the recommended operating conditions for integrated circuits developed with the pad libraries Symbol Param Min Max VoD Note V Low level 0 5V 0 8V 4 5V to Guaranteed Input Low input voltage 5 5V Voltage Vin High level 2 0V Vppt0 5V 4 5V to Guaranteed Input High input voltage 5 5 Voltage Vor Low level 0 4V 4 5V Io 2 to 24 mA TTL output voltage depending on Cell VoH High level 24 4 5V Ion 2 to 24mA TTL output voltage depending on Cell Supply current 20 25 mA 4 5V
3. Vcc 15 mA for VP VM and RCV pins V DC output source or sink Vo 0 to Vcc 50 mA current for D D pins ll DC Vcc or GND current 100 mA Ta Storage temperature range 60 150 C P Power dissipation per package mW NOTES 1 Stresses beyond those listed may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicted under Recommended Operating Conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 The performance capability of a high performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability The maximum junction temperature of this integrated circuit should not exceed 150 C 3 Theinput and output voltage ratings may be exceeded if the input and output clamp current ratings are observed ELECTRICAL CHARACTERISTICS 17 ELECTRICAL CHARACTERISTICS Over recommended operating conditions Voltages are referenced to GND Ground 0V LIMITS SYMBOL PARAMETER TEST CONDITIONS 40 C to 86 C UNIT MIN TYP MAX VHYS Hysteresis on inputs Vcc 3 0V to 3 6V 5 2 4 3 50 4 V VIH HIGH level input Vcc 3 0V to 3 6V 15 20 V VIL LOW level input Vcc 3 0V to 3 6V 0 5 11 V RoH Output impedance HIGH Note 2 28 3
4. tfall Low Speed 75 200 75 200 tRFM Rise and Fall Time 70 130 70 130 Matching Low Speed D D to RCV 3 9 16 16 ns tpHL 9 16 16 tpLH D D to VP VM 1 4 8 8 ns tpHL 4 8 8 tpHZ 12 12 ns tpZH OE to D D RL 4 12 12 tpLZ 500 10 10 tpZL 10 10 Setup for SPEED 5 0 ns Vcp Crossover point 3 1 3 2 0 1 3 2 0 V NOTE 1 The crossover point is in the range of 1 3V to 2 5V for the low speed mode with a 5Cpf capacitance ELECTRICAL CHARACTERISTICS 19 WAVEFORM 1 WAVEFORM 5 D D VP VM OR VPO VMO TO D D SETUP FOR SPEED toy e OUTPUT 50 WAVEFORM 2 D D VP VM OR VPO VMO TO D D LOAD FOR VM VP AND RCV gt 14 TEST POINT D U T 25pF gt VoL WAVEFORM 3 D D TO RCV LOAD FOR ENABLE AND DISABLE TIMES Bese 20V TEST POINT 24 500W DE 40V 50pF x 2 L4 lt 5 8 lt V 0FORt pzp triz V Vcc FORtpz triz WAVEFORM 4 OE TO D D LOAD FOR D D 28 gay TESTPOINT ATO 15kW TS TEST 1 51 0 18 CLOSE C 50pF FULL SPEED C 50pF LOW SPEED MIN TIMING burs CLOSE 350pF LOW SPEED MAX TIMING 1 5KW ON D LOW SPEED OR D FULL SPEED ONLY ELECTRICAL CHARACTERISTICS 5 5 ESD Test Results Test Description ESD Testing was performed on a Zapmaster system using t
5. 4 DP VO USB D for downstream port 1 Add 15KQ pull down to ground 6 PIN ASSIGNMENT USB1_DM Table 3 1 continued Pin Descriptions 1 0 Description USB D for downstream port 1 Add 15KQ pull down to ground SCANI 1 Matrix scan line internal 3 3k pull up SCANI 2 Matrix scan line internal 3 3k pull up SCANI 3 Matrix scan line internal 3 3k pull up SCANI 4 Matrix scan line internal 3 3k pull up SCANI 5 Matrix scan line internal 3 3k pull up SCANI 6 Matrix scan line internal 3 3k pull up SCANI 7 DIN Input Matrix scan line internal 3 3k pull up Output EEPROM data in connect to EEPROM DIN pin 2 mA SCANI 8 EEP CLK SCR LOCK Input Matrix scan line internal 3 3k pull up Output Clock for EEPROM 2 mA Scroll Lock LED Active low 8 mA VDD SCAN2 12 5v power supply Matrix scan line 16 mA internal 33k pull down SCANO2 13 Matrix scan line 16 mA internal 33k pull down SCAN2 14 Matrix scan line 16 mA internal 33k pull down PIN ASSIGNMENT Ping Pin SCAN2 15 Table 3 1 continued Pin Descriptions 1 0 Description Matrix scan line 16 mA internal 33k pull down SCAN2_16 Matrix scan line 16 mA internal 33k pull down SCAN2_17 Matrix scan line 16 mA internal 33k pull down SCAN2_18 Matrix scan line 16 mA internal 33k pull do
6. 4 43 ohm state RoL Output impedance LOW Note 2 28 35 43 ohm state VOH HIGH level output Vcc 3 0V lo 6mA 2 2 2 7 V Vec 3 0V lo 4mA 2 4 Vcc 3 0V 100 2 8 VOL LOW level output Vcc 3 0V lo 6mA 0 3 0 7 V Vec 3 0V lo 4mA 0 4 Vcc 3 0V 100 0 2 IQ Quiecient supply current 3 6 VI Vcc GND 330 600 pA lo 0 Isup Supply current in suspend Vcc 3 6V Vl Vcc GND 70 lo 0 IFS Active supply current Full Vcc 3 3V 9 14 mA Speed ILS Active supply current Low Vcc 3 3V 2 mA Speed ILeak Imput leakage current Vec 3 6V Vl 5 5V or GND not for I O Pins 0 1 0 5 IOFF 3 state output OFF state VI VIN or VII Vo Vcc or 1 VA current GND NOTES 1 All typical values at Vcc 3 3V and 25 2 This value includes an external resistor of 24 ohm 1 details 3 All signals except D and D ELECTRICAL CHARACTERISTICS See Load D and D diagram for testing ELECTRICAL CHARACTERISTICS GND 0V Is 1823 0 C 50pf RL 5000hms SYMBOL PARAMETER TYP WAVFORM 40 to 86 40 C to 86 tpLH VMO VPO to D D 1 0 0 tpHL Full Speed 0 12 0 14 trise Rise and Fall Times 2 4 9 20 4 20 ns tfall Full Speed 4 9 20 4 20 tRFM Rise and Fall Time 90 110 90 110 Matching Full Speed VMO VPO to D D 1 120 300 300 ns tpHL Low Speed 120 300 300 trise Rise and Fall Times 2 75 300 75 300 ns
7. AU9412EEP USB Keyboard Hub Controller Technical Reference Manual Revision 1 03 1998 Alcor Micro Inc All rights reserved Copyright Notice Copyright 1998 Alcor Micro Inc rights Reserved Trademark Acknowledgements The company and product names mentioned in this document may be the trademarks or registered trademarks of their manufacturers Disclaimer Alcor Micro Inc reserves the right to change this product without notice Alcor Micro Inc makes no warranty for the use of its products and bears no responsibility for any errors which appear in this document Specifications are subject to change without notice Contact Information USA Headquarters Los Angeles Alcor Micro Inc Alcor Micro Inc 155A Moffett Park Drive Suite 240 9400 Seventh St Bldg A2 Sunnyvale CA 94089 Rancho Cucamonga CA 91730 Phone 408 541 9700 Phone 909 483 9900 Fax 408 541 0378 Fax 909 944 0464 Taiwan Alcor Micro Inc Taiwan TF No 279 Sec 4 Hsin I Road Taipei Taiwan R O C Phone 886 22 325 9512 Fax 886 22 702 6030 Table of Contents 1 0 Introduction nec 1 1 1 Description epe t rH piece era 1 1 2 SIUS na Eod EE 1 2 0 Application Block Diagram 3 3 0 Pin ASSIGI IMM
8. B DEVICE USB DOWNSTREAM PORT 2 USB DEVICE ALCOR MICRO ds AU9412EEP KEYBOARD AND LEDS KEYBOARD SCAN MATRIX NUM LOCK SCROLL LOCK CAP LOCK OPTIONAL 512 BYTE SERIAL EEPROM FOR KEY MATRIX VENDOR ID CUSTOMIZATION KEYBOARD B 00H BEBE APPLICATION BLOCK DIAGRAM This Page Intentionally Left Blank APPLICATION BLOCK DIAGRAM 3 0 Pin Assignment The AU9412EEP is a 48 dual inline package DIP The following figure shows the signal names for each of the pins on the chip The table on the following page describes each of the pin signals PIN ASSIGNMENT VCC3 3 48 CAP LOCK USB DP 47 NUM LOCK USB DM 46 USB2 DP USB1 DP 45 USB2 DM USB1 DM 44 5 2 11 SCAN1_1 43 SCAN2_10 SCAN1_2 42 SCAN2_9 SCAN1_3 ALCOR MICRO SCAN2_8 0 car EE Se USB KBD HUB SCAN1_6 48 PIN 38 SCAN2_5 SCAN1 7 EEP DIN DIP 37 SCAN2 4 SCAN1 8 EEP 36 GND SCR LOCK 35 VDD VDD 34 RESET SCAN2_12 33 GND SCAN2_13 32 PW_SWITCH SCAN2 14 31 5 2 1 SCAN2 15 30 SCAN2 2 SCAN2 16 29 SCAN2 3 SCAN2 17 28 GND ANA SCAN2 18 27 XTAL1 EEP CS 26 XTAL2 EEP_DOUT 25 VDD_ANA Table 3 1 Pin Descriptions Pin Pin Name Description 1 VCC3 3 3 3V output for upstream D pull up 4 mA 2 USB DP USB D for upstream port Need external 1 5KQ pull up to 3 3V 3 USB_DM IO USB D for upstream port
9. K LED Active low 8 mA PIN ASSIGNMENT 9 This Page Intentionally Left Blank PIN ASSIGNMENT 4 0 System Architecture and Reference Design 4 1 AU9412EEP Block Diagram 18 SUSPEND KEYBOARD T9 Row ROOT PORT esport gt usB 4 command RESUME AND SCAN AND 8 RESET SIE PROCESSOR FRAME TIMER FIFO COLUMN gt NUM LOCK LED CONTROL CAP LOCK SCROLL LOCK 256 X 16 ROM 256 X 16 1 is orton 33V VOLTAGE REGULATOR FEPROM CONTROL 12 MHz DOWNSTREAM DOWNSTREAM PORT PORT SYSTEM ARCHITECTURE AND REFERENCE DESIGN 11 4 2 Sample Schematics Ut MIC2525 2BM TO KEYBOARD COLUMN SCAN LINE TO KEYBOARD ROW SCAN LINE SCAN1_1 SCAN1_2 SCAN1_3 SCAN1 4 SCAN1 5 SCAN1 6 SCAN1_7 EEP_D 5 1 8 EEP CI SCAN2 1 SCAN2 2 SCAN2 3 SCAN2 4 SCAN2 5 SCAN2 6 SCAN2 7 SCAN2 8 SCAN2 9 SCAN2 10 SCAN2 11 SCAN2 12 SCAN2 13 SCAN2 14 SCAN2 15 SCAN2 16 SCAN2 17 SCAN2 18 PW SWITCH Vcc e VDD VDD VDD_ANA VCC3 3 IN LK USB DP USB DM USB DP USB1 DM USB2 DP USB2 DM SCR LOCK LOCK NUM LOCK XTAL1 XTAL2 RESETE EEP CS EEP DOUT Vcc 120uF n 0 1uF 1 2 Vec 3 1 a USB UP c2 10uF J2 1 2 3 4 USB A R5 R6 15K gt 15K mE 2 3 01 Vec T 4 R16 da
10. SOURCE UNTESTED OUTPUT OPEN CIRCUIT UNTESTED INPUT TIED V SUPPLY TRIGGER SOURCE Test Circuit Positive Input Output Overvoltage Overcurrent 22 ELECTRICAL CHARACTERISTICS TRIGGER SOURCE 1 SOURCE lt O UNTESTED INPUT TIED TO V SUPPLY ICC MEASUREMENT O V SUPPLY UNTESTED OUTPUT OPEN CIRCUIT Test Circuit Negative Input Output Overvoltage Overcurrent ICC MEASUREMENT O V SUPPLY UNTESTED OUTPUT OPEN CIRCUIT ALL INPUTS TIED TO V SUPPLY Supply Overvoltage Test Latch Up Data Mode Voltage V Current mA 5 5 Results Vol 11 0 5 Pass otage F 11 0 5 Pass 200 5 Pass Current 200 5 Pass Vdd Vxx 9 0 5 Pass ELECTRICAL CHARACTERISTICS This Page Intentionally Left Blank 24 ELECTRICAL CHARACTERISTICS 6 0 Mechanical Information Following diagram shows the dimensions of Alcor AU9412EEP 48 DIP package Measurements are in millimeters measurements in parenthesis are in inches ALCOR MICRO 13 97 0 550 AU9412EEP 15 88 0 625 48 PIN DIP 4 61 72 2 430 gt 1 91 0 075 482 0 190 A 4 06 0 160 BASE PLANE SEATING PLANE q 1 65 0 065 1 27 0 050 gt 0 46 0 018 ke 2 54 0 100 BSC 13 71 0 540 15 23 0 600 Bsc Die 2502010 MECHANICAL INFORMATION
11. eyboard hub solution available in the market 1 2 Features e Fully compliant with the Universal Serial Bus Specification version 1 0 e USB hub design is compliant with Universal Serial Bus Hub Specification revision 1 1 e USB keyboard design is compliant with USB Device Class Definition for Human Interface Devices HID Firmware Specification version 1 0 e Single chip integrated USB keyboard hub controller with embedded proprietary processor e Integrated USB hub supports two bus powered downstream ports e Patent pending table driven SCANTABLE technology for easy customization to different keyboard matrix e USB vendor ID product ID and keyboard scan code table can be customized via external EEPROM e Built in cost saving default scan code table and vendor ID if customization is not necessary e Built in 3 3v voltage regulator allows single 45V operating voltage drawing directly from USB bus This results in reduced overall system cost e Optional gang powered control pin for downstream port Runsat 12Mhz frequency e Available in 48 pin DIP INTRODUCTION 1 This Page Intentionally Left Blank INTRODUCTION 2 0 Application Block Diagram The AU9412EEP is a single chip which integrates USB keyboard and hub functionality The upstream port is connected to the USB system The downstream ports can be used for a mouse and joystick MOUSE FF JOYSTICK USB HOST SYSTEM USB DOWNSTREAM PORT 1 US
12. he Human Body Model HBM and Machine Model MM according to MIL STD 883 and FIAJ IC 121 respectively e Human Body Model stresses devices by sudden application of a high voltage supplied by 100 capacitor through 1 5k ohm resistance e Machine Model stresses devices by sudden application of a high voltage supplied by a 200pF capacitor through very low 0 ohm resistance Test Circuit amp Condition Zap Interval 1 second Number of Zaps 3 positive and 3 negative at room temperature Criteria I V Curve Tracing ESD Data Model Mode 55 Target Results HBM Vdd Vss 15 2000V PASS MM Vdd Vss 15 200V PASS ELECTRICAL CHARACTERISTICS 21 5 6 Latch Up Test Results Test Description Latch Up testing was performed at room ambient using an IMCS 4600 system which applies a stepped voltage to one pin per device with all other pins open except Vdd and Vss which were biased to 5Volts and ground respectively Testing was started at 5 0V Positive Negative and the DUT was biased for 0 5 seconds If neither the PUT current supply nor the device current supply reached the predefined limit DUT 00mA Icc 100mA then the voltage was increased by 0 1 Volts and the pin was tested again This procedure was recommended by the JEDEC JC 40 2 CMOS Logic standardization committee Notes 1 DUT The device under test 2 PUT The pin under test ICC MEASUREMENT O V SUPPLY 1
13. to 5 5V ELECTRICAL CHARACTERISTICS 15 5 3 Crystal Oscillator Circuit Setup for Characterization The following setup was used to measure the open loop voltage gain for crystal oscillator circuits The feedback resistor serves to bias the circuit at its quiescent operating point and the AC coupling capacitor Cs is much larger than Cl and C2 Rf 100 MEG Cs XIN gt o XOUT si 10pF 10pF 10pF 5 4 USB Transceiver Characteristics RECOMMENDED OPERATING CONDITIONS H OND O MIN MAX Voc DC supply voltage 3 0 3 5 V V DC input voltage range 0 5 5 V Vio DC input range for I Os 0 Voc V Vo DC output voltage range 0 Voc V 1M Operating ambient temperature See DC and AC 0 70 range in free air characteristics for individual device 16 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS 1 2 In accordance with the Absoute Maximum Rating System Voltages are referenced to GND Ground 0v SYMBOL PARAMETER CONDITIONS LIMITS UNIT MIN MAX Vo DC supply voltage 0 5 6 5 V Vi DC input diode current lt 0 50 mA V DC input voltage Note 3 0 5 45 5 V DC input voltage range for I Os 0 5 Vcc V 0 5 Vo DC output diode current gt Vcc or lt 0 50 V DC output voltage Note 3 0 5 Vcc V 40 5 V DC output source sink current Vo 0 to
14. wn EEP_CS Chip select external EEPROM 2 mA EEP_DOUT EEPROM data out connect to EEPROM DOUT pin 2 mA VDD_ANA Analog power connect to 5V XTAL2 Crystal oscillator XTAL out XTALI GND ANA SCAN2 3 Crystal oscillator XTAL in Analog Ground Matrix scan line 16mA internal 33k pull down SCAN2 2 Matrix scan line 16mA internal 33k pull down SCAN2 1 Matrix scan line 16mA internal 33k pull down PW SWITCH Power switch control Active low GND 8 PIN ASSIGNMENT Ground VSS pad Table 3 1 continued Pin Descriptions Ping Pin Name 1 0 Description RESET Reset Active low Schmitt trigger input VDD 5v power VDD pad GND Ground VSS pad SCAN2_4 Matrix scan line 16mA internal 33k pull down SCAN2_5 Matrix scan line 16mA internal 33k pull down SCAN2 6 Matrix scan line 16mA internal 33k pull down SCAN2_7 Matrix scan line 16mA internal 33k pull down SCAN2 8 Matrix scan line 16mA internal 33k pull down 5 2 9 Matrix scan line 16mA internal 33k pull down SCAN2_10 Matrix scan line 16mA internal 33k pull down SCAN2_11 Matrix scan line 16mA internal 33k pull down USB2_DM USB D for downstream port 2 Add 15KQ pull down to ground USB2_DP USB D for downstream port 2 Add 15KQ pull down to ground NUM_LOCK Keyboard NUM_LOCK LED Active low 8 mA CAP_LOCK Keyboard CAP LOC
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