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MN102H55D/55G/F55G LSI User`s Manual

1. Table 2 1 5 Address Data Separate Mode 16 bit Bus Data Access Chapter 2 Bus Interface os rN om e N N N N lt lt lt lt Lae A eek gt ss 5 J J JJ eb eee LE 2 5220 By o 2 o 2 o nn 35 co a o n 9 5 Pse eee ss amp l 4 t 4 t A H d A 1 aa 7 Eaa Asas ww ele a 5 lt lt lt lt 52 o0 b 1 1 1 23 Liu ME FS ah ab hoes Tapuy aa ua a tip ep apna los ak a usus hrs ob o dE NEN agen a ER emis cc lcs S Ex CM NVR Dak ERI amp L E asya a ir AY E ep e 5 pe fe tear
2. 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 PBS PBS PBS PBS PBS PBS PBS PBS PBS PBS PBS PBS PBS PBS PBS PBS W15 W14 W13 W12 W11 W10 W9 W8 W7 W6 W5 W4 W3 W2 wo R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PBS PBS PBS PBS PBS PBS PBS PBS W23 W22 W21 W20 W19 W18 W17 W16 R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 XOOFFBE xOO0FFBC 23 16 15 8 7 0 Write 7 16 Read 484 MN102H55D 55G F55G PBSW x OOFFBC Pointer Byte Swap Register 16 24 bit access register PBSW writes 24 bit pointer data During read operations the up per 8 bit data and the lower 8 bit data are inverted The middle 8 bit remains Chapter 11 Appendix 15 14 13 12 10 9 8 7 6 5 4 3 2 1 fo LBSWL LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS OOFFCC WLIS WLI4 WLI3 WLI2 WLII W
3. 13 Data bus X 8 8 8 FE10 Timer 0 base register TMOBR Load x Reload 8 00 Timer 0 binary counter L Timer 0 underflow interrupt TMOBC Underflow 16 bittimer count L M Y BOSC 2 0 gt 1 2 TMOIO pin P82 Reset Timer output 1 d underflow 2 BOSC 2 generator circuit output by PBLMD TMOIO pin P82 Multiplex Figure 4 1 5 Timer 0 Block Diagram 1 Data bus _ 2 8 8 11 Timer 1 base register TM1BR Load gt Reload 01 dig Timer 1 binary counter m TM1BC Timer 1 underflow interrupt Underflow SerialO 1 4 es EM BOSC 2 Timer 0 underflow Timer 0 cascade gt 2 Timer 4 underflow 0 1 3 Multiplex 112 MN102H55D 55G F55G Figure 4 1 6 Timer 1 Block Diagram Chapter 4 Timers Data bus ZS 8 8 8 FE12 Timer 2 base register TM2BR Load gt Reload FE02 N32IN L Timer 2 binary counter TM2BC Underflow BOSC 2 Timer 0 underflow Timer 1 cascade Timer 4 underflow gt Multiplex Figure 4 1 7 Timer 2 Block Diagram Timer 2 underflow interrupt Serial 0 1 Data bus Timer 3 base r
4. Timer 0 underflow 4 5 a Timer 4 underflow 5 CLK CLR ASEL TM8IOB pin TM8BC BOSC 2 8 UD R TMBIC pin 1 gt Control 4 TMBIOA pin UD LOAD Set by TM8MD2 Set by P9LMD TM8MD2 Match Capture TM8CA R ar 8 e zr 5 8 capture 8 esl TMBIOB pin pin gt TM8CBX u 4 Set by PILMD TM8MD2 MD LD meg J gt TM8MD lt Figure 4 3 12 Timer 8 Block Diagram TM9IC pin Timer 0 underflow gt BC Timer 4 underflow CLK CLA ASEL TMS9IOB 8 gt TM9BC lt ECLA Q BOSC 2 gt 3 UD R Control LOAD 4 pin UD UE us Ja pin y TM9CAX 2H Set by TM9MD2 S iic 5 Capture a D pin pin gt TM9CBX R MD LD ma E TM9MD Figure 4 3 13 Timer 9 Block Diagram MN102H55D 55G F55G Chapter 4 Timers 101 pin Timer 0 underflow lt 5 Timer 4 underflow 5 c CLR T ASEL TM10IOB pin EN gt TM10BC a 5
5. 7 0 C A28 8 X 7 0 23 8 C 47 0 LJ C A238 238 A238 XAT 0X 070 X 270 X 238 X A288 7 0 D7 0 X ATO Hold the last output address Internal peripheral register access a i next don t care A23 8 posture A7 0 Table 2 1 4 Address Data Multiplex Mode 8 bit Bus Data Access No Wait 7 0 23 8 7 0 Hi Z D7 0X Hold the last output address Y 238 XA7 0X PEN C A23 X 238 X A23 8 YA7 0XD7 0X A23 8 A7 0 A7 0 A23 8 A7 0 A23 8 A7 0 X AD7 ADO lt ALE AD7 ADO ALE RE lt a AD7 ADO ALE RE ruf dus lt x Z Z m BOSC BIBT2 BIBT1 A23 A8 E E A23 A8 WEH N A N A A23 A8 WEH WEL WAIT A23 A8 WEH can be set as the general purpose port in 8 bit bus width mode No external access Internal ROM RAM access Base Clock 8 bit Data Read 8 bit Data Write No Access External Wait Bus Request 8 bit H side Data Write 8 bit L side Data Write 69 MN102HF55G H55G H55D The length of wait cycle can be set 0 5 cycle units
6. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EW33EW32EWS31 EW30EW 3EW 22IEW 21EW20 EW13EW12EW11EW10EWO3EWO2EWO EWOO Reset 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 EW 03 00 Set the number of wait for external memory space 0 EW 13 10 Set the number of wait for external memory space 1 EW 23 20 Set the number of wait for external memory space 2 EW 33 30 Set the number of wait for external memory space 3 Please refer to Figure 2 1 1 Address Space on page 52 for Wait Cycle address allocation of the exter 0000 0 0 10 nal memory spaces 0001 0 5 1 5 0010 1 0 2 0 0011 1 5 25 0100 2 0 3 0 0101 2 5 3 5 0110 3 0 4 0 0 5 wait cycle corresponds to 35 45 BOSC 1 cycle 1 wait 1000 40 50 sponds to 1 cycle of instruction With a 34 MHz external oscillator 1001 4 5 5 5 0 5 wait 29 4 ns 1010 5 0 6 0 1 0 wait 58 8 ns 1011 5 5 6 5 1100 6 0 7 0 1101 6 5 7 5 1110 7 0 8 0 1111 perform handshake mode by WAIT pin MN102HF55G H55G H55D 53 Chapter 2 Bus Interface register sets the wait cycles for internal peripherals the bus widths and ROM burst modes for the external memory spaces 0 to 3 MEMMD 1 x 00FF82 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EB21 EB20 EB11 EB10 EBO1 EBOO BRS1 BRSO BRC3 BRC2BRC1 BRCO IOW1 IOWO Reset 0
7. T 6 5 4 3 2 1 0 P4 P4 P4 P4 P4 P4 P4 IN7 ING INS INA IN3 IN2 INI INO R R R R R R R R Port Port Port Port Port Port Port Port 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port 4 Input 0 Input low 1 Input high 7 6 5 4 3 2 1 0 5 5 5 5 5 5 5 5 IN7 ING INS INA IN2 INI INO R R R R R R R R Port Port Port Port Port Port Port Port 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port 5 Input 0 Input low 1 Input high 7 6 5 4 3 2 1 0 P6 P6 P6 P6 IN3 IN2 INI INO R R R R R R R R 0 0 0 0 Port Port Port Port 0 0 0 0 0 1 0 1 0 1 0 1 3 0 Port6 Input 0 Input low 1 Input high 7 6 5 4 3 2 1 0 7 P7 P7 P7 P7 P7 P7 IN6 INS INA IN3 IN2 INI INO R R R R R R R R 0 Port Port Port Port Port Port Port 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6 0 Port 7 Input 0 Input low 1 Input high Chapter 11 Appendix PAIN x OOFFD4 Port 4 Input Register 8 bit access register P4IN reads the port 4 data x OOFFDS5 Port 5 Input Register 8 bit access register reads the port 5 data P6IN x OOFFD6 Port 6 Input Register 8 bit access register P6IN reads the port 6 data P7IN x OOFFD7 Port 7 Input Register 8 bit access register P7IN reads the port 7 data Reading P76 pin identifys the status input
8. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDSTISDSTIADSTI3DSTI2DSTI I DSTIO 0579 DST8 DST7 DST6 0575 DST4 DST3 DST2 DSTI DSTO R W R W R W R W R W R W R W R W R W R W R W undefined undefined undefined Jundefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATO ATO ATO ATO ATO ATO ATO ATO IDST23DST22DST21DDST20DSTI9DSTISDDSTI7 DSTI6 R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 400 MN102H55D 55G F55G ATODST 007008 0 Destination Address Pointer 16 24 bit access register ATODST sets the transfer desti nation address When the desti nation pointer increment bit is set to be fixed the transfer source address do not change When the source pointer incre ment bit is set to increment in crement by 1 in the byte transfer and by 2 in the word trans
9. Bus Master External Memory n External Device A23 A0 015 00 RE CS 015 00 WE Y DMAREQn A23 A0 015 00 RE CS DMAACKn MN102H55D 55G F55G Bus Master External Memory External Device A23 A0 015 00 WE CS 015 00 RE Y DMAREQn A23 A0 015 00 WE CS DMAACKn MN102H55D 55G F55G MN102H55D 55G F55G ETC stops executing the CPU s program transfers the data automatically between the external memory and the external device when low level is input to DMAREQn pin from bus master DMAACKn becomes RE or WE signal for the external device After the transfer ends ETC restarts executing the program External memory is a device such as SRAM that has address input pins data input output pins the RE control pin and the WE control pin The external memory is connected to the chip in processor mode or address expansion mode with either ad dress data separate mode or address data shared mode The external memory has a register to set the number of waits External device is a device such as ASIC that has data input output pins the RE control pin and the WE control pin without using address input pins The external device needs to output the data when a signal is input to RE and read the data when a signal is input to WE When waits are required for accesses the number of waits is set using the regis
10. Se Dp ic o ehh eae ee ee oS A ee a ain eee ee eee eee ic ctl an eee ee Sms 2 ote Sele eh m rt at aat I ai de ei RR See gt F S 3 8 8 g 8 g 8 O 8 3 2 E E 8 72 E LLI W W d d o 3 2 1 4 o 1 d Q gt T o o S 8 o 6 6 8 steele ste teehee ee EE er L pa ac ru Suku gt g a er aem s gad dass hc cte im aeta JI IHE dee ers DH ped Jum
11. 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 AT3 AT3 AT3 AT3 AT3 AT3 AT3 AT3 AT3 AT3 AT3 AT3 EN BW DB8 DI SB8 SI 103 102 101 100 R W R W R W R W R W R W R W R W R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 15 Transfer Busy Start Flag 0 Disable 14 13 Transfer Mode 12 Transfer Units 11 Destination Bus Width 10 Destination Pointer Increment 9 Source Bus Width 8 Source Pointer Increment 3 0 ATC Activation Factor Setup 1 Transfer start transfer in progress 00 One byte word transfer 01 Burst transfer 10 Two bytes transfer 11 Reserved 0 Word 1 Byte 0 16 bit 1 8 bit 0 Fixed 1 Increment 0 16 bit 1 8 bit 0 Fixed 1 Increment 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Software Initialization DMAREQ1 pin input External interrupt 2 External interrupt 3 Timer 2 underflow interrupt Timer 6 underflow interrupt Timer 8 capture B interrupt Timer 10 underflow interrupt Timer 11 capture A interrupt Timer 12 capture B interrupt Serial 2 transmission end interrupt Serial 2 reception end interrupt Serial 3 transmission end interrupt Serial 3 reception end interrupt A D conversion end interrupt Key interrupt MN102H55D 55G F
12. ie A p a n 0 4 7 Figure 4 1 3 8 bit Event Counter Input Timing TMnBC Value Load Value Interrupts TMnlO Output n 0 4 7 Figure 4 1 4 8 bit Timer Output and Interval Timer Timing Chapter 4 Timers Cascading 8 bit counters forms a 16 bit timer 24 bit timer 32 bit timer 40 bit timer 48 bit timer 56 bit timer or 64 bit timer MN102H55D 55G F55G 109 Chapter 4 Timers 4 1 2 8 bit Timer Control Registers The timer binary counters TMnBC the timer base registers TMnBR and the timer mode registers TMnMD control timer counter func tions n 0 to 7 TMn TMn TMn TMn TMn TMn TMn BC7 BCS BC4 BC3 BC2 BCI BCO TMnBC Reset 0 0 0 0 0 0 0 0 TMn TMn TMn TMn TMn TMn TMn TMn TMnBR R W BR7 BR6 BR5 BR4 BR3 BR2 BRO Reset 0 0 0 0 0 0 0 0 TMn TMn TMn TMn TMnMD R W Reset 0 0 0 0 TMnS 1 0 Clock Source Selection 00 BOSC divided by 2 XI divided by 4 1 01 Timer 0 underflow XI divided by 4 1 1 Since the settings may differ 10 Cascading BOSC 1 depending on timers check 11 Pin input Timer 4 underflow BOSC 1 each register explanation in Ap pendix Section Read TMnBR value to TMnBC 0 No operation Read TM
13. Pn Pn Pn Pn MD7 MD6 MDS MD4 MD2 MD1 MDO PnMD PnMMD PnHMD Reset 7 6 5 4 3 2 1 0 Pn Pn Pn Pn Pn Pn Pn Pn PnDIR 0 Input DIR7 DIR6 DIR4 DIR3 DIR2 DIR1 DIRO n 1 Output Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Pn Pn Pn Pn Pn Pn Pn Pn PnPLU 0 Pull up off PLUT PLU6 PLUS PLUA PLU3 PLU2 PLUI PLUO 1 Pull up on Reset 0 0 0 0 0 0 0 0 MN102H55D 55G F55G 261 Chapter 8 Ports Table 8 1 1 List of Port Control Registers Register Address R W Function POPLU R W Port 0 Pull up Control Register POOUT x 00FFCO R W Port 0 Output Register POIN x 00FFDO R W Port 0 Input Register PODIR x 00FFEO R W Port 0 Input Output Control Register POMD x OOFFFO R W Port 0 Mode Register PIPLU 1 R W Port 1 Pull up Control Register x 00FFCI Port 1 Output Register x 00FFDI R W Port 1 Input Register PIDIR x O0FFEI R W Port 1 Input Output Control Register PILMD 2 R W Port 1 Mode Register R W Port 1 Mode Register P2PLU 2 R W Port 2 Pull up Control Register P20UT x 00FFC2 R W Port 2 Output Register P2IN x 00FFD2 R W Port 2 Input Register P2DIR x 00FFE2 R W Port 2 Input Output Control Register P2MD x O0FFFI R W Port 2 Mode Register P3PLU x 00FFB3
14. Data 16 bit External Memory External Device ANEA Address ICS DMAACKO RE x 100000 dataA x 100002 dataB MN102H55D 55G F55G 7 Bus Master DMAREQO Each 16 bits of the data is transferred The 16 bit bus width mode is selected to connect external memory and the CPU from external device to external memory In addition 16 bit bus width is selected to connect the external memory and external device Figure 7 4 5 ETC External Device External Memory Burst Transfer Connection MN102H55D 55G F55G 251 Chapter 7 ATC ETC 252 MN102H55D 55G F55G B ETC Setup 1 Set the destination address x 100000 of the external memory to the ETCO destina tion address pointer ETOSRC ETODST x 00FD48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETO ETO ETO DST15 DST14 DST13 DST12 DST11 DST10 0519 0578 DST7 DST6 DSTS DST4 DST3 DST2 DSTI DSTO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDST23 DST22 DST21 DST20 DST19 DST18 DST17 DST16 0 0 0 1 0 0 0 0 2 Set the words to be transferred automatically
15. gt WEL P62 PO CORE D A Converter P6 WEH P63 1 Interrupt A D Converter P7 7 0 8 bit Timers Serial I F P8 A8 E bit Ti I P92 A15 A8 P3 16 bit Timers ATC Jr P9 DMAACKO P93 A23 A16 P4 8 bit PWM ETC PA 50 P50 P5 Pulse Width Counter ROM PB Figure 7 4 7 ETC External Device External Memory One Byte Transfer Block Diagram External Memory External Device ata 16 bit External Memory External Device a Address WE cs DMAACKO RE x 100000 dataA MN102H55D 55G F55G A Bus Master DMAREQO Each 16 bits of the data is transferred The 16 bit bus width mode is selected to connect external memory and the CPU from external device to external memory In addition 16 bit bus width is selected to connect the external memory and external device Figure 7 4 8 ETC External Device External Memory One Byte Transfer Connection MN102H55D 55G F55G 255 Chapter 7 ATC ETC 256 MN102H55D 55G F55G B ETC Setup 1 Set the destination address x 100000 of the external memory to the ETCO destina tion address pointer ETOSRC ETODST x 00FD48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETO ETO
16. 13 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 8 TMS 8 8 8 8 TM8 TM8 The timer 8 binary counter EN NLD UDI UDO TGE ONE MDI MDO ECLR LP ASEL 52 51 SO TM8BC is stopped 0 0 0 0 0 0 0 1 0 1 0 0 1 1 register RS F F initialized cleared to 0 2 Set the timer 8 divisor Since the divisor is BOSC 2 divided by 5 set the timer 8 compare capture register A TM8CA to 4 The valid range is 1 to TM8CA x 00FE84 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 8 8 8 TM8 8 8 8 TM8 TM8 8 8 8 8 TM8 CA14 CA13 CA12 1 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO 0 0 0 0 0 0 0 0 O 0 1 0 0 3 Set the phase difference for timer 8 Since the phase difference is 2 5 cycles of BOSC 2 set the timer 8 compare capture register B TM8CB to 1 The valid range is 0 lt TM8CB lt TM8CA TM8CB x 00FE88 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 8 TM8 TM8 TM8 TM8 TM8 8 8 8 TM8 8 TM8 TM8 8 TM8 CBI5 CB14 CB13 CB12 CB11 CB8 CB6 CBS CB2 CBO 0 0
17. Figure 4 4 26 External Reset Conirol Block Diagram 16 bit Timer 170 MN102H55D 55G F55G Timer 8 Setting 1 Set the operating mode in the timer 8 mode register TM8MD Set counting stop Select up counting Select BOSC 2 as the clock source Set the TM8BC clear condition to clear when 8 pin is high Set the TM8BC count range to 0 to TM8CA TM8MD x 00FE80 0 0 0 0 0 0 0 0 1 1 100 0 1 1 2 Set the timer 8 looping value to the TM8CA register the valid range 1 to X FFFE The TM8BC register counts from 0 to 1 when writing 1 to the TM8CA register TM8CA x 00FE84 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 8 8 8 8 8 8 8 TM8 TM8 TM8 8 8 8 8 TM8 CA14 CA13 CA12 CA10 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 3 Set TM8NLD and TM8EN of the TM8MD register to 1 and 0 respectively This enables TM8BC and RS F F 4 Set TM8NLD and TM8EN of the TM8MD register to 1 This starts the timer Counting starts at the beginning of the next cycle Chapter 4 Timers 1 Use the MOV instruction to set the data and only use 16 bit write operations The timer 8 binary counter TM8BC is
18. 7 6 5 4 3 2 1 0 SC2T ScoT IR ID R R R W R R 0 0 0 0 0 0 0 0 0 on o 0 0 4 Serial 2 Transmission End 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 0 Serial 2 Transmission End 0 Interrupt undetected Interrupt Detect Flag 1 Interrupt detected 7 6 5 4 3 2 1 0 sc2r sc2r sc2T SC2T LV2 LVO IE R R W R W R W R R W 0 0 0 0 0 0 0 0 o 0 6 4 Serial 2 Transmission End Set the level from 0 to 6 Interrupt Level Setup 0 Serial 2 Transmission End 0 Disable Interrupt Enable Flag 1 Enable Chapter 11 Appendix SC2TICL 00 98 Serial 2 Transmission End Interrupt Control Register 8 bit access register SC2TICL requests and verifies a serial 2 transmission end inter rupt This register allows only byte accesses Use the MOVB in struction to set the data SC2TICH 99 Serial 2 Transmission End Interrupt Control Register 8 bit access register SC2TICH sets a seial 2 trans mission end interrupt level and enables an interrupt This register allows only byte accesses Use the MOVB in struction to set the data MN102H55D 55G F55G 379 Chapter 11 Appendix 7 6 5 4 3 2 0 SCR SC2R IR ID R R R R W R R R 0 0 0 0 0 0 0 on o 0 1 4 Serial 2 Reception
19. 3 Set the timer 8 interrupt value to the TM8CB register the valid range 0 to TMSCA In this example write x 1000 Whenever the up or down counter reaches this value a capture B interrupt occurs at the beginning of the next cycle TM8CB x 00FE88 CBI5 CB14 CB13 CB12 10 CB8 CB6 CBS CB2 CBO 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 4 Set TM8NLD TM8EN of the TM8MD register to 1 and 0 respectively This enables TM8BC and RS F F 5 Set TM8NLD and TM8EN of TM8MD register to 1 This starts the timer Counting begins at the start of the next cycle Interrupt Enable Setting 6 Enable interrupts after clearing all prior interrupt requests To do this set IQOLV 2 0 of the external interrupt 0 control register IQOICH to the interrupt level 0 to 6 TM8BIR of the timer 8 capture B interrupt control register TM8BICL to 0 and TM8BIE of the timer 8 capture B interrupt control register TM8BICH to 1 Thereafter a timer 8 capture B interrupt occurs when the TMSBC counter matches the TM8CB register Interrupt Processing 7 First determine the interrupt group and factor and clear TM8BIR flag during the interrupt service routine 8 Execute the interrupt service routine TMBIOA pin can control the timer 8 count direction The count direction is contro
20. ETO ETO MD0 BW 8 DI 88 SI i DIR EN 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 1 Chapter 7 ATC ETC Interrupt Setup 4 Enable an ETCO transfer end interrupt ETOICL x 00FDAS The interrupt level is set in SC4TLV 2 0 of the SCATICH ETO register Under this state ETCO starts transferring when DMAREQO becomes low by bus mas ter After the ETCO transfer ends an ETCO transfer end interrupt occurs Each ETCO register value is set as follows ETOCNT x OFFF This value is always set regardless the bytes to be transferred ETOSRC x 100002 The result incremented by 1 is set after the last transfer is completed MN102H55D 55G F55G 249 Si E 5 03 kuy gt 2 S Y zc Eo 3 S eo u y a eade gc beret aea eet 8 8 S vet 4 n 8 __ ML SENT Bn 58 Qa sesana 4 2 e 8 lle pasa 1 1 t N es ex MI 1 4 5 28183551 793 p E 5 n Eo 289 vo Hof crc ze 28 y 5 2s coh 6 9
21. 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01100 01 00 01 n f 00 02 00 02 01 00 02 01 00 02 Figure 4 2 5 Clock Output Timing 8 6 Timer MN102H55D 55G F55G 121 Chapter 4 Timers 4 2 3 Interval Timer Using 8 bit Timer Timer 0 timer 4 and timer 5 divide BOSC 2 by 120 000 and generate an interrupt 8 bit Timer 16 bit Timer BOSC 1 2 gt 0 Divided by 2 Divided by 2 This verification is unnecessary after a reset 122 MN102H55D 55G F55G Timer 4 Timer 5 Divided by 60000 x EA60 Timer 5 underflow interrupt F Figure 4 2 6 Interval Timer Configuration Example 8 bit Timer m D A Converter P6 P1 Interrupt A D Converter P7 P2 L 8 bit Timer Serial P8 P3 16 bit Timer P9 P4 8 bit PWM ETC P5 Pulse Width Counter Figure 4 2 7 Interval Timer Block Diagram 8 68 Timer Timer 0 Setting 1 Verify that timer 0 counting is stopped with the timer 0 mode register TMOMD TMOMD x 00FE20 7 6 3 4 3 2 1 0 TMO TMO TMO TMO EN LD 51 50 0 2 Set the timer 0 divisor Since timer 0 divides BOSC
22. e s l ean ul i eS Drs e e t lt m mo ge lu 2 TM13BR TM13CB underflow Timer 0 MN102H55D 55G F55G 180 Chapter 4 Timers 4 7 16 bit Pulse Width Measure Functions 4 7 1 Overview The MN102H55D 55G F55G has one 16 bit pulse width measure counter The 16 bit binary counter value is read into the 16 bit capture register on the rising edge of the pulse waveform which inputs to TMISIA pin Timer 0 underflow BOSC 2 BOSC is selected as the clock source Timer 0 underflow 5 pin 9 16 bit Binary Counter DIEE BOSC 2 CLK Clear BOSC 9 Delay of BOSC 1 clock pin ae Capture at 7 16 bit Capture Register Capture Figure 4 7 1 16 bit Pulse Width Measure Counter MN102H55D 55G F55G 181 Chapter 4 Timers 15 Capture Register Time Y 417 Example 418 Example Figure 4 7 2 16 bit Pulse Width Measure Counter Operation Example The binary counter is up counting The contents of the binary counter are loaded into the capture register on the rising edge of pin The binary cou
23. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Interrupt Setup 4 Enable an ETCO transfer end interrupt ETOICL x 00FDAS ETO Under this state ETCO starts transferring when DMAREQO becomes low by bus mas ter After the ETCO transfer ends an ETCO transfer end interrupt occurs Each ETCO register value is set as follows ETOCNT x OFFF This value is always set regardless of the bytes to be transferred ETODST 100000 The result incremented by 1 is set after the last transfer is completed Chapter 7 ATC ETC The interrupt level is set in SCATLV 2 0 of the SC4TICH register MN102H55D 55G F55G 257 Chapter 7 ATC ETC Transfer ETC Internal Chip Operation Process ETC Internal Process Chip Operation BOSC BIBT2 DMAREQn input ETC bus acquisition interval Address output External device data output output External device RE 0 1 Note the number external memory waits the number of data transfer bytes Figure 7 4 9 ETC External Device External Memory One Byte Transfer Timing MN102H55D 55G F55G 258 Chapter 8 Ports 8 Chapter 8 Ports 8 1 Summary of Ports 8 1 1 Overview The MN102H55D 55G F55G contains twelve I O ports Functions can be switched depending
24. TMO TMO TMO EN LD 51 50 0 3 Set the timer 0 divisor Since timer 0 divides BOSC 2 by 2 set the timer 0 base register TMOBR to 1 The valid range for TMOBR is 0 to 255 TMOBR 00 10 TMO TMO TMO TMO TMO TMO TMO BR7 BRO BRS BR3 BR2 BRI BRO 0 0 0 O 1 4 Load TM0BR value to the timer 0 binary counter At the same time select BOSC 2 as the clock source TM0MD x 00FE20 7 6 5 4 3 2 1 0 TM0 TMO TM0 TMO EN LD 51 50 0 1 0 0 5 Set TMOLD and TMOEN of the TMOMD register to 0 and 1 respectively This starts the timer Counting begins at the start of the next cycle When the binary counter reaches 0 and loads the value from the base register at the next count a timer 0 underflow interrupt request will be sent to the CPU Timer 7 Setting 6 Verify that timer 7 counting is stopped with the timer 7 mode register TM7MD TM7MD x 00FE27 7 6 5 4 3 2 1 0 TM7 TM7 7 TM7 EN LD 51 50 0 7 Set the timer 7 divisor Since timer 7 divides timer 0 output by 3 set the timer 7 base register TM7BR to 2 The valid range for TM7BR is 0 to 255 TM7BR x 00FE17 7 6 5 TM7 TM7 BR7 BR6 TM7 BR5 TM7 TM7 TM7 TM7 BR4 BR3 BR2 BR1 TM7 BRO
25. W IN N CO IN G N O GO N IN IOO IN OO N IN IN IGO INI IN N IN F0 C0 Di lt lt 4 An lt lt 2 Dm Quick decoder ON This setting cannot be made in this series 2 This instruction is supported by the assembler For MOV d8 An Am the assembler will generate a bit pattern for d8 0 3 This instruction is supported by the assembler For MOV Am d8 An the assembler will generate a bit pattern for d8 0 4 This instruction is supported by the assembler The assembler generates bit patterns for the two instructions MOVBU An Dm and EXTXB Dm 5 This instruction is supported by the assembler The assembler generates bit patterns for the two instructions MOVBU abs16 Dn and EXTXB Dn MN102H55D 55G F55G Instruction Mnemonic MOVB Dn abs16 Operation Dn mem8 abs16 wo Cycle Chapter 11 Appendix Machine Code C4 Dn abs16 l abs16 h MOVB Dn abs24 Dn meme8 abs24 F4 44 Dn abs24 l abs24 m abs24 h MOVBU An Dm mem8 An Dm 30 An lt lt 2 Dm MOVBU d8 An Dm mem8 An d8 Dm F5 30 An lt lt 2 Dm d8 MOVBU d16 An Dm 8 16 gt F7 50 An lt lt 2 Dm d16 l d16 h MOVBU 424 0 F4 90 An lt lt 2 Dm d24 d24 m d24 h MOVBU Di An Dm mem8 An Di Dm F0 80 Di lt lt 4 An lt lt 2 Dm MOVBU abs16 Dn mem8 An
26. 550 MN102H55D 55G F55G Chapter 11 Appendix Extended Code L Third byte Byte 1 F5 Byte 2 Fn Upper Lower 0 1 2 3 4 5 6 7 8 9 A B MULQL MULQH imm8 Dn imm8 Dn Ver 1 01 2000 5 16 MN102H55D 55G F55G 551 Chapter 11 Appendix 552 MN102H55D 55G F55G MN102H55D 55G F55G User s Manual Record of Changes Ver 1 1 to Ver 2 0 Former Version New Version 10n Unused pins require handling in the circuit input 1 pins are connected to VDD Vss output pins leave Open input output pins are connected to VDD Vss or leave open depending on pin direction setting The unused pins require handling on the board The input pins are connected to VDD or VSS The output pins leave open The lack of this handling causes the increase of current and unstable operation Pulling the pin low sets 8 bit bus width while pulling the pin high sets 16 bit bus width Pulling the pin high sets 8 bit bus width while pulling the pin low sets 16 bit bus width In addition this pin can reads the pin state as the general purpose input port PAG In addition this pin can reads the pin state as the general purpose input port P76 The 2 1 3 Memory Connection Examples is added W Example of DRAM 2CAS Method Connection 16 bit Bus Width 2 Wait Example of Burst ROM Connection 8 bit Bus Width 4 3 3 3 Waits Lower
27. 16 Pin Configuration in Memory Expansion Mode with 16 bit Bus Address Data Shared Mode 17 Pin Configuration in Processor Mode with 8 bit Bus Address Data Separate Mode 18 Pin Configuration in Processor Mode with 16 bit Bus Address Data Separate Mode 19 Pin Configuration in Processor Mode with 8 bit Bus Address Data Shared Mode 20 Pin Configuration in Processor Mode with 16 bit Bus Address Data Shared Mode 21 OSCI OSCO Connection Example 48 XI XO Connection Example 48 Reset Pin Connection Example 48 WAIT Signal Control Circuit Connection Example 48 External Dimensions 49 Address Space sd e oed bcd a 52 SRAM Mask ROM Connection Example 16 bit Bus Width 62 SRAM Mask ROM Connection Example 8 bit Bus Width 63 DRAM 2WE Method Connection Example 16 biti Busi Width itt bt 64 Burst ROM Connection Example 8 bit Bus Width 65 Figure 2 1 6 Figure 2 1 7 Figure 2 1 8 Figure 2 3 1 Figure 2 3 2 Figure 2 4 1 Figure 3 1 1 Figure 3 1 2 Figure 3 1 3 Figure 3 2 1 Figure 3 2 2 Figure 3 2 3 Figure 3 2 4 Figure 3 2 5 Figure 3 2 6 Figure 3 2 7 Figure 3 2 8 Figure 4 1 1 Figure 4
28. 16 bit access register This register is valid only when the associated compare register is set to the double buffer mode TM12CBX cannot read or write The contents of TM12CB are loaded to TM12CBX by write signal TM12CBX sets the PWM cycle When TM12BC TM12CBX timer 12 capture B interrupt oc curs The contents of TM12CB are loaded to TM12CBX by a timer 12 capture B interrupt and TM12CBX prevents the PWM loss This register writes only 16 bit data Use the MOV instruction to set the data MN102H55D 55G F55G 465 Chapter 11 Appendix 7 6 5 4 3 2 1 0 13 13 13 13 13 13 TMI3 TMI3 CAT CA6 CAS 4 CA2 CAI CAO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 13 13 13 13 13 13 TMI3 TMI3 CB7 CB6 CB5 CB4 CB3 CB2 CBI CBO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 466 MN102H55D 55G F55G TM13CA x OOFEOA Timer 13 Capture A Register 8 bit access register TM13CA sets the timing of changing the PWM waveform output from pin from low level to high level The valid range for TM13CA is 1 to TM13BR TM13CB x OOFE1A Timer 13 Capture B Register 8 bit access register TM13CB se
29. 280 Program Flow of Address Break Setup 282 Stack State after NMI Interrupt 283 CPU Operating Mode Changes 2 286 Operating Mode Control and Clock Oscillation On Off 288 Sequence of Switching to from Standby Mode 291 System Clock 327 Reset TIMING 327 Voltage Rise Timing 2 327 Data Transfer Signal Timing Address Data Separate without Wait Read Write 328 Data Transfer Signal Timing Address Data Separate with Wait 1 5 or More Read Write 329 Data Transfer Signal Timing Address Data Separate with Wait 1 5 or More RE Late Short Mode 330 Data Transfer Signal Timing Address Data Separate with Wait 1 5 or More WE Late Short Mode 331 Figure 11 1 8 Figure 11 1 9 Figure 11 1 10 Figure 11 1 11 Figure 11 1 12 Figure 11 1 13 Figure 11 1 14 Figure 11 1 15 Figure 11 1 16 Figure 11 1 17 Figure 11 1 18 Figure 11 4 1 Figure 11 4 2 Figure 11 4 3 Figure 11 4 4 Figure 11 4 5 Figure 11 4 6 Figure 11 4 7 Figure 11 4 8 Figure 11 4 9 Figure 11 4 10 Figure 11 4 11 Figure 11 4 12 Figure 11 4 13 Data Transfer Signal Timing Address Data Sh
30. R Y x TMBIOB pin gt TM8CB Q Capture interrupt Figure 4 4 17 Two phase Encoder Input 1x Block Diagram 16 bit Timer TM8BC Value 0 1000 Xx1FFF Capture B interrupt Figure 4 4 18 Two phase Encoder Input 1x Configuration Example 1 0 1000 x FFOO Capture interrupt Capture B interrupt Figure 4 4 19 Two phase Encoder Input 1x Configuration Example 2 Chapter 4 Timers As Figure 4 4 19 shown it is possible to set capture A inter rupt and capture B interrput in different places separately Setting TM8LP of the 8 register to 0 is required MN102H55D 55G F55G 161 Chapter 4 Timers 1 Use the MOV instruction to set the data and only use 16 bit write operations The timer 8 binary counter TM8BC is stopped and TM8BC register and RS F F are initialized cleared to 0 1 If this setting is omitted the bi nary counter may not count the first cycle Do not change to any other operating modes 162 MN102H55D 55G F55G Timer 8 Setting 1 Set the operating mode in the timer 8 mode register TM8MD Set counting stop Count setting is ignored Since counting is performed by looping on the TM8CA value set TM8LP of the TM8MD register to 1 Select the two phase encoder 1x as the clock source TM8MD x 00FE80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31. R W R W R W R W R W 0 0 0 0 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRCISISRCIASRCI3SRCI2SRCIISRCIO SRCO SRC8 SRC7 SRC6 5 5 SRC4 SRC3 SRC2 SRC1 SRCO R W R W R W R W R W R W R W R W R W R W undefined undefined undefined Jundefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISRC23SRC22SRC2ISRC2OSRCIO9SRCISSRCIT7SRCI R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 414 MN102H55D 55G F55G ETICNT x 00FD52 ETC 1 Transfer Word Count Register 16 bit access register ET1CNT sets the bytes to be transferred subtracted by 1 Decrement by 1 every time
32. Interrupts x x x x A Figure 4 4 2 Event Counter Timing 16 bit Timer 7 MN102H55D 55G F55G 139 Chapter 4 Timers 4 4 2 One phase PWM Output Using 16 bit Timer Timer 8 is used to divide BOSC 2 by 5 and outputs a one phase PWM on the fifth cycle The signal duty is 2 3 To do this set the compare capture register A to the divisor of 5 set value is 4 and the compare capture register B to the cycle of 2 the set value is 1 PO CORE D A Converter P6 TMB8IOA P1 Interrupt A D Converter P7 P2 8 bit Timers Serial I F P8 L 16 bit Timers ATC P9 P4 8 bit PWM ETC PA P5 Pulse Width Counter ROM RAM PB Timer 8 5 2 TM8BC TM8CA TM8CAX Control TM8CB Y ps Q gt 8 pin TM8CBX Figure 4 4 3 One phase PWM Output Block Diagram 16 bit Timer 140 MN102H55D 55G F55G Chapter 4 Timers Timer 8 Setting 1 Set the operating mode in the timer 8 mode register TM8MD Set counting stop 1 and interrupt disable Select up counting Select BOSC 2 as the clock source Use the MOV instruction to set the data and only use 16 bit write operations Select the double buffer operating mode TM8MD x 00FE80
33. D 5A87 Example Figure 4 3 9 Input Capture 2 Timing 130 MN102H55D 55G F55G Chapter 4 Timers BC Value FLF Fifi TMnIB i E Figure 4 3 10 Two phase Encoder 4x Timing BC Value Time TMnIA i io E i TMnIB mE m m Figure 4 3 11 Two phase Encoder 1x Timing MN102H55D 55G F55G 131 Chapter 4 Timers 4 32 16 bit Timer Control Registers The timer binary counter TMnBC the timer compare capture register A TMnCA the timer compare capture register B TMnCB and the timer mode register TMnMD control 16 bit timer counter functions TMn 5 TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn BC14 BC13 BC12 BC11 BC10 BC8 BC7 BC6 5 BC4 BC3 TMn TMn TMn 2 TMnBC R TMn CAIS TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn 14 13 12 11 10 CA9 CA8 CA7 CA6 CAS CA4 TMn TMn TMn 1 TMnCA R W TMn 15 TMn TMn CB14 CB13 TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn 12 11 10 CB9 CB8 CB6 CBS CB4 TMnCB R W CB2 CB1 CBO
34. iet eta t 8 ol lt d Em gt lt 5 255 eeu dud soc NI Lou Lal s sh St th e 2 z E at sa s s 1 cc oo c ed gt lt lt 24 11 1 2g ec 42 ep ep In N N T N lt lt E lt 5 2 Ra E Q mas Sosa St ey ccu orcs N EIA 2 2 gt gt Loll 50 1 2 1 11 gt OR 2S4 8 54 1 gt A N N iN z z cay We Te pue 15005010205 5 5 ss X gt lt S tH t 4 H 41 H 4 g SPA SER N N m N N N o N lt lt 2 le o o M M 9 5 T T T X A 2 a OG o io E r 8 lt 1 9 an lt lt 8 5 5 o A nee u u iu ce nmala alelo lo lt O lt zz 2 E 52 x 9 x 9 a 9 9 O S s 8 oO oO 9 2 8 m z ysanbey sng 73 MN102HF55G H55G H55D CA
35. seem 107 Timer Configuration 109 8 bit Event Counter Input Timing 109 8 bit Timer Output and Interval Timer Timing 109 Timer 0 Block Diagram eee 112 Timer 1 Block Diagram esee 112 Timer 2 Block Diagram esee 113 Timer Block Diagram esee 113 Timer 4 Block Diagram eee 114 Timer 5 Block Diagram ese 114 Timer 6 Block Diagram sese 115 Timer 7 Block Diagram eee 115 Event Counter Block Diagram 116 Event Counter Timing 118 Clock Output Configuration Example 8 bit Timer 119 Figure 4 2 4 Figure 4 2 5 Figure 4 2 6 Figure 4 2 7 Figure 4 2 8 Figure 4 3 1 Figure 4 3 2 Figure 4 3 3 Figure 4 3 4 Figure 4 3 5 Figure 4 3 6 Figure 4 3 7 Figure 4 3 8 Figure 4 3 9 Figure 4 3 10 Figure 4 3 11 Figure 4 3 12 Figure 4 3 13 Figure 4 3 14 Figure 4 3 15 Figure 4 3 16 Figure 4 4 1 Figure 4 4 2 Figure 4 4 3 Figure 4 4 4 Figure 4 4 5 Figure 4 4 6 Figure 4 4 7 Figure 4 4 8 Figure 4 4 9 Figure 4 4 10 Figure 4 4 11 Figure 4 4 12 Clock Output Block Diagram 8 bit Timer 119 Clock Output Timing 8 bit Timer 121 Interv
36. Timer 10 Compare 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Capture Register Set 16 bit access register This register is valid only when the associated compare register is set to the double buffer mode TM10CBX cannot read or write The contents of TM10CB are loaded to TM10CBX by write signal TM10CBX sets the PWM cycle When TM10BC TM10CBX a timer 10 capture B interrupt oc curs The contents of TM10CB are loaded to TM10CBX by a timer 10 capture B interrupt and TM10CBX prevents the PWM loss This register writes only 16 bit data Use the MOV instruction to set the data MN102H55D 55G F55G 461 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 15 14 1 12 11 10 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIIC TIIC TIIC TIIC TLIC T11C TIIC TLIC TIIC TIIC T11C
37. WEL WEH r T H 1 1 ii WAIT 1 1 Fixed Wait f Fixed Wait 1 1 1 i Access Cycle gt Access M 1 lf WAIT pin is low at this timing If WAIT pin is low at this timing If WAIT pin is high before this timing 200655 cycle ends 1 5 BOSC If WAIT pin is high before this timing access cycle ends 1 5 BOSC wait cycle continues later wait cycle continues cycle later Figure 2 3 2 Fixed Wait and Handshake Wait Control Timing 1 Wait Cycle as Fixed Wait 2 Wait Cycles as Whole Wait Data Write Set 1111 to bits for the number of wait cycles of the EXWMD register to control handshake wait cycles When the fixed wait cycle is required set the necessary num ber of wait cycles to bits for number of fixed wait cycles of MEMMD 2 register at the same time The wait cycle range from 0 to 3 5 cycles is set in 0 5 wait cycle MN102HF55G H55G H55D 81 Chapter 2 Bus Interface 2 4 Activation Sequence 2 4 1 Activation Sequence of Each Mode This section describes the activation sequence and the pin state after power turns on in single chip mode memory expansion mode and pro cessor mode The activation sequences and pin states in mask ROM version MN102H55G and those in flash version MN102HF55G are same Single chip Mode
38. 111 16 bit Timer Functions 127 List of 16 bit Timer Control Registers 134 8 bit PWM Functions 174 List of 8 bit PWM Registers u 176 List of 16 bit Pulse Width Measure Registers 183 Serial Interface Functions 189 List of Serial Interface Control Registers 193 Baud Rate Setting Example in Asynchronous Mode 195 Transfer Clock Setup Example 203 A D Converter Functions 213 List of A D Converter Control Registers 221 D A Converter Functions sss 227 List of D A Converter Control Registers 228 ATG a 233 List of ATC Control Registers 236 ETC Connection Examples 242 List of ETC Control Registers 246 List of Port Control Registers 262 Port Block Diagrams see 264 Watchdog Interrupt Interval 288 Clock Frequency 531 Chapter 1 General Description Chapter 1 General Description 2 MN102H55D 55G F55G 1 1 General Descri
39. ETO DST15 DST14 DST13 DST12 DST11 DST10 0519 0578 DST7 DST6 DSTS DST4 DST3 DST2 DSTI DSTO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDST23 DST22 DST21 DST20 DST19 DST18 DST17 DST16 0 0 0 1 0 0 0 0 2 Set the words to be transferred automatically In this example 1 word data is transferred so that the value 0 subtracting 1 by 1 is set to the ETCO transfer word count register ETOCNT ETOCNT x 00FD42 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETO ETO ETO CNT11 CNT10 CNT9 CNT8 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNTO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 Set the ETCO control register ETOCTR Select burst transfer mode Select one word unit and the destination pointer to be fixed Select the transfer direction is from external device to external memory Set the transfer start busy flag to en able ETOCTR x 00FD40 15 14 13 12 11 10 9 8 7 6 3 4 3 2 1 0 FLG BW DB8 DI 88 SI I I DIR EN
40. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM11CB TMI1 TMI1 TMII TMII TMII TMII TMI TMII x OOFEBS CBI5 CBI4 CBI3 CBI2 CB11 10 CB9 6 5 CB4 CB2 CBO R W R W R W R W R W R W Timer 11 Compare 0 0 0 o o 0 0 oO 0 Capture Register B on 9 16 bit access register TM11CB sets the timer11 PWM duty changes PWM and gener ates a timer 11 capture B inter rupt When capture is selected this register is read only A timer 11 capture B interrupt is generated when capture occurs When compare is selected set the PWM duty When this register matches the timer 11 binary counter a timer 11 capture B in terrupt occurs This register write only 16 bit data Use the MOV instruction to set the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM11CBX TIIC TIIC TIIC TIIC TIIC 15 14 BX13 BX12 BXII BXIO 9 BX8 BX7 6 5 4 BX3 2 x OOFEBA en ew
41. T1 T1 T1 T2 BOSC Address Data gt mm WEL WEH WAIT Xi Access Cycle 1 I Input high level Verify that the WAIT pin is low to the WAIT pin and access cycle ends before this timing 1 5 BOSC cycle later Figure 2 3 1 Handshake Wait Control Timing 1 5 Wait Cycles Data Write Chapter 2 Bus Interface When controlling the handshake wait cycles using the WAIT pin the fixed wait inter val can be determined when the read write access starts During the fixed wait inter val waits are inserted to read write access cycles regardless of the WAIT pin status When the fixed wait cycle ends the normal handshake wait control using the WAIT pin is selected This function is available when the handshake access is performed to the external memory or other devices After low level is input to the WAIT pin to end the access cycle high level must be input to the WAIT pin until BOSC signal of the next access cycle falls If this interval is short timing to input high level cannot be made In this case the next access cycle becomes no wait cycle Using this function prevents such errors T2 T1 T1 T1 T1 T1 T2 T1 T1 Ti T1 Ti i BOSC H 1 1 1 Address 1 i i 1 i 1 Data T T 1 T T
42. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 on on 15 TM9BC Count 0 Disable 1 Enable 14 T F F RS F F 0 Set TM9BC RS F F to 0 Operation 11 10 Up Down Counter Mode Selection Ignored when two phase encoding is selected 9 Count Start External Trigger Enable 8 Counter Operating Mode Selection 7 6 TM9CA TM9CB Operating Mode Selection 5 TM9BC Clear 4 TM9BC Count Range 3 TM9IOA Pin Output 2 0 Clock Source Selection 448 MN102H55D 55G F55G 1 Operate TM9BC T F F RS F F 00 Up counter 01 Down counter 10 Up when pin is high down when pin is low 11 Up when pin is high down when pin is low 0 Disable 1 Start counting on the falling edge of TMSIOB pin 0 Repeat 1 One shot counting 00 Compare register single buffer 01 Compare register double buffer 10 Capture A when pin is high Capture B when pin is low 11 Capture A when pin is high Capture B when pin is high 0 Don t clear 1 Clear when external synchronization is used 0 0 to FFFF 1 0 to TM9CA 0 RS F F output one phase PWM 1 T F F output two phase PWM 000 Timer 0 underflow 001 Timer 4 underflow 010 TM9IOB pin 011 BOSC 2 100 Two phase encoder 4x of TM9IOA pin TM9IOB pin 101 Two
43. 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Capture Register Set 16 bit access register This register is valid only when the associated compare register is set to the double buffer mode TM11CBX cannot read or write The contents of TM11CB are loaded to TM11CBX by write signal TM11CBX sets the PWM cycle When TM11BC TM11CBX a timer 11 capture B interrupt oc curs The contents of TM11CB are loaded to TM11CBX by a timer 11 capture B interrupt and TM11CBX prevents the PWM loss This register writes only 16 bit data Use the MOV instruction to set the data MN102H55D 55G F55G 463 Chapter 11 Appendix 15 TM12 15 TM12 14 TM12 CA13 TM12 12 12 CAII TM12 10 12 9 12 CA8 TM12 CA7 TM12 CA6 TM12 CAS TM12 CA4 TM12 CA3 TM12 CA2 TM12 CAI TM12 CAO R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 T12C 5 T12C AX14 T12C AX13 T12C AX12 T12C T12C AX10 T12C AX9 T12C AX8 T12C AX7 T12C AX6 T12C 5 T12C AX4 T12C AX3 T12C AX2 T12C T1
44. 1 Use the instruction to set TMnCA register and TMnCB register and only use 16 bit write operations 132 MN102H55D 55G F55G The timer compare capture register set AX TMnCAX and the timer compare capture register set BX TMnCBX are valid only when double buffer mode is selected in the compare register These registers prevent PWM losses The value cannot be written directly in these registers by software TMnCA value and TMnCB value can write to TMnCAX and TMnCBxX respectively by writing dummy data to TMnCAX and TMnCBX TMnCAX and TMnCBX registers cannot be read Chapter 4 Timers TMnMD n 8 to 12 TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn EN NLD UDI UDO TGE ONE MD1 MDO ECLR LP 52 51 50 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMnS 2 0 Clock Source Selection 000 Timer 0 underflow 001 Timer 4 underflow 010 TMnIOB 011 BOSC 2 100 Two phase encoder 4x 101 Two phase encoder 1x 110 TMSIC only timer 8 Other Reserved TMnASEL TMnIOA Pin Output 0 RS F F output One phase PWM 1 T F F output Two phase PWM TMnLP TMnBC Count Range 0 0000 to FFFF 1 0000 to TMnCA value TMnBC Clear 0 Don t clear Clear TMnBC when TMnIC 1 Only timer 8 clear unconditionally TMnCA TMnCB Operating Mode Selection Compare register si
45. e 2 N N N N w aite ea proe As lt lt lt lt Nae CE dos TAS 1 1 1 1 1 1 LU et esac zs PS 52 2 e e o 1 1 1 1 1 A Ql A A o taam lt lt lt lt as a NIN IN IN IN iN o9 9 E GI GL GI GI GI A J b A l L La lu dS es A sa L TV PS A L 4 Le 1 S o 52 1 r 1 1 1 3 5 15 2g z i i i 1 gt Oo 22 lt 1 1 1 1 1 Q e eua e O Org i are Fs ein Lf JQ Se LI Se PERDERE ERI wt f Sede lt lt lt lt x z mper ee eene ee ses ed een ee 22 on ees L 2 5 lt e Q Q F e e e e 7 5 e N N N N N o N lt lt lt lt lt lt 8 S 8 9 2 9 2 18 oo oo oo oo oo x lt lt lt lt Oo ogg TL rey at qa I Lid ete qe IL n I Lm m a 0 0 uu lt 0 0 q N N An LL An LI 2 CC lt x alii o lt al o carts Z l lt awiz S
46. 0 0 0 0 0 are changed Zero flag ZF is set if the lower 16 bits of the operation result are 0 otherwise it is reset Negative flag NF is set if bit 15 of the op eration result is 0 otherwise it is reset Carry flag CF is set if the operation resulted in a carry or a borrow out of bit 15 otherwise it is reset Overflow flag VF is set if the operation causes the sign bit to change in a 16 bit signed number other wise it is reset Extension zero flag ZX is set if all bits of the operation result are 0 otherwise it is reset Extension negative flag NX is set if the MSB of the operation result is 1 and it is reset if the MSB is O L Extension carry flag CX is set if the operation resulted in carry or a borrow out of the MSB otherwise it is reset Extension overflow flag VX is set if the operation causes the sign bit to change in a 24 bit signed number otherwise it is reset IM 2 0 indicate the mask level from 0 to 7 of interrupts that the CPU will accept from its seven interrupt input pins The CPU will not accept any interrupt at a higher level than the indicated level here interrupt enable flag IE controls maskable interrupt enable The flag is set if IE 1 and it is reset if IE 0 S 1 0 are OS software control bits These are reserved for the OS
47. 78 48 a P80 DACO PA3 IRQ3 lt 79 47 w A23 P47 AN7 WDOUT PA4 IRQ4 TM15IB 80 46 w A22 P46 AN6 STOP ADSEP 81 45 gt A21 P45 AN5 m RST J 82 44 4 gt 20 44 4 83 43 VREF MN102H55D xis i AD2 lt 86 MN1 02H55G w A17 P41 AD3 87 39 4 gt 16 40 MN102HF55G P37 RT AD5 4 3 89 37 P36 x oe Pas KB AD7 lt 91 35 P34 4 Vss 92 34 4 AD8 93 33 w P33 AD9 94 32 P32 AD10 95 31 4 A9 P31 AD11 96 lt A8 P30 KIO 12 97 29 4 P27 28 4 P26 27 4 P25 AD13 98 AD14 99 AD15 100 26 4 24 Q Ww c s CN Oc s t N i oad wem ce QN QN QN lt 8 08 O Liu EL elle 00920 x 09 c BE FEE EG lt Taga pees 6 g aaa a 55 919 m BER E 8 a Use 33 50 Figure 1 4 8 Pin Configuration in Processor Mode with 8 bit Bus Address Data Shared Mode Unused pins require handling in the circuit input pins are connected to VDD VSS output pins leave Open input output p
48. Q q Q Q Nogga mamppnxnuagawseeaooe2mosSsoQu BEES CS iw Se Z 6 x ulo x og re BE gt 309 lt STEERER lt E B 9 m crc a o 9 Use 33 50 Figure 1 4 4 Pin Configuration in Memory Expansion Mode with 8 bit Bus Address Data Shared Mode Unused pins require handling in the circuit input pins are connected to VDD VSS output pins leave Open input output pins are connected to VDD VSS or leave open depending on pin direction setting 16 MN102H55D 55G F55G 1 4 5 Memory Expansion Mode with 16 bit Bus Address Data Shared Mode 58 a P91 TM10I0A BIBT2 DMAACK1 57 lt P90 8 56 4 P87 TM9IC SBO4 SDA4 55 4 5 p86 TM9IOB SBI4 60 4 gt P93 TM10IC DMAACKO 54 lt VREF 59 a P92 TM10IOB DMAREQO 70 w P73 SBT1 DMUX 69 gt P72 SBO0 UCAS 68 P71 SBIO LCAS CAS 67 P70 SBTO RAS 72 gt 75 5 1 71 P74 SBI1 66 4 65 4 P97 AN3 64 4 gt P96 AN2 63 a P95 AN1 62 P94 ANO 61 4 AVss 74 NNA AWA 75 NMI PAO IRQO PA1 IRQ1 PA2 IRQ2 PA3 IRQ3 m o 78 4 79 PA4 IRQ4 TM15IB 80 ADSEP lt 81 RST 82 Figure 1 4 5 Pin Configuration
49. 8 48 8 BSET abs16 bp mem8 abs16 1 lt lt bp 8 6 16 F5 D0 bp abs16 l abs16 h BSET abs24 bp mem8 abs24 1 lt lt bp 8 6 24 F3 FE D0 bp abs24 l abs24 m abs24 h BSET d8 An bp mem8 An d8 1 lt lt bp F5 90 bp d8 0 mems An d8 F5 98 bp d8 An A1 F3 FF 90 bp d8 An A2 F3 FF 98 bp d8 Quick decoder ON This setting cannot be made in this series Notes 15 16 bit computation 16 Performed under the conditions of bus lock and disabled interrupts 540 MN102H55D 55G F55G Instruction Mnemonic BCLR Dm An Operation mem8 An amp Dm PSW mem8 An amp Dm mem8 An Chapter 11 Appendix Machine Code F0 30 An lt lt 2 Dm 716 BCLR imm8 abs16 mem8 abs16 amp imm8 mem8 abs16 F4 E7 abs16 l abs16 h imm8 BCLR imma abs24 mem8 abs24 amp imm8s mem8 abs24 F4 4F abs24 l abs24 m abs24 h imm8 BCLR imme 48 mem8 An d8 amp imm8 8 8 F4 EC An d8 imm8s BCLR abs16 bp mem8 abs16 amp 1 lt lt bp mem8 abs16 F5 D8 bp abs16 l abs16 h BCLR abs24 bp mem8 abs24 amp 1 lt lt bp mem8 abs24 F3 FE D8 bp abs24 l abs24 m abs24 h BCLR d8 An bp mem8 An d8 amp 1 bp mems An d8 F5 B0 bp d8 An A0 F5 B8 bp d8 1 F3 FF BO bp d8 2
50. Lae gt 4 isl pisi 2 Be 9 3 8 3 58 3 8 8 5 3 8 3 53 8 8 8 2 9 o o o E g o o o lt On lt T2 u qut Ta WE eee uut gs 2 m m mo r3 p r3 ima t Bp leg dm m m 9 2 2 E E E 2 g E u 9 2 S E 8 m a m 025 4 ae 5 3 3 do 5 3 3 o 3 3 lt EA 272 ox 5 E x S gt 9 to a 2 2 5 c o mr 9 5 2 2 d 3 5 3 2 MN102HF55G H55G H55D 76 Chapter 2 Bus Interface Table 2 2 3 WE Late and Short Modes Address Data Shared Mode aeta iw ei mm eie aet e t Nie a P Bae cant v a n Rm ES i Teri Se le cir aT qnit eh D sk gt a P Ne T e PEE ODE PUN ME E od LONE gt os gt 9 3 3 3 g 3 g 3 3 5 2 8 3 r 2 2 g E3 Be E3 Be
51. capacitance values vary depending on the crystal oscillator Figure 1 4 10 OSCI OSCO Connection Example X XO o 32 kHz 166 kHz 100pF 200pF 100 pF 200 pF 32 kHz 166 kHz 77 Note Oscillation Circuit Oscillation The capacitance values vary depending on the crystal oscillator Circuit Figure 1 4 11 XO Connection Example Pd c Di RST 777 10uF 100pF d sw 77 7 77 Figure 1 4 12 Reset Pin Connection Example RE o RESET Delay Circuit _ gt WAIT Figure 1 4 13 WAIT Signal Control Circuit Connection Example Chapter 1 General Description Package Code LQFP100 P 1414 16 00 020 14 00 0 10 76 16 00 0 20 14 00 0 10 0 10 0 10 SEATING PLANE 0 15 095 Unit mm Body Material Epoxy Resin Lead Material FeNi42 Alloy Lead Finish Method Solder Plating Figure 1 4 14 External Dimensions 100 pin LQFP External dimensions are subject to change Before using please contact your nearest sales office for the latest product specifications MN102H55D 55G F55G 49 Chapter 1 General Description 50 MN102H55D 55G F55G Chapter 2 Bus Interface Chapter 2 Bus Interface 2 1 2 1 1 Overview Summary of Bus Interface The MN102H55D 55G F55
52. ex rpm pee 2 o a B m esie deer ts p AN d 4 4 4 E 5 lt lt 7 N ADEA OEO SA a EEA A DX lt 4 a o lt lt ike rhe ice ane tee X Q SES NS ee E s g s NE we ut we 8 e 692 98 Pos LE Lr as 11 a opo EE OR lo mum lt s S m m omo fos nas di m m s 3 s 3 m m lt 3 lt lt lt lt 5 x x o o 9 9 o o m m Chapter 2 Bus Interface 80 MN102HF55G H55G H55D 2 3 Handshake Wait Control 2 3 1 Overview The MN102H55D 55G F55G controls handshake wait cycles using WAIT pin when reading or writing the data for external memory or other devices The MN102H55D 55G F55G determines the wait cycles using WAIT pin when read ing or writing the data When starting read write access input high level to the WAIT pin High level must be input until BOSC signal falls in T2 interval shown in Figure 2 3 1 because the WAIT pin input level is checked every time BOSC signal falls While the WAIT pin is high level the access cycle for the external memory or other devices is continued On the other hand when the WAIT pin becomes low level the access cycle ends 1 5 BOSC cycles later after the next BOSC signal falls
53. m Register Selector gt x 4 P is selected by the P3LMD register or the PSHMD register The input or output direction of KI7 to KIO is determined automatically by setting the P3LMD register or the P3HMD register P37 P30 MN102H55D 55G F55G 267 Chapter 8 Ports Table 8 1 2 Port Block Diagram 5 12 Port Pin Name Block Diagram Port 4 P47 to P40 A23 to A16 STOP Da WDOUT P4PLU 7 0 Register i Y AN7 to AN4 P4OUT 0 lt gt Register 9 Address Output 1 AES ele Selector STOP Output P46 gt WDOUT Output P47 gt _ P47 P40 P4LMD 7 0 Register 0 P4DIR 7 0 lt Register Address Output Control gt Selector STOP Output Control P46 gt WDOUT Output Control P47 gt P4IN 7 0 4 4 Port Input AN7 AN4 A D Input Note The set value of the P4DIR register is valid only when the port function is selected by the P4LMD register or the P4HMD register The input or output direction of STOP and WDOUT is determined automatically by setting the P4LMD register or the P4HMD register 268 MN102H55D 55G F55G Table 8 1 2 Port Block Diagram 6 12 Chapter 8 Ports Port Pin Name Block Diagram Port 5 P57 to P50 TM130A TM130B TM140A P5PLU 7 0 Regist
54. CB2 CBO 0 0 0 0 0 0 0 1 4 Set TM8NLD TM8EN TM8MD register to 1 and 0 respectively This enables TM8BC and RS F F 5 Set TM8NLD and TM8EN to 1 This starts the timer Counting begins at the start of the next cycle Interrupt Enable Setting 6 Enable interrupts after clearing all prior interrupt requests To do this set IQOLV 2 0 of the external interrupt 0 control register IQOICH to the interrupt level 0 to 6 TM8AIR of the timer 8 capture A interrupt control register TM8AICL to 0 TM8BIR of the timer 8 capture B interrupt control register TM8BICL to 0 TM8AIE of TM8AICH register to 1 and TM8BIE of TM8BICH register to 1 Thereafter a timer 8 capture or B interrupt occurs when TM8BC counter matches TM8CA register or TM8CB register is generated Timer 8 functions as an event counter Timer 8 does not operate stably when BOSC stops in STOP mode All external inputs are sampled on BOSC synchronized with BOSC when the external clock operates The event counter frequency should be less than BOSC A 8 5 MHz with a 34 MHz oscillator Figure 4 4 2 shows an example of interrupt timing with an up counter Chapter 4 Timers TM8CA 0004 TM8CB 0002 TM8BC 0000 0001 0002 0003 0004 0000 0001 0002 0003 0004
55. Saturation flag controls whether or not the CPU performs a saturation operation When this bit is 1 the CPU execute a saturate operation When this bit is 0 the CPU operates a normal operation The PXST instruction can reserve the meaning of this bit for the next instruction Figure 1 1 1 Processor Status Word PSW Please refer to 11 5 MN102H00 series High speed Linear Address Instruction Set for the flags reflected by instructions MN102H55D 55G F55G 5 Chapter 1 General Description Internal Registers Memory and Special Function Registers Program Counter 23 PC Address Registers 23 AO Al A2 Data Registers 23 DO D1 D2 D3 Multiplication Division Register 15 MDR Processor Status Word 15 PSW Memory Special Function Registers I O Ports ROM RAM CPUM EFCR IAGR NMICR xxICR SCCTRn TRXBUFn SCSTRn ANCTR ANnBUF TMn BCn BRn MEMMD PnOUT PnIN PnDIR 6 MN102H55D 55G F55G The program counter specifies the 24 bit address of the program during the execution The address registers specify the data location on memory Of four registers is assigned as the stack pointer The data registers perform all arithmetic and logic operations When the byte length 8 bit or word length 16 bit data is trans ferred to memory or to another regi
56. k wees SE bes F 8 F y Lala ERES lt 2 05 1 1 bep oam 9L E ied sedes dst sss ss ir gh Er 5 pe qe n e e zx lt lt lt lt cd gt gt s E MU E tee AE fy a Ts T a a oe 7 7 3 e 5 1 1 1 1 1 N AE gt a On Sr Saas pee aa lt lt 5 NIN IN iN GN a aum amm amm uu D RON MSN M UM CREE 5 11 Bl Nc Disc c eai o o Bie eir 9 9 5 ss s 52217 e 2g t 1 1 1 1 1 1 E dHNLE 1 Ea Sq Se ru Cee eee eee eee Tam aker 0 La BE lt lt 2 P 7 o c S lt aie der ce 2 lt 2 FEE od oe Ia Pk cer pag yy DEDE oe a oe XE SA e Sheer HS gt 2 S niic E ce lo ie oe z 5 o i e Lou N N 5 4 N lt lt o 9 lt c 3 2 9 Q a x 72 a mE aps ma M 7
57. mo 0 o Orn Ot On or N 0 s D N ORDA O amp N G lt lt 2 lt NQ oo Oo GO iD iO o a m Sia 222526 2 S 25555 gt m x 99 E aga lt 0 LO B Li n m e 9 o a D Use 33 50 Figure 1 4 1 Pin Configuration Single chip Mode Unused pins require handling in the circuit input pins are connected to VDD VSS output pins leave Open input output pins are connected to VDD VSS or leave open depending on pin direction setting MN102H55D 55G F55G 13 Chapter 1 General Description 1 4 2 Memory Expansion Mode with 8 bit Bus Address Data Separate Mode Ya O Q lt sls 2 z o a na lt lt 20 qzr Eo xs 5 om 3 HAD 5 Of lt Am CHA 555990 NEP Oooo 89952 55585 55 95 OLANDA y ERE Re QN QN O O P P F F OO GO XO iO 1O 1O 0 LO LO PAO IRQO 76 50 PA1 IRQ1 77 49 PA2 IRQ2 78 48 PA3 IRQ3 79 47 PA4 IRQ4 TM15IB 80 46 81 45 RST 82 44
58. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 6 5 3 1 0 514 P92 Input Output Signal Switch P91 Input Output Signal Switch P90 Input Output Signal Switch MN102H55D 55G F55G 00 Port 01 TM10IOB input DMAREQO input 10 TM10IOB output 000 Port 001 TM10IOA input 010 TM10IOA output 011 BIBT2 output 100 1 output 00 Port 01 TM8IOA input 1 input 10 TM8IOA output 11 BIBT1 output P9LMD x OOFFEC Port 9 Mode Register L 8 bit access register P9LMD sets a signal output to the port 9 7 6 5 4 3 2 1 0 P9 P9 P9 P9 P9 P9 HMD5 HMD4 HMD3 HMD2 HMD1 HMDO0 R R R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 5 P97 Input Output Signal Switch 4 P96 Input Output Signal Switch 3 P95 Input Output Signal Switch 2 P94 Input Output Signal Switch 1 0 P93 Input Output Signal Switch 0 Port 1 AN3 input 0 Port 1 AN2 input 0 Port 1 AN1 input 0 Port 1 ANO input 00 Port 01 TM10IC input 10 DMAACKO output Chapter 11 Appendix P9HMD x OOFFED Port 9 Mode Register H 8 bit access register 9 sets a signal output to the port 9 MN102H55D 55G F55G 515 Chapter 11 Appendix 7 6 5 4 3 2 1 0 PA PA PA PA PA MD4 MD3 MD2 MDI R R R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0
59. 6 5 2 ATOICH ATO LV2 LV1 Lvo IE 00 RW RR 0 Transfer End 0 Interrupt Control Register 8 bit access register ATC 0 Transfer End Interrupt Set the level from 0 to 6 ATOICH sets an ATC 0 transfer Level Setup end interrupt level and enables an interrupt ATC 0 Transfer End Interrupt 0 Disable Enable Flag 1 Enable This register allows only byte accesses Use the MOVB in struction to set the data MN102H55D 55G F55G 387 Chapter 11 Appendix 7 6 5 4 3 2 1 0 1 1 IR ID R R R R W R R R R 0 0 0 0 0 0 0 on o 0 4 ATC 1 Transfer End Interrupt Request Flag 0 ATC 1 Transfer End Interrupt Detect Flag 7 6 5 4 3 2 1 0 gt i ATI IE R R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 ATC 1 Transfer End Interrupt Enable Flag 388 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 Interrupt undetected 1 Interrupt detected 0 Disable 1 Enable AT1ICL 1 Transfer End Interrupt Control Register 8 bit access register AT1ICL requests and verifies an ATC 1 transfer end interrupt This register allows only byte accesses Use the MOVB in struction to set the data
60. 83 ADO 84 AD1 lt 85 AD2 lt 86 AD3 87 AD4 gt 88 AD5 39 89 AD6 s 90 AD7 91 Vss n 92 AD8 lt J 93 AD9 lt 94 AD10 4 3 95 AD11 96 AD12 97 AD13 98 MN102H55D MN102H55G MN102HF55G TOP VIEW AD14 lt 99 AD15 100 6 0 1 2 3 4 5 6 8 9 53 gt 5 5 4 5 14 5 2 52 gt P84 TM71IO SBOS SDA3 51 gt P83 TMAIO 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 ALE ALE 3 WORD P54 BREQO 19 RE P61 2 P55 BRACK lt WEL P62 3 WE WEH P63 4 0 20 6 2 lt A1 P21 SBI2 A2 P22 SBO2 P50 CS0 TM13OA 4 5 P52 CS2 TM140A lt 53 53 14 gt 8 P60 WAIT SBT2 s 1 P51 CS1 TM13OB 9 2 4 3 XI PB1 w lt 20 lt 21 22 OSCI 23 OSCO 4 24 oe 25 Chapter 1 General Description P82 TMOIO SBT3 SCL3 SBI2 P81 DAC1 P80 DACO A23 P47 AN7 WDOUT a gt A22 P46 AN6 STOP lt gt 21 45 5 lt gt 20 44 4 VREF A19 P43 4 A18 P42 4 5 A17 P41 gt A16
61. Address Data Separate Mode 8 bit Bus DRAM WEH and WEL Method Address Data Separate Mode 16 bit Bus Burst ROM Access Address Data Separate Mode 8 bit Bus Burst ROM Access External Memory Control Signal Timing RE Late and Short Modes Address Data Shared Mode WE Late and Short Modes Address Data Shared Mode RE Late and Short Modes Address Data Separate Mode WE Late and Short Modes Address Data Separate Mode ALE Late and Long Modes Address Data Shared Mode AD Long Mode Address Data Shared Mode Comparison of MN102H55D 55G F55G MN102B00 MN102LOO senem enn Interrupt Vector and Class Assignment Handler Preprocessing Handler Postprocessing Table 3 1 5 Table 4 1 1 Table 4 1 2 Table 4 3 1 Table 4 3 2 Table 4 5 1 Table 4 5 2 Table 4 7 1 Table 5 1 1 Table 5 1 2 Table 5 1 3 Table 5 2 1 Table 6 1 1 Table 6 1 2 Table 6 3 1 Table 6 3 2 Table 7 1 1 Table 7 1 2 Table 7 3 1 Table 7 3 2 Table 8 1 1 Table 8 1 2 Table 10 1 1 Table 11 4 1 List of Interrupt Control Registers 91 8 51 Timer Functions 108 List of 8 bit Timer Control Registers
62. TGO TGO TGO TGO R R R R R R RW RW R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 9 8 Set Trigger Conditions for IRQ4 Pin Interrupt 7 6 Set Trigger Conditions for IRQ3 Pin Interrupt 5 4 Set Trigger Conditions for IRQ2 Pin Interrupt 3 2 Set Trigger Conditions for IRQ1 Pin Interrupt 1 0 Set Trigger Conditions for IRQO Pin Interrupt TG1 TGO Trigger Condition 0 0 Low Level 0 1 Both Edges Positive edge Negative edge 1 0 Falling edge Negative edge Rising edge Positive edge Chapter 11 Appendix Ln IRQTRG x O0FCBO External Interrupt Condition Setup Register 16 bit access register IRQTRG sets the trigger condi tions for external interrupts MN102H55D 55G F55G 39 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KI7 6 6 KIS KIS 2 KD KH KII KIO KIO TGO TGO TGO TGO TGO TGO TGI TGO TGI TGO R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 Set Trigger Conditions for KI7 Pin Interrupt 13 12 Set Tr
63. TM8 TM8 8 8 TM8 TM8 8 8 TM8 8 8 TM8 8 TM8 EN NLD UDI UDO TGE ONE MDI MDO ECLR ASEL 52 SI SO 0 0 0 0 0 0 0 0 0 1 100 1 0 1 2 Set the timer 8 looping value to the TM8CA register the valid range 1 to x FFFF The TM8BC register counts from 0 to x IFFF when writing x IFFF to the TM8CA register 8 x 00FE84 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 8 8 8 8 8 8 8 8 TM8 8 8 8 8 TM8 CA14 CAI3 12 10 CA9 CA6 CAS CA2 CAO 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 3 Set the timer 8 interrupt value to the TM8CB register the valid range 0 to TMS8CA Whenever the up or down counter reaches this value a capture inter rupt occurs at the beginning of the next cycle TM8CB x 00FE88 15 CB14 CB13 CB12 CB8 5 CB2 CBO 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 4 Set TM8NLD TM8EN of the TM8MD register to 1 and 0 respectively This enables TM8BC and RS F F 5 Set TM8NLD and TM8EN of the TM8MD register to 1 This starts the timer Counting begins at the start of the next cycle Interrup
64. 79 PA3 IRQ3 TTL Yes Programmable Hi Z Hi Z Hi Z TTL Yes Programmable Hi Z Hi Z Hi Z m 5 82 RST CMOS Yes No Low Input Low Input Low Input High High 84 P00 D00 AD00 TIL Yes Programmable Hi Z Hi Z Hi Z Hi Z excapt P00 Hi Z POO 85 PO1 DO1 ADO1 TTL Yes Programmable Hi Z Hi Z HZ Hi Z excapt P01 Hi Z excapt 86 P02 D02 AD02 TTL CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Z excapt P02 Hi Z excapt P02 87 P03 D03 AD03 TTL Yes Programmable Hi Z Hi Z Hi Z Hi Z excapt Hi Z excapt TIL Yes Programmable Hi Z Hi Z Hi Z Hi Z excapt P04 Hi Z excapt P04 TIL Yes Programmable Hi Z Hi Z Hi Z Hi Z excapt P05 Hi Z excapt POS 90 P06 D06 AD06 TTL CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Z excapt P06 Hi Z excapt P06 91 P07 D07 AD07 TTL Yes Programmable Hi Z Hi Z Hi Z Hi Z excapt P07 Hi Z excapt P07 P10 D08 A CMOS Programmable Hi Z Hi Z Hi Z excapt P10 Hi Z excapt P10 P11 D09 A CMOS Programmable Hi Z Hi Z Hi Z excapt P11 Hi Z excapt P11 P12 D10 A CMOS Programmable Hi Z Hi Z Hi Z excapt P12 Hi Z excapt P12 96 13 011 011 TTL Hi Z Hi Z Hi Z excapt P13 Hi Z excapt P13 97 P14 D12 AD12 TTL CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Z excapt P14 Hi Z excapt P14 98 P15 D13 AD13 TTL Yes Programmable Hi Z Hi Z Hi Z Hi Z excapt P15 Hi Z excapt P15 99 16 014 014 TIL Yes Programmable Hi Z Hi Z Hi Z Hi Z excapt P16 Hi Z excapt P16 100 P17 D15 AD15 TIL Yes Programmable Hi Z Hi Z Hi
65. 83 43 MN102H55D MN102H55G 03 87 39 gt 88 MN102HF55G id 05 89 37 VIEW D7 91 35 Vss 92 34 P10 TM8IOB 93 33 P11 TM8IC 94 32 12 3 95 31 P13 TM111OB 96 30 14 111 97 29 28 27 P15 TM121OA 4 gt 98 P16 TM12IOB 3 99 P17 TM121C 100 26 Q oxi a oort a PA renare NANNAN lt lt lt re 9 m a BE SESS SSPe eRe ages ES ExS RRS see os m x gt S 8 a lt gt 232 B I2 Eo ale Sag m 1 IO IO IO lt lt m B 8508 m t e P82 TMOIO SBT3 SCL3 SBI2 s P81 DAC1 P80 DACO A23 P47 AN7 WDOUT A22 P46 AN6 STOP A21 P45 AN5 A20 P44 AN4 lt VREF lt gt A19 P43 A18 P42 4 5 A17 P41 16 40 A15 P37 lt gt A14 P36 A13 P35 12 34 lt A11 P33 4 9 A10 P32 A9 P31 8 30 KIO A7 P27 A6 P26 gt A5 P25 A4 P24 TM15IA Use 33 50 Figure 1 4 2 Pin Configuration in Memory Expansion Mode with 8 bi
66. xa A cle OS syde L 22 beads es D 2 lt STIN Ol lo o S lt Cic N z z D 8 gt D D 5 HO d 44 H e 8 RE 8 4 pe8 S eed s ss pns eel sa pe Mee oe si l ecd reor dE re 2 5 ep g 5 e L N NI E amp lt lt 9 e 5 bd NM 2 L 2 L L V MM c 9 o uei ines Lote PAL SS me mess DUM Do OT 1 N 2 z c 5 5 T FL IIO r 7 rT vr 7777 voe O 5 5 8 14 Ps 4 lt lt 14 a LEM 4 o z IN N GINE GINE GINE iN z E 9 TCTCI POT OW Jr We sua NES G lt amp DON l L l z 2 c 5 z 3 S lt ali lt e g lt E i oc g Q T T T a ae a a a 5 a T i 10 02 c I 1 Y 910 10 c 5 NEE lt 10 0 c I 5 5 9 10 0 c I L1 g Q omm S omm o A lt lt
67. 100 26 4 orn c st O O O aA 0 OQ w Qo pe XO m a w 9 a NNNN 8 0 ALFER 298 o z Im O m o9 E E gt gt gt mn F z lt REE oe g TY E DNB ee m S 8 0 0 uj x a c IN b x m 77 BBB t5 9 a Use 33 50 Figure 1 4 7 Pin Configuration in Processor Mode with 16 bit Bus Address Data Separate Mode Unused pins require handling in the circuit input pins are connected to VDD VSS output pins leave open input output pins are connected to VDD VSS or leave open depending on pin direction setting MN102H55D 55G F55G 19 Chapter 1 General Description 1 4 8 Processor Mode with 8 bit Bus Address Data Shared Mode van 9 a lt lt ole vw A A o lt lt lt m 0 5 M w slan2 om moo io omm 5 lt Cle m 5zr6oSSg8m oa a oc 2553535 8523 RGmana 8225 2 5555 55 855 20000255444 N c N t gt co x EXIIT co wo IM oe T 0 09 P Q auo T Ps P PF O O do iO tO tO LO LO PAO IRQO 76 50 w P82 TMOIO SBT3 SCL3 SBI2 PA1 IRQ1 lt t 77 49 gt P81 DAC1 PA2 IRQ2
68. 2 1 1 1 ife To Et 2 1 1 2 E 2 1 1 3 OVEIVIEW ui hae B ted a ane 5 1 2 Basic Specifications 9 1 3 Block Diagram 11 1 42 Descriptor Ue RR Ee RE 13 1 4 1 Single chip Mode 13 1 4 2 Memory Expansion Mode with 8 bit Bus Address Data Separate Mode 14 1 4 3 Memory Expansion Mode with 16 bit Bus Address Data Separate Mode 2 15 1 4 4 Memory Expansion Mode with 8 bit Bus Address Data Shared Mode Cri tere deer E Pd 16 1 4 5 Memory Expansion Mode with 16 bit Bus Address Data Address Data Shared Mode 17 1 4 6 Processor Mode with 8 bit Bus Address Data Separate Mode 18 1 4 7 Processor Mode with 16 bit Bus Address Data Separate Mode 19 1 4 8 Processor Mode with 8 Bus Address Data Shared Mode 20 1 4 9 Processor Mode with 16 bit Bus Address Data Shared 21 1 4 10 List of Pin Functions 22 Chapter 2 Bus Interface 2 1 Summary of Bus Interface u u 52 2 1 1 APA PPM 52 2 1 2 Control Registers 53 2 1 3 Memory Connection Examples 62 2 1 4 Access to External Memory sees 67 2 2 3Gontrol Sighals
69. 6 KIS KIS KI2 KIO KIO TGO TGO TG1 TGO TGO TG1 TGO TGO TGO TGO 0 0 0 O 0 0 0 0 0 0 KEYCTR x 00FCB4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KI7 KIS KD KIO EN EN EN EN EN EN EN EN 0 0 0 0 1 1 1 1 MN102H55D 55G F55G 97 Chapter 3 Interrupts When applying to a remote con troller the CPU moves to the STOP mode to reduce power consumption When an inter rupt occurs during the STOP mode the CPU waits for oscilla tion stabilization The CPU waits for up to 4 369 ms with a 30 MHz oscillator After that the program branches to 080008 After the program branches to 080008 the program gener ates the interrupt service routine start address and then branches to that address During the interrupt service rou tine disable an interrupt by set ting the IM flag of PSW register to the interrupt level and the IE flag to 0 In addition other inter rupts except nonmaskable inter rupts are not accepted unless PSW register is set Key determination is performed by reading the port 3 input regis ter 98 MN102H55D 55G F55G 5 Enable interrupts after clearing all prior interrupt requests To do
70. IDST23IDST22 DST21 IDST20 DST19IDST18IDST17 DST 16 R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 undefined undefined undefined Jundefined undefined undefined undefined undefined 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 412 MN102H55D 55G F55G x 00FD48 ETC 0 Destination Address Pointer 16 24 bit access register ETODST sets the transfer desti nation address When the desti nation pointer increment bit is set to be fixed the transfer source address do not change When the source pointer incre ment bit is set to increment in crement by 1 in the byte transfer and by 2 in the word transfer This register writes only 24 bit data or 16 bit data Use the MOV instruction or the MOVX instruction to set the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETI ETI ETI ETI ETI ETI ETI ETI ETI FLG BW DB8 DI SB8 SI DIR EN R W R W R W R W R W R W R W R R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 o 0 0 0 0 15 Transfer Busy Start Flag 0 Disable 1 Transfer start transfer in progress 13 Transfer Mode 0 One byte word transfer 1 Burst transfer 12 Transfer Units 0 Word 1 Byte 11 Destination Bus Width 0 16 bit 1 8 bit 10 Destination Pointer 0 Fixed Increment 1 Increment 9 Source Bus Width 0 1
71. eui J9 S 6e1 ejqnop se pesn si JejsiDeJ 141 JOU peed jouueo 1ejsiDe 141 m UOHONASU XAOIN 24 10 AON eur es uomejedo sseooe 1IQ pz JO 119 91 sk AON eur uonejedo Duunp sseooe 11 9 uononijsu gAOIN 95 559006 16 8 519 Chapter 11 Appendix 1 HOd GNW0d GWW8d 0 400 4 9 O GNW16d GWH6d O O 024400 X 00434300 X 1000 1nOld 1NOZd O 1 541 00 400 fY1d0d O M1d d IMS8d HMS8d 044500 JO1JUOD 06 400 390334 39d33M 35Qq3aa1v 0843400 X pe JeseJ pe JeseJ pe JesaJ 0 3300 31909 Jngova 6 me 07 400 qv AnNasnv ANGONV AdnaZnv 01 400 YLONV p A189S91 00
72. mode 9 Bit Order Selection 0 LSB first 1 MSB first Select only when the character length is 8 bit 8 mode Selection 0 mode off 1 mode on 7 Character Length 0 7 bit 1 8 bit 6 4 Parity Bit Selection 000 None 100 0 output low 101 1 output high 110 Even 1s are even 111 Odd 1s are odd Others Reserved 3 Stop Bit Selection 0 1 bit 1 2 bit asynchronous mode SBO4 Output Hold Time 0 More than BOSC cycles clock synchronous mode 1 More than timer 1 underflow cycles 1 0 Serial 4 Clock Source Asynchronous mode mode 428 Selection MN102H55D 55G F55G 01 Timer 1 underflow 1 8 11 Timer 5 underflow 1 8 Clock synchronous mode 00 SBT4 pin 01 Timer 1 underflow 1 8 10 Timer 5 underflow 1 2 11 Timer 5 underflow 1 8 SCACTR 00 Serial 4 Control Register 16 bit access register SC4CTR sets serial 4 operating conditions Change when transmission or reception is not in progress The SBO4 output hold time is extended only when SBT4 pin is selected as serial 4 clock source Chapter 11 Appendix 1615 3 2 1 0 SCATRB sc4 sca sca SC4 sca sca SC4 sca TRB7 TRB6 TRBS TRB4 TRB3 TRB2 TRBI TRBO x OOFDA2 R W R W RAV Serial 4 Transmit on R
73. 4 Set the ATCO control register ATOCTR Select a serial 0 reception end interrupt Set the source pointer to be fixed and the destination pointer to increment by 1 Select one byte unit and one byte word transfer as the transfer mode Set the transfer start busy flag to disable Select 16 bit as both source bus width and destination bus width ATOCTR x 00FD00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATO BW DB8 DI SB8 SI 103 IQ2 1Q1 1Q0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 5 Enable an ATCO transfer end interrupt ATOICH x 00FCA9 7 6 5 4 3 2 1 0 ATO ATO ATO ATO LV2 LV1 LVO 7 7 IE 1 0 1 1 In this example error cannot be detected during the transfer When error is needed to be detected set the ATOBW flag of the ATOCTR register to to enable the word transfer This allows to transfer the data between the SCOTRB register and the SCOSTR register The 5 word 10 byte memory space is required Checking the contents of the SCOSTR register transferred to the memory during the interrupt service routine indicates each reception status Serial Setup 6 Disable a serial 0 reception end interrupt If an interrupt is enabled the serial 0 reception end interrupt is processed after ATC
74. BIBT1 Ee a d y _ 010 y OE x o dox 4 aed ag mum PE Late 0 5 mode I i Short 0 mode 1 RE Gt 1 1 ae Late 1 mode r Short 0 5 mode r i RE Late 2 mode Short 1 mode I i 1 RE RE Short 1 5 mode Table 2 2 5 WE Late and Short Modes Address Data Separate Mode Late Mode Short Mode Base Clock Bosc 74e 06 358 3 23 0 lt o ANE Late 1 mode a ERA WE 2225 Late 2 mode n Late 3 mode ae G BOSC BBT2 1 i 3 BIBT1 i WE de Short 0 mode WE 22 12 Short 0 5 mode T WE qo Short 1 mode 1 Short 1 5 mode 78 MN102HF55G H55G H55D Chapter 2 Bus Interface Long Mode Table 2 2 6 ALE Late and Long Modes Address Data Shared Mode Late Mode 19 MN102HF55G H55G H55D fut
75. P2DIR x OOFFE2 Port 2 Input Output Control Register 8 bit access register P2DIR controls the port 2 input output P3DIR x OOFFE3 Port 3 Input Output Control Register 8 bit access register P3DIR controls the port 3 input output MN102H55D 55G F55G 495 Chapter 11 Appendix F 6 5 4 3 2 1 0 P4 PA PA PA P4 P4 P4 DIR7 DIR6 DIRS DIR4 DIR3 DIR2 DIR1 DIRO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port4 Input Output 0 Input 1 Output 7 6 5 4 3 2 1 0 5 5 5 5 5 5 5 5 DIR7 DIR6 DIRS DIR4 DIR3 DIR2 DIR1 DIRO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port5Input Output 0 Input 1 Output 7 6 5 4 3 2 1 0 P6 P6 P6 P6 DIR3 DIR2 DIRI DIRO R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 3 0 Port6 Input Output 0 Input 1 Output 7 6 5 4 3 2 1 0 P7 P7 P7 P7 P7 P7 0185 DIR4 DIR3 DIR2 DIRI DIRO R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 5 0 Port 7 Input Output 0 Input 1 Output 496 MN102H55D 55G F55G PADIR x OOFFE4 Port 4 Input Output Control Register 8 bit access register
76. R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADBO ADBO ADBO ADBO 23 A22 A21 A20 19 A18 17 A16 R R R R R R R R R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADBI ADBI ADBI ADBI ADBI ADBI ADBI ADBI ADBI ADBI ADBI ADBI 15 Al4 AI3 AI2 All AIO A9 8 7 6 5 4 2 1 0 R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADBI ADBI ADBI ADBI ADBI A23 A22 A21 A20 19 A18 A17 A16 R R R R R R R R R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 396 MN102H55D 55G F55G ADBO x O0FCD2 Address Break 0 Address Pointer 16 24 bit access register ADBO sets the address to stop address break 0 operation This register writes only 24 bit data or 16 bit data Use the instruction or the MOVX instruction to set t
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78. TMOBR 00 10 TMO TMO TMO TMO TMO TMO TMO BR7 6 BRS BR3 BR2 BRI BRO 0 0 0 O 1 3 Load TMOBR value to the timer 0 binary counter At the same time select BOSC 2 as the clock source TM0MD x 00FE20 7 6 5 4 3 2 1 0 EN LD 51 50 0 1 0 0 4 Set TMOLD to 0 and TMOEN to 1 This starts the timer Counting begins at start of the next cycle When the timer 0 binary counter reaches 0 and the value from the base register is loaded at the next count a timer 0 underflow interrupt request will be sent to the CPU Chapter 4 Timers Timer 8 Setting 1 Set the operating mode in the timer 8 mode register TM8MD Set counting stop 1 Select up counting Select the timer 0 underflow as the clock source Set T F F as Use the MOV instruction to set TMSIOA pin output Select the double buffer mode in the compare register write operations the data and only use 16 bit TM8MD x 00FE80 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 The timer 8 binary counter 8 TM8 TM8 8 TM8 TM8 TM8 TM8 TM8 TM8BC is stopped and EN NLD UDI UDO TGE ONE MD1 MDO ECLR LP ASEL 52 s SO TMBBC register RS F F are 0 0
79. 14 12 AIO ao A8 A7 A6 AS as A3 AL A0 Address Pointer At reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADBn ADBn ADBn ADBn ADBn ADBn ADBn ADBn A23 22 A21 A20 19 18 A16 At reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MN102H55D 55G F55G 281 Chapter 9 System Control 282 MN102H55D 55G F55G 9 1 3 Address Break Setup Examples When an error occurs in the routine on the internal ROM the program cannot be corrected normally An error however can be avoided by storing the solution program on the internal RAM or the external RAM and setting the address break For example the CPU stores the address where the instruction execution is halted and the substitute program on the nonvolatile memory connected externally to the MN102H55D 55G F55G Then the CPU accesses the nonvolatile memory from the main routine after reset Finally the CPU loads the address where the instruction execution is halted and the substitute program on the register or the internal RAM when the address break function is required In this example execute the subroutine 2 on the internal RAM without executing the subroutine 1 on the internal ROM lt 1 Primarily the program subroutine calls from Interrupt Service Routine the main routine to the subroutine 1 by the JSR instruction
80. 2 Read enable signal fall delay time 2 RE 617 Other modes Fig 11 1 8 to9 618 Read enable signal rise delay time Fig 11 1 4006 10 RE Late 1 mode Fig 11 1 4 to 5 20 Write enable signal fall delay time 1 Fig 11 11 7409 WEL Other modes Fig 11 1 4105 Fig 11 1 7 to 9 Late 1 mode x Fig 11 1 4 t0 5 2W L S 2 Fig 11 1 7 to 9 20 Write enable pulse width time WEH WEL Other modes Fig 11 1 4105 Fig 11 1 7 to 9 W is the number of waits W 0 0 5 1 1 5 7 L means WE late mode L 1 2 3 5 means WE short mode S 0 0 5 1 1 5 3 0 V to 3 6 V Output Signal Characteristics Vss 0 V 40 to 85 CL 70 pF Ceo Parameter Symbol Conditions Unit lt Serial Interface Signal Output Timing Synchronous Serial Transmission Transfer data delay time SBO4 0 e 2 Transfer data hold time transfer in Transfer data hold time Transfer end timing at SBT input Fig 11 1 15 te Fig 11 1 16 5 ns SBO4 0 Note Set SBO4 0 output hold time to BOSC cycle or more in SCnCTR n 4 0 register Transfer data hold time Transfer end timing at SBT output SBO4 0 Chapter 11 Appendix MN102H55D 55G F55G 325 Chapter 11 Appendix 326 AC Timing Voltage Level Vppx0
81. AT1ICH x OOFCAB ATC 1 Transfer End Interrupt Control Register 8 bit access register AT1ICH enables an ATC 1 transfer end interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the ATOLV 2 0 bits of the ATOICH register Chapter 11 Appendix e pee m AT2ICL eee tM ATC 2 Transfer End 0 Interrupt Control Register 8 bit access register ATC 2 Transfer End Interrupt 0 No interrupt requested AT2ICL requests and verifies an Request Flag 1 Interrupt requested 2 transfer end interrupt ATC 2 Transfer End Interrupt 0 Interrupt undetected This register allows only byte Detect Flag 1 Interrupt detected accesses Use the MOVB in struction to set the data 6 5 2 AT2ICH AT2 IE x OOFCAD Beal RUE s ATC 2 Transfer End 0 0 0 0 0 0 0 1 Interrupt Control Register 8 bit access register ATC 2 Transfer End Interrupt 0 Disable Enable Flag 1 Enable AT21CH enables 2 transfer end interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same leve
82. An oscillation circuit connected to an external crystal supplies the clock to all blocks in the CPU Program Counter The program counter generates addresses for instruction queues Normally it incre ments based on the sequencer indications but for branch instructions and interrupt acceptance it sets the branch address and the ALU operation result Instruction Queue The instruction queue contains up to four bytes of prefetched instructions Instruction Decoder The instruction decoder decodes the contents of instruction queue and generates con trol signals needed for the instruction execution The instruction executes by control ling each block in the CPU Quick Decoder The quick decoder decodes the 2 byte or larger instruction at faster speed Instruction Execution The instruction execution controller controls the CPU operations based on results Controller from the instruction decoder and interrupt requests ALU The ALU calculates the operand addresses for arithmetic operations logic operations shift operations register relative indirect addressing indexed addressing register in direct addressing Multiplier The multiplier calculates 16 bits x 16 bits 32 bits Internal ROM and RAM These memory allocate the program data and stack areas Address Registers An The address registers An store the addresses in memory accessed during data trans fer They also store the base add
83. External Expansion Address data multiplex port function Address data separate port function Memory Interface DRAM Interface 8 bit 16 bit width Burst ROM Interface I O Port Maximum of 82 I O ports in single chip mode Maximum of 47 I O ports in address data multiplex mode Maximum of 40 I O ports in address data separate mode Package 100 pin LQFP 10 MN102H55D 55G F55G 1 3 Address Registers AO Al A2 A3 Multiplier Program Counter Block Diagram Data Registers DO D1 D2 Multiplication Division Register Chapter 1 General Description T2 Clock Source D3 MDR Instruction Execution Controller Instruction Decoder Incrementer X Z Instruction Interrupt Queue Controller Y 1 Program Address Operand Address Interrupt Bus Bus Controller A ROM Bus RAM Bus Peripheral Execution Bus P Y External Interface Internal ROM Internal RAM Internal Peripheral i i External Extension Bus Figure 1 3 1 Block Diagram BR BG Functions MN102H55D 55G F55G 11 Chapter 1 General Description Table 1 3 1 Block Functions Blcok Function Clock Generator
84. Figure 11 1 11 Data Transfer Signal Timing Data Address Data Address Address Data Shared With Wait 1 5 or More ALE late long mode AD long mode Write MN102H55D 55G F55G 335 Chapter 11 Appendix BRACK y BREQ BREQS Figure 11 1 12 Bus Authority Request Signal Timing NMI Z IRQ4 IRQ0 tiRaw Figure 11 1 13 Interrupt Signal Timing SBT4 SBTO SBO4 SBOO lt lt trxpp tTXDH 1 Figure 11 1 14 Serial Interface Signal Timing 1 Synchronous Serial Transmission Transfer in Progress SBT4 SBTO SBO4 SBOO q lt q lt M tTXDH 2 Figure 11 1 15 Serial Interface Signal Timing 2 Synchronous Serial Transmission Transfer End Timing at SBT Input 336 MN102H55D 55G F55G Chapter 11 Appendix SBT4 SBTO SBO4 SBOO Figure 11 1 16 Serial Interface Signal Timing 3 Synchronous Serial Transmission Transfer End Timing at SBT Output TMnIB n 13 15 TMnIC 8 12 5 4 5 0 pe tscH 5 4 5 0 lt P tRxps Figure 11 1 17 Serial Interface Signal Timing 4 Synchronous Serial Reception Transfer End Timing at SBT Input TMnIO 0 4 7 TMnIOA 8 12 N TMnIOB nz8 12 i TMnIA 13 15 lt trccLkL PS Figure 11 1 18 Timer Counter Signal Timing MN102H55D 55G F55G 337 Ch
85. MN102H55D 55G F55G 201 Chapter 5 Serial Interface 202 MN102H55D 55G F55G Port 7 Setting 1 Set P7LMD 2 0 flags and P7LMD 4 3 flags of the port 7 mode register P7LMD to 001 and 01 respectively This setting allows to input SBTO and SBIO of serial interface P7LMD x 00FFFA 7 6 5 4 3 2 1 0 P7 P7 7 7 7 7 7 7 LMD7 LMD6 LMDS ILMD4 LMD3 ILMD2 LMD 0 0 1 0 0 1 Serial Interface 0 Setting 1 Set the operating conditions in the serial 0 control register SCOCTR Select SBTO pin as the clock source 8 bit data transfer odd parity and reception enable Set the reserved flags of the serial 0 control register SCOCTR to 0 SCOCTR x 00FD80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCO SCO SCO reser reser SCO reser SCO SCO SCO SCO SCO SCO SCO TEN REN BRE ved ved E OD ved LN PTY2 PTYI PTYO SB 51 50 0 1 0 0 0 0 0 1 1 1 1 0 0 0 2 Enable interrupts after clearing all existing interrupt requests At the same time set the interrupt level Thereafter a serial reception end interrupt occurs when the data transfer ends SCORICL x 00FC92 _ cn Scor IR ID 0 0 SCOR IE Thereafter an interrupt occurs when the serial data is received 5 2 3 Serial Cl
86. MN102H55D 55G F55G 363 Chapter 11 Appendix 7 6 5 4 3 2 0 IR ID R R R R W R R R 0 0 0 0 0 0 0 on o 0 1 4 Timer 11 Underflow Interrupt Request Flag 0 Timer 11 Underflow Interrupt Detect Flag 7 6 5 4 3 2 0 A TMIIU IE R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 11 Underflow Interrupt Enable Flag 364 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected 0 Disable 1 Enable TM11UICL x O0FC76 Timer 11 Underflow Interrupt Control Register 8 bit access register TM11UICL requests and veri fies a timer 11 interrupt This register allows only byte accesses Use the MOVB in struction to set the data TM11UICH x 00FC77 Timer 11 Underflow Interrupt Control Register 8 bit access register TM11UICH enables a timer 11 interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the IQ4LV 2 0 bits of the IQ4ICH register 7 6 5 4 3 2 0 KI IR ID R R R W R R 0 0 0 0 0 0 0 0 o 0 1 4 External Key Interrupt 0 No interrupt requested Request Flag 1 Interrupt requested 0 External Key Interrupt 0 No interrupt detecte
87. Output Output System Clock Output Internal System Clock Output General purpose Port BO This pin provides the system clock After reset release the pin outputs BOSC When the high speed oscillation pin is operating at 34 MHz the pin outputs the clock of 34 MHz Pin 18 can output BIBT1 or BIBT2 signal of the internal system clock by setting the PBMD register These signals are inverted signals If pin 18 is not used as the BOSC pin it can be used as a general purpose input output port The PBMD register switches the function The input output direction is con trolled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports 25 MODE Input Mode Setup Input This pin sets either processor mode or single chip mode memory expansion mode Pulling the pin low sets the processor mode In processor mode Internal ROM be comes the external memory area and the chip executes the instruction from x 080000 in memory connected exter nally Pulling the pin high sets the single chip mode memory expansion mode The chip executes the instruc tion from x 080000 of Internal ROM In memory expansion mode the port mode register is set to address output and data output by instruction Do not change the mode setting in this pin during operation When the setting is changed proper operation cannot be guaranteed Refer to 2 1 Summary of Bus Interface 24
88. Pin Number Pin Name y o Function Description WAIT P60 SBT2 Input yo y o Bus Cycle Wait Input General purpose Port 60 Serial Interface 2 Clock Input Output This pin extends or shortens the cycle of accessing to the external memory based on the signal inputted to this pin when the external memory wait is set to the handshake mode in processor mode or memory expansion mode Pull ing this pin low ends access to the external memory Refer to Figure 1 4 13 Table 2 1 3 to Table 2 1 6 This pin can be used as a general purpose input output port if it is not used as WAIT in single chip mode processor mode or memory expansion mode The input output direc tion is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports This pin can be used as a synchronous transfer clock signal input output pin for serial interface 2 if it is not used as WAIT in single chip mode processor mode or memory ex pansion mode Because pin 13 has the same function ei ther pin 13 or pin 1 must be selected Refer to Chapter 5 Serial Interface 13 AO P20 SBT2 Output Address Output General purpose Port 20 Serial Interface 2 Clock Input Output This pin outputs the address of the external memory in pro cessor mode or memory expansion mode Connect this pin to address pin of the external memory or address decode circuit
89. Pin State Undefined All ports are input et External oscillation Wait for Oscillation A 4 A 4 clock cycle or more Stability A Hereafter execute programs Power Self excited Oscillation Set RST pin Set RST pin Fetch the instruction at x 80000 of Internal ROM supplying clock from external tart external oscillation starts device to the CPU to low level to high level Memory Expansion Mode li i Pin State Undefined All ports are input gt lt External oscillation Wait for Oscillation A 4 4 clock cycle or more Stability 4 Hereafter execute Power Self excited Oscillation Set RST pin Set RST pin Fetch the Switch PO P5 programs Stat to low level to high level instruction to address pins The external oscillation starts atx 80000 datapinsor supplying clock from external of Internal control signal pins device to the CPU as needed using program Processor Mode Pin Stat Valid address pins data pins and control signal pins Note The ports except address pins data pins and Other ports are undefined control signal pins are input Pe 4 External oscillation Wait for Oscillation A 4 clock cycle or more Stability 4 Hereafter execute NM programs Power Self excited Oscillation Set RST pin Set RST pin Fetch the tart i instruction The external oscillation starts Iouis to high level at x 80000 supplying clock from exter
90. R W R W R W R W R W R W R W R W System Control Register 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 61 access register 7 0 Programming Disable of 7D Enable all register programming oe SYSCTL disables programming Registers Related to System Others Disable programming for the of registers related to system Operations following registers control CPU Control CPUM EFCR Address Break ADBO ADB1 Programming registers related to ADBCTL system control is disabled by Memory Control EXWMD writing the value except x 7D to 1 the SYSCTL register This vents programming these regis DRAMMD1 ters when iis CPU runs errone ous operations DRAMMD2 Ports POMD P1LMD P1HMD P1MD P3LMD P3HMD PALMD P4HMD PSLMD P5HMD P6MD P7LMD P7HMD P8LMD P8MMD P8HMD P9LMD P9HMD PAMD PBMD MN102H55D 55G F55G 395 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADBO ADBO ADBO ADB0 ADBO ADB0 ADB0 ADB0O ADB0 ADBO0 ADBO ADBO ADB0 ADBO ADBO0 ADBO 15 14 AI3 12 AIO A9 A8 7 AS A4 A3 A2 Al AO R W R W R W R W R W R W
91. The width is calcu lated by the instruction TM8CB TM8CA PO D A Converter P6 TMBIOA pin Ei A D Converter TM8IOB P1 nterrupt P7 P2 8 61 Timers Serial VF P3 E 16 bit Timers ATC P9 P4 8 bit PWM ETC PA P5 Pulse Width Counter ROM RAM PB Timer 8 Timer 0 gt TM8BC underflow up in gt TM8CA pin ms 5 5 Y x 1 TM8CB Capture interrupt Figure 4 4 11 Two phase Capture Input Block Diagram 16 bit Timer 154 MN102H55D 55G F55G Timer 0 Setting 1 Verify that timer 0 counting is stopped with the timer 0 mode register TMOMD TMOMD x 00FE20 7 6 5 4 3 2 1 0 TMO TMO TMO EN LD 7 7 SI SO 0 2 Set the timer 0 divisor In this example since timer 0 divides BOSC 2 by 2 set the timer 0 base register TMOBR tol The valid range for TMOBR 15 0 to 255 TMOBR 00 10 TMO TMO TMO TMO TMO TMO TMO BR7 BR6 BRS 4 BR3 BR2 BRO 0 0 0 0 O 1 3 Load TM0BR value to the timer 0 binary counter TM0BC At the same time select BOSC 2 as the clock source TM0MD x 00FE20
92. Y Y Y Y Y Up Counting Down Counting t TM8IOB 1 1 MN102H55D 55G F55G 163 Chapter 4 Timers 4 4 8 One shot Pulse Using 16 bit Timer Timer 8 is used to generate a one shot pulse The pulse width is 2 cycles of BOSC 2 PO CORE D A Converter P6 TMa 5 a Interrupt A D Converter P7 P2 8 bit Timers Serial I F P8 16 bit Timers 9 P4 8 bit PWM ETC PA P5 Pulse Width Counter ROM RAM PB Timer 8 BOSC 2 gt TM8BC TM8CA 8 N R TMS8IOB pin gt 5 s Q gt TMBIOA TM8CB TM8CBX Figure 4 4 21 One shot Pulse Output Block Diagram 16 bit Timer 164 MN102H55D 55G F55G Timer 8 Setting 1 Set the operating mode in the timer 8 mode register TM8MD Set counting stop Select up counting Select BOSC 2 as the clock source Set the TM8BC count range to 0 to TM8CA Select one shot operation as the counter operating mode Set the count start external trigger to start counting on the falling edge of TM8IOB pin TM8MD x 00FE80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 TM8 8 8 TM8 TM8 8 TM8 TM8 8 8 TM8 TM8 T
93. o es om cte BOSC BIBT2 BIBT1 Chip Operation DMAREQn Chapter 7 ATC ETC ETC bus acquisition interval RE output CS output Address output External memory data output x e lt lt gt As 28 Cw DMAACKn output External device WE Note the number of external memory waits 1 the number of data transfer bytes 2 Figure 7 4 3 ETC External Memory External Device Burst Transfer Timing MN102H55D 55G F55G 250 Chapter 7 ATC ETC 7 4 2 Transfer from External Device to External Memory Burst Transfer DMAREQ0 input from bus master is an activation factor Each 16 bits of 4 byte data are transferred from the external device to the external memory gt WEL P62 PO CORE D A Conversion Pe WER P63 P1 Interrupt A D Conversion P7 7 0 P2 8 bit Timers Serial P8 A8 Ll bit Ti P92 A15 A8 P3 16 bit Timers ATC P9 23 16 P4 8 bit PWM ETC PA 50 P50 5 Pulse Width Counter ROM RAM PB Figure 7 4 4 ETC External Device External Memory Burst Transfer Block Diagram External Memory External Device
94. 07 Description for details 8 yo Timer 8B Input Output This pin can be used as a timer 8 input capture B input pin or a timer 8 output compare B output pin if it is not used as a data input output pin or an address data input output pin in single chip mode processor mode or memory expan sion mode Refer to Chapter 4 Timers 94 D9 yo Data I O Refer to Pin 93 D8 AD8 Description for details AD9 yo Address Data I O P11 General purpose Port 11 Refer to Pins 84 91 00 07 Description for details 8 Input Timer 8 Input This pin can be used as a timer 8 counter clear pin if it is not used as a data input output pin or an address data input output pin in single chip mode processor mode or memory expansion mode Refer to Chapter 4 Timers MN102H55D 55G F55G 35 Chapter 1 General Description Table 1 4 1 List of Pin Functions 15 26 Pin Number Pin Name yo Function Description 95 D10 Data I O Refer to Pin 93 D8 AD8 Description for details AD10 Address Data I O P12 y o General purpose Port 12 Refer to Pins 84 91 7 Description for details TM111OA y o Timer 11A Input Output This pin can be used as a timer 11 input capture A input pin or a timer 11 output compare A output pin if it is not used as a data input output pin or an address data input output pin in single chip mode processor mode or memory expan sion mode Refer to Chap
95. 1 Chapter 11 Appendix 2 W 1 W the number of waits 1 5 2 2 5 7 tcvc tcvc tcvc tcvc gt lt gt lt gt lt s em JC T i 015 00 RE Late 0 5 short 0 mode li lt Write gt 015 000 LLL Data 0 WEH WEL Late 1 short 0 mode Figure 11 1 5 Data Transfer Signal Timing Address Data Separate With Wait 1 5 or More Read Write MN102H55D 55G F55G 329 Chapter 11 Appendix 2 W 1 W the number of waits 1 5 2 2 5 7 tcvc tcvc tcvc tcycxn tcvc gt lt gt lt gt lt gt lt BOSC RE Late 0 5 mode RE Late 1 mode Late 2 mode RE F su Late 3 mode RE Short 0 mode RE Short 0 5 mode Hd 2 RE Short 1 mode RE Short 1 5 mode al Pot pt LAT D15 D00 Figure 11 1 6 Data Transfer Signal Timing Address Data Separate With Wait 1 5 or More RE Late Short Mode 330 MN102H55D 55G F55G Chapter 11 Appendix N 2 W 1 W the number of waits 1 5 2 2 5 7 tcvc tcvc tcvc tcvc WEH WEL Short 0 5 mode WEH WEL Short 1 mode WEH WEL Short 1 5 mode D15 D00 Figure 11 1 7 Data Transfer Signal Timing Address Data Separate With Wait 1 5 or More WE Late Short Mode
96. 15 1 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 468 MN102H55D 55G F55G TM15CA x OOFED4 Timer 15 Capture Register A 16 bit access register TM15CA captures the contents of TM15BC on the rising of pin Chapter 11 Appendix A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ANCTR AN AN AN AN AN AN AN AN 1 NCH2 NCH1 NCHO 2 1 0 EN TC DEC MD MDO x OOFFOO R W R W R R W R W R W RW R W RW R R W R W A D Converter 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 or o o Control Register 16 bit access register 14 12 Channel Selection for 000 Convert ANO Multiple Channel Conversion 001 Convert from ANO to AN1 010 Convert from ANO to AN2 011 Convert from ANO to AN3 100 Convert from ANO to AN4 101 Convert from ANO to AN5 110 Convert from ANO to AN6 111 Convert from ANO to AN7 ANCTR sets the A D converter operating conditions 10 8 Channel Selection for 000 Co
97. 2 9 UD R LOAD 1 TM10IOA pin 1 UD Match Capture TM10CA Set by PSLMD 5 TM10IOB TM10CAX R Select the ERE Lo gt 4 or both edges 1 c Match capture TM10CB t gt gt TM1010 pin TM10IOA pin TM10CBX lq R Set by P9SLMD MD LD TGE TM10MD ONE Figure 4 3 14 Timer 10 Block Diagram TM111C pin Timer 0 underflow 9 Timer 4 underflow 5 CLR ASEL TM111OB 9 TM11BC gt aL BOSC 2 gt 5 TM111OA 1 Capture TM11CA Set by P1LMD SR TM111OB pin _ IMIIGAR 5 Match Capture TM11CB 11 TM111OA pin gt TM11CBX i Set by MD LD TM11MD C ou Figure 4 3 15 Timer 11 Block Diagram 121 pin Timer 0 underflow gt _ 7 5 Timer 4 underflow gt ASEL CLK ER TM12IOB pin 9 EN 2 5 TM12BC EN BOSC 2 UID R Control LOAD 4 TM121OA 1 UD Match R Capture TM12CA Q Set by P1HMD R 12 gt _ IMISUAK E 1 5 Match Capture TM12CB T Q gt 12 TM121OA pin
98. 23 24 OSCO Input Output High speed Oscillator Input High speed Oscillator Output For a self excited oscillator configuration connect crystal or ceramic oscillator across these two pins They have a built in feedback resistor between them For stability in sert capacitor of 20 pF to 33 pF between the OSCI pin or the OSCO pin and the Vss pin For the exact capacitance consult the oscillator manufacturer For an external oscillator configuration connect the OSCI pin to an oscillator with an amplitude of 4 MHz to 34 MHz and the width between and Vss Leave the OSCO pin open Refer to Figure 1 4 10 Connecting the OSCO pin with the external circuit directly is not allowed when the oscillator clock is taken from the chip Select the BOSC pin for a synchronous signal 20 21 XI XO PB1 Input Output Low speed Oscillator Input Low speed Oscillator Output General purpose port B1 pin For a self excited oscillator configuration connect crystal or ceramic oscillator across these two pins They have a built in feedback resistor between them For stability insert ca pacitor of 100 pF to 200 pF between the XI pin or the XO pin and the Vss pin For the exact capacitance consult the os cillator manufacturer For an external oscillator configuration connect the XI pin to an oscillator with an amplitude of 32 kHz to 166 kHz and the width between Vpp and Vs
99. 6 4 Parity Bit Selection 000 None 100 0 output low 101 1 output high 110 Even 1s are even 111 Odd 1s are odd Others Reserved 3 Stop Bit Selection 0 1 bit 1 2 bit asynchronous mode SBOS Output Hold Time 0 More than BOSC cycles clock synchronous mode 1 More than timer 4 underflow cycles 1 0 Serial 3 Clock Source Asynchronous mode mode Selection 01 Timer 4 underflow 1 8 11 Timer 5 underflow 1 8 Clock synchronous mode 00 SBT3 pin 01 Timer 4 underflow 1 8 10 Timer 5 underflow 1 2 11 Timer 5 underflow 1 8 Chapter 11 Appendix SCS3CTR x 0OFD98 Serial 3 Control Register 16 bit access register SC3CTR sets serial 3 operating conditions The SBOS output hold time is extended only when SBT3 is selected as serial 3 clock source MN102H55D 55G F55G 425 Chapter 11 Appendix 7 6 5 4 3 2 1 0 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 7 TRB6 5 TRB4 TRB3 TRB2 TRBI TRBO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Serial Transmit Receive Data 426 MN102H55D 55G F55G SC3TRB x 00FD9A Serial 3 Transmit Receive Buffer 8 bit access register SC3TRB writes the serial 3 transmit data and reads the se rial 3 receive data Transmission starts by writing the data into this register The data is received by reading this register
100. 61 000658 566 ea ee 555090090 5555 2S 253 500002 lt lt lt lt REPRE ito N 9 cQ 6 gt N O n ot GEHE e 8588 588588858805 8 68 5 PAO IRQO 76 50 w P82 TMOIO SBT3 SCL3 SBI2 PA1 IRQ1 77 49 w P81 DAC1 PA2 RQ2 78 48 P80 DACO PA3 IRQ3 79 47 w A23 P47 AN7 WDOUT PA4 IRQ4 TM15IB 80 46 22 46 6 5 ADSEP 81 45 21 45 5 7 RST 82 44 20 44 4 83 43 4 VREF MN102H55D pe Do AD2 86 MN1 02H55G 40 A17 P41 AD3 J 87 39 4 16 40 AD4 lt 88 MN102HF55G a A15 P37 AD5 89 37 A14 P36 6 AD6 90 TOP VIEW 36 4 A13 P35 AD7 91 35 w A12 P34 4 Vss 92 34 42 Ey P10 TM8IOB 5 93 33 4 A11 P33 P11 TM8IC 94 32 A10 P32 P12 TM111IOA 95 31 A9 P31 P13 TM11IOB 96 30 A8 P30 KIO 14 11 97 29 P27 28 w P26 27 4 P25 P15 TM121OA 4 gt 98 P16 TM12IOB lt 99 P17 TM12IC 100 26 lt gt 24 15 C A 0 Ww Oo Q o AS cod N lt
101. 9 Output P86 SBO4 Output P87 P87 P80 SCL3 SDA4 Output P87 SBI3 P8LMD 4 0 SBO3 P8MMD 7 0 Register P8HMD 3 0 SDA3 SBT4 P8DIR7 0 lt Register SCL4 TMOIO TM410 TM710 9 TMSIOB TM9IC SBI4 Input Output Control P82 P87 SBO4 Selector SBI2 SBI3 SBI4 SBO2 SBO3 SBO4 SDA4 SBT2 SBT3 SBT4 SCL3 SCL4 SDA3 SDA4 Input Output Control P82 P87 DACO DAC1 Output Control P80 P81 80 gt DAC1 P81 Analog Switch P8IN 7 0 Port Input TMOIO TM4IO TM7IO 9 TMSIOB TM9IC Input P82 P87 SBI2 SBI3 SBI4 SBT2 SBT3 SBT4 SCL3 SCL4 SDA3 SDA4 Input P82 P84 P87 Note The set value of the P8DIR register is valid only when the port function is selected by the P8LMD register the P8HMD register The input or output direction of D A function timer function and serial function is determined automatically by setting the P8LMD register or the P8HMD register 272 MN102H55D 55G F55G Table 8 1 2 Port Block Diagram 10 12 Chapter 8 Ports Port Pin Name Block Diagram Port 9 P97 to P90 TM8IOA TMIOIOA P9PLU 7 0 lt R Register Y TM10IOB TMIOIC P9OUT 7 0 lt Register gt 2 Output P90 DMAREQI BIBT1 Output P90 See eS 1 Output P91 Selector DMAREQO BIBT2 Output P91 gt Output P91 1010 Output P92 D
102. ANCTR and the A D conversion data buffers ANnBUF corre sponded to AN7 pin to ANO pin Chapter 6 Analog Interface ANnBUF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ANn ANn AMn BUF3 BUFI Reset 0 0 0 0 0 0 UndefinedUndefinedUndefinedUndefinedUndefinedUndefined Undefined Undefined Undefined Undefined At 8 bit resolution ANnBUF 7 0 bits hold the data and the ANnBUF 9 8 bits become 0 At 10 bit resolution the ANnBUFT 9 0 bits hold the data At reset the data is undefined ANnBUF MN102H55D 55G F55G 219 Chapter 6 Analog Interface ANCTR x 00FF00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AN AN AN AN AN AN AN AN AN AN AN AN AN NCH2INCH1 NCHO 1 2 1 1 1 0 EN DEC CK1 CKO MD1 MDO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Operating Mode Selection Single channel single conversion Multiple channels single conversion Single channel continuous conversion Multiple channels continous conversion Clock Source Selection BOSC 2 BOSC 4 BOSC 8 BOSC 16 ANDEC A D Converter Resolution 0 8 bit 1 10 bit ANTC Conversion Start at Timer 3 Underflow 0 Disable 1 Enable ANEN Conversi
103. Burst ROM Connection 8 bit Bus Width 4 3 3 3 Waits Lower 2 bits of Address EXWMD MEMMDI MEMMD2 POMD PILMD P2MD P3HMD P4LMD PSLMD PSHMD P50 P56 MICOM MN102HF55G CSO A18 0 D7 0 BSTRE Burst ROM 256 K 8bit cs A18 0 D7 0 Figure 2 1 5 Burst ROM Connection Example 8 bit Bus Width 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EW EW EW EW 03 02 01 00 1 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EB EB BRS BRS BRC 01 00 1 0 0 0 1 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BST BST BST 2 1 0 0 0 1 7 6 5 4 3 2 1 0 PO PO MD1 0 1 7 6 2 4 3 2 1 0 LMDI1 LMDO 0 1 7 6 5 4 3 2 1 0 2 MDO 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 P3 P3 P3LMD P3 P3 P3 P3 P3 P3 HMD7 HMD6 HMD5 HMD4 HMD3 HMD2 HMDI HMDO LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMDI LMDO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 P4 4 4 LMD2 LMDI LMD0 1 1 1 7 6 5 4 3 2 1 0 PS PS LMDI1 LMDO 0 1 7 6 5 4 3 2 1 0 PS PS PS HMD4 HMD3 HMD2 0 1 1 MN102HF55G H55G H55D Chapter 2 Bus Interface 65 Chapter 2 Bus Interface Example of DRAM Connection 8 bit Bus Width 2 Wait MN102HF55G DRAM MN41V4800 512 K 8bit Row 10 C
104. P1HMD sets a signal output to the port 1 When P1 is used as a port or an input output pin of each periph eral function always set P1LMD 1 0 to 00 7 6 5 4 3 2 1 0 2 2 2 2 2 2 MD7 MDs MD2 R W R R W R W R W R W R R W Processor address data separate mode 0 0 0 0 0 0 1 Other modes 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 0 1 7 P24 Input Output Signal Switch 0 Port 3 2 P22 Input Output Signal Switch P21 Input Output Signal Switch P20 Input Output Signal Switch P2 Input Output Signal Switch 1 input cannot use P56 as TM151lA input 0 Port 1 SBO2 output 0 Port 1 SBI2 input cannot use P82 as SBI2 input 00 Port 01 SBT2 input cannot use P60 as SBT2 input 10 SBT2 half duplex output 11 SBT2 output 0 Port each Function 1 Address Chapter 11 Appendix P2MD x OOFFF1 Port 2 Mode Register 8 bit access register P2MD sets a signal output to the port 2 P23 P25 P26 and P27 can be used as ports if P2MDO is set to 0 When P2 is uesed as a port or an input output pin of each pe ripheral function 2 is al Ways set to 0 MN102H55D 55G F55G 501 Chapter 11 Appendix 7 6 5 4 3 2 1 0 P3 P3 P3 LMD7 LMD6 LMD5 LMD2 LMDI LMDO R W R W R W R W R W R W R W R W Pr
105. Pse EM T uu s lt MOM 10 Aan D 2 2100 N Lu z Q lt Ju x nmam lt a lt a lt o zz lt o rz Z Z m m a B 8 5 T o tr z 2 S 5 2 x 9 z s T lt o o m 2 2 X a m 71 MN102HF55G H55G H55D The length of wait cycle can be set 0 5 cycle units Table 2 1 7 Address Data Separate Mode 16 bit Bus DRAM WEH and WEL Method Chapter 2 Bus Interface ewan ete as RR Ps 4 NS NS PM MET J ee 2 2 9 5 5 2 ee Se T pM EE S EE H t 4 F 4 F 4 H PS H 7 2 N A a Q rer la Iu v pe IA ree Sas ES 2 o eo gt AS A HS dr o 8 S 9119 k
106. R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 T8C 5 T8C AX14 T8C AX13 T8C AX12 T8C T8C AX10 T8C AX9 T8C AX8 T8C AX7 T8C AX6 T8C 5 T8C AX4 T8C AX3 T8C AX2 T8C T8C 456 MN102H55D 55G F55G TM8CA 84 8 Capture Register 16 bit access register TMB8CA sets the timer 8 count ing cycle The timer 8 binary counter counts the cycle of the TM8CA value 1 TM8CA changes PWM and gener ates a timer 8 capture A interrupt When capture is selected this reg ister is read only A timer 8 capture A interrupt is generated when cap ture occurs When compare is se lected set the PWM cycle When this register matches the timer 8 binary counter a timer 8 capture A interrupt occurs This register write only 16 bit data Use the MOV instruction to set the data TM8CAX x OOFE86 Timer 8 Compare Capture Register Set A 16 bit access register This register is valid only when the associated compare register is set to the double buffer mode The TM8CAX cannot read or write The contents of TM8CA are loaded to TM8CAX by write signal TM8CAX sets the PWM cycle When TM8B
107. Set PA4 pin to TMISIB pin input by writing 1 to bit 4 of the port A mode register PAMD The PA4 pin direction control becomes input automatically Setting the port A direction control register PADIR is invalid PAMD x 00FFDC 7 6 5 4 3 2 1 0 MD2 MDI MDO 3 Set TMISEN flag of the TM15MD register to 1 This starts the timer TM15MD x 00FEDO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 15 15 CLKI CLKO 1 0 1 Thereafter the TM15BC counter starts counting up on the rising edge 151 pin input The 15 counter value is loaded to the timer 15 capture register 15 on the rising edge of TMISIA pin When TMISIA pin rises clear 15 counter after BOSC 1 clock This operation allows to store the pulse width which is input from TM15IA pin to the TM15CA register MN102H55D 55G F55G 185 Chapter 4 Timers TM15BC 00 e 02 04 o5 07 00 o1 02 04 o5 o oo 01 TM15CA 00 07 06 me hhnnnnnnnnnnnnnnnnni Figure 4 8 2 16 bit Pulse Width Measure Counter Timing 186 MN102H55D 55G F55G Chapter 5 Serial Interface Chapter 5 Serial Interface 188 MN102H55D 55G F55G 5 1 5 1 1 Overview Serial Interf
108. TM12CBX R Set by P1HMD MD LD TM12MD fos Figure 4 3 16 Timer 12 Block Diagram 136 MN102H55D 55G F55G Chapter 4 Timers 4 4 16 bit Timer Setup Examples 4 4 1 Event Counter Using 16 bit Timer In this example timer 8 counts TM8IOB input cycles of more than BOSC 4 and generates an interrupt on the second and fifth cycles PO CORE D A Converter P6 pin gt P1 Interrupt A D Converter P7 P2 8 bit Timers Serial 8 16 bit Timers ATC 9 P4 8 bit PWM ETC PA P5 Pulse Width Counter ROM RAM PB Timer 8 5 2 1 TM8BG Capture A up y TM8CA 8 Control lt a on TM8CB Capture interrupt Figure 4 4 1 Event Counter Block Diagram MN102H55D 55G F55G 137 Chapter 4 Timers 1 Use the MOV instruction to set the data and only use 16 bit write operations The timer 8 binary counter TM8BC is stopped and TM8BC register and RS F F are initialized cleared to 0 1 If this setting is omitted the bi nary counter may not count the first cycle Do not change to any other operating modes 138 MN102H55D 55G F55G Timer 8 Setting 1 Set the operating mode in the time
109. Transfer Units 0 Byte 1 Word Definition A Add D DRAM PSRAM Operation for External Memory Space 3 DRAM PSRAM Operation for External Memory Space 2 DRAM PSRAM Operation for External Memory Space 1 DRAM PSRAM Operation for External Memory Space 0 Delete Change Page 5 DRAM Operation for External Memory Space 3 DRAM Operation for External Memory Space 2 DRAM Operation for External Memory Space 1 DRAM Operation for External Memory Space 0 15 DRAM Access Method Selection 0 2WE method 1 2CAS method MN102H55D 55G F55G User s Manual Record of Changes Ver 1 1 to Ver 2 0 Former Version New Version 10n 15 DRAM Access Method Selection 0 2WE method 1 Reserved Use only 2WE method in DRAM mode Do not use 2CAS method The RE short mode and the late mode do not affect the BSTRE pin connecting burst ROM 5 4 P7 P7 R R 0 1 5 0 Port 7 Input 6 4 P7 P7 R R 0 1 0 1 Port 7 Input Reading P76 pin identifys the status input NMI reserv reserv ed ed R R 0 1 4 2 P82 Input Output Signal Switch 000 Port 001 TMOIO port SBT3input 010 TMOIO output 011 SBT3 output 100 SBT3 half duplex output 101 SBT3 open drain
110. prevents the PWM loss This register writes only 16 bit data Use the MOV instruction to set the data Chapter 11 Appendix is 14 13 12 10 9 8 7 6 5 4 2 1 TM9CB TM9 TM9 TM9 TM9 TM9 TM9 TM9 TM9 TM9 TM9 TM9 TM9 TM9 TM9 TM9 TM9 x 00FE98 15 14 12 10 CB5 CB2 R W R W R W R W R W R W R W R W R W R W R W RAW R W R W R W R W Timer 9 Compare Capture Reaister on on on on 9 16 bit access register sets the timer 9 PWM duty changes PWM and gener ates a timer 9 capture B inter rupt When capture is selected this register is read only A timer 9 capture B interrupt is generated when capture occurs When compare is selected set the PWM duty When this register matches the timer 9 binary counter a timer 9 capture B in terrupt occurs This register write only 16 bit data Use the MOV instruction to set the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM9CBX 9 ToC TOC TOC TOC TOC TOC TOC TOC TIC BXI5 BX
111. 15 14 13 12 11 10 AX8 AX7 6 5 AX2 AXI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 462 MN102H55D 55G F55G TM11CA 4 11 Capture Register 16 bit access register TM11CA sets the timer 11 counting cycle The timer 11 binary counter counts the cycle of the TM11CA value 1 TM11CA changes PWM and gen erates a timer 11 capture A inter rupt When capture is selected this reg ister is read only A timer 11 cap ture A interrupt is generated when capture occurs When compare is selected set the PWM cycle When this register matches the timer 11 binary counter a timer 11 capture A interrupt occurs This register write only 16 bit data Use the MOV instruction to set the data TM11CAX x OOFEB6 Timer 11 Compare Capture Register Set A 16 bit access register This register is valid only when the associated compare register is set to the double buffer mode The TM11CAX cannot read or write The contents of TM11CA are loaded to TM11CAX by write signal TM11CAX sets the PWM cycle When TM11BC TM11CAX a timer 11 capture A interrupt oc curs The contents of TM11CA are loaded to TM11CAX by a timer 11 capture A interrupt and TM11CAX prevents the PWM loss This register writes only 16 bit data Use the MOV instruction to set the data Chapter 11 Appendix
112. 2 2 Use the address break function and Man Deue generate a NMI interrupt before Internal executing the first address of the subroutine 1 ROM 3 Jump from the NMI interrupt service routine to the subroutine 2 on the internal RAM using the JMP instruction MEE 4 Return to the main routine using the RTS instruction Subroutine 1 4 Internal RAM Subroutine 2 AREE Original Flow Alternative Flow using address break function Figure 9 1 3 Program Flow of Address Break Setup Address Break Setup 1 Set the first address of the subroutine to the address break 0 address pointer 2 Set 1 to ADBOON bit of the address break control register ADBCTL x 00FCDA 7 6 5 4 3 2 1 0 ADBI ADBO ADBI ADBO ON ON CK CK 0 0 0 0 0 1 0 0 Thereafter a NMI interrupt occurs when the CPU executes the address set in the step 1 NMI Interrupt Service Routine 3 Jump to the address x 80008 when the address break occurs The value of the IAGR register at this point is 8 Verify that the ADBOCK flag of the address break control register ADBCTL is during the interrupt service routine This deter mines whether a NMI interrupt occurs by the address break or other factors Clear the ADBOCK flag and the ADBICK flag to 0 by software after verification be cause both the ADBOCK flag and
113. 4 8 1 16 bit Pulse Width Measure Counter Timer 15 is used to measure the pulse width which is input from TMISIA pin The pulse width is stored in the TM15CA register Select TMISIB input as the clock source Set the pulse width input from pin to more than the width of the selected clock source Set the pulse width input from TMISIB pin to more than BOSC 2 PO CORE D A Converter P6 P1 Interrupt A D Converter P7 P2 8 bit Timers Serial 8 16 bit Timers ATC 9 P4 8 bit PWM ETC 15 P5 Width Counter ROM PB Figure 4 8 1 16 bit Pulse Width Measure Counter Block Diagram 1 Set the timer 15 mode register TMI5MD Select TM15IB pin input as the clock source Set counting stop TM15MD x 00FEDO 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 15 15 15 CLK1 CLKO 0 0 1 2 Set TMISIA and TMISIB pin By writing x 100 to PSHMD 4 2 flags of the port 5 mode register H PSHMD set P56 pin to TMISIA pin input The P56 direction control becomes input automatically Setting the port 5 direction control register PSDIR is invalid P5HMD 00 9 7 6 5 4 3 2 1 0 5 5 P 5 PS HMDAHMD3HMD2HMD HMD0 Chapter 4 Timers
114. 400 14 91 GINS HAL VOSLAL 003400 X Ne LAWL Odell VOCAL XV ZINL X892LN L 003400 X 5 1 1083500 980LA L XVOOLWL 890LAL X890LIA L p m s 0 O86lA L VO6lN L XVO6NW1 996 1 X896IA L ZOW6WL 064300 XVO8N1 Xg 8NL O 083400 X 0 3400 X SJeull 19 8 O GINE LLL 023400 X O O 8 O O HAL SOPLAL 019400 OgrLAL 003300 q oz 1 4 MN102H55D 55G F55G Chapter 11 Appendix Pin Name Input Level 11 2 3 List of Pin Functions Output Level Schumitt Pull up EO External Oscillation RESET Note 3 STOP HALT 1 P60 WAIT TIL 2 P61 RE L 3 P62 WEL TTL P63 WEH L CMOS CMOS CMOS CMOS Yes Programmab iz i Z Hi Z Hi Z Hi i 7 iZ Hi Z Hi Z Hi Z at RE Hi Z at RE Hi Z at WEL Hi Z at WEL Hi Z Hi Z Hi Z at WEH Hi Z at WEH 4 5 50 80 TTL 6 P51 C
115. 8 bit bus width 0 0 0 0 0 Other modes 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6 5 P12 Input Output Signal Switch 4 P11 Input Output Signal Switch 32 P10 Input Output Signal Switch 10 P1 Input Output Signal Switch 00 Port 01 TM111OA input 10 TM111OA output 0 Port 1 Reserved 00 Port 01 TM8IOB input 10 TM8IOB output 00 Port each funtion 01 Data output 10 Address data shared mode Chapter 11 Appendix P1LMD x O0FFF2 Port 1 Mode Register L 8 bit access register P1LMD sets a signal output to the port 1 When P1 is used as a port or an input output pin of each periph eral function always set P1LMD 1 0 to 00 MN102H55D 55G F55G 499 Chapter 11 Appendix IHMD7 HMD6 HMD5 HMD4 HMD3 HMD2 HMD 1 HMDO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 P17 Input Output Signal Switch 6 5 P16 Input Output Signal Switch 43 P15 Input Output Signal Switch 2 P14 Input Output Signal Switch 1 0 P13 Input Output Signal Switch 500 MN102H55D 55G F55G 0 Port 1 TM12IC input 00 Port 01 TM121OB input 10 TM121OB output 00 Port 01 TM121OA input 10 TM121OA output 0 Port 1 TM111C input 00 Port 01 TM111OB input 10 TM111OB output P1HMD x OOFFF3 Port 1 Mode Register H 8 bit access register
116. Alwa 1 01 Burst transfer ranster mode 1 valid only in 10 Two bytes words transfer Nis E 11 Reserved becomes 0 and the LSB of the Explanation address in the second word 12 Transfer Units 0 Byte forcibly becomes 1 1 Word Selecting word as the unit is not Destination Bus Width 0 16 bit allowed when 8 Bit bus widths Bit Number 1 8 bit allowed in the external memory space Flag Description Destination Pointer 0 Fixed Selecting 8 bit desitination bus Increment 1 Increment width or 8 bit source bus width is allowed only when 8 bit bus 9 Source Bus Width 0 16 bit width is selected in the external 1 8 bit memory space 8 Source Pointer Increment 0 Fixed When destination poet nee ment or source pointer incre 1 Increment ment is selected the pointer in crements by 1 in byte access 3 0 Activation Factor Setup 0000 Software Initialization and by 2 in word access 0001 DMAREQ1 pin input 0010 External interrupt 2 The 3 bits are cleared 0011 External interrupt 3 to 0 by the ATC3 transfer end 0100 Timer 2 underflow interrupt interrupt 0101 Timer 6 underflow interrupt 0110 Timer 8 capture B interrupt 0111 Timer 10 underflow interrupt 1000 Timer 11 capture A interrupt 1001 Timer 12 capture B interrupt 1010 Serial 2 transmission end interrupt 1011 Serial 2 reception end interrupt 1100 Serial 3 transmission end interrupt 1101 Serial 3 reception end interrupt 1110 A D
117. BUF6 DAO 5 DAO BUF4 DAO BUF3 DAO BUF2 DAO BUFI DAO BUFO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAI ON R W 0 1 DA1 Conversion Start 0 Disable 1 Enable DAI BUF7 DAI BUF6 DAI 5 DAI BUF4 DAI BUF3 DAI BUF2 DAI BUFI DAI BUFO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 474 MN102H55D 55G F55G DAOCTR 00 40 DAO Converter Control Register 8 bit access register DAOCTR controls DAO conver sion DAOBUF 41 DAO Conversion Data Buffer 8 bit access register 16 bit access is possible from even address DAO conversion data DA1CTR x OOFF42 DA1 Converter Control Register 8 bit access register DA1CTR controls DA1 conver sion DA1BUF x OOFF43 DA1 Conversion Data Buffer 8 bit access register 16 bit access is possible from even address DA1 conversion data Chapter 11 Appendix 15 14 13 12 n 10 9 8 7 6 5 4 3 2 1 0 EXWMD EW Ew EW EW EW Ew Ew Ew Ew Ew EW Ew Ew Ew EW 33 32 31 23 22
118. Buunp sseooe 119 9 gAOIN 9 999 0 8 Chapter 11 Appendix eues 93197958 9931798 515798 8 8 0 00 919298 951205 413208 O 91998 991695 915895 O O 060400 X 919098 951005 18005 YLOLOS 891105 915108 6 080400 YLOLLA 1995113 1150114 H1SQLI3 080400 X Y19013 1N9013 085013 5013 150013 150014 0 00 YLOELV LNOELV OUSELY HOUSELV LSCELY LSAELY 0 0400 X YLozLy 961 Ouseclv HOUSZLYV LSAc LV 15021 LNOLLW OUSLY HOUSI LV 150 HLSALLY YLOOLY LNOOLV OUSOLY HOUSOLYV 15001 H1SQ01V 000500 x Wa skS 108AS Hogayv 1180Y HIaav 6 009300X SsJejsibou 00002 1dnueju 94143A HIOA3M 9340M 0g9400 X 791798 5 O 8 O 7010013 H9I0913 1211214 HOILOLA JOI01V HOIOLV rO H ILLY 6 6 TOIELY O HOIELV 0 gt 00 101005 HOILOOS O 1018028 HOIH09S iO 1919195
119. Chapter 5 Serial Interface Synchronous Serial Timing Charts 8 bit charater length parity Transmission SBO bO b1 b2 b3 b4 b5 b6 b7 PTY SBT Data write TXBUSY Transmission end interrupt Figure 5 1 7 Synchronous Serial Timing Transmission Reception SBI bO b1 b2 b3 b4 65 66 b7 PTY SBT 2 Reception end interrupt High when data is received Data read Figure 5 1 8 Synchronous Serial Timing Reception 196 MN102H55D 55G F55G Chapter 5 Serial Interface 5 2 Serial Interface Setup Examples 5 2 1 Serial Transmission in Asynchronous Mode This section describes the example of serial interface 3 transmission in asynchronous mode with the following settings 1 Baud rate 19200 bps set transmit clock by timer 5 M Use a 8 bit timer to set the trans 8 bit data transmission mit clock two stop bits See 5 2 3 Serial Clock Opera odd parity tion Example The next data is transmitted when a transmission end interrupt occurs PO CORE D A Converter P6 P1 Interrupt A D Converter P7 P2 8 bit _ Serial F_f Ps H gt pin P3 16 bit Timer ATC Pe P
120. Dm Dn5Dm 32 bit sign extended word data 7 24 bit sign extended word data 8 24 bit zero extended word data 9 24 bit sign extended byte data 10 24 bit zero extended byte data 11 Addition without changing flag 13 14 32 16 16 16x16 32 signed 16x16 32 unsigned 16 unsigned F3 60 Dn lt lt 2 Dm Quick decoder ON This setting cannot be made in this series MN102H55D 55G F55G 539 Chapter 11 Appendix Instruction Mnemonic CMP Dn Dm Operation Dm Dn PSW Cycle F3 90 Dn lt lt 2 Dm Machine Code CMP Dm An An Dm PSW F2 20 Dm lt lt 2 An CMP An Dm Dm An PSW F2 E0 An lt lt 2 Dm CMP An Am Am An PSW F2 60 An lt lt 2 Am imm8 Dn Dn imm8 PSW D8 Dn imm8 CMP imm16 Dn Dn imm16 PSW F7 48 Dn imm16 l imm16 h CMP imm24 Dn Dn imm24 PSW F4 78 Dn imm24 l imm24 m imm24 h CMP imm16 An An imm16 PSW EC An imm16 l imm16 h CMP imm24 An An imm24 PSW F4 7C An imm24 l imm24 m imm24 h AND Dn Dm Dm amp x FF0000 Dn Dm F3 00 Dn lt lt 2 Dm 715 AND imm8 Dn Dn amp x FF0000 imm8 Dn F5 00 Dn imm8 amp 215 AND imm16 Dn Dn amp x FF0000 imm16 Dn F7 00 Dn imm16 l imm16 h 715 AND imm16 PSW PSW amp imm16 gt PSW F7 10 imm16 l imm16 h 715 Dn Dm Dm Dn amp x 00FFFF gt Dm
121. In this example 2 word data is transferred so that the value 1 subtracting 2 by 1 is set to the ETCO transfer word count register ETOCNT ETOCNT x 00FD42 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETO ETO ETO CNT11 CNT10 CNT9 CNT8 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNTO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 Set the ETCO control register ETOCTR Select burst transfer mode Select one byte unit and the destination pointer to increment by 1 Select the transfer direc tion is from external device to external memory Set the transfer start busy flag to disable ETOCTR x 00FD40 15 14 13 12 11 10 9 8 7 6 2 4 3 2 1 0 ETO ETO MD0 BW DB8 DI 88 SI i i 7 DIR EN 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 Interrupt Setup 4 Enable an ETCO transfer end interrupt ETOICL x 00FDAS ETO Under this state ETCO starts transferring when DMAREQO becomes low by bus mas ter After the ETCO transfer ends an ETCO transfer end interrupt occurs Each ETCO register value is set as follows ETOCNT x OFFF This value is always set regardless of the bytes to be transferred ETODST x 100004
122. MN102H55D 55G F55G Chapter 1 General Description Table 1 4 1 List of Pin Functions 4 26 Pin Number Pin Name Function Description 12 WORD P57 Input Data Bus Width Setup Input General purpose Port 57 This pin sets either 8 bit data bus width or 16 bit data bus width in the external memory space 0 immediately after re set release in processor mode or memory expansion mode Pulling the pin high sets 8 bit bus width while pulling the pin low sets 16 bit bus width In processor mode or memory expansion mode this pin must be used as the data bus width setup pin The MEMMD 1 register determines the data bus width for the external memory spaces 1 to 3 The 1 register can reset the data bus width for the ex ternal memory space 0 after reset release regardless the level of this pin Refer to 2 1 Summary of Bus Interface This pin can be used as a general purpose input output port in single chip mode The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports 81 ADSEP PAS Input y o Address Data Separate Shared Mode Setup General purpose Port A5 This pin sets either address data separate mode or ad dress data shared mode in processor mode or memory expansion mode Pulling the pin high sets the address data separate mode while pulling the pin low sets the ad d
123. One phase PWM Output Timing 16 bit Timer Dynamical Duty Change 144 Two phase PWM Output Block Diagram TODI TIMOR 145 Two phase PWM Output Timing 16 bit Timer 149 Two phase PWM Output Timing 16 bit Timer Dynamical Duty Change 150 One phase Capture Input Block Diagram 16 bit Timer 151 One phase Capture Input Timing 16 bit Timer 153 Two phase Capture Input Block Diagram 16 bit Timer 154 Two phase Capture Input Timing 16 bit Timer 157 Figure 4 4 13 Figure 4 4 14 Figure 4 4 15 Figure 4 4 16 Figure 4 4 17 Figure 4 4 18 Figure 4 4 19 Figure 4 4 20 Figure 4 4 21 Figure 4 4 22 Figure 4 4 23 Figure 4 4 24 Figure 4 4 25 Figure 4 4 26 Figure 4 4 27 Figure 4 5 1 Figure 4 5 2 Figure 4 6 1 Figure 4 6 2 Figure 4 6 3 Figure 4 7 1 Figure 4 7 2 Figure 4 8 1 Figure 4 8 2 Figure 5 1 1 Figure 5 1 2 Figure 5 1 3 Figure 5 1 4 Figure 5 1 5 Figure 5 1 6 Figure 5 1 7 Figure 5 1 8 Figure 5 2 1 Figure 5 2 2 Two phase Encoder Input 4x Block Diagram 16 bit Timer 158 Two phase Encoder Input 4x Configuration Example 1 158 Two phase Encoder Input 4x Configuration Example 2 158 Two phase Encoder Input Timing 4x 16 bit Timer 160 Two phase Encoder Input 1x Block Diagram 16 bit Timer 161 Two phase Encoder Input 1x Configuration Example 1 161 Two phase Enc
124. P4 PA PA P4 P4 P4 P4 LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMDI LMDO R W R W R W R W R W R W R W R W Processor mode 0 1 0 1 1 1 1 1 Other modes 0 0 0 0 0 0 0 0 7 6 P45 Input Output Signal Switch 00 Port 01 A21 output 10 AN5 54 P44 Input Output Signal Switch 00 Port 01 A20 output 10 AN4 3 P43 Input Output Signal Switch 0 Port 2 P42 Input Output Signal Switch 1 P41 Input Output Signal Switch 0 P40 Input Output Signal Switch 504 MN102H55D 55G F55G 1 A19 output 0 Port 1 A18 output 0 Port 1 A17 output 0 Port 1 A16 output PALMD x OOFFF6 Port 4 Mode Register L 8 bit access register P4LMD sets a signal output to the port 4 7 6 5 4 3 2 1 0 P4 P4 IHMD3HMD2 HMD 1 HMDO R R R R R W R W R W R W Processor mode 0 0 0 0 0 1 0 1 Other modes 0 0 0 0 0 0 0 0 0 0 0 0 0 1 01 0 1 3 2 P47 Input Output Signal Switch 00 Port 01 A23 output 10 AN7 1 0 P46 Input Output Signal Switch 11 WDOUT output 00 Port 01 A22 output 10 AN6 11 STOP output Chapter 11 Appendix P4HMD x OOFFF7 Port 4 Mode Register H 8 bit access register P4HMD sets a signal output to the port 4 MN102H55D 55G F55G 505 Chapter 11 Appendix P5 P5 P5 LMD7 LMD6 LMD5 P5 P5 P5 P5 ILMD4 LMD3 LMD2 LMD1 LMDO 5 R W R W R W
125. PO CORE D A Converter P6 1 P1 Interrupt A D Converter 7 P2 8 bit Timers Serial I F P8 P3 16 bit Timers ATC P9 P4 8 bit PWM ETC P5 Pulse Width Counte ROM PB 8 BOSC 2 gt TM8BC up TMBIOA pin TM8CA J TM8CB Capture B interrupt Figure 4 4 9 One phase Capture Input Block Diagram 16 bit Timer Chapter 4 Timers MN102H55D 55G F55G 151 Chapter 4 Timers 1 Use the MOV instruction to set the data and only use 16 bit write operations The timer 8 binary counter TM8BC is stopped and TM8BC register and RS F F are initialized cleared to 0 1 If this setting is omitted the bi nary counter may not count the first cycle Do not change to any other operating modes When TM8MDO 0 and TM8MD1 1 in capture mode TM8CA and TM8CB become read only registers If TM8CB must be set TM8MDO and TM8MD1 must be set to 0 152 MN102H55D 55G F55G Timer 8 Setting 1 Set the operating mode in the timer 8 mode register TM8MD Set counting stop Select up counting Select BOSC 2 as the clock source Set the operating mode of the capture register to capture both edges of TM8IOA pin TM8MD x 00FE80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM8 TM8 TM8 8 TM8 TM8 8 8 TM8 8 8
126. Power supply current Fosc1 34 MHz during operation Output pins open Vi or Vss Power supply current in _ SLOW mode Fosc2 32 kHz Output pins open Oscillator stop Power supply current in STOP mode All functions stop 1 34 MHz Power supply current in HALTO mode Fosc2 32 kHz Fosc1 oscillator stop Power supply current in HALT1 mode Fosc2 32 kHz 296 MN102H55D 55G F55G Chapter 11 Appendix Voo 3 0 V to 3 6 V Vss 0 V NC CA 40 C to 85 C Capactance Parameter Symbol Conditions Unit Input Output Pins 1 lt Output pushpull Input LVTTL level schmidt trigger Programmable pullup gt 00 07 10 17 20 27 P30 P37 P40 P43 P50 P57 P60 P63 P70 P75 P82 P87 P90 P93 PAO PA5 mee e e LII 2 0 mA Output high voltage Von 33V loL 2 0 mA Output low voltage 33 V VSS MN102H55D 55G F55G 297 Chapter 11 Appendix 3 0 V to 3 6 V E 0V oe C to 85 C Cmedeme Parameter Symbol Conditions Unit Input Output Pins 2 lt Output pushpull Input CMOS level schmidt trigger Programmable pullup Analog pins gt P44 P47 AN4 7 80 81 1 94 97 3 Pu loH 2 0 mA loL 2 0 mA aal te emo om v C17 Pullup resistance Ppu2 10 30 kQ 3 3 V 298 MN102H55D 55G F55G Chapter 11 Append
127. R W Port 3 Pull up Control Register P3OUT x 00FFC3 R W Port 3 Output Register P3IN x 00FFD3 R W Port 3 Input Register P3DIR R W Port 3 Input Output Control Register P3LMD x OOFFF4 R W Port 3 Mode Register P3HMD x OOFFFS R W Port 3 Mode Register P4PLU 4 R W Port 4 Pull up Control Register P4OUT x 00FFC4 Port 4 Output Register PAIN x O0FFD4 R W Port 4 Input Register P4DIR x OOFFE4 R W Port 4 Input Output Control Register P4LMD x OOFFF6 R W Port 4 Mode Register P4HMD x OOFFF7 R W Port 4 Mode Register PSPLU 5 R W Port 5 Pull up Control Register PS5OUT 00 5 R W Port 5 Output Register PSIN x 00FFD5 Port 5 Input Register PSDIR 00 5 R W Port 5 Input Output Control Register PSLMD x OOFFF8 R W Port 5 Mode Register L PSHMD x OOFFF9 R W Port 5 Mode Register P6PLU 00 R W Port 6 Pull up Control Register P6OUT x 00FFC6 R W Port 6 Output Register P6IN x O0FFD6 R W Port 6 Input Register P6DIR x O0FFE6 R W Port 6 Input Output Control Register P6MD x 00FFFF R W Port 6 Mode Register 262 MN102H55D 55G F55G P7PLU x O0FFB7 Port 7 Pull up Control Register x 00FFC7 Port 7 Output Register P7IN x O0FFD7 Port 7 Input Register P7DIR x OOFFE7 Port 7 Input Output Control Register P7LMD x O0FFFA Port 7 Mode Register L P7HMD x O0FFFB Port 7 Mode Register
128. R W R W R W R W R W Processor mode 0 1 0 Other modes 7 6 5 4 3 2 1 0 506 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 P53 Input Output Signal Switch P52 Input Output Signal Switch P51 Input Output Signal Switch P50 Input Output Signal Switch MN102H55D 55G F55G 00 Port 01 CS3 output 10 TM14OB output 00 Port 01 CS2 output 10 TM14OA output 00 Port 01 CS1 output 10 TM13OB output 00 Port 01 CSO output 10 TM130A output P5LMD x OOFFF8 Port 5 Mode Register L 8 bit access register P5LMD sets a signal output to the port 5 4 3 2 1 0 P5 P5 P5 P5 P5 HMDAIHMD3HMD2HMDI HMDO R R R R W R W R W R W R W Processor address data separate mode 0 0 0 1 1 0 Processor address data shared mode 0 0 0 0 1 0 Other modes 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 42 P56 Input Output Signal Switch 1 P55 Input Output Signal Switch 0 P54 Input Output Signal Switch 000 Port 001 ALE output 010 ALE output 011 BSTRE output 100 15 cannot use P24 as input 0 Port 1 BRACK output 0 Port 1 BREQ input Chapter 11 Appendix P5HMD x OOFFF9 Port 5 Mode Register H 8 bit access register P5HMD sets a signal output to the port 5 MN102H55D 55G F55G 507 Chapter 11 Appendix 7 6 5 4
129. Serene Se NE pee TM9AICL x 00FC64 ete Timer 9 Capture A Interrupt Control Register 8 bit access register Timer 9 A Interrupt 0 No interrupt requested Request Fla 1 Interrupt requested TMIMGE requests and verites q 9 pereg a timer 9 capture A interrupt Timer 9 Capture A Interrupt 0 No interrupt detected This register allows only byte Detect Flag 1 Interrupt detected accesses Use MOVB instruc tion to set the data RE TM9AICH 5 2 TM9A x 00 65 s z Timer 9 Capture A 1 Interrupt Control Register 8 bit access register Timer 9 Capture A Interrupt 0 Disable Enable Flag 1 Enable TM9AICH enables a timer 9 capture A interrupt This register allows only byte accesses Use MOVB instruc tion to set the data The inter level is the same level set in the IQ2LV 2 0 bits of the IQ2ICH register MN102H55D 55G F55G 355 Chapter 11 Appendix 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected F 6 5 4 3 2 1 0 TM9B TM9B IR ID R R R R W R R R R 0 0 0 0 0 0 0 0 0 1 0 0 0 1 4 Timer 9 Capture Interrupt Request Flag 0 Timer 9 Capture B Interrupt Detect Flag 7 6 5 4 3 2
130. Set the cycle 0 to x FFFE to the TM8CA register and the duty to the TM8CB regis ter When TM8BC TMSCB reset RS F F and TM8BC at the start of the next cycle The following shows the relationship between the waveforms of PWM output and the value TM8CB register 1 When 8 x 8 lt x FFFE all output waveforms consist of 0 2 When 0 TM8CB TM8CA under the condition that the PWM cycle is TM8CA 1 of the clock source output 0 if TM8BC equals to the value between 0 and TM8BC and output 1 if TM8BC equals to the value between TM8CB 1 and TM8CA 3 When TM8CB x FFFF all output waveforms consist of 1 Figure 4 4 4 shows the TM8IOA pin output waveforms when TM8CA 4 capture A interrupt or a capture B interrupt occurs A capture B interrupt occurs only when is set to 0 to TM8CA and does not occur when TM8CB is set to any other values TM8BC and the value cannot be matched In Figure 4 4 4 CLRBC8 means an internal signal which clears TM8BC S8 means an internal signal which sets RS F F for TM8IOA pin output R8 shows an internal signal which resets RS F F for TMBIOA pin output Chapter 4 Timers TM8MD write M EM M TM8EN TM8BC 0 0 BOSC 2 CLRBC8 it TE TE l 1 W
131. Switch polarity of e Clear BC with 9 rising edge falling edge TMSIOA TMSIOB output pin input Pulse phase or both edges difference detection MN102H55D 55G F55G 127 Chapter 4 Timers 128 MN102H55D 55G F55G BC Value CA CB Time TMnIOA TMnOA BC Value CA CB Figure 4 3 2 One phase PWM Output Timing Change reflected Write CB value in next cycle Time TMnIOA TMnOA Figure 4 3 3 One phase PWM Output Timing with Data Rewrite BC Value CA CB Time TMnOA TMnOB Figure 4 3 4 Two phase PWM Output Timing Chapter 4 Timers BC Value Figure 4 3 5 One shot Pulse Output Timing BC Value CA i i i i Time TMnIB TMnIA Figure 4 3 6 External Control Timing BC Value Time ee TU D DURS Figure 4 3 7 Event Counter Input Timing MN102H55D 55G F55G 129 Chapter 4 Timers BC Value FFFF Time TMnIB 32 2 5 Y 1 1 TMnIA NES 0 i 0033 Example I 5A87 Example Figure 4 3 8 Input Capture 1 Timing BC Value FFFF r Time TMnIB x TMnIA sess arc
132. TM121OB pin 011 BOSC 2 100 Two phase encoder 4x of TM12IOA pin TM121OB pin 101 Two phase encoder 1x of TM121OA pin TM121OB pin MN102H55D 55G F55G 453 Chapter 11 Appendix TM13 TMI3 13 13 13 LD CLR OB OA 5 R W R W R W R R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 7 TM13BC Count 6 Load TM13BR to TM13BC 5 TM130A TM130B Signal Level 2 TM130B Output Edge Select 1 TM130A Output Edge Select 0 Clock Source Selection 7 6 5 4 3 2 1 0 14 14 14 14 14 14 LD CLR OB OA 5 R W R W R R R R R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 7 TM14BC Count 6 Load TM14BR to TM14BC 5 TM140A TM140B Signal Level 2 TM140B Output Edge Select 1 TM140A Output Edge Select 0 Clock Source Selection 454 MN102H55D 55G F55G 0 Disable 0 Disable 0 Disable 1 Enable 0 Positive logic 0 Positive logic 0 BOSC 2 1 Timer 0 underflow 0 Disable 0 Disable 0 Disable 1 Enable 0 Positive logic 0 Positive logic 0 BOSC 2 1 Timer 0 underflow 1 Enable 1 Enable 1 Negative logic 1 Negative logic 1 Enable 1 Enable 1 Negative logic 1 Negative logic TM13MD 28 Timer 13 Mode Register 8 bit access register TM13MD sets the timer 13 oper ating conditions Whenever the timer 13 count
133. TM8IOB P Interrupt 6 b P 1 ME m MEM Figure 4 4 12 Two phase Capture Input Timing 16 bit Timer MN102H55D 55G F55G 157 Chapter 4 Timers 4 4 6 Two phase Encoder Input 4x Using 16 bit Timer Timer 8 receives a two phase encoder input 4x and counts up and down An interrupt occurs when the TM8BC value reached the TMSCA value or the TM8CB value PO CORE D A Converter P6 TMBIOB pin P1 Interrupt onverter P7 P2 8 bit Timers Serial 8 16 61 Timers 9 8 bit PWM ETC PA P5 Pulse Width Counter ROM RAM PB Timer 8 TM8BC vadit TM8IOA pin gt TM8CA Lon 5 5 x gt TM8CB interrupt Figure 4 4 13 Two phase Encoder Input 4x Block Diagram 16 bit Timer TM8BC Value 0 1000 Xx1FFF Capture B interrupt Figure 4 4 14 Two phase Encoder Input 4x Configuration Example 1 As Figure 4 4 15 shown it is possible to set capture A interupt and capture B interrupt in different places separately Setting TM8LP of the TM8MD register to 0 is required 158 MN102H55D 55G F55G 0 1000 Capture A interrupt x FFOO Capture B interrup
134. The load program Is attached to the serial writer 11 4 5 Hardware Used in Serial Programming Mode B Interface The MN102HF55G incorporates the following functions as I F for serial program ming One 8 bit Serial Interface Data transmission reception synchronizing external clock or internal clock Bit order LSB first MSB first Maximum transfer speed 7 5 Mbps at 30 MHz oscillation Positive input output logic Two Input Output Pins SBT SBD reserved for serial interface I F Block Diagram SBD 7 8 Serail I F RXC TXC 4 fj SBT 74pin Figure 11 4 3 8 bit Serial Interface Block Diagram for Serial Writer Chapter 11 Appendix Memory Space of Internal Flash EEPROM Address Size Area den Serial Writer FF x 80000 803 1 kbytes Load Program Area x 80400 x 817FF 5 kbytes Fixed User Program Area x 81800 x 81807 Security Code Ge 2 Branch Instruction riya Branch Instruction 1818 8181 8 bytes to Interrupt Service Routine 122 kbytes x 81820 x9FFFF to User Program Area 32 bytes Figure 11 4 4 Flash EEPROM Memory Space Serial Writer Load Program Area The 1 kbyte area from x 80000 stores the load program for serial writer In onboard serial programming mode the erasing programming in this area is protected Programming is possible by using the parallel writer Fixed User Program Area The 5 kbyte area from x 80400
135. Timer 5 Underflow Interrupt Control Register 8 bit access register TMBUICL requests and verifies a timer 5 interrupt This register allows only byte accesses Use the MOVB in struction to set the data TM5UICH x 00FC7B Timer 5 Underflow Interrupt Control Register 8 bit access register 5 enables a timer 5 in terrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the KILV 2 0 bits of the KIICH register Chapter 11 Appendix Ss dues Pi 20 TM11AICL t x 00FC7C 11 Interrupt Control Register 8 bit access register Timer 11 Capture A Interrupt 0 No interrupt requested TM11AICL requests and verifies Request Flag 1 Interrupt requested Eimer capture A interrupt Timer 11 Capture A Interrupt 0 Interrupt undetected This register allows only byte Detect Flag 1 Interrupt detected accesses Use the MOVB in struction to set the data Sr Paes Me de TM11AICH IE x 00FC7D s E Timer 11 Capture A 1 Interrupt Control Register 8 bit access register Timer 11 Capture A Interrupt 0 Disable Enable Flag 1 Enable TM11AICH enables a timer 11
136. W Flag W Code Size e change Unit byte no change 0 normally 0 1 normally 1 undefined W Machine Code separates the byte units lt lt 2 indicates 2 bit shift Dn Dm Di An Am register numbers DO 00 AO 00 D1 01 Al 01 D2 10 A2 10 D3 11 A3 11 Instructions that access 16 bit and 24 bit data must use an even memory address All 8 bit displacements d8 and 16 bit displacements d16 are sign extended 544 MN102H55D 55G F55G MN102H00 SERIES INSTRUCTION MAP First byte Upper Lower 0 1 2 3 4 5 6 0 MOV Dm An Chapter 11 Appendix 1 2 3 MOVBU An Dm 4 MOV Dm d8 An 5 MOV Am d8 An 6 MOV d8 An Dm 7 MOV d8 An Am 8 MOV Dn Dm when src dest MOV imm8 Dn 9 ADD Dn Dm A SUB Dn Dm B EXTX Dn EXTXU Dn EXTXB Dn EXTXBU Dn MOV abs16 MOVB Dn abs16 MOV abs16 Dn MOVBU abs16 Dn D ADD imm8 ADD imm8 Dn imma8 Dn MOV imm16 An BLT BGT BGE BLE BCS BHI BCC label label label label label label label BLS label BNE BRA label label imm16 An Extended code Extended code Extended code Extended code Extended code Extended F A B Second byte Byte 1 FO Second byte Upper Lower 1 2 3 4 5 6 Extended code G imm16
137. When it is not accessing the external memory the output value is undefined Refer to 2 1 Summary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state This pin can be used as a general purpose input output port if it is not used as the address output pin in single chip mode processor mode or memory expansion mode The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports This pin can be used as a synchronous transfer clock sig nal input output pin for serial interface 2 if it is not used as WAIT in single chip mode processor mode or memory ex pansion mode Because pin 13 has the same function ei ther pin 13 or pin 1 must be selected Refer to Chapter 5 Serial Interface 30 MN102H55D 55G F55G Chapter 1 General Description Table 1 4 1 List of Pin Functions 10 26 Pin Number Pin Name Function Description 14 Al Output Address Output Refer to Pin 13 AO Description for details 21 General purpose Port 21 Refer to Pin 13 P20 Description for details SBI2 Input Serial Interface 2 This pin can be used as a data input pin for serial interface Data Input 2 if itis not used as the address output pin in single chip mode processor mode or memory expansion mode Be cause pin 50 has the same function either pin 50 or pin 14 must be selected Refer to Chapter 5
138. When the desti nation pointer increment bit is set to be fixed the transfer source address do not change When the source pointer incre ment bit is set to increment in crement by 1 in the byte transfer and by 2 in the word transfer IDST23DST22DST21 DST20DSTI9DSTI8DSTI7DSTI6 R W R W R W R W R W R W R W R W undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 This register writes only 24 bit data or 16 bit data Use the MOV instruction or the MOVX instruction to set the data MN102H55D 55G F55G 409 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETO ETO ETO ETO ETO ETO ETO ETO ETO FLG MDO BW DB8 DI SB8 SI DIR EN R W R W R W R W R W R W R W R R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 o 0 0 0 0 15 Transfer Busy Start Flag 0 Disable 1 Transfer start transfer in progress 13 Transfer Mode 0 One byte word transfer 1 Burst transfer 12 Transfer Units 0 Word 1 Byte 11 Destination Bus Width 0 16 bit 1 8 bit 10 Destination Pointer 0 Fixed Increment 1 Increment 9
139. When the operating mode selection bits ANMD 1 0 are set to multiple channels single conversion the A D converter converts consecutive AN input signals once An interrupt occurs when the conversion sequence ends The channel selection bits ANICH 2 0 are set to channel 0 and the number of the final channel to be converted is set to ANNCH 2 0 The conversion always starts with channel 0 When the software starts the conversion write 0 and 1 to the timer conversion start flag ANTC and the conversion start execution flag ANEN of the A D converter control register ANCTR respectively When ANTC 1 the ANEN flag becomes 1 at timer 3 underflow The ANEN flag remains 1 during the conversion and clears 0 when the conversion ends AN1CH 2 0 show the number of channel being converted and they clear to 0 when the conversion sequence ends Start Stop Interrupt request Och ch 2ch ponversionponversionponversion State ANEN Figure 6 1 4 Multiple Channels Single Conversion Timing Chapter 6 Analog Interface MN102H55D 55G F55G 215 Chapter 6 Analog Interface 216 MN102H55D 55G F55G Single Channel Continuous Conversion Timing When the operating mode selection bits ANMD 1 0 are set to single channel con tinuous conversion the A D converter converts one AN input signal continuously An interrupt occurs when the conversion ends The number of channel to be converte
140. Write the dummy data x FF al ways Verify that reception ends by an interrupt either a serial 3 trans mission end interrupt or a serial 3 reception end interrupt or poll ing the received data flag of the serial 3 status register Polling the reception busy flag is not al lowed during mode MN102H55D 55G F55G 209 Chapter 5 Serial Interface sequence output bit Write to SC3TRB Dummay data transmission for reception i SDAS pin output 4 b7 b6 b5 b4 b3 b2 b1 bO ACK b7 b6 b5 b4 b3 b2 b1 bO ACK Transmission Transmission interrupt request interrupt request SCL3 pin output START detection bit 1 i j STOP detection bit 1 Data Transmission Reception Setting Data Reception Stop sequence Figure 5 2 8 Master Reception Timing 210 MN102H55D 55G F55G Chapter 6 Analog Interface 6 Chapter 6 Analog Interface 212 MN102H55D 55G F55G 6 1 Summary of A D Converter 6 1 1 Overview The MN102H55D 55G F55G contains a 10 bit charge redistribution A D converter which processes up to 8 channels Using the clock selec tion bits the clock source for A D converter is selected to BOSC 2 BOSC 4 BOSC 8 or BOSC 16 When BOSC is 30 MHz the clock
141. capture A interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the ADLV 2 0 bits of the ADICH register Chapter 11 Appendix ASH EN B TM7UICL Te as 00 88 Timer 7 Underflow Interrupt Control Register 8 bit access register Timer 7 Underflow Interrupt 0 No interrupt requested TM7UICL requests and verifies Request Flag 1 Interrupt requested amher 7 interrupt Timer 7 Underflow Interrupt 0 Interrupt undetected This register allows only byte Detect Flag 1 Interrupt detected accesses Use the MOVB in struction to set the data 6 5 4 3 2 1 0 TM7UICH TM7U TM7U TMTU ITM7U LV2 LVI Lvo IE x 00FC89 op SS MEN d Timer 7 Underflow 0 0 0 0 0 0 on on Interrupt Control Register 8 bit access register Timer 7 Underflow Interrupt Set the level from 0 to 6 Level Setup TM7UICH enables a timer 7 in terrupt Timer 7 Underflow Interrupt 0 Disable This register allows only byte Enable Flag 1 Enable accesses Use the MOVB in struction to set the data MN102H55D 55G F55G 373 Chapter 11 Appendix F 6 5 4 3 2 0 TMDB 12 IR ID
142. ing is stopped and TM130B signals go low when the positive logic is selected as output edge while these signals go high when the negative logic is selected as output edge TM14MD x O0FE29 Timer 14 Mode Register 8 bit access register TM14MD sets the timer 14 oper ating conditions Whenever the timer 14 count ing is stopped TM14OA and TM140B signals go low when the positive logic is selected as output edge while these signals go high when the negative logic is selected as output edge Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM1 5MD E 15 TM15 TM15 BC ed CLKI CLKO x OOFEDO R W R R R R R R R R R R R R W R W Timer 15 Mode Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 16 bit access register 15 TM15BC Count 0 Disable 1 Enable TM15MD sets the timer 15 oper ating conditions 14 Reserved Set to 0 1 0 Clock Source Selection 00 Timer 0 underflow 01 IRQ4 pin 10 BOSC 2 11 BOSC MN102H55D 55G F55G 455 Chapter 11 Appendix 15 TM8 15 8 14 TM8 CA13 TM8 CA12 TM8 CAII TM8 10 TM8 CA9 TM8 CA8 TM8 CA7 TM8 CA6 TM8 CA5 TM8 CA4 TM8 CA3 TM8 CA2 TM8 CA1 TM8 CA0 R W R W R W R W R W R W R W R W R W R W R W
143. nation address When the desti nation pointer increment bit is set to be fixed the transfer source address do not change When the source pointer incre ment bit is set to increment in crement by 1 in the byte transfer and by 2 in the word transfer ATI ATI ATI ATI ATI IDST23DST22DST21 DST20DSTI9DSTI8DSTI7DSTI6 R W R W R W R W R W R W undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 This register writes only 24 bit data or 16 bit data Use the instruction or the MOVX instruction to set the data MN102H55D 55G F55G 403 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AT2 AT2 AT2 AT2 AT2 AT2 AT2 AT2 AT2 AT2 AT2 2 EN BW DB8 DI SB8 SI 103 102 IQ1 100 R W R W R W R W R W R W R W R W R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 15 Transfer Busy Start Flag 0 Disable 14 13 Transfer Mode 12 Transfer Units 11 Destination Bus Width 10 Destination Pointer Increment 9 Source Bus Width 8 Source Pointer Increment 3 0 ATC Activation Factor
144. output two phase PWM 000 Timer 0 underflow 001 Timer 4 underflow 010 TM8IOB pin 011 BOSC 2 100 Two phase encoder 4x of TM8IOA pin TM8IOB pin 101 Two phase encoder 1x of TM8IOA pin 8 pin 110 8 pin TM8MD x O0FES80 Timer 8 Mode Register 16 bit access register TM8MD sets the timer 8 operat ing conditions During repeat counting hold the flag state During one shot counting set the TM8EN flag to 0 when TM8BC TM8CA TM8 8 TM8 IOB IOA R R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 Pin Input Edge Select TMS8IOB Pin Output TMB8IOA Pin Output 0 Change 8 pin output on the ris ing edge 1 Change 8 pin output on the fall ing edge 0 Positive 1 Negative 0 Positive 1 Negative Chapter 11 Appendix TM8MD x OOFE8E Timer 8 Mode Register 2 8 bit access register TM8MD2 sets the timer 8 oper ating conditions MN102H55D 55G F55G 447 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 TM9 TM9 TM9 TM9 TM9 TM9 TM9 TM9 EN NLD UDO TGE ONE MD1 MDO ECLR LP ASEL S2 s SO R W R W R R W R W
145. 0 0 0 0 0 0 1 0 8 Load TM7BR value to the timer 7 binary counter TM7BC At the same time select the timer 0 underflow as the clock source TM7MD x 00FE27 7 6 5 4 3 2 1 0 TM7 TM7 TM7 TM7 EN LD 51 50 0 1 0 1 9 Set TM7LD to 0 and TM7EN to 1 This starts the timer Counting begins at start of the next cycle When the timer 7 binary counter TM7BC reaches 0 and loads the value 1 from the timer 7 base register TM7BR at the next count the TM7IO output signal is simulta neously inverted The TM7IO signal starts 0 and then transfer to at the start of the next count cycle The TM7IO output signal backs to 0 at the start of the following count cycle By repeating this inversion the timers generate a 12 cycle BOSC clock output signal TMO underflow TM7IO pin output BOSC 2 TMOBR TMOBC TM7BR TM7BC Chapter 4 Timers Setting TMOEN and TMOLD to 0 is required between 8 and 9 in the bank address version and the linear address version but this setting is not required in the linear address high speed ver sion Do not change the clock source once you have selected it Selecting the clock source while setting the count operation con trol will corrupt the value in the binary counter
146. 0 0 on on o 0 0 6 4 Serial 0 Transmission End Set the level from 0 to 6 Interrupt Level Setup 0 Serial 0 Transmission End 0 Disable Interrupt Enable Flag 1 Enable Chapter 11 Appendix SCOTICL 00 90 Serial 0 Transmission End Interrupt Control Register 8 bit access register SCOTICL requests and verifies a serial 0 transmission end inter rupt This register allows only byte accesses Use the MOVB in struction to set the data SCOTICH 91 Serial 0 Transmission End Interrupt Control Register 8 bit access register SCOTICH sets a seial 0 trans mission end interrupt level and enables an interrupt This register allows only byte accesses Use the MOVB in struction to set the data 5 MN102H55D 55G F55G 375 Chapter 11 Appendix 7 6 5 4 3 2 0 SCOR SCOR IR ID R R R R W R R R 0 0 0 0 0 0 0 on o 0 1 4 Serial 0 Reception End 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 0 Serial 0 Reception End 0 Interrupt undetected Interrupt Detect Flag 1 Interrupt detected 7 6 5 4 3 2 0 SCOR IE R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 1 0 Serial 0 Reception End 0 Disable Interrupt Enable Flag 1 Enable 376 MN102H55D 55G F55G SCORICL 00 92 Serial 0 Reception End Interrupt Control Register 8 bit access re
147. 0 0 0 0 0 0 0 0 0 0 O 1 4 Write the dummy data to the timer 8 compare capture register TM8CAX to set the initial value in the TM8CAX register The value cannot be written directly in the TM8CAX register by software In the double buffer mode read the timer 8 compare capture register A TM8CA to TM8CAX when TM8CAX TMSBC To read the TM8CA value into TM8CAX write the dummy data to TM8CAX MN102H55D 55G F55G 141 Chapter 4 Timers 1 If this setting is omitted the bi nary counter may not count the first cycle Do not change to any other operating modes 142 MN102H55D 55G F55G 5 Write the dummy data to the timer 8 compare capture register BX TM8CAX to set the initial value in the TM8CBX register The value cannot be written directly in the TM8CBX register by software In the double buffer mode read the timer 8 compare capture register TM8CB to TM8CBX when TM8CBX TM8BC To read the TM8CB value into TM8CBX write the dummy data to TM8CBX 6 Set TM8NLD and TM8EN TM8MD to 1 0 respectively This enables TM8BC and RS F F 7 Set TM8NLD and TM8EN to 1 This starts the timer Counting begins at the start of the next cycle Timer 8 outputs a one phase PWM at any duty Select up counting Do not use timer 8 when BOSC stops in STOP mode All external inputs are sampled on BOSC synchronized with BOSC when the external clock operates
148. 0 0 0 0 0 0 0 0 0 0 0 1 1 1 wait cycle 1 5 wait cycles 2 wait cycles 3 wait cycles 1 Please refer to Figure 2 1 1 Memory Space on page 52 for address allocation of the exter nal memory spaces 54 MN102HF55G H55G H55D BRS 1 0 Address Setting 16 bit Bus Width 8 bit Bus Width for Burst Operation 00 A1 2 words 4 bytes 01 A1 A2 4 words 8 bytes 10 AO A1 A2 A3 8 words 16 bytes 11 AO A1 A2 4 16 words 32 bytes EB 01 00 Bus Width Setting for External Memory Space 0 1 2 16 bit bus width 8 bit bus width Reserved 8 bit bus width when A8 pin is high 16 bit bus width when A8 pin is low 2 The reset value is 00 when WORD pin is low while the reset value is 01 when WORD pin is high EB 11 10 Bus Width Setting for External Memory Space 1 1 00 16 bit bus width 01 8 bit bus width 10 Reserved 11 8 bit bus width when A8 pin is high 16 bit bus width when A8 pin is low EB 21 20 Bus Width Setting for External Memory Space 2 1 00 16 bit bus width 01 8 bit bus width 10 Reserved 11 8 bit bus width when A8 pin is high 16 bit bus width when A8 pin is low EB 31 30 Bus Width Setting for External Memory Space 3 1 00 16 bit bus width 01 8 bit bus width 10 Reserved 11 8 bit bus width when A8 pin is high 16 bit bus width when A8 pin is low Do not access th
149. 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 16 bit access register 15 TM12BC Count 0 Disable 1 Enable TM12MD sets the timer 12 oper ating conditions 14 TM12BC T F F RS F F 0 Set TM12BC T F F RS F F to 0 Operation 1 Operate TM12BC T F F RS F F 11 10 Up Down Counter Mode 00 Up counter Selection Ignored when two 01 Down counter phase encoding is selected 10 Up when TM121OA pin is high down when TM121OA pin is low 11 Up when 2 pin is high down when 12 pin is low 9 Count Start External Trigger 0 Disable Enable 1 Start counting on the falling edge of TM121OB pin 8 Counter Operating Mode 0 Repeat 1 One shot counting During repeat counting hold the Selection TM12EN flag state During one shot counting set the TM12EN 7 6 12 TM12CB Operating 00 Compare register single buffer bei Pn when Mode Selection 01 Compare register double buffer 10 Capture A when pin is high Capture when 12 pin is low 11 Capture A when is high Capture when 2 pin is high 5 TM12BC Clear 0 Don t clear 1 Clear when external synchronization is used 4 TM12BC Count Range 0 0to FFFF 1 0to TM12CA 3 12 Pin Output 0 RS F F output one phase PWM 1 T F F output two phase PWM 2 0 Clock Source Selection 000 Timer 0 underflow 001 Timer 4 underflow 010
150. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 ANS AN5 AN5 AN5 AN5 ANS ANS AN5 AN5 ANS BUF9 BUF8 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF BUFO R R R R R R R R R R R R R R R R 0 0 0 0 0 O Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 472 MN102H55D 55G F55G AN4BUF 10 Conversion Data Buffer 16 bit access register AN4 conversion data When 8 bit is selected as A D converter resolution the AN4BUF 7 0 bits hold the data and the AN4BUF 9 8 bits be come 0 When 10 bit is se lected as A D converter resolu tion the ANABUFT 9 0 bits hold the data AN5BUF x OOFF12 AN5 Conversion Data Buffer 16 bit access register AN5 conversion data When 8 bit is selected as A D converter resolution the ANSBUFT 7 0 bits hold the data and the AN5BUF 9 8 bits be come 0 When 10 bit is se lected as A D converter resolu tion the ANBBUFT 9 0 bits hold the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AN6 AN6 AN6 AN6 AN6 AN6 AN6 AN6 AN6 AN6 BUF9 BUF8 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUFO R R R R R R R R R R R R R R R R 0 0 0 0 0 O Undefined Undefined Undefined Undefined Undefined Un
151. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 9 2 1 0 TM9 9 TM9 9 9 9 9 9 9 9 9 9 9 TM9 9 TM9 5 BC14 BC13 BC12 BC11 BCIO BC8 BC7 BC6 BCS BC4 BC3 BC2 BCO R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO 5 BC14 BC13 BC12 BCII BCIO BC8 BC7 BC6 BCS BC4 BC3 2 BCO R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 3 4 3 2 1 0 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 5 BC14 BC13 BC12 BC10 BC8 BC6 BCS BC4 BC3 BC2 BCO R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Chapter 11 Appendix x OOFE82 Timer 8 Binary Counter 16 bit access register TM8BC operates timer 8 count ing TM9BC x OOFE92 Time
152. 0 5 mode RE short 1 mode RE short 1 5 mode REEL 21 20 RE Late Mode in CS2 Area RE late 0 5 mode at reset RE late 1 mode RE late 2 mode RE late 3 mode 21 20 RE Short Mode in CS2 Area RE short 0 mode at reset RE short 0 5 mode RE short 1 mode RE short 1 5 mode REEL 31 30 RE Late Mode in CS3 Area RE late 0 5 mode at reset RE late 1 mode RE late 2 mode RE late 3 mode REES 31 30 RE Short Mode in CS3 Area RE short 0 mode at reset Please refer to Table 2 2 2 on RE short 0 5 mode page 76 and Table 2 2 4 on RE short 1 mode page 78 for the timing RE short 1 5 mode 58 MN102HF55G H55G H55D Chapter 2 Bus Interface The WEEDGE register sets the WE waveform control modes for the external memory spaces 0 to 3 WEEDGE x 00FF88 15 04 573 ABE 16 5101 19 8 C Gree 32391210 EESWEESWEELWEELWEESWEESWEELWEELWEESWEESWEELWEELWEESWEESWEELWEEL 31 30 31 30 21 20 21 20 11 10 11 10 01 00 01 00 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __ WEEL 01 00 WE Late Mode CSO Area WE late 1 mode at reset WE late 2 mode WE late 3 mode Reserved WEES 01 00 WE Short Mode in CSO Area WE short 0 mode at reset WE short 0 5 mode WE short 1 mode WE short 1 5 mode WEEL 11 10 WE Late Mode CS1 Area WE late 1 mode at reset
153. 00 98 Serial 2 Transmission End Interrupt Control Register SC2TICH 00 99 R W Serial 2 Transmission End Interrupt Control Register SC2RICL 00 9 R W Serial 2 Reception End Interrupt Control Register SC2RICH 00 Serial 2 Reception End Interrupt Control Register SC3TICL 00 R W 3 Transmission End Interrupt Control Register SC3TICH 00 9 R W Serial 3 Transmission End Interrupt Control Register SC3RICL x OOFC9E Serial 3 Reception End Interrupt Control Register SC3RICH x O0FCOF R W 3 Reception End Interrupt Control Register SC4TICL 00 Serial 4 Transmission End Interrupt Control Register SC4TICH x 00FCAI R W Serial 4 Transmission End Interrupt Control Register SC4RICL x O0FCA2 4 Reception End Interrupt Control Register SCARICH x 00FCA3 R W Serial 4 Reception End Interrupt Control Register ATOICL 00 8 R W 0 Transfer End Interrupt Control Register ATOICH 9 R W ATC 0 Transfer End Interrupt Control Register R W 1 Transfer End Interrupt Control Register R W 1 Transfer End Interrupt Control Register AT2ICL x 00FCAC R W ATC 2 Transfer End Interrupt Control Register AT2ICH x 00FCAD ATC 2 Transfer End Interrupt Control Register AT3ICL x 00FCAE R W ATC 3 Transfer End Interrupt Control Register AT3IC
154. 1 2 100 100 100 100 100 100 IR ID LV2 LV1 LVO IE 0 0 1 0 1 1 MN102H55D 55G F55G 3 Enable interrupts by writing the IE flag PSW to 1 and the IMn flag to 7 bit setting 111 Thereafter an interrupt occurs on the negative edge of the IRQO PAO pin The pro gram branches to x 080008 when the interrupt is accepted Interrupt Service Routine 4 Specify the interrupt group by reading the IAGR register during interrupt prepro cessing 5 Execute the interrupt service routine 6 Clear the IQOIR flag of the IQOICL register 7 Return to the main program with the RTI instruction after the interrupt service routine ends PAO IRQO IRQTRG IQOIE IQoIR Interrupt Servicing Registers R W Y Low level Negative Edge IRQTRG W IQOICH W 1 Figure 3 2 2 External Pin Interrupt Timing IQOICL W 2 3 IQ0ICL W 4 5 6 7 IQOICL W 4 5 6 7 Chapter 3 Interrupts After the program branches to 080008 the program gener ates the interrupt service routine start address and then branches to that address During the interrupt service rou tine disable an interrupt by set ting the IM flag of PSW register to the interrupt level and the IE flag to 0 In addition other inter rupts except nonmaskable inter rupts are not accepted unless PSW register is set MN102H55D 55G F55G 95 Chapte
155. 1 1 8 bit Timer Functions Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Timer 7 TMOICL TM1ICL TM2ICL TMSICL TM4ICL TM6ICL TM7ICL Interrupt Request Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Timer 7 Interrupt Source underflow underflow underflow underflow underflow underflow underflow underflow Interval Timer v v v v v v v v Event Counter v v v Clock Source T _ _ 7 _ _ for 16 bit Timer Timer Output v v v TMOIO pin TM4IO pin Clock Source v v 5 for Serial Interface A D Conversion Trigger v z z 1 4 TMO TMO TMO TMO TMO TMO TMO underflow underflow underflow underflow underflow underflow underflow 2 BOSC Cascade Cascade Cascade Cascade Cascade Cascade Cascade 3 TMOIO pin TM4 TM4 TM4 TM4IO BOSC TM4 TM7IO underflow underflow underflow underflow Cascade v v v v v 108 MN102H55D 55G F55G Cascading Cascading eee CO OOOO of Configuration Example 16 bit 8 bit 8 bit 8 bit 8 bit 16 bit Timer Ouput Interval Synchronous UART Event Event Timer Transfer Transfer Counter Counter Clock Clock for serial for serial Figure 4 1 2 Timer Configuration TMnBC Value Load Value pe RES EE ES
156. 1 shows the comparison between this LSI series and the previous 16 bit series Table 3 1 1 Comparison of MN102H55D 55G F55G and MN102B00 MN102L00 Parameters MN102B00 MN102L00 MN102H55D 55G F55G 1 vector per grou Interrupt Groups TURCOES DUI group DU separated by interrupt Generated the group IAGR group numbers 2 service routine number for each interrupt Interrupt Response Time Good Excellent Interrupt Level Setup 4 vectors per level 4 vectors per level Software Compatibility Easily modified The MN102H55D 55G F55G has five external interrupt pins and eight key interrupt pins The IRQTRG register the KEYTRG register and the KEYCTR register set the interrupt conditions positive edge negative edge both edges or low level KEYTRG KEYCTR a 506 ae MASK Interrupt eve MASK to CPU KI7 Edge Level OR Interrupt IR QIRG Arbitration IRQO Edge Level gt IRQ1 Edge Level gt IRQ4 Edge Level d Internal interrupt Figure 3 1 1 Interrupt Controller Block Diagram The MN102H55D 55G F55G contains the watchdog timer and the extended watch dog timer The CPUM register and the WDREG register sets the interval until a watchdog interrupt occurs watchdog timer extended watchdog timer clear the chip reset when a watchdog interrupt o
157. 11 10 9 8 7 6 5 4 3 2 1 0 6 KIS 2 KI2 KIO KIO TG1 TGO TG1 TGO TG1 TGO TG1 TGO TG1 TGO TG1 TGO TG1 TGO TG1 TGO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KIOTG 1 0 Interrupt trigger condition for IRQ4 pin Low level Both edges Negative edge Positive edge Interrupt trigger condition for KIO pi KH TG 1 0 Interrupt trigger condition for KI1 pi KI2TG 1 0 Interrupt trigger condition for KI2 pi KISTG 1 0 Interrupt trigger condition for KI3 pi KI4TGI1 0 Interrupt trigger condition for KI pi Interrupt trigger condition for KI5 pi KI6TG 1 0 Interrupt trigger condition for KI6 pi KI5TG 1 0 KI7TG 1 0 Interrupt trigger condition for pi Low level Both edges Negative edge Positive edge MN102H55D 55G F55G 89 Chapter 3 Interrupts KEYCTR x 00FCB4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KI6 E KI3 K KIO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OR interrupt trigger condition for KIO pi OR interrupt trigger condition for pi n OR interrupt trigger condition for KI2 pin OR interrupt trigger condition for KI3 pin OR interrupt trigger conditi
158. 12 12 12 12 12 12 12 12 12 12 12 x OOFECS8 15 CB14 12 CB11 CB9 CB8 CB7 6 5 CB4 2 R W R W R W R W R W R W R W R W R W R W R W R W Timer 12 Compare 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Ca ture Re ister B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 9 16 bit access register TM12CB sets the timer 12 PWM duty changes PWM and gener ates a timer 12 capture B inter rupt When capture is selected this register is read only A timer 12 capture B interrupt is generated when capture occurs When compare is selected set the PWM duty When this register matches the timer 12 binary counter a timer 12 capture B in terrupt occurs This register write only 16 bit data Use the MOV instruction to set the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2CBX T12C T12C T12C T12C TI2C T12C TI2C TI2C T12C TI2C TI2C T12C T12C TI2C TI2C TI2C 15 14 12 10 9 BX8 7 6 5 4 BX3 BX2 BXO x OOFECA uh sie dr ger eM 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Capture Register Set
159. 13 PWM output pin if it is not used as a chip select output pin in single chip mode processor mode or memory expansion mode Refer to Chapter 4 Timers 6 51 Output Chip Select Output Refer to Pin 5 CSO Description for details TM130B Output Timer 13B Output This pin can be used as a timer 13 PWM output pin if it is not used as a chip select output pin in single chip mode processor mode or memory expansion mode Refer to Chapter 4 Timers 7 CS2 Output Chip Select Output Refer to Pin 5 CSO Description for details TM14OA Output Timer 14A Output This pin can be used as a timer 14 PWM output pin if it is not used as a chip select output pin in single chip mode processor mode or memory expansion mode Refer to Chapter 4 Timers 28 MN102H55D 55G F55G Chapter 1 General Description Table 1 4 1 List of Pin Functions 8 26 Pin Number Pin Name Function Description CS3 TM14OB Output Output Chip Select Output Timer 14B Output Refer to Pin 5 50 Description for details This pin can be used as a timer 14 PWM output pin if it is not used as a chip select output pin in single chip mode processor mode or memory expansion mode Refer to Chapter 4 Timers ALE ALE BSTRE P56 15 Output Output Output y o Input Address Latch Enable Output Positive Logic Address Latch Enable Output Negative Logic Read Enable for Burst RO
160. 16 kbytes eee Block14 14 kbytes 15 1 kbyte x 9FFFF Block16 1 kbyte Figure 11 4 1 Memory Map for Flash EEPROM Version Chapter 11 Appendix 11 4 2 Flash EEPROM Programming The following figure shows the steps of flash memory programming Write 0 to entire memory Erase ERASE Process Erase Routine Reverse User Data Program Figure 11 4 2 Flash EEPROM Program Flow As the above figure shows programming starts after erasing is completed The whole erase routine consists of three steps 1 Programming process which writes x 0000 to flash EEPROM before the actual erase process occurs 2 Erase process which operate the actual erasing 3 Reverse process 11 4 3 PROM Writer Mode In this mode the MN102HF55G allows a PROM writer to program the flash EEPROM The MN102HF55G uses a dedicated adaptor which connects to the DATA I O s LabSite PROM writer or the Minato Electronics Model 1930 writer Using the dedicated adaptor selects PROM writer mode automatically MN102H55D 55G F55G 525 Chapter 11 Appendix 526 MN102H55D 55G F55G 11 4 4 Onboard Serial Programming Mode The serial programming mode is used to program the flash ROM in the MN102HF55SG that is installed on the board The following sections describe the MN102HF55G hardware system configuration protocol for this programming mode When using YDC dedicated writer please refer to its user manual
161. 2 bits of Address The 2 1 4 Access to External Memory is added Table 2 1 4 Table 2 1 6 Table 2 1 8 8 bit Data Write WEH Note Pages 68 70 and 72 are changed to pages 69 71 and 73 1 Table 2 1 4 Table 2 1 6 Table 2 1 8 8 bit Data Write WEH Note Pages 69 70 are changed to pages 70 71 1 A23 0 Note Pages 71 and 72 are changed to pages 72 and 73 A22 8 Table 2 1 9 Address Data Separate Mode 16 bit Bus DRAM UCAS and LCAS Method Note Page 73 is changed to page 74 Table 2 1 9 Address Data Separate Mode 16 bit Bus Burst ROM Access Definition A Add D Delete Table 2 1 10 Address Data Separate Mode 8 bit Bus DRAM UCAS and LCAS Method C Change Page 1 Table 2 1 10 Address Data Separate Mode 8 bit Bus Burst ROM Access Former Version MN102H55D 55G F55G User s Manual Record of Changes Ver 1 1 to Ver 2 0 New Version The RE short mode and the RE late mode do not affect the BSTRE pin connecting burst ROM The 2 4 Activation Sequence is added Normally the program generates the interrupt start address and then branches to that address After the program branches to x 080008 the program generates the interrupt service routine start address and then branches to that address The watchdog interrupt is used to detect the CPU errors The CPU cannot return to the previous operati
162. 2 by 2 set the timer 0 base register TMOBR tol The valid range for TMOBR is 0 to 255 TMOBR 00 10 TMO BR7 TMO BR4 TMO BR3 TMO BR2 TMO TMO BRO 0 0 0 0 0 0 0 1 3 Load value to the timer 0 binary counter At the same time select BOSC 2 as the clock source TMOMD x 00FE20 7 6 5 4 3 2 1 0 TMO TMO TMO TMO EN LD 51 50 0 1 0 0 4 Set TMOLD to 0 and TMOEN to 1 This starts the timer Counting begins at the start of the next cycle When the timer 0 binary counter TMOBC reaches 0 and loads the value from the base register at the next count a timer 0 underflow interrupt request will be sent to the CPU Timer 4 Timer 5 Settings 5 Verify that timer counting is stopped with the timer 4 mode register TM4MD and the timer 5 mode register TM5MD TMAMD x 00FE24 7 6 5 4 3 2 1 0 TM4 TM4 TM4 TM4 EN LD 51 50 0 TMSMD x 00FE25 7 6 5 4 3 2 1 0 TMS 5 TMS 5 EN LD 51 50 0 6 Enable interrupts after clearing all existing interrupt requests do this set KILV 2 0 of the external key interrupt control register to interrupt level to 6 set TMSIR to 0 TMSIE to 1 TMAIR to 0 and to 0 Thereafter an interrupt will be generated whenever timer 5 underflows
163. 3 2 1 0 PLUS PLU4 PLU3 PLU2 PLUI PLUO R R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 on 50 Port A Pullup Resistor 0 Off 1 On 7 6 5 4 3 2 1 0 reserv ed ed ed PLUI PLUO R R R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 on on 4 2 Reserved Set to 0 1 0 Port B Pullup Resistor 0 Off 1 On 488 MN102H55D 55G F55G P8PLU x OOFFBS8 Port 8 Pullup Control Register 8 bit access register P8PLU controls the port 8 pullup resistor P9PLU 00 9 Port 9 Pullup Control Register 8 bit access register P9PLU controls the port 9 pullup resistor PAPLU x OOFFBA Port A Pullup Control Register 8 bit access register PAPLU controls the port A pullup resistor PBPLU x OOFFBB Port Pullup Control Register 8 bit access register PBPLU controls the port B pullup resistor OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUTI OUTO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 70 PortO Output 0 Output low 1 Output high OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUTI OUTO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0
164. 3 6 V 0V C to 85 C Capacitance Parameter Symbol Conditions Fw m Input Pins lt Input CMOS level schmidt trigger gt NMI MODE RST Vpp 3 6 V OSCI pin pin at external clock input crystal ceramic self excited oscillation See Figure 1 4 10 to Figure 1 4 11 me PER w Pin Capacitance epe Input output pin MN102H55D 55G F55G 315 Chapter 11 Appendix 316 MN102H55D 55G F55G D A D Converter Characteristics Vpp AVDD 3 3 V Vss AVss 0 V 25 Capaian Parameter Symbol Conditions Unit epe ED eee aid ee ae Zero scale transition voltage ipe dd REF 0 V REF 3 3 V 2 oe di REF 10 lt lt lt lt lt lt emm ect s pe apee eeta ese e PI lt lt Note 1 Always set in relation of VDD gt AVDD gt VREF gt VREF gt AVSS gt VSS D A Converter Characteristics Vpp AVDD 3 3 V Vss AVss 0 Ta 25 C Parameter Symbol Conditions Unit _ ee VREF 3 3 V VREF 3 3 r PET L el pi voltage pin 10 10 ee Pet leakage current Note The capacitance values of E2 are operational under VDD VREF 3 3 V Vss VREF 0 V Chapter 11 Appendix MN102H55D 55G F55G 317 Chapter 11 Appendix 318 MN102H55D 55G F
165. 46 w A22 P46 AN6 STOP L ADSEP 81 45 A21 P45 AN5 RST 82 44 4 A20 P44 AN4 83 43 VREF DO 84 42 gt A19 P43 D1 85 MN1 02H55D 41 gt A18 P42 86 40 4 17 41 eae MN102H55G er do Pm MN102HF55G x Ais D5 lt 89 07 91 35 12 Vss 92 34 F 4 P10 TM8IOB 93 11 11 lt 94 32 10 P12 TM11IOA 3 95 31 gt A9 P13 TM11IOB 96 30 8 P14 TM11IC 97 29 7 P15 TM121OA 3 98 o 28 P16 TM12IOB 99 27 17 121 lt 100 26 4 U e S n e r M m tD Q Q m lt 2 0 q Q G O El e posopospe228 52R52292908 77 ta o m m 69 BE a BRB c m Sag 5 a c 19 le a Use 33 50 Figure 1 4 6 Pin Configuration in Processor Mode with 8 bit Bus Address Data Separate Mode Unused pins require handling in the circuit input pins are connected to VDD VSS output pins leave Open input output pins are connected to VDD VSS or leave open depending on pin direction setting 18 MN102H55D 55G F55G 1 4 7 Processor Mode with 16 bit Bus Address Data Separate Mode Chapter 1
166. 55G F55G 9 1 9 1 1 The MN102H55D 55G F55G generates a NMI interrupt before execut ing the instruction located on an arbitrary address The MN102H55D 55G F55G has two registers of the address break 0 address pointer and the address break 1 address pointer specifying the address where an in terrupt is generated When the address of the instruction fetch matches the address of either the address break 0 address pointer or the address break 1 address pointer the CPU generates a NMI interrupt by replac ing its instruction code into the undefined instruction x FF This func tion can debug the software or correct mask ROM under the production process x 800FE x800FF x 80100 x 80101 80102 Address Break Overview Address Break Instruction Fetch CPU Address Pointer Address Bus Register Comparison Circuit Address Bus Y ROM RAM Peripheral Register Address Break Control Register Match gt x FF Generator Valid Circuit Data Bus Instruction Code Figure 9 1 1 Address Break Operation Example Memory Space First address of the next instruction Instruction 1 Instruction 1 Instruction Address Break 0 Instruction 2 Instruction 2 NMI Interrupt break 0 address pointer or 80100 Address Pointer Register Address Break 1 80200 Address Pointer Regis
167. 57 P90 y o General purpose Port 90 This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports TM8IOA Timer 8 Input Output This pin can be used as a timer 8 input output pin Refer to Chapter 4 Timers BIBT1 Output Internal System Clock Refer to Pin 18 BIBT1 Description for details Output Refer to Chapter 5 Serial Interface DMAREQ1 Input Activation Request This pin is an ETC activation request pin When ETC Input starts the data is transferred automatically between the external memory and the external device which requires no address specification Refer to Chapter 7 ATC ETC 58 P91 yo General purpose Port 91 This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports 10 Timer 10 Input Output This pin can be used as a timer 10 input output pin Refer to Chapter 4 Timers BIBT2 Output Internal System Clock Refer to Pin 18 BIBT1 Description for details Output Refer to Chapter 5 Serial Interface DMAACK1 Output ETC1 Acknowledge This pin is an acknowledge signal output pin for ETC acti Output vation request Refer to Chapter 7 ATC ETC 44 MN102H55D 55G F55G Chapter 1 General Description Table 1 4 1
168. 6 5 4 3 2 1 0 1 MDO BW DB8 DI SB8 SI 1Q3 IQ2 1101 100 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 ATC Activation Factor Settings Software initialization DMAREQO pin input External interrupt 0 External interrupt 1 External interrupt 4 Timer 3 underflow interrupt Timer 7 underflow interrupt Timer 9 underflow interrupt Timer 10 capture A interrupt Timer 11 capture A interrupt Serial 0 transmission end interrupt Serial 0 reception end interrupt Serial 3 transmission end interrupt Serial 3 reception end interrupt A D conversion end interrupt Key interrupt Note This example is ATCO Please refer to List of Registers for ATC1 ATC3 settings ATnSI Increment Control Flag for Source Address Pointer Fixed Increment by 1 in the byte transfer by 2 in the word transfer ATnSB8 Source Bus Width 0 16 bit 8 bit only when 8 bit bus width for external memory is selected Increment Control Flag for Destination Address Pointer Fixed Increment by 1 in the byte transfer by 2 in the word transfer ATnDB8 Destination Bus Width 0 16 bit 8 bit only when 8 bit bus width for external memory is selected Transfer Unit 0 Word disable whe
169. 6 5 4 3 2 1 0 TMOU TMOU IR ID R R R R W R R R R 0 0 0 0 0 0 0 on o 0 1 4 Timer 0 Underflow Interrupt Request Flag 0 Timer 0 Underflow Interrupt Detect Flag 7 6 5 4 3 2 1 0 2 TMOU IE R R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 0 Underflow Interrupt Enable Flag 346 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected 0 Disable 1 Enable TMOUICL x 00FC52 Timer 0 Underflow Interrupt Control Register 8 bit access register TMOUICL requests and verifies a timer 0 interrupt This register allows only byte accesses Use MOVB instruc tion to set the data TMOUICH x 00FC53 Timer 0 Underflow Interrupt Control Register 8 bit access register TMOUICH enables a timer 0 terrupt This register allows only byte accesses Use MOVB instruc tion to set the data The inter rupt level is the same level set in the IQOLV 2 0 bits of the IQOICH register Chapter 11 Appendix owe DUE died pe TMS8UICL 00 54 Timer 8 Underflow 0 Interrupt Control Register 8 bit access register Timer 8 Underflow Interrupt 0 No interrupt requested TMB8UICL requests and verifies Request Flag 1 Int
170. 7 6 5 4 9 2 1 0 ET1DST sets the transfer desti nation address When the desti nation pointer increment bit is set to be fixed the transfer source address do not change When the source pointer incre ment bit is set to increment in crement by 1 in the byte transfer and by 2 in the word transfer DST23DST22DST21 DST20DSTI9DSTI8DSTI7DST16 R W R W R W R W R W R W R W R W undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 This register writes only 24 bit data or 16 bit data Use the MOV instruction or the MOVX instruction to set the data MN102H55D 55G F55G 415 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCOCTR SCO SCO SCO SCO SCO SCO SCO SCO SCO Sco SCO REN BRE ed ed OD ed LN PTY2 PTY1 PTYO SB 51 50 x 00FD80 R W R W R W R W R W R R W R W R W R W R W R W R W R R W R W Serial 0 Control Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o on 16 bit access register
171. 75 2 4 2 0 1 MER 75 Handshake Wait Control 80 2 3 1 OVEIVIOW 80 Activation Sequence 82 2 4 1 Activation Sequence of Each Mode 82 Chapter3 Interrupts 3 1 3 2 Interr pt Group Siae n etate e i nr uqu asiy hani 84 3 1 1 QU NE 84 3 1 2 Control 88 Interrupt Setup Examples 94 3 2 1 External Pin Interrupt Setup Examples 94 3 2 2 Key Input Interrupt Setup Examples 96 3 2 3 Watchdog Timer Interrupt Setup Examples 1 100 3 2 4 Watchdog Timer Interrupt Setup Examples 2 102 Chapter4 Timers 4 1 4 2 4 4 Summary of 8 bit Timer Functions 106 4 1 1 e tr eee a ee unes 106 4 1 2 8 bit Timer Control Registers 110 4 1 3 8 bit Timer Block Diagrams see 112 8 bit Timer Setup Examples sss 116 4 2 1 Event Counter Using 8 bit Timer 116 4 2 2 Clock Output Using 8 bit Timer 119 4 2 3 Interval Timer Using 8 bit Timer 122 Summary of 16 bit Timer Functions 2 126 4 3 1 GNI EE 126 4 3 2 1
172. 8 8 TM8 EN NLD UDI UDO TGE ONE MDI MDO ECIR LP ASEL 52 51 SO 0 0 0 0 0 0 1 0 0 0 100 0 1 1 2 Set TM8NLD TM8EN of TM8MD to 1 and 0 respectively This enables TM8BC and RS F F 3 Set TM8NLD and TM8EN to 1 This starts the timer Counting begins at the start of the next cycle Interrupt Enable Setting 4 Enable interrupts after clearing all prior interrupt requests To do this set IQOLV 2 0 of the external interrupt 0 control register IQOICH to the interrupt level 0 to 6 TM8BIR of the timer 8 capture B interrupt control register TM8BICL to 0 and TM8BIE of the timer 8 capture B interrupt control register TM8BICH to 1 Thereafter a timer 8 capture interrupt occurs when the cap ture to the TM8CB register is generated on the rising edge of TM8IOA pin Interrupt Processing and Signal Width Calculation 5 Execute the interrupt service routine The interrupt service routine determines the interrupt group and factor and clears TM8BIR flag 6 Calculate the signal width Save the TM8CA value and the TM8CB value to the data registers DRO to DR3 and subtract the TM8CA value from the TM8CB value The width will be calculated correctly even if the TM8CA value is greater than the TM8CB value by setting TM8LP to 0 Figure 4 4 10 shows 000 0007 0003 or 3 cycles Chapter 4 Timers Timer 8 functions as a one phase capture input Select up counting Timer 8 does not operate stably w
173. 9 Input Signal Vppx0 9 Voox0 9 Vppx0 1 x 1 Voox0 17 Pulse Width High Pulse WidthLow 1 gt 4 gt Fall Time Rise Time Cycle Time 1 r gt I i Output Signal 0 9 Voox0 9 Voox0 9 Voox0 1_7 Voox0 1 Voox0 1 7 Pulse Width High Pulse Width Low 1 i 1 A DE Fall Time Rise Time 0 5 Output Signal Delay Time Vppx 0 5 Both setup time and hold time are 0 5 MN102H55D 55G F55G Chapter 11 Appendix 1 Fosdl 1 gt lt gt gt We q lt gt BC N Z gt A gt x p q p q iR Figure 11 1 1 System Clock Timing RST Figure 11 1 2 Reset Timing vee fe VDD VEND lt Note Figure 11 1 3 Voltage Rise Timing Note VDD VPP setup time tvDP is the capacitance value only for MN102HF55G MN102H55D 55G F55G 327 Chapter 11 Appendix BOSC A23 A00 CS3 CS0 read D15 D00 RE Late 0 5 short 0 mode lt write gt D15 D00 WEH WEL Late 1 short 0 mode 328 MN102H55D 55G F55G tcSDF1 tREDF1 top1 gt WEDF1 twEPW Figure 11 1 4 Data Transfer Signal Timing Address Data Separate Without Wait Read Write
174. A14 A5 A14 A6 A13 A4 A13 5 12 12 4 11 2 11 A1 A10 A2 A9 AO A9 A1 D15 8 D15 8 07 0 07 0 70 RAS RAS P71 CAS CAS P61 RE OE P63 EH UWE P62 EL LWE Figure 2 1 4 DRAM 2WE Method Connection Example 16 bit Bus Width 11 10 9 8 EW EW EW EW EXWMD 23 22 21 20 0 1 0 0 15 14 13 12 11 10 9 8 2 6 4 3 2 1 0 MEMMDI 21 20 2 0 0 0 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 ARE AS SEL SEL SEL CAS CAS CAS RAS RAS RAS DRAMMDI 2 1 0 EN 2 1 0 1 0 2 1 0 1 0 0 1 0 1 0 1 1 0 0 1 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 DRAM DRAM R RCY RCY RCY RCY RCS RCS RCS RRS RRS RRS DRAMMD2 ON 3 2 1 0 1 0 2 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 7 6 2 4 3 2 1 0 POMD MD1 0 1 7 6 3 4 3 2 1 0 Pl PIEMD LMDI LMDO 0 1 7 6 9 4 3 2 1 0 7 6 2 4 3 2 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3HMD HMD7 HMD6 HMD5 HMD4 HMD3 HMD2 HMDI HMDO P3LMD LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 0 1 0 1 0 1 0 1 0 1 0 0 1 7 6 3 4 3 2 1 0 P4 P4 P4 LMD2 LMD I LMDO 1 1 1 7 6 5 4 3 2 1 0 P6 P6 P6 P6MD MDS MD4 MD3 1 1 1 7 6 5 4 3 2 1 0 P7 P7 P7 P7 P7 LMD4 LMD3 LMD2 LMDI LMDO 1 1 1 0 1 64 MN102HF55G H55G H55D Example
175. ATO SRCISSRCIASRCI3SRCI2SRCIISRCIO SRC9 SRC8 SRC7 SRC6 5 5 SRC4 SRC3 SRC2 SRC1 SRCO x 00 FD04 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W ATC 0 Sou rce undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address Pointer 16 24 bit access register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATOSRC sets the transfer source address When the source pointer increment bit is set to be fixed the transfer source address do not change When the source pointer incre ment bit is set to increment in crement by 1 in the byte transfer and by 2 in the word transfer SRC23SRC22SRC2ISRC2OSRCIO9SRCISSRCIT7SRCI R W R W R W R W R W R W R W R W undefined undefined undefined undefined undefined undefined undefined Jundefined 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 This register writes only 24 bit data or 16 bit data Use the MOV instruction or the MOVX instruction to set the data MN102H55D 55G F55G 399 Chapter 11 Appendix
176. Address Output COL Address Output P P46 A22 A11 A11 10 10 bit P45 21 A10 A10 P44 A20 Lo A10 11 Reserved P43 A19 Lo A9 P42 18 5 AQ A8 P41 A17 A8 40 16 A8 A7 P37 A15 A7 A6 A5 P36 A14 A6 A5 A4 35 A13 5 A4 A3 P34 12 A4 A3 A2 P33 11 2 A1 P32 A10 A2 A1 AO P31 AQ Al AO A0 P30 A8 AO 9 Shift Setting from Row 0 Dont shift addresses of AD15 ADO pins 1 Shift to Column addresses 8 6 Shift Timing Setting from Row 000 At the beginning of 0 5 cycle Address to Column Address 001 At the beginning of 1 0 cycle 010 At the beginning of 1 5 cycles 5 3 Timing Setting of CAS Falling 011 At the beginning of 2 0 cycles Edge 100 At the beginning of 2 5 cycles 101 At the beginning of 3 0 cycles 2 0 Timing Setting of RAS Falling 110 At the beginning of 3 5 cycles Edge 111 At the beginning of 4 0 cycles 478 MN102H55D 55G F55G 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRAMDRAM reserv RON RCY RCY RCY RCS RCS RCS RRS RRS RRS ACC TM ed ed ed 3 2 1 0 2 1 0 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 DRAM Access Method Selection 14 Clock Source Selection for DRAM Refresh 13 11 Reserved 10 DRAM Refre
177. CNT2 CNTI CNTO R R R R R W R W R W R W R W R W R W 0 0 0 0 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATI ATI ATI ATI ATI ATI ATI ATI ATI ATI ATI SRCISISRCIASRCI3SRCI2SRCIISRCIO SRC9 SRC8 SRC7 SRC6 5 5 SRC4 SRC3 SRC2 SRCI SRCO R W R W R W R W R W R W R W R W R W R W R W undefined undefined undefined Jundefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATI ATI ATI ATI ISRC23SRC22SRC2ISSRC20SRCIO9SRCISSRCIT7SRCI R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 402 MN102H55D 55G F55G AT1CNT x 00FD12 ATC 1 Transfer Word Count Register 16 bit access register AT1ONT sets the bytes to be transferred subtracted by 1 Decrement by 1 every time 1 byte data
178. CPU mode control regis ter CPUM to enable 07 after reset When the watchdog timer overflows a nonmaskable interrupt occurs This requires to clear the watchdog timer in the main program PO CORE D A Converter P6 P1 L Interrupt A D Converter P7 P2 8 bit Timers Serial 8 P3 16 bit Timers ATG P9 8 bit PWM P5 Pulse Width Counter ROM Figure 3 2 6 Watchdog Timer Interrupt Block Diagram Interrupt Enable Setting 1 Clear the WDRST flag of the CPUM register This starts the watchdog timer In addition set the WDM flags to the time for error detection function CPUM x 00FCOO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WD WD WD 0 ISSC sropiHALriosci osco RST MO ID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Clearing the Watchdog Timer 2 Set the WDRST flag of the CPUM register to 1 and then immediately clear it to 0 The watchdog timer clears to 0 when the WDRST flag is 1 Interrupt Service Routine When an interrupt is generated and accepted the program branches to x 080008 3 Specify the interrupt group by reading the IAGR register during interrupt prepro cessing 4 Verify a watchdog interrupt by reading the watchdog interrupt control register WDICR Check the
179. Conditions Vss 0 V Ta 40 C to 85 C Parameter Symbol Conditions Unit External Clock Input Timing Fosc1 34 MHz external clock input high pulse Ue External clock input low pulse width Reset Input Timing Reset signal pulse width RST Fig 11 1 2 GHEHE Power Rise Timing 2 Note VDD VPP setup time tvpP is the capacitance only for MN102HF55G 3 0 V to 3 6 V Input Timing Conditions Vss 0 V 40 C to 85 Capacitance Parameter Symbol Conditions Data Transfer Signal Input Timing Data acknowledge signal setup time WAIT F8 Fig 11 1 5 9 F Fig 11 1 4 data setup time 015 00 Fig 11 1 5 Flg 11 1 6 ORE Fig 11 1 8 Read data hold time D15 00 Fig 11 1 9 Fig 11 1 10 Tes pare Nonmaskable interrupt signal pulse width NMI Fig 11 1 13 Note io M pulse width gt Note An interrupt may occur when the noise of the specified time or less is input SRE means RE short mode Sre 0 0 5 1 1 5 tws Data acknowledge signal hold time fe Fig 11 1 9 WAIT Data Transfer Signal Input Timing Chapter 11 Appendix MN102H55D 55G F55G 303 Chapter 11 Appendix Voo 3 0 V to 3 6 V Input Timing Conditions Vss 0 V E 40 C to 85 C Capacitance Pa
180. Control 0 1 0 0 HALTO On OSCI 0 0 1 1 1 HALTI On XI 1 1 0 0 0 STOPO Off 1 0 1 1 STOPI Off The following describes programming rules and precautions in the STOP HALT mode Points for Programming 1 Setting the CPUM address in the address register in advance set the CPUM register using the MOV instruction with the register indirect addressing mode 2 Immediately after the MOV instruction locate three NOPs consecutively 3 Immediately before the MOV instruction locate the JMP instruction and align to the even address This avoids the effects by the differences of the bus widths in the memory mode or expansion mode and provides the same result when operating in any conditions Programming Coding Example in Assembler as 102Ver 1 0 Ver 2 0 MOV CPUM AO Set AO to the CPUM address MOV A0 DO Transfer the contents of CPUM to DO OR x 000 DO Generate the data to set the STOP HALT mode JMP STP HLT Branch unconditionally to the even address to ALIGN 2 eliminate the difference of operating conditions STP HLT MOV DO A0 Set the STOP HALT mode to CPUM NOP Dummy NOP Dummy NOP Dummy Precautions 1 of OR instruction varies depending on the STOP or HALT mode 2 Set the ALIGN value to 2 or more in the above file when the ALIGN value is set using SECTION dummy instruction before this programming coding is described 3 Code the above programming in another file of the asse
181. D Converter P7 SBIO P71 P2 8 bit Timers Serial P8 P3 16 bit Timers ATC P9 P4 8 bit PWM ETC PA P5 Pulse Width Counter ROM RAM PB Interrupt Service Routine dataJ Interrupt Service Routine dataA H dataB HdataC H dataE dataF HdataGHdataH H datal Receive the 5 byte data 0 8000 dataA Receive the next 5 byte and store each byte data 0 8001 dataB data and stores each on the memory 0 8002 dataC byte data on the memory 0 8003 dataD 0x 8004 dataE ae Figure 7 2 2 Serial Reception Sequence 0 8000 0x 8001 0 8002 0 8003 0 8004 dii dataF dataG dataH datal dataJ MN102H55D 55G F55G Chapter 7 ATC ETC 237 Chapter 7 ATC ETC ATC Setup 1 Set the address x O0FD82 of the serial 0 reception buffer to the ATCO source address pointer ATOSRC ATOSRC x 00FD04 The space for 5 bytes is from 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRCIS SRCIAISRCIS SRCDZ2 SRCII1 SRCIOSSRC9 SRC8 SRC7 SRC6 SRCS5 SRCA SRC3 SRC2 SRCI SRCO 1 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 15 14 13 12 11 10 9 8 7
182. DRAM in processor mode or memory expansion mode Refer to 2 1 Summary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state This pin can be used as a general purpose input output port if itis not used as RAS in single chip mode processor mode or memory expansion mode The input output direc tion is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports This pin can be used as a synchronous transfer clock sig nal input output pin for serial interface 0 if it is not used as RAS in single chip mode processor mode or memory ex pansion mode Refer to Chapter 5 Serial Interface 68 CAS LCAS P71 SBIO Output Output Input DRAM Control Output DRAM Control Output General purpose Port 71 Serial Interface 0 Data Input This pin outputs CAS or LCAS signal when connecting DRAM in processor mode or memory expansion mode Refer to 2 1 Summary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state This pin can be used as a general purpose input output port if it is not used as CAS or LCAS in single chip mode pro cessor mode or memory expansion mode The input output direction is controlled in bit units The pin has a built in soft ware control pull up resistor Refer to Chapter 8 Ports This pin can be used as a data input pi
183. Disable 1 Enable Chapter 11 Appendix SC3TICL x OOFC9C Serial 3 Transmission End Interrupt Control Register 8 bit access register SC8TICL requests and verifies a serial 3 transmission end inter rupt This register allows only byte accesses Use the MOVB in struction to set the data SC3TICH x OOFC9D Serial 3 Transmission End Interrupt Control Register 8 bit access register enables a seial transmission end interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the SC2TLV 2 0 bits of the SC2TICH register MN102H55D 55G F55G 381 Chapter 11 Appendix 7 6 5 4 3 2 0 SCoR SC3R IR ID R R R R W R R R 0 0 0 0 0 0 0 on o 0 1 4 Serial 3 Reception End 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 0 Serial 3 Reception End 0 Interrupt undetected Interrupt Detect Flag 1 Interrupt detected 7 6 5 4 3 2 0 SC3R IE R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 1 0 Serial 3 Reception End 0 Disable Interrupt Enable Flag 1 Enable 382 MN102H55D 55G F55G SCS3RICL x 0O0FC9E Serial 3 Reception End Interrupt Control Register 8 bit access register SC3RICL requests and verifies seial 3 reception end interrupt This register allows only byte acces
184. Disable Enable 1 Start counting on the falling edge of pin 8 Counter Operating Mode 0 Repeat 1 One shot counting During repeat counting hold the Selection TM11EN flag state During one shot counting set the TM11EN i fl to 0 wh TM11BC 7 6 11 TM11CB Operating 00 Compare register single buffer I 1 A aro Mode Selection 01 Compare register double buffer 10 Capture A when pin is high Capture B when TM111OA pin is low 11 Capture A when TM111OA pin is high Capture B when TM111OB pin is high 5 TM11BC Clear 0 Don t clear 1 Clear when external synchronization is used 4 TM11BC Count Range 0 0to FFFF 1 0to TM11CA 3 TM111OA Pin Output 0 RS F F output one phase PWM 1 T F F output two phase PWM 2 0 Source Selection 000 Timer 0 underflow The TM10IOB pin edge is set in 001 Timer 4 underflow the TM10MD2 register 010 TM111OB pin 011 BOSC 2 100 Two phase encoder 4x of TM11IOA pin TM111OB pin 101 Two phase encoder 1x of TM11IOA pin TM111OB pin 452 MN102H55D 55G F55G Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM12MD TM12 TM12 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 x OOFECO EN NLD UDO TGE ONE MD1 ECLR LP ASEL S2 51 50 R W R W R R W R W R W R W R W R W R W R W R W R W R W R W Timer 12 Mode Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
185. Dn JMP label16 2 BSET Dm An 3 BCLR Dm An MOVB Di An Dm MOVBU Di An Dm MOVB Dm Di An MN102H55D 55G F55G 545 Chapter 11 Appendix Extended Code B Second byte Byte 1 F1 Second byte Upper Lower 0 1 2 3 4 5 6 7 8 9 A B Di Am MOV Di Dm MOV Di An MOV Dm Di An Extended Code C Second byte Byte 1 F2 Second byte Upper Lower 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 ADD Dm An 1 SUB Dm An 2 CMP Dm An 3 MOV Dm An 4 ADD An Am 5 SUB An Am 6 CMP An Am 7 MOV An Am 8 ADDC Dn Dm 9 SUBC Dn Dm ADD Dm D SUB An Dm 546 MN102H55D 55G F55G Extended Code D Second byte Byte 1 F3 Second byte Chapter 11 Appendix Upper Lower 0 1 2 3 4 5 6 7 8 9 0 AND Dn Dm 1 OR Dn Dm 2 XOR Dn Dm 3 ROL Dn 4 MUL Dn Dm 5 MULU Dn Dm 6 DIVU Dn Dm 7 8 9 CMP Dn Dm A B Dn MOV PSW code Extended Code E Second byte Byte 1 F4 Second byte Upper Lower 0 1 2 3 4 5 6 0 MOV Dm d24 An 1 MOV 424 An 2 MOVB 424 An 3 MOVX Dm d24 An 4 MOV Dn abs24 MOVB Dn abs24 BSET imm8 abs24 BCLR
186. E3 Be ze ES tn m zz zo EL zc zz So EL a a m o t o t o 5 2 2 5 2 5 2 5 2 5 2 5 5 2 60 9 5 2 60 9 5 2 2 9 5 Z 0 9 UR aba apana esent L AE ERE AERE ET o 2 dina setas ua ss eden anl EE E a k ir t ELI Ses ee A RR VON AU ERES Plage eo Bee PG RE So ERU POR iS EVE CO OP 3 85 g BP S g g g 9 amp F u lt u ue 4 we we we m m T8 Fy 55 2 gt mme 2 129 E m m E as S OF E lt a d d lt d lt i d lt lt 5 iac 9 E gt s x 2 i 8 2 2 o 9 2 d 9 a o m p m 9 5 o 3 lt 77 MN102HF55G H55G H55D Chapter 2 Bus Interface Table 2 2 4 RE Late and Short Modes Address Data Separate Mode Late Mode Short Mode Base Clock Bosc TE EI BOSC i ft Binnie
187. End 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 0 Serial 2 Reception End 0 Interrupt undetected Interrupt Detect Flag 1 Interrupt detected 7 6 5 4 3 2 0 SC2R IE R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 1 0 Serial 2 Reception End 0 Disable Interrupt Enable Flag 1 Enable 380 MN102H55D 55G F55G SC2RICL x 0O0FC9A Serial 2 Reception End Interrupt Control Register 8 bit access register SC2RICL requests and verifies a seial 2 reception end interrupt This register allows only byte accesses Use the MOVB in struction to set the data SC2RICH x 00FC9B Serial 2 Reception End Interrupt Control Register 8 bit access register SC2RICH enables a serial 2 re ception end interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the SC2TLV 2 0 bits of the SC2TICH register 6 5 4 3 2 1 0 SC3T SC3T IR ID R RW R R 0 0 0 0 0 0 0 0 0 1 0 0 0 Serial 3 Transmission End Interrupt Request Flag Serial 3 Transmission End Interrupt Detect Flag 6 5 4 3 2 1 0 SC3T IE R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 Serial Transmission End Interrupt Enable Flag 0 No interrupt requested 1 Interrupt requested 0 Interrupt undetected 1 Interrupt detected 0
188. General Description Zoic SE ag Yo lt ot n na lt lt 0 lt gt m Eo lt 2 a m Om mos HHA 295 5 00 enr 555990 O E OSSE aan OR 2 2 222 gt gt gt gt 1 sx N ok O O O P PF P Por F O O O O PAO IRQO gt 76 50 w P82 TMOIO SBT3 SCL3 SBI2 PA1 IRQ1 lt 77 49 w P81 DAC1 PA2 IRQ2 lt 78 48 a P80 DACO PA3 IRQ3 79 47 lt A23 P47 AN7 WDOUT PA4 IRQ4 TM15IB 4 gt 80 46 gt A22 P46 AN6 STOP a 81 45 w A21 P45 AN5 RST 82 44 lt A20 P44 AN4 83 43 VREF DO 84 42 4 A19 P43 Sed e MN102H55D 02 lt 86 40 4 17 41 03 87 MN102H55G 39 gt A16 P40 4 MN102HF55G e S 05 89 37 A14 VIEW s 07 91 35 12 Vss 92 34 w 08 93 33 11 D9 94 32 A10 010 lt 95 31 A9 011 lt 96 30 gt A8 012 lt 97 29 A7 013 98 28 014 lt 99 27 5 015
189. H P8PLU x O0FFBS8 Port 8 Pull up Control Register P8OUT 00 8 Port 8 Output Register P8IN x O0FFDS Port 8 Input Register P8DIR x O0FFES Port 8 Input Output Control Register P8LMD x O0FFFC Port 8 Mode Register L P8MMD x O0FFFD Port 8 Mode Register M P8HMD x O0FFFE Port 8 Mode Register H POPLU 00 9 Port 9 Pull up Control Register P9OUT x O0FFCO Port 9 Output Register P9IN x 0OFFD9 Port 9 Input Register P9DIR 00 9 Port 9 Input Output Control Register P9LMD Port 9 Mode Register 9 x 00FFED Port 9 Mode Register H PAPLU x 00FFBA Port A Pull up Control Register PAOUT x 00FFCA Port A Output Register PAIN x O0FFDA Port A Input Register PADIR x O0FFEA Port A Input Output Control Register PAMD x 00FFDC Port A Mode Register PBPLU x O0FFBB Port B Pull up Control Register PBOUT Port Output Register PBIN x O0FFDB Port B Input Register PBDIR x O0FFEB Port B Input Output Control Register PBMD x O0FFDD Port B Mode Register Chapter 8 Ports MN102H55D 55G F55G 263 Chapter 8 Ports 8 1 3 Port Block Diagram The MN102H55D 55G F55G contains twelve I O ports of PO to PB set consists of two ports to eight ports Each pin serves as a general purpose port function or an input output function for each peripheral function The function can be switched by each port mode register When the input output pin of the peripheral function is select
190. Linear Addressing for Large Systems The MN102H series contains up to 16 Mbytes of linear address space The CPU does not detect borders between address spaces which provides an effective development environment The hardware architecture is also optimized for large systems The memory is not divided into instruction areas and data areas so that operations can share instructions Chapter 1 General Description 3 Single byte Basic Instruction Length Conventional Register Assignment 15 r 0 The MN102H series has replaced general registers with eight internal Register Specification Field CPU registers divided four address registers A0 A3 and four data reg isters 20 03 The register specification fields are four bits less and 7 0 the code size of the basic instructions including register to register opera His ca dic tions and load store operations is one byte New Register Assignement 4 High speed Pipeline Processing 1 Machine Cycle Instruction 1 Fetch gt Decode The MN102H series executes instructions in a 3 stage pipeline fetch Address Execute decode execute This allows the MN102H series to execute instruc tions of single byte in one machine cycle Instruction 2 Fetch gt Decode Address Calculation Ep 5 Simple Instructio
191. MN102H55D 55G F55G 331 Chapter 11 Appendix tcvc tcvc i m A23 A16 e ALE Long 0 Late 0 mode Address AD1 tAH1 tcspr1 4 tcsH 1 lt Read gt lt 8 bit Bus Mode gt AD15 AD8 AD long 1 mode Address AD7 ADO A AD long 1 mode aisi lj lt 16 bit Bus Mode gt AD15 ADO Late 1 short 0 mode Address Late 0 5 short 0 mode lt Write gt tREDR1 lt 8 bit Bus Mode gt AD15 AD8 A AD long 1 mode ddress AD7 ADO AD long 1 mode ddress lt 16 bit BUS Mode gt AD15 ADO A Late 1 short 0 mode lt M gt E WEDF1 Adress WEH WEL Late 0 5 short 0 mode Figure 11 1 8 Data Transfer Signal Timing Address Data Shared Without Wait Read Write 332 MN102H55D 55G F55G Chapter 11 Appendix 2 W 1 W the number of waits 1 5 2 2 5 7 tcvc tcvc tcvc tcvc gt lt gt lt z lt BOSC TcL AD23 AD16 Address Rand 01 e tapi CS3 CS0 CSDR1 WAIT N tws ALE gt Late 0 long 0 mode TALERI lt Read gt Js E 8 bit Bus Mode gt ne AD15 AD8 Address AD long 1 mode tapi AD7 ADO Address Dat AD long 1 mode lapi 80 lt 16 bit Bus
192. NMI MN102H55D 55G F55G 493 Chapter 11 Appendix J 6 5 4 3 2 1 0 P8 P8 P8 P8 P8 P8 P8 P8 IN7 ING INS IN4 IN3 IN2 INI INO R R R R R R R R Port Port Port Port Port Port Port Port 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 70 Port8 Input 0 Input low 1 Input high 7 6 5 4 3 2 1 0 P9 P9 P9 P9 P9 P9 P9 P9 IN7 ING INS IN4 IN3 IN2 INI INO R R R R R R R R Port Port Port Port Port Port Port Port 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 70 Port9 Input 0 Input low 1 Input high 7 6 5 4 3 2 1 0 PA PA IN5 4 IG IN2 INI INO R R R R R R R R 0 0 Port Port Port Port Port Port 0 0 0 0 0 1 0 1 0 1 0 1 5 0 Port A Input 0 Input low 1 Input high 7 6 5 4 3 2 1 0 reserv PB PB ed ed INI INO R R R R R R R R 0 0 0 Port Port 0 Port Port 0 0 0 0 1 0 1 0 0 1 0 1 1 0 Port B Input 0 Input low 1 Input high 494 MN102H55D 55G F55G P8IN x OOFFDS8 Port 8 Input Register 8 bit access register P8IN reads the port 8 data P9IN x OOFFD9 Port 9 Input Register 8 bit access register 9 reads the port 9 data PAIN x OOFFDA Port A Input Register 8 bit access register PAIN reads the port A data PBIN
193. Other modes 10 Fig 11 1 4 to 6 ALE late 0 long 0 mode AD long 1 mode RE Read enable signal fall delay time 2 RE Fig 11 1 8 to 9 Other modes Fig 11 1 8109 REDF2 Late 1 mode Fig 11 1 4 to Write enable signal fall delay time 1 WEH WEL Other modes Fig 11 1 4t0 5 Fig 11 1 7 to 9 Late 1 mode x Fig 11 1 4 to 5 2W L S 2 Fig 11 1 7109 20 Other modes Fig 11 1 4 to 5 Fig 11 1 7 to9 Write enable pulse width time WEH WEL W is the number of waits W 0 0 5 1 1 5 7 L means WE late mode L 1 2 3 S means WE short mode S 0 0 5 1 1 5 3 0 V to 3 6 V Output Signal Characteristics Vss 0 V Ta 40 C to 85 C CL 70 pF Capacitance Parameter Symbol Conditions Unit oa Serial Interface Signal Output Timing Synchronous Serial Transmission Transfer data delay time SBO4 0 2 Transfer data hold time transfer in E Transfer data hold time Transfer end timing at SBT input Fig 11 1 15 tsch tsct Fig 11 1 16 5 SBO4 0 Note Set SBO4 0 output hold time to BOSC cycle or more in SCnCTR n 4 0 register G23 Transfer data hold time Transfer end timing at SBT output SBO4 0 Chapter 11 Appendix MN102H55D 55G F55G 309 Chapter 11 Appendix 310 MN102H55D 55G F55G 11 1 2 MN102HF55G CMOS integrated circuit
194. P6MD MN102HF55G SRAM 256 K 8bit Chapter 2 Bus Interface 1 50 CSO cs A18 0 A18 0 When connecting to mask ROM do not need to connect WEH D7 0 D7 0 and WEL P61 RE OE P62 EL WE Figure 2 1 3 SRAM Mask ROM Connection Example 8 bit Bus Width 5 4 12 d 0 9 8 7 6 5 4 3 2 1 0 EW EW EW EW 02 o 0 0 1 0 15 4 12 d 0 9 8 7 6 5 4 3 2 1 0 EB EB BRC 01 00 0 0 1 0 15 4 12 d 0 9 8 7 6 5 4 3 2 1 0 ARE 0 0 7 6 5 4 3 2 1 0 MDI 0 1 7 6 5 4 3 2 1 0 LMDI LMDO 0 0 7 6 5 4 3 2 1 0 P2 MDO 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 P3 p P3EMD HMD7 HMD6 HMD5 HMD4 HMD3 HMD2 HMDI HMDO LMD7 LMD6 LMDS LMDA LMD3 LMD2 LMDI LMDO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 P4 pa P4 LMD2 LMDI LMDO 1 1 1 7 6 5 4 3 2 1 0 Ps Ps LMDI LMDO 0 1 7 6 5 4 3 2 1 0 P6 P6 MD5 MD4 MD3 0 1 1 MN102HF55G H55G H55D 63 Chapter 2 Bus Interface Example of DRAM 2WE Method Connection 16 bit Bus Width 2 Wait MN102HF55G DRAM MN41V4170 256 K 16bit Row 10 Colum 8 A18 A9 A18 A17 A8 A17 A16 7 16 A8 A15 A6 A15 A7
195. P7 P7 P7 P7 P7 P7LMD LMD4 LMD3 LMD2 LMDI LMDO 66 MN102HF55G H55G H55D 2 1 4 Access to External Memory The MN102H55D 55G F55G can access to external memory The ex ternal memory space is divided into four areas When the MN102H55D 55G F55G accesses to each area the corresponded CSn pin n 0 to 3 outputs a chip select signal In addition the number of wait cycles and 8 bit or 16 bit bus width can be selected for each area The clock output from BOSC pin is the base clock at external access The address data or control signals output synchronizing with BOSC clock The BOSC clock fre quency is the same as the oscillation clock frequency input from OSCI pin For ex ample the BOSC clock frequency become 40 MHz with a 40 MHz external oscillator The clock input from OSCI pin and BOSC clock have the phase difference The BIBT or 2 is the internal clock synchronizing with BOSC clock it shows memory access cycle During 1 memory access first the BIBT2 clock becomes high level and then the BIBTI clock becomes high level When the number of wait cycles 15 set the BIBTI clock cycle being high level will be extended When no wait cycle is selected the BIBT2 clock cycle and the BIBTI clock cycle being high level equals 1 BOSC cycle The necessary cycle for 1 access should be 2 BOSC clock cycles Cycle Figure 2 1 7 External Access No Wait Cycle When the numb
196. P8MMD P8LMD P8MMD P8LMD x 00FFFC 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ps ps ps ps ps ps Ps PS ps P8 ps PB MMD7 MMD6 MMDS MMD4MMD3 MMD2 MMD1 MMDO LMD4 LMD3 LMD2 LMD LMDO 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 2 Set the serial 3 control register SC3CTR Select 8 bit character length PC ACK is set by the parity bits To output 1 to ACK select 1 by the parity bits To output 0 to select 0 by the parity bits output none to ACK select none protocol PC mode on The parity bit is set to 1 to enable both transmission and reception enable flags disable the break and set the ACK output to 1 SC3CTR x 00FD98 by the parity bits 5 3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 TEN REN BRE PTL OD ICM LN PTY2 PTYI PTYO SB 51 50 1 1 0 0 1 1 1 1 1 0 1 0 0 1 Start Sequence Transmission 3 Write 1 to the sequence output flag SC3IIC of the SC3CTR register This Enabling transmission detects sets the SDA3 pin output to low When the start sequence occurs correctly the fno start sequence detection flag SC3IST of the serial 3 status register SC3STR becomes 1 The arbitration lost detection cannot be performed even though the start sequence exists Data Transmission 1 4 Load th
197. R R R R R R R 0 0 0 0 0 O Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Chapter 11 Appendix x AN2BUF x OOFFOC AN2 Conversion Data Buffer 16 bit access register AN2 conversion data When 8 bit is selected as A D converter resolution the AN2BUF 7 0 bits hold the data and the AN2BUFT 9 8 bits be come 0 When 10 bit is se lected as A D converter resolu tion the AN2BUFT 9 0 bits hold the data ANS3BUF x OOFFOE AN3 Conversion Data Buffer 16 bit access register conversion data When 8 bit is selected as A D converter resolution the ANS3BUFT 7 0 bits hold the data and the ANSBUFT 9 8 bits be come 0 When 10 bit is se lected as A D converter resolu tion the 9 0 bits hold the data MN102H55D 55G F55G 471 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AN4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 BUF8 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF BUFO R R R R R R R R R R R R R R R R 0 0 0 0 0 O Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 0 0 0 0 0
198. Registers 284 Chapter 10 Low power Modes 10 1 Summary of Low power Modes 2 44440 40 0 286 10 1 1 VERVIOW Me EE 286 10 1 2 CPU Mode Control Registers 288 10 1 3 Transferring between SLOW Mode and NORMAL 289 10 1 4 Switching to Standby Mode 291 Chapter 11 Appendix 11 1 11 3 11 4 Electrical Characteristics crt cen etna edet i 294 11 1 1 MNTO2H55D 55 G et ene oed dite 294 11 1 2 MNTO2EHEB55 G cates eate 310 Data Appendix td ird nn Qa d i 339 11 2 1 List of Special Registers 339 11 22 MN102H55D 55G F55G Address Map 518 11 2 3 List of Pin Functions u l L l 520 Initialization Program 522 Flash EEPROM Version 524 11 4 1 PLETA EIN ics stets ott e 524 11 4 2 Flash EEPROM Programming eee 525 11 4 3 PROM Writer Mode 525 11 4 4 Onboard Serial Programming Mode 526 11 4 5 Hardware Used in Serial Programming Mode 526 11 4 6 Connecting Onboard Serial Programming Mode 529 11 4 7 System Configuration for Onboard S
199. Serial Interface 15 A2 Output Address Output Refer to Pin 13 AO Description for details P22 General purpose Port 21 Refer to Pin 13 P20 Description for details SBO2 Output Serial Interface 2 This pin can be used as a data output pin for serial inter Data Output face 2 if it is not used as the address output pin in single chip mode processor mode or memory expansion mode Because pin 53 has the same function either pin 53 or pin 15 must be selected Refer to Chapter 5 Serial Interface 16 Output Address Output Refer to Pin 13 AO Description for details P23 y o General purpose Port 23 Refer to Pin 13 P20 Description for details MN102H55D 55G F55G 3 Chapter 1 General Description Table 1 4 1 List of Pin Functions 11 26 Pin Number Pin Name yo Function Description 26 A4 Output Address Output Refer to Pin 13 AO Description for details P24 General purpose Port 24 Refer to Pin 13 P20 Description for details 15 Input Timer 15 Pulse Input This pin can be used as a timer 15 pulse input pin if it is not used as the address output pin in single chip mode pro cessor mode or memory expansion mode Because pin 11 has the same function either pin 11 or pin 26 must be se lected Refer to Chapter 4 Timers 27 29 5 7 Output Address Output Refer to Pin 13 AO Description for details P25 P27 General purpose Port Refer to Pin 13 P20 Description for deta
200. Source Bus Width 0 16 bit 1 8 bit 8 Source Pointer Increment 0 Fixed 1 Increment 1 Transfer Direction 0 External device external memory 1 External memory external device 0 ETC Transfer Enable 0 Disable 1 Enable 410 MN102H55D 55G F55G ETOCTR x 00FD40 ETC 0 Control Register 16 bit access register ETOCTR sets the ETCO operat ing control conditions Trans fers the data automatically be tween the external device with ACK input function and the ex ternal memory Selecting word as the unit is not allowed when 8 bit bus width is allowed in the external memory space Selecting 8 bit destination bus width or 8 bit source bus width is allowed only when 8 bit bus width is selected in the external memory space When destination pointer incre ment or source pointer incre ment is selected the pointer in crements by 1 in byte access and by 2 in word access The ETOEN flag is cleared to 0 by the ETCO transfer end inter rupt Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETOCNT ETO ETO ETO ETO ETO ETO 0 0 4 2 CNTIICNTIOCNT 9 CNTS8 CNT7 6 5 4 CNT3 CNT2 CNTI x R W R W R W R W R W R W R W R W ETC 0 Transfer Word 0 0 0 0 undefined undefined undef
201. TM2BR sets the counting cycle 1 to 256 The timer 2 binary counter counts the cycle of the TM2BR value 1 The valid range for TM2BR is 0 to 255 TM3BR 00 13 Timer 3 Base Register 8 bit access register 16 bit access is possible from even address sets the timer 3 count ing cycle TM3BR sets the counting cycle 1 to 256 The timer 3 binary counter counts the cycle of the TMSBR value 1 The valid range for is 0 to 255 Chapter 11 Appendix 6 5 4 3 2 1 0 T M 4 B R 4 4 4 4 4 4 4 TM4 BR7 BR6 BRS BR4 BR3 BR2 BRO x 0 0 F E 1 4 R W R W R W R W Timer 4 Base Register 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 bit access register sets the timer 4 count ing cycle sets the counting cycle 1 to 256 The timer 4 binary counter counts the cycle of the TM4BR value 1 The valid range for TM4BR is 0 to 255 7 6 5 4 3 2 1 0 T M 5 B R 5 5 5 5 5 5 5 5 BR7 BRO BRS BR4 BR3 BR2 BRI BRO x 0 0 F E 1 5 R W R W R W R W R W Timer 5 Base Register 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 bit access register 16 bit access is possible from even address TM5BR sets the ti
202. TMBIOB pin TP Interrupt P7 P2 8 5 Timers Serial I F P8 P3 16 bit Timers ATC P9 P4 8 bit PWM ETC PA P5 Pulse Width Counter ROM RAM PB Timer 8 Timer 0 underflow gt TM8BC up 8 gt T Q gt TM8IOA TM8CAX R 5 TM8CB Control gt T Q gt 8 TM8CBX Figure 4 4 6 Two phase PWM Output Block Diagram 16 bit Timer Chapter 4 Timers MN102H55D 55G F55G 145 Chapter 4 Timers This verification is unnecessary after a reset Setting TMOEN and TMOLD to 0 is required between 3 and 4 in the bank address version and the linear address version but this setting is not required in the linear address high speed ver sion 1 Do not change the clock source once you have selected it Selecting the clock source while setting the count operation con trol will corrupt the value in the binary counter 146 MN102H55D 55G F55G Timer 0 Setting 1 Verify that timer 0 counting is stopped with the timer 0 mode register TMOMD TMOMD x 00FE20 7 6 5 4 3 2 1 0 EN LD 51 50 0 2 Set the timer 0 divisor Since timer 0 divides BOSC 2 by 2 set the timer 0 base register TMOBR tol The valid range for TMOBR is 0 to 255
203. W R W R W R R W R W Serial 2 Control Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o on 16 bit access register 15 Transmit Enable 0 Disable SC2CTR sets serial 2 operating 1 Enable conditions 14 Receive Enable 0 Disable 1 Enable 13 Break Transmission 0 Don t break 1 Break 12 Reserved Set to 0 11 Reserved Set to 0 9 Bit Order Selection 0 LSB first 1 MSB first Select only when the character length is 8 bit 8 Reserved Set to 0 7 Character Length 0 7 bit 1 8 bit 6 4 Parity Bit Selection 000 None 100 0 output low 101 1 output high 110 Even 1s are even 111 Odd 1s are odd Others Reserved 3 SBO2 Output Hold Time 0 More than BOSC cycles 1 More than timer 4 underflow cycles 1 0 Serial 2 Clock Source 00 SBT2 pin The SBO2 output hold time is 422 Selection MN102H55D 55G F55G extended only when SBT2 is selected as serial 2 clock Source 01 Timer 4 underflow 1 8 10 Timer 5 underflow 1 2 11 Timer 5 underflow 1 8 Chapter 11 Appendix 7 6 5 4 3 2 1 0 SC2TRB 5 2 8 2 sc2 sc2 sc2 sc2 SC2 SC2 i TRB7 TRB6 TRBS TRB4 TRB3 TRB2 TRB1 TRBO 00 092 R W Serial 2 Transmit 0 0 0 0 0 0 0 0 on Receive Buffer 8 bit acces
204. WDID flag with the bit test instruction BTST If the WDID flag is 1 execute the interrupt service routine 5 Clear the WDID flag of the WDICR register 6 Return to the main program with the RTI instruction after the interrupt service routine ends The watchdog timer shares the oscillation stabilization wait counter The WDID flag is cleared to 0 when the program moves to the STOP mode because the watchdog timer operates as the oscillation stabilization wait counter when the program returns from the STOP mode The WDID flag is cleared to 0 again after moving to the normal mode 2 6 Standby Function in the MN10200 Series Linear Addressing High speed Version LSI User Manual Overflow RST pin Watchdog Count u _ NWDEN CPUM WDIF WDICR mE Interrupt Servicing x Clear Registers R W CPUM W CPUM W CPUM W CPUM W 1 2 2 3 4 5 6 Figure 3 2 7 Watchdog Timer Interrupt Timing Watchdog Timer in STOP Mode When the watchdog timer is enabled and the CPU switches to STOP mode the watch dog timer starts counting after it operates as the oscillation stabilization wait counter if the CPU returns to the previous mode either NORMAL mode or SLOW mode from STOP mode by an interrupt In the MN102HF55G Flash EEPROM version 2 must be selected as the watchdog interrupt cycle WDMO 0 WDM1 1 when the CPU moves to STOP mode Chapter 3 Int
205. WE late 2 mode WE late 3 mode Reserved WEES 11 10 WE Short Mode in CS1 Area WE short 0 mode at reset WE short 0 5 mode WE short 1 mode WE short 1 5 mode WEEL 21 20 WE Late Mode in CS2 Area WE late 1 mode at reset WE late 2 mode WE late 3 mode Reserved 21 20 WE Short Mode in CS2 Area WE short 0 mode at reset WE short 0 5 mode WE short 1 mode WE short 1 5 mode WEEL 31 30 WE Late Mode CS3 Area WE late 1 mode at reset WE late 2 mode WE late 3 mode Reserved WEES 31 30 WE Short Mode in CS3 Area WE short 0 mode at reset WE short 0 5 mode WE short 1 mode WE short 1 5 mode Please refer to Table 2 2 3 on page 77 and Table 2 2 5 on page 78 for the timing MN102HF55G H55G H55D 59 Chapter 2 Bus Interface The ALEEDGE register sets the RE waveform control modes for the external memory spaces 0 to 3 during address data shared mode ALEEDGE x 00FF8A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALEG ALEG ALEL ALEL ALEG ALEG ALEL ALEL ALEG ALEG ALEL ALEL ALEG ALEG ALEL ALEL 31 30 31 30 21 20 21 20 11 10 11 10 01 00 01 00 Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 ALEL 01 00 Late Mode CSO Area ALE late 0 mode ALE late 0 5 mode ALE late 1 mode
206. after a reset Setting TM5EN and TM5LD to 0 is required between 7 and 8 in the bank address version and the linear address version but this setting is not required in the linear address high speed ver sion Do not change the clock source once you have selected it Selecting the clock source while setting the count operation con trol will corrupt the value in the binary counter MN102H55D 55G F55G 205 Chapter 5 Serial Interface BOSC 2 TMOBR 00 40 EE 5 y y y y y Y TMOBC 00 40 00 40 00 49 00 40700 40700 4 00 40 00 40 00 4 40 00 40 1 W W output BM j EL TM5BR 00 01 TM5BC 00 01 00 01 00 01 00 01 00 o Y Y Y Y Timer 5 underflow KI to serial I F means the omission Figure 5 2 6 Serial Clock Timing 206 MN102H55D 55G F55G Chapter 5 Serial Interface 5 2 4 Transmission This section describes the transmission using the serial interface 3 Master transmission is operated using SDA3 and SCL3 pins Initial Setting 1 Set the SDA and SCL pins to open drain with the port 8 mode control registers
207. be used as the port B1 when this pin is not used as the low speed oscillation pin Definition A Add D Delete Change Page 4 MN102H55D 55G F55G User s Manual Record of Changes Ver 1 1 to Ver 2 0 Former Version New Version In the MN102H55D 55G the ADBOCK and ADBICK flags do not operate correctly Compare the return ad dress to the ADBO register or ADBI register to check the address break interrupt generation The return address is the ADBO register value plus 1 or the ADBI register value plus 1 In the MN102H55D 55G the ADBOCK and ADBICK flags do not operate correctly Compare the return ad dress to the ADBO register or ADBI register to check the address break interrupt generation The return address is the ADBO register value plus 1 or the ADB1 register value plus 1 15 14 Set Triger Conditions for K17 Pin Interrup 13 12 Set Triger Conditions for K16 Pin Interrupt 11 10 Set Triger Conditions for K15 Pin Interrup 9 8 Set Triger Conditions for K14 Pin Interrup 7 6 Set Triger Conditions for Pin Interrup 5 4 Set Triger Conditions for K12 Pin Interrupt 3 2 Set Triger Conditions for K11 Pin Interrup 1 0 Set Triger Conditions for K10 Pin Interrup Set OR Pin for K17 Pin Set OR Pin for K16 Pin Set OR Pin for K15 Pin Set OR Pin for K14 Pin Set OR Pin for K13 Pin Set OR Pin for K12 Pin Set OR Pin for K11 Pin Set OR Pin for K10 Pin 7 6 5 4 3 2 1 0 NW
208. between Vref and Vref divided by 256 MN102H55D 55G F55G DACO P80 Figure 6 4 1 Analog Voltage Output Example Vref PO CORE gt D A Converter P6 vret P1 Interrupt A D Converter P7 P2 8 bit Timer Serial I F P8 DACO P80 P3 16 bit Timer P4 8 bit PWM ETC PA P5 Pulse Width Counter ROM RAM PB Figure 6 4 2 D A Conversion Block Diagram Using DAO Channel MN102H55D 55G F55G 229 Chapter 6 Analog Interface Port Output and D A Converter Setup 1 Set D A 0 conversion to start in the D A 0 converter control register DAOCTR This applies the voltage to the ladder resistor for the D A 0 conversion circuit and increases the power current To reduce the power current this setting is not al lowed when the D A conversion is performed DAOCTR x 00FF40 7 6 5 4 3 2 1 0 DAO ON 2 Set the data to be converted to the D A 0 conversion data buffer DAOBUF DAOBUF x 00FF41 7 6 5 4 3 2 1 0 DAO DAO DAO DAO DAO BUF7 BUFGIBUFSIBUFABBUF3 BUF2 BUFI BUFO 3 Set P80 of the port 8 to output using the PSLMD register P8LMD x 00FFFC f 6 5 4 3 2 1 0 P8 P8 P8 P8 P8 ILMD4 LMD3 LMD2 LMD 1 The DACO pin outputs the D A conversio
209. bus lock and disabled interrupts This setting cannot be made in this series 17 src dest lower 16 bits 18 srczdest lower 16 bits 19 src gt dest lower 16 bits signed MN102H55D 55G F55G 541 Chapter 11 Appendix Instruction Mnemonic Operation Cycle Machine Code BLE label VF NF ZF 1 PC 2 d8 label PC VF NF ZF 0 2 gt label 0 PC 2 d8 label PC VFANF 1 2 gt BGT label VF NF ZF 0 PC 2 d8 label PC VFANF ZF 1 PC 2 P BCS label CF 1 PC 2 d8 label PC CF 0 2 BLS label CF ZF 1 PC 2 d8 label PC CF ZF 0 PC 2 PC BCC label CF 0 PC 2 d8 label gt PC CF 1 PC 2 PC BHI label CF ZF 0 PC 2 d8 label PC CF ZF 1 PC 2 PC BVC label VF 0 F5 FC d8 PC43 d8 label VF 1 3 gt BVS label VF 1 F5 FD d8 PC 3 d8 label PC VF 0 3 gt BNC label NF 0 F5 FE d8 PC 3 d8 label PC NF 1 3 gt BNS label NF 1 F5 FF d8 PC43 4d8 label PC NF 0 3 gt BRA label PC 2 d8 label PC EA d8 BEQX label ZX 1 F5 E8 d8 PC 3 d8 label PC ZX 0 3 gt label ZX 0 F5 E9 d8 3 8 PC ZX 1 3 gt Quick decoder ON Notes 20 src2dest lower 16 bits signed This setting cannot be made in this series 21 src l
210. but ATC accepts an interrupt after the transfer ends When NMI occurs during transfer ATC stops the transfer and executes the interrupt service routine The bus acquisition priority is as follows ATCO ATCI ATC2 ATC3 CPU Chapter 7 ATC ETC Table 7 1 1 ATC Functions Mode Operation Memory Operation by ATC Transfer Main ATC Interrupt Program Transfer Program 5 c MA at E Interrupt Z iR Interrupt program 2 Ve is activated only a EN when the last transfer e ends ib O gt Y Main ATG Interrupt 5 Program Transfer Program c 5 x gt Interrupt Interrupt program x 57 is activated only J _ 2 when the transfer ends Y Main ATC Interrupt Program Transfer Program o 5 5 a 5 3 3 mE 0 Y 22 4 a N Y Interrupt program activation can be set optionally shows one instruction MN102H55D 55G F55G 233 Chapter 7 ATC ETC 7 1 2 Control Registers The ATC contains the ATC control registers ATnCTR and the ATC transfer word count registers ATnCNT the source address pointers ATnSRC and the destination address pointers ATnDST ATnCTR 15 14 13 12 11 10 9 8 7
211. cleared by the read or write operation of the SC4TRB register Set 1 to the SC4REN bit A framing error occurs when the stop bit is 0 Framing error data is updated whenever the stop bit is received A parity error occurs when the parity bit is 1 although it is set to 0 when the parity bit is 0 al though it is set to 1 when the parity bit is odd although it is set to even and when the parity bit is even although it is set to odd Parity error data is updated whenever the parity bit is re ceived An overrun error occurs when the next data is received com pletely before the CPU reads the received data SC4TRB Over run error data is updated when ever the last data bit seventh or eighth bit is received Do not poll the SC4RBY flag to verify the reception end in clock synchronous mode Generate a serial 4 reception end interrupt or poll the SC4RXA flag to verify the reception end Chapter 11 Appendix 7 6 5 4 3 2 1 0 T M 0 B TMO TMO TMO TMO TMO TMO TMO TMO BC7 BC6 BCS BC4 BC3 BC2 BCO x 00 0 0 0 0 0 0 0 0 0 on on Counter 8 bit access register TMOBC operates timer 0 count ing 7 6 5 4 3 2 1 0 T
212. in the timer 8 mode register TM8MD Set counting stop Select up counting By setting TM8NLD of the TM8MD register to 1 select repeat counting from 0 to x FFFF Select timer 0 underflow as the clock source Set the operating mode of the capture register to the rising edge of TM8IOA pin and the rising edge of TM8IOB pin TM8MD x 00FE80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM8 TM8 TM8 8 TM8 TM8 8 8 TM8 8 8 8 8 TM8 EN NLD UDI UDO TGE ONE MDI MDO ECLR ASEL 52 51 SO 0 0 0 0 0 0 1 1 0 0 100 0 0 0 2 Set TM8NLD TM8EN TM8MD to 1 0 respectively This enables TM8BC and RS F F 3 Set TM8NLD and TM8EN to 1 This starts the timer Counting begins at the start of the next cycle Interrupt Enable Setting 4 Enable interrupts after clearing all prior interrupt requests To do this set IQOLV 2 0 of the external interrupt 0 control register IQOICH to the interrupt level 0 to 6 TM8BIR of the timer 8 capture B interrupt control register TM8BICL to 0 and TM8BIE of the timer 8 capture B interrupt control register TM8BICH to 1 Thereafter a timer 8 capture B interrupt occurs when the ture to TM8CB register is generated on the rising edge of TMSIOB pin Interrupt Processing and Signal Width Calculation 5 Execute the interrupt service routine The interrupt service ro
213. is transferred and reach x OFFF when the transfer is completed This register writes only 16 bit data Use the MOV instruction to set the data AT1SRC x 00FD14 ATC 1 Source Address Pointer 16 24 bit access register AT1SRC sets the transfer source address When the source pointer increment bit is set to be fixed the transfer source address do not change When the source pointer incre ment bit is set to increment in crement by 1 in the byte transfer and by 2 in the word transfer This register writes only 24 bit data or 16 bit data Use the MOV instruction or the MOVX instruction to set the data Chapter 11 Appendix x 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AT1 DST ATI ATI ATI ATI ATI ATI ATI ATI ATI OOFD1 8 IDSTISDSTIADSTI3DSTI2DSTI IIDSTIO DST9 DST8 DST7 DST6 DSTS DST4 DST3 0872 DSTI DSTO x R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W ATC 1 Desti nation undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address Pointer 16 24 bit access register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AT1DST sets the transfer desti
214. must be disabled during this routine and Oxf7ff psw Clear IE flag of PSW nop Inserted to ensure that XnICH is accessible nop 3 after clearing IE flag completely mov 40 Write LV IE or 0x0800 psw Set IE flag of PSW The program does need to clear the IE flag PSW to disable interrupts during interrupt servicing since IE 0 unless the IE flag is set The nop instructions can be any instructions except those which write the IE flag of PSW or LV and IE flags of register Two nop instructions are inserted in the example to keep the mini mum number of cycles to change the IE flag More than two nop instructions can be inserted IAGR x 00FCOE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GN5 GN4 GN3 GN2 GN1 GNO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Group number IRQTRG x 00FCBO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1Q4 104 103 IQ3 102 192 1Q1 IQ1 100 100 TGO TG1 TGO TGO TGO TGO IQOTG 1 0 Chapter 3 Interru Interrupt trigger condition for IRQO pin pts IQ1TG 1 0 Interrupt trigger condition for IRQ1 pin IQ2TG 1 0 Interrupt trigger condition for IRQ2 pin IQ3TG 1 0 Interrupt trigger condition for IRQ3 pin IQ4TG 1 0 KEYTRG x 00FCB2 15 14 13 12
215. o corsse lo lt ar Zz zZ mam 2 2 O T o 595 A 2 25 937 Lo gt 2 e 204 E ot ge o lt tr e d o o 8 5 s 0 g 2 x 3 colo 9 9 ESSE Q Q MN102HF55G H55G H55D 70 Chapter 2 Bus Interface Table 2 1 6 Address Data Separate Mode 8 bit Bus Data Access The length of wait cycle can be set in 0 5 cycle units i e o co N N lt lt z o Ave Him o e a Or ee ee ee eee ee ee Lets Sl ENTER CREDE 9 seh S e TEES al ele eo ei AAAA AAAA AAAA AAAA lel ae Oe 8 le mete ei LbL T L L 1 o 29 gt N gt x lt Shis E 8 3 2 z e l E AC E E 8L p eM e L lt lt G 1 1 1 1 1 5 G ro 9 as H ected Ime
216. on the selected mode pins Please refer to 11 2 3 Pin Functions for details Internal Data Bus Pin Peripheral Function Output Peripheral Function Input Input Level Schumitt Input LVTTL level at 3 3 V of voltage Peripheral Function Direction Control PnDIR R lt lt Figure 8 1 1 I O Port Configuration 260 MN102H55D 55G F55G Chapter 8 Ports 8 1 2 Control Registers The MN102H55D 55G F55G contains the port output register PnOUT the port input registers PnIN the port mode registers PnMD the port input output control registers PnDIR and the port pull up control registers PnPLU Refer to 11 2 3 List of Pin Func tions for details because some bits are not carried depending on ports The port input output control register is valid only when each port is used as its port input output function The direction is determined by setting each mode register when each port is used as an input output pin of peripheral function 7 6 5 4 3 2 1 0 Pn Pn Pn PnOUT OUT7 OUT6 OUTS OUT4 OUT3 OUT2 OUT1 OUTO n Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Pn IN7 Pn Pn Pn Pn Pn Pn Pn IN6 INS INA IN3 IN2 INI INO PnIN Reset Port Port Port Port Port Port Port Port 7 6 5 3 2 1 0 PnLMD
217. parity bit is odd although it is set to even and when the parity bit is even although it is set to odd Parity error data is updated whenever the parity bit is re ceived An overrun error occurs when the next data is received com pletely before the CPU reads the received data SC3TRB Over run error data is updated when ever the last data bit seventh or eighth bit is received Do not poll the SC3RBY flag to verify the reception end in clock synchronous mode Generate a serial 3 reception end interrupt or poll the SC3RXA flag to verify the reception end MN102H55D 55G F55G 427 Chapter 11 Appendix I 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sc4 SCA SCA SCA 5 4 5 4 4 SCA 4 SCA SCA SCA SC4 4 TEN REN BRE PTL OD ICM LN PTY2 PTYI PTYO SB SI 50 R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 on on on o 15 Transmit Enable 0 Disable 1 Enable 14 Receive Enable 0 Disable 1 Enable 13 Break Transmission 0 Don t break 1 Break 12 PC Start or Stop Sequence 0 Stop sequence output when changing this bit from 1 to 0 1 Start sequence output when changing this bit from 0 to 1 11 Protocol Selection 0 Asynchronous mode 1 Clock synchronous mode
218. source must be set to BOSC 8 conversion time 3 73 us or higher The voltage between Vref and Vref must be input to each analog input pin Set the voltages of Vref pin and Vref pin as follows Vss lt Vref Vref lt Vref ANO ANOBUF M AN1BUF AN2 10 bit AN2BUF ANS U gt successive ANSBUF ANM m approximation AN4BUF ANS X ADC ANSBUF AN6 AN6BUF AN7BUF Vref Figure 6 1 1 Analog Interface Configuration Notices When Using A D Converter 1 Set the impedance of the analog signal for A D conversion to 8 kQ or less 2 If the impedance of the analog signal cannot be set to 8 kQ or less connect the A D input pin to the condenser of 2000 pF or more to control the voltage change of the A D input pin 3 To prevent the power potential fluctuation do not change the chip output level from high level to low level or vice verse or do not switch the peripheral load circuit on off during A D conversion Equivalent Circuit Block Outputs Analog Signal MN102H55D 55G F55G R i A D Input Pin ig AVss lt 8 kQ Or C gt 2000 pF Table 6 1 1 A D Converter Functions Chapter 6 Analog Interface Feature Description Sample and Hold Built in Conversion Resolution 10 bit an
219. stores the fixed user program In onboard serial programming mode the erasing programming in this area 15 protected Programming is possible by using the parallel writer Security Code The area stores the security code for the serial writer password Enter 8 character ASCII code Reserved Area Do not write in this area MN102H55D 55G F55G 527 Chapter 11 Appendix Branch Instruction to Reset Start Service Routine Normally the reset start address is x 80000 but the program branches into x 81820 with the soft branch instruction in the serial writer loader In this area the JMP instruction to the actual reset service routine is stored Branch Instruction to Interrupt Service Routine Normally the jump address at interrupt is 80008 but the program branches into x 81818 with the soft branch instruction in the serial writer loader In this area the JMP instruction to the actual interrupt service routine is stored User Program Area This area stores the user program Size 122kbytes 32 bytes 528 MN102H55D 55G F55G 11 4 6 Connecting Onboard Serial Programming Mode Use YDC serial writer for flash microcontroller All input output pins must be set to input at reset release SBT To Writer SBD To Writer To Writer Pins 73 and 74 must always be connected pull up resistors when using writer or not 4 RESET PAO IRQO PA2 IRO2 PA3 IRO3
220. system control register prohibits programming the system related registers 9 2 2 Control Registers SYSCTL x 00FCDO 7 6 5 4 3 2 1 0 SYS SYS SYS SYS SYS SYS SYS SYS 5 c2 c1 CO System Control Register Atreset 0 1 1 1 1 1 0 1 7D Program all registers at reset Others Do not program the following the system related registers CPU Control Address Break Memory Control Port Control 284 MN102H55D 55G F55G CPUM EFCR ADBO ADB1 ADBCTL EXWMD MEMMD1 MEMMD2 DRAMMD1 DRAMMD2 POMD P1LMD P2MD P3LMD PSHMD PALMD P4HMD P5LMD PSHMD P6MD P7LMD P7HMD P8LMD P8MMD P9LMD P9HMD PAMD PBMD Chapter 10 Low power Modes Chapter 10 Low power Modes 10 1 10 1 1 Summary of Low power Modes Overview The MN102H55D 55G F55G provides two oscillation pins high speed and low speed for system clock It has two CPU operating modes NORMAL and SLOW and two standby modes HALT and STOP Using these modes effectively helps to reduce power consumption HALT Mode HALTO OSCI Oscillation XI Oscillation Interrupt Reset NORMAL Mode NORMAL OSCI Oscillation HALTO OSCI Halt XI Oscillation Program 1 Interrupt Interrupt STOP Mode XI Oscillation Program 5 IDLE OSCI Oscillation XI Oscillation Program 3 Program
221. underflow 1 8 Chapter 11 Appendix SC1CTR x 0OOFD88 Serial 1 Control Register 16 bit access register SC1CTR sets serial 1 operating conditions The SBO1 output hold time is extended only when SBT1 pin is selected as serial 1 clock Source MN102H55D 55G F55G 419 Chapter 11 Appendix 7 6 5 4 3 2 1 0 5 SCI 5 1 5 1 SCI SCI SCI TRB7 TRB6 TRB5 TRB4 TRB3 TRB2 TRBI TRBO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Serial Transmit Receive Data 420 MN102H55D 55G F55G SC1TRB x OOFD8A Serial 1 Transmit Receive Buffer 8 bit access register SC1TRB writes the serial 1 transmit data and reads the se rial 1 receive data Transmission starts by writing the data into this register The data is received by reading this register In 7 bit transfer the MSB bit 7 becomes 0 The data is read when an interrupt occurs or the SC1RXA flag of the SC1STR register is 1 7 6 5 4 3 2 1 0 SC1 SCI jreserv 5 reserv SCI SCI TBY RBY ed RXA ed ed PE R R R R R R R R 0 0 0 0 0 0 0 0 7 Transmission Busy Flag 6 Reception Busy Flag 5 Reserved 4 Received Data 3 2 Reserved 1 Parity Error 0 Overrun Error Ready to transmit Transmission in p
222. will be sent to the CPU The A D converter converts each ANO to AN2 a single time at timer 3 underflow Timer 3 underflow Conversion Interrupts ch1 ch2 cho chi ch2 Figure 6 2 6 3 channel A D Conversion Timing Chapter 6 Analog Interface 6 3 Summary of D A Converter 6 3 1 Overview The MN102H55D 55G F55G contains two 8 bit redistribution R 2R D A converters Each D A converter has one output channel and one 8 bit data register When the D A converter is unused turning the ladder resistor off reduces the power current DAC 1 0 pins output the voltage the difference between Vref and Vref divided by 256 when the data register changes 1 LSB Set the voltages of Vref pin and Vref pin as follows Vss Vref D A Converter Control Registers DAOCTR D A Conversion Data Buffers DAOBUF R 2R 8 bit DAC DA1BUF R 2R 8 bit DAC DA1CTR Figure 6 3 1 D A Converter Configuration Table 6 3 1 D A Converter Functions Feature R 2R 8 bit D A Converter Conversion Resolution 8 bit The voltage corresponding to the value set in DAnBUF n 0 1 between Vref and Vref is output Conversion Time Maximum of 6 0 us External load capacitance 70 pF MN102H55D 55G F55G Chapter 6 Analog Interface 6 3 2 Control Registers The D A converter contains the D A converter control r
223. 0 0 0 1 0 0 0 0 initialized cleared to 0 2 Set the timer 8 divisor Since the divisor is the timer 0 underflow divided by 5 set the timer 8 compare capture register A TM8CA to 4 The valid range is 1 to TM8CA x 00FE84 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 8 8 TM8 8 8 8 8 TM8 TM8 8 8 8 8 TM8 CA14 CAI3 CA12 CA10 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO 0 0 0 0 0 0 0 0 0 0 1 0 0 3 Set the phase difference for timer 8 Since the phase difference is 2 cycles of the timer 0 underflow set the timer 8 compare capture register B TM8CB to 1 The valid range is 0 lt TM8CB lt TM8CA TM8CB x 00FE88 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 8 TM8 TM8 8 TM8 TM8 8 8 8 8 8 TM8 TM8 8 TM8 15 CB14 CB12 CB9 CB8 CB6 CBS CB4 CB2 0 0 0 0 0 0 0 0 0 0 1 4 Write the dummy data to the timer 8 compare capture register AX TM8CAX to set the initial value in the TM8CAX register The value cannot be written in the TM8CAX by software In the double buffer mode read the timer 8 compare captur
224. 0 Address Long Mode CSO Area 00 long 1 mode 01 long 1 5 mode 10 long 2 mode 11 long 3 mode at reset ADL 11 10 Address Long Mode in CS1 Area AD 00 long 1 mode at reset 01 AD long 1 5 mode 10 AD long 2 mode 11 AD long 3 mode ADL 21 20 Address Long Mode in CS2 Area 00 ong 1 mode at reset 01 ong 1 5 mode 10 ong 2 mode ong 3 mode ADL 31 30 Address Long Mode in CS2 Area 00 AD long 1 mode at reset AD long 1 5 mode AD long 2 mode AD long 3 mode Table 2 1 2 List of Bus Interface Control Registers Register Address R W Function EXWMD 00 80 R W_ External Memory Wait Register MEMMDI 00 82 R W_ Memory Mode Setup 1 Register MEMMD2 00 84 R W_ Memory Mode Setup 2 Register DRAMMDI 00 90 R W_ DRAM Control Register Please refer to Table 2 2 7 on DRAMMD2 x 00FF92 R W DRAM Control 2 Register page 79 for the timing REEDGE x 00FF86 R W RE Waveform Control Register WEEDGE 00 88 R W_ WE Waveform Control Register ALEEDGE x O0FF8A R W ALE Waveform Control Register MPXADR x O0FF8C R W Address Output Time Control Register MN102HF55G H55G H55D 61 Chapter 2 Bus Interface Q When connecting to mask ROM do not need to connect WEH and WEL 62 2 1 3 Memory Connection Examples The MN102H55D 55G F55G can connect to SRAM DRAM mask ROM or
225. 0 Peripheral Register Peripheral Register x 010000 Ext IM 5 0 x 010000 External Device CSO ou emoy space 080000 CSO output 080000 Reset Start Reset Start Internal ROM 128K bytes 1 x 0A0000 2 pee External Device 200000 E x 400000 x 400000 External Device External Memory Space 1 x 800000 output x 800000 55 External Memory Space 2 x C00000 CS2 output x C00000 _ External Memory Space 3 CS3 output xFFFFFF xFFFFFF Up to 16M space Up to 16M space expansion is possible exapnsion is possible 2 MN102HF55G 128K bytes x 0A0000 4096 bytes x 009000 MN102H55G 128Kbytes x 0A0000 4096 bytes x 009000 MN102H55D 64Kbytes x 090000 4096 bytes x 009000 Figure 2 1 1 Address Space 52 MN102HF55G H55G H55D Chapter 2 Bus Interface 2 1 2 Control Registers These registers control the bus interface the external memory wait reg ister EXWMD the memory mode setup 1 register MEMMD1 the memory mode setup 2 register MEMMD2 the DRAM control regis ter DRAMMDI the DRAM control 2 register DRAMMDJ2 the RE waveform control register REEDGE the WE waveform control regis ter WEEDGE the ALE waveform control register ALEEDGE and the address output time control register MPXADR The EXWMD register sets the number of waits for devices in the external memory spaces 0 to 3 EXWMD x 00FF80
226. 0 1 0 1 0 1 15 T9C 5 T9C AX14 T9C AXI2 T9C AXII T9C 10 T9C AX9 AX8 TIC AX7 6 T9C 5 T9C T9C AX3 T9C AX2 T9C AXI T9C 458 MN102H55D 55G F55G TM9CA 94 9 Capture Register 16 bit access register sets the timer 9 count ing cycle The timer 9 binary counter counts the cycle of the TM9CA value 1 TM9CA changes PWM and gener ates a timer 9 capture A interrupt When capture is selected this reg ister is read only A timer 9 capture A interrupt is generated when cap ture occurs When compare is se lected set the PWM cycle When this register matches the timer 9 binary counter a timer 9 capture A interrupt occurs This register write only 16 bit data Use the MOV instruction to set the data TM9CAX 96 9 Capture Register Set 16 bit access register This register is valid only when the associated compare register is set to the double buffer mode The TM9CAX cannot read or write The contents of TM9CA are loaded to TM9CAX by write signal TM9CAX sets the PWM cycle When TM9BC TM9CAX a timer 9 capture A interrupt oc curs The contents of TM9CA are loaded to TM9CAX by a timer 9 capture A interrupt and
227. 0 1 0 1 0 1 0 1 0 1 4 4 Input Output Signal Switch 3 PA3 Input Output Signal Switch 2 PA2 Input Output Signal Switch 1 PA1 Input Output Signal Switch 0 PAO Input Output Signal Switch 7 6 5 4 3 2 1 0 reserv reserv reserv PB PB ed ed ed ed 2 R W R W R W R W R W R W R W 0 0 0 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6 4 Reserved 3 Reserved 2 PB1 Input Output Signal Switch 1 0 PBO Input Output Signal Switch 516 MN102H55D 55G F55G 0 Port 1 IRQ4 input or input 0 Port 1 IRQ3 input 0 Port 1 IRQ2 input 0 Port 1 IRQ1 input 0 Port 1 IRQO input Setto 0 Set to 1 0 Port 1 Xl input 00 Port 01 BOSC output 10 BIBT1 output 11 BIBT2 output PAMD x OOFFDC Port A Mode Register 8 bit access register PAMD sets a signal output to the port A PBMD x OOFFDD Port B Mode Register 8 bit access register PBMD sets a signal output to the port B Chapter 11 Appendix MN102H55D 55G F55G 517 peioejes WAAd 24 1 1 4 ejqnop se pesn si 1 141 JOU peed jouueo 19 S1691 slu D XAON 10 AOW eur es apum sseooe IIq pz JO 110 91 AON eur esq
228. 0 MHz Output pins open or Vss Power supply current in SLOW mode 2 32 kHz Output pins open Oscillator stop Power supply current in 1003 STOP mode All functions stop 1 30 MHz Power supply current in HALTO mode Fosc2 32 kHz Fosc1 oscillator stop Power supply current in 005 HALT1 mode Fosc2 32 kHz 312 MN102H55D 55G F55G Chapter 11 Appendix Voo 3 0 V to 3 6 V Vss 0 V NC CA 40 C to 85 C Capactance Parameter Symbol Conditions Unit Input Output Pins 1 lt Output pushpull Input LVTTL level schmidt trigger Programmable pullup gt 00 07 10 17 20 27 P30 P37 P40 P43 P50 P57 P60 P63 P70 P75 P82 P87 P90 P93 PAO PA5 mee e fe ILLI 2 0 mA Output high voltage VoD 33 V loL 2 0 mA Output low voltage VoD 33 V C11 Pullup resistance PPU1 VSS 10 30 kQ 3 3 V MN102H55D 55G F55G 313 Chapter 11 Appendix 3 0 V to 3 6 V Vss 0 V lt a 40 C to 85 C Parameter Symbol Conditions Unit Input Output Pins 2 lt Output pushpull Input CMOS level schmidt trigger Programmable pullup Analog pins gt P44 P47 AN4 7 80 81 1 94 97 3 fe um epe me polo eem 314 MN102H55D 55G F55G Chapter 11 Appendix Vpp 3 0 V to
229. 0 reception end interrupt Serial 1 transmission end interrupt Serial 1 reception end interrupt Serial 4 transmission end interrupt Serial 4 reception end interrupt MN102H55D 55G F55G Chapter 11 Appendix ATA1CTR x 00FD10 ATC 1 Control Register 16 bit access register AT1CTR sets the ATC1 operat ing control conditions Selecting the two bytestransfer mode is valid only in byte ac cess The LSB of the address in the first byte forcibly becomes 0 and the LSB of the address in the second byte forcibly be comes 1 Selecting word as the unit is not allowed when 8 bit bus width is allowed in the external memory space Selecting 8 bit destination bus width or 8 bit source bus width is allowed only when 8 bit bus width is selected in the external memory space When destination pointer incre ment or source pointer incre ment is selected the pointer in crements by 1 in byte access and by 2 in word access The AT1IQ 3 0 bits are cleared to 0 by the ATC1 transfer end in terrupt 401 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATI ATI 1 CNT8 CNT7 CNT6 CNTS CNTA CNT3
230. 0 x 0O0FE23 x EW Timer 3 Mode Register 0 0 0 0 0 0 0 0 on 0 0 on 8 bit access register 16 bit access is possible from even address 7 TM3BC Count 0 Disable 1 Enable sets the timer operat ing conditions 6 Load TM3BR to TM3BC 0 Disable 1 Enable T Reset the 1 2 divisor circuit 1 0 Clock Source Selection 00 BOSC 2 01 Timer 0 underflow 10 Timer 2 cascade 11 Timer 4 underflow MN102H55D 55G F55G 443 Chapter 11 Appendix 7 6 5 4 3 2 1 0 TMAMD TM4 5 TM4 TM4 1 si so x OOFE24 ROWO ee ee Timer 4 Mode Register 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 8 bit access register 7 TM4BC Count 0 Disable sets the timer 4 operat 1 Enable ing conditions 6 Load TM4BR to TM4BC 0 Disable 1 Enable Reset the 1 2 divisor circuit 1 0 Clock Source Selection 00 BOSC 2 01 Timer 0 underflow 10 Timer 3 cascade 11 TM4IO pin input 7 6 5 4 3 2 1 0 TM5MD 5 5 5 5 LD 1 0 x OOFE25 RW RAW R ea Timer 5 Mode Register 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 8 bit access register 16 bit access is possible from even address 7 TM5BC Count 0 Disable 1 Enable 5 sets the timer 5 operat ing conditions 6 Load TM5BR to TM5BC 0 Disable 1 Enable Reset the 1 2 divisor circuit 1 0 Cl
231. 00FD93 Serial 2 Status Register SC3CTR x O0FD98 Serial 3 Control Register Serial 3 SC3TRB x O0FD9A Serial 3 Transmit Receive Buffer SC3STR x 00FD9B Serial 3 Status Register SCACTR x O0FDAO Serial 4 Control Register Serial 4 SCATRB x 00FDA2 Serial 4 Transmit Receive Buffer SC4STR x 00FDA3 Serial 4 Status Register Chapter 5 Serial Interface MN102H55D 55G F55G 193 Chapter 5 Serial Interface 5 1 3 Serial Interface Connection 1 In half duplex connection mode the SBT pin requires a pullup re sistor externally or an internal pullup resistor Clock Synchronous Mode The serial interface can connect using either simplex or duplex synchronous transfer SBO SBO SBO SBO SBO SBO SBI SBI 9 SBI ss SB 8 a a a a SBT SBT spT sBT SBT SBT S 18 5 Transmit Receive E E 5 Full Duplex Connection Half Duplex Connection Figure 5 1 2 Synchronous Mode Connections Asynchronous Mode In the duplex half duplex asyn The serial interface can connect using either simplex or duplex asynchronous transfer chronous mode both SBT pins become input when they are not selected to transmit so they re SBO SBO SBO SBO quired pullup resistors gt D gt D o SBI SBI 9 SBI SBI 9 c c 5 5 Transmit Receiv
232. 1 byte word data is transferred and reach x OFFF when the transfer is completed This register writes only 16 bit data Use the MOV instruction to set the data ET1SRC x 00FD54 ETC 1 Source Address Pointer 16 24 bit access register ET1SRC sets the transfer source address When the source pointer increment bit is set to be fixed the transfer source address do not change When the source pointer incre ment bit is set to increment in crement by 1 in the byte transfer and by 2 in the word transfer This register writes only 24 bit data or 16 bit data Use the MOV instruction or the MOVX instruction to set the data Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ET1 DST O0FD58 IDSTISDSTIADSTI3DSTI2DSTI IIDSTIO DST9 DST8 DST7 DST6 DSTS DST4 DST3 DST2 DSTI DSTO x R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W ETC 1 Desti nation undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address Pointer 16 24 bit access register 15 14 13 12 11 10 9 8
233. 1 Even Odd Character Length 7 bit 8 bit Bit Order LSB first or MSB first 8 bit only Clock Source 1 2 1 8 of timers 1 2 4 5 underflow External clock 1 8 of timers 1 2 4 5 underflow Maximum Baud Rate 8 5 Mbps with a 34 MHz oscillator 28800 bps 1228800 bps Error Detection Parity error Overrun error Parity error Overrun error Framing error Buffers Independent transmit receive buffers single tranmit buffer double receive buffer Interrupts Transmission or reception end interrupt Master transmission and reception are possible No start sequence detection function When the oscillation frequency of 19 6608 MHz is selected MN102H55D 55G F55G 189 Chapter 5 Serial Interface 190 MN102H55D 55G F55G 5 1 2 Control Registers Three registers control the serial interface the serial transmit receive buffers SCnTRB the serial port status registers 5 5 and the serial control registers SCnCTR 7 6 5 4 3 2 1 0 SCn 5 5 5 5 SCn SCn SCn SCnTRB TRB7 TRB6 TRB5 TRB4 TRB3 TRB2 TRB 1 TRBO Reset 0 0 0 0 0 0 0 0 Transmission starts when the data is written to the SCnTRB register The CPU reads the received data by reading the SCnTRB register During 7 bit data reception the MSB bit 7 is set to 0 When an serial 0 reception end interrupt occurs or the SCnRXA flag of the SCnS
234. 1 0 2 TM9B IE R R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 9 Capture Interrupt Enable Flag 356 MN102H55D 55G F55G 0 Disable 1 Enable TM9BICL 00 66 9 Interrupt Control Register 8 bit access register requests and verifies a timer 9 capture B interrupt This register allows only byte accesses Use MOVB instruc tion to set the data x 00FC67 Timer 9 Capture B Interrupt Control Register 8 bit access register enables a timer 9 capture B interrupt This register allows only byte accesses Use instruc tion to set the data The inter rupt level is the same level set in the IQ2LV 2 0 bits of the IQ2ICH register 7 6 5 4 2 0 103 103 IR ID R R R W R R 0 0 0 0 0 0 0 0 0 1 4 External Interrupt 3 0 No interrupt requested Request Flag 1 Interrupt requested 0 External Interrupt 3 0 No interrupt detected Detect Flag 1 Interrupt detected 7 6 5 4 2 0 IQ3 IQ3 IQ3 103 LV2 LVI LVO IE R R W R W R W R R W 0 0 0 0 0 0 on 0 0 1 6 4 External Interrupt 3 Set the level from 0 to 6 Level Setup 0 External Interrupt 3 Interrupt 0 Disable Enable Flag 1 Enable Chapter 11 Appendix 00 68 External Interrupt 3 Control Register 8 bit ac
235. 1 0 1 0 1 0 1 7 0 1 Output 0 Output low 1 Output high P2 P2 P2 P2 P2 P2 P2 P2 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUTO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 2 Output 0 Output low 1 Output high P3 P3 P3 P3 P3 P3 P3 P3 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUTI OUTO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 0 Output low 1 Output high Chapter 11 Appendix POOUT x OOFFCO Port 0 Output Register 8 bit access register POOUT sets the data output to the port 0 P10UT x OOFFC1 Port 1 Output Register 8 bit access register P1OUT sets the data output to the port 1 P2OUT x OOFFC2 Port 2 Output Register 8 bit access register P2OUT sets the data output to the port 2 x OOFFCS3 Port 3 Output Register 8 bit access register P3OUT sets the data output to the port 3 MN102H55D 55G F55G 489 Chapter 11 Appendix P4 P4 P4 P4 P4 P4 P4 P4 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUTI OUTO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port4 Output 0 Output low 1 Output high P5 P5 P5 P5 P5 P5 P5 P5 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUTI OUTO
236. 1 2 Figure 4 1 3 Figure 4 1 4 Figure 4 1 5 Figure 4 1 6 Figure 4 1 7 Figure 4 1 8 Figure 4 1 9 Figure 4 1 10 Figure 4 1 11 Figure 4 1 12 Figure 4 2 1 Figure 4 2 2 Figure 4 2 3 DRAM Connection Example 8 bit Bus Width 66 External Access No Wait Cycle 67 External Access 0 5 Wait Cycle 67 Handshake Wait Control Timing 1 Wait Cycles Data Write 80 Fixed Wait and Handshake Wait Control Timing 1 Wait Cycle as Fixed Wait 2 Wait Cycles as Whole Wait Data Write 81 Activation Sequence of Each Mode 82 Interrupt Controller Block Diagram 85 Watchdog Timer Block Diagram 85 Interrupt Servicing Time 87 External Pin Interrupt Block Diagram 94 External Pin Interrupt Timing 95 Key Input Interrupt Block Diagram 96 4x4 Key Input Interrupt Timing 96 Key Input Interrupt Timing 2 99 Watchdog Timer Interrupt Block Diagram 100 Watchdog Timer Interrupt Timing 101 Extended Watchdog Timer Interrupt Timing 102 8 bit Timer Block Diagram
237. 1 Appendix F 6 5 4 3 2 1 0 7 H M D P7 P7 P7 P7 P7 P7 P7 IHMD6 HMDS5 HMD4 HMD3 HMD2 HMD1 HMD0O x 0 0 F F F B R W R W R W R W R W R W R W Port 7 Mode Register H 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 bit access register 6 5 P75 Input Output Signal Switch 00 Port 01 SBO1 output P7HMD sets a signal output to 4 3 P74 Input Output Signal Switch 00 Port 01 SBI1 input 2 0 P73Input Output Signal Switch 000 Port 001 SBT1 input 010 SBT1 output 011 SBT1 half duplex output 100 DMUX output 510 MN102H55D 55G F55G 6 5 4 3 2 1 P8 P8 P8 P8 P8 LMD4 LMD3 LMD2 LMD1 LMDO R R R W R W R W R W R W 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 4 2 1 0 P82 Input Output Signal Switch P81 Input Output Signal Switch P80 Input Output Signal Switch 000 Port 001 TMOIO input SBT3 input 010 TMOIO output 011 SBT3 output 100 SBT3 half duplex output 101 SCL3 open drain output 110 SBT2 input cannot use P21 as SBI2 input 0 Port 1 DAC1 output 0 Port 1 DACO output Chapter 11 Appendix P8LMD x OOFFFC Port 8 Mode Register L 8 bit access register P8LMD sets a signal output to the port 8 MN102H55D 55G F55G 511 Chapter 11 Appendix 6 5 4 3 2 1 8 8 8 8 8 8 8 8 MMD7IMMD
238. 1 Appendix J 6 5 4 3 2 1 0 TM1 3BR 13 13 13 13 13 13 13 13 BR7 BR6 BRS BR4 BR3 BR2 BRO x OOFE1 8 R W R W R W R W R W R W R W R W Timer 13 Base Register 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 bit access register Sets the timer 13 counting cycle Sets the counting cycle 1 to 256 The timer 13 binary counter counts the cycle of the TM13BR value 1 The valid range for TM13BR is 0 to 255 7 6 2 4 3 2 1 0 TM1 4BR 14 14 14 14 14 14 14 BR7 BR6 BRS BRA BR3 BR2 BRI BRO x OOFE1 9 R W R W R W R W R W R W R W R W Timer 14 Base Register 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 bit access register 16 bit access is possible from even address Sets the timer 14 counting cycle Sets the counting cycle 1 to 256 The timer 14 binary counter counts the cycle of the TM14BR value 1 The valid range for TM14BR is 0 to 255 MN102H55D 55G F55G 441 Chapter 11 Appendix 7 6 5 4 3 2 1 0 TMO TMO TMO EN LD 1 so R W R W R R W R W 0 0 0 0 0 0 0 0 o 0 0 7 TMOBC Count 0 Disable 1 Enable 6 Load TMOBR to 0 Disable 1 Enable Reset the 1 2 divisor
239. 10 bit A D conversion results MN102H55D 55G F55G eere ca TES P46 POS E sie Figure 6 2 1 Analog Voltage Input Example PO CORE D A Converter P6 P1 Interrupt A D Converter 7 P2 8 bit Timer Serial VF P8 Vref P3 16 bit Timer ATG P9 AN6 P46 8 bit PWM ETC PA P5 Pulse Width Counter ROM RAM PB Figure 6 2 2 Single Channel A D Conversion Block Diagram Port Input and A D Converter Setup 1 Set AN6 pin P46 of the port 4 to AN6 input using the register 2 Set the operating conditions in the A D converter control register ANCTR Se lect single channel single conversion mode by setting ANMD 1 0 to 00 BOSC 8 as the clock source by setting ANCK 1 0 to 10 and 10 bit conversion resolution by setting ANDEC to 1 Set the conversion start execute flag ANEN to 0 and ANICH 2 0 bits to the number of channel to be converted ANCTR x 00FFO00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AN AN AN AN AN AN AN _ AN AN AN AN 2 ICH2J1CHI ICHO TC DEC MDI MDO 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 3 Set ANEN flag to 1 to start conversion Conversion begins on the first rising edge of the A D converter clock a
240. 11 14 Fig 11 1 8 ALE late 0 long 0 mode AD long 1 mode Fig 11 1 8 Address hold time 2 Other Modes tcycx Lao Fig 11 1 8 Write data delay time D15 0 AD15 0 Fig 11 1 4105 Fig 11 17 Fig 11 1 4 to 5 Fig 11 1 7 to 10 S means WE short mode S 0 0 5 1 1 5 LAD means AD long mode LAD 1 2 3 LALE means ALE long mode LALE 0 0 5 1 1 5 322 MN102H55D 55G F55G Output Signal Characteristics Parameter Data Transfer Signal Output Timing 2 G11 G12 14 15 Chip select signal fall delay time CS3 0 CS3 1 Chip select signal rise delay time CS3 0 CS3 1 Chapter 11 Appendix Vpp 3 0 V to 3 6 V Vss 0V 40 C to 85 C CL 70 pF Symbol Conditions Unit Fig 11 1 4 to 5 Fig 11 1 8 to 9 Chip select signal hold time latch signal rise delay time Fig 11 1 8 to 11 E n latch signal fall delay time Fig 11 1 8 to 11 ns means WE short mode S 0 0 5 1 1 5 MN102H55D 55G F55G 323 Chapter 11 Appendix 324 MN102H55D 55G F55G 3 0 V to 3 6 V Output Signal Characteristics Vss 20V 40 C to 85 C p T 70 pF Parameter Symbol Conditions Unit E SEJE Data Transfer Signal Output Timing 3 Late 0 5 mode ds Read enable signal fall delay time 1 Fig 11 1 4106 RE Other modes 40 Fig 11 1 4106 ALE late 0 long 0 mode AD long 1 mode 20 Fig 11 1 8109
241. 12 11 10 9 8 7 6 5 4 3 2 1 0 TMSCBX T8C T8C T8C T8C T8C T8C T8C T8C T8C T8C T8C T8C T8C T8C T8C T8C BXI5 BXIA BXI3 BXI2 BXII BXIO 9 BX8 BX7 6 BX5 BX4 BX3 BX2 BXO x OOFE8A es d Loss 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Capture Register Set 16 bit access register This register is valid only when the associated compare register is set to the double buffer mode TM8CBX cannot read or write The contents of TM8CB are loaded to 8 by write sig nal TM8CBX sets the PWM cycle When TM8BC TMS8CBX timer 8 capture B interrupt oc curs The contents of TM8CB are loaded to TM8CBX by a timer 8 capture B interrupt and TM8CBX prevents the PWM loss This register writes only 16 bit data Use the MOV instruction to set the data MN102H55D 55G F55G 457 Chapter 11 Appendix 15 TM9 15 TM9 14 TM9 CA13 TM9 12 9 CAII TM9 10 9 9 9 CA8 TM9 CA7 TM9 CA6 TM9 CA5 TM9 CA4 TM9 CA3 TM9 CA2 TM9 CA1 TM9 CA0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
242. 15 Transmit Enable 0 Disable SCOCTR sets serial 0 operating 1 Enable conditions 14 Receive Enable 0 Disable 1 Enable 13 Break Transmission 0 Don t break 1 Break 12 Reserved Set to 0 11 Reserved Set to 0 9 Bit Order Selection 0 LSB first 1 MSB first Select only when the character length is 8 bit 8 Reserved Set to 0 7 Character Length 0 7 bit 1 8 bit 6 4 Parity Bit Selection 000 None 100 0 output low 101 1 output high 110 Even 1s are even 111 Odd 1s are odd Others Reserved 3 SBOO Output Hold Time 0 More than BOSC cycles 1 More than timer 1 underflow cycles 1 0 Serial 0 Clock Source 00 SBTO pin The SBOO output hold time is 416 Selection MN102H55D 55G F55G extended only when SBTO pin is selected as serial 0 clock Source 01 Timer 1 underflow 1 8 10 Timer 2 underflow 1 2 11 Timer 2 underflow 1 8 Chapter 11 Appendix 1615 4 3 2 1 0 SCOTRB sco sco sco sco sco sco sco sco TRB7 TRB6 TRBS TRB4 TRB3 TRB2 TRBI TRBO 00 082 R W R W R W RAV Serial 0 Transmit on Receive Buffer 8 bit access register 7 0 Serial Transmit Receive D ansmit Receive Data SCOTRB writes the serial 0 transmit data and reads the se rial 0 receive data Transmission starts by writing the data into thi
243. 16 An SUB imm16 An OR imm16 PSW ADD imm16 Dn SUB imm16 Dn 2 MOV An abs16 3 abs16 An 4 imm16 Dn CMP imm16 Dn XOR imm16 Dn 5 MOVBU d16 An Dm 6 MOVX Dm d16 An 7 MOVX d16 An Dm 8 MOV d16 An 9 MOVB d16 An A MOV Am 416 An B MOV d16 An Am C d16 An Dm D MOVB d16 An Dm 548 MN102H55D 55G F55G Chapter 11 Appendix Extended Code H Third byte Byte 1 F3 Byte 2 FE Third byte Upper Lower 0 1 2 3 4 5 6 7 8 9 A B TBZ abs24 bp label TBNZ abs24 bp label D BSET abs24 bp BCLR abs24 bp Extended Code I Third byte Byte 1 F3 Byte 2 FF Third byte Upper Lower 0 1 2 3 4 5 6 7 8 9 A B 8 TBZ d8 A2 bp label TBZ d8 A3 bp label 9 BSET d8 A2 bp BSET d8 A3 bp A TBNZ d8 A2 bp label TBNZ d8 A3 bp label BCLR d8 A2 bp BCLR d8 A3 bp MN102H55D 55G F55G 549 Chapter 11 Appendix Extended Code J Third byte Byte 1 F5 Byte 2 4n Upper Lower 0 1 2 3 4 5 6 4 8 9 A B MULQL MULQH 0 Dn Dm Dn Dm Extended Code K Third byte Byte 1 F5 Byte 2 6n Upper Lower 0 1 2 3 4 5 6 7 8 9 A B 0 MULQ Dn Dm
244. 16 l d16 h Dm mem16 An d16 Dm mem16 An d24 F4 00 An lt lt 2 Dm d24 d24 m d24 h A MOV Dm d24 An MOV Dm Di An Dm mem16 An Di F1 C0 Di lt lt 4 An lt lt 2 Dm MOV Dn abs16 Dn mem16 abs16 C0 Dn abs16 l abs16 h MOV Dn abs24 Dn mem16 abs24 F4 40 Dn abs24 l abs24 m abs24 h MOV Am An Am mem24 An 50 An lt lt 2 Am 00 3 Am mem24 An d8 50 An lt lt 2 Am d8 MOV Am d16 An Am mem24 An d16 F7 A0 An lt lt 2 Am d16 1 d16 h AC MOV Am d8 An Am d24 An Am gt mem24 4 10 lt lt 2 24 1 024 024 An d24 Am mem24 An Di F1 80 Di lt lt 4 An lt lt 2 Am MOV An abs16 An mem24 abs16 F7 20 An abs16 l abs16 h MOV An abs24 An mem24 abs24 F4 50 An abs24 l abs24 m abs24 h MOV imm8 Dn imm8 Dn 80 Dn lt lt 2 Dn imm8 MOV imm16 Dn imm16 Dn F8 Dn imm16 l imm16 h MOV imm24 Dn imm24 Dn F4 70 Dn imm24 l imm24 m imm24 h imm16 An imm16 An DC An imm16 l imm16 h MOV imm24 An 24 F4 74 An imm24 l imm24 m imm24 h MOVX d8 An Dm 24 18 F5 70 An lt lt 2 Dm d8 MOVX d16 An Dm mem24 An d16 Dm F7 70 An lt lt 2 Dm d16 l d16 h MOVX d24 An Dm 24 924 gt F4 B0 An lt lt 2 Dm d24 d24 m d24 h MOVX Dm
245. 2 11 10 9 8 7 6 5 4 3 2 1 0 AT2 2 AT2 AT2 AT2 AT2 2 AT2 AT2 2 IDSTISDSTIADSTI3DSTI2DSTI I DSTIO 0579 DST8 DST7 DST6 0575 DST4 DST3 DST2 DSTI DSTO R W R W R W R W R W R W R W R W R W R W R W R W undefined undefined undefined Jundefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AT2 AT2 AT2 AT2 AT2 AT2 AT2 AT2 IDST23IDST22 DST21 IDST20 DST19IDST18IDST17 DST 16 R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 406 MN102H55D 55G F55G AT2DST x 00FD28 ATC 2 Destination Address Pointer 16 24 bit access register AT2DST sets the transfer desti nation address When the desti nation pointer increment bit is set to be fixed the transfer source address do not change When the source pointer incre ment bit is set to increment in crement by 1 in the byte transfer and by 2 in the word transfer This register writes only 24 bit data or 16 bit data Use the MOV instruction or the MOVX instruction to set the data
246. 21 20 13 12 11 10 02 1 00 x OOFF80 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W External Memory 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 on Wait Register 16 bit access register 15 12 Wait Setting for External Memory Space 3 EXWMD sets the external memory wait cycles 11 8 Wait Setting for External Memory Space 2 Please refer to Figure 2 1 1 7 4 Wait Setting for External Memory Space 1 Address Space on page 52 for address allocation of external 3 0 Wait Setting for External Memory Space 0 memory spaces Setting Waits Cycles 0 0000 0 0 1 0 1 0001 0 5 1 5 2 0010 1 0 2 0 0 5 wait cycle corresponds to 3 0011 1 5 2 5 BOSC 1 cycle 1 wait cycle responds to 1 cycle of instruc 5 50 tion With 34 MHz oscillator 5 0101 2 5 3 5 0 5 wait cycle 29 4 ns 6 0110 3 0 4 0 1 wait cycle 58 8 ns 7 0111 3 5 4 5 8 1000 4 0 5 0 9 1001 4 5 5 5 10 1010 5 0 6 0 11 1011 5 5 6 5 12 1100 6 0 7 0 13 1101 6 5 7 5 14 1110 7 0 8 0 15 1111 perform handshake mode by WAIT pin MN102H55D 55G F55G 475 Chapter 11 Appendix 9 8 T 6 5 4 3 2 1 EB EB EB EB EB 31 30 21 20 11 EB 10 EB EB BRS BRS BRC BRC BRC BRC IOW 0l 00 1 0 3 2 1 0 1 IOW R W R W R W R W R W R W R
247. 2C 464 MN102H55D 55G F55G TM12CA 4 12 Capture Register 16 bit access register TM12CA sets the timer 12 counting cycle The timer 12 binary counter counts the cycle of the TM12CA value 1 TM12CA changes PWM and gen erates a timer 12 capture A inter rupt When capture is selected this reg ister is read only A timer 12 cap ture A interrupt is generated when capture occurs When compare is selected set the PWM cycle When this register matches the timer 12 binary counter a timer 12 capture A interrupt occurs This register write only 16 bit data Use the MOV instruction to set the data TM12CAX 6 12 Capture Register Set 16 bit access register This register is valid only when the associated compare register is set to the double buffer mode The TM12CAX cannot read or write The contents of TM12CA are loaded to TM12CAX by write signal TM12CAX sets the PWM cycle When TM12BC TM12CAX a timer 12 capture A interrupt oc curs The contents of TM12CA are loaded to TM12CAX by a timer 12 capture A interrupt and TM12CAX prevents the PWM loss This register writes only 16 bit data Use the MOV instruction to set the data Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM12CB 12 12 12 12 12
248. 3 PLU2 PLUI PLUO x OOFFB6 R W R W R W R W Port 6 Pullup UNS UM LARGE qe Control Register 0 0 0 on on 8 bit access register 3 0 Port 6 Pullup Resistor 0 Off P6PLU controls the port 6 pullup 1 resistor 7 6 5 4 3 2 1 0 P7PLU P7 P7 7 P2 P7 PLUS PLU4 PLU3 PLU2 PLU1 PLUO x 0O0FFB7 R W R W R W R W R W R W Port 7 Pullup Sape dedic SR E Control Register 8 bit access register 5 0 7 Pullup Resistor 0 Off 1 P7PLU controls the port 7 pullup resistor MN102H55D 55G F55G 487 Chapter 11 Appendix 7 6 5 4 3 2 1 0 ps P8 P8 P8 P8 P8 P8 P8 PLU7 PLU6 PLUS PLU4 PLU3 PLU2 PLUI PLUO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 on on 7 0 Port8 Pullup Resistor 0 Off 1 7 6 5 4 3 2 1 0 P9 P9 P9 P9 P9 P9 PLU7 PLU6 PLUS PLU4 PLU3 PLU2 PLUI PLUO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 on on on on 7 0 Port9 Pullup Resistor 0 Off 1 On 7 6 5 4
249. 3 2 1 0 T10C TIOC TIOC T10C TIOC T10C TIOC TIOC T10C TIOC T10C TIOC T10C T10C T10C 15 14 13 12 11 AXIO AX8 AX7 6 5 AX3 AX2 AXI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 460 MN102H55D 55G F55G TM10CA x OOFEA4 Timer 10 Compare Capture Register A 16 bit access register TM10CA sets the timer 10 counting cycle The timer 10 binary counter counts the cycle of the TM10CA value 1 TM10CA changes PWM and gen erates a timer 10 capture A inter rupt When capture is selected this reg ister is read only A timer 10 cap ture A interrupt is generated when capture occurs When compare is selected set the PWM cycle When this register matches the timer 10 binary counter a timer 10 capture A interrupt occurs This register write only 16 bit data Use the MOV instruction to set the data TM10CAX x OOFEA6 Timer 10 Compare Capture Register Set A 16 bit access register This register is valid only when the associated compare register is set to the double buffer mode The TM10CAX cannot read or write The contents of TM10CA are loaded to TM10CAX by write signal TM10CAX sets the PWM cycle When TM10BC TM10CAX a timer 10 capture A interrupt oc curs The contents of TM10CA are loaded to TM10CAX by a timer 10 capture A interrupt and TM10CAX prevents the PWM loss This register writes only 16 bit data Use the MOV i
250. 3 2 1 0 P6MD P6 P6 P6 P6 P6 P6 2 x OOFFFF R R R W R W R W R W R W Port 6 Mode Register Processor mode 16 bit 0 0 1 1 1 0 0 0 Processor mode 8 bit 0 0 0 1 1 0 I Other modes ololololo 0 8 bit access register 0 5 P63 Input Output Signal Switch 0 Port P6MD sets a signal output to the 1 WEH WE output port 6 4 P62 Input Output Signal Switch 0 Port 1 WEL output 3 P61 Input Output Signal Switch 0 Port 1 RE output 2 0 P60 Input Output Signal Switch 000 Port 001 WAIT input 010 SBT2 input cannot use P20 as SBT2 input 011 SBT2 output 100 SBT2 half duplex output 508 MN102H55D 55G F55G 5 4 3 2 1 P7 P7 P7 P7 P7 P7 P7 ILMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0O R R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6 5 P72 Input Output Signal Switch 43 71 Input Output Signal Switch 2 0 P70 Input Output Signal Switch 00 Port 01 SBOO output 10 UCAS output 00 Port 01 SBIO input 10 LCAS output 11 CAS output 000 Port 001 SBTO input 010 SBTO output 011 SBTO half duplex output 101 RAS output MN102H55D 55G F55G Chapter 11 Appendix P7LMD x O0FFFA Port 7 Mode Register L 8 bit access register P7LMD sets a signal output to the port 7 509 Chapter 1
251. 3 control register SC3CTR during the serial transmission end interrupt service routine SC3CTR x 00FD98 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 REN BRE PTL OD LN PTY2 PTY1 PTYO SB 51 50 1 1 0 0 1 1 1 1 1 0 1 0 0 1 Data Reception 2 Load the dummy data x FF to the serial 3 transmit receive buffer SC3TRB This starts master reception by setting SDA3 pin output to high 3 Retrieve the data by reading the SC3TRB register during the serial reception inter rupt service routine A serial transmission end interrupt can be served as a serial reception end interrupt 4 Load the dummy data x FF to the SC3TRB register if the next data is received continuously Stop Sequence 5 Write 0 to the 5 3 flag of the SC3CTR register to start the stop sequence 6 The stop sequence output makes the data reception in progress After the stop sequence is output disable the reception enable flag and initialize the reception Chapter 5 Serial Interface This step is not required when reception is enabled by the initial setting This step can be omitted if it is the same setting in transmis sion ACK is set by the parity bits To output 1 to ACK select 1 by the parity bits To output 0 to ACK select 0 by the parity bits To output none to ACK select none by the parity bits
252. 31 KH AD11 96 P30 AD12 97 29 4 P27 28 4 P26 27 4 P25 AD13 98 AD14 99 AD15 100 26 4 P24 TM15IA O O O WM C s D UV a NNN QI Q AN Qu s Q o m lt mjo Xxu s s a oao a GOO m 0 y m a m pe EB SSS ES 26 Ub Eug 2 m lt FFE Se TARA 1 z 5886 u m a BBE d 777 8 a Use 33 50 Figure 1 4 9 Pin Configuration in Processor Mode with 16 bit Bus Address Data Shared Mode Unused pins require handling in the circuit input pins are connected to VDD VSS output pins leave Open input output pins are connected to VDD VSS or leave open depending on pin direction setting MN102H55D 55G F55G 21 Chapter 1 General Description 1 4 10 List of Pin Functions Refer to 11 2 3 List of Pin Functions for each pin s input level and Schmidt avail ability TTL in the input level column means that the input is determined at TTL level CMOS in the input level column means that the input is determined at CMOS level The column with yes sign shows Schmidt while the column with no mark shows no Schmidt Pull up can be programmable with the pull up control registers Please refer to Chapter 8 Ports for details The unused pins require handling on the board The input pins are connected
253. 4 SLOW OSCI Halt CPU is stopped Program 1 OSCI Clock for high speed operation Sample programs for program 1 to program 5 are described on the following pages 286 MN102H55D 55G F55G XI Oscillation Program 2 Interrupt STOPO OSCI Halt XI SLOW Mode lt The oscillation stabilization wait is inserted XI Clock for low speed operation Program 2 Figure 10 1 1 CPU Operating Mode Changes STOP1 OSCI Halt XI The MN102H55D 55G F55G contains two oscillation circuits for system clock OSCI is the pin for high speed operation in NORMAL mode while XI is the pin for low speed operation in SLOW mode The CPU mode control register CPUM con trols the transitions between NORMAL mode and SLOW mode or from NORMAL SLOW mode to standby mode A normal reset or an interrupt recovers the CPU from standby mode The oscillation stabilization wait occurs when the CPU is reset or when the CPU returns from STOP mode The oscillation stabilization wait does not occur when the CPU returns from HALT mode when the CPU returns from standby mode NORMAL STOP mode becomes the state before the CPU enters the standby mode The current from pins and the input pin level must not be unstable to reduce power consumption in STOP mode or HALT mode For output pins either match the output level to the level input to this pin e
254. 4 PAO TM15IB Input 4 PA4 ADSEP Input 4 Note The set value of the PADIR register is valid only when the port function is selected by the PAMD register The input or output direction of interrupt and timer function is determined automatically by setting the PAMD register 274 MN102H55D 55G F55G Chapter 8 Ports Table 8 1 2 Port Block Diagram 12 12 Port Pin Name Block Diagram Port PBI to PBO 2 PBPLU 1 0 Register g BOSC XI PBOUT 1 0 Register gt XO BIBT1 Output PBO 8 elector BIBT2 Output PB0 gt BOSC Output PB0 PB1 PB0 PBMD 2 0 Register PBDIR 1 0 gt Register BIBT1 BIBT2 BOSC Output Control gt Selector PBO XI Input Control PB1 gt PBIN 1 0 4 e Port Input XI Input 4 Low speed Oscillation Input STOP Control XO Note The set value of the PBDIR register is valid only when the port function is selected by the PBMD register The input or output direction of BIBT1 BIBT2 BOSC and XI is determined automatically by setting the PBMD register The XI pin can be used as the port B1 when this pin is not used as the low speed oscillation pin MN102H55D 55G F55G 215
255. 4 7 6 5 4 3 2 1 0 TM4 TM4 TM4 TM4 TM4 BR7 6 BRS BR3 BR2 BRI BRO 0 1 0 1 1 1 1 1 TMSBR 00 15 7 6 5 4 3 2 1 0 TMS TMS TMS TMS TMS TM5 5 TM5 BR7 6 BRS BR4 BR3 BR2 BRI BRO 1 1 1 0 1 0 1 0 8 Load TM4BR value to the timer 4 binary counter TM4BC the timer 5 binary counter 5 respectively At the same time select the timer 0 underflow and the timer 4 cascade as the clock source for timer 4 and timer 5 respectively x 00FE24 7 6 5 4 3 2 1 0 TM4 TM4 TM4 TM4 EN LD 51 50 0 1 0 1 TMSMD x 00FE25 7 6 5 4 3 2 1 0 TMS 5 TMS 5 EN LD 51 50 0 1 1 0 9 Set TMSLD to 0 5 to 1 TM4LD to 0 and TM4EN to 1 This starts the timer Counting begins at the start of the next cycle When both TM4BC value and 5 value reach 0 and the values from TM4BR register and register are loaded at the next count a timer 5 underflow inter rupt request will be sent to the CPU The timer 4 underflow interrupt request can not be used Chapter 4 Timers Setting TMOEN and TMOLD to 0 is required between 8 and 9 in the bank address version and the linear address version but this setting is not required in the linea
256. 4 SRC3 SRC2 SRC1 SRCO x R W R W R W R W R W R W R W R W R W R W R W ATC 2 Sou rce undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address Pointer 16 24 bit access register 15 14 13 12 11 10 9 8 7 6 5 4 9 2 1 0 AT2SRC sets the transfer source address When the source pointer increment bit is set to be fixed the transfer source address do not change When the source pointer incre ment bit is set to increment in crement by 1 in the byte transfer and by 2 in the word transfer AT2 AT2 AT2 AT2 AT2 AT2 AT2 2 SRC23SRC22SRC2ISRC2OSRCIO9SRCISSRCIT7SRCI R W R W R W R W R W R W R W R W undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 This register writes only 24 bit data or 16 bit data Use the MOV instruction or the MOVX instruction to set the data MN102H55D 55G F55G 405 Chapter 11 Appendix 15 14 13 1
257. 4 8 bit PWM Em P5 Pulse Width Counter RAM PB Figure 5 2 1 Asynchronous Transmission Block Diagram Data transmission starts when the data is written to the serial 3 transmit receive buffer SC3TRB The transmission starts synchronizing with timer 5 underflow When an interrupt occurs the SC3TRB register is cleared and then the next data is written to the SC3TRB register If polling the data must be written to the SC3TRB register after verifying that the SC3TBY flag of the serial 3 status register SC3STR is 0 MN102H55D 55G F55G 197 Chapter 5 Serial Interface Setting the P8MMD to SBO3 output slects the P84 direction to output Setting the port 8 control register P8DIR is not required P8DIR operates only when it is used as the port input or output 198 MN102H55D 55G F55G Port Setting 1 Set PPMMD 4 2 flags of the port 8 mode control register P8MMD to 011 This setting allows to output SBOO of serial interface P8MMD x 00FFFD 7 6 5 4 3 2 1 0 8 8 8 8 8 8 8 8 MMD7 MMD6 MMD5 MMD4 MMD3 MMD2 MMD 1 MMDO 0 0 0 1 1 Serial Interface Setting 1 Select timer 5 underflow 1 8 as the serial 3 clock source because the transfer base clock is 1 8 of timer 5 Select asynchronous mode odd parity two stop bits 8 bit transmission and LSB first bit order Set the SC3REN and SC3TEN flags of the serial 3 cont
258. 5 O 101205 H ILZOS 71914298 HOIHZOS 6 6 101608 HOLLEOS 6 6 7914595 05 060300 1210 O OINSWL HOINSWL O TOINZHNL HOINZ LL TOW HALLIHOTVE LL TOINZINL HOINZINL O 082 00 O O TOIBOHWL HOISOLWL 30IQ E LALLIHOTQ E LAL O HOIDI TOINSWL HOINSWL 0 TONE LALLIHONW LAL O O TOIL HAL 1020500 121201 HOIcOI O TOINZWL TOIVENL HOIV6WL O TOI86NW1 HOIB6IALL O O H IEOI TOINEWL HOINEWL O TOINOLWLL HOINO HANLI TOIVOLALL O 092 00 121001 HOIOOI 6 OINOWL HOINOWL 0 HOINSWL TONSIL HOIWSWL O TOMO O 8 HOIGSIALL 6 TOINGWL 080400 X 1 O YOINN DNE HOll3 pewesei O p m s p m s 072 00 0407 ndo 1 1 1 3933 dew sseppy 5664 9SS QSSH2OLNIN Z Z LL peAleseal 1 002 00 sug 9 7 MN102H55D 55G F55G 518 peioejes
259. 5 4 3 2 1 0 2 TM6U IE R R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 6 Underflow Interrupt Enable Flag 370 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 Interrupt undetected 1 Interrupt detected 0 Disable 1 Enable TM6UICL x 00FC82 Timer 6 Underflow Interrupt Control Register 8 bit access register TM6UICL requests and verifies a timer 6 interrupt This register allows only byte accesses Use the MOVB in struction to set the data TM6UICH x 00FC83 Timer 6 Underflow Interrupt Control Register 8 bit access register TM6UICH enables a timer 6 in terrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the ADLV 2 0 bits of the ADICH register Chapter 11 Appendix ee TM12UICL 00 84 Timer 12 Underflow 0 0 0 0 0 0 0 Interrupt Control Register 8 bit access register Timer 12 Underflow Interrupt 0 No interrupt requested TM12UICL requests and veri Request Flag 1 Interrupt requested fies a timer 12 interrupt Timer 12 Underflow Interrupt 0 Interrupt undetected This register allows only byte Detect Flag 1 Interrupt detected accesses Use the MOVB in struction to set the data
260. 5 P37 A14 P36 13 5 A12 P34 4 4 AVDD A11 P33 4 10 32 4 A9 P31 A8 P30 KIO gt A7 P27 A6 P26 gt A5 P25 lt 4 24 N iQ G G j gt HHH HHA O G O O O G Q O N o orn IO O O O C 0 ee QI QN GQ G lt zac m a tu pe PEO Op ir m r 500 mQ m 09 lt BISEREE oO TRON E YBBR Sea e Z lo IO lO IO lt lt I amp 588 m LEA 8 E m Use 33 50 Figure 1 4 3 Pin Configuration Memory Expansion Mode with 16 bit Bus Address Data Separate Mode Unused pins require handling in the circuit input pins are connected to VDD VSS output pins leave Open input output pins are connected to VDD VSS or leave open depending on pin direction setting MN102H55D 55G F55G 15 Chapter 1 General Description 1 4 4 Memory Expansion Mode with 8 bit Bus Address Data Shared Mode o Sp g lt 2 52 a Z oa lt lt Q A x o lt Eo e 5 Ww 5 m 5 amp
261. 55G F AC Characteristics 3 0 V to 3 6 V Input Timing Conditions E 0V lt lt C to 85 C Capactance Parameter Symbol Conditions Unit ae External Clock Input Timing Fosc1 30 MHz external clock input high pulse External clock input low pulse width fe Reset Input Timing Reset signal pulse width RST Fig 11 1 2 Power Rise Timing 3 2 Note VDD VPP setup time tVDP is the capacitance only for MN102HF55G Input Timing Conditions Data Transfer Signal Input Timing 8 Data acknowledge signal setup time tws WAIT Fig 11 1 5 9 Data acknowledge signal hold time twa Fig 11 1 9 WAIT Data Transfer Signal Input Timing Capacitance Parameter Symbol Conditions F10 Read data setup time D15 00 Read data hold time D15 00 Bus Authority Request Input Timing Bus authority request signal setup time F12 BREQS fa BREQ Fig 11 1 12 Bus authority request signal hold time BREQH Interrupt Signal Input Timing Nonmaskable interrupt signal pulse 10 NMI Dus Fig 11 1 13 Note External interrupt signal pulse width IRQ4 0 Note An interrupt may occur when the noise of the specified time or less is input SRE means RE short mode Sre 0 0 5 1 1 5 Voo 3 0 V to 3 6 V Vss 0 V Ta 40 C to 85 C l po t Note 11 MN102H55D
262. 55G Chapter 11 Appendix ATS3CTR x 00FD30 ATC 3 Control Register 16 bit access register sets the ATC3 operat ing control conditions Selecting the two bytes transfer mode is valid only in byte ac cess The LSB of the address in the first byte forcibly becomes 0 and the LSB of the address in the second byte forcibly be comes 1 Selecting word as the unit is not allowed when 8 bit bus width is allowed in the external memory space Selecting 8 bit destination bus width or 8 bit source bus width is allowed only when 8 bit bus width is selected in the external memory space When destination pointer incre ment or source pointer incre ment is selected the pointer in crements by 1 in byte access and by 2 in word access 3 0 bits are cleared to 0 by the ATC3 transfer end in terrupt 407 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AT3 AT3 AT3 AT3 AT3 AT3 AT3 AT3 AT3 AT3 AT3 AT3 1 CNT8 CNT7 CNT6 CNTS CNT4 CNT3 CNT2 CNTI CNTO R R R R R W R W R W R W R W R W R W 0 0 0 0 undefined undefined undefined undefined undefined undefined undef
263. 55G F55G 319 Chapter 11 Appendix 3 0 V to 3 6 V Input Timing Conditions Vss 0 V NN 40 C to 85 Capactance Parameter Symbol Conditions Serial Interface Related Signal Timing Synchronous Serial Reception F16 Data reception setup time SBI4 0 trxps Flg 11 1 17 Transfer clock input high pulse width 18 icycx4 SBT4 0 Fig 11 1 16 Fig 11 1 17 re iy roe opa wen e de Input Timing Timer external input clock low pulse width n 0 4 7 iun TMNIOB TMnIC n 8 12 Timer external input clock high pulse width n 0 4 7 TMnIOB TMnIC n 8 12 TMnIA TMnIB n 13 15 320 MN102H55D 55G F55G AC Characteristics Output Vpp 3 0 V to 3 6 V Output Signal Characteristics Vss 0 V 40 C to 85 E pF Capactance Parameter Symbol Conditions Unit Ed System Clock Output Timing System clock output cycle time BOSC 33 3 ns DEME tell e TE Te Chapter 11 Appendix MN102H55D 55G F55G 321 Chapter 11 Appendix 3 0 V to 3 6 V Output Signal Characteristics Vss 0 V Ta 40 C to 85 C CL 2 70 pF Parameter Symbol Conditions Unit EXE AES Data Transfer Signal Output Timing 1 Fig 11 1 4 Fig 11 1 5 Fig 11 1 8 to 11 Address hold time 1 A23 0 A23 16 Fig
264. 5G Chapter 11 Appendix WEEDGE x OOFF88 WE Waveform Control Register 16 bit access register WEEDGE sets the WE wave form control modes 481 Chapter 11 Appendix I 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALEG ALEG ALEL ALEL ALEG ALEG ALEL ALEL ALEG ALEG ALEL ALEL ALEG ALEG ALEL ALEL 31 30 31 30 21 20 21 2 10 10 01 00 01 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 on on on on on o1 on on on 15 14 ALE Long Mode 00 ALE Long 0 Mode Reset in CS3 Space 01 ALE Long 0 5 Mode 10 ALE Long 1 Mode 11 ALE Long 1 5 Mode 13 12 ALE Late Mode 00 ALE Late 0 Mode Reset in CS3 Space 01 ALE Late 0 5 Mode 10 ALE Late 1 Mode 11 ALE Late 1 5 Mode 11 10 ALE Long Mode 00 ALE Long 0 Mode Reset in CS2 Space 01 ALE Long 0 5 Mode 10 ALE Long 1 Mode 11 ALE Long 1 5 Mode 9 8 ALE Late Mode 00 ALE Late 0 Mode Reset in CS2 Space 01 ALE Late 0 5 Mode 10 ALE Late 1 Mode 11 ALE Late 1 5 Mode 7 6 ALE Long Mode 00 ALE Long 0 Mode Reset in CS1 Space 01 ALE Long 0 5 Mode 10 ALE Long 1 Mode 11 ALE Long 1 5 Mode 5 4 ALE Late Mode 00 ALE Late 0 Mode Reset in CS1 Space 01 ALE Late 0 5 Mode 10 ALE Late 1 Mode 11 ALE Late 1 5 Mode 3 2 ALE Long
265. 5G 235 Chapter 7 ATC ETC 236 Table 7 1 2 List of ATC Control Registers Register Address Function ATOCTR x 00FDO0 ATC 0 Control Register ATCO ATOCNT 00 02 ATC 0 Transfer Word Count Register ATOSRC x 00FD04 ATC 0 Source Address Pointer ATODST 00 08 0 Destination Address Pointer ATICTR x 00FD 10 ATC 1 Control Register ATCI ATICNT x 00FD12 ATC 1 Transfer Word Count Register ATISRC 00 14 ATC 1 Source Address Pointer ATIDST 00 18 ATC 1 Destination Address Pointer AT2CTR x 00FD20 ATC 2 Control Register AT2CNT x 00FD22 ATC 2 Transfer Word Count Register AT2SRC x 00FD24 ATC 2 Source Address Pointer AT2DST x 00FD28 ATC 2 Destination Address Pointer AT3CTR x 00FD30 ATC 3 Control Register ATC3 AT3CNT x 00FD32 ATC 3 Transfer Word Count Register AT3SRC 00 034 ATC 3 Source Address Pointer AT3DST 00 038 ATC 3 Destination Address Pointer MN102H55D 55G F55G 7 2 7 2 1 ATC Setup Examples Serial Reception The serial interface 0 receives the 5 byte data After the serial reception is completed ATC reads the data using the serial reception buffer and writes the data on the memory After that ATC generates an interrupt and starts software processing Figure 7 2 1 ATC Serial Reception Block Diagram PO CORE D A Converter P6 P1 Interrupt A
266. 6 5 4 3 2 1 0 ATO i 7 JSRC23SRC22 SRC21 SRC2O SRCIO SRCISSSRCI7 SRCIO 0 0 0 0 0 0 0 0 2 Secure the space for the 5 byte serial 0 reception data Set the first address of the secured space to the ATCO destination address pointer ATODST ATODST x 00FD08 008000 to 008004 teta 8 1 391 0 ATO ATO ATO ATO ATO DST15 DST14 DST13 DST12 DST11 DST10 DST9 DST8 DST7 DST6 DST5 DST4 DST3 DST2 DST 1 DSTO 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O 15 14 13 12 11 110 9 8 7 6 5 4 2 1 ATO 7 7 i 7 7 DSI23 DST22 DST21 DST20DSTI9 DSTIS DSTI7 DSTI6 0 0 0 0 O 3 Set the bytes to be transferred automatically In this example 5 byte data is trans ferred so that the value 4 subtracting 5 by 1 is set to the ATCO transfer word count register ATOCNT 238 MN102H55D 55G F55G ATOCNT x 00FD02 11 10 0 ATO CNT11 0 ATO CNT10 0 ATO CNT9 0 ATO CNT8 0 ATO CNT7 0 ATO CNT6 ATO 5 0 CNT4 ATO CNT3 ATO CNT2 ATO CNTI ATO CNTO 0
267. 6 A5 P36 A14 A6 A5 A4 P35 A13 A5 A4 A3 P34 A12 A4 A3 A2 P33 A11 A3 A2 A1 P32 A10 A2 A1 AO P31 AQ A1 AO A0 P30 A8 AO 0 DRAM Operation for External Memory Space 3 0 0 Disable 1 Enable Please refer to Figure 2 1 1 Memory Space on page 52 for address allocation of the external memory spaces 56 MN102HF55G H55G H55D Chapter 2 Bus Interface The DRAMMD2 register sets the DRAM refresh operation the refresh timing and the access method DRAMMD2 x 00FF92 15 14 13 2 11 10 9 8 7 6 5 4 3 2 1 0 DRAMDRAMreserv reserv RON IRCY3IRCY2 RCY1 RCYORCS2 RCS1 RCSORRS2IRRS1RRSO ACC TM ed ed ed Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRS 2 0 Timing Setting of the RAS s Falling Edge at Refresh At the beginning of 0 5 At the beginning of 1 0 At the beginning of 1 5 At the beginning of 2 0 At the beginning of 2 5 At the beginning of 3 0 At the beginning of 3 5 At the beginning of 4 0 at Refresh At the beginning of 0 5 RCS 2 0 Timing Setting of the CAS s Falling Edge At the beginning of 1 0 At the beginning of 1 5 At the beginning of 2 0 At the beginning of 2 5 At the beginning of 3 0 At the beginning of 3 5 At the b
268. 6 bit 1 8 bit 8 Source Pointer Increment 0 Fixed 1 Increment 1 Transfer Direction 0 External device external memory 1 External memory external device 0 ETC Transfer Enable 0 Disable 1 Enable MN102H55D 55G F55G Chapter 11 Appendix x 00FD50 ETC 1 Control Register 16 bit access register ET1CTR sets the ETC1 operat ing control conditions Trans fers the data automatically be tween the external device with ACK input function and the ex ternal memory Selecting word as the unit is not allowed when 8 bit bus width is allowed in the external memory space Selecting 8 bit destination bus width or 8 bit source bus width is allowed only when 8 bit bus width is selected in the external memory space When destination pointer incre ment or source pointer incre ment is selected the pointer in crements by 1 in byte access and by 2 in word access The ET1EN flag is cleared to 0 by the ETC1 transfer end inter rupt 413 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT11CNT10 CNT9 CNT8 CNT7 CNT6 CNTS CNT4 CNT3 CNT2 CNTI CNTO R R R R R W R W
269. 6 bit Timer Control Registers 132 4 3 3 16 bit Timer Block Diagrams 1 135 16 bit Timer Setup Examples sss 137 4 4 1 Event Counter Using 16 bit Timer 137 4 4 2 One phase PWM Output Using 16 bit Timer 140 4 4 3 Two phase PWM Output Using 16 bit Timer 145 4 4 4 One phase Capture Output Using 16 bit Timer 151 4 5 4 6 4 7 4 8 4 4 5 Two phase Capture Input Using 16 bit Timer 154 4 4 6 Two phase Encoder Input 4x Using 16 bit Timer 158 4 4 7 Two phase Encoder Input 1x Using 16 bit Timer 161 4 4 8 One shot Pulse Using 16 bit Timer 164 4 4 9 External Count Direction Control Using 16 bit Timer 167 4 4 10 External Reset Control Using 16 bit Timer 170 Summary of 8 bit PWM Functions sees 173 4 5 1 Ee edi E LIAE 173 4 5 2 Control Registers serisini ukllak qan aaa q diaa 175 8 bit PWM Setup Examples 177 4 6 1 8 bit PWM Output 2 177 16 bit Pulse Width Measure Functions 181 4 7 1 OVOIVIBW i cer t 181 4 7 2 Control Registers 183 16 bit Pulse
270. 6 h imm24 imm24 l imm24 m imm24 h d8 416 d16 l d16 h d24 d24 l d24 m d24 h abs16 0516 abs16 h abs24 0524 abs24 m abs24 h 8 mem8 abs16 mem8 abs24 mem16 An mem16 abs16 mem16 abs24 24 mem24 abs16 mem24 abs24 bp Isb msb amp 1 lt lt VX CX NX ZX VF CF NF ZF temp gt en H M W OP EX Operand Extension zero extension 5 sign extension applicable E Cycle The minimum number cycles are specified Unit machine cycle a b there are branches in the a cycle there are no branches in the b cycle Notes Quick decoder ON This setting cannot be made in this series Ver 2 01 2000 5 16 Data register Address register Multiplication and division register program status word program counter Constant Displacement Absolute address 8 bit memory data referenced at the address enclosed in parenthesis 16 bit memory data referenced at the address enclosed in parenthesis 24 bit memory data referenced at the address enclosed in parenthesis Bit specification Logical AND logical OR exclusive OR Bit reversal bit shift Extended overflow flag extended carry flag extended negative flag extended zero flag Overflow flag carry flag negative flag zero flag Temporary register inside CPU Assignment reflection of computation results High speed Multiplication
271. 6IMMDS5MMD4MMD3 MMD2MMDIMMDO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 5 P85 Input Output Signal Switch 4 2 P84 Input Output Signal Switch 1 0 P83 Input Output Signal Switch 512 MN102H55D 55G F55G 000 Port 001 TM9IOA input SBT4 input 010 TM9IOA output 011 SBT4 output 100 SBT4 half duplex output 101 SCL4 open drain output 110 SBO2 output 000 Port 001 TM7IO input 010 TM7IO output 011 SBO3 output 100 SBD3 open drain input output 00 Port 01 TM4IO input input 10 TM4IO output 11 Reserved P8MMD x OOFFFD Port 8 Mode Register M 8 bit access register P8MMD sets a signal output to the port 8 2 1 8 8 P8 P8 IHMD3HMD2HMDI HMDO R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 3 2 P87 Input Output Signal Switch 1 0 P86 Input Output Signal Switch 00 Port 01 SBO4 output 10 SBD4 open drain output SBD4 input 11 input 00 Port 01 TMSIOB input SBI4 input 10 TM9IOB output Chapter 11 Appendix P8HMD x OOFFFE Port 8 Mode Register H 8 bit access register P8HMD sets a signal output to the port 8 MN102H55D 55G F55G 513 Chapter 11 Appendix P9 LMD7 P9 LMD6 P9 LMD5 P9 LMD4 P9 LMD3 P9 LMDI P9 LMDO R W R W R W R W R W R W R W
272. 6LMD5LMDAILMD3LMD2LMDI LMDO HMD7HMD6HMD5HMD4HMD3HMD2HMDIHMDO 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 2 Set the port 3 input output control register P3DIR to the I O direction Set P37 P34 pins to output P33 P30 pins are selected as input regardless of the set value of P3DIR because these pins are set to KI input by the port 3 mode register L PSDIR x 00FFE3 7 6 5 4 3 2 1 0 P3 DIR7 DIR6 DIR5 DIRA DIR3 DIR2 DIR1 DIRO 1 1 1 1 0 0 0 0 3 Set P33 P30 pins to pull up by the port 3 pull up control register P3PUL not to generate an interrupt when the key is not pushed Set P37 P34 pins to output low to generate an interrupt when one of any keys is pushed Generate a key interrupt signal when any of P33 P30 pins becomes 0 if one of keys is pushed P3PUL x 00FFB3 x 00FFC3 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 P3 P3 P3 P3 P3 PLU7 PLU6 PLUS PLU4 PLU3 PLU2 PLU1 PLUO OUT7OUTGOUTS OUTAOUT3OUT2JUTI OUTO 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 4 Set the key input pin to low by the KEYTRG register Enable P33 P30 key interrupts of the KEYCTR register KEYTRG x 00FCB2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
273. 7 6 5 4 3 2 1 0 EN LD 51 50 0 1 0 0 4 Set TMOLD to 0 and TMOEN to 1 This starts the timer Counting begins at start of the next cycle When TMOBC reaches 0 and the value 1 from the TMOBR register is loaded at the next count a timer 0 underflow interrupt request will be sent to the CPU Chapter 4 Timers This verification is unnecessary after a reset Setting TMOEN and TMOLD to 0 is required between 3 and 4 in the bank address version and the linear address version but this setting is not required in the linear address high speed ver sion Do not change the clock source once you have selected it Selecting the clock source while setting the count operation con trol will corrupt the value in the binary counter MN102H55D 55G F55G 155 Chapter 4 Timers 1 Use the MOV instruction to set the data and only use 16 bit write operations The timer 8 binary counter TM8BC is stopped and TM8BC register and RS F F are initialized cleared to 0 1 If this setting is omitted the bi nary counter may not count the first cycle Do not change to any other operating modes When TM8MDO 0 TM8MD1 1 in capture mode TM8CA and TM8CB become read only registers If 8 must be set TM8MDO and TM8MD1 must be set to 0 156 MN102H55D 55G F55G Timer 8 Setting 1 Set the operating mode
274. 8 7 pin P3 16 bit Timer ATC P9 P4 8bitPWM 5 Pulse Wdith Counter ROM RAM PB Figure 4 2 4 Clock Output Block Diagram 8 bit Timer Port Setting 1 Set TM7IO P84 of the port 8 to timer output Set PPMMD 4 2 flags of the port 8 mode control register P8MMD to 010 TM7IO output With this setting the direction control of P84 switches to output P8MMD x 00FFFD 7 6 5 4 3 2 1 0 8 8 8 8 8 8 8 8 MMD7 MMD6 MMD5 MMD4 MMD3 MMD2 MMD1 MMDO 0 0 0 1 0 Chapter 4 Timers Setting the port 8 control reg ister P8DIR is not required P8DIR operates only when it is used as the port input or output MN102H55D 55G F55G 119 Chapter 4 Timers This verification is unnecessary after a reset Setting TMOEN and TMOLD to 0 is required between 4 and 5 in the bank address version and the linear address version but this setting is not required in the linear address high speed ver sion 1 Do not change the clock source once you have selected it Selecting the clock source while setting the count operation con trol will corrupt the value in the binary counter This verification is unnecessary after a reset 120 MN102H55D 55G F55G Timer 0 Setting 2 Verify that timer 0 counting is stopped with the timer 0 mode register TMOMD TMOMD x 00FE20 7 6 5 4 3 2 1 0
275. A P5 Pulse Width Counter ROM RAM PB Figure 5 2 3 Synchronous Reception Block Diagram 200 MN102H55D 55G F55G In synchronous mode the data input from the SBIn pin is received synchronizing with the SBTn pin and the received data is stored into the serial n transmit receive buffer SCnTRB The SBTn clock is generated in transmitter or receiver When the SBTn clock is generated in transmitter the clock is transferred to the receiver through the SBTn pin as soon as the transmitted data is written to the SCnTRB register On the other hand when the SBTn clock is generated in receiver the dummy data must be written to the SCnTRB register in the receiver after writing the transmitted data into the SCnTRB register in the transmitter The reason for the dummy data requirement is because the clock is generated as soon as the data is written to the SCnTRB register 1 Generate SBTn Clock in Transmitter Write transmitted data Read received data Y SCnTRB SCnTRB am SCnTRB Clock Generation SBTn SBTn Transmitter Receiver 2 Generate SBTn Clock in Receiver Read received data after Write transmitted data writing dummy data SCnTRB gt SBOn SBin n SBTn SBTn Clock Generation Transmitter Receiver Figure 5 2 4 Clock Generation in Synchronous Reception Chapter 5 Serial Interface
276. A23 A16 A23 16 X A23 16 X 23 16 C 23 16 X A23 16 X A236 AD15 ADO A15 0 15 0 015 0 15 0 X 15 0 15 0 YAT50X D15 0 8 bit H side ALE valid output D138 valid output Data Write RE WER IAS pese ees WEL A23 A16 742316 72316 X A28 16 CR28 18 X 2316 AD15 AD0 C 15 0 5 0 015 A15 0 150 50 D50 A150 8 bit L side ALE TTN D7 0 vag output rin van Data Write RE I i i WER Szu WEL AE SCR A28 A16 A28 16 last C 23 16 Holdthelast p AD15 ADOC output address A150 output address TT ALE REA ae No Access Tu CE ME EE WEL WE UE NE EE No external access internal ROM RAM access Internal peripheral register access External Wait WAIT next don t are wait next don t care A23 A16 DNO dx ore AD15 AD0C 150 ca coder Mpeg dese ecc I laic S SK E EE M RE p q ne LINES NN Bus Request a s Eum BRACK 7 E 68 MN102HF55G H55G H55D Chapter 2 Bus Interface 1 Wait The length of wait cycle can be set in 0 5 cycle units
277. A8 and B8 are internal control signals Chapter 4 Timers Figure 4 4 7 shows the TM8IOA pin and TM8IOB pin output waveforms when TM8CA 4 A capture A interrupt a capture B interrupt occur Both interrupts occur at the start of the next cycle when TM8CA and TM8CB match A capture B interrupt occurs only when TM8CB is set to 0 to TM8CA and does not occur when TMSCB is set to any other value TM8BC and the value cannot be matched TM8MD write sere eee este TM8BC 0 o 1 2 BOSC 2 CLRBC8 oe eee eae ee When 8 2 25 1p Soc que Who ire Q x TMBIOA HEY 4 ee C 03 Figure 4 4 7 Two phase PWM Output Timing 16 bit Timer MN102H55D 55G F55G 149 Chapter 4 Timers When outputting the PWM waveform the timer may change the duty of the PWM output dynamically The PWM waveform may be corrupted and interrupts are lost depending on the timing of changing the duty dynamically in the single buffer mode on the figure below In the double buffer mode the duty can be changed from the next cycle and the PWM loss does not occur at any timing of changin
278. AR R 14 0 0 0 0 0 0 0 0 on Counter 8 bit access register 16 bit access is possible from even address TM14BC operates timer 14 counting MN102H55D 55G F55G 435 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 15 15 15 15 15 15 15 15 TM15 15 15 TMI5 TMIS TMIS TMI5 5 BC14 BC13 BC12 BCII BCIO BC8 7 BC6 5 BC4 BC3 BC2 BCO R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 436 MN102H55D 55G F55G TM15BC x O0FED2 Timer 15 Binary Counter 16 bit access register TM15BC operates timer 15 counting TM15BC is cleared on the rising of TM15IA pin Chapter 11 Appendix KA 6 5 4 3 2 1 0 T M 0 B R TMO TMO TMO TMO TMO TMO TMO BR7 6 BRS BR4 BR3 BR2 BRI BRO x 0 0 F E 1 0 R W R W R W R W 0 Register 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 bit access register TMOBR sets the timer 0 count ing cycle TMOBR sets the counting cycle 1 to 256 The timer 0 binary counter counts the cycl
279. Analog CMOS 50 P82 TM2IO Analog CMOS CMOS CMOS CMOS Yes Yes Yes Programmab Z i Z Programmab H H H H Hi Z A A A20 A A21 A Z at A23 Hi Z Hi Z Hi Z 520 MN102H55D 55G F55G Chapter 11 Appendix 51 P83 TM3IO TTL CMOS Yes Programmable Hi Z Hi Z Hi Z 52 P84 TM4IO Yes Programmable Hi Z Hi Z Hi Z 53 P85 TMSIO Yes Programmable Hi Z Hi Z Hi Z Vref P86 TM6IOA TTL CMOS Programmable Hi Z Hi Z 87 6 CMOS Programmable i Hi Z Hi Z 58 91 7 TTL CMOS Yes Programmable Hi Z Hi Z Hi Z 59 P92 TM7IOB Yes Programmable Hi Z Hi Z Hi Z 60 P93 TM7IC Yes Programmable Hi Z Hi Z Hi Z 62 P94 ANO Analog CMOS CMOS Yes Programmable Hi Z Hi Z Hi Z 63 P95 AN1 CMOS Yes Programmable Hi Z Hi Z Hi Z 66 VDD VPP 67 P70 SBTO Yes Programmable Hi Z Hi Z Hi Z 69 72 8800 Yes Programmable Hi Z Hi Z Hi Z 70 P73 SBT1 TTL CMOS Yes Programmable Hi Z Hi Z Hi Z 71 P74 SBI1 Yes Programmable Hi Z Hi Z Hi Z Yes Programmable Hi Z Hi Z Hi Z me 74 Pull up 2 75 CMOS Yes No NMI NMI NMI NMI NMI 76 PAQ IRQO TTL Yes Programmable Hi Z Hi Z Hi Z 77 PA1 IRQ1 TTL Yes Programmable Hi Z Hi Z Hi Z 78 PA2 IRQ2 TTL CMOS Yes Programmable Hi Z Hi Z Hi Z
280. Application General purpose 16 bit microcontroller Pin Configuration Figure 1 4 1 to Figure 1 4 9 External Dimensions Figure 1 4 14 A Absolute Maximum Ratings Vss 0V Power supply voltage 0 3 to 4 6 voltage Input pin voltage 0 3 to 0 3 Output pin voltage 0 3 to 0 3 voltage temperature Storage temperature 55 to 125 Note 1 Absolute Maximum Ratings are stress ratings not to cause damage to the device Operation at these ratings is not guaranteed 2 All of the Vpp and Vss pins are external pins Connect them directly to the power source and ground 3 To prevent latch up tolerance connect more than one by pass condenser between power supply pins and ground Use at least 0 2 condenser Operating Conditions Vss 0 V 40 C to 85 Parameter Symbol Conditions Unit Crystal Oscillator 1 Crystal Oscillator 2 pee eI Operating Conditions for Flash EEPROM Version E OV Capacitance Parameter Symbol Conditions Unit Vpp power supply Operating ambient fe fst e Programming sme Chapter 11 Appendix MN102H55D 55G F55G 311 Chapter 11 Appendix C Electrical Characteristics 1 DC Characteristics Vpp 3 3 V Vss 0V 40 C to 85 C Parameter Symbol Conditions or Vss Power supply current during operation 101 1 3
281. B An Am Am An Am F2 50 An lt lt 2 Am SUB imm16 Dn Dn imm16 Dn F7 1C Dn imm16 l imm16 h SUB imm24 Dn Dn imm24 Dn F4 68 Dn imm24 l imm24 m imm24 h SUB imm16 An An imm16 An F7 0C An imm16 l imm16 h SUB imm24 An 24 F4 6C An imm24 l imm24 m imm24 h SUBC Dn Dm Dm Dn CF gt Dm NI O N lt NS ee F2 90 Dn lt lt 2 Dm MUL Dn Dm Dm Dn gt Dm Dm 16 A NINI N N N N e A F3 40 Dn lt lt 2 Dm 712 ULU Dn Dm Dm Dn gt Dm Dm 16 A F3 50 Dn lt lt 2 Dm MULQ Dn Dm Dm Dn Dm H M Dm Dn gt gt 16 gt MDR F5 60 Dn lt lt 2 Dm 10 ULQL Dn Dm Dm Dn Dm F5 40 Dn lt lt 2 Dm 00 ULQL imm8 Dn Dn imm8 Dn F5 F0 Dn 04 imm8s ULQL imm16 Dn Dn imm16 Dn F5 F4 Dn 08 imm16 l imm16 h ULQH Dn Dm Dm Dn 16 Dm H M F5 40 Dn lt lt 2 Dm 01 ULQH imm8 Dn Dn imm8 gt gt 16 Dn H M F5 F0 Dn 05 imm8 amp M M M M M M ULQH imm16 Dn imm16 gt gt 16 Dn H M F5 F4 Dn 09 imm16 l imm16 h DIVU Dn Dm MDR 16
282. BI2 P2OUT 7 0 Register gt 15 1 Address Output gt Selector A07 A00 SBT2 Output P20 5802 Output P22 P2MD7 5 2 0 Register P2DIR 7 0 Register gt gt e 27 20 Address Output Control gt Selector SBT2 Input Output Control P20 SBI2 Input Control P21 SBO2 Output Control P22 i TM151A Input Control P24 P2IN 7 0 4 e Port Input T P6MD 2 0 SBT2 Input P60 Pin 21 P8LMD 4 2 SBI2 Input pgp P82 Pin P24 2 P5HMD 42 TMASIA Input 56 Pin Note The set value of the register is valid only when the port function is selected by the P2MD register The input or output direction SBT2 SBI2 SBO2 and TM151A is determined by setting the P2MD register 266 MN102H55D 55G F55G Table 8 1 2 Port Block Diagram 4 12 Chapter 8 Ports Port Pin Name Block Diagram Port 3 P37 to P30 15 to 08 KI7 to KIO P3PLU 7 0 P3OUT 7 0 Address Output A15 A08 P3LMD 7 0 P3HMD 7 0 P3DIR 7 0 Address Output Control P3IN 7 0 Port Input Key Input Interrupt Note The set value of the P3DIR register is valid only when the port function 4 Register gt Register Selector gt gt Register
283. BO1 Output Serial Interface 1 This pin can be used as a data output pin for serial interface Data Output 1 Refer to Chapter 5 Serial Interface 48 P80 VO General purpose Port 80 This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports DACO Output D A Converter 0 Conver This pin can be used as a pin to output the D A conversion sion Output results Refer to 6 3 Summary of D A Converter 49 P81 VO General purpose Port 81 This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports DAC1 Output D A Converter 1 Conver This pin can be used as a pin to output the D A conversion results Refer to 6 3 Summary of D A Converter 40 MN102H55D 55G F55G Chapter 1 General Description Table 1 4 1 List of Pin Functions 20 26 Pin Number Pin Name Function Description 50 P82 General purpose Port 82 This can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports TMOIO Timer 0 Input Output This pin can be used as a timer 0 input output pin Refer to Chapter 4 Timers SBl2 Input Seri
284. C TM8CAX a timer 8 capture A interrupt oc curs The contents of TM8CA are loaded to TM8CAX by a timer 8 capture A interrupt and TM8CAX prevents the PWM loss This register writes only 16 bit data Use the MOV instruction to set the data Chapter 11 Appendix 15 14 13 12 H 1 9 8 7 6 5 4 2 1 8 8 8 8 8 8 8 8 8 TMB TM8 8 x OOFE88 15 14 12 10 CB5 CB2 R W R W R W R W R W R W R W R W R W R W R W RAW R W R W R W R W Timer 8 Compare Capture Reaister on on on on 9 16 bit access register sets the timer 8 PWM duty changes PWM and gener ates a timer 8 capture B inter rupt When capture is selected this register is read only A timer 8 capture B interrupt is generated when capture occurs When compare is selected set the PWM duty When this register matches the timer 8 binary counter a timer 8 capture B in terrupt occurs This register write only 16 bit data Use the MOV instruction to set the data 15 14 13
285. CL i us 00 80 RWI AD Conversion End j oj o j o o Interrupt Control Register 8 bit access register AD Conversion End Interrupt 0 No interrupt requested ADICL requests and verifies an Request Flag 1 Interrupt requested AD conversion end interrupt AD Conversion End Interrupt 0 Interrupt undetected This register allows only byte Detect Flag 1 Interrupt detected accesses Use the MOVB in struction to set the data 6 5 2 ADICH AD LV2 Lv1 Lvo IE x 00FC81 RARE RAW OR I R RR AD Conversion End on Interrupt Control Register 8 bit access register AD Conversion End Interrupt Set the level from 0 to 6 ADICH sets an AD conversion Level Setup end interrupt level and enables an interrupt AD Conversion End Interrupt 0 Disable Enable Flag 1 Enable This register allows only byte accesses Use the MOVB in struction to set the data MN102H55D 55G F55G 369 Chapter 11 Appendix 7 6 5 4 3 2 1 0 TM6U TM6U IR ID R R R R W R R R R 0 0 0 0 0 0 0 on o 0 1 4 Timer 6 Underflow Interrupt Request Flag 0 Timer 6 Underflow Interrupt Detect Flag 7 6
286. CO source ad dress pointer ETOSRC ETOSRC x 00FD44 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETO ETO ETO ETO SRCI15 SRC14 SRC13 SRC12 SRCH SRC10 SRC9 SRC8 SRC7 SRC6 SRC5 SRC4 SRC3 SRC2 SRC1 SRCO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRC23 ISRCZ2 SRC21 SRC20SRCI9 SRCI8 SRCI7 SRCI6 0 0 0 1 0 0 0 0 2 Set the bytes to be transferred automatically In this example 2 byte data is trans ferred so that the value 1 subtracting 2 by 1 is set to the ETCO transfer word count register ETOCNT x 00FD42 ETO ETO ETO ETO ETO CNTI11 CNTIO CNT9 8 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNTI CNTO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 Set the ETCO control register ETOCTR Select burst transfer mode Select one byte unit and the source pointer to increment by 1 Select the transfer direction is from external memory to external device Set the transfer start busy flag to dis able ETOCTR x 00FD40 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
287. Chapter 8 Ports 276 MN102H55D 55G F55G 8 2 Setup Examples 8 2 1 Port Setup This section describes a light emitting diode LED on off based on switch input status P71 is connected to the switch and P70 is connected to the LED In this configuration the LED is on when the switch is on while the LED is off when the switch is off A 470 9 lt 10kQ MN102HF55G v P70 P71 SW 77 Figure 8 2 1 General purpose Port Setup Example 1 Both P71 pin and P70 pin are set to input by the initial values after reset release Under this condition the LED is off Next set the P70 pin to the general purpose port output P7DIR x 00FFE7 P7LMD x 00FFFA 7 6 5 4 2 2 1 0 7 6 5 4 3 2 1 0 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 DIR7 DIR6 DIR5 DIRA DIR3 DIR2 DIRI DIRO LMD7ILMD6LMDSLMDAILMD3LMD2 LMDI ILMDO 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 2 Read the P71 pin status P7IN with the MOVB instruction If bit 1 is 0 set POOUT to x 00 P7OUT x 00FFC7 P7IN x 00FFD7 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 OUT7OUT6 JOUTS OUTA4 OUT3OUT2JUTI OUTO IN7 6 INS IN4 IN3 IN2 INI INO 0 0 0 0 0 0 0 0 Chapter 8 Ports On the contrary if bit 1 is 11 set P
288. Compare Capture Register Set AX TM9CB x 00FE98 Timer 9 Compare Capture Register B TM9CBX x O0FE9A Timer 9 Compare Capture Register Set BX TM9MD2 x O0FE9E Timer 9 Mode Register 2 TMIOMD x 0O0FEAO Timer 10 Mode Register TMIOBC x 00FEA2 Timer 10 Binary Counter TMIOCA x O0FEA4 Timer 10 Compare Capture Register A Timer 10 TMIOCAX 00 6 Timer 10 Compare Capture Register Set 10 x O0FEAS Timer 10 Compare Capture Register B TMIOCBX x 00FEAA Timer 10 Compare Capture Register Set BX TMIOMD2 x 00FEAE Timer 10 Mode Register 2 TMIIMD x OO0FEBO Timer 11 Mode Register TMIIBC x O0FEB2 Timer 11 Binary Counter Timer 11 TMIICA x 00FEB4 Timer 11 Compare Capture Register A TMIICAX x O0FEB6 Timer 11 Compare Capture Register Set AX x OOFEB8 Timer 11 Compare Capture Register B TMIICBX x O0FEBA Timer 11 Compare Capture Register Set BX TMI2MD x 00FECO Timer 12 Mode Register TMI2BC x 00FEC2 Timer 12 Binary Counter Timer 12 TMI2CA 00 4 Timer 12 Compare Capture Register A 12 x 00FEC6 Timer 12 Compare Capture Register Set AX TMI2CB x 00FECS Timer 12 Compare Capture Register B TMI2CBX x 0O0FECA Timer 12 Compare Capture Register Set BX 4 3 3 16 bit Timer Block Diagrams Chapter 4 Timers
289. D 55G F55G Definition Add 4 Load the value of TM3BR 00 13 D Delete C Change Page 3 MN102H55D 55G F55G User s Manual Record of Changes Ver 1 1 to Ver 2 0 Former Version New Version Transfer Unit Transfer Unit Byte Word disable when 8 bit bus width for Word disable when 8 bit bus width for external memory is selected external memory is selected Byte Do not activate ATC by an interrupt and write 0 to ATNEN flag by the user program simultaneously Omitting this procedure causes the CPU to stop Set the applicable register not to generate an interrupt for ATC activation factor before writing 0 to ATnEN flag 15 14 13 11 10 9 15 14 11 9 ATO ATO ATO ATO ATO ATO ATO EN MD1 MDO DB8 DI SB8 EN MDI DB8 SB8 SI 0 0 0 0 1 0 0 0 Q 0 0 Busy flag Hold Hold Hold Hold Hold Busyflag Hold Hold Hold Hold indication indication Transfer Unit Transfer Unit Byte Word Word Byte Add XO in pin name section and add STOP Control block diagram The XI pin can
290. EYTRG register 1 Set Set OR Pin for 4 Pin 0 Don t set 1 Set Set OR Pin for KI3 Pin 0 Don t set 1 Set Set OR Pin for KI2 Pin 0 Don t set 1 Set Set OR Pin for KH Pin 0 Don t set 1 Set Set OR Pin for 0 Pin 0 Don t set 1 Set MN102H55D 55G F55G 393 Chapter 11 Appendix 15 14 13 12 110 9 8 7 6 5 4 2 1 WD WD WD WD WD CLR 2 RST R W R R R R W R W R W R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 on o 0 0 0 0 1 15 Expansion Watchdog 0 Don t clear Counter Clear 1 Clear 10 8 Watchdog Interrupt 000 Watchdog time set in CPUM Generation Time register x 1 001 Watchdog time set in CPUM register x 4 010 Watchdog time set in CPUM register x 16 011 Watchdog time set in CPUM register x 64 100 Watchdog time set in CPUM register x 256 101 Watchdog time set in CPUM register x 1024 110 Watchdog time set in CPUM register x 4096 0 Watchdog Timer Reset 0 Don t reset 394 MN102H55D 55G F55G 1 Reset WDREG x O0FCBe6 Watchdog Interrupt Extension Control Register 16 bit access register WDREG extends the watchdog interrupt cycles set in the CPUM register The extended watchdog counter count during those set ting time Chapter 11 Appendix 7 6 5 4 3 2 1 0 SYSCT L SYS SYS SYS SYS SYS SYS SYS SYS C7 C6 C5 C4 C3 C2 CI CO x OOFCDO
291. F3 10 Dn lt lt 2 Dm 715 8 Dn 8 08 8 715 imm16 Dn Dnlimm16Dn F7 40 Dn imm16 l imm16 h 715 OR imm16 PSW PSW imm16 gt PSW F7 14 imm16 l imm16 h 15 XOR Dn Dm DmA x 00FFFF amp Dn Dm F3 20 Dn lt lt 2 Dm 15 imm16 Dn Dn imm16Dn F7 4C Dn imm16 l imm16 h 15 NOT Dn Dn x 00FFFF Dn F3 E4 Dn 715 ASR Dn 1 6 gt Dn bp Dn bp 1 bp15 1 Dn bp15 Dn bp15 o o o o o o e e e e e oe oe e o o o o cle o o ce e e e oe e N N O m m 0 Q N N IO N N IN SN Tm W N I IO N 38 715 Dn bp Dn bp 1 bp15 1 0 Dn bp15 F3 3C Dn Dn Isbtemp Dn bp Dn bp 1 bp15 1 CFDn bp15 temp CF F3 34 Dn Dn bp15 temp Dn bp Dn bp 1 bp14 0 CFDn Isb temp CF F3 30 Dn BTST imm8 Dn Dn amp imms PSW 04 8 BTST imm16 Dn Dn amp imm16 PSW F7 04 Dn imm16 l imm16 h BSET Dm An mem8 An amp Dm PSW 8 Dmmem8 An F0 20 An lt lt 2 Dm BSET imm8 abs16 mem8 abs16 imm8 mem8 abs16 F4 E3 abs16 l abs16 h imm8 BSET imm8 abs24 mem8 abs24 imm8 8 0524 F4 4B abs24 l abs24 m abs24 h imm8 BSET imm8 d8 An mem8 An d8 imm8 8 8
292. F3 FF B8 bp d8 TBZ abs16 bp label mem8 abs16 amp 1 bp PSW If ZF 1 PC 5 d8 label PC If ZF 0 5 gt F5 C0 bp abs16 l abs16 h label TBZ abs24 bp label mem 8 abs24 amp 1 bp PSW If ZF 1 PC 7 d8 label PC If ZF 0 7 F3 FE C0 bp abs24 l abs24 m abs24 h label TBZ d8 An bp label mem8 An d8 amp 1 lt lt bp PSW If ZF 1 PC 4 5 d8 label PC If ZF 0 4 5 gt F5 80 bp d8 label An A0 F5 88 bp d8 label 1 F3 FF 80 bp d8 label An A2 F3 FF 88 bp d8 label TBNZ abs16 bp label mem8 abs16 amp 1 lt lt bp PSW If ZF 1 5 gt If ZF 0 PC 5 d8 label PC F5 C8 bp abs16 l abs16 h label TBNZ abs24 bp label mem8 abs24 amp 1 lt lt bp PSW If ZF 1 7 If ZF 0 PC 7 d8 label PC F3 FE C8 bp abs24 l abs24 m abs24 h label TBNZ d8 An bp label mem8 An d8 amp 1 lt lt bp PSW If ZF 1 PC 4 5 PC If ZF 0 PC 4 5 d8 label PC F5 A0 bp d8 label An A0 F5 A8 bp d8 label 1 F3 FF A0 bp d8 label 2 F3 FF A8 bp d8 label BEQ label If ZF 1 PC 24d8 label gt PC If ZF 0 PC 2 PC E8 d8 BNE label If ZF 0 PC 24d8 label gt PC If ZF 1 PC 2 gt PC BLT label If VF NF 1 PC 2 d8 label PC If VF NF 0 PC 2 gt PC Quick decoder Notes 16 Performed under the conditions of
293. FFF all output waveforms consist of 1 3 When TM8CB x FFFF all output waveforms consis of 1 Figure 4 4 10 shows 000A 0007 0003 or 3 cycles Figure 4 4 12 shows 000A 0007 0003 or 3 cycles lt Definition gt A Add D Delete Change Page 2 In the duplex half duplex asynchronous mode both SBT pins become input when they are not selected to transmit so they required pullup resistors Former Version MN102H55D 55G F55G User s Manual Record of Changes Ver 1 1 to Ver 2 0 New Version Transmission reception is possible within 2 of baud rate errors W Data Transmission 2 6 Repeat steps 4 to 7 if the data is transmitted con tinuously W Stop Sequence 7 Write 0 to the SC3IIC flag of the SC3CTR register to end the data transmission Do not write during trans mission 8 Set the SCL3 pin output to high as soon as the SC3IIC flag is written One cycle later set the SDA3 pin output to high to start the stop sequence transmis sion The SC3ISP flag of the SC3STR register be comes 1 Reception must be enabled to detect the stop sequence Clear the SC3IST and SC3ISP flags of the SC3STR register by writing to or reading from the SC3TRB register 6 Read the dummy data of the serial 3 transmit receive buffer SC3TRB after transmission ends 7 Verify that a parity error occurs by reading the serial 3 status register SC3STR When a parity error oc curs this means the
294. G 10 10 IB1 IBO R R R R R W R W 0 0 0 0 0 0 0 0 0 0 0 0 01 10 TM10IB Pin Input Edge 00 Rising edge 01 Falling edge 10 Both edges Chapter 11 Appendix TM10MD2 Timer 10 Mode Register 2 8 bit access register TM10MD2 sets the TM10IB input edge MN102H55D 55G F55G 451 Chapter 11 Appendix 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 TM11MD TM11 TM11 11 11 11 11 11 11 11 11 11 11 11 11 EN NLD UDI UDO TGE ONE ECLR LP ASEL 52 51 50 x 00 FE R W R W R R R W R W R W R W R W R W R W R W R W R W R W R W Timer 11 Mode Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o on o on 16 bit access register 15 TM11BC Count 0 Disable 1 Enable TM11MD sets the timer 11 oper ating conditions 14 TM11BC T F F RS F F 0 Set TM11BC T F F RS F F to 0 Operation 1 Operate TM11BC T F F RS F F 11 10 Up Down Counter Mode 00 Up counter Selection Ignored when two 01 Down counter phase encoding is selected 10 Up when TM1 110A pin is high down when 11 pin is low 11 Up when pin is high down when 11 pin is low 9 Count Start External Trigger 0
295. G has a function to expand memory to ex ternal devices Table 2 1 1 shows memory modes 8 or 16 bit data bus width can be selected by setting pins Table 2 1 1 Mode Setting Modes External Connecting Modes External Data Bus Width MODE ADSEP WORD uen Single chip mode H Memory Expansion Address data separate mode 8 bit H H H Note 1 16 bit H H L Note 1 Address data shared mode 8 bit H L H Note 1 16 bit H L L Note 1 Processor mode Address data separate mode 8 bit L H H Note 2 16 bit L H L Note 2 Address data shared mode 8 bit L L Note 2 16 bit L L Note 2 Note 1 Set each mode register to input or output an address data control signal from single chip mode using user program on internal ROM becuase the CPU starts in single chip mode after reset Note 2 Initialize the setting to input or output an address data control signal after reset release Memory Expansion Mode Processor Mode External Memory Space 0 CSO output 7 External Memory Space 1 CS1 output 71 External Memory Space 2 52 output _ External Memory Space 3 CS3 output x 000000 E x 000000 External Device External Device 008000 i i 008009 Internal RAM 2005000 Internal RAM 009000 4 4096 bytes 3 009000 4 4096 bytes 3 x 00FC00 x 00FC0
296. H 00 77 R W Timer 11 Underflow Interrupt Control Register TMIIAICL 00 7 R W Timer 11 Capture A Interrupt Control Register TMIIAICH x 00FC7D R W Timer 11 Capture A Interrupt Control Register TMIIBICL x 00FC7E R W Timer 11 Capture B Interrupt Control Register TMIIBICH x 00FC7F R W Timer 11 Capture B Interrupt Control Register TMI2UICL 00 84 R W Timer 12 Underflow Interrupt Control Register TM12UICH 00 85 R W Timer 12 Underflow Interrupt Control Register TMI2AICL 00 86 R W Timer 12 Capture A Interrupt Control Register TM12AICH 00 87 R W Timer 12 Capture A Interrupt Control Register TMI2BICL x O0FC8A R W Timer 12 Capture B Interrupt Control Register TMI2BICH x OOFC8B R W Timer 12 Capture B Interrupt Control Register SCOTICL 00 90 Serial 0 Transmission End Interrupt Control Register SCOTICH x 00FC91 Serial 0 Transmission End Interrupt Control Register SCORICL x 00FC92 Serial 0 Reception End Interrupt Control Register SCORICH x 00FC93 Serial 0 Reception End Interrupt Control Register SCITICL 00 94 1 Transmission End Interrupt Control Register SCITICH 00 95 R W 1 Transmission End Interrupt Control Register SCIRICL 00 96 R W 1 Reception End Interrupt Control Register SCIRICH 00 97 R W 1 Reception End Interrupt Control Register SC2TICL
297. H x 00FCAF R W ATC 3 Transfer End Interrupt Control Register 00 4 ETC 0 Transfer End Interrupt Control Register ETCOICH x 00FCAS ETC 0 Transfer End Interrupt Control Register ETCIICL 00 R W 1 Transfer End Interrupt Control Register 00 7 R W 1 Transfer End Interrupt Control Register ADICL 00 80 R W AD Conversion End Interrupt Control Register ADICH x 00FC81 AD Conversion End Interrupt Control Register KIICL 00 78 R W External Key Interrupt Control Register KIICH x 00FC79 R W External Key Interrupt Control Register KEYTRQ x 00FCB2 External Key Interrupt Condition Setup Register KEYCTR 00 4 R W External Key Interrupt Enable Register WDREG x O0FCB6 R W Watchdog Interrupt Extension Control Register The error interrupt control register does not exist in the hardware The CPU write to the IAGR register to indicate that it detected an error interrupt if the interrupt cannot be matched All registers except IAGR IRQTRG KEYTRG KEYCTR and WDREG allow only byte accesses Use the MOVB instruction to set the data Chapter 3 Interrupts MN102H55D 55G F55G 93 Chapter 3 Interrupts The interrupt level is 5 in this example 94 3 2 Interrupt Setup Examples 3 2 1 External Pin Interrupt Setup Examples In this example an interrupt occurs on the negati
298. H55D 55G F55G 87 Chapter 3 Interrupts CLASS 0 System Interrupt 7 6 5 4 3 2 3 1 2 Control Registers These registers control the interrupt function the interrupt accept group register the interrupt condition setup register IRQTRG the external key interrupt condition setup register KEYTRG the external key interrupt enable register KEYCTR and the watchdog interrupt extension control register WDREG CLASS 1 13 7 6 5 4 3 2 1 0 Nonmaskable interrupt NMICR ID Watchdog overflow WDICR Undefined instruction UNICR Interrupt arbitriation error interrupt Interrupt detect flag 0 Interrupt undetected 1 Interrupt detected LV Interrupt priority level LV 2 0 7 6 5 4 3 2 IR X IQ External interrupt XnICH TM or T Timer interrupt SC Serial interrupt Interrupt enable flag IE AT ATC transfer end interrupt 0 Disable AD AD conversion end interrupt 1 Enable Key interrupt 1 0 ID XnICL Some registers do not have LV flags These bits are read to 0 t Interrupt request flag IR t Interrupt detect flag ID 0 No interrupt requested 0 Interrupt undetected 1 Interrupt requested 88 MN102H55D 55G F55G 1 Interrupt detected The following is an example of setting the interrupt level LV and the interrupt enable IE in the interrupt control register XnICH Interrupts
299. IA BXI3 BXI2 BXII BXIO 9 BX8 BX7 6 5 BX4 BX3 BX2 x 00 F 9 Tes ese aa p 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Capture Register Set 16 bit access register This register is valid only when the associated compare register is set to the double buffer mode TM9CBX cannot read or write The contents of TM9CB are loaded to 9 by write sig nal TM9CBX sets the PWM cycle When TM9BC TM9CBX a timer 9 capture B interrupt oc curs The contents of TM9CB are loaded to TM9CBX by a timer 9 capture B interrupt and TM9CBX prevents the PWM loss This register writes only 16 bit data Use the MOV instruction to set the data MN102H55D 55G F55G 459 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO TMIO 15 14 CAI3 12 CAII 10 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4
300. In 7 bit transfer the MSB bit 7 becomes 0 The data is read when an interrupt occurs or the SC3RXA flag of the SC3STR register is 1 7 6 5 4 3 2 1 0 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 TBY RBY ISP RXA IST FE PE OE R R R R R R R R 0 0 0 0 0 0 0 0 7 Transmission Busy Flag 6 Reception Busy Flag 5 Stop Sequence Detect 4 Received Data 3 Start Sequence Detect 2 Framing Error 1 Parity Error 0 Overrun Error Ready to transmit Transmission in progress Ready to receive Reception in progress Undetected 1 Detected No received data Received data Undetected Detected No error 1 Error No error Error No error Error Chapter 11 Appendix SCS3STR x OOFD9B Serial 3 Status Register 8 bit access register 16 bit access is possible from even address SC3STR reads the status for se rial interface 3 This bit is cleared by the read or write operation of the SC3TRB register Set 1 to the SC3REN bit This bit is cleared by the read or write operation of the SC3TRB register Set 1 to the SC3REN bit A framing error occurs when the stop bit is 0 Framing error data is updated whenever the stop bit is received A parity error occurs when the parity bit is 1 although it is set to 0 when the parity bit is 0 al though it is set to 1 when the
301. LIO WL9 WL8 WL7 WL6 WL5 WL4 WL3 WL2 WLI WLO X R W R W R W R W R W R W R W R W R W R W R W R W Long Word Byte Swap Reaister L om on on on on on g 8 16 bit access register LBSWL writes 16 bit data During read operations bits 7 0 read bits 15 8 of the LBSWH register and bits 15 8 read bits 7 0 of the LBSWH reg ister Combining with the LBSWH register 24 bit upper and lower data can swapped in 8 bit unit In addition 16 bit up per and lower data can be swapped by writing the 16 bit data to the LBSWL register and reading the data from the LBSWH register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LBSWH LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS LBS OOF FCE WH15 WH14 WH13 WH12 WH11 WH10 WH9 WH8 WH7 WH6 WHS WH4 WH3 WH2 WHO x R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Long Word Byte Swap 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R egi ster H 8 16 bit access register LBSWH writes 16 bit data During read operations bits 7 0 r
302. List of Pin Functions 24 26 Pin Number Pin Name Function Description 59 P92 TM10IOB DMAREQO Input General purpose Port 92 Timer 10B Input Output ETCO Activation Request Input This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports This pin can be used as a timer 10 input output pin Refer to Chapter 4 Timers This pin is an ETC activation request pin When ETC starts the data is transferred automatically between the external memory and the external device which requires no address specification Refer to Chapter 7 ATC ETC 60 P93 TM10IC DMAACKO y o Input Output General purpose Port 93 Timer 10C Input ETCO Acknowledge Output This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports This pin can be used as a timer 10 counter clear input pin Refer to Chapter 4 Timers This pin is an acknowledge signal output pin for ETC acti vation request Refer to Chapter 7 ATC ETC 62 P94 ANO y o Input General purpose Port 94 A D Converter 0 Conversion Input This pin can be used as a general purpose input output port The
303. M General purpose Port 56 Timer 15A Input This pin provides a timing signal of latching the address which outputs to ADO to AD15 pins during address data shared mode in processor mode or memory expansion mode ALE outputs at positive logic at reset release but the PSHMD changes to negative logic Because of this ALE cannot be used at negative logic in processor mode Refer to 2 1 Summary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state When connecting burst ROM to the external memory space in processor mode or memory expansion mode connect this pin to RE in burst ROM Refer to 2 1 Summary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state This pin can be used as a general purpose input output port if itis not used as ALE ALE or BSTRE in single chip mode processor mode or memory expansion mode The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports This pin can be used as a timer 15 pulse input pin if it is not used as ALE ALE or BSTRE in single chip mode proces sor mode or memory expansion mode Because pin 26 has the same function either pin 26 or pin 11 must be se lected Refer to Chapter 4 Timers MN102H55D 55G F55G 29 Chapter 1 General Description Table 1 4 1 List of Pin Functions 9 26
304. M 7 1 2 Control Registers Setup Examples 7 2 1 Serial Reception Summary ETG a ei tie Ue eb SE dae ete 7 3 1 OVGIVIOW aati eue aries 7 3 2 Control Registers 8 ETG Setup Examples teet edes 7 4 1 Transfer from External Memory to External Device 7 4 2 Transfer from External Device to External Memory Burst Transfer ee heec dete 7 4 3 Transfer from External Device to External Memory One Byte Transfer Chapter8 Ports 8 1 8 3 Summary of Poms 8 1 1 OVEIVIOW sibi Ce ea Mp ev Gaetan Ex 8 1 2 Control Registers 8 1 3 Port Block Diagram Port Setup Ex mbples e vec 8 2 1 General purpose Port Setup Summary of Byte swapped Registers 8 3 1 OVGIVIOW De e diee Chapter9 System Control 9 1 9 2 Address Break eere ed ide de er tuu 280 9 1 1 OVEIVIOW u Qu ata a Qua au Ede UAR La 280 9 1 2 Control Registers 281 9 1 3 Address Break Setup Examples 282 System Related Register Protection 284 9 2 1 OVeIVIBW dat tear 284 9 2 2 Control
305. M 1 B TMI TMI TMI TMI TM BC7 BC6 BCS BC4 BC3 BC2 BCO x 0 0 F E 0 1 ee 1 0 0 0 0 0 0 0 0 Counter 8 bit access register 16 bit access is possible from even address TM1BC operates timer 1 count ing 7 6 5 4 3 2 1 0 T M 2 B TM2 TM2 TM2 TM2 TM2 TM2 TM2 TM2 BC7 BC6 BCS BC4 BC2 BCI BCO x 00 FEO2 SM M Timer 2 Binary 0 0 0 0 0 0 0 0 Counter 8 bit access register TM2BC operates timer 2 count ing 7 6 5 4 3 2 1 0 T M 3 B TM3 TM3 TM3 TM3 TM3 TM3 TM3 TM3 BC7 BC6 BCS BC4 BC3 BC2 BCI BCO x 00 Re ee 3 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Counter 8 bit access register 16 bit access is possible from even address operates timer 3 count ing MN102H55D 55G F55G 431 Chapter 11 Appendix TM4 4 4 TM4 4 TM4 BC7 BC6 BCS BC4 BC3 BC2 BCO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TMS TMS TMS TMS TMS TMS TMS TMS 7 BC6 BCS BC4 BC3 BC2 BCO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
306. M8 EN NLD UDI UDO TGE ONE MDI MDO ECLR ASEL 52 51 50 0 0 0 0 1 1 0 0 0 1 100 0 1 1 2 Set the pulse width Since the width is 2 cycles BOSC 2 set the timer 8 pare capture register TM8CA to 3 the valid range is 1 to x FFFE TM8BC counts from 0 to 3 and TM8IOA pin outputs H while TM8BC counts from 2 to 3 by setting TM8CB in the next procedure 3 The operation is the same as that of the two phase PWM output 8 x 00FE84 CAI4 CAI3 CAI2 CA10 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 Write 1 to the timer 8 compare capture register B TM8CB When TM8BC reaches TM8CB TM8BC 2 TM8IOA pin outputs H at the start of the next cycle TM8CB x 00FE88 15 CB14 CB13 CB12 9 CB8 CB6 5 CB2 CBO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 4 Set TM8NLD and TM8EN of the TM8MD register to 1 and 0 respectively This enables TM8BC RS F F During the count operation 1 is written automatically to TM8EN of the TM8MD register on the falling edge of TM8IOB pin Therefore counting starts at the begin ning of the next cycle after TM8IOB pin falls TM8EN of the TM8MD register can replace as the busy flag for one shot operatio
307. MAACKO DMAACKO Output P93 AN3 to ANO _ P97 P90 POLMD 7 3 1 0 gt Register 5 0 P9DIR 7 0 Register TMBIOA TM10IOA TM10IOB TM10IC l Input Output Control P90 P93 Selector BIBT1 BIBT2 Output Control P90 P91 T l DMAREQO DMAREQ1 DMAACKODDMAACK1 Input Output Control P90 P93 ANO Input Control 97 P94 gt ANO Input 4 97 94 TM8IOA TM10IOA TM10IOB 101 Input P90 P93 DMAREQ1 DMAREQO Input 4 4 90 92 P9IN 7 0 Input 4 Port Input Note The set value of the P9DIR register is valid only when the port function is selected by the POLMD register or the 9 register The input or output direction of timer BIBT1 BIBT2 ETC and A D is determined automatically by setting the P9LMD register or P9HMD register MN102H55D 55G F55G 273 Chapter 8 Ports Table 8 1 2 Port Block Diagram 11 12 Port Pin Name Block Diagram Port A PAS to PAO IRQ4 to IRQO 15 ADSEP PAPLU 5 0 Register Ts PAOUT 5 0 Register PAMD 4 0 gt Register 5 PADIR 5 0 O Register PAIN 5 0 Port Input IRQ4 IRQ0 Input
308. MnMD 6 5 4 3 2 1 0 TMn TMn TMn TMn TMn TMn EN LD CLR OB OA S Mode Register TMnS Clock Source Selection BOSC 2 Timer 0 underflow TMnOA TMnOA Output Edge Selection Positive logic Negative logic TMnOB TMnOB Output Edge Selection Positive logic Negative logic TMnCLR TMnBC and RS F F Clear No operation Clear TMnLD Read TMnBR value to TMnBC 0 No operation 1 Read TMnEN TMnBC Counting Operation 0 Count stop 1 Count operation MN102H55D 55G F55G 175 Chapter 4 Timers 176 MN102H55D 55G F55G Binary Counter BC7 BC6 BCS BC4 BC3 BC2 BCO TMn TMn TMn TMn TMn TMn TMn TMn Base Register BR6 BRS BR4 BR3 BR2 BRI BRO TMn TMn TMn TMn TMn TMn TMn TMn Output Compare Register A CAT CA6 CAS CA4 CA2 CAI CAO TMn TMn TMn TMn TMn TMn TMn TMn Output Compare Register B CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 Table 4 5 2 List of 8 bit PWM Registers Register Address Function TM13BC x 00FE08 Timer 13 Binary Counter x O0FEOA Timer 13 Output Compare Register A TM13BR 00 18 Timer 13 Base Register TM13CB x OOFEIA Timer 13 Output Compare Reg
309. Mode 00 ALE Long 0 Mode in CSO Space 01 ALE Long 0 5 Mode 10 ALE Long 1 Mode Reset 11 ALE Long 1 5 Mode 1 0 ALE Late Mode 00 ALE Late 0 Mode in CSO Space 01 ALE Late 0 5 Mode 10 ALE Late 1 Mode Reset 11 ALE Late 1 5 Mode 482 MN102H55D 55G F55G ALEEDGE x OOFF8A ALE Waveform Control Register 16 bit access register ALEEDGE sets the ALE wave form control modes 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADL ADL ADL ADL ADL ADL 31 30 21 20 11 10 01 00 R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 6 Address Long Mode 00 AD Long 1 Mode Reset in CS3 Space 01 AD Long 1 5 Mode 10 AD Long 2 Mode 11 AD Long 3 Mode 5 4 Address Long Mode 00 AD Long 1 Mode Reset in CS2 Space 01 AD Long 1 5 Mode 10 AD Long 2 Mode 11 AD Long 3 Mode 3 2 Address Long Mode 00 AD Long 1 Mode Reset in CS1 Space 01 AD Long 1 5 Mode 10 AD Long 2 Mode 11 AD Long 3 Mode 1 0 Address Long Mode 00 AD Long 1 Mode in CSO Space 01 AD Long 1 5 Mode 10 AD Long 2 Mode 11 AD Long 3 Mode Reset MN102H55D 55G F55G Chapter 11 Appendix x MPXADR x OOFF8C Address Output Time Control Register 16 bit access register MPXADR sets the address out put time control modes during address data shared mode 483 Chapter 11 Appendix
310. Mode gt AD15 ADO Address Dat AD long 1 mode 01 RDS in RE Late 0 5 short 0 mode Write REDF2 tREDRI lt 8 bit Bus Mode gt AD15 AD8 Address AD long 1 mode tapi AD7 ADO Address Data AD long 1 mode lapi tui 16 bit Bus Mode AD15 ADO Address Data AD long 1 mode tap1 WEH WEL Late 1 short 0 mode REDF1 iwePw Figure 11 1 9 Data Transfer Signal Timing Address Data Shared With Wait 1 5 or More Read Write MN102H55D 55G F55G 333 Chapter 11 Appendix BOSC ALE Late 0 long 0 mode ALE Late 0 long 0 5 mode ALE Late 0 long 1 mode ALE Late 0 long 1 5 mode T 1 ALE Late 0 5 long 1 5 mode ALE tcvc tcvc N 2 W 1 W the number of waits 1 5 2 2 5 tcycxn tcvc tcH 7 TALEF1 TALER1 TALER1 Late 1 long 1 5 mode ALE Late 1 5 long 1 5 mode lt 8 bit Bus Mode gt AD15 AD8 AD long 1 mode AD7 ADO AD long 1 mode AD15 AD8 AD long 1 5 mode AD7 ADO AD long 1 5 mode AD15 AD8 AD long 2 mode AD7 ADO AD long 2 mode AD15 AD8 AD long 3 mode AD7 ADO AD long 3 mode lt 16 bit Bus Mode gt AD15 ADO AD long 1 mode AD15 ADO AD long 1 5 mode AD15 ADO AD long 2 mode AD15 ADO AD long 3 mode TALER1 TALER1 tALEF1 Address B Address Address Pe
311. Ms TMs 8 TM8 8 8 TM8 EN NLD UDO TGE ONE MD1 MDO ECLR LP ASEL S2 s SO R W R W R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 on on 15 TM8BC Count 0 Disable 1 Enable 14 TMSBC T F F RS F F 0 Set TM8BC T F F RS F F to 0 Operation 11 10 Up Down Counter Mode Selection Ignored when two phase encoding is selected 9 Count Start External Trigger Enable 8 Counter Operating Mode Selection 7 6 8 TM8CB Operating Mode Selection 5 TM8BC Clear 4 TM8BC Count Range 3 Pin Output 2 0 Clock Source Selection 446 MN102H55D 55G F55G 1 Operate TM8BC T F F RS F F 00 Up counter 01 Down counter 10 Up when 8 pin is high down when 8 pin is low 11 Up when 8 is high down when 8 pin is low 0 Disable 1 Start counting on the falling edge of 8 0 Repeat 1 One shot counting 00 Compare register single buffer 01 Compare register double buffer 10 Capture A when TMB8IOA pin is high Capture B when 8 pin is low 11 Capture A when 8 pin is high Capture B when 8 pin is high 0 Don t clear 1 Clear 0 0to FFFF 1 0 to TM8CA 0 RS F F output one phase PWM 1 T F F
312. N102HF55G dif fers depending on each user purpose The following table shows the clock frequency for the MN102HF55G during serial programming The clock frequency for the MN102HF55G is assumed to be 30 MHz if the clock frequency is not specified in the manual If the clock frequency for the MN102HF55G is different from the clock frequency on the target board the value should be calculated proportionately depending on the clock frequency of the MN102HF55G Table 11 4 1 Clock Frequency Max Clock Frequency Min Clock Frequency 30 MHz 4 MHz Chapter 11 Appendix MN102H55D 55G F55G 531 Chapter 11 Appendix 11 4 8 Onboard Serial Programming Mode Setup Programming Mode Setup Timing To set serial programming mode the microcontroller must be in write mode This section describes the pin setup for the serial writer Normal Timing Waveform High Timing Waveform during Serial Programming Figure 11 4 8 Timing for Onboard Serial Programming Mode 532 MN102H55D 55G F55G Chapter 11 Appendix Setup Steps 1 Supply VDD from the external power At this point the serial writer detects the VDD level 2 Supply VPP at Timing A At this point output RST SBD Low 3 Through the serial writer drive RST for T2 term from Timing B when SBT goes high while the MN102HF55G is The MN102HF55G initializes 4 Through the serial writer drive RST for T3 term from Timi
313. NEN flag remains 1 during the conversion To end the conversion write 0 ti the ANEN flag ANICH 2 0 show the number of channel being converted and they clear to 0 when the conversion sequence ends Start Stop Interrupt request Och tch 2ch Och 1ch 2ch Och conversion conversion conversion conversion conversion conversion conversion State ANEN Figure 6 1 6 Multiple Channels Continous Conversion Timing Chapter 6 Analog Interface MN102H55D 55G F55G 217 Chapter 6 Analog Interface oo lt 9 512 256 128 64 m 16 18 14 2 1 1 gt M AN5 r O O O O AN6 AN7 X Vref Vref 4 Shift register for state information SN ANCTR AN aie ave EN Tcbec 4 WE 5 Divider Comp INC Interrupt Data registers Eight 10 bit registers A D interrupt request Figure 6 1 7 A D Converter Block Diagram 218 MN102H55D 55G F55G 6 1 2 Control Registers The A D converter contains the A D converter control register
314. NI INO Port Port Port Port Port Port Port Port 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 PortO Input 0 Input low 1 Input high IN7 INO INS INA IN3 IN2 INI INO Port Port Port Port Port Port Port Port 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port 1 Input 0 Input low 1 Input high 2 P2 P2 P2 P2 P2 P2 P2 IN7 INO INS INA IN3 IN2 INI INO Port Port Port Port Port Port Port Port 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port 2 Input 0 Input low 1 Input high P3 P3 P3 P3 P3 P3 P3 P3 IN7 ING INS INA IN3 IN2 INI INO Port Port Port Port Port Port Port Port 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 70 Port3Input 0 Input low 1 Input high 492 MN102H55D 55G F55G POIN x OOFFDO Port 0 Input Register 8 bit access register POIN reads the port 0 data 1 x OOFFD1 Port 1 Input Register 8 bit access register P1IN reads the port 1 data x OOFFD2 Port 2 Input Register 8 bit access register P2IN reads the port 2 data P3IN x OOFFD3 Port 3 Input Register 8 bit access register reads the port data
315. NSX label NX 1 PC 3 d8 label NX 0 3 gt F5 EF d8 JMP label16 PC 3 d16 label16 gt PC FC d16 l d16 h JMP label24 PC 5 d24 label24 gt PC 4 0 024 424 24 Notes 33 34 35 36 37 38 39 40 41 42 43 44 JMP An src gt dest src2dest src lt dest src lt dest src gt dest src2dest src lt dest src lt dest VX 0 VX 1 NX 0 NX 1 24 bits signed 24 bits signed 24 bits signed 24 bits signed 24 bits unsigned 24 bits unsigned 24 bits unsigned 24 bits unsigned F0 An 2 Quick decoder ON This setting cannot be made in this series MN102H55D 55G F55G 543 Chapter 11 Appendix Instruction Mnemonic Operation JSR label16 A3 4 A3 PC 3 mem24 A3 PC 3 4d16 label16 gt PC Cycle Machine Code FD d16 I d16 h JSR label24 A3 4 A3 5 gt 24 PC 54d24 label24 PC F4 E1 d24 I d24 m d24 h A3 4 A3 PC 2 mem24 A3 An PC F0 01 An lt lt 2 1 gt 24 A344 A3 mem16 A3 PSW 24 2 gt A346 A3 Prefix instruction reversing the following instruction of addition subtraction on saturation operation flag of PSW How to Read INSTRUCTION SET W Explanation of symbols used in the chart Dn Dm Di An Am MDR PSW PC imm8 imm16 imm16 l imm1
316. OPLU controls the port 0 pullup resistor 1 x OOFFB1 Port 1 Pullup Control Register 8 bit access register P1PLU controls the port 1 pullup resistor P2PLU x OOFFB2 Port 2 Pullup Control Register 8 bit access register P2PLU controls the port 2 pullup resistor P3PLU x OOFFB3 Port 3 Pullup Control Register 8 bit access register P3PLU controls the port 3 pullup resistor Chapter 11 Appendix 4 ee sse 1 0 P4PLU PA PA P4 PA P4 P4 PLU7 PLUG PLUS PLU4 PLU3 PLU2 PLU1 PLUO x OOFFB4 R W R W R W R W R W R W R W R W Port 4 Pullup Control Register on on 8 bit access register 7 0 4 Pullup Resistor 0 Off P4PLU controls the port 4 pullup 1 On resistor 716 5 4 3 2 1 0 P5PLU PS Ps Ps PS 5 P5 PS P5 PLU7 PLU6 PLUS PLU4 PLU3 PLU2 PLUI PLUO x OOFFB5 R W R W R W R W R W R W R W R W Port 5 Pullup E MUR MN Control Register 8 bit access register 7 0 Port 5 Pullup Resistor 0 Off P5PLU controls the port 5 pullup 1 On 4 resistor 7 16 5 2 P6PLU P6 P6 P6 P6 PLU
317. OUT to 01 P7OUT x 00FFC7 7 6 5 4 3 2 1 0 P7 P7 P7 P7 P7 P7 P7 OUT7OUT6 JOUTSI OUTA4JOUT3OUT2JOUTI OUTO 0 0 0 0 0 0 0 1 Under this condition the low level is output to P70 pin if the switch is on while the high level is output to P70 pin if the switch is off resulting that the light emitting diode is on or off Thereafter reading the P71 pin status is repeated Figure 8 2 2 and Figure 8 2 3 show the flowcharts of general purpose port operations When the port is input set the PaMDm flag and PnDIRm flag to 0 and read the PnINm flag When the port is output set PnDIRm flag to 1 and write the data output to the PROUTm flag Regardless of input or output direction set the PaPLUm flag to for the pull up setting n means the port number m means bit position Reset Release Reset Release Y PnMDm 0 PnMDm 0 PnPLUm 0 or 1 a PnOUTm Initial Value Y PnPLUm 0 or 1 Y PnDIRmz 0 PnDIRm 1 Read PniNm PnOUTm Set Value 1 Figure 8 2 2 Basic Flowchart of Figure 8 2 3 Basic Flowchart of General purpose Port Input General purpose Port Output MN102H55D 55G F55G 277 Chapter 8 Ports 278 8 3 Summary of Byte swapped Registers 8 3 1 Overview The MN102H55D 55G F55G contains byte swapped registers for pointers and long word data Ea
318. OVB in struction to set the data TM4UICH x 00FC73 Timer 4 Underflow Interrupt Control Register 8 bit access register TM4UICH enables a timer 4 in terrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the IQ4LV 2 0 bits of the IQ4ICH register Chapter 11 Appendix Serie dud P 120 TM10BICL ing 00 74 Timer 10 Capture Interrupt Control Register 8 bit access register Timer 10 Capture B Interrupt 0 No interrupt requested TM10BICL requests and verifies Request Flag 1 Interrupt requested B interub Timer 10 Capture Interrupt 0 No interrupt detected This register allows only byte Detect Flag 1 Interrupt detected accesses Use the MOVB in struction to set the data TM10BICH 5 2 TM10B IE x 00FC75 s z Timer 10 Capture B 1 Interrupt Control Register 8 bit access register Timer 10 Capture B Interrupt 0 Disable Enable Flag 1 Enable TM10BICH enables a timer 10 capture B interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the IQ4LV 2 0 bits of the IQ4ICH register
319. Output 0 Input 1 Output 0 Input 1 Output Set to 0 0 Input 1 Output Chapter 11 Appendix P8DIR 8 Port 8 Input Output Control Register 8 bit access register P8DIR controls the port 8 input output P9DIR 00 9 Port 9 Input Output Control Register 8 bit access register P9DIR controls the port 9 input output PADIR x OOFFEA Port A Input Output Control Register 8 bit access register PADIR controls the port A input output PBDIR x OOFFEB Port B Input Output Control Register 8 bit access register PBDIR controls the port B input output MN102H55D 55G F55G 497 Chapter 11 Appendix 7 6 5 4 3 2 1 0 MDI R R R R R R R W R W Processor address data separate mode 0 0 0 0 0 0 0 1 Processor address data shared mode 0 0 0 0 0 0 1 0 Other modes 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 Input Output Signal Switch 00 Port 01 Data 498 MN102H55D 55G F55G 10 Address data shared mode POMD x OOFFFO Port 0 Mode Register 8 bit access register POMD sets a signal output to the port 0 7 6 5 4 3 2 1 0 1 1 LMD6 LMDS LMD4 LMD3 LMD2 LMDI LMDO R R W R W R W R W Processor address data separate mode 16 bit bus width 0 0 0 0 0 1 Processor address data shread mode
320. Output P12 TMI2IOB TM111OB Output P13 gt TMI2IC TM121OA Output 1210 Output P16 P1LMDI6 0 IT P1HMD 7 0 Register P1DIR 7 0 gt Register gt Address Data Input Output Contro Selector Input Output Contro TM111OA Input Output Control P12 TM111OB Input Output Control P13 P10 Input Control P14 gt 12 Input Output Control P15 1210 Input Output Control P16 TM12IC Input Control P17 PIN ZO 4 P17 P10 Port Input Inpu TM111OA TM1110B 121 TM12IOB TM12IC Inpu P10 P12 P13 TM11IC Input P14 P15 P16 P17 Datalnput 4 015 008 Note The set value the P1DIR register is valid only when the port function is selected by the P1LMD register or P1HMD register The input or output direction of TMnIOA TMnIOB and TMnIC is determined by setting the P1LMD register or register MN102H55D 55G F55G 265 Chapter 8 Ports Table 8 1 2 Port Block Diagram 3 12 Port Pin Name Block Diagram Port 2 P27 to P20 A07 to A00 SBT2 P2PLU 7 0 Register V SBO2 S
321. P ETCOICL ME ics NA a x 00FCA4 i PM Led RR RR ETC 0 Transfer End 0 0 0 0 0 0 0 Interrupt Control Register 8 bit access register ETC 0 Transfer End Interrupt 0 No interrupt requested ETCOICL requests and verifies Request Flag 1 Interrupt requested a ETC 0 transfer end interrupt ETC 0 Transfer End Interrupt 0 Interrupt undetected This register allows only byte Detect Flag 1 Interrupt detected accesses Use the MOVB in struction to set the data ETCOICH 5 2 lt lt IE x OOFCAS CN UE M REGAIN ETC 0 Transfer End 0 0 0 0 0 0 0 1 Interrupt Control Register 8 bit access register ETC 0 Transfer End Interrupt 0 Disable Enable Flag 1 Enable ETCOICH enables a ETC 0 transfer end interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the SCATLV 2 0 bits of the SC4TICH register MN102H55D 55G F55G 385 Chapter 11 Appendix 1 IR ID R R R R W R R R R 0 0 0 0 0 0 0 on o 0 0 1 4 1 Transfer End Interrupt 0 No interrupt requested Request Flag 1 Interrupt requested 0 ETC 1 Transfer End Interrupt 0 Interrupt undetecte
322. P40 5 P37 gt gt P36 gt 5 P34 4 r AVDD P33 P32 P31 P30 KIO MH P27 r P26 gt P25 2 Use 33 50 in Memory Expansion Mode with 16 bit Bus Address Data Shared Mode Unused pins require handling in the circuit input pins are connected to VDD VSS output pins leave open input output pins are connected to VDD VSS or leave open depending on pin direction setting MN102H55D 55G F55G 17 Chapter 1 General Description 1 4 6 Processor Mode with 8 bit Bus Address Data Separate Mode gic og 9 5 SE lt gt lt oc lt 0 7 5 lt Eo 2 5 slan om moo 2 2 o rcn aa HHA 2 TANA oS do 5559900 1 BmangahsSSeS 55 2 25 lt 55 4 N O Oi tL ooN O L 1 5 HHR PSP FB SEES w o0 OL S O OQ COO i10 p ON gt 0 PF PF PF rl F O O O O dq do do do O 10 IO 0 76 50 w P82 TMOIO SBT3 SCL3 SBI2 PA1 IRQ1 77 49 4 P81 DAC1 PA2 RQ2 78 48 a P80 DACO PA3 IRQ3 79 47 a A23 P47 AN7 WDOUT 5 80
323. P4DIR controls the port 4 input output P5DIR x OOFFES Port 5 Input Output Control Register 8 bit access register P5DIR controls the port 5 input output P6DIR x OOFFE6 Port 6 Input Output Control Register 8 bit access register P6DIR controls the port 6 input output P7DIR x OOFFE7 Port 7 Input Output Control Register 8 bit access register P7DIR controls the port 7 input output F 6 5 4 3 2 1 0 8 P8 8 P8 8 8 P8 8 DIR7 DIR6 DIRS DIR4 DIR3 DIR2 DIRI DIRO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 70 Port8 Input Output 7 6 5 4 3 2 1 0 P9 P9 P9 P9 P9 P9 9 P9 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIRO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port9 Input Output 7 6 3 4 3 2 1 0 PA PA PA PA PA PA DIRS DIR4 DIR3 DIR2 DIRI DIRO R R R W R W R W 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 5 0 PortA Input Output 7 6 5 4 3 2 1 0 reserv reserv PB ed ed ed DIRI DIRO R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 4 2 Reserved 1 0 Port B Input Output 0 Input 1
324. P63 to P60 SBT2 RE WEL WEH WAIT P6PLU 3 0 nn Register 4 6 3 0 n Register SBT2 Output P60 RE Output P61 WEL Output P62 WEH Output p63 Selector Y 6 5 0 gt Register P6DIR 3 0 lt Register Selector SBT2 Input Output Control P60 gt RE WEL WEH Output Control gt P61 P63 P6IN 7 0 Port Input lt 7 WAIT Input P60 e Handshake Input SBT2 Input P60 To Port 2 Block Note The set value of the P6DIR register is valid only when the port function is selected by the P6MD register rd eet The input or output direction of SBT2 RE WEL WEH and WAIT is determined automatically by setting the P6MD register P67 P60 270 MN102H55D 55G F55G Table 8 1 2 Port Block Diagram 8 12 Chapter 8 Ports Port Pin Name Block Diagram Port 7 P75 to P70 SBTO SBIO P7PLU 5 0 Register gt SBOO Y SBTI P7OUT 5 0 Register gt SBII SBOI SBTO Output P70 RAS RAS Output P70 LCAS LCAS Output P71 CAS Output P71 Selector CAS 8800 Output P72 gt UCAS Output P72 UCAS SBT1 Output P73 a DMUX Output P73 DMUX SBO1 Output P74 NMI P76 75 70 P7LMD 6 0 P7HMD 6 0 Register P7DIR S 0 Register SBTO In
325. PA4 IRO4 To Writer 71 P16 gt 99 P17 100 9 o o O O O 1D lo 10 10 LALALALA P60 TOP VIEW P54 100 pin LQFP MN102HF55G P82 P81 P80 WDOUT P47 STOP P46 P45 P44 VREF P43 P42 P41 P40 P37 P36 P35 P34 AVDD P33 P32 P31 P30 P27 P26 P25 P24 Self excited external excited 4 MHz to 30 MHz Figure 11 4 5 Pin Configuration During Serial Programming Pins 73 74 and 82 connect to the serial writer VDD and Vss connect to the external power sources of 3 3 V and 0 V respectively In addition the level is detected by the writer VDD and Vss must be output to the writer OSCI and OSCO must be set to the self excited oscillation or external excited oscillation The input pins with no specifi cations in the above figure are don t care Fix them to VDD Vss The output pins BOSC XD with no specifications in the above figure must be open Chapter 11 Appendix MN102H55D 55G F55G 529 Chapter 11 Appendix 530 MN102H55D 55G F55G 11 4 7 System Configuration for Onboard Serial Programming System Configuration wa AC Adaptor Power Source VDD J ast Target Board Es RS232C af Serial Writer Figure 11 4 6 System Configuration for Onboard Serial Writer The PC sends the program data to
326. Pana Series The One toWatch for Constant Innovation Making the Future ComeAlive MICROCOMPUTER 102 00 MN102H55D 55G F55G LSI User s Manual Pub No 22355 020E Panasonic PanaXSeries is a trademark of Matsushita Electric Industrial Co Ltd The other corporation names logotypes and product names written in this manual are trademarks or registered trademarks of their corresponding corporations The MN102HF55G is manufactured and sold under the License Agreement with BULL 8 Inc and the use of the MN102HF55G into the card is not allowed Request for your special attention and precautions in using the technical informa tion and semiconductors described in this manual 1 The approval of the Japanese Government is required for the export of any products and technologies listed in this manual which are subjected to the provisions of the Foreign Exchange and Foreign Trade Law 2 Thecontents of this manual are subject to change without notice to improve design func tion or performance 3 Matsushita Electronics assumes no responsibility or liability for damages or for infringe ments of patents or other rights arising from use of the information in this manual 4 The contents of this manual may not be copied or reproduced without permission in writ ing from Matsushita Electronics 5 This manual describes standard specifications Obtain the latest product standard specifi cations befo
327. R R R R W R R R 0 0 0 0 0 0 0 0 0 1 0 0 1 4 Timer 12 Capture Interrupt Request Flag 0 Timer 12 Capture B Interrupt Detect Flag 7 6 5 4 3 2 0 2 s 12 IE R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 12 Capture Interrupt Enable Flag 374 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 Interrupt undetected 1 Interrupt detected 0 Disable 1 Enable TM12BICL x O0FC8A Timer 12 Capture B Interrupt Control Register 8 bit access register TM12BICL requests and verifies a timer 12 capture B interrupt This register allows only byte accesses Use the MOVB in struction to set the data TM12BICH x O0FC8B Timer 12 Capture B Interrupt Control Register 8 bit access register TM12BICH enables a timer 12 capture B interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the TM7ULV 2 0 bits of the TM7UICH register 2 SCOT SCOT IR ID R R R W R R 0 0 0 0 0 0 0 0 0 on 0 0 0 4 Serial 0 Transmission End 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 0 Serial 0 Transmission End 0 Interrupt undetected Interrupt Detect Flag 1 Interrupt detected 7 6 5 4 3 2 1 0 SCOT SCOT SCOT SCOT LV2 LVO IE R R W R W R W R R W 0 0 0 0 0 0
328. R R R W R R R 0 0 0 0 0 0 0 0 0 1 0 0 1 4 Timer 10 Capture Interrupt Request Flag 0 Timer 10 Capture A Interrupt Detect Flag 7 6 5 4 3 2 0 2 s IE R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 10 Capture Interrupt Enable Flag 360 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected 0 Disable 1 Enable TM10AICL x OOFC6E Timer 10 Capture A Interrupt Control Register 8 bit access register TM10AICL requests and verifies atimer 10 capture A interrupt This register allows only byte accesses Use the MOVB in struction to set the data TM10AICH x OOFC6F Timer 10 Capture A Interrupt Control Register 8 bit access register TM10AICH enables a timer 10 capture A interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the IQ3LV 2 0 bits of the register 7 6 5 4 2 0 104 104 ID R R R W R R 0 0 0 0 0 0 0 0 0 1 4 External Interrupt 4 0 No interrupt requested Request Flag 1 Interrupt requested 0 External Interrupt 4 0 No interrupt detected Detect Flag 1 Interrupt detected 7 6 5 4 2 0 IQ4 IQ4 IQ4 104 LV2 LVI LVO IE R R W R W R W R R W 0 0 0 0 0 0 on on 0 0 1 6 4 External Interru
329. R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port 5 Output 0 Output low 1 Output high OUT3 OUT2 OUTI OUTO R W R W R W R W 0 0 0 0 0 1 0 1 0 1 0 1 3 0 Port 6 Output 0 Output low 1 Output high OUT5 OUT4 OUT3 OUT2 OUTI OUTO R W R W R W R W R W 0 0 0 1 0 1 0 1 0 1 0 1 0 1 5 0 Port 7 Output 0 Output low 1 Output high 490 MN102H55D 55G F55G x OOFFC4 Port 4 Output Register 8 bit access register P4OUT sets the data output to the port 4 5 x OOFFCS Port 5 Output Register 8 bit access register P5OUT sets the data output to the port 5 P6OUT x OOFFC6 Port 6 Output Register 8 bit access register P6OUT sets the data output to the port 6 P7OUT x OOFFC7 Port 7 Output Register 8 bit access register P7OUT sets the data output to the port 7 Chapter 11 Appendix 7 6 5 4 3 2 1 PSOUT P8 P8 P8 P8 P8 8 P8 P8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUTO x 0O0FFC8 R W R W R W R W Port 8 Output oO 0 on on Register 8 bit access regist
330. RAM in processor mode or memory expansion mode When connecting DRAM with 2CAS method connect this pin to WE in DRAM WE outputs low during write operation and writes the data to DRAM Refer to 2 1 Summary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state Refer to 11 2 3 List of Pin Functions MN102H55D 55G F55G 27 Chapter 1 General Description Table 1 4 1 List of Pin Functions 7 26 Pin Number Pin Name yo Function Description P63 y o General purpose Port 63 This pin can be used as a general purpose input output port when 8 bit bus width is selected in single chip mode pro cessor mode or memory expansion mode The input out put direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports 5 50 Output Select Output This pin provides a chip select signal corresponding to each external memory space when accessing SRAM and ROM connected to the external memory spaces 0 to 3 in processor mode or memory expansion mode Connect 50 CS3 to CS pins in external memory CSO cannot be output when accessing Internal ROM or Internal RAM Refer to 2 1 Summary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state Refer to 11 2 3 List of Pin Functions TM130A Output Timer 13A Output This pin can be used as a timer
331. S must be delayed externally to hold the setup time of the COLUMN address Chapter 2 Bus Interface Table 2 1 9 Address Data Separate Mode 16 bit Bus Burst ROM Access The length of wait cycle can be set in 0 5 cycle units 4 3 3 3 Waits BOSC 21 Base Clock BIBT2 BIBT1 i 16 bit Data Read 53 50 pa EE E MENT CPU select and A23 AQ i read the necessary 8 bit data of either 015 00 D15 0 D15 0 0150 DI50 0150 015 08 or 07 00 i 1 jae CS3 CS0 E ET z lt Hold the last P No Access output data ER 015 00 BSTRE a E Table 2 1 10 Address Data Separate Mode 8 bit Bus Burst ROM Access The length of wait cycle can be set in 0 5 cycle units 4 3 3 3 Waits Bosc UUL Base Clock BIBT2 4 BIBT1 653550 EN EN E 8 bit Data Read A23 A0 A230 A230 A230 D7 Do i d 57 5750 gt 570 070 BSTRE EE jos NX gt 5 50 E EN E Ho
332. S1 TTL 52 52 CMOS CMOS CMOS Yes Yes Yes Programmab i Z Hi Z iz Hi Z at CS0 Hi Z at CS0 Hi Z at CS1 Hi Z at CS2 Hi Z at CS2 P53 CS3 CMOS Yes Programmab Hi Z at CS3 Hi Z at CS3 P54 BREQ P55 BRACK P56 ALE ALE BSTRE CMOS CMOS CMOS Yes Yes Yes Programmab Programmab i Z Hi Z Hi Z Programmab Hi Z H 5 i i Hi Z Low Low Hi Z except P56 Hi Z except P56 P57 WORD CMOS Yes Programmab Hi Z Hi Z Hi Z 2 3 P20 A00 4 P21 A01 T CMOS CMOS CMOS Yes Yes Programmab Hi Z Hi Z H Undefined Undefined Hi Z at A00 Hi Z at A00 Hi Z at A01 Hi Z at A01 Hi Z at A02 Hi Z at A02 iz i Z 5 P22 A02 TTL CMOS CMOS Yes Programmable i Z Undefined Hi Z w is Low Hi Z at A03 Hi Z at A03 Low 9 VSS 23 OSCI CMOS Note 5 24 OSCO 25 MODE CMOS 26 P24 A04 L CMOS CMOS lt D S Yes High EO High EO No High Input High Input High Input MODE MODE High EO Note 6 A04 H Programmab Hi Z Undefined Hi Z Hi Z al i Z at A04 Hi Z at A05 i Z at A05 27 P25 A05 TTL 28 P26 A06 TTL 29 P27 A07 TTL 30 P30 A08 TTL 31 P31 A09 L CMOS CMOS CMOS CMOS Yes Yes Y
333. Sain at wak allw wasata ha a ak uta Fo as d TE Qr en der sk fmi D cm dai PW Wa Suwa karayay EL AE y c dai P i d ABE t ae comcs oraya onze tot t a lt a ce amp eee AME eL use 25 z S gt lt CRI LC uz ms lt T Leod eee eer bases ee ae 5 8 lt k Qy lt 5 2 44 T T g o v 9 o o gt u we 8 Qr iE WE iE Ee Ip pU I Tw o lt 5 lt o m Qo 5 2 5 2 A m 5 5 lt 5 a 2 a i d S Nini Mon rs o 9 3 ct ae lt en rs ee 5 5 7 MOM RR EO LENT beets lt o 5 BEST a
334. Serial Programming 529 System Configuration for Onboard Serial Writer 530 Target Board Serial Writer Connection 530 Timing for Onboard Serial Programming Mode 532 Load Program Start Flow 533 Reset Service Routine Flow sse 534 Interrupt Service Routine Flow 534 Data Transfer Timing 2 535 Programming Flow 2 u ayauya saq 536 List of Tables Table 1 1 1 Table 1 2 1 Table 1 3 1 Table 1 4 1 Table 2 1 1 Table 2 1 2 Table 2 1 3 Table 2 1 4 Table 2 1 5 Table 2 1 6 Table 2 1 7 Table 2 1 8 Table 2 1 9 Table 2 1 10 Table 2 2 1 Table 2 2 2 Table 2 2 3 Table 2 2 4 Table 2 2 5 Table 2 2 6 Table 2 2 7 Table 3 1 1 Table 3 1 2 Table 3 1 3 Table 3 1 4 Memory Modes Basic Specifications Block FUNCIONS Re a a List of Pin F nctions uuu ener ete te senis Mode Setting List of Bus Interface Control Registers Address Data Multiplex Mode 16 bit Bus Data Access Address Data Multiplex Mode 8 bit Bus Data Access Address Data Separate Mode 16 bit Bus Data Access Address Data Separate Mode 8 bit Bus Data Access Address Data Separate Mode 16 bit Bus DRAM WEH WEL Method
335. Setup 404 MN102H55D 55G F55G 1 Transfer start transfer in progress 00 One byte word transfer 01 Burst transfer 10 Two bytes transfer 11 Reserved 0 Word 1 Byte 0 16 bit 1 8 bit 0 Fixed 1 Increment 0 16 bit 1 8 bit 0 Fixed 1 Increment 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Software Initialization DMAREQ0 pin input External interrupt 0 External interrupt 1 Timer 1 underflow interrupt Timer 5 underflow interrupt Timer 8 capture A interrupt Timer 9 capture B interrupt Timer 11 underflow interrupt Timer 12 capture A interrupt Serial 1 transmission end interrupt Serial 1 reception end interrupt Serial 2 transmission end interrupt Serial 2 reception end interrupt Serial 4 transmission end interrupt Serial 4 reception end interrupt AT2CTR x 00FD20 ATC 2 Control Register 16 bit access register AT2CTR sets the ATC2 operat ing control conditions Selecting the two bytes transfer mode is valid only in byte ac cess The LSB of the address in the first byte forcibly becomes 0 and the LSB of the address in the second byte forcibly be comes 1 Selecting word as the unit is not allowed when 8 bit bus width is allowed in the external memory space Selecting 8 bit destination bus width or 8 bit source bus width is allowed only when 8 bit bus width is selected in the external memory space When des
336. TM12UICH 5 2 TM12U w 00 85 Timer 12 Underflow 0 0 0 0 0 0 0 1 Interrupt Control Register 8 bit access register Timer 12 Underflow Interrupt 0 Disable Enable Flag 1 Enable TM12UICH enables a timer 12 interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the ADLV 2 0 bits of the ADICH register MN102H55D 55G F55G 371 Chapter 11 Appendix 7 6 5 4 3 2 0 12 IR ID R R R R W R R R 0 0 0 0 0 0 0 0 0 1 0 0 1 4 Timer 12 Capture Interrupt Request Flag 0 Timer 12 Capture A Interrupt Detect Flag 7 6 5 4 3 2 0 2 IE R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 12 Capture Interrupt Enable Flag 372 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 Interrupt undetected 1 Interrupt detected 0 Disable 1 Enable TM12AICL 86 Timer 12 Capture Interrupt Control Register 8 bit access register TM12AICL requests and verifies a timer 12 capture A interrupt This register allows only byte accesses Use the MOVB in struction to set the data TM12AICH x 00FC87 Timer 12 Capture A Interrupt Control Register 8 bit access register TM12AICH enables timer 12
337. TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 7 BC6 BCS BC4 BC3 BC2 BCO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 7 BC6 BCS BC4 BC3 BC2 BCO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 432 MN102H55D 55G F55G TMABC x OOFE04 Timer 4 Binary Counter 8 bit access register TM4BC operates timer 4 count ing TM5BC x OOFEOS Timer 5 Binary Counter 8 bit access register 16 bit access is possible from even address TM5BC operates timer 5 count ing TM6BC x OOFEO6 Timer 6 Binary Counter 8 bit access register TM6BC operates timer 6 count ing TM7BC x OOFEO7 Timer 7 Binary Counter 8 bit access register 16 bit access is possible from even address TM7BC operates timer 7 count ing 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM8 TM8 TM8 8 8 8 8 8 8 8 8 8 TM8 TM8 TM8 TM8 5 BC14 BC13 BC12 BCIO BC8 BC6 5 BC4 BC3 2 BCO R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
338. TR register is 1 the CPU can read the SCnTRB register Reset SCnSTR 7 6 5 4 3 2 1 0 SCn SCn SCn SCn SCn SCn SCn SCn RBY ISP RXA IST PE 0 0 0 0 0 0 Chapter 5 Serial Interface SCnOE Overrun Error 1 0 No error 1 Error SCnPE Parity Error 2 0 No error 1 Error SCnFE Framing Error 3 0 No error 1 Error 2 Start Sequence Detect cleared by read or write operation of SCnTRB For Serial 0 1 2 For Serial 3 4 Reserved set to 0 No start sequence detected Start sequence detected SCnRXA Received Data 0 No received data 1 Received data I C Stop Sequence Detect cleared by read or write operation of SCnTRB For Serial 0 1 2 For Serial 3 4 Reserved set to 0 No stop sequence detected Stop sequence detected SCnRBY Reception Busy Flag 4 0 Ready to receive 1 Reception in progress SCnTBY Transmission Busy Flag 0 Ready to transmit 1 Transmission in progress 1 An overrun error occurs when the next data is received completely before the CPU reads the received data SCnTRB Overrun error data is updated whenever the last data bit seventh or eighth bit is received 2 A parity error occurs when the parity bit is 1 although it is set to 0 when the parity bit is O although it is set to 1 when the parity bit is odd although it is set to even and when the parit
339. The result incremented by 1 is set after the last transfer is completed Chapter 7 ATC ETC The interrupt level is set in SCATLV 2 0 of the SC4TICH register MN102H55D 55G F55G 253 Chip Operation Process ETC Internal 1 Wait Access Process ETC Internal DMAACKn 1 Wait Access Process Process ETC Internal ETC Internal 1 o 111 in WERL gE 93 c E A frs pac 2 2 uy s Chip Operation Chapter 7 ATC ETC BIBT2 BIBT1 WE output CS output Address output 5 5 c tc lt gt a ETC bus acquisition interval External device data output DMAACKn output External device RE 1 the number of data transfer bytes 2 Note the number of external memory waits Figure 7 4 6 ETC External Device External Memory Burst Transfer Timing MN102H55D 55G F55G 254 Chapter 7 ATC ETC 7 4 3 Transfer from External Device to External Memory One Byte Transfer DMAREQO input from bus master is an activation factor The two byte data is transferred from the external device to the external memory
340. The timer 4 underflow is not required KIICH x 00FC79 KI LV2 LV1 LVO IE 1 0 0 Chapter 4 Timers Setting TMOEN and TMOLD to 0 is required between 3 and 4 in the bank address version and the linear address version but this setting is not required in the linear address high speed ver sion 1 Do not change the clock source once you have selected it Selecting the clock source while setting the count operation con trol will corrupt the value in the binary counter This verification is unnecessary after a reset The timer 5 underflow interrupt level and the external key inter rupt level should be the same The interrupt level is 4 in this ex ample MN102H55D 55G F55G 123 Chapter 4 Timers 1 When cascading timers set the lowest timer divisor 1 to the low est timer base register 124 MN102H55D 55G F55G TMA4UICL x 00FC72 TM4U TM4U IR ID 0 TM4UICH x 00FC73 7 6 5 4 3 2 1 0 TMBUICL x 00FC7A 7 6 5 4 3 2 1 0 50 50 IR ID 0 TMSUICH x 00FC7B 7 Set the timer divisor Since timer divides timer output by 60 000 x EA60 set the timer 4 base register TM4BR and the timer 5 base register TM5BR to x 5F and X EA respectively The valid range is 0 to 255 TM4BR x 00FE1
341. Timer 5 Block Diagram Serial 2 3 4 Chapter 4 Timers Data bus 8 8 FE16 Timer 6 base register TM6BR Load gt Reload 8 06 N39IA L qT9N1 Timer 6 binary counter TM6BC x Count Timer 6 underflow interrupt Underflow 4 Timer 0 underflow Timer 5 cascade Timer 4 underflow 0 Multiplex Figure 4 1 11 Timer 6 Block Diagram 18 FE17 Timer 7 base register TM7BR Load Reload 8 07 INL Timer 7 binary counter TM7BC gt limer 7 underflow interrupt TM7IO pin P84 d San Underflow oun a gt 1 2 Reset imer output underflow 2 0 generator circuit Timer 0 underflow gt Timer 6 cascade gt TM7IO pin input 3 P84 Multiplex Set output by PBMMD Figure 4 1 12 Timer 7 Block Diagram MN102H55D 55G F55G 115 Chapter 4 Timers 1 When the pulse is output by the event counter the change tim ing is quantized synchronized with BOSC This verification is unnecessary after a reset 116 MN102H55D 55G F55G 4 2 4 2 1 8 bit Timer Setup Examples Event Counter Using 8 bit Timer Timer 0 divides TMOIO pin input by 4 and generates an underflow in terrupt Event counter ope
342. Transfer from External Memory to External Device DMAREQO input from bus master is an activation factor Each byte data is transferred from the external memory to the external device D A Converter P6 gt RE P61 1 Interrupt A D Converter P7 7 0 P2 8 bit Timers Serial P8 aisas 16 bit Timers mE 52 A23 A16 P4 4 8 bit PWM ETC PA 50 P50 P5 H Pulse Width Counter ROM RAM PB Figure 7 4 1 ETC External Memory External Device Transfer Block Diagram External Memory External Device 8 bit External Memory External Device ER Address RE cs DMAACKO WE x 100000 dataA x 100001 dataB MN102H55D 55G F55G Bus Master DMAREQO di 2 Each one byte data on external memory is transferred to external device Because each one byte data is transferred the 8 bit bus width mode is selected to connect the external memory and the CPU In addition 8 bit bus width is selected to connect the external memory and external device Figure 7 4 2 ETC External Memory gt External Device Transfer Connection MN102H55D 55G F55G 247 Chapter 7 ATC ETC 248 MN102H55D 55G F55G B ETC Setup 1 Set the source address 100000 of the external memory to the ET
343. W Reserved Reserved 0 transmission end OOFC90 R W 0 reception end 00FC92 R W 1 transmission end 00FC94 R W 1 end OOFC96 R W 2 transmission end O0FC98 R W 2 reception end OOFC9A R W 3 transmission end OOFC9C R W 3 reception end OOFC9E R W Serial 4 transmission end OOFCAO R W Serial 4 reception end OOFCA2 R W ETCO transfer end OOFCA4 R W transfer end OOFCA6 R W ATCO transfer end OOFCA8 R W 4 ATC1 transfer end O0FCAA R W ATC2 transfer end OOFCAC R W transfer end OOFCAE R W 86 MN102H55D 55G F55G Address 80008 Interrupt Handler preprocessing es gro 9 max 6 cycles 7 machine cycles Interrupt service routine Handler rts 5 Cycles e postprocessing 2 Pop register Chapter 3 Interrupts Release the interrupt request at the beginning included in the cycle shown to the left Figure 3 1 3 Interrupt Servicing Time Table 3 1 3 Handler Preprocessing Sequence Assembler Byte Cycle add 8 A3 2 1 Push register mov 2 2 DO 4 3 3 Read group number mov FCOE DO 3 1 address for TOY AO 3 1 P mov D0 A0 A0 2 2 service routine Branch jsr A0 2 5 Total 17 15 Table 3 1 4 Handler Postprocessing Sequence Assembler Byte Cycle mov Pop register movx add Total MN102
344. W R W R W R W R W R W R W R W R W Single chip Mode bam0 o olol o ol ri Memory Expansion Mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 16 bit bus width Memory Expansion Mode 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 8 bit bus width Processor Mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 16 bit bus width Processor Mode 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 8 bit bus width 0 1 10 1 0 1 0 1 0 1 0 1 0 1 O 1 O 1 0 1 O 1 O 1 O 1 0 1 0 1 1514 Bus Width Setting 00 16 bit bus width 13 12 11 10 9 8 T 6 1 0 476 for External Memory Space 3 Bus Width Setting for External Memory Space 2 Bus Width Setting for External Memory Space 1 Bus Width Setting for External Memory Space 0 Address Setting for Burst Operation Burst ROM setting for External Memory Space 3 Burst ROM setting for External Memory Space 2 Burst ROM setting for External Memory Space 1 Burst ROM setting for External Memory Space 0 Wait Setting for Internal I O Space MN102H55D 55G F55G 01 8 bit bus width 10 Reserved 11 8 bit bus width when A8 is high 16 bit bus width when A8 is low MEMMD1 00 82 Memory Mode Setup 1 Register 16 bit access register MEMMD sets the bus width for external memory and the wait cycles for internal I O registers Do not access the burst ROM area and
345. WM output Setting the port 5 direction control register PSDIR is not required The PWM is output regardless of the PSDIR register value P5SLMD x O0FFF8 7 6 5 4 3 2 1 0 PS P5 P5 P5 P5 PS PS P5 LMD7LMDGLMDS ILMDAILMD3LMD2LMDILMDO 0 0 0 0 1 0 1 0 MN102H55D 55G F55G 179 respectively This starts the timer When the timer 0 binary counter reaches 0 the value 1 of the timer 0 base register is loaded automatically to the TM8BC counter 8 Set TMI3LD TMI3EN and TM13CLR of the TM13MD register to 0 1 and 0 at the next count TM13MD x 00FE28 Chapter 4 Timers 8 TM13MD Figure 4 6 3 8 bit PWM Timing W 5 W TM13CA TM13MD 4 Ut e te 527 Pen EN papa 2l cea J smua l 222 L uc uc 5 E 1 1 11 a Y Betti M E Ls I 1 das g P E oe 5 lt ES o icu ELE S 3 Jac E S Y sn Y oo e zn ELT BEEN n M O ans een cee me a 22
346. Width Counter Setup 184 4 8 1 16 bit Pulse Width Measure Counter 184 Chapter5 Serial Interface 5 1 5 2 Serial Interface een e Ten eet ee 188 5 1 1 etti et Lo tue EC ees 188 5 1 2 Control Registers 190 5 1 3 Serial Interface Connection 2 194 Serial Interface Setup Examples 2 197 5 2 1 Serial Transmission in Asynchronous Mode 197 5 2 2 Serial Reception in Synchronous Mode 200 5 2 3 Serial Clock Operation Example 203 5 2 4 Transmission 207 5 2 5 Reception e ien ee dette Pe teenth 209 Chapter 6 Analog Interface 6 1 6 2 Summary of A D Converter 212 6 1 1 ed Lucia e Had de EC ee 212 6 1 2 Control Registers 219 A D Converter Setup Examples sse eene 222 6 3 6 4 6 2 1 Single Channel A D Conversion 6 2 2 Three Channel A D Conversion Summary of D A Converter 6 3 1 GM EM 6 3 2 Control Registers D A Converter Setup Examples Chapter7 7 1 7 2 7 3 7 4 Summary Of 7 1 1
347. Z Hi Z excapt P17 Hi Z excapt P17 Depends on pin setting Note 1 Single chip mode Note 2 Processor mode address data separated mode Note 3 Processor mode address data shared mode Note 5 High during STOPO 1 mode Note 4 Low during STOPO 1 mode Note 6 High during STOPO 1 HALT1 mode MN102H55D 55G F55G 521 Chapter 11 Appendix 522 MN102H55D 55G F55G 11 3 Initialization Program The initialization program must be executed first after reset release The initialization program should be allocated on x 80000 in single chip mode memory expansion mode or processor mode Initialization Program start equ x 080000 jmp init init equ Register Initialization sub 40 40 40 41 40 42 mov 40 0 mov 40 21 mov 40 2 mov STACK_TOP a3 mov d0 mdr Memory Mode Setting mov EXW_INT d0 mov d0 Exwmd 40 43 mov 40 mov d0 Memmd1 mov 2 40 mov d0 Memmd2 mov DRAMI 40 mov d0 Drammd1 mov 2 40 mov dO Drammd2 Other Setting Interrupt Enable mov INIT 5 40 mov dO psw Clear register to 0 Execute this operation although this step is not always required Set the initial value of the stack pointer Always set the even address Set the number of waits for external memory space Select the ex
348. ace The MN102H55D 55G F55G contains two serial interfaces serial 3 and serial 4 with asynchronous mode clock synchronous mode and mode It also has three serial interfaces serial 0 serial 1 and serial 2 reserved for clock synchronous mode The maximum baud rate in clock synchronous mode is 8 5 Mbps The maximum baud rate in asynchro nous mode is 28800 bps with a 34 MHz oscillator 1228800 bps is possible by setting the oscillation frequency to 19 6608 MHz Signal from 8 bit Timer Timer 1 underflow Timer 2 underflow E 7 Transmitter m I SBTO 5 RXC Receiver lt 80 TXD gt SBO1 Transmitter TXC r SBT1 EE RXC eceiver 41 Signal from 8 bit Timer Timer 4 underflow Timer 5 underflow E _ Transmitter TXD m XC ro r SBT2 lt Receiver XD 4 sBl2 TXD SBO3 Transmitter E SDA3 SBT3 ae RXC SCL3 eceiver 7 Signal from 8 bit Timer Timer 1 underflow Timer 5 underflow m m Transmitter TD Boos RXC iver eceivel RXD SBO4 SDA4 I sBT4 SCL4 I SBI4 y Figure 5 1 1 Serial Interface Configuration lt Table 5 1 1 Serial Interface Functions Chapter 5 Serial Interface Clock Synchronous Mode Asynchronous Mode Mode Parity None 0
349. al Interface 2 This pin can be used as a data input pin for serial interface Data Input 2 Because pin 14 has the same function either pin 14 or pin 50 must be selected Refer to Chapter 5 Serial Interface SBT3 y o Serial Interface 3 This pin can be used as a synchronous transfer clock sig Clock Input Output nal input output pin for serial interface 3 Refer to Chapter 5 Serial Interface SCL3 Output Serial Interface 3 This pin can be used as clock signal output pin for Clock Output serial interface 3 Refer to Chapter 5 Serial Interface 51 P83 yo General purpose Port 83 This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports TM4IO Timer 4 Input Output This pin can be used as a timer 4 input output pin Refer to Chapter 4 Timers SBI3 Input Serial Interface 3 This pin can be used as a data input pin for serial interface Data Input 3 Refer to Chapter 5 Serial Interface MN102H55D 55G F55G 41 Chapter 1 General Description Table 1 4 1 List of Pin Functions 21 26 Clock Output Pin Number Pin Name yo Function Description 52 P84 General purpose Port 84 This be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull
350. al Timer Configuration Example 8 bit Timer 122 Interval Timer Block Diagram 8 bit Timer 122 Interval Timer Timing 8 bit Timer 125 16 bit Timer Block Diagram see 126 One phase PWM Output Timing 128 One phase PWM Output Timing with Data Rewrite 128 Two phase PWM Output Timing 128 One shot Pulse Output Timing 129 External Control Timing 129 Event Counter Input Timing 129 Input Capture 1 Timing 130 Input Capture 2 Timing sse 130 Two phase Encoder 4x Timing 131 Two phase Encoder 1x Timing sese 131 Timer 8 Block Diagram sss 135 Timer 9 Block Diagram esee 135 Timer 10 Block Diagram sem 136 Timer 11 Block Diagram sse 136 Timer 12 Block Diagram sse 136 Event Counter Block Diagram 137 Event Counter Timing 16 bit Timer 139 One phase PWM Output Block Diagram 16 bit Timer 140 One phase PWM Output Timing 16 bit Timer 143
351. apter 11 Appendix 338 MN102H55D 55G F55G Chapter 11 Appendix 11 2 Data Appendix 11 2 1 List of Special Registers MN102H55D 55G F55G 339 Chapter 11 Appendix About This Section Description of Each Page Each page of this chapter describes one or more registers Each page lists the register name address register access bit map flag explanation of each bit number and supplementary explanation The following is the layout and definition of this section Bit Map Bit Number Flag Name Access R Read only 15 14 13 12 11 10 9 8 7 6 5 4 4 2 1 0 z Write EN MDI MDO DB8 DI 588 SI 103 IQ2 101 100 2 R W R W R W R W R W R W R W R W R R W R W R W R W R W Read Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 Value at reset 15 Transfer Busy Start Flag 0 Disable Chapter 9 Appendix AT3CTR Register x 00FD30 lt ATC 3 Control Register 16 bit access register lt Register Access Sets the ATC3 operating control Read value 1 Transfer start transfer in progress conditions 0 Always 0 14 13 Transfer Mode 00 One byte word transfer es Two 2 1
352. ared without Wait Read Write 332 Data Transfer Signal Timing Address Data Shared with Wait 1 5 or More Read Write 333 Data Transfer Signal Timing Address Data Shared with Wait 1 5 or More ALE Late Long Mode AD Long Mode Read 334 Data Transfer Signal Timing Address Data Shared with Wait 1 5 or More ALE Late Long Mode AD Long Mode Write 335 Bus Authority Request Signal Timing 336 Interrupt Signal Timing 2 336 Serial Interface Signal Timing 1 Synchronous Serial Transmission Transfer in Progress 336 Serial Interface Signal Timing 2 Synchronous Serial Transmission Transfer End Timing at SBT Input 336 Serial Interface Signal Timing 3 Synchronous Serial Transmission Transfer End Timing at SBT Output 337 Serial Interface Signal Timing 4 Synchronous Serial Reception Transfer End Timing at SBT Input 337 Timer Counter Signal Timing sese 337 Memory Map for Flash EEPROM Version 524 Flash EEPROM Program Flow 525 8 bit Serial Interface Block Diagram for Serial Writer 526 Flash EEPROM Memory Space 527 Pin Configuration During
353. at reset ALE late 1 5 mode ALEG 01 00 ALE Long Mode in CSO Area ALE long 0 mode ALE long 0 5 mode ALE long 1 mode at reset ALE long 1 5 mode ALEL 11 10 ALE Late Mode in CS1 Area ALE late 0 mode at reset ALE late 0 5 mode ALE late 1 mode ALE late 1 5 mode ALEG 11 10 ALE Long Mode CS1 Area ong 0 mode at reset ong 0 5 mode ong 1 mode ong 1 5 mode ALEL 21 20 E Late Mode in CS2 Area ate 0 mode at reset ate 0 5 mode ate 1 mode ate 1 5 mode ALEG 21 20 ALE Long Mode in CS2 Area ALE long 0 mode at reset ALE long 0 5 mode ALE long 1 mode ALE long 1 5 mode ALEL 31 30 ALE Late Mode in CS3 Area ALE late 0 mode at reset ALE late 0 5 mode ALE late 1 mode ALE late 1 5 mode ALEG 31 30 ALE Long Mode in CS3 Area ALE long 0 mode at reset Please refer to Table 2 2 6 on ALE long 0 5 mode on ALE long 1 mode page 79 for the timing ALE long 1 5 mode 60 MN102HF55G H55G H55D Chapter 2 Bus Interface The MPXADR register sets the address output timing for the external memory spaces 0 to 3 during address data shared mode MPXADR x 00FF8C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADL ADL ADL ADL ADL ADL ADL ADL 31 30 21 20 11 10 01 00 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ADL 01 0
354. ata is updated when ever the last data bit seventh or eighth bit is received Do not use the SCORBY flag to set polling for the received data wait in clock synchronous mode Use the interrupt service rou tine the serial interrupt flag or the SCORXA flag 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCI SCI reserv 1 1 1 SCI SCI 5 1 SCI TEN REN BRE ed ed OD ed LN 2 1 SB S1 SO R W R W R W R W R W R R W R W R W R W R W R W R W R R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o o on 15 Transmit Enable 0 Disable 1 Enable 14 Receive Enable 0 Disable 1 Enable 13 Break Transmission 0 Don t break 1 Break 12 Reserved Set to 0 11 Reserved Set to 0 9 Bit Order Selection 0 LSB first 1 MSB first Select only when the character length is 8 bit 8 Reserved Set to 0 7 Character Length 0 7 bit 1 8 bit 64 Parity Bit Selection 000 100 0 output low 101 1 output high 110 Even 1s are even 111 Odd 1s are odd Others Reserved 3 SBO1 Output Hold Time 0 More than BOSC cycles 1 More than timer 1 underflow cycles 1 0 Serial 1 Clock Source 00 SBT1 pin Selection 01 Timer 1 underflow 1 8 10 Timer 2 underflow 1 2 11 Timer 2
355. ates the group number When the first address of the interrupt service routine add the contents of the IAGR register to the first address of the table in which registered vector address for each interrupt servicing The IAGR register is only read Watchdog Interrupt Detect Flag 1 0 NMID R R W 0 0 No interrupt detected 1 Interrupt detected 1 0 WDID R R W 0 0 0 No interrupt detected 1 Interrupt detected 1 0 UNID R R W 0 0 Undefined Instruction Interrupt Detect Flag 0 No interrupt detected 1 Interrupt detected Chapter 11 Appendix 00 40 Nonmaskable Interrupt Control Register 8 bit access register NMICR verifies a nonmaskable interrupt WDICR x 00FC42 Watchdog Interrupt Control Register 8 bit access register WDICR verifies a watchdog in terrupt UNICR 00 44 Undefined Instruction Interrupt Control Register 8 bit access register UNICR verifies an undefined in struction interrupt MN102H55D 55G F55G 343 Chapter 11 Appendix 7 5 4 3 2 R R 0 0 0 0 0 0 0 0 0 344 MN102H55D 55G F55G EIICR 00 46 Error Interrupt Control Register 8 bit a
356. burst ROM This section shows the connection Examples Example of SRAM Mask ROM Connection 16 bit Bus Width 1 Wait MN102HF55G SRAM SRAM 256 K 8bit 256 K 8bit P50 CSO cs CS A19 1 A18 0 A18 0 D15 8 D7 0 D7 0 D7 0 P61 RE OE OE P63 WEH WE P62 WEL WE Figure 2 1 2 SRAM Mask ROM Connection Example 16 bit Bus Width 5 4 3 2 11 10 9 8 z 6 4 3 2 0 EW EW EW EW EXWMD 03 02 01 00 0 0 0 5 4 3 2 11 10 9 8 2 6 4 3 2 0 MEMMDI callers 0 0 0 5 4 3 2 11 10 9 8 7 6 4 3 2 0 DRAMMDI 0 7 6 5 4 3 2 0 PO PO POMD MDI 0 7 6 5 4 3 2 0 PI PI PILMD LMDI LMDO 0 T 6 5 4 3 2 0 P2 P2MD 7 6 5 4 3 2 0 7 6 5 4 3 2 1 0 P3HMD P3LMD P3 HMD7 HMD6 HMD5 HMD4 HMD3 HMD2 HMDI HMDO LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMDI LMDO 0 1 0 0 1 0 0 1 0 1 0 1 0 1 7 6 5 4 3 2 0 P4 P4 P4 P4 P4LMD LMD3 LMD2 LMDI LMDO 1 if 7 6 5 4 3 2 0 5 5 PSLMD LMDI LMDO 0 7 6 5 4 3 2 0 P6 P6 P6 P6MD MDS 1 1 MN102HF55G H55G H55D Example SRAM Mask ROM Connection 8 bit Bus Width 1 Wait EXWMD MEMMDI DRAMMDI POMD PILMD P2MD P3HMD P4LMD PSLMD
357. capture A interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the KILV 2 0 bits of the KIICH register MN102H55D 55G F55G 367 Chapter 11 Appendix F 6 5 4 3 2 0 TMIIB ITM11B IR ID R R R R W R R R 0 0 0 0 0 0 0 0 0 1 0 0 1 4 Timer 11 Capture Interrupt Request Flag 0 Timer 11 Capture B Interrupt Detect Flag 7 6 5 4 3 2 0 2 s IE R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 11 Capture Interrupt Enable Flag 368 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 Interrupt undetected 1 Interrupt detected 0 Disable 1 Enable TM11BICL x OOFC7E Timer 11 Capture B Interrupt Control Register 8 bit access register TM11BICL requests and verifies timer 11 capture B interrupt This register allows only byte accesses Use the MOVB in struction to set the data TM11BICH x OOFC7F Timer 11 Capture B Interrupt Control Register 8 bit access register TM11BICH enables a timer 11 capture B interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the KILV 2 0 bits of the KIICH register Chapter 11 Appendix 6 5 ADI
358. ccess register EIICR verifies an error interrupt This register does not exist When an interrupt vector is not determined this register indi cates an error by writing IAGR register to Chapter 11 Appendix 615 2 3 2 14009 IQOICL E E 100 2 1Q0 0 I ib 00 50 REPRAN OR EROS SR R External Interrupt 0 oloflolololoTo o o o Control Register 8 bit access register External Interrupt 0 0 No interrupt requested Request Fla 1 Interrupt requested q 9 pereg external interrupt 0 interrupt External Interrupt 0 0 No interrupt detected This register allows only byte Detect Flag 1 Interrupt detected accesses Use MOVB instruc tion to set the data IQOICH 100 1Q0 100 1Q0 LV2 LVI LVO IE x OOFC51 SS ee External Interrupt 0 0 0 0 0 0 0 0 on on o 0 Control Register 8 bit access register External Interrupt 0 Set the level from 0 to 6 IQOICH sets an external inter Level Setup O interrupt level and en ables an interrupt External Interrupt 0 Interrupt 0 Disable Enable Flag 1 Enable This register allows only byte accesses Use MOVB instruc tion to set the data MN102H55D 55G F55G 345 Chapter 11 Appendix 7
359. ccurs PUM Regi i i CPUM Register WDREG register De Chip Reset Control Control BOSC Watchdog Timer Extended Watchdog Timer Watchdog Interrupt Generate pulse signal of Generate Watchdog interrupt BOSC divisor of 25 213 215 of watchdog timer output divisor 217 see note of 1 22 2 26 28 20 212 Figure 3 1 2 Watchdog Timer Block Diagram Notices When Using Watchdog Interrupt The watchdog interrupt is used to detect error operations Because of this the CPU normal operation cannot be guaranteed after the watchdog interrupt service routine Therefore do not return the old program from the watchdog interrupt service routine The watchdog interrupt occurs in the following cases 1 The program cannot be executed using the normal algorithm due to the infinity loop or error operations 2 The CPU hangs up due to the device errors or system errors The CPU hangs up the response signal without recognizing during the access to the external device Especially in case of 2 the instruction in progress enters the interrupt service routine without completing the instruction execution because the CPU terminates the bus cycles forcibly In addition the data may not be transferred correctly during the ATC operation Due to this the normal program operation cannot be guaranteed even though the program returns from the interrupt service routine Chapter 3 Interrupt
360. ception data Reset the first address of the secured space to the ATCO destination address pointer ATODST 10 Set the bytes to be transferred automatically In this example 5 byte data is transferred so that the value 4 subtracting 5 by 1 is set to the ATCO transfer word count register ATOCNT ATOCNT x 00FD02 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATO ATO ATO ATO CNTIH CNTIOCNTO9 CNTS8 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNTI CNTO 0 0 0 0 0 0 0 0 0 1 0 0 11 Set ATCO control register ATOCTR Reselect serial 0 reception end interrupt Select the conditions as set in procedure 4 12 Verify that a serial 0 reception end interrupt does not occur If the serial 0 recep tion end interrupt occurs avoid the interrupt by setting the ATOEN flag of the ATOCTR register to 1 start the first byte data transfer by software The data after the second byte is transferred automatically with the serial reception end interrupt Chapter 7 ATC ETC 7 3 Summary of ETC 7 3 1 Overview The MN102H55D 55G F55G contains an external transfer control ETC The ETC has two channels to transfer the data between the external memory and the external device The data transfer request oc curs when DMAREQ 1 0 become low DMAACK 1 0 become low when the ETC accepts the data transfer request The time requ
361. cess register IQ3ICL requests and verifies an external interrupt 3 interrupt This register allows only byte accesses Use MOVB instruc tion to set the data IQSICH 69 External Interrupt 3 Control Register 8 bit access register sets an external inter rupt 3 interrupt level and en ables an interrupt This register allows only byte T accesses Use instruc tion to set the data MN102H55D 55G F55G 357 Chapter 11 Appendix 7 6 5 4 3 2 1 0 TM3U TM3U IR ID R R R R W R R R R 0 0 0 0 0 0 0 on o 0 1 4 Timer 3 Underflow Interrupt Request Flag 0 Timer 3 Underflow Interrupt Detect Flag 7 6 5 4 3 2 1 0 2 s TM3U IE R R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 3 Underflow Interrupt Enable Flag 358 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected 0 Disable 1 Enable TM3UICL x O0FC6A Timer 3 Underflow Interrupt Control Register 8 bit access register TMSUICL requests and verifies a timer 3 interrupt This register allows only byte accesses Use the MOVB in struction to set the data TM3UICH x OOFC6B Timer 3 Underflow Interrupt Control Register 8 bit access register TM3UICH enables a timer in terrupt This register allows only b
362. cess register SCATICH sets a seial 4 trans mission end interrupt level and enables an interrupt This register allows only byte accesses Use the MOVB in struction to set the data MN102H55D 55G F55G 383 Chapter 11 Appendix 7 6 5 4 3 2 0 SCAR SC4R IR ID R R R R W R R R 0 0 0 0 0 0 0 on o 0 1 4 Serial 4 Reception End 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 0 Serial 4 Reception End 0 Interrupt undetected Interrupt Detect Flag 1 Interrupt detected 7 6 5 4 3 2 0 5 I SC4R IE R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 1 0 Serial 4 Reception End 0 Disable Interrupt Enable Flag 1 Enable 384 MN102H55D 55G F55G SCARICL x O0FCA2 Serial 4 Reception End Interrupt Control Register 8 bit access register SCARICL requests and verifies a seial 4 reception end interrupt This register allows only byte accesses Use the MOVB in struction to set the data SCARICH 4 Interrupt Control Register 8 bit access register SC4RICH enables a serial 4 re ception end interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the SC4TLV 2 0 bits of the SC4TICH register Chapter 11 Appendix DT
363. ch written data is swapped and read as follows Point byte swap registers PBSWPH x 00FFBE PBSWPL x 00FFBC Initial values are all 0 bp23 16 15 87 0 A B C WRITE C B A READ Long word byte swap registers LBSWPH xOOFFCE LBSWPL x0OOFFCC Initial values are all 0 bp31 24 23 1615 87 0 A B C D WRITE D C B A READ Figure 8 3 1 Byte swapped Register The MN102H55D 55G F55G has no byte swapped registers for the word data When the word data needs to be swapped use the byte swapped register for long word data Write the word data to LBSWPH 00 and read the data from LBSWPL or vice versa MN102H55D 55G F55G Chapter 9 System Control 9 Chapter 9 System Control Q In the MN102HF55G Flash ROM version or ICE this func tion cannot be used In addition in the MN102H55D 55G the ad dress break 0 1 generation flags of the address break control reg ister cannot be used Instead the function of these flags are substituted by verifying whether the PC values upper or lower bits on the stack pointer match the address break 0 1 address pointer during NMI interrupt rou tine service 1 Set the first address of the struction code to be suspended to the address break address pointer 1 The address break function makes the CPU suspend ex ecuting all instructions 280 MN102H55D
364. circuit 1 0 Clock Source Selection 00 BOSC 2 01 4 10 BOSC 11 TMOIO pin input 7 6 5 4 3 2 1 0 1 TM 1 EN LD 51 so R W R W R R W R W 0 0 0 0 0 0 0 0 on o 0 0 7 TM1BC Count 0 Disable 1 Enable 6 Load TM1BR to TM1BC 0 Disable 1 Enable Reset the 1 2 divisor circuit 1 0 Clock Source Selection 00 BOSC 2 442 MN102H55D 55G F55G 01 Timer 0 underflow 10 Timer 0 cascade 11 Timer 4 underflow TMOMD 00 20 Timer 0 Mode Register 8 bit access register TMOMD sets the timer 0 operat ing conditions When BOSC is selected as the clock source the valid range for TMOBR is 1 to 255 TM1MD 00 21 Timer 1 Mode Register 8 bit access register 16 bit access is possible from even address TM1MD sets the timer 1 operat ing conditions Chapter 11 Appendix 7 6 5 4 3 2 1 0 TM2MD TM2 TM2 TM2 TM2 EN LD 1 80 22 RW RW Timer 2 Mode Register 0 0 0 0 0 0 0 0 on 0 0 8 bit access register 7 TM2BC Count 0 Disable TM2MD sets the timer 2 operat 1 Enable ing conditions 6 Load TM2BR to TM2BC 0 Disable 1 Enable Reset the 1 2 divisor circuit 1 0 Clock Source Selection 00 BOSC 2 01 Timer 0 underflow 10 Timer 1 cascade 11 Timer 4 underflow 7 6 5 4 3 2 1 0 TM3MD TM3 TM3 TM3 TM3 EN LD 1 8
365. commands and options for the C complier MN10200 Series Linear Addressing High speed Version C Compiler User Manual Language Description Describes the syntax for the C complier MN10200 Series Linear Addressing High speed Version C Compiler User Manual Library Reference Describes the standard libraries for the C complier MN10200 Series Linear Addressing High speed Version Cross Assembler User Manual Language Description Describes the assembler syntax and notation MN10200 Series Linear Addressing Version Source Code Debugger User Manual Describes the use of the C source code debugger MN10200 Series Linear Addressing Version PanaXSeries Installation Manual Describes the installation of the C complier cross assembler and C source code debugger and the procedures for using the in circuit emulator Questions and Comments Please send your questions comments and suggestions to the semiconductor design center closest to you See the last page of this manual for a list of addresses and tele phone numbers Contents Chapter 1 General Description Chapter 2 Bus Interface Chapter 3 Interrupts Chapter 4 Timers Chapter 5 Serial Interface Chapter 6 Analog Interface Chapter 7 ATC ETC Chapter 8 Ports Chapter 10 System Control Chapter 11 Low power Modes Chapter 11 Appendix Contents o Contents Chapter1 General Description 1 1 General Description
366. conditions 14 TM10BC T F F RS F F 0 Set TM10BC T F F RS F F to 0 Operation 1 Operate TM10BC T F F RS F F 11 10 Up Down Counter Mode 00 Up counter Selection Ignored when two 01 Down counter phase encoding is selected 10 Up when TM10IOA pin is high down when TM10IOA pin is low 11 Up when TM10IOB pin is high down when 1 pin is low 9 Count Start External Trigger 0 Disable Enable 1 Start counting on the falling edge of pin 8 Counter Operating Mode 0 Repeat 1 One shot counting During repeat counting hold the Selection TM10EN flag state During one shot counting set the TM10EN 7 6 TM10CB Operating 00 Compare register single buffer Wen Mode Selection 01 Compare register double buffer 10 Capture when TM10IOA pin is high Capture B when TM10IOA pin is low 11 Capture A when TM10IOA pin is high Capture B when TM10IOB pin is high 5 TM10BC Clear 0 Dont clear 1 Clear when external synchronization is used 4 TM10BC Count Range 0 0to FFFF 1 0to TM10CA 3 TM10IOA Pin Output 0 RS F F output one phase PWM 1 T F F output two phase PWM 2 0 Clock Source Selection 000 Timer 0 underflow The TM10IOB pin edge is set in 001 Timer 4 underflow the TM10MD2 register 010 TM10IOB pin Rising falling both edges 011 BOSC 2 100 Two phase encoder 4x of TM10IOA pin TM10IOB pin 101 Two phase encoder 1x of TM10IOA pin TM10IOB 450 MN102H55D 55G F55
367. conversion end interrupt 1111 Key interrupt MN102H55D 55G F55G 9 69 340 MN102H55D 55G F55G Chapter 11 Appendix 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 CPUM WD WD WD OSC STOP HALT OSCI 5 RST ID 00 00 RW RW RW R R R R R R R R W R CPU Mode Control 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 on o 0 0 0 0 0 0 on Register 15 Watchdog Timer Enable 0 Enable 1 Disable and clear 16 bit access register 14 13 Watchdog Timer Count 00 27 modes and oscillator for watchdog 01 25 timer 10 213 11 2 5 Shorten the oscillation time from bit Watchdog Interrupt Return Time From STOP mode a watchdog timer 14 Cycle BOSC Signal STOP Mode interrupt cycle The same counter is 00 2 cycles 217 1 fosci used for setting both values Setthe 0 2 cycles 2 x 1 fosci 10 213 cycles 213 1 fosci WDREG register to extend the watchdog timer interrupt cycle addi tionally 11 215 cycles 2 x 1 fosci In the MN102HF55G set these bits to only 00 4 System Clock Monitor 0 OSCI input 1 Low speed clock input 3 2 CPU Operating Control STOP HALT OSCI OSCO CPU Mode CPU Clock OSCID Value 0 0 0 0 NORMAL On OSCI 0 0 0 1 1 SLOW On XI 1 1 0 Oscillator
368. cted 0 Disable 1 Enable TM9UICL x OOFC5E Timer 9 Underflow Interrupt Control Register 8 bit access register TM9UICL requests and verifies a timer 9 interrupt This register allows only byte accesses Use MOVB instruc tion to set the data TM9UICH x OOFC5F Timer 9 Underflow Interrupt Control Register 8 bit access register TM9UICH enables a timer 9 in terrupt This register allows only byte accesses Use MOVB instruc tion to set the data The inter rupt level is the same level set in the IQ1LV 2 0 bits of the IQ1ICH register 7 6 5 4 2 0 102 102 IR ID R R R W R R 0 0 0 0 0 0 0 0 0 1 4 External Interrupt 2 0 No interrupt requested Request Flag 1 Interrupt requested 0 External Interrupt 2 0 No interrupt detected Detect Flag 1 Interrupt detected 7 6 5 4 2 0 IQ2 102 102 102 LV2 LVI LVO IE R R W R W R W R R W 0 0 0 0 0 0 0 0 1 6 4 External Interrupt 2 Set the level from 0 to 6 Level Setup 0 External Interrupt 2 Interrupt 0 Disable Enable Flag 1 Enable Chapter 11 Appendix IQ2ICL 00 60 External Interrupt 2 Control Register 8 bit access register IQ2ICL requests and verifies an external interrupt 2 interrupt This register allows only byte accesses Use MOVB instruc tion to set the data IQ2ICH x 0OOFC61 Exter
369. ctions including DMA handshake function and bus arbitration 9 C language Development Environment The MN102H series has simple hardware optimized for C language programming and highly efficient C compiler With this advantage this series improves development environment for C language embedded applications without expanding the program size The PanaXSeries development tools support the MN102H series devices 10 Outstanding Power Savings The MN102H series contains separate buses for instructions data and peripheral func tions which distribute and reduce load capacitance This reduces overall power con sumption The MN102H series also supports three modes of SLOW HALT and STOP for power savings PanaXSeries is a trademark of the Matsushita Electric Industrial Co Ltd Chapter 1 General Description 1 1 3 Overview This section describes the basic configuration and functions of the MNI102H55D 55G F55G Note 1 These bits change de pending on all 24 bits of the op eration result Processor Status Word PSW Mois 2 Theda bits change do The PSW register contains the operating result flags and interrupt mask level flags pending on the lower 16 bits of the operation result 1 2 7 15 8 7 0 The IE flag should be set to 0 PSW IST 51 SO IE 2 IM1 IMO VX CX NX ZX VF NF ZF before the IM 2 0 flags of PSW Reset
370. d The ETnSRC register and the ETnDST register write only 24 bit data or 16 bit data Use the MOV instruction or the MOVX instruction to set the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETn ETn ETn ETn ETn ETnD 5 T DSTI5 DST14 DST13 DSTI2 DST11 DSTIO DST9 DST8 DST7 DST6 DSTS DST4 DST3 DST2 DSTI DSTO Reset undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 7 6 3 4 3 2 1 0 _ _ ETn ETn ETn DST23 DST22 DST21 DST20 DST19 DST18 DSTI7 DSTIG Reset 0 0 0 0 0 0 0 undefined undefined undefined undefined undefined undefined undefined undefined MN102H55D 55G F55G 245 Chapter 7 ATC ETC 246 Table 7 3 2 List of ETC Control Registers Register Address Function ETOCTR 00 40 ETC 0 Control Register ETCO ETOCNT 00 42 ETC 0 Transfer Word Count Register ETOSRC 00 44 ETC 0 Source Address Pointer ETODST 00 048 ETC 0 Destination Address Pointer ETICTR 00 50 ETC 1 Control Register ETCI ETICNT 00 052 ETC 1 Transfer Word Count Register ETISRC 00 054 ETC 1 Source Address Pointer ETIDST 00 058 1 Destination Address Pointer MN102H55D 55G F55G Chapter 7 ATC ETC 7 4 Setup Examples 7 4 1
371. d Detect Flag 1 Interrupt detected 7 6 5 4 3 2 0 KI KI KI KI LV2 LVI LVO IE R R W R W R W R R W 0 0 0 0 0 0 0 o 0 0 1 6 4 External Key Interrupt Set the level from 0 to 6 Level Setup 0 External Key Interrupt 0 Disable Enable Flag 1 Enable Chapter 11 Appendix KIICL 00 78 External Key Interrupt Control Register 8 bit access register KIICL requests and verifies an external key interrupt interrupt This register allows only byte accesses Use the MOVB in struction to set the data KIICH x 00FC79 External Key Interrupt Control Register 8 bit access register KIICH sets an external key inter rupt level and enables an inter rupt This register allows only byte accesses Use the MOVB in struction to set the data MN102H55D 55G F55G 365 Chapter 11 Appendix 7 6 5 4 3 2 1 0 59 50 IR ID R R R R W R R R R 0 0 0 0 0 0 0 o o 0 4 Timer 5 Underflow Interrupt Request Flag 0 Timer 5 Underflow Interrupt Detect Flag 7 6 5 4 3 2 1 0 2 s TMS5U IE R R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 5 Underflow Interrupt Enable Flag 366 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected 0 Disable 1 Enable x O0FC7A
372. d Detect Flag 1 Interrupt detected 7 6 5 4 3 2 1 0 IE R R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Transfer End Interrupt 0 Disable Enable Flag 1 Enable 386 MN102H55D 55G F55G ETC1ICL x O0FCAe6 ETC 1 Transfer End Interrupt Control Register 8 bit access register ETC1ICL requests and verifies a ETC 1 transfer end interrupt This register allows only byte accesses Use the MOVB in struction to set the data ETC1ICH x 00FCA7 ETC 1 Transfer End Interrupt Control Register 8 bit access register ETC1ICH enables a ETC 1 transfer end interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the SC4TLV 2 0 bits of the SC4TICH register Chapter 11 Appendix 6 5 4 3 2 1 0 ATOICL 2 0 m x 00FCA8 R URANO R ATC 0 Transfer End Interrupt Control Register 8 bit access register ATC 0 Transfer End Interrupt 0 No interrupt requested ATOICL requests and verifies an Request Flag 1 Interrupt requested ATC 0 transfer end interrupt 0 Transfer End Interrupt 0 Interrupt undetected This register allows only byte Detect Flag 1 Interrupt detected accesses Use the MOVB in struction to set the data
373. d is set to the channel selection bits AN1CH 2 0 ANNCH 2 0 are ignored When the software starts the conversion write 0 and 1 to the timer conversion start flag ANTC and the conversion start execution flag ANEN of the A D converter control register ANCTR respectively When ANTC 1 the ANEN flag becomes 1 at timer 3 underflow The ANEN flag remains 1 during the conversion To end the conversion write 0 to the ANEN flag Start Stop Interrupt request State Non conversion Nch conversion Nch conversion Nch conversion Nch conversion ANEN Figure 6 1 5 Single Channel Continous Conversion Timing Multiple Channels Continuous Conversion Timing When the operating mode selection bits ANMD 1 0 are set to multiple channels continuous conversion the A D converter converts multiple consecutive AN input signals continuously An interrupt occurs when the conversion sequence ends The channel selection bits 2 0 are set to channel 0 and the number of the final channel to be converted is set to ANNCH 2 0 The conversion always starts with channel 0 When the software starts the conversion write 0 and 1 to the timer conversion start flag ANTC and the conversion start execution flag ANEN of the A D converter control register ANCTR respectively When ANTC 1 the ANEN flag becomes 1 at timer 3 underflow The A
374. d this converted result is stored in ANnBUF The A D converter converts the voltage between Vref and Vref divided into 1024 Conversion Time 2 83 us or more per channel 3 73 us per channel with 30 MHz external oscillator Clock Source Internal Clock BOSC divided by 2 4 8 16 Operating Mode 30 operating modes Single conversion of channel 0 to n n 1 to 7 Single conversion of channel m m 0 to 7 Continous conversion of channel 0 to n n 1 to 7 Continous conversion of channel m m 0 to 7 Converstion Start Timer 3 underflow or register setting Interrupts An interrupt occurs each time the conversion sequence ends Selecting the A D Converter Clock Source The A D converter clock source is selected to BOSC 2 BOSC 4 BOSC 8 or BOSC 16 as the A D conversion time is 2 8 us or more at 10 bit resolution and 2 4 us or more at 8 bit resolution Calculate the A D conversion time as follows Conversion time s 10 bit resolution 14 x BOSC cycle Clock Source ch Conversion time s 8 bit resolution 12 x BOSC cycle Clock Source ch For example when the A D converter clock source is selected to BOSC 8 the conver sion time is BOSCx112 cycles 10 bit resolution Figure 6 1 2 shows the A D Con verter timing Generate an interrupt State S H bp9 bp8 bp7 bp6 bp5 bp4 bp3 bp2 bp1 bp0 Transter In conti Write to register n
375. d to the SC3TRB register transmission starts synchronizing with timer 5 5 Execute the interrupt service routine when a serial transmission end interrupt oc curs The interrupt service routine determines the interrupt group and vector and clears the SC3TIR flag 6 Write the next data After the data is written transfer starts in 1 2 cycles of the transfer base clock timer 5 underflow Figure 5 2 2 illustrates the timing of asynchronous transmission Timer 5 underflow FL FL FL FL FL H H H RR AL AL AL AL AL AL AL ALL H H SC3TRB write ST bo b1 b2 b3 b4 b5 be b7 interuptrequest 101 02 i i GE EEG Interrupt routine M a s Figure 5 2 2 Serial 3 Asynchronous Transmission Timing MN102H55D 55G F55G 199 Chapter 5 Serial Interface 5 2 2 Serial Reception in Synchronous Mode This section describes the example of serial interface 0 reception in syn chronous mode with the following settings LSB first bit order Q 8 bit data transfer odd parity The data is received when a serial reception end interrupt occurs D A Converter P6 i SBIO pin 1 Interrupt A D Converter P7 SBTO pin P2 8 bit Timer Serial 8 P3 16 bit Timer ATC P9 P4 8 bit PWM ETC P
376. d24 Dm mem8 abs16 Dn CC Dn abs16 l abs16 h MOVBU abs24 Dn mem8 abs24 gt Dn F4 08 Dn abs24 l abs24 m abs24 h EXT Dn If Dn bp15 0 x 0000 MDR If Dn bp15 1 xFFFF MDR N OQ N F3 C1 Dn lt lt 2 6 EXTX Dn If Dn bp15 0 Dn amp x 00FFFF gt Dn If Dn bp15 1 Dn 0000 EXTXU Dn Dn amp x 00FFFF gt Dn EXTXB Dn If Dn bp7 0 Dn amp x 0000FF gt Dn If Dn bp7 1 Dn x FFFFOO gt Dn EXTXBU Dn Dn amp x 0000FF gt Dn BC Dn ADD Dn Dm Dm Dn 5Dm 90 Dn lt lt 2 Dm ADD Dm An An Dm gt An F2 00 Dm lt lt 2 An ADD An Dm Dm An gt Dm F2 C0 An lt lt 2 Dm ADD An Am Am An gt Am F2 40 An lt lt 2 Am ADD imm8 Dn Dn imm8Dn D44Dn imm8 ADD imm16 Dn Dn imm16Dn F7 18 Dn imm16 l imm16 h ADD imm24 Dn Dn imm24 Dn F4 60 Dn imm24 l imm24 m imm24 h ADD imm8 An An imm8An DO An imm8s ADD imm16 An An imm16 4An F7 08 An imm16 l imm16 h ADD imm24 An An imm24 An F4 64 An imm24 l imm24 m imm24 h ADDC Dn Dm Dm Dn CF gt Dm F2 80 Dn lt lt 2 Dm ADDNF imm8 An An imm8An F5 0C An imm8 11 SUB Dn Dm Dm Dn 5Dm A0 Dn lt lt 2 Dm SUB Dm An An Dm An F2 10 Dm lt lt 2 An SUB An Dm Dm An Dm F2 D0 An lt lt 2 Dm SU
377. d8 An Dm mem24 An d8 F5 50 An lt lt 2 Dm d8 MOVX Dm d16 An Dm mem24 An d16 F7 60 An lt lt 2 Dm d16 l d16 h MOVX Dm d24 An 24 24 F4 30 An lt lt 2 Dm d24 d24 m d24 h Notes 1 Itis not possible to specify that Dn Dm 538 MOVB An Dm 8 gt 30 An lt lt 2 Dm B8 Dn 4 d8 An Dm mem8 An d8 Dm F5 20 An lt lt 2 Dm d8 d16 An Dm 8 16 gt F7 D0 An lt lt 2 Dm d16 I d16 h F4 A0 An lt lt 2 Dm d24 d24 m d24 h MOVB Di An D mem8 An Di Dm F0 40 Di lt lt 4 An lt lt 2 Dm MOVB 424 0 abs16 Dn 8 924 gt mem8 abs16 Dn CC Dn abs16 l abs16 h B8 Dn 75 abs24 Dn mem8 abs24 Dn F4 C4 Dn abs24 l abs24 m abs24 h MOVB Dm An Dm mems An 10 Dm lt lt 2 An MOVB 48 Dm mem8 An d8 F5 10 An lt lt 2 Dm d8 MOVB Dm d16 An Dm mem8 An d16 F7 90 An lt lt 2 Dm d16 l d16 h MOVB Dm d24 An F4 20 An lt lt 2 Dm d24 d24 m d24 h MOVB Di An Dm mems An d24 Dm mem8 An Di O IN IN O N N GO IN N JN IN QI N IN IN N N N N IN
378. de control register because the low speed oscillation clock operates stably In this case the CPU does not need to go through IDLE mode The following is the program example of switching from NORMAL mode to SLOW mode Program 3 Oxfc00 al al dO Read CPUM register 0 3 dO Set SLOW mode do al Chapter 10 Low power Modes MN102H55D 55G F55G 289 Chapter 10 Low power Modes The CPU operates based on low speed oscillation clock in IDLE mode 1 The oscillation stabilization wait time is required to stabilize oscil lation The program needs to count the same time as the os cillation stabilization time 290 MN102H55D 55G F55G Transferring from SLOW mode to NORMAL mode When the CPU transits from SLOW mode to NORMAL mode the CPU needs to wait in IDLE mode with the program until the high speed oscillation clock starts oscillation and becomes stable It takes at least 3 9 ms when the CPU switches from SLOW mode to NORMAL mode at 34 MHz operation The following is the program example of switching from SLOW mode to NORMAL mode Program 4 Oxfc00 al al dO Read CPUM register Oxfffd Set IDLE mode 40 al Program 5 This is the loop of waiting for 3 9 ms LOOP in 32 kHz clock operation to switch from 32 kHz clock operation to 34 MHz clock operation Oxfc00 al Not required when the program continues from program 4 al dO Read CPUM register Oxff
379. defined Undefined Undefined Undefined Undefined 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 AN7 AN7 AN7 AN7 AN7 AN7 AN7 AN7 AN7 ANT BUF9 BUF8 BUF7 BUF6 5 BUF4 BUF3 BUF2 BUF1 BUFO R R R R R R R R R R R R R R R R 0 0 0 0 0 O Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Chapter 11 Appendix A AN6BUF x OOFF14 AN6 Conversion Data Buffer 16 bit access register AN6 conversion data When 8 bit is selected as A D converter resolution the AN6BUF 7 0 bits hold the data and the 6 9 8 bits be come 0 When 10 bit is se lected as A D converter resolu tion the AN6BUF 9 0 bits hold the data AN7BUF x OOFF16 AN7 Conversion Data Buffer 16 bit access register AN7 conversion data When 8 bit is selected as A D converter resolution the AN7BUF 7 0 bits hold the data and the AN7BUFT 9 8 bits be come 0 When 10 bit is se lected as A D converter resolu tion the AN7BUFT 9 0 bits hold the data MN102H55D 55G F55G 473 Chapter 11 Appendix DAO ON R W gt gt S S 0 1 DAO Conversion Start 0 Disable 1 Enable DAO BUF7 DAO
380. e Simplex Connection Full Duplex Connection Figure 5 1 3 Asynchronous Mode Connections PC Mode The serial interface can connect to slave transmitters or slave receivers i The SDA and SCL pins connect a pullup resistor externally or an internal pullup resistor by setting the register SDA SCL Master Transmit Slave Slave Receive Transmit Transmit Receive Receive 194 MN102H55D 55G F55G Figure 5 1 4 Mode Connection Chapter 5 Serial Interface Table 5 1 3 Baud Rate Setting Example in Asynchronous Mode whet BOSC 209 MHz Unused Unused Unused Unused Unused 2 Unused 4 Unused Unused Unused BOSC Hz Transmission reception is pos Baud Rate sible within 2 of baud rate 16x Timer Divisor errors Asynchronous Serial Timing Charts 8 bit charater length no parity two stop bits Transmission SBO ST b0 b1 b2 b3 b4 b5 be 67 8 8 Data write TXBUSY Transmission end interrupt Figure 5 1 5 Asynchronous Serial Timing Transmission Reception SBI ST b0 b1 62 63 64 65 b6 67 SP SP RXBUSY Reception end interrupt i High when data is received Data read Figure 5 1 6 Asynchronous Serial Timing Reception MN102H55D 55G F55G 195
381. e Ty tt ett ke Address sss s C Address omm 2 Address tapi Figure 11 1 10 Data Transfer Signal Timing Address Data Shared With Wait 1 5 or More ALE late long mode AD long mode Read 334 MN102H55D 55G F55G BOSC ALE Late 0 long 0 mode ALE Late 0 long 0 5 mode ALE Late 0 long 1 mode ALE Late 0 long 1 5 mode ALE Late 0 5 long 1 5 mode ALE tcvc tcvc icvc Chapter 11 Appendix 2 W 1 W the number of waits 1 5 2 2 5 7 tcYcxN tcyc La taLEF1 taLEF1 tALEF1 a TALER1 Late 1 long 1 5 mode ALE ALER1 Late 1 5 long 1 5 mode 8 bit Bus Mode AD15 AD8 AD long 1 mode AD7 ADO AD long 1 mode AD15 AD8 AD long 1 5 mode AD7 ADO AD long 1 5 mode AD15 AD8 AD long 2 mode AD7 ADO AD long 2 mode AD15 AD8 AD long 3 mode AD7 ADO AD long 3 mode 16 bit Bus Mode AD15 ADO AD long 1 mode AD15 ADO AD long 1 5 mode AD15 ADO AD long 2 mode AD15 ADO AD long 3 mode Address ALER1 tALEF1 A NS Address Data Address Address Data Address Address Address Address Address NS Data Data Data Data Address a tan
382. e Channels Single Conversion Timing 215 Single Channel Continuous Conversion Timing 216 Multiple Channels Continuous Conversion Timing 217 A D Converter Block Diagram 218 Analog Voltage Input Example 222 Single Channel A D Conversion Block Diagram 222 Single Channel A D Conversion Timing 223 3 channel A D Conversion Configuration 224 3 channel A D Conversion Block Diagram 224 3 channel A D Conversion Timing 226 D A Converter Configuration 2 227 Analog Voltage Output Example 229 D A Conversion Block Diagram Using DAO Channel 229 Bus Acquisition Timing eee 232 ATC Serial Reception Block Diagram 237 Serial Reception Sequence 237 ETC Bus Acquisition Timing 241 ETC External Memory External Device Transfer Block Diagram 247 ETC External Memory External Device Transfer Connection 247 ETC External Memory External Device Burst Transfer Timing 250 ETC External Device Externa
383. e PWM output of the pin changes to high The PWM output starts low at first The pin duty is 1 2 while the pin duty is 2 1 Since the TM13BC counter is down counting set the TM13CA regis ter and the TM13CB register to 5 and 2 respectively TM13CA x 00FEOA 7 6 5 4 3 2 1 0 TMI3 TMI3 TMI3 TMI3 TMI3 TMI3 TMI3 TMI13 CAT CA6 CAS CA4 CA2 CAI CAO 0 0 0 0 0 1 0 1 7 6 5 3 2 1 0 CB7 6 5 4 CB3 CB2 0 0 0 0 1 0 6 Load TMOBR value to the timer 13 binary counter TM13BC At same time select timer 0 underflow as the clock source Set the PWM waveform polarity which is output from pin and pin to the positive logic When setting the polarity to the negative logic an error of inverting high and low oc curs To clear TM13BC counter or RS F F for TM13OA pin output and pin output set the TMI3CLR flag to 1 TM13MD x 00FE28 7 6 5 4 3 2 1 0 LD CLR 0 1 1 0 0 1 7 Set pin Since TM130A and pin func tion as P50 and P51 respectively set the port 5 mode register L PSLMD to P
384. e burst ROM area and other areas consecutively Chapter 2 Bus Interface The MEMMD2 register sets the cycles during burst ROM mode and the fixed wait cycles during handshake mode MEMMD2 x 00FF84 15 14 13 12 11 10 9 8 z 6 5 4 3 2 1 0 81 50 _ BsT2 BST1 BSTO ved ved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BST 2 0 Cycle Setting for Burst ROM Shortening First Cycle Setting at Burst Access 000 0 5 cycle 001 1 0 cycle 010 1 5 cycles 011 2 0 cycles 100 2 5 cycles 101 3 0 cycles 110 3 5 cycles 111 4 0 cycles Reserved Setto 0 HS 2 0 Fixed Wait Setting When Controlling Wait Cycles in WAIT Pin Handshake Mode 000 No wait 001 0 5 wait cycle 010 1 wait cycle 011 1 5 wait cycles 100 2 wait cycles 101 2 5 wait cycles 110 3 wait cycles 111 3 5 wait cycles MN102HF55G H55G H55D 55 Chapter 2 Bus Interface The DRAMMDI register sets the external memory DRAM operation the timing of RAS and CAS and the size of address shift DRAMMD1 x 0OFF90 15 14 43 14211 109 87 65 4 0 2 1 1 0 SEL2 SEL1 SEL0 CAS2 CAS1 CASO RAS2 RAS1 RASO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAS 2 0 Timing Setting of the RAS s Fa
385. e data to the serial 3 transmit receive buffer SC3TRB This allows the data to output The SDA3 pin output changes with a 1 8 cycle delay of the falling edge of the SCL3 pin output 5 After transmission ends SDA3 pin output and SCL3 pin output stay low MN102H55D 55G F55G 207 Chapter 5 Serial Interface Verify that transmission ends by an interrupt either a serial 3 transmission end interrupt or a serial 3 reception end interrupt or polling the received data flag of the serial 3 status register Polling the reception busy flag is not allowed during mode 6 Read the dummy data of the serial 3 transmit receive buffer SC3TRB after trans mission ends 7 Verify that a parity error occurs by reading the serial 3 status register SC3STR When a parity error occurs this means the slave responds normally When a parity error does not occur this means the slave does not respond This step is unnecessary for the system without ACK Data Transmission 2 8 Repeat steps 4 to 7 if the data is transmitted continuously Stop Sequence 9 Write 0 to the 5 3 flag of the SC3CTR register to end the data transmission Do not write during transmission 10 Set the SCL3 pin output to high as soon as the SC3IIC flag is written One cycle later set the SDA3 pin output to high to start the stop sequence transmission The SC3ISP flag of the SC3STR register becomes 1 Reception must be enabled to detect the sto
386. e of the TMOBR value 1 When BOSC is selected as the clock source the valid range for TMOBR is 1 to 255 Otherwise the valid range for TMOBR is 0 to 255 7 6 5 4 3 2 1 0 T M 1 B R TM TMI TMI BR7 6 BRS BR4 BR3 BR2 BRI BRO x 0 0 F E 1 1 R W R W R W R W R W Timer 1 Base Register 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 bit access register 16 bit access is possible from even address sets the timer 1 count ing cycle TM1BR sets the counting cycle 1to 256 The timer 1 binary counter counts the cycle of the value 1 The valid range for TM1BR is 0 to 255 MN102H55D 55G F55G 437 Chapter 11 Appendix 7 6 5 4 3 2 1 0 TM2 TM2 TM2 TM2 TM2 TM2 TM2 TM2 BR7 BR6 BRS BR4 BR3 BR2 BRI BRO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 TM3 TM3 TM3 TM3 TM3 TM3 TM3 TM3 BR7 BR6 BRS BR4 BR3 BR2 BRI BRO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 438 MN102H55D 55G F55G TM2BR 00 12 Timer 2 Base Register 8 bit access register TM2BR sets the timer 2 count ing cycle
387. e register TM8CA to TM8CAX when TM8CAX TMSBC To read the TMSCA value into TM8CAX write the dummy data to TM8CAX MN102H55D 55G F55G 147 Chapter 4 Timers 1 If this setting is omitted the bi nary counter may not count the first cycle Do not change to any other operating modes 148 MN102H55D 55G F55G 5 Write the dummy data to the timer 8 compare capture register BX TM8CAX to set the initial value in the TM8CBX register The value cannot be written in the 8 by software In the double buffer mode read the timer 8 compare capture register B TM8CB to TM8CBX when TM8CBX TMSBC To read the TMSCB value into TM8CBX write the dummy data to TM8CBX 6 Set TM8NLD and TM8EN of TM8MD to 1 and 0 respectively This enables TM8BC and RS F F 7 Set TM8NLD and TM8EN to 1 This starts the timer Counting begins at the start of the next cycle Timer 8 outputs a one phase PWM at any duty Select up counting Do not use timer 8 when BOSC stops in STOP mode external inputs are sampled on BOSC synchronized with BOSC when the external clock operates Set the cycle 0 to x FFFE to the TM8CA register and the phase difference to the TMSCB register When TM8BC 8 generate a B8 pulse signal and invert T F F for TM8IOB pin output at the start of the next cycle When TM8BC TM8CA generate an 8 pulse signal invert T F F for TM8IOA pin output and reset TM8BC at the start of the next cycle
388. ead bits 15 8 of the LBSWL register and bits 15 8 read bits LBSWH LBSWL Write 7 0 of the LBSWL register xo0FFCE xOOFFCD xOOFFCC 15 8 7 0 15 8 7 0 LBSWL i LBSWH Read MN102H55D 55G F55G 485 Chapter 11 Appendix PLU7 PLU6 PLUS PLU4 PLU3 PLU2 PLU1 PLUO R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 PortO Pullup Resistor 0 Off 1 On PLU7 PLU6 PLUS PLU4 PLU3 PLU2 PLU1 PLUO R W R W R W R W R W R W RW R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 70 Port 1 Pullup Resistor 0 Off 1 On 2 2 2 2 2 2 2 2 PLU7 PLU6 PLUS PLU4 PLU3 PLU2 PLU1 PLUO R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port 2 Pullup Resistor 0 Off 1 On P3 P3 P3 P3 PLU7 PLU6 PLUS PLU4 PLU3 PLU2 PLU1 PLUO R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port3 Pullup Resistor 0 Off 1 On 486 MN102H55D 55G F55G POPLU x OOFFBO Port 0 Pullup Control Register 8 bit access register P
389. eceive Buffer 8 bit access register 7 0 Serial Transmit Receive D ansmit Receive Data SC4TRB writes the serial 4 transmit data and reads the se rial 4 receive data Transmission starts by writing the data into this register The data is received by reading this register In 7 bit transfer the MSB bit 7 becomes 0 The data is read when an interrupt occurs or the SC4RXA flag of the SC4STR register is 1 MN102H55D 55G F55G 429 Chapter 11 Appendix 430 MN102H55D 55G F55G 7 6 5 4 3 2 1 0 sc4 SC4 SC4 SC4 SC4 4 8 4 4 TBY RBY ISP RXA IST FE PE OE R R R R R R R R 0 0 0 0 0 0 0 0 7 Transmission Busy Flag 6 Reception Busy Flag 5 Stop Sequence Detect 4 Received Data 3 Start Sequence Detect 2 Framing Error 1 Parity Error 0 Overrun Error Ready to transmit Transmission in progress Ready to receive Reception in progress Undetected 1 Detected No received data Received data Undetected Detected No error 1 Error No error Error No error Error SCASTR x 00FDA3 Serial 4 Status Register 8 bit access register 16 bit access is possible from even address SC4STR reads the status for se rial interface 4 This bit is cleared by the read or write operation of the SC4TRB register Set 1 to the SC4REN bit This bit is
390. eck with the bit test instruction BTST 18 Write x 70 to the register bit setting 01110000 set 0 only in P37 19 The bit corresponding to the port 3 input register P3IN becomes 0 if any one of keys 3 7 B F Check with the bit test instruction BTST The following figure shows the timing of the key input interrupt Chapter 3 Interrupts STOP mode Low level 4 KIIE CPUM Normal mode STOP mode Oscillation Normal mode stability wait Interrupt Servicing Figure 3 2 5 Key Input Interrupt Timing MN102H55D 55G F55G 99 Chapter 3 Interrupts The watchdog interrupt is used to detect the CPU errors The CPU cannot return to the previ ous operation before the watch dog interrupt occurred after in terrupt service routine is ex ecuted Therefore the CPU must reset after the watchdog interrupt occurred If WDM1 WDMO are 00 a watchdog interrupt occurs when the watchdog timer counts 217 BOSC cycles 4 369 ms with a 30 MHz oscillator The following is the WDM set ting 00 27 BOSC cycles 01 25 BOSC cycles 10 219 BOSC cycles 11 215 BOSC cycles Normally clear the watchdog timer before an interrupt occurs 100 MN102H55D 55G F55G 3 2 3 Watchdog Timer Interrupt Setup Examples An interrupt occurs by using the watchdog timer The watchdog timer starts by setting the WDRST flag of the
391. ed setting each port mode register determines the input output direction automati cally When the general purpose input output port is selected each port direction control register controls the input output direction Each port has a pull up resistor which is controlled by software and switches ON OFF regardless of each port mode register and the direction control reg ister setup Table 8 1 2 Port Block Diagram 1 12 Port Pin Name Block Diagram Port 0 P07 to POO 207 to DOO A07 to A00 POPLU 7 0 gt Register gt x POOUT 7 0 Register Address Data Output A07 A00 007 000 POMD 1 0 4 07 P00 PODIR 7 0 lt Register Selector Address Data Input Output Control POIN 7 0 Port Input 7 Data Input 4 007 000 Note set value of the PODIR register is valid only when the port function is selected by the POMD register 264 MN102H55D 55G F55G Table 8 1 2 Port Block Diagram 2 12 Chapter 8 Ports Port Pin Name Block Diagram Port 1 P17 to 015 to D08 15 to A08 P1PLU 7 0 lt gt Register y TMSIOB 1 P1OUT 7 0 gt Register gt Address Data Output eni 5 TM11IC D15 008 Selector Output P10 TM111OA
392. ed as a data input output pin or an address data input output pin in single chip mode processor mode or memory expan sion mode Refer to Chapter 4 Timers 99 D14 VO Data I O Refer to Pin 93 D8 AD8 Description for details AD14 yo Address Data I O P16 General purpose Port 16 Refer to Pins 84 91 00 07 Description for details TM121OB Timer 12B Input Output This pin can be used as a timer 12 input capture B input pin or a timer 12 output compare output pin if it is not used as a data input output pin or an address data input output pin in single chip mode processor mode or memory expansion mode Refer to Chapter 4 Timers 100 D15 VO Data I O Refer to Pin 93 D8 AD8 Description for details AD15 yo Address Data I O P17 yo General purpose Port 17 Refer to Pins 84 91 00 07 Description for details TM12IC Input Timer 12C Input This pin can be used as a timer 12 counter clear pin if it is not used as a data input output pin or an address data in put output pin in single chip mode processor mode or memory expansion mode Refer to Chapter 4 Timers MN102H55D 55G F55G 37 Chapter 1 General Description Table 1 4 1 List of Pin Functions 17 26 Pin Number Pin Name yo Function Description 67 RAS P70 SBTO Output y o y o DRAM Control Output General purpose Port 70 Serial Interface 0 Clock Input Output This pin outputs RAS signal when connecting
393. ed watchdog timer is continuously cleared while the WDCLR flag is 1 Normally clear the watchdog timer and the extended watchdog timer before a watchdog interrupt occurs Chapter 3 Interrupts If WDM1 WDMO are 00 a watchdog interrupt occurs when the watchdog timer counts 217 BOSC cycles 4 369 ms with a 30 MHz oscillator The following is the WDM set ting 00 217 BOSC cycles 01 25 BOSC cycles 10 213 BOSC cycles 11 215 BOSC cycles MN102H55D 55G F55G 103 Chapter 3 Interrupts 104 MN102H55D 55G F55G Chapter 4 Timers Chapter 4 Timers 106 MN102H55D 55G F55G 4 1 Summary of 8 bit Timer Functions 4 1 1 Overview The MN102H55D 55G F55G contains eight 8 bit down counters that can serve as interval timers event counters clock outputs underflow divided by 2 base clocks for serial interface or start timing for A D conversion The internal clocks oscillation frequency BOSC 2 low speed frequency XI 4 or the external clocks less than BOSC 4 can be selected as clock sources Interrupts are generated when timers underflow Up to eight 8 bit timers can cascade For example cascading timers 4 and 5 forms a 16 bit timer while cascading timers 0 1 2 3 forms a 32 bit timer When cascading timers the clock source of the lowest cascaded timer should be selected as the clock source Timers 0 and 4 function as prescalars They can supply to timers 1 to 3 and timers 5 to 7 as clock sources This allows l
394. efined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 470 MN102H55D 55G F55G ANOBUF x OOFFO8 ANO Conversion Data Buffer 16 bit access register ANO conversion data When 8 bit is selected as A D converter resolution the ANOBUF 7 0 bits hold the data and the ANOBUF 9 8 bits be come 0 When 10 bit is se lected as A D converter resolu tion the ANOBUF 9 0 bits hold the data AN1BUF x OOFFOA AN1 Conversion Data Buffer 16 bit access register AN1 conversion data When 8 bit is selected as A D converter resolution the AN1BUF 7 0 bits hold the data and the AN1BUFT 9 8 bits be come 0 When 10 bit is se lected as A D converter resolu tion the AN1BUFT 9 0 bits hold the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AN2 AN2 AN2 AN2 AN2 AN2 AN2 AN2 AN2 AN2 BUF9 BUF8 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUFI BUFO R R R R R R R R R R R R R R R R 0 0 0 0 0 O Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AN3 AN3 AN3 AN3 AN3 AN3 AN3 AN3 AN3 AN3 BUF9 BUF8 BUF7 BUF6 5 BUF4 BUF3 BUF2 BUF1 BUFO R R R R R R R R R
395. eginning of 4 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Others les interrupt is generated Reserved Set to 0 RON DRAM Refresh Enable 0 Disable 1 Enable DRAM is refreshed once when the timer 10 12 underflow At 256 times 8 ms the refresh interval is 31 25 us or less DRAMTM Clock Source Selection for DRAM Refresh 0 Timer 12 underflow 1 Timer 10 underflow DRAMACC DRAM Access Method Selection 0 2WE method 1 Reserved MN102HF55G H55G H55D 57 Chapter 2 Bus Interface The REEDGE register sets the RE waveform control modes for the external memory spaces 0 to 3 REEDGE x 00FF86 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REESREES REEL REELREES REESIREEL REEL REESRREES REEL REEL REESIREES REEL REEL 31 30 31 30 21 20 21 20 11 10 11 10 01 00 01 00 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 REEL 01 00 RE Late Mode CS0 Area RE late 0 5 mode at reset RE late 1 mode RE late 2 mode RE late 3 mode REES 01 00 RE Short Mode in CSO Area RE short 0 mode RE short 0 5 mode at reset RE short 1 mode RE short 1 5 mode REEL 11 10 RE Late Mode in CS1 Area RE late 0 5 mode at reset RE late 1 mode RE late 2 mode RE late 3 mode REES 11 10 RE Short Mode CS1 Area RE short 0 mode at reset RE short
396. egister TM3BR Load gt Reload 8 FE03 Timer 3 binary counter TM3BC com Underflow H BOSC 2 gt Timer 0 underflow gt Timer 2 cascade Timer 4 underflow gt Mutliplex Figure 4 1 8 Timer 3 Block Diagram Timer 3 underflow interrupt A D activation MN102H55D 55G F55G 113 Chapter 4 Timers Data bus FE14 Timer 4 base register TM4BR Load Reload FE04 TM4BC Timer 4 binary counter Timer 4 underflow interrupt gom BOSC 2 gt Timer 0 underflow gt Timer cascade gt gt Underflow Y 16 bit timer Serial 2 3 P83 Multiplex Reset gt 1 2 Timer output underflow 2 generator circuit Set output by PBMMD Figure 4 1 9 Timer 4 Block Diagram gt TM4O pin P83 gt limer 5 underflow interrupt L Data bus 8 18 8 FE15 Timer 5 base register TM5BR Load Reload 8 FEO5 Timer 5 binary counter TM5BC Underflow Count L BOSC 2 Timer 0 underflow gt Timer 4 cascade BOSC Multiplex 114 MN102H55D 55G F55G Figure 4 1 10
397. egisters DAnCTR and the D A conversion data buffers DAnBUF corre sponding to and pins DAnCTR 7 6 5 4 3 2 1 0 DAO ON Reset 0 0 0 0 0 0 0 0 D A Conversion Start 0 Disable 1 Enable DAnBUF 7 6 5 4 3 2 1 0 BUF7 BUF6 BUF5 BUF3 BUF2 BUF1 BUFO 0 0 0 0 0 0 0 0 The DAnBUF register stores 8 bit D A conversion data Reset Table 6 3 2 List of D A Converter Control Registers Register Address R W Function D AO DAOCTR 00 40 R W D A 0 Converter Control Register DAOBUF 41 R W D A 0 Conversion Data Buffer D AI DAICTR 00 42 R W D A 1 Converter Control Register DAIBUF 43 R W D A 1 Conversion Data Buffer The D A converter control registers DAnCTR set the D A conversion operating con ditions The D A conversion data buffers DAnBUF input and store the conversion data for channels 1 and 0 DACI and pins 228 MN102H55D 55G F55G Chapter 6 Analog Interface 6 4 D A Converter Setup Examples 6 4 1 D A Conversion Using DAO Channel This section describes D A conversion circuit operation The D A con verter setup procedure is the same for DAO channel and DAI channel The conversion data is set in the D A conversion data buffer and the pin P80 outputs the analog voltage 1 LSB data set in the D A conversion data buffer corresponds to the difference
398. ement in crement by 1 in the byte transfer and by 2 in the word transfer ETO ETO ETO SRC23SRC22SRC2ISRC2OSRCIO9SRCISSRCIT7SRCI R W R W R W R W R W R W R W R W undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 This register writes only 24 bit data or 16 bit data Use the MOV instruction or the MOVX instruction to set the data MN102H55D 55G F55G 411 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETO ETO ETO ETO ETO ETO ETO ETO ETO ETO ETO ETO IDSTISDSTIADSTI3DSTI2DSTI I DSTIO 0579 DST8 DST7 DST6 0575 DST4 DST3 DST2 DSTI DSTO R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W undefined undefined undefined Jundefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETO ETO ETO ETO
399. eneral purpose Port 55 BREQ and BRACK pins operate bus arbitration Refer to Pin 9 BREQ Description for details This pin can be used as a general purpose input output port in single chip mode The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports P61 Output Read Enable Output General purpose Port 61 This pin provides a control signal for the external memory read in processor mode or memory expansion mode When connecting SRAM and ROM connect RE to OE in memory RE outputs low level during read operation and the chip reads the contents of the memory Refer to 2 1 Summary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state Refer to 11 2 3 List of Pin Functions This pin can be used as a general purpose input output port if it is not used as RE in single chip mode processor mode or memory expansion mode The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports 26 MN102H55D 55G F55G Chapter 1 General Description Table 1 4 1 List of Pin Functions 6 26 Pin Number Pin Name Function Description WEL P62 Output Lower Byte Write Enable Output General purpose Port 62 This pin provides a control signal for the exter
400. er 7 0 Port 8 Output 0 Output low 4 Output high P8OUT sets the data output to the port 8 7 6 5 4 3 2 1 0 P9OUT P9 9 P9 P9 P9 P9 P9 P9 3 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUTI OUTO x OOFFC9 R W R W R W R W R W R W R W R W Port 9 Output 0 0 0 0 0 0 0 0 Reaister egiste 8 bit access register 7 0 9 Output 0 Output low 1 Output high P9OUT sets the data output to the port 9 7 6 5 4 3 2 1 0 PAOUT PA PA PA PA PA PA OUTS OUTA4 OUT3 OUT2 OUTI OUTO x OOFFCA R W R W R W R W R W R W Port A Output 0 0 0 0 0 0 0 0 Reaister 0 9 8 bit access register 5 0 Port A Output 0 Output low 1 Output high PAOUT sets the data output to the port A 7 6 3 4 3 2 1 0 U T E reserv reserv PB PB ed ed ed OUTI OUTO x 0 0 F FC B R R W R W R W R W R W Port B Output 0 0 0 0 0 0 0 0 Re ister 0 0 0 0 1 0 1 0 1 0 1 0 1 9 8 bit access register 4 2 Reserved Setto 0 PBOUT sets the data output to h B 10 Port B Output 0 Output low 1 Output high MN102H55D 55G F55G 491 Chapter 11 Appendix PO IN7 INO INS INA IN3 IN2 I
401. er TM7UICH x 00FC89 Timer 7 Underflow Interrupt Control Register TMSUICL 00 54 Timer 8 Underflow Interrupt Control Register TM8UICH 00 55 Timer 8 Underflow Interrupt Control Register TMS8AICL 00 56 Timer 8 Capture A Interrupt Control Register TM8AICH x 00FC57 Timer 8 Capture A Interrupt Control Register TM8BICL x 00FCSC Timer 8 Capture B Interrupt Control Register TM8BICH x O0FC5D Timer 8 Capture B Interrupt Control Register TM9UICL x O0FCSE Timer 9 Underflow Interrupt Control Register TM9UICH x O0FCSF Timer 9 Underflow Interrupt Control Register TM9AICL x 00FC64 Timer 9 Capture A Interrupt Control Register TM9AICH x 00FC65 Timer 9 Capture A Interrupt Control Register x 00FC66 Timer 9 Capture B Interrupt Control Register TM9BICH x 00FC67 Timer 9 Capture B Interrupt Control Register Chapter 3 Interrupts MN102H55D 55G F55G 91 Chapter 3 Interrupts 92 MN102H55D 55G F55G TMIOUICL x O0FC6C R W Timer 10 Underflow Interrupt Control Register TMIOUICH x 00FC6D Timer 10 Underflow Interrupt Control Register TMIOAICL x 00FC6E R W Timer 10 Capture A Interrupt Control Register TMI0AICH x 00FC6F R W Timer 10 Capture A Interrupt Control Register TMI0BICL x 00FC74 R W Timer 10 Capture B Interrupt Control Register TMI0BICH x 00FC75 R W Timer 10 Capture B Interrupt Control Register TMIIUICL 00 76 Timer 11 Underflow Interrupt Control Register TMIIUIC
402. er gt X P50UT 7 0 Register TMISIA 2 gt gt CS3 to CSO TM130A Output P50 gt CS0 Output P50 gt BREQ TM13OB Output P51 BRACK CS1 Output P51 gt enn TM140A Output P52 gt Selector BSTRE CS2 Output P52 gt ALE 14 Output P53 CS3 Output P53 gt ALE BRACK Output P55 BSTRE Output P56 E ALE ALE Output P56 gt SA SESO P5LMD 7 0 Register P5HMD 4 0 PSDIR 7 0 Register 83 CSO Input Output Control gt P53 P50 TM130A TM130B TM140A TM140B Selector Input Output Control P53 P50 ALE BSTRE Output Control P56 n BRACK BREQ Input Output Control y P55 P54 TM151A Input Control P56 5 7 0 4 i Port Input BREG Input P54 Input P56 To Port 2 Block Note The set value of the P5DIR register is valid only when the port function is selected by the P5LMD register or the PSHMD register The input or output direction of CS3 to CSO ALE ALE BREQ BRACK and timer output is determined automatically by setting the PSLMD register or the register MN102H55D 55G F55G 260 Chapter 8 Ports Table 8 1 2 Port Block Diagram 7 12 Port Pin Name Block Diagram Port 6
403. er of wait cycles 0 5 wait cycle to 7 wait cycles is set the BIBT1 clock cycle being high level is extended 1 BOSC clock cycle in each 0 5 wait cycle The necessary cycle for 1 access should be 3 BOSC clock cycles BOSC EN BIBT BIBT A oS CaS Figure 2 1 8 External Access 0 5 Wait Cycle Chapter 2 Bus Interface MN102HF55G H55G H55D 67 Chapter 2 Bus Interface Table 2 1 3 Address Data Multiplex Mode 16 bit Bus Data Access The length of wait cycle can be set in 0 5 cycle units No Wait 1 Wait BOSC a Base Clock 2 Pee ue BIBT1 A23 A16 23 16 X A23316 X 23 16 gt 23 16 X 23 16 X 23 16 16 bit Data Read AD15 AD0 150 15 00155 15 0 15 0 15 0 15 0 The CPU selects the necessary data BEE 1 h of H side or L side RE NS o a NN under 8 bit bus width WEH WEL ux X NE ND A23 A16 23 16 X A2336 X 23 16 A2836 X A23346 _ 23 16 AD15 ADO C A150 XA150D15 15 0 CABO XA520X 0150 X 16 bit Data Write ALE i RE WEH na uf ef e WEL m uni 5
404. erflow Timer 4 underflow TMSIB pin 1 2 of BOSC Two phase encoder of TMSIOA TMSIOB 4x Two phase encoder of TMSIOA TMSIOB 1x Timer 0 underflow Timer 4 underflow e TM9IOB pin 1 2 of BOSC Two phase encoder of TM9IOA TMOIOB 4 Two phase encoder of TM9IOA TMOIOB 1 Timer 0 underflow Timer 4 underflow TMIOIOB pin 1 2 of BOSC Two phase encoder TMIOIOA TMIOIOB 4x Two phase encoder of Timer 0 underflow Timer 4 underflow TMIIIOB pin 1 2 of BOSC Two phase encoder of TMIIIOA TMIIIOB 4x Two phase encoder of Timer 0 underflow Timer 4 underflow TMI2IOB pin 1 2 of BOSC Two phase encoder of TMI2IOA TMI2IOB 4x Two phase encoder of TMSIC pin TMIOIOB TMI2IOB 1 1 1 Cownt Up Down Up Down Up Down Up Down Up Down Direction P P P P P Interval Timer Event Counter One shot Puls ne shot Pulse 1 Capture Input d d 2 phase Capture Input 5 lt d 2 phase Encoder 4x v 4 4 2 phase Encoder 1x External Count Direction Control Switch edge polarity Switch edge polarity of Switch edge polarity of TMSIC pin input TMOIOB pin input TMIOIOB pin input Other
405. erial Programming 530 11 4 8 Onboard Serial Programming Mode Setup 532 11 4 9 Branch to User Program 534 11 4 10 Serial Interface for Onboard Serial Programming 535 11 4 11 PROM Writer Onboard Serial Programming 536 11 5 List of MN102H00 Series Linear Address High speed Edition Hem 538 List of Figures Figure 1 1 1 Figure 1 1 2 Figure 1 1 3 Figure 1 1 4 Figure 1 3 1 Figure 1 4 1 Figure 1 4 2 Figure 1 4 3 Figure 1 4 4 Figure 1 4 5 Figure 1 4 6 Figure 1 4 7 Figure 1 4 8 Figure 1 4 9 Figure 1 4 10 Figure 1 4 11 Figure 1 4 12 Figure 1 4 13 Figure 1 4 14 Figure 2 1 1 Figure 2 1 2 Figure 2 1 3 Figure 2 1 4 Figure 2 1 5 Processor Status Word PSW 5 Address Space Memory Expansion Mode 7 Interrupt Controller Configuration 8 Interrupt Servicing Sequence sss 8 Block Diagram cucine eterne 11 Pin Configuration in Single chip Mode 13 Pin Configuration in Memory Expansion Mode with 8 bit Bus Address Data Separate Mode 14 Pin Configuration in Memory Expansion Mode with 16 bit Bus Address Data Separate Mode 15 Pin Configuration in Memory Expansion Mode with 8 bit Bus Address Data Shared Mode
406. error data is updated whenever the parity bit is re ceived An overrun error occurs when the next data is received com pletely before the CPU reads the received data SC2TRB Over run error data is updated when ever the last data bit seventh or eighth bit is received Do not poll the SC2RBY flag to verify the reception end in clock synchronous mode Generate a serial 2 reception end interrupt or poll the SC2RXA flag to verify the reception end 15 SC3 SC3 SC3 SC3 583 SC3 SC3 SC3 SC3 3 8 3 SC3 SC3 SC3 TEN REN BRE PTL OD ICM LN PTY2 PTYI PTYO SB 51 50 R W R W R W R W R W R R W R W R W R W R W R W R W R R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 on on o 15 Transmit Enable 0 Disable 1 Enable 14 Receive Enable 0 Disable 1 Enable 13 Break Transmission 0 Don t break 1 Break 12 PC Start or Stop Sequence 0 Stop sequence output when changing this bit from 1 to 0 1 Start sequence output when changing this bit from 0 to 1 11 Protocol Selection 0 Asynchronous mode 1 Clock synchronous mode mode 9 Bit Order Selection 0 LSB first 1 MSB first Select only when the character length is 8 bit 8 mode Selection 0 mode off 1 mode on 7 Character Length 0 7 bit 1 8 bit
407. errupt requested timer 8 interrupt Timer 8 Underflow Interrupt 0 No interrupt detected This register allows only byte Detect Flag 1 Interrupt detected accesses Use MOVB instruc tion to set the data ee TMB8UICH 5 2 TM8U IE 00 55 R Timer 8 Underflow 1 Interrupt Control Register 8 bit access register Timer 8 Underflow Interrupt 0 Disable Enable Flag j Enable TM8UICH enables a timer 8 in terrupt This register allows only byte accesses Use MOVB instruc tion to set the data The inter rupt level is the same level set in the IQOLV 2 0 bits of the IQOICH register MN102H55D 55G F55G 347 Chapter 11 Appendix 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected 7 6 5 4 3 2 1 0 8 TM8A IR ID R R R R W R R R R 0 0 0 0 0 0 0 0 0 1 0 0 0 1 4 Timer 8 Capture A Interrupt Request Flag 0 Timer 8 Capture A Interrupt Detect Flag 7 6 5 4 3 2 1 0 2 2 TM8A IE R R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 8 Capture A Interrupt Enable Flag 348 MN102H55D 55G F55G 0 Disable 1 Enable x 00FC56 Timer 8 Capture A Interrupt Control Register 8 bit access register requests and verifies a timer 8 capture A interrupt This
408. errupts After the program branches to x 080008 the program gener ates the interrupt service routine start address and then branches to that address During the interrupt service rou tine other interrupts are not ac cepted because IM of PSW be comes the highest level MN102H55D 55G F55G 101 Chapter 3 Interrupts The following is the WDP 2 0 setting 102 000 1 001 22 010 24 011 25 100 28 101 210 110 212 MN102H55D 55G F55G 3 2 4 Extended Watchdog Timer Setup Examples The MN102H55D 55G F55G has the extended watchdog timer which generates a longer watchdog interrupt than the normal watchdog timer does In addition the CPU resets itself instead of generating an inter rupt In this example if the CPU does not clear the watchdog timer and the extended watchdog timer for 4 47 s with 30 MHz external oscilla tor the CPU judges error operation and resets The CPU operation when the chip resets using the watchdog timer is the same as the CPU operation when low level is input to RST pin Generate a pulse signal of 2 BOSC cycles using the CPUM register and then set 2 using the WDREG register Since BOSC cycle at 30 MHz external oscillator is approximately 33 3 ns 33 3nsx2 x2 4 47 s and the watchdog timer the extended watchdog timer should be cleared during this interval 1 D A Conver
409. es e Programmable Hi Z Undefined i Z Programmable Hi Z Undefined i Z H Yes Programmable i Z Undefined i Z Hi Z al Hi Z al A06 i Z at A06 A07 i Z at A07 A08 Hi Z at A08 Hi Z at A09 Hi Z at A09 3 P32 A10 TTL 2 33 P33 A11 TTL 34 AVDD L CMOS CMOS CMOS i H H H H Yes Programmable Hi Z Undefined i Z Yes Programmable Hi Z Undefined i Z H Hi Z at Hi Z at A10 Yes Programmable i Z Undefined i Z Hi Z at A11 Hi Z at A11 Yes Programmab 2 Undefined i Z Hi Z at A12 Hi Z at A12 35 P34 A12 TTI 36 P35 A13 TTL 37 P36 A14 TTL 38 P37 A15 TTL CMOS CMOS CMOS CMOS Yes Yes Yes Programmab e e H Hi Z Undefined H Hi Z Hi Z at A13 Hi Z at A13 H 14 H Hi Z at A15 Hi Z Hi Z al A15 A16 Hi Z at A16 39 P40 A16 TTL 40 P41 A17 TTL 41 P42 A18 TTL 42 P43 A19 TTL 43 Vref CMOS CMOS CMOS Yes Yes Hi Z at A17 Hi Z at A17 Yes Programmable i Z Undefined Undefined Hi Z al i Z at A18 e Programmable Hi Z Undefined Undefined H H CMOS CMOS CMOS CMOS Yes Programmable i Z Undefined Undefined Hi Z al i Z at A19 No Programmable Hi Z Undefined Undefined Hi Z al i Z at No No Programmab 2 18 19 H 21 22 23 Hi Z Hi Z Hi Z i Z 44 P44 A20 AN4 Analog CMOS 45 P45 A21 AN5 Analog CMOS 47 P47 A23 WDOUT AN7 Analog CMOS 48 P80 DACO
410. ess register Timer 8 Interrupt 0 No interrupt requested TM8BICL requests and verifies Request Flag 1 Interrupt requested a timer 8 capture B interrupt Timer 8 Capture B Interrupt 0 No interrupt detected This register allows only byte Detect Flag 1 Interrupt detected accesses Use MOVB instruc tion to set the data TM8BICH 5 2 TM8B x OOFC5D i E gt Timer 8 Capture B 1 Interrupt Control Register 8 bit access register Timer 8 Capture B Interrupt 0 Disable Enable Flag 1 Enable TM8BICH enables a timer 8 capture B interrupt This register allows only byte accesses Use MOVB instruc tion to set the data The inter level is the same level set in the IQ1LV 2 0 bits of the IQ1ICH register MN102H55D 55G F55G 351 Chapter 11 Appendix 7 6 5 4 3 2 1 0 TM9U TM9U IR ID R R R R W R R R R 0 0 0 0 0 0 0 on o 0 1 4 Timer 9 Underflow Interrupt Request Flag 0 Timer 9 Underflow Interrupt Detect Flag 7 6 5 4 3 2 1 0 2 s TM9U IE R R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 9 Underflow Interrupt Enable Flag 352 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt dete
411. et the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATnSRC 15 SRC14 SRCI3 SRC12 SRC11 SRC10 SRC9 SRC8 SRC7 SRC6 SRC5 SRC4 SRC3 SRC2 SRCI SRCO n Reset undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATn ATn ATn ATn ATn ATn ATn ATn I B 7 i 7 7 SRC23 SRC22 SRC21 SRC20 SRCI9 SRC18 SRCI7 SRC16 Reset 0 0 0 0 0 0 0 O undefined undefined undefined undefined undefined undefined undefined undefined a The ATnSRC register and the ATnDST register write only 24 bit data or 16 bit data Use the MOV instruction or the MOVX instruction to set the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATnDST DSTIS5 DST14 DSTI3 DSTI2 DST11 DST10 DST9 DST8 DST7 DST6 DST5 DST4 DST3 DST2 DSTI DSTO Reset undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 22 _ _ ATn ATn ATn ATn ATn ATn ATn ATn DST23 DST22 DST21 DST20 DST19 DST18 DSTI7 DSTIG Reset 0 0 0 0 0 0 0 O undefined undefined undefined undefined undefined undefined undefined undefined MN102H55D 55G F5
412. ever timer 0 underflows IQOICH x 00FC50 7 6 5 4 3 2 1 0 100 100 100 100 LV2 LV1 LVO IE T 0 0 0 TMOICL x 00FC52 z _ TMO 2 _ TMO IR ID 0 0 4 Set the timer 0 divisor Since timer 0 divides TMOIO pin by 4 set the timer 0 base register TMOBR to 3 The valid range for TMOBR is 0 to 255 TMOBR 00 10 7 6 5 4 3 2 1 0 TMO TMO TMO TMO TMO TMO TMO BR7 BR6 BRS 4 BR3 BR2 BRO 0 0 0 0 0 0 1 1 5 Load TMOBR value to the timer 0 binary counter TMOBC At the same time select TMOIO pin input as the clock source TMOMD x 00FE20 7 6 5 4 3 2 1 0 TMO TMO TMO TMO EN LD 51 50 0 1 1 1 Chapter 4 Timers 1 IQOICH TMOICL TMOICH use only byte access Use the MOVB instruction IQOICH sets the timer 0 interrupt level See 3 1 Interrupt Group The interrupt level is 4 in this ex ample 1 Set the value of timer 0 divisor 1 in the timer 0 base register TMOBR If 0 is set in the TMOBR register the TMOBC value remains 0 but the cycle of the timer 0 underflow and the cycle of the clock source are same Setting TMOEN and TMOLD to 0 is required between 5 and 6 in the bank address version and the linear address version but this setting is not required i
413. ext cycle This prevents PWM losses and waveform distortion These counters can serve as interval timers event counters in clock oscillation mode one phase PWMs two phase PWMs two input captures two phase encoders 1x and 4x one shot pulse generators and external count direction controllers They select internal clocks external pins timer 0 underflow or timer 4 underflow as their clock sources TMnIC Timer 0 underflow Timer 4 underflow Up downCounter BOSC 2 Up down Counter CLR Two phase encoder Match TMnIOB 16 bit compare captureA TMnIOA Capture TMnIOA AIR 9 gt 16 bit compare capture gt Q gt TMnIOB Capture Figure 4 3 1 16 bit Timer Block Diagram Table 4 3 1 16 bit Timer Functions Chapter 4 Timers Timer 8 Timer 9 Timer 10 Timer 11 Timer 12 Int i T8UICL T9UICL TIOUICL T11UICL T12UICL e T8AICL T9AICL TIOAICL TI2AICL TIIBICL TI2BICL Int i Timer 8 underflow Timer 9 underflow Timer 10 underflow Timer 11 underflow Timer 12 underflow Timer 8 capture Timer 9 capture A Timer 10 capture A Timer 11 capture A Timer 12 capture A Timer 8 capture B Timer 9 capture B Timer 10 capture B Timer 11 capture B Timer 12 capture B Clock Sources Timer 0 und
414. f0 dO Set NORMAL mode do al 10 1 4 Switching to Standby Mode The program transits the CPU from the CPU operating mode to the standby mode An interrupt switches the CPU from the standby mode to the CPU operating mode The following procedures are required before transferring to the standby mode 1 Clear the interrupt enable flag IE of the processor status word PSW and the interrupt enable flag xxIE of the maskable interrupt control register xxICH to disable all interrupts temporarily 2 Specify interrupt vector for returning from standby mode to the CPU operating mode and set only appropriate xxIE In addition set the IE flag of PSW NORMU V SLOW Mode P Clear IE flag of PSW and all xxIE flags Disable all interrupts of maskable interrupt control registers Enable interrupt for return vector Set HALT STOP Mode Set xxlE for return vector and IE PSW STOP Mode When returning from STOP mode gt wait for oscillation stabilization Y Generate an interrupt for return vector NORMAL The watchdog timer restarts counting V SLOW Mode STOP The watchdog timer is disabled Interrupt Acceptance Cycle Y Figure 10 1 3 Sequence of Switching to from Standby Mode STOP The watchdog timer is reset Chapter 10 Low power Modes 1 CPU cannot recover to the CPU operating mode when in
415. fer This register writes only 24 bit data or 16 bit data Use the MOV instruction or the MOVX instruction to set the data 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 ATI ATI ATI ATI ATI ATI ATI ATI ATI EN BW DB8 DI 88 SI 103 102 IQ1 100 R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 15 Transfer Busy Start Flag 0 Disable 14 13 Transfer Mode 12 Transfer Units 11 Destination Bus Width 10 Destination Pointer Increment 9 Source Bus Width 8 Source Pointer Increment 3 0 ATC Activation Factor Setup 1 Transfer start transfer in progress 00 One byte word transfer 01 Burst transfer 10 Two bytes transfer 11 Reserved 0 Word 1 Byte 0 16 bit 1 8 bit 0 Fixed 1 Increment 0 16 bit 1 8 bit 0 Fixed 1 Increment 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Software Initialization DMAREQ1 pin input External interrupt 2 External interrupt 3 Timer 0 underflow interrupt Timer 4 underflow interrupt Timer 8 underflow interrupt Timer 9 capture A interrupt Timer 10 capture B interrupt Timer 12 capture B interrupt Serial 0 transmission end interrupt Serial
416. flag to 0 and 1 respectively Set the ANICH 2 0 flags to channel 0 and the ANNCH 2 0 flags to the number of the final channel to be converted 2 in this example ANCTR x 00FFO00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AN AN AN AN AN AN AN AN AN AN AN AN AN NCH2 NCHI NCH0 ICH2J1CHI ICHO EN TC DEC CKO MD1 MDO A D Conversion Interval Setup 3 Set the divisor for timer 3 To divide BOSC 2 by 256 write 255 to the timer 3 base register TM3BR The valid range is 0 to 255 00 13 3 3 TM3 TM3 TM3 TM3 TM3 BR7 BR6 BRS 4 BR3 BR2 BRO Do not change the clock source Selecting the clock source while controlling the count operation 7 6 5 4 3 2 1 0 will corrupt the value in the bi TM3 TM3 TM3 nary counter 4 Load the value of the TM3BR register to the timer 3 binary counter TM3BC TM3MD x 00FE23 MN102H55D 55G F55G 225 Chapter 6 Analog Interface 226 MN102H55D 55G F55G 5 Set TM3LD and TM3EN of the TM3MD register to 0 and 1 respectively This starts the timer Counting begins at the start of the next cycle When the timer 3 binary counter reaches 0 and loads the value 255 from the timer 3 base register at the next count a timer 3 underflow interrupt request
417. fter the ANEN flag is set The conversion time is 14 cycles of the A D converter clock 3 73 us 3 73 us to 4 0 us after the ANEN flag is set 4 Wait for conversion to end The ANEN flag is 1 during the conversion and is cleared to 0 when the conversion is completed The program waits until the ANEN flag becomes 0 5 Read the AN6 conversion data buffer AN6BUF The converter divides the volt age between Vref and Vref into 1024 and the conversion result is a value from 0 to 1023 AN6BUF x 00FF14 15 14 12 11 10 3 2 0 AN6 BUF9 AN6 BUF8 AN6 BUF7 AN6 BU6F AN6 BUF5 AN6 BUF4 AN6 AN6 BUF3 BUF2 AN6 BUFI AN6 BUFO ANCTR Setup lE ANEN State Chapter 6 Analog Interface The CPU can read the result value by generating an interrupt In this case the program does not need to wait until the ANEN flag is 0 because an interrupt occurs after the result data is stored in the AN6BUF register AN6 Conversion in Progress eese LT VE ELE LLL 314 AN6BUF AN6BUF Read Interrupt dm 5 er 12113 14 VALID Figure 6 2 3 Single Channel A D Conversion Timing f MN102H55D 55G F55G 223 Chapter 6 Analog Interface 6 2 2 Three Channel A D Conversion The ANO ANI and AN2 pins input analog voltages Vref to Vref and the A D converter convert
418. g TM8CB This loss does not occur even when the output waveforms consist of 1s or Os Use double buffer mode when the PWM is used Select single buffer mode depending on applications TM8EN TM8CB write TM8CB 3 1 TM8BC 0 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 CLRBC8 1 In Double Buffer Mode TM8CB 3 1 TM8CBX 3 i B8 A8 TM8IOA TM8IOB pow Interrupts E 2 In Single Buffer No PWM ahd interrupt distortion TM8CB 3 B8 TM8IOA TM8IOB EN CE A Interrupts z PWM and interrupt losses Figure 4 4 8 Two phase PWM Output Timing 16 bit Timer Dynamical Duty Change 150 MN102H55D 55G F55G 4 4 4 One phase Capture Input Using 16 bit Timer Timer 8 is used to divide BOSC 2 by 65 536 and measure how long TMSIOA input is high An interrupt occurs on capture The width is calculated by the instruction TM8CB TM8CA
419. gister SCORICL requests and verifies a seial 0 reception end interrupt This register allows only byte accesses Use the MOVB in struction to set the data SCORICH x 00FC93 Serial 0 Reception End Interrupt Control Register 8 bit access register SCORICH enables a serial 0 re ception end interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the SCOTLV 2 0 bits of the SCOTICH register 6 5 4 3 2 1 0 SCIT SCIT IR ID R RW R R 0 0 0 0 0 0 0 0 0 1 0 0 0 Serial 1 Transmission End Interrupt Request Flag Serial 1 Transmission End Interrupt Detect Flag 6 5 4 3 2 1 0 5 SCIT IE R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 Serial 1 Transmission End Interrupt Enable Flag 0 No interrupt requested 1 Interrupt requested 0 Interrupt undetected 1 Interrupt detected 0 Disable 1 Enable Chapter 11 Appendix SC1TICL 00 94 Serial 1 Transmission Interrupt Control Register 8 bit access register SC1TICL requests and verifies a serial 1 transmission end inter rupt This register allows only byte accesses Use the MOVB in struction to set the data SC1TICH 00 95 Serial 1 Transmission End Interrupt Control Register 8 bit access register SC1TICH enab
420. he data ADB1 x O0FCDe Address Break 1 Address Pointer 16 24 bit access register ADB 1 sets the address to stop address break 1 operation This register writes only 24 bit data or 16 bit data Use the instruction or the MOVX instruction to set the data R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 Address Break 1 On Off Address Break 0 On Off Address Break 1 Generation Address break 0 Generation Off Off Not generated 1 Generated Not generated Generated Chapter 11 Appendix x ADBCTL x O0FCDA Address Break Control Register 8 bit access register ADBCTL selects the address break function and verifies the address break is generated MN102H55D 55G F55G 397 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATO ATO ATO ATO ATO ATO ATO ATO EN BW DB8 DI 588 SI 103 102 IQ1 100 R W R W R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 15 Transfer Busy Start Flag 0 Disable 14 13 Transfer Mode 12 Transfer Units 11 Destination Bus Width 10 Destination Poi
421. hen BOSC stops in STOP mode All external inputs are sampled on BOSC synchronized with BOSC when the external clock operates TM8CA is cap tured on the rising edge of TM8IOA and is captured on the falling edge of TMBIOA A capture B interrupt is generated on the TM8CB capture and the TM8CA and TM8CB values are read during the interrupt service routine Figure 4 4 10 shows 000 0007 0003 or 3 cycles The same result is obtained even if the TM8CA value is greater than the TM8CB value For example 0003 FFFE 0005 The signal width is calculated by ignoring flags E y mures fio 2 TMBBC 0 0 1 2 4 5 6 7 8 95 10 11 12 ke TM8CA 0 7 TM8CB 0 A E Jh ad hub NE 1 1 22 22202 23 10 Figure 4 4 10 One phase Capture Input Timing 16 bit Timer MN102H55D 55G F55G 153 Chapter 4 Timers 4 4 5 Two phase Capture Input Using 16 bit Timer Timer 8 is used to divide timer 0 underflow by 65 536 and measures the width from the rising edge of the TM8IOA input to the rising edge of TMSIOB input An interrupt occurs on capture
422. hen TM8CB 4 ALLO P ox oe 1 58 Sa EE RENTE NEN EA ie puc i W M M ME i o Interrupts i i 2 When 8 2 X Ue Seri 58 R8 Interrupts 3 When TM8CB FFFF ALL1 040040106 A ee NE BI Re Pod A TA 924 8 EE NE NE ZEE M UM EL T A o ETG n Interrupts 0 is output because S8 does rise onthe first URL UE ig cycle Figure 4 4 4 One phase PWM Output Timing 16 bit Timer MN102H55D 55G F55G 143 Chapter 4 Timers TM8EN TM8CB write TM8CB TM8BC BOSC 2 CLRBC8 1 In Double Buffer Mode TM8CB TM8CBX S8 R8 TM8IOA Interrupts 2 In Single Buffer Mode TM8CB S8 R8 Interrupts 144 MN102H55D 55G F55G When outputting the PWM waveform the timer may change the duty of the PVM output dynamically and may invert 1 and 0 due to the circuit configuration This is caused when the trigger to be changed is lost based on the T F F output circuit The RS F F configuration in timer 8 prevents this error of inverting 1 and 0 at the trig ger loss In addition the PWM waveform may be corrupted and interrupts are lost de
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424. igger Conditions for KI6 Pin Interrupt 11 10 Set Trigger Conditions for 5 Pin Interrupt 9 8 7 6 5 4 3 2 1 0 392 Set Trigger Conditions for Pin Interrupt Set Trigger Conditions for KI3 Pin Interrupt Set Trigger Conditions for KI2 Pin Interrupt Set Trigger Conditions for Pin Interrupt Set Trigger Conditions for KIO Pin Interrupt TG1 TGO Trigger Condition 0 0 Low Level 0 1 Both Edges Positive edge Negative edge 1 0 Falling edge Negative edge 1 1 Rising edge Positive edge MN102H55D 55G F55G KEYTRG x 00FCB2 External Key Interrupt Condition Setup Register 16 bit access register KEYTRG sets the trigger condi tions for external key interrupts Chapter 11 Appendix 13 12 n 10 9 8 7 6 5 4 3 2 1 0 KI7 KI6 5 KI4 KD KIO EN EN EN EN EN EN EN EN x OOFCB4 R R R R R R R R W R W R W R W R W R W R W R W External Key Interrupt 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 on 0 1 Enable Register 16 bit access register Set OR Pin for KI7 Pin 0 Don t set KEYCTR enables an external 1 Set key interrupt Set OR Pin for KI6 Pin 0 Don t set When OR pin is selected key 1 Set interrupt is generated by trigger ing the condition set in the Set OR Pin for KI5 Pin 0 Don t set K
425. ils 25 27 30 33 A8 A15 Output Address Output Refer to Pin 13 AO Description for details 35 38 P30 P37 General purpose Port Refer to Pin 13 P20 Description for details 30 37 0 Input Key Input Interrupt These pins can be used as key input interrupt pins if they are not used as the address output pins in single chip mode processor mode or memory expansion mode The key input interrupt pins can be controlled in bit units Refer to 3 2 2 Key Input Interrupt Setup Examples 32 MN102H55D 55G F55G Chapter 1 General Description Table 1 4 1 List of Pin Functions 12 26 Pin Number Pin Name Function Description 39 42 A16 A19 Output Address Output Refer to Pin 13 AO Description for details P40 P43 VO General purpose Port Refer to Pin 13 P20 Description for details 40 43 44 45 A20 A21 Output Address Output Refer to Pin 13 AO Description for details P44 P45 yo General purpose Port Refer to Pin 18 P20 Description for details 44 45 AN4 AN5 Input A D Conversion Input These pins can be used as A D conversion input pins if they are not used as address output pins in single chip mode processor mode or memory expansion mode Refer to 6 1 Summary of A D Converter 46 A22 Output Address Output Refer to Pin 13 AO Description for details P46 VO General purpose Port 46 Refer to Pin 13 P20 Description for details AN6 Input A D Converter 6 This pin can be used as a A D c
426. iming generation for A D converter MN102H55D 55G F55G 9 Chapter 1 General Description Table 1 2 1 Basic Specifications Timer Counter Five 16 bit timers TM8 to TM12 Two channels of compare capture registers Selectable internal or external clock PWM one shot pulse output Two phase encoder input 4x or 1x method Two 8 bit PWM TM 13 TM14 Two internal compare registers for each channel Two pattern outputs One 16 bit pulse width counter TM15 Capture the counter value whenever the input pulse rises 16 bit watchdog timer ATC Four Channels Automatic transfer is possible between memories memory and peripheral I O for each interrupt vector Transfer unit byte or word Transfer mode single chip or burst mode Transfer addressing source destination pointer increment Up to 4096 words can be transferred Access to 16 Mbyte address space ETC Two Channels Automatic transfer is possible between external device and external memory Transfer unit byte or word Transfer mode single chip or burst mode Transfer addressing source destination pointer increment Up to 4096 words can be transferred Access to 16 Mbyte address space Serial Interface Three Synchronous Interfaces ASCIO to ASCI2 Two shared UART Synchronous TC single master only Interfaces ASCI3 ASCIA A D Converter 10 bit with 8 channels can be used as 8 bit Automatic Scanning D A Converter Two 8 bit channels
427. imm8 abs24 5 MOV An abs24 6 ADD imm24 Dn ADD imm24 An SUB imm24 Dn SUB imm24 An 7 MOV imm24 Dn MOV imm24 An CMP imm24 CMP imm24 An 8 MOV d24 An Dm 9 MOVBU d24 An Dm A MOVB d24 An Dm B 424 Dm MOV abs24 Dn MOVB abs24 Dn MOVBU abs24 Dn D MOV abs24 An JMP JSR BSET label24 label24 m abet BCLR imm8 abs16 BSET imme d8 An BCLR imma d8 An 424 MN102H55D 55G F55G 547 Chapter 11 Appendix Extended Code F Second byte Byte 1 F5 Second byte Upper Lower 0 1 2 3 0 AND imm8 BTST imm8 Dn OR imm8 ADDNF imm8 An 1 MOVB Dm d8 An 2 MOVB d8 An Dm 3 MOVBU d8 An Dm 4 Extended Code J 5 MOVX Dm d8 An 6 Extended Code K 7 MOVX d8 An Dm 8 TBZ d8 0 bp label BZ d8 A1 bp label 9 BSET d8 A0 bp BSET d8 A1 bp A TBNZ d8 0 bp label TBNZ d8 A1 bp label B BCLR d8 0 bp BCLR d8 1 bp C TBZ abs16 bp label TBNZ abs16 bp label D BSET abs16 bp BCLR abs16 bp BGTX BGEX BLEX label label label BEQX BNEX label F Extended Code L Extended Code G Second byte Byte 1 F7 Second byte Upper Lower 0 1 2 3 0 AND imm16 Dn BTST imm16 Dn ADD imm
428. ined undefined undefined undefined undefined undefined 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRCISISRCIASRCI3SRCI2SRCIISRCIO SRCO SRC8 SRC7 SRC6 5 5 SRC4 SRC3 SRC2 SRC1 SRCO R W R W R W R W R W R W R W R W R W R W undefined undefined undefined Jundefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISRC23SRC22SRC2ISSRC20SRCIO9SRCISSRCIT7SRCI R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 408 MN102H55D 55G F55G x 00FD32 ATC 3 Transfer Word Count Register 16 bit access register sets the bytes to be transferred subtracted by 1 Decrement by 1 every time 1 byte data is transferred and reach x OFFF when the transfer is completed This register writes only 16 bit data Use the MOV in
429. ined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 on on on on Count Register 16 bit access register ETOCNT sets the bytes to be transferred subtracted by 1 Decrement by 1 every time 1 byte word data is transferred and reach x OFFF when the transfer is completed This register writes only 16 bit data Use the MOV instruction to set the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETOSRC ETO ETO ETO ETO ETO ETO ETO ETO ETO ETO ETO ETO 0 0 F D44 SRCISISRCIASRCI3SRCI2SRCIISRCIO SRC9 SRC8 SRC7 SRC6 SRCS SRC4 SRC3 SRC2 SRC1 SRCO x R W R W R W R W R W R W R W R W R W R W R W ETC 0 Source undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address Pointer 16 24 bit access register 15 14 13 12 11 10 9 8 7 6 5 4 9 2 1 0 ETOSRC sets the transfer source address When the source pointer increment bit is set to be fixed the transfer source address do not change When the source pointer incre ment bit is set to incr
430. input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports This pin can be used as an A D conversion input pin Refer to 6 1 Summary of A D Converter MN102H55D 55G F55G 45 Chapter 1 General Description Table 1 4 1 List of Pin Functions 25 26 Pin Number Pin Name yo Function Description 63 P95 y o General purpose Port 95 This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports 1 Input A D Converter 1 This pin can be used as an A D conversion input pin Conversion Input Refer to 6 1 Summary of A D Converter 64 P96 yo General purpose Port 96 This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports AN2 Input A D Converter 2 This pin can be used as an A D conversion input pin Conversion Input Refer to 6 1 Summary of A D Converter 65 P97 VO General purpose Port 97 This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports AN3 Input A D Converter 3 This pin can be used as a
431. ins are connected to VDD VSS or leave open depending on pin direction setting 20 MN102H55D 55G F55G Chapter 1 General Description 1 4 9 Processor Mode with 16 bit Bus Address Data Shared Mode 2 og 9 20 z o 0 a o lt lt 2 lt gt amp RR 201590 lt Am lt 555000 89959 5558 83 85 DOEHAHHE lt FFFEFEFLIEEF 10 XK OON OW x OR x c QN 00 QI x F O O O O O OOOH PAO IRQO s 76 50 4 P82 TMOIO SBT3 SCL3 SBI2 PA1 IRQ1 77 49 w P81 DAC1 PA2 IRQ2 78 48 P80 DACO PA3 IRQ3 79 47 w A23 P47 AN7 WDOUT PA4 IRQ4 TM15IB 80 46 lt gt A22 P46 AN6 STOP ADSEP 81 45 A21 P45 AN5 m RST 82 44 w A20 P44 AN4 gt 83 43 w VREF ADI ales MN102H55D i a AD2 lt 86 MN1 02H55G 40 4 A17 P41 AD3 87 39 w A16 P40 ap mo MN102HF55G ne P37 R7 4 3 89 37 4 P36 ADs lt gt 90 TOP VIEW P35 AD7 91 35 gt P34 Vss 92 34 AD8 93 33 4 33 AD9 lt gt 94 32 32 2 AD10 5 95 31 P
432. ion Table 1 2 1 Basic Specifications Structure Internal multiplier 16 bitx16 bit 32 bit and internal saturate operation calculator Load store architecture Eight registers Four 24 bit data registers Four 24 bit address registers Others 24 bit program counter 16 bit processor status word 16 bit multiplication division register Instruction Set 41 instructions 6 addressing modes 1 byte basic instruction length Code assignment 1 byte basic 0 to 6 bytes extension Performance Maximum of 17 MHz internal operating frequency with 34 MHz external oscillator MN102H55D 55G Maximum of 15 MHz internal operating frequency with a 30 MHz external oscillator MN102HF55G Instruction execution clock cycles For register to register operations minimum 1 cycle For branch operations minimum 2 cycles For load store operations minimum 1 cycle Pipeline 3 stage instruction fetch decode execute Address Space Up to 16 Mbyte linear address space Shared instruction data space Interrupt external nonmaskable interrupt 46 maskable interrupts 7 priority level settings Low power Mode SLOW STOP HALT Oscillation Up to 34 MHz Frequency Timer Counter Eight 8 bit timers to TM7 Cascading function form as 16 bit to 64 bit timer Timer output Internal clock source or external clock source Serial Interface clock generation Start t
433. ired from the data transfer request until the data transfer end 15 the total of the bus acquisition and the data transfer time The data transfer time changes depending on the number of waits in the transfer source and the transfer destination The time required for bus acquisition is a minimum of 1 75 x internal operating cycle s after the ETC receives a data transfer request For example if the internal operating cycle is 66 7 ns with a 30 MHz external oscillator the time for bus acquisition is 116 725 ns Internal Operating Cycle T BOSC Data Transfer Request Bus Acquisition gt Bus Acquisitipn Figure 7 3 1 ETC Bus Acquisition Timing After bus is acquired the time required for the data transfer is calculated as follows 4 Ws Wd x m x internal operating cycle s where m the number of data transfer words Ws the number of waits in the source Wd the number of waits in the destination After the transfer ends an ETC transfer end interrupt occurs ETC does not accept an interrupt except NMI during transfer but the ETC accepts an interrupt after the trans fer ends When NMI occurs during transfer the ETC stops the transfer and executes the interrupt service routine The bus acquisition priority is ETCO gt ETC1 gt CPU MN102H55D 55G F55G 241 Chapter 7 ATC ETC 242 Table 7 3 1 ETC Connection Examples
434. ister B TM13MD 00 28 Timer 13 Mode Register TM14BC 00 09 Timer 14 Binary Counter 00 Timer 14 Output Compare Register TM14BR 00 19 Timer 14 Base Register TM14CB x 00FE1B Timer 14 Output Compare Register B TM14MD 00 29 Timer 14 Mode Register Chapter 4 Timers 4 6 8 bit PWM Setup Examples 4 6 1 8 bit PWM Output Timer 13 is used to output PWM from pin and pin The PWM cycle is timer 0 underflow 9 The pin duty is 1 2 and the pin duty is 2 1 The PWM output starts low Set timer 0 to underflow at BOSC 2 divided by 2 CORE D A Converter P6 P1 Interrupt A D Converter P7 P2 8 bit Timers Serial I F P8 P3 16 bit Timers ATC P9 P4 8 bit PWM ETC PA i 5 5 E pulse Width Counter ROM Figure 4 6 1 8 bit PWM Block Diagram 1 Set the timer 0 divisor Since timer 0 divides BOSC 2 by 2 set the timer 0 base register TMOBR to 1 The valid range for TMOBR is 0 to 255 and the actual setting is the divisor to be set 1 TMOBR x 00FE10 7 6 5 4 3 2 1 0 TMO TMO TMO TMO TMO TMO BR7 BR6 BRS 4 BR3 BR2 BRO 0 0 0 0 0 O 1 2 Load TM0BR value to the timer 0 binary counter At the sa
435. ix Vpp 3 0 V to 3 6 V 0V C to 85 C Capacitance Parameter Symbol Conditions Twin Input Pins lt Input CMOS level schmidt trigger gt NMI MODE RST Vpp 3 6 V OSCI pin XI pin at external clock input crystal ceramic self excited oscillation See Figure 1 4 10 to Figure 1 4 11 Pin Capacitance pen Input output pin MN102H55D 55G F55G 299 Chapter 11 Appendix 300 MN102H55D 55G F55G D A D Converter Characteristics VDD AVDD 3 3 V Vss AVss 0 V 25 C Capectarce Parameter Symbol Conditions jot a VREF 3 3 V ee oe Vner 0 V VREF 3 3 V ao 5 em p pepe om e fm ff el Note 1 Always set in relation of VDD gt AVDD gt VREF gt VREF gt AVSS gt VSS Chapter 11 Appendix E D A Converter Characteristics Vpp AVDD 3 3 V Vss AVss 0 V Ta 25 C Capectarce Parameter Symbol Conditions Unit E noa 27 VREF 3 3 V VREF 3 3 L el EX voltage pin 107 40 10 leakage current Note The capacitance values of E2 are operational under VDD VREF 3 3 V Vss VREF 0 V MN102H55D 55G F55G 301 Chapter 11 Appendix 302 MN102H55D 55G F55G F AC Characteristics 3 0 V to 3 6 V Input Timing
436. l set in the ATOLV 2 0 bits of the ATOICH register MN102H55D 55G F55G 389 Chapter 11 Appendix 7 6 5 4 3 2 1 0 AT3 AT3 IR ID R R R R W R R R R 0 0 0 0 0 0 0 on 0 4 ATC 3 Transfer End Interrupt Request Flag 0 ATC Transfer End Interrupt Detect Flag 7 6 5 4 3 2 1 0 gt IE R R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 Transfer End Interrupt Enable Flag 390 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 Interrupt undetected 1 Interrupt detected 0 Disable 1 Enable x OOFCAE ATC 3 Transfer End Interrupt Control Register 8 bit access register requests and verifies an 3 transfer end interrupt This register allows only byte accesses Use the MOVB in struction to set the data ATS3ICH x OOFCAF ATC 3 Transfer End Interrupt Control Register 8 bit access register enables an 3 transfer end interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the ATOLV 2 0 bits of the ATOICH register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 104 104 103 IQ3 102 102 101 100 100 TGO
437. l Memory Burst Transfer Block Diagram 251 Figure 7 4 5 Figure 7 4 6 Figure 7 4 7 Figure 7 4 8 Figure 7 4 9 Figure 8 1 1 Figure 8 2 1 Figure 8 2 2 Figure 8 2 3 Figure 8 3 1 Figure 9 1 1 Figure 9 1 2 Figure 9 1 3 Figure 9 1 4 Figure 10 1 1 Figure 10 1 2 Figure 10 1 3 Figure 11 1 1 Figure 11 1 2 Figure 11 1 3 Figure 11 1 4 Figure 11 1 5 Figure 11 1 6 Figure 11 1 7 ETC External Device External Memory Burst Transfer Configuration 251 ETC External Device External Memory Burst Transfer Timing 2 254 ETC External Device External Memory One Byte Transfer Block Diagram 255 ETC External Device External Memory One Byte Transfer Connection 255 ETC External Device External Memory One Byte Transfer Timing 258 Port Configuration 260 General purpose Port Setup Example 276 Basic Flowchart of General purpose Port Input 277 Basic Flowchart of General purpose Port Output 277 Byte swapped Register 278 Address Break Block Diagram 280 Address Break Operation Example
438. ld the last r No Access output data D7 Do i seme 14 MN102HF55G H55G H55D 2 2 Control Signals 2 2 1 Overview The MN102H55D 55G F55G can delay or hasten the rising timing and the falling timing of RE WE and ALE waveforms in the external memory extension mode In addition it can delay the switching timing of address and data in the address data shared mode The RE short mode and the RE late mode do not affect the BSTRE pin connecting burst ROM The following table shows settings Table 2 2 1 External Memory Control Signal Timing Signal Mode Timing Function Late 05 1 2 3 Delay the falling timing of RE RE Reset Short 0 0 5 1 1 5 Hasten the rising timing of RE Late 1 2 3 Delay the falling timing of WE WE Reset Short 0 0 5 1 1 5 Hasten the rising timing of WE Reset Late 0 0 5 1 1 5 Delay the rising timing of ALE ALE Short 0 0 5 1 1 5 Hasten the falling timing of ALE Address Long 1 1 5 2 3 Delay the switch timing of address and Data data in the address data shared mode Please refer to page 76 to page 79 for the waveform in each mode Chapter 2 Bus Interface MN102HF55G H55G H55D 75 Chapter 2 Bus Interface Table 2 2 2 RE Late and Short Modes Address Data Shared Mode
439. le 1 4 1 List of Pin Functions 22 26 Pin Number Pin Name Function Description 55 P86 yo General purpose Port 86 This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports 9 Timer 9B Input Output This pin can be used as a timer 9 input output pin Refer to Chapter 4 Timers SBI4 Input Serial Interface 4 This pin can be used as a data input pin for serial interface Data Input 4 Refer to Chapter 5 Serial Interface 56 P87 yo General purpose Port 87 This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports 9 Input Timer 9C Input This pin can be used as a timer 9 count clear input pin Refer to Chapter 4 Timers SBO4 Output Serial Interface 4 This pin can be used as a data output pin for serial inter Data Output face 4 Refer to Chapter 5 Serial Interface SDA4 y o Serial Interface 4 This pin be used as an data input output pin for se Data Input Output rial interface 4 Refer to Chapter 5 Serial Interface MN102H55D 55G F55G 43 Chapter 1 General Description Table 1 4 1 List of Pin Functions 23 26 Pin Number Pin Name yo Function Description
440. les a seial 1 transmission end interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the SCOTLV 2 0 bits of the SCOTICH register MN102H55D 55G F55G 377 Chapter 11 Appendix 7 6 5 4 3 2 0 SCIR SCIR IR ID R R R R W R R R 0 0 0 0 0 0 0 o 0 1 4 Serial 1 Reception End 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 0 Serial 1 Reception End 0 Interrupt undetected Interrupt Detect Flag 1 Interrupt detected 7 6 5 4 3 2 0 5 I SCIR IE R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 1 0 Serial 1 Reception End 0 Disable Interrupt Enable Flag 1 Enable 378 MN102H55D 55G F55G SC1RICL 00 96 Serial 1 Reception End Interrupt Control Register 8 bit access register SC1RICL requests and verifies a seial1 reception end interrupt This register allows only byte accesses Use the MOVB in struction to set the data SC1RICH x 00FC97 Serial 1 Reception End Interrupt Control Register 8 bit access register SCARICH enables a serial 1 re ception end interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the SCOTLV 2 0 bits of the SCOTICH register
441. lled on the rising edge of the clock source BOSC 2 Timer 8 does not operate when BOSC stops in STOP mode All external inputs are sampled on BOSC synchronized with BOSC when the external clock operates Figure 4 4 25 shows the timing chart In the example an interrupt occurs when timer 8 changes from down counting to up counting Chapter 4 Timers 1 1 1 1 1 1 1 1 TM8CA 1 1 1 1 1 1 1 1 i TM8CB 1000 1 1 1 1 1 1 11 1 TM8BC 0000 1FFF 1FFE 1FFD 1FFE 1FFF 0000 0001 0002 1000 1001 BOSC 2 Y Y Y Y 101017422 B Interrupt i Figure 4 4 25 External Count Direction Control Timing 16 bit Timer MN102H55D 55G F55G 169 Chapter 4 Timers 4 4 10 External Reset Control Using 16 bit Timer Timer 8 is reset by an external signal while counting up PO CORE D A Converter P6 TMBIC pin gt 1 Interrupt A D Converter P7 P2 8 bit Timers Serial I F P8 gt 16 bit Timers ATC P9 P4 8 amp bitPWM P5 Pulse Width Counter ROM RAM PB Timer 8 BOSC 2 7 TM8BC ree TM8CA 5 L R TMBIC pin gt TM8CB
442. lling Edge 000 At the beginning of 0 5 cycle 001 At the beginning of 1 0 cycle 010 At the beginning of 1 5 cycles 011 At the beginning of 2 0 cycles 100 At the beginning of 2 5 cycles 101 At the beginning of 3 0 cycles 110 At the beginning of 3 5 cycles 111 At the beginning of 4 0 cycles CAS 2 0 Timing Setting of the CAS s Falling Edge 000 At the beginning of 0 5 cyc 001 At the beginning of 1 0 cyc 010 At the beginning of 1 5 cyc 011 At the beginning of 2 0 cyc 100 At the beginning of 2 5 cyc 101 At the beginning of 3 0 cyc 110 At the beginning of 3 5 cyc 111 At the beginning of 4 0 cyc SEL 2 0 Timing Setting of Shifting from Row address to Column Address At the beginning of 0 5 cyc At the beginning of 1 0 cyc At the beginning of 1 5 cyc At the beginning of 2 0 cyc At the beginning of 2 5 cyc At the beginning of 3 0 cyc At the beginning of 3 5 cyc At the beginning of 4 0 cyc Shift Setting from Row Address of AD15 ADO pins to Column Address 0 Do not shift 1 Shift MMD 1 0 Shift Size of DRAM Address 00 8 bit 01 9 bit 10 10 bit 11 Reserved MMD 1 0 Setting 00 01 10 Shift 8 Shift 9 Shift 10 Pin Name ROW Address Output COL Address Output P46 A22 11 11 P45 21 A10 A10 P44 A20 Lo A10 P43 A19 z Lo 9 P42 A18 9 8 41 17 z A8 A7 P40 A16 A8 A7 A6 P37 A15 A7 A
443. lowing is the program example of switching to HALT mode Program 1 mov al d0 or 0 4 dO jump stp hlt Read CPUM Set HALT mode Branch unconditionally to an even ad align 2 gt dress to erase the difference of operating gt conditions mov 40 al nop Insert more than three nops to execute a nop few instructions in the state of pipeline nop after writing to CPUM Returning from HALT mode An interrupt or a reset recovers the CPU from HALT mode Reset proceeds normal operation An interrupt returns the previous mode before entering HALT mode and the watchdog timer restarts counting Switching to STOP mode The CPU transits from NORMAL mode to STOPO mode and from SLOW mode to mode In both cases the oscillation and the CPU stop When the CPU switches to STOP mode the watchdog timer is reset The following is the program example of switching to STOP mode Program 2 Oxfc00 al al dO 0 8 40 Read CPUM Set STOP mode stp_hlt gt Branch unconditionally to an even ad 2 gt dress to erase the difference of operating gt conditions Insert more than three nops to execute a few instructions in the state of pipeline after writing to CPUM Returning from STOP mode An interrupt or a reset recovers the CPU from STOP mode At reset the watchdog timer becomes disabled after operating as the oscillation stabilization wait counter Chapter 11 Appendix Chap
444. ly when 8 bit bus width is selected in the external memory space When destination pointer incre ment or source pointer incre ment is selected the pointer in crements by 1 in byte access and by 2 in word access The ATOIQ 3 0 bits are cleared to 0 by the ATCO transfer end in terrupt Chapter 11 Appendix A 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 ATOCNT ATO ATO 0 0 0 2 CNTLICNT10 CNT9 CNT8 CNT7 6 5 CNT4 CNT3 CNT2 CNTI x R W R W R W R W R W R W R W R W R W R W R W R W ATC 0 Transfer Word 0 0 0 0 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 on on on Count Register 16 bit access register ATOCNT sets the bytes to be transferred subtracted by 1 Decrement by 1 every time 1 byte data is transferred and reach x OFFF when the transfer is completed This register writes only 16 bit data Use the MOV instruction to set the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATOSRC ATO ATO ATO ATO ATO ATO ATO ATO ATO ATO
445. m m m lt AO l lo lO Z lt Z Z lt x altilo HEA 9 2550 x 5955 3 o8 x i 8 3513 gt 8 E gt 2995 2 9 225 2910 8 8988 A asses g O os O oso m 5 of SOE a 2 sng DS ESSE LS CAS must be delayed externally to hold the setup time of the COLUMN address MN102HF55G H55G H55D 72 Chapter 2 Bus Interface The length of wait cycle can be set in 0 5 cycle units Table 2 1 8 Address Data Separate Mode 8 bit Bus DRAM WEH and WEL Method Bish Ey SO eS Sa Sas rut ner NS ky N 1 BENE N z z lt 5 5 ee eee ee Ael ie e p DET 56 ER s ENGEL OQ bas 5 d FH HS 2 2 o ecc 9 S L ee ee a asa gt lt
446. mbler source file when the program is developed with C complier cc 102 MN102H55D 55G F55G 341 Chapter 11 Appendix 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 z STEN QDEC R R R R R W R W 0 0 0 1 Saturation Operation 0 Disable normal operation Setup 1 Enable saturation operation when the ST flag of the PSW register is 1 0 2 bytes 1 cycle Decode 0 Disable Decode at the same cycles Setup in the MN102L00 series 1 Enable Decode the 2 byte instruc tion at high speed 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 GN5 GN4 GN3 GN2 GNI GNO R R R R R R R R R R R R R R R 0 o 7 2 Returns the group number 342 multiplied by 4 MN102H55D 55G F55G EFCR x 0O0FCOS Expansion Control Register 16 bit access register EFCR sets 2 byte 1 cycle de code mode IAGR x O0FCOE Interrupt Accept Group Register 16 bit access register IAGR returns the group number of the accepted interrupt IAGR stores the group number of the accepted interrupt The 6 bit GN field indic
447. me time select BOSC 2 as the clock source TM0MD x 00FE20 7 6 5 4 3 2 1 0 TMO TMO TMO TMO EN LD S1 50 0 1 0 0 MN102H55D 55G F55G 177 Chapter 4 Timers 3 Set TMOLD and TMOEN of the TMOMD register to 0 and 1 respectively This starts the timer Counting begins at the start of the next cycle When the timer 0 binary counter reaches 0 the value 1 of the timer 0 base register is loaded auto matically to the TM8BC counter at the next count TMOBR 00 u 01 TMOBC 00 01 01 00 BOSC 2 BOSC 1 3 TMOMD W TMOMD W Figure 4 6 2 Timer 0 Timing 4 Set the PWM cycle to the timer 13 base register Since the PWM cycle is timer 0 underflow 9 set 8 to the TM13BR register TM13BR x 00FE18 7 6 5 4 3 2 1 0 TMI3TMI3 TMI3 TMIS3 TMI3 TMI3 TMI3 TMI3 BR7 BR6 BRS BR4 BR3 BR2 BRI BRO 0 0 0 0 1 0 178 MN102H55D 55G F55G Chapter 4 Timers 5 Set the duty to the timer 13 output compare register When the TM13BC counter matches the TM13CA register the PWM output of the pin changes to low When the TM13BC counter underflows the PWM output of the TM130A pin changes to high When the TM13BC counter matches the TM13CB register the PWM output of the TM13OB pin changes to low When the TM13BC counter underflows th
448. memory expansion mode During address data shared mode these pins time divides input or output the lower 8 bit address and the lower 8 bit data of the ex ternal memory They become input when the external memory is not accessed Refer to 2 1 Summary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state These pins can be used as general purpose ports if they are not used as data input output pins or address data in put output pins in single chip mode processor mode or memory expansion mode The input output direction is controlled in bit units The pin has a built in software con trol pull up resistor Refer to Chapter 8 Ports 34 MN102H55D 55G F55G Chapter 1 General Description Table 1 4 1 List of Pin Functions 14 26 Pin Number Pin Name Function Description 93 D8 Data I O This pin inputs or outputs the upper 8 bit data of the exter AD8 Address Data nal memory during address data separate mode sor mode or memory expansion mode During address data shared mode this pin time divides input or output the upper 8 bit address and the upper 8 bit data of the external memory It becomes input when the external memory is not accessed Refer to 2 1 Summary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state P10 y o General purpose Port 10 Refer to Pins 84 91 00
449. mer 5 count ing cycle TM5BR sets the counting cycle 1 to 256 The timer 5 binary counter counts the cycle of the TMSBR value 1 When BOSC is selected as the clock source the valid range for TM5BR is 1 to 255 Otherwise the valid range for TM5BR is 0 to 255 MN102H55D 55G F55G 439 Chapter 11 Appendix 7 6 5 4 3 2 1 0 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BRO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 TM7 TM7 TM7 TM7 TM7 TM7 TM7 TM7 BR7 BR6 BRS BRA BR3 BR2 BRI BRO R W R W R W 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 440 MN102H55D 55G F55G TM6BR 16 Timer 6 Base Register 8 bit access register TM6BR sets the timer 6 count ing cycle TM6BR sets the counting cycle 1to 256 The timer 6 binary counter counts the cycle of the TM6BR value 1 The valid range for TM6BR is 0 to 255 TM7BR 17 Timer 7 Base Register 8 bit access register 16 bit access is possible from even address TM7BR sets the timer 7 count ing cycle TM7BR sets the counting cycle 1 to 256 The timer 7 binary counter counts the cycle of the TM7BR value 1 The valid range for TM7BR is 0 to 255 Chapter 1
450. mmary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state This pin can be used as a general purpose input output port if itis not used as DMUX in single chip mode processor mode or memory expansion mode The input output direc tion is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports This pin can be used as a synchronous transfer clock signal input output pin for serial interface 1 if it is not used as DMUX in single chip mode processor mode or memory ex pansion mode Refer to Chapter 5 Serial Interface MN102H55D 55G F55G 39 Chapter 1 General Description Table 1 4 1 List of Pin Functions 19 26 sion Output Pin Number Pin Name yo Function Description 71 74 General purpose Port 74 This be used as general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports SBI Input Serial Interface 1 This pin can be used as a data input pin for serial interface 1 Data Input Refer to Chapter 5 Serial Interface 72 P75 yo General purpose Port 75 This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports S
451. n Chapter 4 Timers 1 Use the MOV instruction to set the data and only use 16 bit write operations The timer 8 binary counter TM8BC is stopped and TM8BC register and RS F F initialized cleared to 0 1 If this setting is omitted the bi nary counter may not count the first cycle Do not change to any other operating modes MN102H55D 55G F55G 165 Chapter 4 Timers TM8CA TM8CB TM8BC BOSC 2 TM8EN TM8IOB S8 R8 166 MN102H55D 55G F55G Timer 8 generates a one shot pulse Timer 8 does not operate when BOSC stops in STOP mode All external inputs are sampled on BOSC synchronized with BOSC when the external clock operates Figure 4 4 22 shows the timing chart Set TM8EN of the TM8MD register on the falling edge of TM8IOB pin and counting starts at the beginning of the next cycle Before counting starts TM8BC is 0 the initial value of TM8IOA pin is 0 and R8 reset signal or S8 set signal cannot be output R8 and S8 are internal control signals When counting starts the count changes from 0 to 1 and the 58 signal is output This sets TM8IOA pin to 1 and outputs the one shot pulse When the count reaches 3 TM8BC resets from 3 to 0 and the R8 signal is output simultaneously TMSIOA pin outputs 0 Since TM8ONE of the TM8MD register is set to 1 TM8EN of the TM8MD register is resets and then counting stops The state is the same state before the falling edge of TM8IOB
452. n 8 bit bus width for external memory is selected 1 Byte Transfer Mode One byte word transfer Burst Transfer Two bytes words transfer available in the byte transfer Reserved Note The LSB of address forcibly becomes 0 in the first byte data transfer and the LSB of address forcibly becomes 1 in the second byte data transfer Transfer Start Busy Flag Disable Transfer start Transfer in progress Note Do not activate ATC by an interrupt and write 0 to ATnEN flag by the user program simultaneously Omitting this procedure causes the CPU to stop Set the applicable register not to generate an interrupt for ATC activation factor before writing 0 to ATnEN flag 234 MN102H55D 55G F55G 15 12 11 Chapter 7 ATC ETC 10 9 8 7 6 5 4 3 2 1 0 7 n ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATn ATnCNT CNTI1 CNT10 CNT9 8 CNT7 CNT6 CNTS 4 CNT3 CNT2 CNTO n Reset 0 0 0 O undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined The ATnCNT register writes only 16 bit data Use the MOV instruction to s
453. n A D conversion input pin Conversion Input Refer to 6 1 Summary of A D Converter 76 PAO yo General purpose Port AO This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports IRQO Input External Interrupt 0 This pin can be used as an external interrupt request input Input pin Refer to Chapter 3 Interrupts 77 1 General purpose Port A1 This can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports IRQ1 Input External Interrupt 1 This pin can be used as an external interrupt request input Input pin Refer to Chapter 3 Interrupts 46 MN102H55D 55G F55G Chapter 1 General Description Table 1 4 1 List of Pin Functions 26 26 Pin Number Pin Name Function Description 78 PA2 General purpose Port 2 This be used as general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports IRQ2 Input External Interrupt 2 This pin can be used as an external interrupt request input Input pin Refer to Chapter 3 Interrupts 79 PA3 y o General purpose Port A3 This pin can be used as a general pur
454. n Set The MN102H series uses an instruction set of 41 instructions designed specially for the programming model for embedded applications To shrink code size instructions have a variable length of one to seven bytes The most frequently used instructions in C language compiler are single byte 6 High speed Interrupt Response Main Program The MNIO2H series halts the instructions execution even during the instruction T N Interrupt Service Routine execution of the instruction with long execution cycles After an inter adus Instruction 2 rupt occurs the program moves to the interrupt service routine within di I Ri six cycles or less The MN102H series improves real time control per formance using the interrupt handler which adjusts interrupt servicing speed Instruction 3 Instruction 4 MN102H55D 55G F55G 3 Chapter 1 General Description 4 MN102H55D 55G F55G 7 Flexible Interrupt Control Structure The interrupt controller supports a maximum of 64 interrupt vectors of them inter rupt vectors 0 to 3 are reserved for nonmaskable interrupts In addition groups of up to four vectors are assigned to classes Each class can be set to one of seven priority levels This provides the software design flexibility and control The CPU is compat ible with software from previous Panasonic peripheral modules 8 High speed High functional External Interface The MN102H series supports external interface fun
455. n data 230 MN102H55D 55G F55G Chapter 7 ATC ETC 7 Data Automatic Transfer Function Chapter 7 ATC ETC 232 MN102H55D 55G F55G 7 1 Summary of 7 1 1 Overview The MN102H55D 55G F55G contains an automatic transfer control ATC The ATC has four channels to transfer the data between the memory spaces The time required from the data transfer request until the data transfer end is the total of the bus acquisition and the data trans fer time The data transfer time changes depending on the number of waits in the transfer source and the transfer destination The time required for bus acquisition is a minimum of 1 75 x internal operating cycle s after the ATC receives a data transfer request For example if the internal operating cycle is 66 7 ns with 30 MHz external oscillator the time for bus acquisition is 116 725 ns Internal Operating Cycle gt BOSC Data Transfer Request Bus Acquisition 2 Bus Acquisition Figure 7 1 1 ATC Bus Acquisition Timing After bus is acquired the time required for the data transfer is calculated as follows 4 Ws Wd x m x internal operating cycle s where m the number of data transfer words Ws the number of waits in the source Wd the number of waits in the destination After the transfer ends an ATC transfer end interrupt occurs ATC does not accept an interrupt except NMI during transfer
456. n for serial interface 0 if itis not used as CAS or LCAS in single chip mode pro cessor mode or memory expansion mode Refer to Chapter 5 Serial Interface 38 MN102H55D 55G F55G Chapter 1 General Description Table 1 4 1 List of Pin Functions 18 26 Pin Number Pin Name Function Description 69 UCAS P72 SBOO Output y o Output DRAM Control Output General purpose Port 72 Serial Interface 0 Data Output This pin outputs UCAS signal when connecting DRAM in processor mode or memory expansion mode Refer to 2 1 Summary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state This pin can be used as a general purpose input output port if it is not used as UCAS in single chip mode processor mode or memory expansion mode The input output direc tion is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports This pin can be used as a data output pin for serial interface 0 if it is not used as UCAS in single chip mode processor mode or memory expansion mode Refer to Chapter 5 Serial Interface 70 DMUX P73 SBT1 Output y o DRAM Control Output General purpose Port 73 Serial Interface 1 Clock Input Output This pin outputs DMUX signal when connecting DRAM in processor mode or memory expansion mode Refer to 2 1 Su
457. n gt Dm 80 Dn lt lt 2 Dm MOV An Am F2 70 An lt lt 2 Am MOV PSW Dn PSW Dn F3 F0 Dn MOV Dn PSW Dn gt PSW F3 D0 Dn lt lt 2 MOV MDR Dn MDR Dn F3 E0 Dn MOV Dn MDR Dn MDR F3 C0 Dn lt lt 2 MOV An Dm mem16 An Dm 20 An lt lt 2 Dm MOV d8 An Dm 16 8 gt 60 An lt lt 2 Dm d8 MOV d16 An Dm mem16 An d16 5Dm F7 C0 An lt lt 2 Dm d16 I d16 h MOV d24 An Dm mem16 An d24 Dm F4 80 An lt lt 2 Dm d24 d24 m d24 h MOV Di An Dm mem16 An Di Dm F1 40 Di lt lt 4 An lt lt 2 Dm MOV abs16 Dn mem16 abs16 Dn C8 Dn abs16 l abs16 h MOV abs24 Dn mem16 abs24 Dn F4 C0 Dn abs24 l abs24 m abs24 h MOV An Am 24 gt 70 lt lt 2 00 72 MOV d8 An Am 24 8 gt 70 An lt lt 2 Am d8 d16 An Am mem24 An d16 Am F7 B0 An lt lt 2 Am d16 1 d16 h MOV d24 An Am 24 924 gt F4 F0 An lt lt 2 Am d24 d24 m d24 h MOV Di An Am mem24 An Di Am F1 00 Di lt lt 4 An lt lt 2 Am MOV abs16 An mem24 abs16 An F7 30 An abs16 l abs16 h MOV abs24 An mem 24 abs24 An F4 D0 An abs24 l abs24 m abs24 h MOV Dm An Dm mem16 An 00 An lt lt 2 Dm MOV Dm d8 An Dm mem16 An d8 40 An lt lt 2 Dm d8 MOV Dm d16 An F7 80 An lt lt 2 Dm d
458. n progress 244 MN102H55D 55G F55G 11 10 Chapter 7 ATC ETC 9 8 7 6 5 4 3 2 1 0 ETn ETIn ETn ETn ETn CNT 7 CNTIO CNT9 CNT8 CNT7 CNT6 CNTS CNT4 CNT3 CNT2 CNTI CNTO Reset 0 0 0 0 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined a The ETnCNT register writes only 16 bit data Use the MOV instruction to set the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETn ETn ETn ETn ETn ETn 5 R 5 5 SRC14 SRCI3 SRCI2 SRC11 SRC1O SRC9 SRC8 SRC7 SRC6 5 5 SRC4 SRC3 SRC2 SRCI SRCO Reset undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETn ETn B 7 7 7 7 SRC23 SRC22 SRC21 SRC20 SRC19 SRC18 SRC17 SRC16 Reset 0 0 0 0 0 0 0 O undefined undefined undefined undefined undefined undefined undefined undefine
459. n the linear address high speed ver sion MN102H55D 55G F55G 117 Chapter 4 Timers Do not change the clock source once you have selected it Selecting the clock source while setting the count operation con trol will corrupt the value in the binary counter 6 Set TMOLD to 0 and TMOEN to 1 This starts the timer Counting begins at the start of the next cycle When the binary counter reaches 0 and loads the value 3 from the base register at the next count a timer 0 underflow interrupt request will be sent to the CPU Interrupt enable TMOBR 90 03 TMOBC 00 01 00 03 Timer 0 underflow interrupt 4 4 TMOIO pin 2 3 5 6 IQOLV W 4 TMOMD W TMOMD W TMOBR W Figure 4 2 2 Event Counter Timing 8 bit Timer 118 MN102H55D 55G F55G 4 2 2 Clock Output Using 8 bit Timer Timer 0 and timer 7 output a BOSC 2 divided by 6 12 cycle pulse the duty is 1 1 8 bit Timer 8 bit Timer BOSC 1 2 Timer 0 Timer 7 gt Timer Pulse Output Divided by 2 Divided by 2 Divided by 3 Figure 4 2 3 Clock Output Configuration Example 8 bit Timer P CORE D AConverer Pe P1 Interrupt A D Converter P7 P2 8 bit Timer Serial F__ P
460. nBR value to TMnBC Reset 2 divisor circuit for timer output TMnEN Timer Counting Operation 0 Counting stop 1 Count operation 110 MN102H55D 55G F55G Table 4 1 2 List 8 bit Timer Control Registers Register Address Function TMOBC x 00FE00 Timer 0 Binary Counter Timer 0 TMOBR x 00FE10 Timer 0 Base Register TMOMD x 00FE20 Timer 0 Mode Register x O0FEOI Timer 1 Binary Counter Timer 1 TMIBR x 00FE11 Timer 1 Base Register TMIMD x O0FE21 Timer 1 Mode Register TM2BC 00 02 Timer 2 Binary Counter Timer 2 TM2BR x 00FE12 Timer 2 Base Register TM2MD 00 22 Timer 2 Mode Register TM3BC x 00FE03 Timer 3 Binary Counter 3 TM3BR x 00FE13 Timer 3 Base Register TM3MD x 00FE23 Timer 3 Mode Register TM4BC x 00FE04 Timer 4 Binary Counter Timer4 TM4BR x 00FE14 Timer 4 Base Register TM4MD x 00FE24 Timer 4 Mode Register TMSBC 00 05 Timer 5 Binary Counter Timer5 TMSBR 00 15 Timer 5 Base Register TMSMD 00 25 Timer 5 Mode Register TM6BC x 00FE06 Timer 6 Binary Counter Timer6 TM6BR x 00FE16 Timer 6 Base Register TM6MD x 00FE26 Timer 6 Mode Register TM7BC 00 07 Timer 7 Binary Counter Timer 7 TM7BR x 00FE17 Timer 7 Base Register TM7MD 00 27 Timer 7 Mode Register Chapter 4 Timers MN102H55D 55G F55G 111 Chapter 4 Timers 4 1 3 8 bit Timer Block Diagrams
461. nal Interrupt 2 Control Register 8 bit access register IQ21CH sets an external inter rupt 2 interrupt level and en ables an interrupt This register allows only byte T accesses Use MOVB instruc tion to set the data MN102H55D 55G F55G 353 Chapter 11 Appendix 7 6 5 4 3 2 1 0 TMQU TM2U IR ID R R R R W R R R R 0 0 0 0 0 0 0 o o o 0 1 4 Timer 2 Underflow Interrupt Request Flag 0 Timer 2 Underflow Interrupt Detect Flag 7 6 5 4 3 2 1 0 2 s TM2U IE R R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 2 Underflow Interrupt Enable Flag 354 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected 0 Disable 1 Enable TM2UICL x 00FC62 Timer 2 Underflow Interrupt Control Register 8 bit access register TM2UICL requests and verifies a timer 2 interrupt This register allows only byte accesses Use MOVB instruc tion to set the data TM2UICH x 0O0FC63 Timer 2 Underflow Interrupt Control Register 8 bit access register TM2UICH enables a timer 2 in terrupt This register allows only byte accesses Use MOVB instruc tion to set the data The inter rupt level is the same level set in the IQ2LV 2 0 bits of the IQ2ICH register Chapter 11 Appendix
462. nal memory write in processor mode or memory expansion mode When connecting SRAM and ROM connect WEL to WE in memory WEL outputs low level when writing the lower bytes bits 0 to 7 of data and writes the data to memory Refer to 2 1 Summary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state Refer to 11 2 3 List of Pin Functions This pin can be used as a general purpose input output port if it is not used as WEL in single chip mode processor mode or memory expansion mode The input output direc tion is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports WEH Output Output Upper Byte Write Enable Output Write Enable Output for DRAM Connection This pin provides a control signal for the external memory write in processor mode or memory expansion mode When connecting SRAM and ROM connect WEH to WE in memory WEH outputs low level when writing the upper bytes bits 8 to 15 of data and writes the data to memory WEH is invalid when 8 bit bus width is selected in proces sor mode or memory expansion mode so that it can be used as a general purpose port 63 pin Refer to 2 1 Summary of Bus Interface During a bus request STOP mode or HALT mode this pin will be in a high impedance state Refer to 11 2 3 List of Pin Functions This pin provides a write enable pin when connecting D
463. nal of External device to the CPU ROM Note The CSn pin RE pin WEL pin and WEH pin are high level The initial values of the address pins and data pins are undefined Figure 2 4 1 Activation Sequence of Each Mode 82 MN102HF55G H55G H55D Chapter Interrupts Chapter 3 Interrupts 84 MN102H55D 55G F55G 3 1 Interrupt Groups 3 1 1 Overview The most important factor in the real time control is how fast the pro gram moves to the interrupt handler processing The MN102H55D 55G F55G improves the interrupt response by aborting instructions in cluding the multiply and divide instruction which require multiple clock cycles The aborted instruction is executed once again after it is returned from the interrupt service routine This section describes the overview of the interrupt system The MN102H55D 55G F55G contains 56 interrupt groups Each interrupt group controls interrupts An inter rupt is generated speedily because one interrupt vector is assigned to each interrupt group Interrupt groups are classified into 14 classes which set its interrupt level AII interrupts from the peripheral circuits such as timers and external pins except reset interrupts are registered into interrupt group controller Once interrupts are regis tered interrupt requests are sent to the CPU according to the interrupt priority level level 0 to 6 set in interrupt group controller Groups 0 to 3 are interrupts for the system Table 3 1
464. nchronous mode Stop Bit Selection SBO Output Hold Time asynchronous mode clock synchronous mode by SBTn pin More than BOSC cycles More than Timer 1 or 4 underflow cycles SCnPTY 2 0 Parity Bit Selection 000 None 100 0 output low 101 1 output high 110 Even 1s are even 111 Odd 1s are odd Others Reserved SCnLN Character Length 0 7 bit 1 8 bit 12 Mode Selection For Serial 0 1 2 For Serial 3 4 Reserved set to 0 12 mode off 12 mode on Bit Order Selection LSB first MSB first select only when the character length is 8 bit SCnPTL Protocol Selection 0 Asynchronous mode 1 Clock synchronous mode 12 mode Start or Stop Sequence Output For Serial 0 1 2 For Serial 3 4 Reserved set to 0 Stop sequence output when changing from 1 to 0 Start sequence output when changing from 0 to 1 SCnBRE Break Transmission 0 Don t break 1 Break Receive Enable Disable Enable Transmit Enable Disable Enable 192 MN102H55D 55G F55G Table 5 1 2 List of Serial Interface Control Registers Register Address Function SCOCTR x 00FD80 Serial 0 Control Register Serial 0 SCOTRB x 00FD82 Serial 0 Transmit Receive Buffer SCOSTR x 00FD83 Serial 0 Status Register SCICTR x 00FD88 Serial 1 Control Register Serial 1 SCITRB x O0FD8A Serial 1 Transmit Receive Buffer SCISTR x O0FD8B Serial 1 Status Register SC2CTR x O0FD90 Serial 2 Control Register Serial 2 SC2TRB 00 92 Serial 2 Transmit Receive Buffer SC2STR x
465. ng when SBD goes high while the MN102HF55G is on This informs that the MN102HF55G is con nected to the serial writer 5 During T3 term the serial writer makes SBD pin to input low level longer enough than the MN102HF55G stabilization wait time Load Program Reset Start SBT pin High amp amp SBD pin Low Yes SBT pin High amp amp SBD pin Low Start serial writer E uH PEE load program ecute user progra Figure 11 4 9 Load Program Start Flow Conditions 1 When the load program initializes a reset start SBD low and SBT high 2 The program waits for tWAIT1 3 SBD must still be low and SBT high 4 Wait that both SBD and SBT become high during tW AIT2 If any above conditions are not met the program returns to the user program MN102H55D 55G F55G 533 Chapter 11 Appendix 11 4 9 Branch to User Program Branch to Reset Service Routine Reset Start Serial Writer Start serial writer load program Branch to 81810 Execute User Program Figure 11 4 10 Reset Service Routine Flow When the reset starts the serial writer load program initializes only if SBD is low The program branches to the user program at address x 81810 Branch to Interrupt Service Routine Interrupt Start Address jmp x 81818 Instruction 80008 3 bytes 2 cycles Write a branch instruction to 81818 Branch to x 81818 Execute user inte
466. ngle buffer Compare register double buffer Capture register TMnIOA pin high or low Capture register TMnIOA pin or TMnIOB pin high TMnONE Counter Operating Mode Selection 0 Repeat example in PWM output mode One shot counting counting stops at the next cycle when TMnBC TMnCA TMnTGE Count Start External Trigger Enable 0 Disable 1 Start counting on the falling edge of TMnIOB Up Down Operating Mode Selection Up counter Down counter Up when TMnIOA is high down when TMnIOA is low Up when TMnIOB is high down when TMnIOB is low TMnNLD TMnBC T F F and RS F F for Pin Output 0 Clear all initialization 1 Enable TMnEN TMnBC Count 0 Disable 1 Enable MN102H55D 55G F55G 133 Chapter 4 Timers 134 MN102H55D 55G F55G Table 4 3 2 List of 16 bit Timer Control Registers Register Address Function TM8MD x 00FE80 Timer 8 Mode Register TM8BC 00 82 Timer 8 Binary Counter TM8CA 00 84 Timer 8 Compare Capture Register Timer 8 TM8CAX x 00FE86 Timer 8 Compare Capture Register Set AX TM8CB 00 88 Timer 8 Compare Capture Register TM8CBX x O0FE8A Timer 8 Compare Capture Register Set BX TM8MD2 x OO0FESE Timer 8 Mode Register 2 TM9MD x 00FE90 Timer 9 Mode Register TM9BC x 00FE92 Timer 9 Binary Counter TM9CA x 00FE94 Timer 9 Compare Capture Register A Timer 9 TM9CAX x 00FE96 Timer 9
467. ning of the next cycle TM8CB x 00FE88 CBI5 CB14 CB12 CB9 CB8 CB6 CBS CB4 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 4 Set TM8NLD and TM8EN of the TM8MD register to 1 and 0 respectively This enables TM8BC RS F F 5 Set TM8NLD and TM8EN of the TM8MD register to 1 This starts the timer Counting begins at the start of the next cycle Chapter 4 Timers 1 Use the MOV instruction to set the data and only use 16 bit write operations The timer 8 binary counter TM8BC is stopped and TM8BC register RS F F are initialized cleared to 0 If this setting is omitted the bi nary counter may not count the first cycle Do not change to any other operating modes MN102H55D 55G F55G 159 Chapter 4 Timers Interrupt Enable Setting 6 Enable interrupts after clearing all prior interrupt requests To do this set IQOLV 2 0 of the external interrupt 0 control register IQOICH to the interrupt level 0 to 6 TM8BIR of the timer 8 capture B interrupt control register TM8BICL to 0 and TM8BIE of the timer 8 capture B interrupt control register TM8BICH to 1 Thereafter a timer 8 capture B interrupt occurs when the TM8BC counter matches TM8CB register Interrupt Processing 7 First determine the interrupt group and factor and clear TM8BIR flag during
468. nstruction to set the data Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM1 OCB 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 8 15 CB14 12 CB11 CB10 9 CB8 CB7 CB6 5 CB4 2 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Timer 10 Compare 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Ca ture Re ister B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 9 16 bit access register TM10CB sets the timer10 PWM duty changes PWM and gener ates a timer 10 capture B inter rupt When capture is selected this register is read only A timer 10 capture B interrupt is generated when capture occurs When compare is selected set the PWM duty When this register matches the timer 10 binary counter a timer 10 capture B in terrupt occurs This register write only 16 bit data Use the MOV instruction to set the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM 1 OCBX E T10C TLOC T10C TIOC TIOC TIOC T10C TIOC T10C T10C TIOC T1OC TIOC T10C T10C 15 14 13 12 10 9 BX8 7 6 5 4 BX3 BX2 BXO x OOFEAA
469. nter Increment 9 Source Bus Width 8 Source Pointer Increment 3 0 ATC Activation Factor Setup 398 MN102H55D 55G F55G 1 Transfer start transfer in progress 00 One byte word transfer 01 Burst transfer 10 Two bytes transfer 11 Reserved 0 Word 1 Byte 0 16 bit 1 8 bit 0 Fixed 1 Increment 0 16 bit 1 8 bit 0 Fixed 1 Increment 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Software Initialization pin input External interrupt 0 External interrupt 1 External interrupt 4 Timer 3 underflow interrupt Timer 7 underflow interrupt Timer 9 underflow interrupt Timer 10 capture A interrupt Timer 11 capture B interrupt Serial 0 transmission end interrupt Serial 0 reception end interrupt Serial 3 transmission end interrupt Serial 3 reception end interrupt A D conversion end interrupt Key interrupt ATOCTR 00 000 0 Control Register 16 bit access register ATOCTR sets the ATCO operat ing control conditions Selecting the two bytes transfer mode is valid only in byte ac cess The LSB of the address in the first byte forcibly becomes 0 and the LSB of the address in the second byte forcibly be comes 1 Selecting word as the unit is not allowed when 8 bit bus width is allowed in the external memory space Selecting 8 bit destination bus width or 8 bit source bus width is allowed on
470. nter is cleared after BOSC 1 clock The pulse width is always stored in the capture register 182 MN102H55D 55G F55G Chapter 4 Timers 4 7 2 Control Registers TM15MD x 00FEDO TM15 15 15 EN CLKIICLKO Mode Register 1 Timer 15 Count Control 0 Count stop 1 Counting Clock Source Selection 00 Timer 0 underflow 01 TM15IB 10 BOSC 2 11 BOSC TM15BC x 00FED2 TMIS 15 TM15 TMI5 TMI5 TMI5 TMI5 TMI5 TMI5 TMI5 TMI5 15 TMIS TMIS TMI5 TMIS Binary Counter 5 BC14 BC13 BC12 BCI1 BC10 BC6 BCS BC3 BC2 TM15CA x 00FED4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 15 TM15 TMI5 TMI5 TMI5 TMI5 TMI5 TMI5 TMI5 TMI5 15 15 15 TMI5 5 Capture Register CAI3 12 10 CA9 CA7 CA6 CAS CA2 CAI CAO Table 4 7 1 List of 16 bit Pulse Width Measure Registers Register Address Function TMISMD x 00FEDO Timer 15 Mode Register TMISBC x O0FED2 Timer 15 Binary Counter TMISCA x O0FED4 Timer 15 Capture Register A MN102H55D 55G F55G 183 Chapter 4 Timers 184 MN102H55D 55G F55G 4 8 16 bit Pulse Width Counter Setup
471. nvert ANO Single Channel Conversion 001 Convert AN1 010 Convert AN2 011 Convert AN3 100 Convert AN4 101 Convert AN5 110 Convert ANG 111 Convert AN7 7 Conversion Start Execution 0 No conversion Flag 1 Conversion in progress 6 Conversion Start at Timer 3 0 Disable underflow 1 Enable 5 AD Converter Resolution 0 8 bit 1 10 bit 3 2 Clock Source Selection 00 BOSC 2 01 BOSC 4 10 BOSC 8 11 BOSC 16 1 0 Operating Mode Selection 00 Single channel single conversion 01 Multiple channels single conversion 10 Single channel continuous conversion 11 Multiple channels continuous conversion MN102H55D 55G F55G 469 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ANO ANO ANO ANO ANO ANO ANO ANO ANO ANO BUF8 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF BUFO R R R R R R R R R R R R R R R R 0 0 0 0 0 O Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ANI ANI BUF8 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUFO R R R R R R R R R R R R R R R R 0 0 0 0 0 O Undefined Undefined Und
472. ocessor address data separate mode 0 1 0 1 0 1 0 1 Other modes 0 0 0 0 0 0 0 0 7 6 Input Output Signal Switch 00 Port 01 11 output 10 input 5 4 P32 Input Output Signal Switch 00 Port 01 A10 output 10 KI2 input 3 2 P31 Input Output Signal Switch 00 Port 01 A9 output 10 input 1 0 P30 Input Output Signal Switch 00 Port 502 MN102H55D 55G F55G 01 A8 output 10 KIO input P3LMD x OOFFF4 Port 3 Mode Register L 8 bit access register P3LMD sets a signal output to the port 3 Chapter 11 Appendix 7 6 5 4 3 2 1 0 P3HMD P3 P3 P3 P3 P3 P3 P3 P3 HMD7 HMD6HMDS HMD4IHMD3HMD2 HMD1 HMDO x O0FFF5 R W R W R W R W R W R W R W R W Port 3 Mode Register H Processor address data separate mode 0 1 0 1 0 1 0 1 Other modes 0 0 0 0 0 0 0 0 I on 8 bit access register 7 6 P37 Input Output Signal Switch 00 Port 01 A15 output P3HMD sets a signal output to 10 KI7 input the port 3 5 4 P36 Input Output Signal Switch 00 Port 01 A14 output 10 KI6 input 3 2 P35 Input Output Signal Switch 00 Port 01 A13 output 10 input 1 0 P34Input Output Signal Switch 00 Port 01 A12 output 10 input MN102H55D 55G F55G 503 Chapter 11 Appendix 7 6 5 4 3 2 1 0
473. ock Operation Example This section describes how to set 19200 bps transfer clock for asynchro nous serial interface by using timer 0 and timer 5 to divide BOSC 2 by 98 In this example select 1 8 as the serial clock source and 8 times of baud rate as the transfer clock The serial Interface determines the baud rate with the 8 bit timer underflow Select the transfer clock to make the timer 5 underflow twice or eight times of the baud rate The serial interface divides the timer underflow by 2 or 8 Always select 1 8 in asynchro nous mode For a baud rate of 19200 bps since BOSC 2 15 MHz with a 30 MHz oscillator 15 MHz 98 8 19132 65 bps This means the timer 5 underflow is divided by 98 In this example timer 0 is divided by 49 and timer 5 by 2 PO CORE D A Converter P6 P1 Interrupt A D Converter P7 8 bit Timer Serial I F P8 P2 P3 16 bit Timer ATC P9 P4 8 bit PWM Erc pa P5 Pulse Width Counter ROM RAM Figure 5 2 5 Serial Clock Block Diagram Table 5 2 1 Transfer Clock Setup Example Transfer Clock Divisor at 30 MHz Divisor Setting Method Setting Examples 38400 bps 49 Set divisor of 49 using timer 5 Set divisor of 98 using timer 5 19200 bps 98 Set divisor of 49 using timer 0 and divisor of 2 using timer 5 Set divisor of 196 using timers 4 and 5 9600 bps 196 Set di
474. ock Source Selection 00 BOSC 2 01 Timer 0 underflow When selecting BOSC as the 10 Timer 4 cascade clock source set 11 the valid 11 BOSC range for TM5BR is 1 to 255 444 MN102H55D 55G F55G Chapter 11 Appendix 7 6 5 4 3 2 1 0 TM6MD TM6 TM6 TM6 TM6 EN LD 1 so x 0O0FE26 RMY RW Timer 6 Mode Register 0 0 0 0 0 0 0 0 on 0 0 8 bit access register 7 TM6BC Count 0 Disable TM6MD sets the timer 6 operat 1 Enable ing conditions 6 Load TM6BR to TM6BC 0 Disable 1 Enable Reset the 1 2 divisor circuit 1 0 Clock Source Selection 00 4 01 Timer 0 underflow 10 Timer 5 cascade 11 Timer 4 underflow 7 6 5 4 3 2 1 0 TM7MD TM7 TM7 TM7 TM7 EN LD 1 80 x 00FE27 x IOWA ARA Timer 7 Mode Register 0 0 0 0 0 0 0 0 on 0 0 on 8 bit access register 16 bit access is possible from even address 7 TM7BC Count 0 Disable 1 Enable TM7MD sets the timer 7 operat ing conditions 6 Load TM7BR to TM7BC 0 Disable 1 Enable T Reset the 1 2 divisor circuit 1 0 Clock Source Selection 00 4 01 Timer 0 underflow 10 Timer 6 cascade 11 TM7IO pin input MN102H55D 55G F55G 445 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 TM8 TMs TMs TMs T
475. ode 0 0 0 0 0 0 0 0 0 0 0 0 Other Modes 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1514 RE Short Mode in CS3 Space 1312 RE Late Mode in CS3 Space 1110 RE Short Mode in CS2 Space 9 8 T 6 5 4 3 2 1 0 480 RE Late Mode in CS2 Space RE Short Mode in CS1 Space RE Late Mode in CS1 Space RE Short Mode in CS0 Space RE Late Mode in CSO Space MN102H55D 55G F55G 00 RE Short 0 Mode Reset 01 RE Short 0 5 Mode 10 RE Short 1 Mode 11 RE Short 1 5 Mode 00 RE Late 0 5 Mode Reset 01 RE Late 1 Mode 10 RE Late 2 Mode 11 RE Late 3 Mode 00 RE Short 0 Mode Reset 01 RE Short 0 5 Mode 10 RE Short 1 Mode 11 RE Short 1 5 Mode 00 RE Late 0 5 Mode Reset 01 RE Late 1 Mode 10 RE Late 2 Mode 11 RE Late 3 Mode 00 RE Short 0 Mode Reset 01 RE Short 0 5 Mode 10 RE Short 1 Mode 11 RE Short 1 5 Mode 00 RE Late 0 5 Mode Reset 01 RE Late 1 Mode 10 RE Late 2 Mode 11 RE Late 3 Mode 00 RE Short 0 Mode 01 RE Short 0 5 Mode Reset 10 RE Short 1 Mode 11 RE Short 1 5 Mode 00 RE Late 0 5 Mode Reset 01 RE Late 1 Mode 10 RE Late 2 Mode 11 RE Late 3 Mode REEDGE x OOFF86 RE Waveform Control Register 16 bit access register REEDGE sets the RE waveform control modes The RE short mode and the RE late mode do no
476. oder Input 1x Configuration Example 2 161 Two phase Encoder Input Timing 1x 16 bit Timer 163 One shot Pulse Output Block Diagram 16 bit Timer 164 One shot Pulse Output Timing 16 bit Timer 166 External Count Direction Control Block Diagram 16 bit Timer ege c a iai 167 External Count Direction Control Configuration Example 167 External Count Direction Control Timing 16 bit Timer 169 External Reset Control Block Diagram 16 bit Timer 170 External Reset Control Timing 16 bit Timer 172 8 bit PWM FUNCOM u A ia Ses uY 173 PWM Output Waveform sse 174 8 bit PWM Block Diagram 177 Timer 0 Timing i a 178 it PWM 180 16 bit Pulse Width Measure Counter 181 16 bit Pulse Width Measure Counter Operation Example 182 16 bit Pulse Width Measure Counter Block Diagram 184 16 bit Pulse Width Measure Counter Timing 186 Serial Interface Configuration 188 Synchronous Mode Connections 194 Asynchronous Mode Connections 194 Mode Connection
477. olum 9 A18 A9 A18 A17 gt A17 A8 A16 7 16 A7 A15 A6 A15 14 5 14 5 1 A4 A13 A4 12 12 11 2 11 2 A10 A1 A10 A1 A9 AO A9 AO D7 0 D7 0 P70 RAS RAS P71 CAS CAS P61 RE OE P62 EL WE Figure 2 1 6 DRAM Connection Example 8 bit Bus Width 15 4 3 12 0 9 8 7 6 5 4 3 2 1 0 EW EW EW EW EXWMD 23 22 21 20 0 1 0 0 15 4 3 12 0 9 8 7 6 5 4 3 2 1 0 EB EB BRC MEMMDI 21 20 2 0 1 0 15 4 3 12 0 9 8 7 6 5 4 3 2 1 0 ARE AS SEL SEL SEL CAS CAS CAS RAS RAS RAS DRAMMDI 2 1 0 EN 2 1 0 2 1 0 2 1 0 1 0 1 1 0 1 0 0 1 1 0 0 1 15 4 3 12 1 0 9 8 7 6 5 4 3 2 1 0 DRAMIDRAM R RCY RCY RCY RCY RCS RCS RCS RRS RRS RRS DRAMNMD2 ACC TM ON 3 2 1 0 2 1 0 2 1 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 1 7 6 5 4 3 2 1 0 PO PO POMD MDI 0 1 T 6 gt 4 3 2 1 0 PILMD 7 6 5 4 3 2 1 0 P2 P2MD MDO 0 7 6 5 4 3 2 1 0 T7 6 5 4 3 2 1 0 P3 P3HMD HMD7 HMD6 HMD5 HMD4 HMD3 HMD2 HMDI HMDO P3LMD LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 FADMD LMD2 LMDI LMDO 1 1 1 7 6 9 4 3 2 1 0 P6 P6 P6MD MD4 MD3 1 1 6 5 4 3 2 1 0
478. on Start Execution Flag 0 No conversion 1 Conversion in progress Channel Selection for Single Channel Conversion Convert ANO Convert AN1 Convert AN2 Convert AN3 Convert AN4 Convert 5 Convert AN6 Convert AN7 Channel Selection for Multiple Channel Conversion Convert ANO Convert from ANO to AN1 Convert from ANO to AN2 Convert from ANO to AN3 Convert from ANO to ANA Convert from ANO to AN5 Convert from ANO to AN6 Convert from ANO to AN7 220 MN102H55D 55G F55G Table 6 1 2 List of A D Converter Control Registers Register Address R W Function ANCTR 00 00 R W A D Converter Control Register 00 8 R A D 0 Conversion Data Buffer ANIBUF x OOFFOA R A D 1 Conversion Data Buffer AN2BUF R A D 2 Conversion Data Buffer AN3BUF x O0FFOE R A D 3 Conversion Data Buffer ANABUF 00 10 R A D 4 Conversion Data Buffer ANSBUF x 00FF12 R A D 5 Conversion Data Buffer AN6BUF x 00FF14 R A D 6 Conversion Data Buffer AN7BUF 00 16 R A D 7 Conversion Data Buffer Chapter 6 Analog Interface MN102H55D 55G F55G 221 Chapter 6 Analog Interface The P46 direction is always set to input regardless of the P4DIR value 222 MN102H55D 55G F55G 6 2 A D Converter Setup Examples 6 2 1 Single Channel A D Conversion The AN6 pin inputs an analog voltage Vref to Vref and obtains the
479. on before the watcchdog interrupt occurred after interrupt service routine is executed Therefore the CPU must reset after the watchdog interrupt occurred Watchdog Timer in STOP Mode When the watchdog timer is enabled and the CPU switches to STOP mode the watchdog timer starts count ing after it operates as the oscillation stabilization wait counter if the CPU returns to the previous mode either NORMAL mode or SLOW mode from STOP mode by an interrupt In the MN102HF55G Flash EEPROM version 217 must be selected as the watchdog interrupt cycle WDMO 0 WDM1 1 when the CPU moves to STOP mode These counters can serve as interval timers event counters in clock oscillation mode one phase 5 two phase PWMs one phase captures two phase encoders 1x and 4 These counters can serve as interval timers event counters in clock oscillation mode one phase PWMs two phase PWMs two input captures two phase encoders 1x and 4 TMnCA TMnCB Operating Mode Selection TMnCA TMnCB Operating Mode Selection Compare register single buffer Compare register single buffer Compare register double buffer Compare register double buffer Capture register TMnIOA pin high and low Capture register TMnIOA pin high or low Capture register TMnIOA pin high TMnIOB pin high Capture register TMnIOA pin or TMnIOB pin high 3 When TM8BC x F
480. on for KI4 pin n n n OR interrupt trigger condition for KI5 pi OR interrupt trigger condition for KI6 pi OR interrupt trigger condition for KI7 Do not set Set 0 1 WDREG x 00FC88 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WD WD WD WD WD CLR P2 PO RST Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset the chip when watchdog interrupt occurs 0 Disable 1 Enable 2 0 Watchdog Interrupt Interval Interval set in CPUM register x 1 Interval set in CPUM register x 2 Interval set in CPUM register x 2 Interval set in CPUM register x 2 Interval set in CPUM register x 2 Interval set in CPUM register x 210 WDCLR Extended Watchdog Counter Clear 0 Do not clear 1 Clear 90 MN102H55D 55G F55G Table 3 1 5 List of Interrupt Control Registers Register Address Function IARG Interrupt Accepted Group Number Register NMICR x 00FC40 Nonmaskable Interrupt Control Register WDICR x 00FC42 Watchdog Interrupt Control Register UNICR x 00FC44 Undefined Instruction Interrupt Control Register EIICR x 00FC46 Error Interrupt Control Register IRQTRG x 00FCBO External Interrupt Condition Setup Register IQOICL 00 50 External Interrupt 0 Control Regis
481. one byte transfer ends SCORICH x 00FC92 7 Select serial reception mode Refer to Serial Interface Setup Examples for de tails Chapter 7 ATC ETC Select 16 bit source bus width and 16 bit destination bus width Select 8 bit source bus width bit source bus width and 8 bit desti nation bus width only when 8 bit bus width for the external memory space is selected The interrupt level is 5 in this ex ample MN102H55D 55G F55G 239 Chapter 7 ATC ETC 1 If this setting is omitted the 4096 byte data is transferred because the ATOCNT value is x OFFF 240 MN102H55D 55G F55G Reset 8 Process the 5 byte serial O reception data Each ATC register value is set as follows ATOCTR x 00FD00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN BW DB8 DI 88 SI 7 7 103 102 101 100 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 Busy flag Hold Hold Hold Hold Hold Hold Hold Reset after 5 byte data indication transfer ATOCNT x OFFF This value is always set regardless of the bytes to be transferred ATOSRC 00 082 The last value is stored ATODST x 008005 The result incremented by 1 is set after the last transfer is com pleted 9 Secure the space for the 5 byte serial 0 re
482. onversion input pin if it is Conversion Input not used as the address output pin in single chip mode processor mode or memory expansion mode Refer to 6 1 Summary of A D Converter STOP Output STOP Status Output This pin outputs high to indicate STOP status if it is not used as the address output pin in single chip mode processor mode or memory expansion mode MN102H55D 55G F55G 33 Chapter 1 General Description Table 1 4 1 List of Pin Functions 13 26 Pin Number Pin Name y o Function Description 47 A23 P47 AN7 WDOUT Output Input Output Address Output General purpose Port 47 A D Converter 7 Conver sion Input Watchdog Timer Overflow Output Refer to Pin 13 AO Description for details Refer to Pin 13 P20 Description for details This pin can be used as a A D conversion input pin if it is not used as the address output pin in single chip mode processor mode or memory expansion mode Refer to 6 1 Summary of A D Converter This pin outputs high when the watchdog timer overflows if itis not used as the address output pin in single chip mode processor mode or memory expansion mode 84 91 00 07 ADO AD7 P00 P07 y o Data I O Address Data I O General purpose Ports 00 07 These pins input or output the lower 8 bit data of the exter nal memory during address data separate mode in proces sor mode or
483. other areas consecu tively Please refer to Figure 2 1 1 Address Space on page 52 for address allocation of external memory spaces EB 01 00 bits at reset can be changed depending on WORD pin input 16 bit Bus Width 8 bit Bus Width 00 AO A1 2 words 01 A1 2 4 words 10 AO A1 A2 A3 8 words 11 A1 A2 A4 16 words 0 Disable 1 Enable 0 Disable 1 Enable 0 Disable 1 Enable 0 Disable 1 Enable 00 1 0 wait cycle 01 1 5 wait cycles 10 2 0 wait cycles 11 3 0 wait cycles 4 bytes 8 bytes 16 bytes 32 bytes 0 5 wait cycle corresponds to BOSC 1 cycle 1 wait cycle cor responds to 1 cycle of instruc tion With a 34 MHz oscillator 0 5 wait cycle 29 4 ns 1 wait cycle 58 8 ns 15 7 6 5 4 3 2 1 0 HS2 HS1 HSO reserv BST BST BST ed ed 2 1 0 R W R W R W R W R W R W R W R W 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 1 0 1 10 8 2 0 Fixed Wait Setting Reserved Reserved Cycle Setting for Burst ROM Shortening First Cycle at Burst Access 000 No wait 001 0 5 wait cycle 010 1 wait cycle 011 1 5 wait cycles 100 2 wait cycles 101 2 5 wait cycles 110 3 wait cycles 111 3 5 wait cycles Set to 0 Set to 0 000 0 5 cycle 001 1 cycle 010 1 5 cycles 011 2 c
484. ous conversion mode S H bp9 A D Converter Base Clock 14 Cycles Figure 6 1 2 A D Converter Timing Therefore select the A D converter clock source as follows Clock Source 5 MHz BOSC frequency For example select BOSC 8 or BOSC 16 with a 30 MHz external oscillator since Clock Source 5 MHz 30 MHz MN102H55D 55G F55G 215 Chapter 6 Analog Interface 214 MN102H55D 55G F55G Single Channel Single Conversion Timing When the operating mode selection bits ANMD 1 0 are set to single channel single conversion the A D converter converts one AN input signal once interrupt occurs when the conversion ends The number of channel to be converted is set to the channel selection bits ANICH 2 0 ANNCH 2 0 are ignored When the software starts the conversion write 0 and 1 to the timer conversion start flag ANTC and the conversion start execution flag ANEN of the A D converter control register ANCTR respectively When ANTC 1 the ANEN flag becomes 1 at timer 3 underflow The ANEN flag remains 1 during the conversion and clears 0 when the conversion ends Start Stop Interrupt request Nch conversion State 71 ANEN Figure 6 1 3 Single Channel Single Conversion Timing Multiple Channels Single Conversion Timing
485. output 110 SBT2 input cannot use P21 as SBI2 input 4 2 P82 Input Output Signal Switch 000 Port 001 TMOIO port SBT3input 010 TMOIO output 011 SBT3 output 100 SBT3 half duplex output 101 SCL3 open drain output 110 SBT2 input cannot use P21 as SBI2 input 7 5 P85 Input Output Signal Switch 000 Port 001 TM9IOA port SBT4 input 010 TM9IOA output 011 5 output 100 SBT4 half duplex output 101 SBT4 open drain output 110 SBO2 output 7 5 P85 Input Output Signal Switch 000 Port 001 9 port SBT4 input 010 TMO9IOA output 011 5 output 100 5 half duplex output 101 SCLA open drain output 110 SBO2 output After reset the initialization program must be located in the external memory space 0 x 000000 to x 3FFFFF The initialization program must be executed first after reset release The initialization program must be allo cated on x 080000 in single chip mode memory expan sion mode or processor mode The pullup resistor value is 10 10 96 The pullup resistor value is 10 1 Definition A D Delete Descrption of low active pins xxx C Change Page 6 Descrption of low active xxx MN102H55D 55G F55G LSI User s Manual September 2000 2nd Edition Issued by Matsushita Electric Industrial Co Ltd Matsushita Electronics Corporation Matsushita Electric Industrial Co Ltd Matsushita Electronics Corporation
486. ow speed frequency generation and synchronization between timers easily In addition they can supply to 16 bit timers as clock sources The BOSC frequency is the same as the high speed oscillation frequency in the normal mode while the BOSC frequency is the same as the low speed oscillation frequency in the slow mode The XI frequency becomes the low speed oscillation frequency under any modes To 16 bit Timer TMOICL Interrupt 16 bit Timer Serial 2 3 Interrupt Interrupt TMZ2ICL Interrupt Serial 0 1 Interrupt AD Converter Activation TMSICL Interrupt Serial 2 3 TMOICL Interrupt Interrupt Serial 0 1 4 Chapter 4 Timers Underflow r Cascade InputO Inputl Input2 Input3 Underflow TMO Underflow Cascade TM3 Cascade InputO Inputl Input2 Input3 Underflow Underflow 4 TM5 Cascade InputO Inputl Input2 Input3 Cascade InputO 4 Inputl Input2 Input3 Underflow Cascade TM6 InputO Inputl Input2 Input3 Underflow TM7 Cascade 4 Timer Output Figure 4 1 1 8 bit Timer Block Diagram _ pin Y Timer Output TM4tO pin imer Output TM7IO pin MN102H55D 55G F55G 107 Chapter 4 Timers Table 4
487. p sequence Clear the SC3IST SC3ISP flags of the SC3STR register by writing to or reading from the SC3TRB register 11 Set the SC3REN flag to disable once immediately after the stop sequence occurs sequence output bit b7 66 65 64 b3 b2 b1 60 JACK Transmission interrupt request Transmission b7 b6 b5 04 03 b2 b1 bO ACK Write to SC3TRB output pin output interrupt request START detection bit 1 i STOP detection bit 1 Start sequence transmission Data Transmisssion 1 Data Transmission 2 Stop bit output Figure 5 2 7 Master Transmission Timing With ACK 208 MN102H55D 55G F55G 5 2 5 Reception This section describes the reception using the serial interface 3 Master reception is operated using SDA3 and SCL3 pins To enter the master reception mode the first 1 byte must be transmitted during master transmission Therefore master reception is performed during the interrupt service routine which runs after the data has been transferred Please refer to 5 2 4 Transmission for master transmission Initial Setting 1 Enable the reception enable flag SC3REN of the serial
488. pending on the timing of changing the duty dynamically in the single buffer mode on the figure below In the double buffer mode the duty can be changed from the next cycle and the PWM loss does not occur at any timing of changing TMnCB Use double buffer mode normally when the PWM is used Select single buffer mode This loss does not occur even when the output waveforms consist of 1s or Os based on applications iB 424 PWM ahd interrupt distortion PWM ihterr pt losses Figure 4 4 5 One phase PWM Output Timing 16 bit Timer Dynamical Duty Change 4 4 3 Two phase PWM Output Using 16 bit Timer Timer 8 is used to divide timer 0 underflow by 5 and outputs a two phase PWM on the fifth cycle The phase difference is two cycles To do this set the timer 8 compare capture register A to the divisor of 5 set value is 4 and the timer 8 compare capture register B to the cycle of 2 the set value is 1 PO D A Converter P6 8 lt
489. phase encoder 1x of TM9IOA pin TM9IOB pin TM9MD x 00FE90 Timer 9 Mode Register 16 bit access register TM9MD sets the timer 9 operat ing conditions During repeat counting hold the TM9EN flag state During one shot counting set the TM9EN flag to 0 when TM9BC TM9CA Chapter 11 Appendix i 6 5 4 3 2 1 0 TMSOMD2 BC RW RW Timer 9 Mode 0 Register 2 8 bit access register 1 TM9BC Clear Using TM9IOB 0 Don t clear TM9MD2 sets the conditions to Pin Input 1 Clear clear the timer 9 binary counter 0 9 Pin Input Polarity 0 Positive 1 Negative MN102H55D 55G F55G 449 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM10MD 10 10 10 10 10 10 10 10 10 10 10 10 10 10 EN NLD UDO TGE ONE ECLR LP ASEL 52 51 50 x 00 FEAO R W R W R R R W R W R W R W R W R W R W R W R W R W R W R W Timer 10 Mode Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o o o on on on 16 bit access register 15 TM10BC Count 0 Disable 1 Enable TM10MD sets the timer 10 oper ating
490. pin When the falling edge of TM8IOB pin occurs again set TM8EN of the TM8MD register repeat the same operations and then results in the one shot pulse output 0003 0001 0000 0001 0002 0003 0000 0001 0002 0003 0000 Figure 4 4 22 One shot Pulse Output Timing 16 bit Timer 4 4 9 External Count Direction Control Using 16 bit Timer Timer 8 counts BOSC 2 and TM8IOA pin controls the count direction up or down An interrupt occurs when the counter reaches the value set in TM8CB register D A Converter P6 TM8IOA 1 P1 Interrupt A D Converter P7 P2 8 bit Timers Serial I F LE 16 bit Timers ATC 8 bit PWM ETC PA P5 Pulse Width Counter ROM RAM Timer 8 BOSC 2 gt TM8BC up down TM8CA E Y Y TMBIOA pin Control 2 TM8CB Capture B interrupt Figure 4 4 23 External Count Direction Control Block Diagram 16 bit Timer TM8BC Value 0 1000 x 1 FFF Capture B interrupt Figure 4 4 24 External Count Direction Control Configuration Example Chapter 4 Timers MN102H55D 55G F55G 167 Chapter 4 Timers 1 Use the MOV ins
491. pose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports IRQ3 Input External Interrupt 3 This pin can be used as an external interrupt request input Input pin Refer to Chapter 3 Interrupts 80 PA4 General purpose Port 4 This be used as general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports IRQ4 Input External Interrupt 4 This pin can be used as an external interrupt request input Input pin Refer to Chapter 3 Interrupts TM15IB Input Timer 15B Input This pin can be used as a base clock input pin for timer 15 pulse width measurement Refer to Chapter 4 Timers 75 NMI Input Nonmaskable Interrupt This pin can be used as a NMI interrupt pin The NMI inter Input rupt occurs on the falling edge of low level In addition this pin can reads the pin state as the general purpose input port P76 Refer to Chapter 3 Interrupts 73 74 PULLUP Input Pull up These pins must be pullde up with 33 50 MN102H55D 55G F55G 47 48 MN102H55D 55G F55G Chapter 1 General Description Connection Examples of Power Pins Oscillator Circuits Reset Pins OSCI OSCO OSCI s H 4 MHz 34 MHz 20pF 33pF 20pF 33 pF 77 Note
492. pt 4 Set the level from 0 to 6 Level Setup 0 External Interrupt 4 Interrupt 0 Disable Enable Flag 1 Enable Chapter 11 Appendix IQ4ICL x 00FC70 External Interrupt 4 Control Register 8 bit access register IQ4ICL requests and verifies an external interrupt 4 interrupt This register allows only byte accesses Use the MOVB in struction to set the data IQA4ICH x 00FC71 External Interrupt 4 Control Register 8 bit access register IQ4ICH sets an external inter rupt 4 interrupt level and en ables an interrupt This register allows only byte accesses Use the MOVB in struction to set the data MN102H55D 55G F55G 361 Chapter 11 Appendix 7 6 5 4 3 2 1 0 ITMAU TM4U IR ID R R R R W R R R R 0 0 0 0 0 0 0 LO o 0 4 Timer 4 Underflow Interrupt Request Flag 0 Timer 4 Underflow Interrupt Detect Flag 7 6 5 4 3 2 1 0 TM4U IE R R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 4 Underflow Interrupt Enable Flag 362 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected 0 Disable 1 Enable TMAUICL x 00FC72 Timer 4 Underflow Interrupt Control Register 8 bit access register TMAUICL requests and verifies a timer 4 interrupt This register allows only byte accesses Use the M
493. ption 1 1 1 Introduction The 16 bit MN102 series high speed linear addressing version designs the new architecture for C language programming based on a detailed analysis for embedded applications This improves the previous system architecture in speed and function to meet the requirements in user sys tems including miniaturization to power consumption This series adapts a load store architecture method for computing within registers in stead of the accumulator system for computing within the memory space in the previ ous series The basic instructions are one byte one machine cycle This reduces code size and improves compiler efficiency This series uses the circuit designed for sub micron technology providing optimized hardware and low system power consump tion This series has up to 16 Mbytes of linear address space and can develop the highly efficient programs The optimized hardware architecture allows lower power con sumption even in large systems 1 1 2 Features This series contains a flexible and optimized hardware architecture as well as a simple and efficient instruction set This allows economy and speed This section describes the features of this series CPU 1 High speed Signal Processing An internal multiplier operates 16 bit x16 bit 32 bit in a single cycle In addition the hardware contains a saturation calculator which must be used in signal processing and increases the signal processing speed 2
494. put Output Control P70 RAS Output Control P70 LCAS Output Control P71 CAS Output Control P71 Selector SBIO Input Control P71 gt SBO0 Output Control P72 UCAS Output Control P 72 SBT1 Input Output Control P73 DMUX Output Control P73 SBI1 Input Control P74 SBO1 Output Control P75 P7IN 5 0 4 Port Input NMI P7IN6 5 1 SBTO Input 70 SBIO Input P71 P71 SBT1 Input P73 SBI1 Input P74 Note The set value of the P7DIR register is valid only when the port function is selected by the P7LMD register or the P7HMD register The input or output direction of serial and DRAM I F is determined automatically by setting the P7LMD register or P7HMD register MN102H55D 55G F55G 271 Chapter 8 Ports Table 8 1 2 Port Block Diagram 9 12 Port Pin Name Block Diagram Port 8 P87 to P80 DACO DACI P8PLU 7 0 gt Register EV TMOIO TM4IO P8OUT 7 0 Register gt N TMOIO Output P82 SBT3 Output P82 TM9IOA SCL3 Output P82 TM4IO Output P83 TM9IOB TM7IO Output P84 SBOS Output P84 elector TM9IC SDA3 Output P84 gt SBI2 TM9IOA Output P85 SBT4 Output P85 SBO2 SBL4 Output P85 SBO2 Output P85 SBT3
495. r Counting begins at the start of the next cycle When the timer 0 binary counter reaches 0 and loads the value 1 from the timer 0 base register at the next count a timer 0 underflow interrupt request will be sent to the CPU Timer 5 Setting 5 Set timer 5 counting stop with the timer 5 mode register TM5MD TMSMD x 00FE25 5 5 TMS 5 EN LD 51 50 0 6 Set the timer 5 divisor Since timer 5 divides BOSC 2 by 2 set the timer 5 base register TM5BR to 1 The valid range for 5 is 0 to 255 TMSBR 00 15 TMS TMS TMS TMS TMS TM5 5 TM5 BR7 BR6 BRS 4 BR3 BR2 BRO 0 O 0 O 1 7 Load TMSBR value to the timer 5 binary counter TM5BC At the same time select the timer 0 underflow as the clock source TMSMD x O0FE25 7 6 5 4 3 2 1 0 5 TM5 TMS 5 EN LD 51 50 0 1 0 1 8 Set 5 and 5 of the TM5MD register to 0 and 1 respectively This starts the timer Counting begins at the start of the next cycle When the timer 5 binary counter reaches 0 and loads the value 1 from the timer 5 base register at the next count a timer 5 underflow interrupt request will be sent to the CPU The serial interface operates synchronizing with the timer 5 underflow output Chapter 5 Serial Interface This setting is unnecessary
496. r 3 Interrupts 96 MN102H55D 55G F55G 3 2 2 External pins P33 P30 KI3 KIO generates key input interrupts An interrupt signal is generated whenever one of P33 P30 is low level After reset is released the external key interrupt condition setup register KEYTRG is sets low level and the KIIR flag of the external key interrupt control register KIICL becomes 0 pin pin KI2 pin pin Key Input Interrupt Setup Examples Y PO CORE D A Converter P6 1 r gt Interrupt A D Converter P7 P2 8 bit Timers Serial I F P8 16 bit Timers ATC P9 8 bit PWM ETC 5 Pulse Width Counter ROM RAM PB Figure 3 2 3 Key Input Interrupt Block Diagram P31 P37 P36 P35 P34 P33 P32 lt AWA LWA P30 Le le hee 3 2 4 4 4 Chapter 3 Interrupts Interrupt Enable Setting 1 Set the port functions to the port 3 mode register L and the port 3 mode register H P3LMD and P3HMD Set P33 P30 pins to input select all P37 P34 pins as ports P3LMD x 00FFF4 PSHMD x 00FFFS 7 6 5 4 3 2 1 0 7 6 5 3 2 1 0 P3 P3 LMD7 LMD
497. r 8 mode register TM8MD Set counting stop and interrupt disable Select up counting Then select TM8IOB pin as the clock source TM8MD x 00FE80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM8 TM8 8 8 TM8 TM8 8 8 TM8 8 8 8 8 TM8 EN NLD UDI UDO TGE ONE MDI MDO ECLR LP ASEL 52 SI SO 0 0 0 0 0 0 0 0 0 1 0 0 1 0 2 Set the timer 8 divisor Since timer 8 divides TM8IOB pin by 5 set the timer 8 compare capture register A TM8CA to 4 The valid range is 1 to x FFFE 8 x 00FE84 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 8 8 8 TM8 8 8 8 8 TM8 8 8 8 8 TM8 CAI5 CA14 CAI3 12 10 CA9 CA6 CAS CA2 CAO 0 0 0 0 0 0 0 0 0 1 0 0 3 Set the phase difference for timer 8 Since the phase difference is 2 cycles of TMSIOB set the timer 8 compare capture register B TM8CB to 1 The valid range is 0 TM8CB TM8CA TM8CB x 00FE88 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 TM8 TM8 TM8 8 TM8 TM8 8 8 8 8 8 TM8 TM8 TM8 TM8 CBI5 CB14 CB12 CB8 CB6
498. r 9 Binary Counter 16 bit access register TM9BC operates timer 9 count ing TM10BC x OOFEA2 Timer 10 Binary Counter 16 bit access register TM10BC operates timer 10 counting TM11BC x O0FEB2 Timer 11 Binary Counter 16 bit access register TM11BC operates timer 11 counting MN102H55D 55G F55G 433 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 TMI2 5 BC14 BC13 BC12 BCII BCIO BC9 BC8 BC7 BC6 BCS BC4 BC3 BC2 BCO R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 434 MN102H55D 55G F55G TM12BC x OOFEC2 Timer 12 Binary Counter 16 bit access register TM12BC operates timer 12 counting Chapter 11 Appendix 7 6 5 4 3 2 1 0 TM1 3BC TMI13 TMI3 TMI3 TMI3 TMI3 TMI3 TMI3 TMI3 BC7 BC6 BCS BC4 BC3 BC2 BCO x OOFE08 SUR R A EIE UE Timer 8 Binary 0 0 0 0 0 0 0 0 Counter 8 bit access register TM13BC operates timer 8 counting F 6 5 4 3 2 1 0 TM1 4BC TM14 TM14 TM14 TM14 TM14 TM14 TM14 TM14 I BC7 BC6 BC5 BC4 BC3 BC2 BCI BCO x OOFEO9 R
499. r address high speed ver sion 1 Do not change the clock source once you have selected it Selecting the clock source while setting the count operation con trol will corrupt the value in the binary counter 1 When starting the timer use the MOV instruction to set TM5MD and TM4MD and only use 16 bit write operations Or set TM5MD first and then set TM4MD LLL dium um n TMOBR 00 01 TMOBC 00 01 01 00 01 00 01 00 01 00 0100 01 00 01 00 00 01 ek P i TMO underflow TM5 4BR 00 EASF TM5 4BC 00 0002 0001 0000 EA60 221 S underflow interrupt ir sit Bp ex je agi NE i d Interrupt enable NE x 1 2 3 4 6 7 8 9 Figure 4 2 8 Interval Timer Timing 8 bit Timer MN102H55D 55G F55G 125 Chapter 4 Timers 1 16 bit timer underflow interrupts occur only during down count ing 126 MN102H55D 55G F55G 4 3 Summary of 16 bit Timer Functions 4 3 1 Overview The MN102H55D 55G F55G has five 16 bit up down counters Each counter has two compare capture registers which capture and compare the up down counter value generate PWM and interrupts The has a mode that changes cycle and transition at the beginning of the n
500. rade Zone Shenzhen 518048 Tel 755 359 8500 Fax 755 359 8516 Panasonic Industrial Shanghai Co Ltd PICS 1F Block A Development Mansion 51 Ri Jing Street Wai Gao Qiao Free Trade Zone Shanghai 200137 Tel 21 5866 6114 Fax 21 5866 8000 THAILAND SALES OFFICE Panasonic Industrial Thailand Ltd PICT 252 133 Muang Thai Phatra Complex Building 31st Fl Rachadaphisek Rd Huaykwang Bangkok 10320 Tel 02 6933407 Fax 02 6933423 KOREA SALES OFFICE Panasonic Industrial Korea Co Ltd PIKL Group Bldg 11th 191 Hangangro 2ga Youngsans ku Seoul 140 702 Korea Tel 82 2 795 9600 Fax 82 2 795 1542 PHILIPPINES SALES OFFICE National Panasonic Sales Philippines NPP 102 Laguna Boulevard Laguna Technopark Sta Rosa Laguna 4026 Philippines Tel 02 520 3150 Fax 02 843 2778 080600 Printed in JAPAN
501. rameter Symbol Conditions Unit EE Serial Interface Related Signal Timing Synchronous Serial Reception F16 Data reception setup time SBI4 0 trxps Flg 11 1 17 Transfer clock input high pulse width F18 icycx4 SBT4 0 Fig 11 1 16 Fig 11 1 17 Input Timing Timer external input clock low pulse width n 0 4 7 t TMnIOA TMnIOB TMnIC n 8 12 me TMnIA TMnIB n 13 15 Fig 11 1 18 Timer external input clock high pulse width 0 4 7 TMnIOB TMnIC 8 12 TMnIA TMnIB 13 15 304 MN102H55D 55G F55G Chapter 11 Appendix G AC Characteristics Output Voo 3 0 V to 3 6 V Output Signal Characteristics Vss 0 V 40 C to 85 70 Capactance Parameter Symbol Conditions Unit System Clock Output Timing System clock output cycle time G1 BOSC 33 3 5 G2 clock output low pulse width G oen output high pulse width ni Mum M s C4 System clock output rise time BOSC MN102H55D 55G F55G 305 Chapter 11 Appendix Von 3 0 V to 3 6 V Output Signal Characteristics Vss 0 V 40 to 85 C pum 70pF EET UM Parameter Symbol Conditions Unit Data Transfer Signal Output Timing 1 Fig 11 1 4 Fig 11 1 5 Fig 11 1 8 to 11 Add
502. rates even while the CPU stops The event counter samples TMnIO pin input on BOSC when the CPU operates On the other hand the event counter counts when TMnIO pin input changes during the CPU stop The CPU transfers to the normal mode after oscillation stability wait when an interrupt is generated At this point the event counter counts TMnIO pin input at the change timing until the oscilla tion stability wait is completed The event counter however starts counting TMnIO pin input at the timing the event counter samples on BOSC PO CORE D A Converter P6 P1 Interrupt A D Converter P7 P2 8 bit Timers Serial I F lt 16 bit Timers ATC P9 P4 8 bit PWM ETC PA P5 Pulse Width Counter ROM RAM PB Figure 4 2 1 Event Counter Block Diagram TMOIO pin 1 Set the interrupt enable flag IE of the processor status word PSW to 1 2 Verify that timer 0 counting is stopped with the timer 0 mode register TMOMD TMOMD x 00FE20 7 6 2 3 2 1 0 TMO TMO TMO TMO EN LD 51 50 0 3 Enable interrupts after clearing all existing interrupt requests do this set IQOLV 2 0 of the external interrupt 0 control register IQOICH to interrupt level 0 6 set TMOIR to 0 and set TMOIE to 1 Thereafter an interrupt will be gener ated when
503. re you design purchase or use For inquiries regarding this manual or any Matsushita semiconductor please contact one of the sales offices listed at the end of this manual or the sales department of Matsushita Electronics Corporation About This Manual This manual is intended for assembly language programming engineers It describes the internal configuration and hardware functions of the MN102H55D 55G F55G microcontrollers Text Conventions This manual contains titles sub titles special notes and warnings Supplementary comments appear in the sidebar 1 Warning Please read and follow these instructions to prevent damage reduced performance Finding Desired Information This manual provides four methods for finding desired information quickly and easily 1 An index for the front of the manual for finding each section 2 A table of contents at the front of the manual for finding desired titles 3 list of figures at the front of the manual for finding illustrations and charts by names 4 Achapter name is located at the upper corner of each page Related Manuals MN10200 Series Linear Addressing High speed Version LSI User Manual Describes the MN10200 series specifications MN10200 Series Linear Addressing High speed Version Instruction Manual Describes the instruction set MN10200 Series Linear Addressing High speed Version C Compiler User Manual Usage Guide Describes the installation
504. register allows only byte accesses Use MOVB instruc tion to set the data x 00FC57 Timer 8 Capture A Interrupt Control Register 8 bit access register TMB8AICH enables a timer 8 capture A interrupt This register allows only byte accesses Use instruc tion to set the data The inter rupt level is the same level set in the IQOLV 2 0 bits of the IQOICH register 7 6 5 4 2 0 101 101 IR ID R R R W R R 0 0 0 0 0 0 0 0 0 1 4 External Interrupt 1 0 No interrupt requested Request Flag 1 Interrupt requested 0 External Interrupt 1 0 No interrupt detected Detect Flag 1 Interrupt detected 7 6 5 4 2 0 101 IQI IQI 101 LV2 LVI LVO IE R R W R W R W R R W 0 0 0 0 0 0 0 0 1 6 4 External Interrupt 1 Set the level from 0 to 6 Level Setup 0 External Interrupt 1 Interrupt 0 Disable Enable Flag 1 Enable Chapter 11 Appendix IQ1ICL 00 58 External Interrupt 1 Control Register 8 bit access register IQ1ICL requests and verifies an external interrupt 1 interrupt This register allows only byte accesses Use MOVB instruc tion to set the data IQ1ICH 59 External Interrupt 1 Control Register 8 bit access register IQ1ICH sets an external inter rupt 1 interrupt level and en ables an interrupt This register allo
505. ress data shared mode In processor mode or memory expansion mode this pin must be used as the address data separate shared mode setup pin Do not change this pin s input during operation When the setting is changed proper operation cannot be guaranteed Refer to 2 1 Summary of Bus Interface This pin can be used as a general purpose input output port in single chip mode The input output direction is con trolled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports MN102H55D 55G F55G 25 Chapter 1 General Description Table 1 4 1 List of Pin Functions 5 26 Pin Number Pin Name y o Function Description 9 BREQ P54 Input y o Bus Request Input General purpose Port 54 BREQ and BRACK pins operate bus arbitration Pulling BREQ low suspends the execution of the current instruc tion makes addresses data and control signals high im pedance and then releases bus After that pull BRACK low While the chip is accessing the bus the chip releases the bus after the bus access is completed Pulling BREQ high at the level detector restores the bus This pin can be used as a general purpose input output port in single chip mode The input output direction is con trolled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports 10 BRACK P55 Output y o Output Bus Request Enable G
506. ress delay time 1 A23 0 A23 16 AD15 0 Address hold time 1 Fig 11 1 4 A23 0 A23 16 Fig 11 1 8 ALE late 0 long 0 mode AD long 1 mode Other Modes tcycx Lap Fig 11 1 8 Late 1 Write data delay time Fig 11 1 4 to 5 D15 0 AD15 0 Fig 11 1 7 5 means WE short mode S 0 0 5 1 1 5 LAD means AD long mode LAD 1 2 3 LALE means ALE long mode LALE 0 0 5 1 1 5 Address hold time 2 AD15 0 Write data hold time D15 0 Fig 11 1 4 to 5 Fig 11 1 7 to 10 306 MN102H55D 55G F55G Chapter 11 Appendix Vpp 3 0 V to 3 6 V Output Signal Characteristics Vss 0 V Ta 40 C to 85 E 70 pF Parameter Symbol Conditions Data Transfer Signal Output Timing 2 Chip select signal fall delay time G11 tcspF ns Bl CS3 0 CS3 1 Fig t1 1 4 105 2 select signal rise delay time Fig 11 1 8109 CS3 0 CS3 1 tesori re 2 signal hold time mo i T i T i i BED mo i i T 7 E i jet S means WE short mode S 0 0 5 1 1 5 MN102H55D 55G F55G 307 Chapter 11 Appendix 308 MN102H55D 55G F55G 3 0 V to 3 6 V Output Signal Characteristics Vss 0 V 40 C to 85 70 pF Parameter Symbol Conditions Unit Data Transfer Signal Output Timing 3 Late 0 5 mode S Read enable signal fall delay time 1 t Fig 11 1 4 to 6 REDF1
507. resses in register relative indirect addressing indexed addressing and register indirect addressing modes Operation Registers The data registers Dn store data transferred to memory and results of arithmetic op erations They also store the offset addresses in indexed addressing and register indi rect addressing modes The multiplication division register MDR stores data for multiplication division op erations PSW The processor status word register stores the flags that indicate the status of the CPU interrupt controller and operation results Interrupt Controller The interrupt controller detects interrupt requests from the peripheral functions and requests the CPU to move to the interrupt servicing routine Bus Controller The bus Controller controls the connection between the CPU internal bus and the CPU external bus It also contains the bus arbitration function Internal Peripheral Function The MN102H55D 55G F55G contains internal peripheral functions including timers serial interface A D converter and D A converters Internal peripheral functions vary depending on the chip models 12 MN102H55D 55G F55G Chapter 1 General Description 1 4 Pin Description 1 4 1 Mode N a lt lt a a oa 0 9 mE omm ooo lt m 22 5550900 ooo o
508. rogress Ready to receive Reception in progress No received data Received data No error Error No error 1 Error Chapter 11 Appendix SC1STR x O0FD8B Serial 1 Status Register 8 bit access register 16 bit access is posible from even address SC1STR reads the status for se rial interface 1 A parity error occurs when the parity bit is 1 although it is set to 0 when the parity bit is O al though it is set to 1 when the parity bit is odd although it is set to even and when the parity bit is even although it is set to odd Parity error data is updated whenever the parity bit is re ceived An overrun error occurs when the next data is received com pletely before the CPU reads the received data SC1TRB Over run error data is updated when ever the last data bit seventh or eighth bit is received Do not poll the SC1RBY flag to verify the reception end in clock synchronous mode Generate a serial 1 reception end interrupt or poll the SC1RXA flag to verify the reception end MN102H55D 55G F55G 421 Chapter 11 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SC2CTR SC2 SC2 SC2 SC2 SC2 5 2 SC2 SC2 SC2 5 2 SC2 TEN REN BRE ed ed OD ed LN 2 1 SB 51 50 x 00FD90 R W R W R W R W R W R R W R W R W R W R
509. rol register SC3CTR to disable and the reserved flags to 0 SC3CTR x 00FD98 SC3 SC3 SC3 5 3 SC3 _ SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 BRE PTL ICM LN PTY2 PTY1 PTYO SB 51 50 0 0 0 0 0 0 0 1 1 1 1 1 1 1 2 Enable serial transmission To do this set the SC3TEN flag of the serial 3 control register SC3CTR to 1 SC3CTR x 00FD98 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SC3 SC3 SC3 5 3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 SC3 5 3 BRE PTL OD LN PTY2 PTY1 PTYO SB 51 50 1 0 0 0 0 0 0 1 1 1 1 1 1 1 3 Enable interrupts after clearing all existing interrupt requests At the same time set the interrupt level Thereafter a serial transmission end interrupt occurs when the data transfer ends SCSTICL x 00FC9C SOT scr IR ID 0 0 Chapter 5 Serial Interface SC2TICH x 00FC98 SC8TICH x 00FC9D The interrupt level is 5 in this ex 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ample SC2T SC2T SC2T alll _ LV2 LV1 LVO IE IE 1 0 1 0 0 0 0 0 0 0 0 1 4 Load the first transfer data to the serial 3 transmit receive register SC3TRB Once the data is loade
510. rrupt service routine Generate 2 cycle delay Figure 11 4 11 Interrupt Service Routine Flow Write only the instruction branching to address x 81818 at the interrupt start address x 80008 534 MN102H55D 55G F55G Chapter 11 Appendix 11 4 10 Serial Interface for Onboard Serial Programming Features Fixed length Serial Interface Character length Data Timing 8 bits or 7 bits Transmission bit order LSB MSB can be selected only when the character Clock source length is 8 bits External clock Timer 5 underflow 1 2 1 8 Timer 1 underflow 1 8 Maximum transfer speed 7 5 Mbps with 30 MHz oscillator Error detection Buffer SBD Overrun error Transmit receive shared buffer Single transmit buffer Double receive buffer usB SBT Figure 11 4 12 Data Transfer Timing MN102H55D 55G F55G 535 Chapter 11 Appendix 11 4 11 PROM Writer Onboard Serial Programming Vpp 3 0 5 0 V All O Program Reverse User Data Program Figure 11 4 13 Programming Flow 536 MN102H55D 55G F55G Chapter 11 Appendix MN102H55D 55G F55G 537 Chapter 11 Appendix 11 5 List of MN102H00 Series Linear Address High speed Edition Instructions MN102H00 SERIES INSTRUCTION SET Instruction Mnemonic MOV Dm An Operation Dm An F2 30 Dm lt lt 2 An MOV An Dm gt F2 F0 An lt lt 2 Dm MOV Dn Dm D
511. rs 5555338 253 000000zazxc zx FEFFEPFEEFFEEF z PF PNT gt 995 9 5890909 c ON 0 OH YT OA Or ON P Po P P Po O OOO tO UO LO O O IO LO UO PAO IRQO gt PA2 IRQ2 PA3 RQ3 PA4 IRQ4 TM15IB 4 P82 TMOIO SBT3 SCL3 SBI2 4 P80 DACO P47 AN7 WDOUT gt P46 AN6 STOP SO AND RRR PA O 81 45 gt P45 AN5 RST 82 44 a P44 AN4 83 43 VREF gt P43 4 gt P42 gt P41 gt P40 5 P37 n P36 P35 lt P34 P33 P32 P31 P30 KIO 4 gt P27 P26 t P25 gt P24 TMI5IA A 1 2 lt MN102H55D MN102H55G MN102HF55G TOP VIEW a o B o I P04 4 3 P05 lt POG P07 lt Vss P10 TM8IOB gt P11 TM8IC P12 TM11IOA lt J P13 TM111IOB P14 TM11lC P15 TM121OA 16 121 lt P17 TM121C 100 oak ON oc RO Oo oo
512. ry Counter Port output y Overflow Output Compare Register A Output Compare Register B Figure 4 5 1 8 bit PWM Function gt ues TMnOA R Selector Port output O TMnOB Selector MN102H55D 55G F55G 173 Chapter 4 Timers Binary Counter PWM cycle set in the base register 174 MN102H55D 55G F55G Output compare A Output compare B E TMnOA pin TMnOB pin Figure 4 5 2 PWM Output Waveform Time When the value in the output compare register matches the value in the binary counter high level is output When the binary counter underflows low level is output Count ing starts when the value in the base register is read into the binary counter again High and low signals are output by switching TMnOA pin or TMnOB pin to a general purpose port without using the PWM function Figure 4 5 2 shows the waveforms which the PWM outputs different duties can be output The binary counter is down counting Table 4 5 1 8 bit PWM Functions Timer 13 Timer 14 Clock Source 0 BOSC 2 1 Timer 0 underflow 0 BOSC 2 1 Timer 0 underflow Output Compare Register TM13CA TM14CA TM13CB TM14CB Output Pin TM140A TM130B TM14OB The PWM cycle is fixed and two waveforms with the Chapter 4 Timers 4 5 2 Control Registers T
513. s 194 Asynchronous Serial Timing Transmission 195 Asynchronous Serial Timing Reception 195 Synchronous Serial Timing Transmission 196 Synchronous Serial Timing Reception 196 Asynchronous Transmission Block Diagram 197 Asynchronous Transmission Timing 199 Figure 5 2 3 Figure 5 2 4 Figure 5 2 5 Figure 5 2 6 Figure 5 2 7 Figure 5 2 8 Figure 6 1 1 Figure 6 1 2 Figure 6 1 3 Figure 6 1 4 Figure 6 1 5 Figure 6 1 6 Figure 6 1 7 Figure 6 2 1 Figure 6 2 2 Figure 6 2 3 Figure 6 2 4 Figure 6 2 5 Figure 6 2 6 Figure 6 3 1 Figure 6 4 1 Figure 6 4 2 Figure 7 1 1 Figure 7 2 1 Figure 7 2 2 Figure 7 3 1 Figure 7 4 1 Figure 7 4 2 Figure 7 4 3 Figure 7 4 4 Synchronous Reception Block Diagram 200 Clock Generation in Synchronous Reception 201 Serial Clock Block Diagram 203 Serial Clock Timing 206 Master Transmission Timing with ACK 208 Master Reception Timing 210 Analog Interface Configuration 212 A D Converter Timing 213 Single Channel Single Conversion Timing 214 Multipl
514. s In the MN102HF55G use only the BOSC divisor of 217 MN102H55D 55G F55G 85 Chapter 3 Interrupts Table 3 1 2 Interrupt Vector and Class Assignment Group Interrupt Vector Class Non mascable O0FCAO R W 102 00 Watchdog 00FC42 R W CPU Core Undefined instruction O0FCAA R W Error interrupt OOFC46 R W Reserved LevelOto6 Reserved Reserved Reserved External interrupt 0 00FC50 R W Timer 0 underflow O0FC52 R W Timer 8 underflow OOFC54 R W Timer 8 capture A OOFC56 R W External interrupt 1 O0FC58 R W Timer 1 underflow OOFC5A R W Timer 8 capture B OOFC5C R W Timer 9 underflow OOFC5E R W External interrupt 2 OOFC60 R W a Timer 2 underflow 00FC62 R W Timer 9 capture A 00FC64 R W Timer 9 capture B 00FC66 R W External interrupt 3 00FC68 R W Timer 3 underflow OOFC6A R W Timer 10 underflow OOFC6C R W Timer 10 capture A OOFC6E R W External interrupt 4 O0FC70 R W Timer 4 underflow 00FC72 R W Timer 10 capture B 00FC74 R W Timer 11 underflow 00FC76 R W External key interrupt O00FC78 R W Timer 5 underflow OOFC7A R W Timer 11 capture A OOFC7C R W Timer 11 capture B OOFC7E R W AD conversion end OOFC80 R W Timer 6 underflow O00FC82 R W Timer 12 underflow OOFC84 R W Timer 12 capture A OOFC86 R W Timer 7 underflow O0FC88 R W Timer 12 capture OOFC8A R
515. s Leave the XO pin open Refer to Figure 1 4 11 If the XI pin is not used as the low speed oscillator input pin connect the XI pin to Vss or If the XO pin is not used as the low speed oscillator output pin leave the XO pin open When the oscillation clock is taken from the chip connecting the XO pin with the external circuit directly is not allowed Select the BOSC pin for a synchronous signal If pin 20 is not used as the XI pin this pin can be used as the general purpose I O port The PBMD register switches the function The input output direction is controlled in bit units The pin has a built in software control pull up resis tor Refer to Chapter 8 Ports MN102H55D 55G F55G 23 Chapter 1 General Description Table 1 4 1 List of Pin Functions 3 26 Pin Number Pin Name y o Function Description 82 RST Input Reset Input This pin resets the chip With a 34 MHz oscillator reset starts when the low level is input to this pin for more than 117 ns Reset starts even when the noise is input to this pin for 117 ns When the high level is input to the pin reset is released After the reset pin becomes high level the oscil lation waits of the high speed oscillation pins OSCI and OSCO are performed approximately 3 855 ms with a 34 MHz oscillator After that the chip starts executing the in struction from x 080000 Refer to Figure 1 4 12 BOSC BIBT1 BIBT2 PBO Output
516. s 8 bit data The conversion occurs peri odically when timer 3 underflows Slider 1 Slider 2 Slider 3 10 10 10 5 5 5 L h1 2 p A D Conversion Data Buffers MN10200 Undertow CPU Core Timer 3 Figure 6 2 4 3 channel A D Conversion Configuration PO CORE D A Converter 1 Interrupt A D Converter P2 8 bit Timer Serial AN2 P96 AN1 P95 P3 16 bit Timer ATC ANO P94 Saree Vref P4 8 bit PWM ETC Vref P5 Pulse Width Counter ROM RAM PB Figure 6 2 5 3 channel A D Conversion Block Diagram 224 MN102H55D 55G F55G Chapter 6 Analog Interface Port Input and A D Converter Setup 1 Set ANO AN1 and AN2 pins P94 P95 and P96 of the port 8 to input using the P9HMD register 9 x 00FFED 7 6 5 4 3 2 1 0 P9 P9 P9 P9 9 9 PO P9 MD7 MD6 5 4 MD2 1 0 0 0 1 1 1 0 0 2 Set the operating conditions in the A D converter control register ANCTR Se lect multiple channel single conversion mode BOSC 8 as the clock source 8 bit conversion resolution Set the conversion start execute flag ANEN and the ANTC
517. s register 7 0 Serial Transmit Receive D ansmit Receive Data SC2TRB writes the serial 2 transmit data and reads the se rial 2 receive data Transmission starts by writing the data into this register The data is received by reading this register In 7 bit transfer the MSB bit 7 becomes 0 The data is read when an interrupt occurs or the SC2RXA flag of the SC2STR register is 1 MN102H55D 55G F55G 423 Chapter 11 Appendix 7 6 5 4 3 2 1 0 SC2 SC2 SC2 SC2 SC2 TBY RBY ed ed ed PE OE R R R R R R R R 0 0 0 0 0 0 0 0 7 Transmission Busy Flag 6 Reception Busy Flag 5 Reserved 4 Received Data 3 2 Reserved 1 Parity Error 0 Overrun Error 424 MN102H55D 55G F55G 0 Ready to transmit 1 Transmission in progress 0 Ready to receive 1 Reception in progress 0 No received data 1 Received data 0 No error 1 Error 0 No error 1 Error SC2STR x 00FD93 Serial 2 Status Register 8 bit access register 16 bit access is possible from even address SC2STR reads the status for se rial interface 2 A parity error occurs when the parity bit is 1 although it is set to 0 when the parity bit is 0 al though it is set to 1 when the parity bit is odd although it is set to even and when the parity bit is even although it is set to odd Parity
518. s register The data is received by reading this register In 7 bit transfer the MSB bit 7 becomes 0 The data is read when an interrupt occurs or the SCORXA flag of the SCOSTR register is 1 MN102H55D 55G F55G 417 Chapter 11 Appendix 7 6 5 4 3 2 1 0 SCO SCO SCO reserv SCO SCO TBY RBY ed ed ed PE OE R R R R R R R R 0 0 0 0 0 0 0 0 7 Transmission Busy Flag 6 Reception Busy Flag 5 Reserved 4 Received Data 3 2 Reserved 1 Parity Error 0 Overrun Error 418 MN102H55D 55G F55G 0 Ready to transmit 1 Transmission in progress 0 Ready to receive 1 Reception in progress 0 No received data 1 Received data 0 No error 1 Error 0 No error 1 Error SCOSTR x 00FD83 Serial 0 Status Register 8 bit access register 16 bit access is posible from even address SCOSTR reads the status for se rial interface 0 A parity error occurs when the parity bit is 1 although it is set to 0 when the parity bit is 0 al though it is set to 1 when the parity bit is odd although it is set to even and when the parity bit is even although it is set to odd Parity error data is updated whenever the parity bit is re ceived An overrun error occurs when the next data is received com pletely before the CPU reads the received data SCOTRB Over run error d
519. ses Use the MOVB in struction to set the data SC3RICH x 0O0FC9F Serial 3 Reception End Interrupt Control Register 8 bit access register SC3RICH enables a serial re ception end interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the SC2TLV 2 0 bits of the SC2TICH register 7 6 5 4 3 2 1 0 E SC4T SC4T IR ID R R R W R R 0 0 0 0 0 0 0 0 0 on 0 0 4 Serial 4 Transmission End 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 0 Serial 4 Transmission End 0 Interrupt undetected Interrupt Detect Flag 1 Interrupt detected 7 6 5 4 3 2 1 0 SCAT SCAT SCAT SC4T LV2 LV1 LVO IE R R W R W R W R R W 0 0 0 0 0 0 0 0 on on o 0 6 4 Serial 4 Transmission End Set the level from 0 to 6 Interrupt Level Setup 0 Serial 4 Transmission End 0 Disable Interrupt Enable Flag 1 Enable Chapter 11 Appendix SCATICL Serial 4 Transmission Interrupt Control Register 8 bit access register SCATICL requests and verifies a serial 4 transmission end inter rupt This register allows only byte accesses Use the MOVB in struction to set the data SCATICH x OOFCA1 Serial 4 Transmission End Interrupt Control Register 8 bit ac
520. sh Enable 9 6 Cycle Setting at Refresh 5 3 Timing Setting of CAS Falling Edge 2 0 Timing Setting of RAS Falling Edge 0 2WE method 1 Reserved 0 Timer 12 underflow 1 Timer 10 underflow Set to 0 0 Disable 1 Enable 0000 2 0 cycles 0001 2 5 cycles 0010 3 0 cycles 0011 3 5 cycles 0100 4 0 cycles 0101 4 5 cycles 0110 5 0 cycles 0111 5 5 cycles 1000 6 0 cycles 1001 6 5 cycles 1010 7 0 cycles Other 7 0 cycles 000 At the beginning of 0 5 cycle 001 At the beginning of 1 0 cycle 010 At the beginning of 1 5 cycles 011 At the beginning of 2 0 cycles 100 At the beginning of 2 5 cycles 101 At the beginning of 3 0 cycles 110 At the beginning of 3 5 cycles 111 At the beginning of 4 0 cycles Chapter 11 Appendix DRAMMD x OOFF92 DRAM 2 Register 16 bit access register DRAMMD2 sets the DRAM modes Use only 2WE method in DRAM mode Do not use 2CAS method DRAM is refreshed once when timer 10 or 12 underflow rupt occurs At 256 times 8 ms the refresh interval is 31 25 us or less MN102H55D 55G F55G 479 Chapter 11 Appendix 15 14 13 I2 11 31 30 31 30 21 REES REES REEL REEL REES REES 20 REEL REEL REES REES REEL REEL REES 21 20 11 10 11 10 OI REES 00 REEL 01 REEL 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Processor M
521. slave responds normally When a parity error does not occur this means the slave does not respond This step is unnecessary for the system without ACK Data Transmission 2 8 Repeat steps 4 to 7 if the data is transmitted con tinuously Stop Sequence 9 Write 0 to the SC3IIC flag of the SC3CTR register to end the data transmission Do not write during transmission 10 Set the SCL3 pin output to high as soon as the SC3IIC flag is written One cycle later set the SDA3 pin output to high to start the stop sequence transmission The SC3ISP flag of the SC3STR reg ister becomes 1 Reception must be enabled to de tect the stop sequence Clear the SC3IST and SC3ISP flags of the SC3STR register by writing to or reading from the SC3TRB register Set the SC3REN flag to disable once immediately after the stop sequence occurs Write the dummy data x FF always Verify that reception ends by an interrupt either a serial 3 transmission end interrupt or a serial 3 re ception end interrupt or polling the received data flag of the serial 3 status register Polling the recep tion busy flag is not allowed during PC mode Equivalent Circuit Block Outputs Analog Signal MN102H55D 55G F55G AVss R lt 8 Or C 2 2000 pF Connect to Vss in the chip model which has no AVss Equivalent Circuit Block Outputs Analog Signal MN102H55
522. ster an instruction adds a Zero or sign extension The multiplication division register stores the upper 16 bits of the 32 bit product of multiplication operations In division operations this register stores the upper 16 bits of the 32 bit dividend before execution and the 16 bit remainder of the quotient after execu tion Memory ROM RAM special function registers for peripheral function control and I O ports are assigned to the same address space Internal Control Registers Interrupt Control Registers Serial Interfacel Registers A D Converter Registers Timer Counter Registers This allocation is an example Actual memory peripheral func tions special function registers and port allocation depends on the model Memory Control Registers Port Registers Chapter 1 General Description Address Space The memory contains up to 16 Mbytes of linear address space The instruction and data areas are not separated so that the internal RAM special function registers for internal peripheral functions are allocated into the first 64 kbytes in memory as the basic configuration There are three memory modes as following depending on mod els 000000 A External Memory x 008000 Internal RAM i 4 Kbytes x 009000 3 4 Reserved 00 00 VO Control Registers 1 Kbyte x 010000 External Memory Program iss 5 16 Mbytes x 080000 Interr
523. stopped and TM8BC register RS F F are initialized cleared to 0 1 If this setting is omitted the bi nary counter may not count the first cycle Do not change to any other operating modes MN102H55D 55G F55G 171 Chapter 4 Timers 172 TM8BC BOSC 2 TM8IC MN102H55D 55G F55G Timer 8 is reset asynchronously while high is input from TMSIC pin This allows to synchronize externally It can be used to adjust the motor speed or to initialize the timer by the hardware Timer 8 does not operate when BOSC stops in STOP mode All external inputs are sampled on BOSC synchronized with BOSC when the external clock operates Figure 4 4 27 shows the timing chart 0000 0001 0002 0003 0004 0000 0001 0002 0003 Pea ees Figure 4 4 27 External Reset Control Timing 16 bit Timer Chapter 4 Timers 4 5 Summary of 8 PWM Functions 4 5 1 Overview The MN102H55D 55G F55G has two 8 bit PWM waveform counters timer 13 and timer 14 A timer can output two waveforms using two output pins BOSC 2 or timer 0 underflow is selected as the clock source Each counter sets the PWM cycle Each counter can output two PWM waveforms with the different duties since each counter has two output compare registers The PWM counters can not generate interrupts BOSC 2 Timer 0 underflow Selector 8 bit Base Register Reload 8 bit Bina
524. struction to set the data AT3SRC x 00FD34 ATC 3 Source Address Pointer 16 24 bit access register AT3SRC sets the transfer source address When the source pointer increment bit is set to be fixed the transfer source address do not change When the source pointer incre ment bit is set to increment in crement by 1 in the byte transfer and by 2 in the word transfer This register writes only 24 bit data or 16 bit data Use the MOV instruction or the MOVX instruction to set the data Chapter 11 Appendix A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AT3DST 0 0 F D 3 8 IDSTISDSTIADSTI3DSTI2DSTI IIDSTIO DST9 DST8 DST7 DST6 DSTS DST4 DST3 DST2 DSTI DSTO x R W R W R W R W R W R W R W R W ATC 3 Desti nation undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined on Address Pointer 16 24 bit access register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AT3DST sets the transfer desti nation address
525. t xFFFF Figure 4 4 15 Two phase Encoder Input 4x Configuration Example 2 Timer 8 Setting 1 Set the operating mode in the timer 8 mode register TM8MD Set counting stop Count setting is ignored Since counting is performed by looping on the TM8CA value set TM8LP of the TM8MD register to 1 Select the two phase encoder 4x as the clock source TM8MD x 00FE80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 TM8 TM8 TM8 TM8 TM8 TM8 TM8 TM8 8 8 8 8 EN NLD UD1 UDO ONE MDI MDO ECLR ASEL 52 SI SO 0 0 0 0 0 0 0 0 0 1 100 1 0 0 2 Set timer 8 looping value to the TM8CA register the valid range to X FFFF The TM8BC counter counts from 0 to x IFFF when writing x 1FFF to the TM8CA register TM8CA x 00FE84 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 8 8 8 8 8 8 8 TM8 8 8 8 8 8 TM8 CAI4 CAI3 CA12 1 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 3 Set the timer 8 interrupt value to the TM8CB register the valid range 0 to TM8CA In this example write x 1000 Whenever the up or down counter reaches this value a capture B interrupt occurs at the begin
526. t Bus Address Data Separate Mode Unused pins require handling in the circuit input pins are connected to VDD VSS output pins leave Open input output pins are connected to VDD VSS or leave open depending on pin direction setting 14 MN102H55D 55G F55G Chapter 1 General Description 1 4 3 Memory Expansion Mode with 16 bit Bus Address Data Separate Mode lt zu a see 232 ole Q na lt lt 2 4 Eo Om moo 2 lt o 205 055242 88 moo E GOO ORFOLEBSHRASS a 2 22 2 1010101 0o0o oogozzzc c r r FrLLEFEEwLEFREF 2 T Ro ON G 5 0 gt 3 35 EEIE PRRRKRS 8588 58858885885 BAS PAO IRQO e PA1 IRQ1 gt PA2 IRQ2 78 PA3 IRQ3 lt 79 PA4 IRQ4 TM151B 4 80 ee ADSEP 4 5 81 RST 82 83 a MN102H55D 2 4 MN102H55G 03 87 MN102HF55G 05 gt 89 ede TOP VIEW D7 91 Vss 92 08 93 09 94 010 lt gt 95 011 96 012 97 013 98 014 a 99 015 100 P82 TMOIO SBT3 SCL3 SBI2 gt P81 DAC1 P80 DACO a A23 P47 AN7 WDOUT A22 P46 AN6 STOP A21 P45 AN5 a A20 P44 AN4 VREF lt gt A19 P43 A18 P42 A17 P41 gt A16 P40 rq A1
527. t Enable Setting 6 Enable interrupts after clearing all prior interrupt requests To do this set IQOLV 2 0 of the external interrupt 0 control register IQOICH to the interrupt level 0 to 6 TM8BIR of the timer 8 capture B interrupt control register TM8BICL to 0 and TM8BIE of the timer 8 capture B interrupt control register TM8BICH to 1 Thereafter a timer 8 capture B interrupt occurs when the TMSBC counter matches the TM8CB register Interrupt Processing 7 First determine the interrupt group and factor and clear TM8BIR flag during the interrupt service routine 8 Execute the interrupt service routine Timer 8 functions as a two phase encoder input Timer 8 does not operate when BOSC stops in STOP mode external inputs are sampled on BOSC synchro nized with BOSC when the external clock operates Figure 4 4 20 shows the counting direction When counting down the next value after 0 becomes the TM8CA value When the TM8BC value matches the TM8CB value a capture B interrupt occurs TM8CA TM8CB TM8BC TM8IOA TM8IOB Interrupts Chapter 4 Timers Figure 4 4 20 Two phase Encoder Input Timing 1x 16 bit Timer 1FFF T A1 1000 0000 1FFF 1FFE 1FFD 1FFE 1FFF 0000 0001 JjoFFF 1000 1001
528. t affect the BSTRE pin connecting burst ROM 15 14 13 12 11 10 9 WEES WEES WEEL WEEL WEES WEES WEEL 31 30 31 30 21 20 21 WEEL 20 WEES WEES WEEL WEEL WEES WEES WEEL 11 10 11 10 01 00 01 WEEL 00 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 WE Short Mode CS3 Space 13 12 WE Late Mode in CS3 Space 11 10 WE Short Mode in CS2 Space 9 8 WE Late Mode in CS2 Space 7 6 WE Short Mode in CS1 Space 5 4 WE Late Mode CS1 Space 3 2 WE Short Mode in CS0 Space 1 0 WE Late Mode in CS0 Space 00 WE Short 0 Mode Reset 01 WE Short 0 5 Mode 10 WE Short 1 Mode 11 WE Short 1 5 Mode 00 WE Late 1 Mode Reset 01 WE Late 2 Mode 10 WE Late 3 Mode 11 Reserved 00 WE Short 0 Mode Reset 01 WE Short 0 5 Mode 10 WE Short 1 Mode 11 WE Short 1 5 Mode 00 WE Late 1 Mode Reset 01 WE Late 2 Mode 10 WE Late 3 Mode 11 Reserved 00 WE Short 0 Mode Reset 01 WE Short 0 5 Mode 10 WE Short 1 Mode 11 WE Short 1 5 Mode 00 WE Late 1 Mode Reset 01 WE Late 2 Mode 10 WE Late 3 Mode 11 Reserved 00 WE Short 0 Mode Reset 01 WE Short 0 5 Mode 10 WE Short 1 Mode 11 WE Short 1 5 Mode 00 WE Late 1 Mode Reset 01 WE Late 2 Mode 10 WE Late 3 Mode 11 Reserved MN102H55D 55G F5
529. t dest lower 16 bits signed 22 src lt dest lower 16 bits signed 23 src gt dest lower 16 bits unsigned 24 src2dest lower 16 bits unsigned 25 src lt dest lower 16 bits unsigned 26 src lt dest lower 16 bits unsigned 27 0 28 VF 1 29 NF 0 30 NF 1 31 src dest 24 bits 32 srczdest 24 bits 542 MN102H55D 55G F55G Instruction Mnemonic Operation BLTX label VX NX 1 C434d8 label VX NX 0 C43 PC Cycle Chapter 11 Appendix Machine Code F5 E0 d8 BLEX label VX NX ZX 1 C434d8 label VX NX ZX 0 C43 PC F5 E3 d8 label VX NX 0 PC 3 d8 label gt PC If VX NX 1 3 gt F5 E2 d8 BGTX label 2 0 PC 3 d8 label gt PC VXANX ZX 1 3 gt F5 E1 d8 BCSX label 1 PC 3 d8 label gt PC CX 0 3 gt 5 4 08 BLSX label CX 1 29 1 PC 3 d8 label gt PC CX 2 0 3 gt F5 E7 d8 label CX 0 PC 3 d8 label PC CX 1 3 gt F5 E6 d8 BHIX label CX ZX 0 PC 3 d8 label PC CX 1 29 1 3 gt F5 E5 d8 label VX 0 PC 3 d8 label PC VX 1 3 gt F5 EC d8 BVSX label VX 1 PC 3 d8 label PC VX 0 3 gt F5 ED d8 BNCX label NX 0 PC 3 d8 label PC NX 1 PC4 3 PC F5 EE d8 B
530. ter When the CPU fetches the ope code of the instruction 2 and the first address of the instruction 2 matches either the address he address break 1 address pointer the CPU operates the undefined instruction x FF instead of the instruction 2 ope code and generates a NMI interrupt forcibly Figure 9 1 2 Address Break Block Diagram Chapter 9 System Control 9 1 2 Control Registers The MN102H55D 55G F55G contains the address break address point ers ADBn and the address break control register ADBCTL ADBCTL x 00FCDA 7 6 5 4 3 2 1 0 Address Break Control Register lm Sp Sp S SD I In the MN102H55D 55G the ADBOCK Address Break 0 Generation ADBOCK and ADB1CK flags do Do not generate not operate correctly Compare Generated the return address to the ADB0 register or ADB1 register to ADB1CK Address Break 1 Generation check the address break inter rupt generation The return ad Do not generate d ADBO real Generated ress is the register value plus 1 or the ADB1 register value plus 1 ADBOON Address Break 0 Operation ADB1ON Address Break 1 Operation ADBO x 00FCD2 ADB1 x 00FCD6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADBn ADBn ADBn ADBn ADBn ADBn ADBn ADBn ADBn ADBn ADBn ADBn ADBn Address Break Als
531. ter IQOICH 00 51 External Interrupt 0 Control Register IQIICL 00 58 External Interrupt 1 Control Register IQIICH x 00FC59 External Interrupt 1 Control Register IQ2ICL x 00FC60 External Interrupt 2 Control Register IQ2ICH x 00FC61 External Interrupt 2 Control Register x 00FC68 External Interrupt 3 Control Register x 00FC69 External Interrupt 3 Control Register IQ4ICL x 00FC70 External Interrupt 4 Control Register IQ4ICH x 00FC71 External Interrupt 4 Control Register TMOUICL x 00FC52 Timer 0 Underflow Interrupt Control Register TMOUICH 00 53 Timer 0 Underflow Interrupt Control Register TMIUICL x 0O0FC5A Timer 1 Underflow Interrupt Control Register TMIUICH x O0FCSB Timer 1 Underflow Interrupt Control Register TM2UICL x 00FC62 Timer 2 Underflow Interrupt Control Register TM2UICH x 00FC63 Timer 2 Underflow Interrupt Control Register TM3UICL x 0O0FC6A Timer 3 Underflow Interrupt Control Register TM3UICH x O0FC6B Timer 3 Underflow Interrupt Control Register TM4UICL x 00FC72 Timer 4 Underflow Interrupt Control Register TM4UICH x 00FC73 Timer 4 Underflow Interrupt Control Register TMSUICL x 00FC7A Timer 5 Underflow Interrupt Control Register 5 x 00FC7B Timer 5 Underflow Interrupt Control Register x 00FC82 Timer 6 Underflow Interrupt Control Register TM6UICH x 00FC83 Timer 6 Underflow Interrupt Control Register TM7UICL x 00FC88 Timer 7 Underflow Interrupt Control Regist
532. ter 11 Appendix 1 This LSI user s manual de scribes standard specifications When using this LSI chip please contact one of our sales offices for product standards 294 MN102H55D 55G F55G 11 1 Electrical Characteristics 11 1 1 MN102H55D 55G CMOS integrated circuit Application General purpose 16 bit microcontroller Pin Configuration Figure 1 4 1 to Figure 1 4 9 External Dimensions Figure 1 4 14 A Absolute Maximum Ratings Vss 0V Power supply voltage 0 3 to 4 6 Input pin voltage 0 3 to 0 3 Output pin voltage 0 3 to 0 3 voltage temperature Storage temperature 55 to 125 Note 1 Absolute Maximum Ratings are stress ratings not to cause damage to the device Operation at these ratings is not guaranteed 2 All of the and Vss pins are external pins Connect them directly to the power source and ground 3 To prevent latch up tolerance connect more than one by pass condenser between power supply pins and ground Use at least 0 2 WF condenser Chapter 11 Appendix B Operating Conditions Vss 0 V KCN 40 C to 85 NM Parameter Symbol Conditions Unit Crystal Oscillator 1 Crystal Oscillator 2 MN102H55D 55G F55G 295 Chapter 11 Appendix C Electrical Characteristics 1 DC Characteristics 3 3 V Vss 0V 40 to 85 Parameter Symbol Conditions or Vss
533. ter 4 Timers 96 D11 VO Data I O Refer to Pin 93 D8 AD8 Description for details AD11 yo Address Data I O P13 General purpose Port 13 Refer to Pins 84 91 00 07 Description for details TM111OB yo Timer 11B Input Output This pin can be used as a timer 11 input capture B input pin or atimer 11 output compare B output pin if it is not used as a data input output pin or an address data input output pin in single chip mode processor mode or memory expansion mode Refer to Chapter 4 Timers 97 D12 VO Data I O Refer to Pin 93 D8 AD8 Description for details AD12 yo Address Data I O P14 General purpose Port 14 Refer to Pins 84 91 00 07 Description for details TM111C Input Timer 11C Input This pin can be used as a timer 11 counter clear pin if it is not used as a data input output pin or an address data in put output pin in single chip mode processor mode or memory expansion mode Refer to Chapter 4 Timers 36 MN102H55D 55G F55G Chapter 1 General Description Table 1 4 1 List of Pin Functions 16 26 Pin Number Pin Name Description 98 D13 Data I O Refer to Pin 93 D8 AD8 Description for details AD13 Address Data I O P15 y o General purpose Port 15 Refer to Pins 84 91 00 07 Description for details TM121OA yo Timer 12A Input Output This pin can be used as a timer 12 input capture A input pin timer 12 output compare A output pin if it is not us
534. ter P6 Reset E m P1 Interrupt A D Converter P7 P2 8 bit Timer Serial 8 P3 16 bit Timer ATC P9 P4 8 bit PWM ETC PA P5 Pulse Width Counter ROM RAM PB Figure 3 2 8 Extended Watchdog Timer Block Diagram Interrupt Enable Setting 1 Set WDP 2 0 bits of the WDREG register to the time for error detection function In this example set 219 Since the chip is reset as soon as a watchdog interrupt occurs set the WDRST flag to 1 WDREG x 00FCBe6 WD WD WD WD WD CLR P2 7 RST 2 Clear the WDRST flag of the CPUM register This starts the watchdog timer and the extended watchdog timer In addition set the WDM flags to the time for error detection function In this example select 2 CPUM x 00FCOO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WD WD WD Osc RST MO 7 7 7 2 ID STOP HALT OSCI 05 0 0 0 0 O 0 0 0 0 0 0 0 0 0 0 0 0 When the above steps complete genertae watchdog interrupt after 4 47 s and reset the chip Clearing the Watchdog Timer 3 Set the WDCLR flag of the WDREG register and the WDRST flag of the CPUM register to 1 and then immediately clear them to 0 This clears the watchdog timer and the extended watchdog timer The watchdog timer is continuously cleared while the WDRST flag is and the extend
535. ter in the external memory Chapter 7 ATC ETC MN102H55D 55G F55G 243 Chapter 7 ATC ETC 7 3 2 Control Registers The ETC contains the ETC control registers ETnCTR and the ETC transfer word count registers ETnCNT the source address pointers ETnSRC and the destination address pointers ETnDST ETnCTR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETn ETn ETn ETn ETn ETn ETn FLG BW 088 DI SB8 SI DIR EN Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETnEN ETC Transfer Enable 0 Disable 1 Enable Transfer Direction between External Device and External Memory From External Device to External Memory From External Memory to External Device Increment Control Flag for Source Address Pointer Fixed Increment by 1 in the byte transfer by 2 in the word transfer 16 bit 8 bit only when 8 bit bus width for external memory is selected Increment Control Flag for Destination Address Pointer Fixed Increment by 1 in the byte transfer by 2 in the word transfer ETnDB8 Destination Bus Width 0 16 bit 8 bit only when 8 bit bus width for external memory is selected ETnBW Transfer Unit 0 Word 1 Byte ETnMDO Transfer Mode 0 One byte word transfer 1 Burst transfer ETnFLG Transfer Start Busy Flag 0 Disable 1 Transfer start Transfer i
536. ternal memory bus width Set the mode such as burst ROM mode Set the DRAM mode Recommend to initialize the port in this step Chapter 11 Appendix MN102H55D 55G F55G 523 Chapter 11 Appendix 524 MN102H55D 55G F55G 11 4 Flash EEPROM Version 11 4 1 Overview The MN102HFS55G replaces the MN102H55G mask ROM with the 128 kbyte EEPROM which is an electrically erasable programmable memory The MN102HF55G has two modes PROM writer mode which uses a dedicated writer either a DATA I O LabSite writer or a Minato Electronics Model 1930 writer and onboard serial program ming mode which the CPU controls The 128 kbyte flash memory is divided into three spaces as follows 1 Load program area 1 kbyte x 80000 x 803FF This area stores the load program for serial programming 2 Fixed user program area 5 kbytes x 80400 x 817FF This area stores the user program It is programmed only in PROM writer mode 3 User program area 122 kbytes x 81800 x OFFFF This area stores the user program It is programmed in both PROM writer mode and onboard serial programming mode The operation is guaranteed with up to ten programming 80000 6 kbytes 2020 Program Area Fixed User Program Area Block3 8 kbytes Block5 8 kbytes Block6 8 kbytes Block7 8 kbytes Block8 8 kbytes User Program Area Block9 8 kbytes Block10 8 kbytes Block11 8 kbytes Block12 8 kbytes Block13
537. terrupt is enabled and the inter rupt priority level is higher than the mask level set in PSW be fore switching to the CPU oper ating mode HALT HALT The watchdog timer stops counting The process shown in parenthe ses is controlled by hardware MN102H55D 55G F55G 291 Chapter 10 Low power Modes Assign the JMP instruction and set the CPUM write to an even address with ALIGN instruction This prevents the effects due to the difference of memory mode and expansion bus widths and outcomes the same result under any conditions Note The ALIGN value must be set to more than 2 when the ALIGN value is set by the quasi SEC TION instruction before this ex ample within the file describing the program When the CPU ends the oscilla tion stabilization wait and switches to the CPU operating mode the watchdog timer be comes disabled automatically When the watchdog timer op eration is required set the watchdog timer enabled 1 The oscillation stabilization wait is executed by hardware when returning from STOP mode The program does not need to count the oscillation stabilization wait time 292 MN102H55D 55G F55G Switching to HALT mode The CPU switches from NORMAL mode to HALTO mode and from SLOW mode to mode In both cases only CPU stops keeping oscillation status When the CPU switches to HALT mode while the watchdog timer is enabled the watchdog timer stops counting The fol
538. the interrupt service routine 8 Execute the interrupt service routine Timer 8 functions as a two phase encoder input Timer 8 does not operate stably when BOSC stops in STOP mode external inputs are sampled on BOSC synchro nized with BOSC when the external clock operates Figure 4 4 16 shows the counting direction When counting down the next value after 0 becomes the TM8CA value When the TM8BC value matches the TM8CB value a capture B interrupt occurs TM8CA 1FFF TM8CB TM8BC TM8IOA 8 Interrupt Up Counting Down Counting TMBIOA T 1 4 o T 0 4 1 TMsiOoB 0 T 1 i 1 T 4 Figure 4 4 16 Two phase Encoder Input Timing 4x 16 bit Timer 160 MN102H55D 55G F55G 4 4 7 Two phase Encoder Input 1x Using 16 bit Timer Timer 8 receives a two phase encoder input 4x and counts up and down An interrupt occurs when the preset value is reached PO CORE D A Converter P6 TM8IOA T A D Converter 1 Interrupt V P7 P2 8 bit Timers Serial P8 P3 16 bit Timers ATC P9 P4 8 bit PWM ETC PA P5 Pulse Width Counter ROM RAM PB Timer 8 TM8BC TM8CA
539. the ADBICK flag are not cleared automati cally ADBCTL x 00FCDA ADBI ADBO ADBI ADBO 4 Jump into the subroutine 2 developed on the internal RAM in advance Add 6 to the value of the stack pointer AR3 register to remove the program counter PC value and PSW value stored by the NMI interrupt from the stack In addition clear the NMIF flag of the NMICR register to 0 16 bits PI U Stack Pointer 0 PSW AR3 Program Counter PC and PSW Lower PC Stored by a NMI interrupt 4 Upper PC lt 4 6 Lower PC PC stored when the program jumps 8 Upper PC __ from the main routine to the subroutine 1 Figure 9 1 4 Stack State after NMI Interrupt 5 Execute the subroutine 2 on the internal RAM and return to the original main routine with the RTS instruction Chapter 9 System Control In the MN102H55D 55G the ADBOCK and ADB1CK flags do not operate correctly Compare the return address to the ADBO register or ADB1 register to check the address break inter rupt generation The return ad dress is the ADBO register value plus 1 or the ADB1 register value plus 1 MN102H55D 55G F55G 283 Chapter 9 System Control 9 2 System Related Register Protection 9 2 1 Overview The MN102H55D 55G F55G contains the system control register which prohibits programming the system related registers by the erro neous operations Writing the value except x 7D to the
540. the serial writer through RS 232C The serial writer programs the flash memory through serial communication between the serial writer and the MN102HF55G on the target board The power is required only when the power source is supplied to the target Pin Connection for Target Board External Power Source Target Board gt y O RST VPP SCL1 SDA1 chip Figure 11 4 7 Target Board Serial Writer Connection Pin Description VPP 5 0 V power supply supplied from serial writer VDD 3 3 V external power supply VDD for level detection VDD level detection pin for target board RST Reset SBT Serial interface clock supply SBD Serial interface data supply GND Ground VDD detects the VDD level on the target board using the serial writer If the VDD level is not satisfied the serial writer outputs an error message The serial writer supplies VPP VPP for the serial writer and VPP for external power source for operation should be selected using switch RST outputs microcontroller reset Connect pullup resistors to RST SBT and SBD on the target board The pullup resistor value is 10 KQ 1 RST SBT and SBD are output from the serial writer through an open collector MN102HF55G Clock on the Target Board Use the existing clock on the target board for the clock supply to the MN102HF55G on the target board Because of this the clock frequency of the M
541. this set the KIIR flag of the external key interrupt control register KIICL to 0 the KILV2 0 flags of the external key interrupt control register KIICH to the interrupt level 0 to 6 and the flag to 1 6 Enable interrupts by writing the IE flag of PSW to 1 and the IMn flag to 7 bit setting 111 Thereafter an interrupt occurs when one of any keys is pushed Interrupt Service Routine 7 Specify the interrupt group by reading the IAGR register during interrupt prepro cessing 8 Execute the key interrupt service routine 9 Clear the KIIR flag of the KIICL register 10 Execute the key determination routine 11 Return to the main program with the RTI instruction after the interrupt service routine ends Key Determination Routine 12 Write 0 to the port 3 output register bit setting 11100000 set 0 to only P34 13 The bit corresponding to the port 3 input register P3IN becomes 0 if any one of keys 0 4 8 C Check with the bit test instruction BTST 14 Write x DO to the P3OUT register bit setting 11010000 set 0 only to P35 15 The bit corresponding to the port 3 input register P3IN becomes 0 if any one of keys 1 5 9 D Check with the bit test instruction BTST 16 Write x BO to the PSOUT register bit setting 10110000 set 0 only to P36 17 The bit corresponding to the port 3 input register P3IN becomes 0 if any one of keys 2 6 A E Ch
542. tination pointer incre ment or source pointer incre ment is selected the pointer in crements by 1 in byte access and by 2 in word access The AT2IQ 3 0 bits are cleared to 0 by the ATC2 transfer end in terrupt Chapter 11 Appendix A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AT2CNT AT2 AT2 AT2 AT2 AT2 AT2 AT2 AT2 AT2 AT2 AT2 0 0 2 2 CNTLICNT10 CNT9 CNT8 CNT7 6 5 4 CNT3 2 x R W R W R W R W R W R W R W R W R W R W R W R W ATC 2 Transfer Word 0 0 0 0 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 0 0 0 on on on on Count Register 16 bit access register AT2CNT sets the bytes to be transferred subtracted by 1 Decrement by 1 every time 1 byte data is transferred and reach x OFFF when the transfer is completed This register writes only 16 bit data Use the MOV instruction to set the data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AT2SRC 2 2 AT2 AT2 AT2 AT2 AT2 2 AT2 AT2 0 0 F D 2 4 SRCISISRCIASRCI3SRCI2SRCIISRCIO SRC9 SRC8 SRC7 SRC6 SRCS SRC
543. to VDD or VSS The output pins leave open The lack of this handling causes the increase of current and unstable operation Table 1 4 1 List of Pin Functions 1 26 Pin Number Pin Name yo Function Description 17 There four pins The mask ROM chip 22 VDD E Power MN102H55D 55G must connect these four pins to a 66 Vpp VPP 2 power supply of 3 0 to 3 6 The flash chip 83 x Power MN102HF55G must connect pin 66 to a power supply of 4 5 V to 5 5 V because the pin 66 becomes the power pin for the flash ROM programming During the normal opera tion the pin 66 must be input the same voltage of other pins 19 Vss Power Ground There are two Vss pins They must be connected to a 92 Vss Power Ground power supply of 0 V 34 AVDD Analog Voltage There is one It must be connected to the same volt age as VDD 61 AVss Analog Voltage There is one AVss It must be connected to the same volt Ground age as Vss 43 Vref Analog Basic There is one Vref It must be connected with relation of Voltage Vss lt Vref lt Vref lt VDD 54 Vref Analog Basic There is one Vref It must be connected with relation of Voltage Vss lt Vref lt Vref lt VDD 22 MN102H55D 55G F55G Chapter 1 General Description Table 1 4 1 List of Pin Functions 2 26 Pin Number Pin Name Function Description
544. top Stop STOP1 2 1 0 1 1 Stop Stop Stop Stop Figure 10 1 2 Operating Mode Control and Clock Oscillation On Off Table 10 1 1 Watchdog Interrupt Interval Watchdog Interrupt Expected Return WDMI YEDMD Interval BOSC Signal Time from STOP 27 1 21x 27x 25 l foscl 213 Cycles 23 x l foscl 25 Cycles 25x l foscl WDM bits reduce the oscillation stabilization wait time from STOP mode When both WDMI and WDM0 are 0 the expected oscillation stabilization time is calculated as follows Oscillation stabilization wait time tosciw of the oscillation frequency fosci is 2 x 1 fosci For example tosciw 3 85506 ms when fosci is 34 MHz tosciw 55G 10 1 3 Transferring between SLOW Mode NORMAL Mode The MN102H55D 55G F55G has two CPU operating modes NOR MAL and SLOW The CPU needs to go through IDLE mode when switching from SLOW mode to NORMAL mode The system clock monitor flag OSCID finds out whether the system clock for the existing peripheral function is the high speed oscillation clock or the low speed oscil lation clock Setting OSCID to 0 means that the high speed oscillation clock is se lected while setting OSCID to 1 means that the low speed oscillation clock is selected Transferring from NORMAL mode to SLOW mode The CPU can switch from NORMAL mode to SLOW mode by setting only the CPU mo
545. trol Register NMICR No vector exists WDICR when interrupt occurs UNICR Group 4 Maskable Interrupt Controller Maskable Interrupt Control Register Maskable interrupts Max 240 vectors Peripheral interrupts External pin interrupts Group 63 Maskable Interrupt Controller Maskable Interrupt Control Register The hardware configuration of the interrupt controller depends on the model Interrupt AW 8 MN102H55D 55G F55G Figure 1 1 3 Interrupt Controller Configuration The CPU checks the processor status word to determine whether an interrupt request is accepted or not If an interrupt is accepted automatic servicing by hardware starts and the program counter and PSW are pushed to the stack Next the program moves to interrupt searches the interrupt vector and branches to the entry address of the inter rupt service routine for that interrupt Interrupt preprocessing Push registers branch to entry address etc Main program 080008 Interrupt service routine Resets interrupt vector at the beginning Hardware processing JMP etc Max 6 machine cycles 7 machine cycles Figure 1 1 4 Interrupt Servicing Sequence Chapter 1 General Description 1 2 Basic Specificat
546. truction to set the data and only use 16 bit write operations The timer 8 binary counter TM8BC is stopped and TM8BC register and RS F F are initialized cleared to 0 1 If this setting is omitted the bi nary counter may not count the first cycle Do not change to any other operating modes 168 MN102H55D 55G F55G Timer 8 Setting 1 Set the operating mode in the timer 8 mode register TM8MD Set counting stop The count direction is up when TM8IOA is 1 while the direction is down when TMSIOA is 0 Select BOSC 2 as the clock source Set the TM8BC count range to 0 to TM8CA TM8MD x 00FE80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM8 TM8 8 8 TM8 8 8 8 TM8 8 8 TM8 8 TM8 EN NLD UDI UDO TGE ONE MDI MDO ECLR LP ASEL 52 SI SO 0 0 1 0 0 0 0 0 0 1 100 0 1 1 2 Set the timer 8 looping value to the TM8CA register the valid range 1 to x FFFE The TM8BC counter counts from 0 to x FFF when writing x 1FFF to the TM8CA register 8 x 00FE84 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 8 8 8 8 8 8 8 8 TM8 8 8 8 8 TM8 CA14 CAI3 12 10 CA9 CA6 CAS CA2 CAO 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
547. ts the timing of changing the PWM waveform output from pin from low level to high level The valid range for TM13CB is 1 to TM13BR TM14 CA7 TM14 CA6 TM14 CA5 TM14 CA4 TM14 CA3 TM14 CA2 TM14 CA1 TM14 CA0 R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TM14 CB7 TM14 CB6 TM14 CB5 TM14 CB4 TM14 CB3 TM14 CB2 TM14 TM14 CBO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Chapter 11 Appendix TM14CA x OOFEOB Timer 14 Capture A Register 8 bit access register TM14CA sets the timing of changing the PWM waveform output from TM140A pin from low level to high level The valid range for TM14CA is 1 to TM14BR TM14CB 1 Timer 14 Capture Register 8 bit access register TM14CB sets the timing of changing the PWM waveform output from TM14OB pin from low level to high level The valid range for TM14CB is 1 to TM14BR MN102H55D 55G F55G 467 Chapter 11 Appendix 15 13 11 15 15 15 14 15 13 15 12 15 CAII 15 CA10 15 9 15 CA8 15 7 15 CA6 15 CAS 15 4 15 15 2
548. up resistor Refer to Chapter 8 Ports TM7IO y o Timer 7 Input Output This pin can be used as a timer 7 input output pin Refer to Chapter 4 Timers SBOS3 Output Serial Interface 3 This pin can be used as a data output pin for serial inter Data Output face 3 Refer to Chapter 5 Serial Interface SDAS3 Serial Interface 3 This can be used as data input output pin for Data Input Output serial interface 3 Refer to Chapter 5 Serial Interface 53 P85 yo General purpose Port 85 This pin can be used as a general purpose input output port The input output direction is controlled in bit units The pin has a built in software control pull up resistor Refer to Chapter 8 Ports TM9IOA Timer 9A Input Output This pin can be used as a timer 9 input output pin Refer to Chapter 4 Timers SBO2 Output Serial Interface 2 This pin can be used as a data output pin for serial inter Data Output face 2 Because pin 15 has the same function either pin 15 or pin 53 must be selected Refer to Chapter 5 Serial Interface SBT4 Serial Interface 4 This pin can be used as a synchronous transfer clock signal Clock Input Output input output pin for serial interface 4 Refer to Chapter 5 Serial Interface SCL4 Output Serial Interface 4 This pin can be used as clock signal output pin for serial interface 4 Refer to Chapter 5 Serial Interface 42 MN102H55D 55G F55G Chapter 1 General Description Tab
549. upt handler start address I 128 Kbytes x 080008 gt ae 1 x 0A0000 2 Reserved x 200000 External Memory xFFFFFF Y Note Parameters on the right table 1 2 3 4 differ on each chip model MN102HF55G 128 KBytes x0A0000 4096 Bytes x 009000 MN102H55G 128 KBytes x 0A0000 4096 Bytes x 009000 MN102H55D 64 KBytes 090000 4096 Bytes x 009000 Figure 1 1 2 Address Space Memory Expansion Mode Table 1 1 1 Memory Modes ROM Capacity Address Bit Width External Memory Access Mode i chi Not accessible Single chip mode 64 k 128 kbytes Memory expansion mode Processor mode Up to 24 bits None Accessible MN102H55D 55G F55G Chapter 1 General Description Interrupt Controller The interrupt controller allocated to the outside of the core controls all nonmaskable and maskable interrupts except reset Each class has up to four interrupt vectors and specifies any of seven priority levels Interrupt Enable nterrupt Masking i Maskable Interrupt Nonmaskable Interrupt Reset Receive Receive Receive lt Reset A Interrupt Controlle Nonmaskable interrupts 4 External NMI pin input Watchdog timer Undefined instruction Groups 0 to 3 Nonmaskable Interrupt Controllers Nonmaskable Interrupt Con
550. utine determines the interrupt group and factor and clears TM8BIR flag 6 Calculate the signal width Save the TM8CA value and the TM8CB value to the data registers DRO to DR3 and subtract the TM8CA value from the TM8CB value The width will be calculated correctly even if the TM8CA value is greater than the TM8CB value by setting TM8LP to 0 Figure 4 4 12 shows 000A 0007 0003 or 3 cycles Timer 8 functions as a one phase capture input Select up counting Timer 8 does not operate stably when BOSC stops in STOP mode All external inputs are sampled on BOSC synchronized with BOSC when the external clock operates The TM8CA register is captured on the rising edge of TM8IOA pin and the TM8CB register is captured on the rising edge of TM8IOB pin A capture B interrupt is generated on the TMSCB capture and the TM8CA and TM8CB values are read during the interrupt processing routine Figure 4 4 12 shows 000A 0007 0003 or 3 cycles The same result is obtained even if the TM8CA value is greater than the TM8CB value For example 0003 FFFE 0005 The signal width is calculated by ignoring flags Chapter 4 Timers TM8EN ea ed TM8BC 1 2 31415 6 7 9 BOSC 2 rT rat TM8CA 0 7 TM8CB 0 A TM8I0A s
551. ve edge from the exter nal interrupt pin IRQO PAO On reset all bits of the external interrupt condition setup register IRQTRG are set to 0 and the IRQOIR flag of the external interrupt 0 control register IQOICL is set to 0 PO CORE D A Converter 6 P1 Interrupt A D Converter P7 P2 8 bit Timers Serial I F 8 16 bit Timers 4 e amp btPwM ETC Pin P5 Pulse Width Counter Figure 3 2 1 External Pin Interrupt Block Diagram Interrupt Enable Setting 1 Set the interrupt conditions for the IRQO PAO pin In this example set IQOTG 1 0 of the IRQTRG register to 2 bit setting 10 IRQTRG x 00FCBO 104 104 103 103 IQ2 102 IQ1 IQ1 100 IQO TG1 TGO TG1 TGO TG1 TGO TG1 TGO TG1 0 0 0 0 0 0 0 0 1 0 2 Enable interrupts after clearing all prior interrupt requests To do this set the IQOIR flag of the external interrupt 0 control register IQOICL to 0 the IQOLV 2 0 flags of the external interrupt 0 control register IQOICH to the inter rupt level 0 to 6 the IQOIE flag to 1 IQOICL 00 50 IQOICH x O0FC51 71615 4 2 71615 4
552. visor of 49 using timer 0 and divisor of 4 using timer 5 Chapter 5 Serial Interface MN102H55D 55G F55G 203 Chapter 5 Serial Interface This setting is unnecessary after a reset Setting TMOEN and TMOLD to 0 is required between 3 and 4 in the bank address version and the linear address version but this setting is not required in the linear address high speed ver sion 1 Do not change the clock source once you have selected it Selecting the clock source while setting the count operation con trol will corrupt the value in the binary counter 204 MN102H55D 55G F55G Timer 0 Setting 1 Set timer 0 counting stop with the timer 0 mode register TMOMD TMOMD x 00FE20 TMO TMO TMO TMO EN LD 51 50 0 2 Set the timer 0 divisor Since timer 0 divides BOSC 2 by 49 set the timer 0 base register TMOBR to 48 x 30 The valid range for TMOBR is 0 to 255 TMOBR 00 10 TMO TMO TMO TMO TMO TMO TMO BR7 BR6 BRS BR4 BR3 BR2 BRI BRO 0 0 1 1 0 0 3 Load TMOBR value to the timer 0 binary counter At the same time select BOSC 2 as the clock source TMOMD x 00FE20 7 6 5 4 3 2 1 0 TMO TMO TMO TMO EN LD S1 50 0 1 0 0 4 Set TMOLD and TMOEN of the TMOMD register to 0 and 1 respectively This starts the time
553. ws only byte T accesses Use instruc tion to set the data MN102H55D 55G F55G 349 Chapter 11 Appendix 7 6 5 4 3 2 1 0 ITMIU IR ID R R R R W R R R R 0 0 0 0 0 0 0 on o 0 1 4 Timer 1 Underflow Interrupt Request Flag 0 Timer 1 Underflow Interrupt Detect Flag 7 6 5 4 3 2 1 0 2 s IE R R R R R R R R W 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Timer 1 Underflow Interrupt Enable Flag 350 MN102H55D 55G F55G 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected 0 Disable 1 Enable TM1UICL x O0FC5A Timer 1 Underflow Interrupt Control Register 8 bit access register TM1UICL requests and verifies a timer 1 interrupt This register allows only byte accesses Use MOVB instruc tion to set the data TM1UICH x OOFC5B Timer 1 Underflow Interrupt Control Register 8 bit access register TM1UICH enables a timer 1 in terrupt This register allows only byte accesses Use MOVB instruc tion to set the data The inter rupt level is the same level set in the IQ1LV 2 0 bits of the IQ1ICH register Chapter 11 Appendix s ad B UD pes x OOFC5C Timer 8 Capture Interrupt Control Register 8 bit acc
554. x OOFFDB Port B Input Register 8 bit access register PBIN reads the port B data DIR6 DIRS DIR3 DIR2 DIRI DIRO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port 0 Input Output 0 Input 1 Output Pl DIR7 DIR6 DIRS DIR3 DIR2 DIRI DIRO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port 1 Input Output 0 Input 1 Output 2 2 2 2 2 2 2 2 DIR6 DIRS DIR3 DIR2 DIRI DIRO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port 2 Input Output 0 Input 1 Output P3 P3 DIR7 DIR6 DIRS DIR4 DIR3 DIR2 DIRI DIRO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Port 3 Input Output 0 Input 1 Output Chapter 11 Appendix PODIR x OOFFEO Port 0 Input Output Control Register 8 bit access register PODIR controls the port 0 input output P1DIR x OOFFE1 Port 1 Input Output Control Register 8 bit access register P1DIR controls the port 1 input output
555. xternally or set the pin to input For input pins high or low level is fixed externally Chapter 10 Low power Modes MN102H55D 55G F55G 287 Chapter 10 Low power Modes 1 The CPU transits from NOR MAL mode to HALTO mode and from SLOW mode to HALT1 mode 2 The CPU transits from NOR MAL mode to STOPO mode and from SLOW mode to STOP1 mode program changes the oscil lation stabilization wait time The oscillation stablization wait time is 277 at reset The time for error detection function changes as a result of the oscillation stablization wait time change 1 Set only 00 the WDM flags the MN102HF55G 288 MN102H55D 55G F 10 1 2 Control Registers The CPU mode control register CPUM controls each mode transition CPUM 00 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WD WDM WDM 0 0 0 0 0 0 0 DSCIDSTOPHALT OSC1 OSCO RST 1 0 Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 System clock monitor flag EMT d uM Operating OSCI System Mode STOP HALT OSC1 OSCO OSCO XI XO Clock CPU NORMAL 0 0 0 0 Oscillation Oscillation OSCI OSCO Operation IDLE 0 0 0 1 Oscillation Oscillation XI XO Operation SLOW 0 0 1 1 Stop Oscillation XI XO Operation HALTO 1 0 1 0 Oscillation Oscillation OSC OSCO Stop HALT1 1 0 1 1 1 Stop Oscillation Stop STOPO 2 1 0 0 0 Stop Stop S
556. y bit is even although it is set to odd Parity error data is updated whenever the parity bit is received 3 A framing error occurs when the stop bit is 0 Framing error data is updated whenever the stop bit is received 4 Do not use the SCnRBY flag to set polling for the received data wait in clock synchronous mode Use the interrupt service routine the serial interrupt flag or the SCnRXA flag MN102H55D 55G F55G 191 Chapter 5 Serial Interface SCnCTR 15 14 13 2 10 9 8 7 6 5 4 3 2 1 0 SCn SCn SCn SCn SCn SCn SCn SCn SCn TEN REN BRE IIC PTL OD ICM LN PTY2 PTY1 PTYO SB 1 0 Reet 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 SCnS 1 0 Clock Source Selection For Serial 0 1 For Serial 2 3 For Serial 4 00 SBTn pin SBTn pin SBTn pin 01 Timer 1 underflow 1 8 Timer 4 underflow 1 8 Timer 1 underflow 1 8 10 Timer 2 underflow 1 2 Timer 5 underflow 1 2 Timer 5 underflow 1 2 11 Timer 2 underflow 1 8 Timer 5 underflow 1 8 Timer 5 underflow 1 8 Some selections cannot be made in each mode asynchronous synchronous l C Please refer to list of special registers in appendix for setting Always select 1 8 of clock in asy
557. ycles 100 2 5 cycles 101 3 cycles 110 3 5 cycles 111 4 cycles Chapter 11 Appendix MEMMD x OOFF84 Memory Mode Setup 2 Register 16 bit access register MEMMD2 sets the burst ROM cycles and changes the pulse timing of WEH WEL and RE MN102H55D 55G F55G AT Chapter 11 Appendix 15 14 13 12 n 10 9 8 7 6 5 4 3 2 1 0 DRAMMD1 ARE ARE MMD MMD ASEN SEL SEL SEL CAS CAS CAS RAS RAS RAS 1 3 2 1 0 1 0 2 1 0 2 1 0 2 1 0 x OOFF90 R W R W R W R W DRAM Control 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 on Register 16 bit access register 15 DRAM Operation 0 Disable DRAMMD1 sets the DRAM for External Memory Space 3 1 Enable modes 14 DRAM Operation 0 Disable Please refer to Figure 2 1 1 for External Memory Space 2 1 Enable Address Space on page 52 for address allocation of external 13 DRAM Operation 0 Disable memory spaces for External Memory Space 1 1 Enable 12 DRAM Operation 0 Disable for External Memory Space 0 1 Enable n MMD 1 0 Setti 00 01 10 11 10 Shift Size of DRAM Address 00 8 bit eung ME Sut 01 9 bit Pin Name ROW
558. yte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the IQ3LV 2 0 bits of the register Chapter 11 Appendix A NR UU TM10UICL SE t x O0FC6C Timer 10 Underflow 0 Interrupt Control Register 8 bit access register Timer 10 Underflow Interrupt 0 No interrupt requested TM10UICL requests and veri Request Flag 1 Interrupt requested fies a timer 10 interrupt Timer 10 Underflow Interrupt 0 No interrupt detected This register allows only byte Detect Flag 1 Interrupt detected accesses Use the MOVB in struction to set the data E TM10UICH i TM10UI IE x OOFC6D SNL RUE E URL n S Timer 10 Underflow 0 0 0 0 0 0 0 1 Interrupt Control Register 8 bit access register Timer 10 Underflow Interrupt 0 Disable Enable Flag 1 Enable TM10UICH enables a timer 10 interrupt This register allows only byte accesses Use the MOVB in struction to set the data The in terrupt level is the same level set in the IQ3LV 2 0 bits of the IQ3ICH register MN102H55D 55G F55G 359 Chapter 11 Appendix 7 6 5 4 3 2 0 IR ID R

MN102H55D/55G/F55G LSI User`s Manual

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