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Stellaris LM3S9B96 Development Kit User`s Manual (Rev. F)

Contents

1. 5 4 3 1 Primary EM header 3V 32KHz clock for BT boards M ks 3 3V CC P1 CC P2 3 3V p Di mm J2 J1 MOD1 SDIO DO B2 02 2 125 INSTALL RESISTOR R7 WHEN 2nd RFMON SDIO MOD MART STS ES E DS 1 LI 1 MODI 5010 01 B4 D4 MOD1 AUD L MOD1 AUD 2 MODULE NEEDS 32KHz Clock 27007 SDIO MOD SLOWCLK B5 04 05 MODI AUD FSYNC 3 je e MODI SDIO MODI SDIO D2 85 05 06 MOD1 AUD ANA MODI AUD DATA IN 34 SEC MOD R7 0 4MOD1 500 03 MOD UART B7 D7 AUD DATA OUT 5 9 D 48 8V MOD1_SDIO_D3 B8 87 lt 07 08 7 MOD1 AUD DATA OUT ul D 5 1 TX 89 8 4 X 08 DS MOD SLOWCLK 8 0 1 Tour vec i MODI Bo Dann Di0 MOD AUD DAT
2. D P 0 Revision Date Description He TIO 0 A 6 24 2009 Released for manufacturing ug 50 EPH4 116 35 2 EPH3 117 10 1026 0 gt 8 19 2009 Changed camera connector P1 to vertical connector lt Al SDA 4 45 3 _ 122 10 104p Q GCLK4 5 Board width increased by 110mils Added test pads EPIS 27 4 PGI EPH4 1985 pant 46 5 PHT EPI27 EPI20 125 Released for manufacturing EPIS 45 6 PJO EPIT6 EPIS 125 TO 105 D GCLK6 24 7 21 EPI29 196 1 L 43 8 PD2 EPI20 EPI20 1 128 8 I2CSDA 42 9 PJ6 EPI3O EPI30 PXLCLK 1 dau 21 10 PUS EPI29 29 28 20 1l 2 28 EPIO 29 12
3. 45 LGD Eatch Register cie ER tu E oe otia P oe rd hi hee 45 FPGA Expansion Board Memory 54 Version c M M 55 System Control 56 Interrupt Enable 57 Interrupt Status Register oie Fere re reet Dan eter heel Aa tenis 57 Tost Pad ROOSE pee b me Ree e eed eno notes 58 ECD Gontrol Register tror no ti er ep ta 59 EPI Signal Descriptions A epee 63 EPI 5 Descriptioris d 75 September 5 2010 Stellaris LM3S9B96 Development Board Overview The Stellaris LM3S9B96 Development Board provides a platform for developing systems around the advanced capabilities of the LM3S89B96 Cortex M3 based microcontroller The LM3S9B96 is a member of the Stellaris Tempest class microcontroller family Tempest class devices include capabilities such as 80 MHz clock speeds an External Peripheral Interface EPI and Audio 125 interfaces In addition to new hardware to support these features the DK LM3S9B96 board includes a rich set of peripherals
4. Revision History MAD 0 27 0 Revision Date Description Ti VF A 5 29 2009 Released for manufacturing 33V 1 FLASH B 7h7 2009 Changed J2 to top entry moved to bottom Added R9 R11 PC4 EPI2 25 3 PGO EPI13 MA13 MAD3 47 4 25 129 MADO PC6 EPIA 46 5 27 27 MA2 24 DO 31 MADI MAD5 PC7 EPI5 45 6 PJO EPI16 MA16 23 paz 33 MAD2 44 7 121 21 22 535 MAD3 l I2CSCL 43 5 2 20 2l pos 38 MAD4 5 12CSDA 42 9 PJ6 EPIB0 ALE MAG 20 40 MADS Al SDA 5 do IN R al 5 29 MAT 19 5 pos 52 MADS A 40 28 18 44 MAD7 AT 8 0 39 119 MA9 8 GND 2 8 138 PES EPI2S 7 30 Note R1 is not fitted A9 24 01 37 PEQ EPI24 poo 32 1 128X8 7 PG7 EPIS1 36 PBA EPI23 33V 12 5 22 18 35 16 PBS EPI22 4 pon 38 gt 15 PFS EPHS 34 17 7 4 3 pon 39 33 18 PHO EPIG MAD6 dra MAIS 2 pais dl 32 19 PHI EPI7 MAD7 10K 16 1 A15 43 9 31 20 2 MADI 48 Aie 1541 1525 33V MAB 30 21
5. Figure 2 1 Factory Default Jumper Settings 75 g u8 c50 5V zr 5 054 LED2 amp T C gs 2e ES 5 5 CAN USB 087 m qx 057 us Beene 854 052 R30 ell Lp 1 QJ 2 ro 5 SBSSSFRBEBBSE b ESL e 2 HM ale sssesesresi g 2 182 B 3 gt lt 5 N rra sj RSS zd wm 125 AUDIO 5 OTHER 5 5 E UNE OUT ESPPpPPPSEE TUM Ri PAT TXD 8 RIT UM RXD 022 45V VCAN 6552 ceon m USB HOST DEVICE OTG ul PBI as amp 88 8 EXTERNAL PERIPHERAL INTERFACE PBO 0160 w EPEN oa E PA7 p C36 1040 5 LUMINARYMICRO 5 P LM3S9B96 d DEVELOPMENT BOARD F PF2 LED ETHERNET PF3 gp2 LED2 8 R9 Ts C26 VDD 82 DEBUG n Eg INTERFACE H 5 ES E 4 as 2E 3 3V seve e E 5 05 Ji VREF 3 00V 9653 PB4 e LED REN Y 5 2225 2 LED SERIAL FLASH 2 USER 8 13 SD CARD SWITCH 8 18888858882 232228 amp s22285 QVGALCD p see lt 555 32 29 o 188 v 828 Swi 118 1 188 3 00VREF 8800 02
6. EPI Connector i MA 7 EPI 7 0 MAD 7 0 7 0 MA 27 8 EPI 27 8 dio MA27 5 28 9En EE S Ep129 NEn NENNEN D MA26 1 MA27 WE LCD DECODE CD Control ___ gt LCD de Connector Functional Description The Flash and SRAM memory expansion board schematics are described in this section The first page of the schematics shows the memory devices and address latch part of the design The second page shows the LCD I F and regulator Flash SRAM Schematic 1 on page 47 Page 1 of the schematics shows the EPI connector address latch and memory devices EPI Connector The EPI connector J1 is a 50 pin receptacle with 0 5 mm pitch that plugs into the EPI header on the DK LM3S9B96 board The 32 EPI signals and the 2 ICO signals from the LM3S9B96 are provided on this connector It also provides 5 V for the on board DC regulator Note that not all EPI signals are used in this design September 5 2010 43 8 bit Latch This 8 bit latch is used to store the lower 8 bits of the address which are transmitted during the address phase of an EPI transfer The EPI must be configured in Host bus 8 mode 0 mode HB8 ADMUX with EPI30 configured as an Address Latch Enable ALE signal to control this latch Flash Memory The Flash memory used is a 64 Mbit 90 nsec Spansion S29GLO64N90TFI040 This 8 16 bit memory is
7. Designer Drawing Title Araldo Cruz FLASH SRAM LCD IF board for DK LM3S9B96 Drawn by Page Title Arnaldo Cruz FLASH SRAM Approved Size Document Number Rev 0001 Date 7 21 2009 Sheet 1 of 2 gt 6 6 LCD DECODE CPLD A10 B10 All B11 A12 B12 A13 B13 Al4 B14 15 15 1 CLKO INO CLK2 IN2 CLK3 IN3 CPLD TCK CPLD TMS TP1 TP2 CPLD TDI TDI CPLD 5 3 TMS TP6 TDO GNDO0I GNDII GNDI C2 C3 C7 C13 GND2 0 tuF 0 tuF 0 1uF LC4032V 5v P U4 l vour 3 2 GND NR 4JuF TPS73033 GREEN LED SMT Socket 2x17 LCD I F Texas INSTRUMENTS Drawing Title FLASH SRAM LCD IF board for DK LM3S9B96 Page Title LCD Interface Size Document Rev B B Date 7 18 2009 Sheet 2 o 2 6 Stellaris LM3S9B96 FPGA Expansion Board This chapter describes the FPGA expansion board for the DK LM3S9B96 development board The FPGA expansion board provides a quick start platform to evaluate the capabili
8. 72 Figure G 6 Fully Assembled DK LM3S9B96 Board with EM2 Expansion Board and Wireless EM Module 73 Figure G 7 EM2 Expansion Board Block 74 Figure G 8 Component Placement Plot for Top and 77 September 5 2010 5 List of Tables Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Table C 1 Table D 1 Table E 1 Table E 2 Table F 1 Table F 2 Table F 3 Table F 4 Table F 5 Table F 6 Table F 7 Table F 8 Table G 1 Board Features and Peripherals that are Disconnected in Factory Default Configuration 13 SB Related Signals iot no eere 15 Hardware Debugging 16 Debug Related Signals i eet erret n neto ri exte Do aite E e PE io 17 GD Related Signals 2 5 a a e ob E en ee re dier EE TUS 18 eS Audia RelatedGIghalsa obit 19 Navigation Switch Related 19 Debug Interface Pin Assignments 35 Microcontroller GPIO 37 Flash and SRAM Memory Expansion Board Memory
9. VCCINT _3 VCCINT 1 105 3JLHCLK2 2 IO 105 3 LHCLKS IRDY2 10_LO6P_3 LHCLK4 TRDY2 1O_LO6N_3 LHCLKS IO LO3P 3 i N IO 3 10 104 i LO4N 3 LECLKI XC3S100E 4TQGI44C 10 L07P NILHCLK6 10_LO7N_3 LHCLK7 10 108 3 MAS 10 LORN 3 MAT 10 109 3 MAB 10 109873 10 LI0P 3 10 LION 3 MATI 0 2 MATS XC3ST00E ITQGI44C MATS 16 17 MATS MATS 20 MOS n 8 MOE n MWE n 15 C4 _ 5 e C6 ursi ISGIWVIO2S IMx8 5 TMS NC P TCK NC 28VD TDI NC uu EN VCCINT 5v 28VA 3 3uH VCCI Ri XCFOIS 0 033 Mbit 28V 33V UIF DONE 1 nile lt PROG B FEDN338P ib s 144 e 4 7uF 4 TDI LI 109 LIN Di 199 4 579228 D HU C10 GREEN TMS 0 tuF XC3STO0E ATQGT44C 5v eue A TX 68u 8 ap 20 c2
10. 4 eis 68uF plene i TEXAS INSTRUMENTS Drawing Title AD TR 68uF FPGA board for DK EPI Xilinx JTAG 6 C19 C20 C21 P Title 1500pF 1500pF 1500pF 10uF age Title 4 Power JTAG Size Rev B B Date 8 20 2009 Sheet 2 o 32 68 September 5 2010 APPENDIX Stellaris LM3S9B96 EM2 Expansion Board This document describes the Stellaris amp LM3S9B96 EM2 Expansion Board DK LM3S9B96 EM2 for the DK LM3S9B96 development board The EM2 expansion board provides a transition between the Stellaris External Peripheral Interface EPI connector and the RF Evaluation Module EM connector DK LM3S9B96 EM2 enables wireless application development using Low Power RF LPRF and RF ID evaluation modules on the Stellaris DK LM3S9B96 platform Figure G 1 EM2 Expansion Board Features The DK LM3S9B96 EM2 expansion board has the following features 2 sets of EM connectors to support up to 2 RF evaluation modules 1 kilobit of C memory for storing configuration data and EM2 expansion board detection EM digital and analog audio signal headers EM MOD1 SDIO connection headers 32 Khz oscillator for slow clock source to primary EM2 expansion board connector Installation To install the EM2 expansion board on the DK LM3S9B96 development board do the following 1 On DK LM3S9B96 board shown in Figure G 2 on page 70 remove any installed board on EPI connector J2
11. 9 EPO 25 TO LOEN ONREF 38 13 PESEPI25 25 L RSTn 0 dau sv 37 14 2 24 24 PWDN Sern 1 7 36 15 PB4 EPI2S EPI23 XVCLK PJP EPIT8 16 PBS EPI22 22 TO LION SWAP 5 17 7 Breve 2 18 PHO EPIG EPI6 35100 2 00144 5 FID3 19 HEP 2 1p 40 Mil Pad 40 Mil Pad 40MilPad on SI PHEEPI EB 40K 5290 paka op 6 PWDNR 100 Mask 100 Mask 100 PEO EPIB 21 d ees e e e 22 PHWEPI0 EPIO gt 10 i PHG EPI26 po IO 101 A16 20E DN m EE U7 4 x 4 8 40 Mil Pad 40 Mil Pad 40 Mil Pad 33V 10 102 Z C50 100 Mil Mask 100 Mil Mask 100MilMask SCLI SCL2 IO 1023 lt SDAI SDA2 28VD 33V IO LO3P e 4 IO LO3N e LS EN VREFIL 10K 10 IO VREF 1 VREF2H 4 T 10_L04P_1 A10 RHCLKO E 10_LO4N_1 A9 RHCLK1 iducials PCAS306 1823 624 LL our any 10_LOSP_1 A8 RHCLK2 5 4 10_LOSN_I A7 RHCLK3 TRDY1 GND VDD ie 10_LO6P_1 A6 RHCLK4 IRDY 1 10 1063 I AS RHCLKS 10 107 I A4 RHCLK6 1073 I A3 RHCLK7 IO LO8P 1 A2 IO IO AO 10_L09P_1 HDC 10_LO9N_I LDCO UIE 10_L10P_1 LDC1 IO LION
12. 53 24 MLEIZ OsSeCIIIAtOl edet tee oa eae esu i is ot antec 53 External Peripheral Interface EPI 53 Using the Widget 53 Writing Your Own Stellaris 53 MINUTE AEA E AASR ALATE 54 Register Descriptions ec rt better n E e ee paa debuts eb Eee 55 Loading New Image to the 61 Installing the SoftWafe aen e heb eie ee i E eere 62 Modifying the Default 1 62 Default FPGA Image eaaa 62 Signal Descriptions ped Rate pter oe tet n ee oe eae ee 63 Component LOCATIONS coerente tete eren ir nce te set epu ro 64 OI EUER IEEE 65 Appendix Stellaris amp LM3S9B96 EM2 Expansion 69 gucci 69 S 69 Installation of EM Modules the EM2 Expansion
13. 0 MADO MAIS 17 10 29 22 __16 is 15 R2 10K MA26 26 28 23 MA10 MA20 9 27 24 MAZ 10 50 a 726 22 13 TP8 27 26 DFI2A 50DS CE 294 E MOEn 28 GF 10K MWEn 1L Wr 1 RP vP 5 BYTE 3 MAO vas MADi 4 37 _ 7 2 VSS veg MAD3 8 Te 13 MA4 S29GL064N MADS i4 MAS 64Mbit MAD6 17 MAG MAD7 _ 18 u2 SRAM n 54 A0 MADO T 33V RT Al Dal MADI 43 MAD2 2 14 MAD3 10 A3 MA4 1 pos 21 MAD4 Lata 441 5 pos 152 MADS 0 1uF MAG 43 1 25 MADS MA 22 36 MAD7 AE gt AT MA8 39 d 28 7 1 gt A9 NC 5 5 _ 27 8 A10 NC 26 15 252 NC Tis mats 24 12 NC 2 23 13 NC 30 14 H MAIS 22 37 7 gt 15 6 21 38 16 20 417 CERT gt 19 AI8 9 18 Decode Table MA26 6 ipti MA27 30 Device MA 27 26 Description CE2 MOEn _ 41 GF FLASH Flash memory MWEn 17 WE SRAM 10 SRAM memory 12 vss 34 vss Austin LCD 11 LCD Latch Port EXAS I 108 Wild Basin Rd Suite 350 CY62158EV30 NSTRUMENTS Austin TX 78746 8Mbit
14. 72 Hardware Description ioo eint an qae e E eruit dd 74 Primary EM Gade aeo eterne aee xh Deb ren bed pei Hebe a bh Dee teftes 74 Secondary EM EC 75 GAT24601 EEPROM eue ede Quee tt eee ep 75 2S Entiendo decus 75 Analog Feader eee ole ite De Ro moe 75 SDIO Heade si M M 75 EPI Signal Descriptions a a ERRAT ash ERR HB dn 75 Component Locations 2 2 udi dae te pea dart ideas 77 SCMEMAUCS IT 77 Appendix References ct 79 4 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual List of Figures Figure 1 1 DK LM3S9B96 Development 9 Figure 1 2 DK LM3S9B96 Development Board Block 11 Figure 2 1 Factory Default Jumper 14 4 1 ICD Interface Out MOG s ttn ee Eee E 23 Figure B 1 Component Placement Plot for 34 Figure E 1 Flash and SRAM Memory Expansion 41 Figure E 2 Removing E
15. 1l 12 RASn 13 14 15 16 17 DOMI 18 06 19 AD7 20 21 ADO 22 ADIO 23 24 25 DFI2A S0DS SDRAM Expansion Board ADO 23 ADI 24 25 AD3 26 29 ADS 30 ADG 31 ADT 32 ADS 33 AD9 34 ADIO 22 ADIT 35 BA0 DI3 20 21 CSn 19 WEn 16 18 CASn 17 SDCLK 38 SDCKE 37 DOMI 39 DQMO 15 EPI Signal Breakout Board Expansion Connector 15 uo _ 8MB SDRAM AO Al A2 A3 A4 AS A6 AT AB A9 10 11 0 CAS CLK CKE DQMH DQML VSS VSS VSS VSSQ VSSQ VSSQ VSSQ 004 095 097 DQS 209 DQIO DQI2 DQI3 DQI4 DQIS NC VDD VDD VDD VDDQ VDDQ VDDQ VDDQ 2 ADO 4 ADI 5 T ADS AD 10 ADS 13 ADT 42 ADS 45 ADIO 47 48 50 BAU DI3 51 BAI DI4 S DIS 3 3V 3 3 MT48LC4M16A2 jl 50 1 49 2 X_PC4 EPIO2 48 3 X X PCS EPIOG 47 4 X PGI EPII4 X_PCG EPIO4 46 5 X_PH7 EPI27 X PCT EPIS 45 6 X PJU EPIIG 9 24 7 XCPDSEPDI 43 8 X_PD2 EPI20 42 9 X PJG EPI30 21 10 X PIEP 40 11 X PM EPDS 39 12 X 5 138 13 X PEMEPDS o X 5V 37 14 X PEJEPDM o X PGZEPBI 36 15 X PBA EPD3 o X PIJEPIS 35 16 X PBNEPD2 X PES EPIIS 34 17 X 7 5 X PEVEPI2 __33 18 PHO EPIO6
16. Date 4 23 2009 sheet 1 Rev y D QVGA LCD Panel dms microSD Card Slot 433V with touch interface 16 iok iok 8 bit 8080 mode SDCSn aes m R19 9 Reset 10K ILED 2 MOS ES R59 ILED 2 PAS SSIOTX RESETS 3 JP10 SW B3S1000 100 LEDA 4 2908 05WB PA2 SSIOCLK 2006 OSWE MG PESADCI ___ 16 x TOUCH XP XR 6 TOUCH YN 1 YD 7 JP17 TOUCH XN XL 8 PAd SSIORX PEMEPDS TOUCH YU 9 PE2 EPI24 IPIS 10 433V 1 n apie YE lt PE7 ADCO Ed 1 CA R20 LCD_RSTA 14 IUE 10K CSn 15 e 433V PB7 NMI gt L T RB ANY 1220 19 330 100 LDO 20 2 T lt PDO 2SRXSCK IE LCD 1MB Serial Flash wGreen POWer LCD DI LD2 us x PDI DSRXWS LD3 23 433V LD4 24 me lt PD2 EPDO LD5 25 nHOLD VDD den 26 24 27 nWP n LD6 28 FLCSn SCK C25 PD4 12SRXSD LD7 29 PFO nCE 0 1UF 5
17. The LCD Latch register is implemented as a set clear register To set a bit the corresponding bit must be set when writing to the LCD Latch Set register To clear a bit the corresponding bit must be set when writing to the LCD Latch Clear register XN When clear the L_XN signal is set to clear When set the signal is tri stated This signal is used for the X input to the touchscreen YN When clear the L_YN signal is set to clear When set the L_YN signal is tri stated This signal is used for the Y input to the touchscreen RST When clear the L_RSTN signal is set to clear When set the RSTN signal is reset This signal is used to reset the LCD panel September 5 2010 45 Component Locations Figure E 4 shows the details of the component locations Figure E 4 Component Placement Plot for Top and Bottom 90 960 N N i E 13 S pmm c L E 9 5 E 1 780 aem ad Bottom Schematics This section shows the schematics for the DK LM3S9B96 EXP FS8 memory expansion board W Flash SRAM on page 47 LCD Interface on page 48 46 September 5 2010 gt 6
18. 24 01 EEPROM Primary EM Header 74 The primary EM header should always be used when only one EM module is installed unless otherwise indicated in the README First document for the EM module you are installing The primary EM header connects three buses to the EPI connector that are also shared with the secondary EM header These buses are UART1 and SPI NOTE The primary and secondary EM headers have a unique SPI chip select signal but share the data and clock signals The primary EM header contains four GPIO connections to the EPI connector These GPIOs can be used as inputs or outputs depending upon the EM module installed In addition four unique GPIOs are provided to each EM header September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual The primary EM header contains one GPIO connection used to shut down and or reset the EM module The actual function depends on the EM module installed The MODx nSHUTD signal is pulled up to 3 3 V on the EM2 adapter Each header has its own MODx nSHUTD signal The primary EM header contains additional features not found on the secondary EM header including a 32 KHz oscillator input and a header for a 4 bit SDIO module These features are not currently used by the EM modules available today but are available for future expansion Secondary EM Header The secondary EM header should only be used when two EM modules are installed in the system or whe
19. 55 System Control Register The System Control register provides access to configuration bits for the video capture and display system It is implemented as a read modify write register and includes LCD and capture 56 modes Table F 3 System Control Register SYSCTRL 0xA000 0002 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 PCBrA R R R R R R R R W 7 6 5 4 3 2 1 0 VCTES VCQV VSCAL CMKE 1 GA MPRI E N LGDEN LVDEN VCEN R W R W R W R W R W R W R W R W Bit Name Description VCEN Video capture DMA enable Enables video capture to memory Disabling this bit captures the remainder of the current frame and then stops LVDEN LCD Video DMA enable Enables DMA from the video memory region to the LCD LGDEN LCD Graphics DMA enable Enables DMA from the graphics memory region to the LCD CMKEN Chroma key enable VSCALE Video scale control Scales the video during output to the LCD If set the LCD DMA engine skips every other pixel and every other row during LCD video DMA output Graphics DMA is not affected As a result the video object displays at its normal size Memory port row increment If set to 0 any read or write to the memory port auto increments the MPC register at the end of the transfer by 1 If MPC is at the last column MPNR 1 then it sets to 0 and the MPR increments by 1 If the end of the row is reached then it increments by columns If set to 1 any read or wr
20. R60 R11 0 Ohms for LM3S9B96 Rev PIO EPI16 14 PHS EPIOS 1 962 26 EEM PTI EPITT PHGEPIOS26 15 PH7 EPI27 Ethernet 10 100baseT 4 PJI EPIOSI7 0827 T PIZ EPIIS 39 M333V f PJ EPIOSIS R2 50 58 86 128 108 459520 lt 16 5 29 10 10 PIG EPI3O 35 dd Bj gt RESETn 64 RSTn T TXON 4 4 A XTLN 17 40 16 RAIE 1 C21 0 01UF Osco x OSCI RXIN X i 2 R5 R7 C14 C17 HK 3499 8499 25 R3 25 00MHz 16 00MHz 222 Eh RI e C ave 335 EIAS 33v S USBODP EL J3011G21DNL dle TE USBODM 56 es epe 0 1UF 32 v Hi 4 56 c6 cg 0 lt 12 lt 15 T game 00109 0 01UH 0 1UF 0 1UF 2206 History vpp L3 1 Revision Date Description 1 3 293 a Indicates factory default jumper position GND P 15 Apr 09 First production release A a jt I 45 Texas INSTRUMENTS GND 32 GND vomas 389 O 6 Drawing Tite 14359896 Development Board GND VDD25 0 01UR O IUF 2 2UF T Page Title Micro EPI connector USB and Ethern ooo 016 Required only for le IMASE Sie Document Number 1 350896 TE See errata
21. 32 19 X_PHI EPIOT 5 X _ 31 20 X PH2 EPIOI 9 X PEU EPIOS 30 21 X PHS EPIQ0 X PHS EPII 29 22 X PHA EPIIO 5 X PHO EPD6 28 23 27 24 4 26 25 14 M ces C64 65 C66 i 0 01UF 0 1UF 0 1UF 43 1 29 Texas INSTRUMENTS Drawing Tite N3S9B96 Development Board Page EPI and SDRAM Expansion Boards Size Document Number 1 350896 Sheet Date 4 23 2009 5 of 6 A 6 6 Ez 12 11 Debugger USB Interface 5 SN7ALVCI25A ae 54819 0572 R52 U13A 10K SN7ALVCI25A 3 3y USB Device Controller 8 TDI DBGHSV 012 R51 10K U14C b SN7ALVCI25A ADBUSO 5 3V30UT ADBUSI ADBUS2 FL TDO DO ADBUSS TMS OUTEN 6 USBDM ADBUS4 5 rm P FT_SRSTN SN74LVC125A 0 01UF 2 7 DBGENn 3 TMS SWDIO ANN USBDP ADBUS6 ER 4 ADBUS 15 UISA ACBUSO DRUMS B
22. 1 8 0 7 PDS DSRXMCLK 3226 SI vss LDIO 32 2 gt LDII 33 8 W25X80AVSSIG ND 6 PDT JP28 E gt LED PF3 LEDO E HSYNC s 2 aw W UD User LED LDC 433V Ns Green PHT EPI27 29 LRDn RIO lt PBS EPI22 10K JP30 SWI LWRn SWITCH 5 oe e pH o User Switch lt 26 i 1 6 SW B381000 J PAT USBPFLT CANOTX ua 15 TXD CANH ud 1 PAG USBEPE CANORX RXD CANL 3 5 5 VREF 3 0V RS T FPC Socket 60pin ile 9 GND indicates factory default jumper position POT xi2 PBA ADCIO EPI23 gt i SN65HVDIOSOD S m 5 Texas INSTRUMENTS 0 1UF Drawing Tite 111359896 Development Board Thumbwheel Potentiometer Tite CAN Serial Memory User IO Size Document Number p Date 4 03 2009 tect CHR ESSEN 6 6 D 5V DC INPUT 7 ANE PJ 002BH SMT L 3 0V PB6 TXSCK AVREF TP1 3 3 TP3 US JP60 PQILA333MSPQ DBG 5V paren VBUS 5 VIN VOUT 1 ON NR E TP2 o C39 GND a 0 01UF Main 3 3V Supply Power Source Selection
23. A September 5 2010 69 2 DK LM3S9B96 board shown in Figure G 2 confirm that shunt jumpers JP16 JP31 B are installed to enable the LCD touch screen JP39 C the leftmost jumper indicated should remain uninstalled Figure G 2 Removing EPI Board from DK LM3S9B96 Development Board Ei A Remove board sc 29 825 M B Confirm shunt jumpers C Leave JP39 JP16 JP31 installed uninstalled 3 Place the EM2 expansion board on top of the DK LM3S9B96 board while aligning the male EPI expansion connector on the bottom side of the EM2 expansion board with the female EPI expansion connector on the DK LM3S9B96 development board J2 70 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Figure G 3 EM2 Expansion Board Bottom side of EM2 module Male EPI expansion connector gt 3 3 4 Press firmly downward until the board snaps in place Figure G 4 Assembled DK LM3S9B96 Development Board with EM2 Expansion Board EM2 Expansion Board 4 5 INSTRUMENTS www ti com stellaris September 5 2010 71 Installation of EM Modules onto EM2 Expansion Board The EM2 expansion board has a primary EM header MOD1 and a secondary EM header MOD2 as indicated on the silk screen see Figure G 5 The secondary EM header is rotated 180 degrees from the primary EM header There are many types of EM modules that can be
24. Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF IF and ZigBee Solutions www ti com audio amplifier ti com dataconverter ti com www dlp com www ti com clocks interface ti com logic ti com power ti com microcontroller ti com www ti rfid com www ti com lprf Applications Communications and Telecom Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space Avionics and Defense Transportation and Automotive Video and Imaging Wireless TI E2E Community www ti com communications www ti com computers www ti com consumer apps www ti com energy www ti com industrial www ti com medical www ti com security www ti com space avionics defense www ti com automotive www ti com video www ti com wireless apps Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2011 Texas Instruments Incorporated
25. Installing Software To install the software do the following 1 Plug the provided cable into J4 on the right side of the board taking care to ensure proper alignment and orientation The silk screened signal names should match with the exception that 2 5 V corresponds to VDD When correctly aligned the JTAG SPI Full Speed text should face in toward the FPGA Modifying the Default Image This section provides the descriptions for the default FPGA image blocks Default FPGA Image Blocks Configuration Registers The configuration registers are transparently mapped into the Stellaris microcontroller s memory and are used to control the flow of the video streams Register Descriptions on page 55 provides the detailed register maps This is contained within the vregs v file Memory Windower The memory windower allows the Stellaris microcontroller to work with a rectangular portion of a frame buffer For example this can be used to pull macro cells for JPEG compression This is contained within the mport v file Memory Arbiter The memory arbiter negotiates access to the external SRAM The camera capture block is given highest priority This is contained within the arb v file Video Compositor The video compositor assembles the final image from the video and graphics frame buffers and passes it directly to the LCD Interface It also converts the camera s VGA resolution to the LCD s QVGA resolution by either downsampling
26. For more information on the DK LM3S9B96 FPGA expansion board see Appendix Stellaris amp LM3S9B96 FPGA Expansion Board on page 49 Stellaris amp EM2 Expansion Board DK LM3S9B96 EM2 sold separately Provides a transition between the Stellaris External Peripheral Interface EPI connector and the RF Evaluation Module EM connector Enables wireless application development using Low Power RF and RF ID evaluation modules on the Stellaris DK LM3S9B96 platform For more information on the DK LM3S9B96 EM 2 expansion board see Appendix G Stellaris amp LM3S9B96 EM2 Expansion Board on page 69 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Figure 1 1 DK LM3S9B96 Development Board 5 VDC supply input Headphone Output Audio Line Output Microphone Input Audio Line Input USB Connector for Debug and or Power PELA UE 2n board JTAG SWD Debug Interface CAN Bus Interface EPI Expansion Board USB connector with Host Device and On the Go modes Reset switch JTAG SWD WP Eel i lt Stellaris Out Connector gt 122 LM3S39B96 gt i T Microcontroller LL ssec gt 35 10 100 Ethernet Ground Test m e Points UL i I User LED Potentiometer User Switch 3 00V Analog Reference microSD Card Slot 1MB Serial Flash Memory 3 5 LCD Touch Panel S
27. IP_LO6N_O GCLK9 35100 4 00144 LOGP 0 GCLKS Uie IP LO3N 0 wan IP LO3P 0 a IO LOIP 2 CSO B IP IO LOIN 2 INIT B CHE XINITB gt IP E IO LO2P 2 DOUT BUSY IP 2 101025 2 MOSICSI B HE E IO 04 2 D7 GCLK12 IP VREF 1 IO LO4N 2 DG GCLK13 L D6 IP 10 25 D DS IP IO LOSP 2 DA GCLK14 10 LOSN 2 D3 GCLKIS RS 10_LO7P_2 D2 GCLK2 XVCLKR H 2 DI GCLKG LD be 56 2 2 MO 2 PXLCLK 1 IO LOSN 2 DIN DO 36 IP LOGN_2 M2 GCLK1 LO9P 2 VS2 A19 a TPS TES 18 1 IP_LO6P_2 RDWR_B GCLKO LO9N 2 5 18 M TP7 471 TP LO3N_2 VREF 2 LIOP 2 0 17 a SMT Socket 2x17 TP6 pea IP LO3P 2 LION 2 CCLK LCD 185 as Ib 35100 2 06142 1 0K R5 1 0K 24 31 x mis 3 TI AEC Austin M2 MI __24 108 Wild Basin Rd ak Wis TEXAS INSTRUMENTS 2 127 IP RERO Austin TX 78746 ds Socket al Designer Drawing Title XC3ST00E ATQGI44C aki Amaldo Cruz FPGA board for DK EPI gt z MMBT3904 Drawn by Page Title M Arnaldo Cruz EPI LCD Camera I F Approved Size Document Number Rev B 0001 B Date 8 21 2009 Sheet 1 2 VCCO 0 VCCAUX UID VCCO 0 VCCAUX ONES VCCO 1 VCCAUX x IO LOIN 3 inm 4 10 MAD2 MAD3
28. This is contained within the vicd v file LCD I F The LCD interface connects to the Kitronix 3 5 LCD display using an 8 bit parallel mode This is usually driven by the Video Compositor but can also be driven directly by the EPI interface This is contained within the vregs v file Camera I F The camera interface block captures pixel data from the Omnivision OV7690 s 8 bit digital video port and synchronization signals This is contained within vcapture v Camera FIFO The Camera FIFO serves two main purposes reclocking and flow control The camera and camera interface run in their own 12 24 MHz clock domain whereas the rest of the system runs off of the EPI clock or twice the EPI clock The FIFO bridges these difference clock domains The camera does not support any flow control functions once triggered it proceeds through an entire image In order to prevent loss of pixels this FIFO is 64 elements deep This is contained within the vcapture v and async_fifo_64 v files 62 September 5 2010 EPI Signal Descriptions Table F 8 provides the EPI module s signal descriptions Table F 8 EPI Signal Descriptions Stellaris amp LM3S9B96 Development Kit User s Manual EPIOS 31 PG7 CLK In EPI Clock EPIOS 30 PJ6 E Out Interrupt Signal to Microcontroller EPIOS 29 PJ5 E RD In EPI Read Strobe EPIOS 28 PJ4 WR In EPI Write Strobe EPIOS 27 PH7 Out EPI Ready Signal EPIOS 26 PH6
29. Use aslight pressure to seat the EM module firmly on the EM2 expansion board See Figure G 6 on page 73 for fully assembled DK LM3S9B96 board with EM2 expansion board and wireless EM module Figure G 6 Fully Assembled DK LM3S9B96 Board with EM2 Expansion Board and Wireless EM Module Antenna for EM module EM module EM expansion board DK LM3S9B96 DK LM3S9B96 board www ti com stellaris Follow these same steps for installing a second module into the secondary EM header location which will be oriented 180 degrees from the primary EM header location NOTE The secondary EM header should only be used when two EM modules are installed in the system or when specifically indicated in the EM module s README First document September 5 2010 73 Hardware Description The block diagram for the EM2 expansion board is shown in Figure G 7 Figure G 7 2 Expansion Board Block Diagram 32 KHZ OSC Connector 33 V SDIO FOIE AE Header UART1 4 eM UART PRIMARY SPI Nh PI EM 5 10 MOD1 SPI_CS HEADER C WO MOD1 SHUTDOWN PO MOD 1 MOD1 GPIO 4 4 hhh cro _ NDS Header 3 3V Ps 22 SECONDARY 6555 L p UART EM Header 8 SPI CS HEADER M gt Audio MOD2 SHUTDOWN MEN MOD2 Header MOD GPIO 4 GPIO AD I2C 4
30. found on other Stellaris boards The development board includes an on board in circuit debug interface ICDI that supports both JTAG and SWD debugging A standard ARM 20 pin debug header supports an array of debugging solutions The Stellaris LM3S9B96 Development Kit accelerates development of Tempest class microcontrollers The kit also includes extensive example applications and complete source code Features The Stellaris amp LM3S9B96 Development Board includes the following features Simple set up USB cable provides debugging communication and power Flexible development platform with a wide range of peripherals W Color LCD graphics display TFT LCD module with 320 x 240 resolution Resistive touch interface 80 MHz LM3S9B96 microcontroller with 256 Flash 96 SRAM and integrated Ethernet USB and CAN communications 8MB SDRAM plug in EPI option board break out board plug in option board 1 MB serial Flash memory Precision 3 00 V voltage reference SAFERTOS operating system in microcontroller ROM 25 stereo audio codec Line In Out Headphone Out Microphone In Controller Area Network CAN Interface 10 100 BaseT Ethernet USB On The Go OTG Connector Device Host and OTG modes September 5 2010 7 User LED and push button Thumbwheel potentiometer can be used for menu navigation MicroSD card slot Supports a range of debuggi
31. ies es 14 acc LE 15 Power Supplies cebat boues dete 15 Ui EIL 15 BE aN E M 16 Color QVGA LCD Touch 17 SE Tom m 19 User Swich and PD 19 Chapter 3 Stellaris amp LM3S9B96 Development Board External Peripheral Interface 21 SDRAM Expansi n Boa iere cte ener Erat e P e s ene eve ior o A TO eap bes Peau eu see ee rg ele 21 Flash and SRAM Memory Expansion 9 21 FPGA Expansion BOar ties iui di a duit deed dag doe PU dev dde de 21 EM2 Expansion aet dee ne e e 21 Chapter 4 Using the In Circuit Debugger Interface eese eee ennt nennen nnns 23 Appendix A Stellaris amp LM3S9B96 Development Board 2 2 25 Appendix B Stellaris amp LM3S9B96 Development Board Component Locations 33 Appendix C Stellaris amp LM3S9B96 Development Board Connection Details 35 DC o lo M N 35 ARM Target PinoUt det ecu een bert pt teu eirca eet da Pe ERE PRORA ENS 35 Appendix D Stellaris amp LM3S9B96 Development Board Microcontroller GPIO Assignments 37 Appendix E Stellaris amp LM3S9B96 Flas
32. or the next highest power of two Memory Port Number of Columns Register The MPNC register specifies the number of columns in pixels of the memory port Memory Port Current Row Register The MPR register identifies the selected row in the memory port Memory Port Current Column Register The MPC register identifies the selected column in the memory port Memory Port Address Low Register The MPML register contains the lower address bits of the memory region accessed by the memory port Memory Port Address High Register The MPMH register contains the upper address bits of the memory region accessed by the memory port Memory Port Stride Register The MPMS register specifies the number of bytes between the first pixels on adjacent rows in the memory port Recommended to be either the length of a row in bytes or the next highest power of two 60 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Memory Port Register The MPORT register allows sequential video graphics memory plane access A write read to this port generates a memory write read to the memory location calculated as follows Mem address MPH MPL MPR x MPS MPC After the transfer if the MPC is not at the last pixel of the row it automatically increments by 1 If the MPC is at the last pixel of the row it sets to 0 and the MPR is incremented by MPS Memory Window Register Use the MEMPAGE register to select the active page 1 Kbyt
33. out JTAG SWD 5 Output Input 8 a QVGA Color LCD Module Debug USB OTG Host Device signals ZEE Ethernet Phones Line Output Tempest LM3S9B96 Development Board J Development Board Specifications Board supply voltage 4 75 5 25 from one of the following sources Debugger ICDI USB cable connected to a PC USB Micro B cable connected to a PC DC power jack 2 1 x 5 5 from external power supply Break out power output 3 3 100 mA max September 5 2010 11 12 Dimensions excluding LCD panel 4 50 x 4 25 x 0 60 LXWxH with SDRAM board 4 50 x 4 25 x 0 75 LXWxH with EPI breakout board Analog Reference 3 0 V 0 2 RoHS status Compliant NOTE When the LM3S9B96 Development Board is used in USB Host mode the host connector is capable of supplying power to the connected USB device The available supply current is limited to 200 mA unless the development board is powered from an external 5 V supply with a 600mA rating September 5 2010 Stellaris amp LM3S9B96 Development Board Hardware Description In addition to an LM3S9B96 microcontroller the development board includes a range of useful peripheral features and an integrated in circuit debug interface ICDI This chapter describes how these peripherals operate and interface to the microcontr
34. used in 8 bit mode Note that MA27 is used as a chip select signal for this memory SRAM The SRAM used is 8 Mbit 45 nsec Cypress Semiconductor CY62158EV30LL 45ZSX which is an 8 bit memory Note that MA27 and MA26 are used as chip selects for this memory Memory This serial memory is used for storing configuration data This is a 1 kilobit On Semiconductor memory LCD I F Power Schematic 2 on page 48 Page 2 of the schematics shows the LCD DECODE CPLD LCD interface connector and the 3 3 V regulator LCD DECODE CPLD The LCD DECODE CPLD provides address latch and decode for the LCD interface The LCD Command and Data registers are mapped on the EPI memory space to streamline access to these registers The LCD panel control signals L RDn L RWn and L DC and the L D bus are controlled by decode logic on the CPLD with timing derived from EPI signals and do not require direct control from the microcontroller The LCD latch register is provided to control the XN and YN signals used for the touchscreen and also the reset signal to the LCD The LCD backlight signal L BL is controlled by the Stellaris GPIO 24 can be programmed as a GPIO for ON OFF control of the LCD A second option is to configure PE2 for use as CCP2 or 4 with a PWM output for brightness control The 1 4 testpoints connect to the CPLD JTAG signals and along with TP5 and TP6 provide an interface for test and programming
35. 003 10503 23 6 054 SDRAM 004 0504 22 055 005 0805 September 5 2010 37 38 Table D 1 Microcontroller GPIO Assignments Continued LM3S9B96 GPIO Pin Development Board Use Number Description Default Function Default Use Alt Function Alternate Use 10 PDO PDO LCD Data 0 I2SRXSCK 125 Audio In 11 PD1 PD1 LCD Data 1 I280RXWS 125 Audio In 12 PD2 PD2 LCD Data 2 EPIOS20 EPI Breakout 13 LCD Data 3 10521 EPI Breakout 97 PD4 PD4 LCD Data 4 I2SRXSD 125 Audio In 98 PD5 PD5 LCD Data 5 I2SRXMCLK 128 Audio In 99 PD6 PD6 LCD Data 6 100 PD7 PD7 LCD Data 7 74 PEO 058 SDRAM 08 0508 75 PE1 EPIOS9 SDRAM D9 EPIOSO9 95 PE2 PE2 Touch XN EPIOS24 96 Touch YN 10525 6 4 125 5 125 Audio Out 5 PE5 125 5 125 Audio Out 2 PE6 ADC1 ADC Touch XP 1 PE7 ADCO ADC Touch YP 47 PFO PFO Flash CSn 61 PF1 I2STXMCLK 125 Audio Out 60 PF2 LED1 Green Enet LED 59 User LED LEDO Yw Enet LED 42 4 0512 012 41 PF5 0515 015 19 PGO EPIOS13 SDRAM D13 18 PG1 EPIOS14 SDRAM 014 36 PG7 EPIOS31 SDRAM CLK 86 PHO 0506 SDRAM 006 85 PH1 10507 SDRAM 007 84 PH2 0501 001 83 PH3 EPIOSOO SDRAM D00 76 PH4 EPIOS10 SDRAM D10 September 5 2010 Table D 1 Microcontroller GPIO Assignments Con
36. 1 Remove the DK LM3S9B96 EXP FS8 memory expansion board from the antistatic bag 2 Onthe DK LM3S9B96 board remove any installed board on EPI connector J2 September 5 2010 41 3 DK LM3S9B96 board remove the shunt jumpers JP16 JP31 and the JP39 headers as shown in Figure E 1 on page 41 Figure E 2 Removing EPI Board from DK LM3S9B96 Development Board 1 iB 5 3 Remove board Remove jumpers 4 Install the two snap in nylon standoffs on mounting holes above the EPI connector J2 Place the expansion board on top of the DK LM3S9B96 board and align the standoffs the EPI connector and the 2x17 J2 header 6 Press firmly downward until the board snaps in then verify that the board is firmly seated on the EPI connector the 2x17 header and the standoffs 7 When powering up the board verify that the power indicator LED D1 is lit 42 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Hardware Description The Flash and SRAM memory expansion board is designed for use with the Stellaris EPI module configured in Host Bus 8 address data multiplexed mode This mode requires the use of an external 8 bit latch for storing the lower 8 address lines A 7 0 transmitted during the address phase of an EPI transfer This latch can be seen on the expansion board block diagram shown in Figure E 3 Figure E 3 Flash SRAM LCD IF Expansion Board Block Diagram
37. 2 AUD DATA OUT OUT 5 je MISO 15 2 z 16 1 SPI CS2 MOD UART TX 89 88 4 x 09 e SPI_CS1 16 1 3 3V a 19 28 MOD2_GPIOO Bio 9 MOD2 109 1510 MOD2 AUD DATA IN 40 1 EPIS 27 4 010 Header 1x6 100 4301 d n 38 MOD I2C SDA HPA MB MODULE ASSY RF p U MOD2 AUD FSYNC e 125 HAES MOD2 1 1 12 811 EDIZ 88 MOD I2C SCL RF MODULE PORT 1A 7013 MOD2_GPIO2 EPIS 35 13 9 578 MOD UART RTS SPI 652 Bi4 13 014 5 35 18 17 10 7 2 SDA 15 814 014 pie MOD2 nSHUTD J5 EPH2 5 n 06 11 6 MOD1_GPIOO SPI CLK Bie 815 gt 015 7016 RFMOD2 ANALOG 07 12 5 MOD1 GPIOT B17 D17 MOD2 AUD CLK ila EP109 32 19 EPIOT 18 4 MOD1 GPIO2 SPI MOSI Big 817 D17 DIS UART RTS MOD2 AUD R e us 2 00 14 3 819 818 2916 MOD2_nSHUTD MOD2 AUD ANAL 3 e 15 2 SPI CLK SPI MISO 1 820 D20 MOD2_GPIO3 41 29 22 16 1 MOD2 nSHUTD B20 D20 28 23 Header x4 100 4301 27 24 27 e 26 25 a E DF12A 50DS Be 100K PED Adapter Board Assignment PED Adapter Board Assignment 2 chip to enable adapterboard auto discovery 10K SDIO_CLK R14 15 c5 zB 2 R11 427 lt 27K FTH 1 8 0 VCC 7 we 3 A1 WP 6 AD I2C SCLO 2 SDIO DO A 4 A2 SCL 5 1 12 SDAO 4 SDIO_D1 LAS EXAS INSTRU
38. 3 3 U6 TPS2051BDBV 4VBUS R23 5V IN OUT 1 PA6 USBEPE CANORX DSBUBRE 4 EN JP37 PFLT PA7 USBPFLT CANOTX USBOBELE JP38 a C20 C36 R24 0 1UF 22UF 10K VBUS Fault Protected Switch 3 3 22 VREF 3 00V I3K CATHODE 3 ILED LI D3 NC 4 45V NR4018T100M 10uH FYV0704SMTF D4 LM4040B30IDB R25 17 7152 24 30s a VIN SW ILED Backlight 3 0V 0 2 Voltage Reference m ej 4 SHDN JP39 LED Backlight Controller indicates factory default jumper position Texas INSTRUMENTS Drawing Tite M3S9B96 Development Board Tite Power Supplies Size Document Number PB 1 1 359896 Date Sheet 4 23 2009 6 6 D Line Input i R54 3 R55 ANN STX 3000 n R6 AK Tue T7 Tone 4 4 J9 1 Microphone Input e STX 3000 433v R27 09 2200 SDA 2j PBI DCOSDA 104 LLINEIN LHPOUT went MIC
39. A Header 1x6 100 4301 GND EN I2C SDA B11 2 HPA MB MODULE ASSY RF 8 011 MOD1 AUD FSYNC 32 768kHz Header 1x8 100 430L MODI GPIOT 811 8 011 512 p c4 MOD 2 SCL Bis 812 MODULE PORT 012 Dis MOD GPIO2 10000pF SPI 51 Big 813 o 013 Dia J33 DNI MODI SDIO CLK B15 814 014 015 MOD1 nSHUTD RFMOD1_ ANALOG 1 1 SPI CLK Bie 815 gt 015 916 ifa MODi SDIO CMD B17 EE 018 017 MOD1 AUD MOD AUD ANA R2 SPI MOSI BIB 817 017 MOD UART RIS MODi AUD ANA 9 19 D19 MODI nSHUTD 4 3 3V SPI MISO B20 B19 019 620 B20 026 Header 1x4 100 4301 i Stellaris LM3S9B96 header 33 R13 S R12 T J6 ise Sue 83V 1 359896 Header Secondary header 33 T CC P1 CC P2 100K 50 1 H B1 D1 43 3V 02 49 2 9 ALS MOD2_GPIO0 2 01 52 J4 MOD nSHUTD 9 8 T J 3 EPHA 10 T MOD2 GPIO1 UART CTS Bs 82 02 93 125 MOD TX 10 7 04 25 1i 6 83 83 04 MOD2 AUD ANA L 11 6 05 16 12 5 MOD I2C SCL SEC MOD SCLK B5 D5 MOD2 AUD CLK za MOD2 GPIO2 12 5 E PB2 13 4 AD 120 SCLO B6 85 05 pe MOD2 AUD MODZ AUD FSYNC 3 MOD2 GPIO3 13 4 2 44 7 14 3 2 SDAO MOD UART RX B7 B6 D6 D7 MOD2 AUD DATA IN 4 SPI MOSI 14 3 PBS 22 E 15 2 CTS B8 Sr lt 08 T _ MOD
40. AO UORX zm s 5 NE JP56 6 Num DB LM3S9B96 Date Sheet Rev 4 23 2009 6 of 6 6 32 September 5 2010 Stellaris amp LM3S9B96 Development Board Component Locations This appendix contains details on component locations including Component placement plot for top Figure B 1 September 5 2010 33 Figure 1 34 Component Placement Plot for Top BD SDR9B96 A C65 C64 C62 BD EPI9B96 A Jt5 8 519 8 15 e U8 um 5V E 5 0 z x a 102 5 eio 22 cs ICDI o z We 76 CAN USB C67 R321 650 Tess 4 652 061 850 58 55 2585 me TUE S un 229ggg2o028g9gg 2 Eo 5 z 52 8 J SESSPEEBEPES E e amp 58 52552525528 2522 5 8 Al amp amp 5 amp 8 6 amp 8 433 8 5 09 125 AUDIO 2 a9 R58 ss POTHER 5 LINE QUT Boe a RB a EN C72 RSI 9261 MCU PA7 JP14 TXD RIT PAG RXD Y3 622 5V 0732 R52 USB HOST DEVICE OTG RESET pei 1805 88 8 15 Ui EXTERNAL PERIPHERAL INTERFACE PBO 724 OTG D 37 a PAT
41. BIAS 17 rU if PB2 DCOSCL gt MIGIN 18 2200 R32 834 wv 47K TXSD PES DSTXSD 33 spin C IP42 Rework 2 Loop TXWS to RXWS 22 SCLK 5 2 S T um TXWS 51 MODE LOUT A 1 PEA DSTXWS gt ncs ROUT 047UF 100 Jp43 3 CSS z RXSD Tem 5 5 3000 PDA DSRXSD ne ANY 1244 z LRCIN 047UF 100 um 2 m de PDI DSRXWS me 1 rRcour JP45 3 BCLK PB6 BCLK 2 PB6 TXSCK AVREF 25 CLKOUT IP46 m PDO BCLK VMID PDO DSRXSCK i JP47 BVDD HPVDD C56 cs9 60 261 PEUMCLK AVDD 7248 PDS MCLK PDS DSRXMCLK me HPGND 740 DGND AGND TLV320AIC23BPW Analog 3 3V 50mA Power Supply U9 PQILA333MSPQ 5V 4 VOUT 3 on NR c49 C53 22UF 51 22UF a ees Audio Headphone Output Audio Line Output ES indicates factory default jumper position Texas INSTRUMENTS Drawing M3S9B96 Development Board Page Title DS Audio Expansion Board Size Document Number PP 1 M359B96 Date 4 93 9909 Sheet 4 of 6 Rev 6 6 D Expansion Connector 12 50 1 ES II AD2 48 3 BAO DI3 47 4 BALDI 5 6 7 zm 9 SDCKE 1
42. D2 GPIO2 GPIO for Secondary EM Module PJ2 PJ2 MOD2 GPIO3 GPIO for Secondary EM Module 76 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Component Locations Figure G 8 shows the details of the component locations Figure G 8 Component Placement Plot for Top and Bottom gt LI m m PRIMARY EM HEADER MOD1 01 RL 1359896 Header TELLITE 26 1 5 R I B20 01 TEXAS INSTRUMENTS INC 2010 REV C DK LM359B96 EM2 S N RFMOD2 125 m i i e m GND ANAL ANAR GND GND DOUT DIN FSYN CLK VDD VDD CMD CLK 03 02 DI DO GND o z lt 5 wp VDD CLK FSYN DIN DOUT GND GND ANAR ANAL GND B2 2007 ANVONOO3S 02 103 e e e e 53 ale Bottom Schematics This section shows the schematics for the EM2 expansion board B Expansion Board on page 78 September 5 2010 77
43. E RSTn In FPGA Reset Signal P PE3 PE2 PB4 EPIOS 25 16 PB5 PD3 PD2 PJ3 E_ADDR 10 1 In EPI Address Bus PJ2 PJ1 PJO PF5 PG1 PGO PF4 PH5 PH4 PE1 PEO EPIOS 15 0 1 7 PC6 E DATA 15 0 EPI Data Bus PC5 PC4 PH2 PH3 a Configure as Stellaris GPIO input with negative level sensitive interrupts During power up reset is used for PLL lock status b Configure as Stellaris GPIO output September 5 2010 63 Component Locations Figure F 5 shows the details of the component locations from the top view and Figure F 6 shows the details of the component locations from the bottom view Figure F 5 Component Placement Plot for Top 64 2775 00 12 _ 20 70 gt mmu BI NU UN tg 430 00 I 780 00 mil EM n 00 9 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Figure F 6 Component Placement Plot for Bottom fe 2070 00 MI m a eco 2775 00 lt 12 A 430 00 Y ____ 780 00 o 00 9 Schematics This section shows the schematics for the LM3S89B96 FPGA memory expansion board EPI LCD Camera I F on page 66 SRAM Power JTAG on page 67 September 5 2010 65 Revision History
44. MENTS CAT24C01 D3 xA 42 GPIO1 LM3S9B96 EM2 Adapter Shunt_100 ize Document Number lev B DK LM3S9B96_EM2 Date Monday July 12 2010 Bheet 1 of 1 5 4 3 2 1 References In addition to this document the following references are included on the Stellaris DK LM3S9B96 Development Kit Documentation and Software CD and are also available for download at www ti com stellaris Stellaris LM3S9B96 Microcontroller Data Sheet m LCD Data Sheet StellarisWare Driver Library StellarisWare Driver Library User s Manual publication number SW DRL UG Additional references include FT2232D Dual USB UART FIFO IC Data sheet version 0 91 2006 Future Technology Devices International Ltd Texas Instruments TLV320AIC23BPM Audio CODEC Data Sheet Information on development tool being used September 5 2010 RealView MDK web site www keil com arm rvmdkkit asp IAR Embedded Workbench web site www iar com Code Sourcery GCC development tools web site www codesourcery com gnu_toolchains arm Code Red Technologies development tools web site www code red tech com Texas Instruments Code Composer Studio IDE web site www ti com ccs 79 80 September 5 2010 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its prod
45. P38 PFLT C36 1040 45 52 RESET LUMINAR Y MICRO 9754 Sco pss LM3S9B96 mij ee DEVELOPMENT VCPTX 4956 BOARD 1004953 uso 0 RB m Gis ETHERNET 2 TD 452 T 8 PFS 20241 m cn 026 PIN1 9657 VDD 4 GND 59 8 DEBUG 69 INTERFACE n 04 25 OE sv eren 5 0 POT VREF 3007 33 pas e e 2 LED 2 m m SERIAL FLASH 2 5 525 SDCARD u 5 8 282225 E FER 885885 QVGALCD un mN T ab gg 3 00VREF 83 E 13 September 5 2010 Stellaris amp LM3S9B96 Development Board Connection Details This appendix contains the following sections DC Power Jack see page 35 ARM Target Pinout see 35 DC Power Jack The EVB provides DC power jack for connecting an external 5 V regulated 5 power source Center Positive The socket is 5 5 mm dia with a 2 1 mm pin ARM Target Pinout In ICDI input and output mode the Stellaris LM3S9B96 Development Kit supports 5 standard 20 pin JTAG SWD configuration The same pin configuration can be used for debugging over serial wire debu
46. PI Board from DK LM3S9B96 Development 42 Figure E 3 Flash SRAM LCD IF Expansion Board Block 43 Figure E 4 Component Placement Plot for Top and 46 Figure F 1 FPGA Expansion 49 Figure F 2 Removing EPI Board from DK LM3S9B96 Development 51 Figure F 3 FPGA Expansion Board Block 52 Figure F 4 FPGA Boundary 61 Figure F 5 Component Placement Plot for Top 64 Figure F 6 Component Placement Plot for 65 Figure G 1 EM2 Expansion 69 Figure G 2 Removing EPI Board from DK LM3S9B96 Development 70 Eig re G 3 EM2 Expansion Boardi REEL tete nieder en ar po te i e Ert ve eive ihe 71 Figure G 4 Assembled DK LM3S9B96 Development Board with EM2 Expansion 71 Figure G 5 Connecting an EM Module to the EM2 Expansion Board
47. PI and SDRAM Expansion Boards on page 30 In circuit Debug Interface ICDI on page 31 September 5 2010 25 PE2 EPI24 EPI Expansion Connector 25 2 2 ANR PDOEPDO See Stellaris Microcontroller PDSEPDI Ju PBA ADCIUEPED 2 49 UL PBSEPD2 NPQUEPII3 3 48 02 USB On the Go PHO EPD6 phe Epp 4 47 PCS EPIO3 J3 2 5 2 7 5 PAQ UORX gt 26 PBO USBOID Lo Hf PBOUSBID gt ao USB Micro 565 PBI USBOVBUS tj PBIUSBVBUS PBSEPIST 7 PA2 SSIOCLK 507 PAZ SSIOCLK PB2 CCPO 2 lt PB2 I2COSCL gt PDEPDOBES PA3 PA3 SSIOFSS PB3 gt 4 2 PAd SSIORX 2 PAd SSIORX PBA EPIOS23 92 PEL a E PAS SSIOTX 377 PASISSIOTX 0522 MZ ERIS PAG USBEPE CANORX PAG USBOEPEN PBO AVREF PB6 TXSCK AVREF BEEN PAT USBPFL
48. R R R R 2 R W R W R W Bit Name Description LCD panel touchscreen X control When set to 0 the LCD Xn signal is set to 0 When set to 1 the LCD Xn signal is tri stated YN LCD panel touchscreen Y control When set to 0 the LCD Yn signal is set to 0 When set to 1 the LCD Yn signal is tri stated RST LCD panel reset control When set to 0 the LCD RSTn signal is set to 0 When set to 1 the LCD RSTn signal is set to 1 BL LCD backlight control When set to 0 the LCD panel backlight is turned off When set to 1 the LCD panel backlight is turned on Chroma Key Register The CHRMKEY register contains the RGB values to compare for graphics overlay operation During LCD screen updates data from graphics memory is compared with this register if a match occurs the corrsponding frame video pixel is sent to the output instead Video Capture Row Match Register During video capture at the start of a row the current row value is compared with the register A match generates an interrupt if enabled Video Memory Address Low Register The VML register provides a pointer to the start of video capture memory and contains the lower 16 bits of the address Video Memory Address High Register The VMH register provides a pointer to the start of video capture memory and contains the higher 16 bits of the address Video Memory Stride Register The VMS register specifies the number of locations in video memory between successive
49. SN74LVCI26A ACBUS2 R44 SK ACBUS3 3 B 2 42 _443 3v BDBUSO VCP TX SWO js M 45V 45V BDBUSI AI 10K 6 BDBUS2 Gn SN7ALVCI25A Ul BDPS SWO EN SN7ALVCI25A 5 10K BDBUS4 e UISB H veo cH EECS BDBUSS SN74LVC126A SK 5 EESK BDBUS6 H ORG zu EEDATA BDBUS7 H9w 0 TEST 9 _ 15K XTIN BCBUS TDO SWO XTOUT BCBUS2 BCBUS3 A 20 3 3 UISC Holes RESET A SN74LVCI26A BOONES RSTOUT PWREN C68 C69 45V 9 GND 4 27PF 27PF 18 5 25 GND d GND VCCIOA GND C73 U14B 45 SN74LVC125A SOND AVEG 0 1UF O 1UF O 1UF 0 1UF ev FT2232D T H Channel A JTAG SW Debug 5 10K Channel B Virtual Com Port TCK TCK 0150 mu Em SN74LVCI26A TMS PCI TMS TMS SWDIO JTAG SWD In Out 5 J14 R46 SRSTN gt TD p L JP52 ui PC3 TDO wm TDO_SWO ww POSNE 433V 433V 3 27 ES ES SN74LVCI25A indicates factory default jumper position R48 RESETE SRSTN 3 433V D 1954 2 use UISE 5 Texas INSTRUMENTS VCPTX R49 SWDIO SN7ALVCI25A SNTALVCI25A SN74LVCI26A C99 IMS SWDIO PAI UOTX 27 Drawing M3S9B96 Development Board JS PIN1 PEE R50 Page Title ERUIT VCPRX 2X10 HDR SHRD 5 TDI 9 d In circuit Debug Interface ICDI ANS P
50. Stellaris LM3S9B96 Development Kit User s Manual X TEXAS INSTRUMENTS DK LM3S9B96 05 Copyright 2009 2010 Texas Instruments Copyright Copyright 2009 2010 Texas Instruments Inc rights reserved Stellaris and StellarisWare are registered trademarks of Texas Instruments ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited Other names and brands may be claimed as the property of others Texas Instruments 108 Wild Basin Suite 350 P Austin TX 78746 http www ti com stellaris T Cortex Intelligent Processors by 2 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Table of Contents Chapter 1 Stellaris LM3S9B96 Development Board Overview nnna 7 EI c IE 7 Developrmient 5 iie etre a deb ada d Du adde 10 DIA QR ei 11 Development Board 11 Chapter 2 Stellaris amp LM3S9B96 Development Board Hardware Description 13 LM3S9B96 Microcontroller Overview 13 Jumpers and GPIO 13 e et m of orc e d i ai
51. Stellaris DK LM3S9B96 development board to demonstrate the machine to machine M2M high bandwidth parallel interface capability of the Stellaris microcontroller Right out of the box users are able to control and display the FPGA expansion board s video on the DK LM3S9B96 development board s large 3 5 touchscreen display For more information on the FPGA Expansion Board sold separately see Appendix Stellaris LM3S9B96 FPGA Expansion Board on page 49 EM2 Expansion Board The EM2 Expansion Board DK LM3S9B96 EM2 is an optional expansion board which connects directly to the External Peripheral Interface EPI port of the Stellaris DK LM3S9B96 development board The EM2 Expansion Board provides a transition between the Stellaris External Peripheral Interface EPI connector and the RF Evaluation Module EM connector The DK LM3S9B96 EM2 enables wireless application development using Low Power RF and RF ID evaluation modules on the Stellaris DK LM3S9B96 platform For more information on the EM2 Expansion Board sold separately see Appendix Stellaris LM3S9B96 EM2 Expansion Board on page 69 September 5 2010 21 22 September 5 2010 Using the In Circuit Debugger Interface The Stellaris LM3S9B96 Development Kit can operate as an In Circuit Debugger Interface ICDI ICDI acts as a USB to the JTAG SWD adaptor allowing debugging of any external target board that uses a Stellaris microcontroller See Debug
52. T CANOTX 35 PATIUSBOPFLT PB7 NMI lt A 2 4 PCO TCK gt 59 PCUITCK SWCLK 10 lt PDO I2SRXSCK ih VBUS PCI TMS gt PCI TMS SWDIO PDI lt PDU DSRXWS 78 12 PDZEPDO PBS EPD2 16 PIZ EPITS PC2 TDI PC2 TDI PD2 EPIOS20 Sees 7 17 PFS EPIIS 2 PCA EPIOZ 25 5 SD OT 18 PFAJEPIT2 DI D2 PCS EPIO3 og PDA DSRXSD 07 19 2 1 2 0 5 0503 PDS DSRXMCLK 1 PCO EPIOA pps 299 20 00 4 7 105 22 100 gt 4 00 21 PEU EPIOS B72590D0050H160 B72590D0050H160 BCT BESS eeu PHA EPIIO PHS EPITI IDE D PEO EPIOSO8 PFO a lt gt 955 PEI EPIOSO9 PFI lt PFI TXMCLK LED1 55 BEUEBDR 9 PE2 EPIOS24 PEJLEDI 35 IHH 4VBUS DM 0525 PEYLEDO 55 PFSLEDO 1 1 PBI USBVBUS PEA DSTXWS PEAADC3 PE EPIOSI2 f JP3 05 PES DSTXSD 2 PES ADC2 PES EPIOSIS gt ID LED2 205 OTG ID Tilda PEG ADCI PEO ADCI PBO USBID gt 1 PE7 ADCO PET ADCO PHO EPIOSO6 pri Epio JP2 JP 19 0807 55 PHO EPIOI PGU EPITA PHS EPIOO Note PGT EPISI 0500 376 PHa EPIO R60 61 10 Ohms for LM3S9B96 Rev B1 see errata 5 63 PHS EPIII
53. WD ULINK JLINK etc withthe header development board Debug In Considerations Debug Mode 3 supports board debugging using an external debug interface such as a Segger J Link or Keil ULINK Most debuggers use Pin 1 of the Debug connector to sense the target voltage and in some cases power the output logic circuit Installing the VDD PIN1 jumper will apply 3 3 V power to this pin in order to support external debuggers Debug USB Overview 16 An FT2232 device from Future Technology Devices International Ltd implements USB to serial conversion The FT2232 is factory configured to implement a JTAG SWD port synchronous serial on channel A and a Virtual COM Port VCP on channel B This feature allows two simultaneous communications links between the host computer and the target device using a single USB cable Separate Windows drivers for each function are provided on the Documentation and Software CD The In Circuit Debug Interface USB capabilities are completely independent from the LM3S9B96 s on chip USB functionality September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual A small serial EEPROM holds the FT2232 configuration data The EEPROM is not accessible by the LM3S9B96 microcontroller For full details on FT2232 operation go to www ftdichip com USB to JTAG SWD The FT2232 USB device performs JTAG SWD serial operations under the control of the debugger A simple logic circuit multipl
54. a SDA I2COSCL CODEC Configuration Clock SCL I2STXSD Audio Out Serial Data TXSD I2STXWS Audio Out Framing signal TXWS 125 Audio Out Bit Clock BCLK I2STXMCLK Audio Out System Clock MCLK I2SRXSD Audio In Serial Data RXSD l2SRXWS Audio In Framing signal Rxws I2SRXSCK Audio In Bit Clock BCLK I2SRXMCLK Audio In System Clock MCLK a Shares GPIO line with Analog voltage reference Jumper installed by default b Shares GPIO line with LCD data bus Port D Jumper omitted by default The Audio CODEC has a number of control registers which are configured using the 2 bus signals CODEC settings can only be written but not read using See the StellarisWare example applications for programming information and the TLV320AIX23B data sheet for complete register details The Headphone output can be connected directly to any standard headphones The Line Output is suitable for connection to an external amplifier including PC desktop speaker sets User Switch and LED The development board provides a user push switch and LED see Table 2 7 Table 2 7 Navigation Switch Related Signals Microcontroller Pin Board Function Jumper Name PJ7 User Switch SWITCH PF3 User LED LED a Shared with Ethernet Jack Yellow LED This jumper is installed by default September 5 2010 19 20 September 5 2010 Stellaris amp LM3S9B96 Development Board External Peripheral Interface EPI The External Pe
55. array elements stride and is measured in bytes Using stride enables better processing time LCD Row Match Register During LCD display DMA output at the start of each row the current row value is compared with the LRM register A match generates an interrupt if enabled September 5 2010 59 LCD Video Memory Address Low Register The LVML register provides a pointer to the start of video data for transfer to the LCD This contains the lower 16 bits of the address LCD Video Memory Address High Register The LVMH register provides a pointer to the start of video data for transfer to the LCD This contains the higher 16 bits of the address LCD Video Memory Stride Register The LVMS register specifies the number of bytes between the first pixels on adjacent rows in LCD video memory Recommended to be either the length of a row in bytes or the next highest power of two LCD Graphics Memory Address Low Register The LGML register provides a pointer to the start of graphics memory for output to the LCD and contains the lower 16 bits of the address LCD Graphics Memory Address High Register The LGMH register provides a pointer to the start of graphics memory for output to the LCD and contains the higher 16 bits of the address LCD Graphics Memory Stride Register The LGMS register specifies the number of bytes between the first pixels on adjacent rows in LCD graphics memory Recommended to be either the length of a row in bytes
56. dRegister The Test Pad register is used to access the on board test pads TP1 TP8 which are connected to unused FPGA pins Table F 6 Test Pad Register TXPAD 0xA000 000A 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 TP8 TP7 TP6 TP5 4 2 1 R W R W R W Bit Name Description TP1 TP3 Test Pins 1 3 These are connected to FPGA I O pins Writing 1 sets the corresponding test pin output to 1 Writing a 0 sets the corresponding test pint output to 0 Reading these bits returns the value at the corresponding test pin input NOTE The FPGA output driver for these signals is always enabled 4 8 Test Pins 4 8 These are connected to FPGA input pins Writing these bits has effect Reading these bits returns the value at the corresponding test pin input LCD Control Register The LCD Control register is implemented as a set clear register and contains four bits for LCD panel control To set a bit set the corresponding bit to 1 when writing to the LCD Control Set register To clear a bit set the corresponding bit when writing to the LCD Control Clear register 58 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Table F 7 LCD Control Register LCDCTRL 0xA000 0012 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 BL RST YN XN R
57. device drawing more than 500 mA USBOPFLT indicates the over current status back to the microcontroller The development board can be either a bus powered USB device or self powered USB device depending on the power supply configuration jumpers When using the development board in USB host mode power to the EVB should be supplied by the In circuit Debugger USB cable or by a 5 V source connected to the DC power jack Note that the LM3S9B96 s USB capabilities are completely independent from the In Circuit Debug Interface USB functionality Debugging Stellaris microcontrollers support programming and debugging using either JTAG or SWD JTAG uses the TCK TMS TDI and TDO signals SWD requires fewer signals SWCLK SWDIO and optionally SWO for trace The debugger determines which debug protocol is used Debugging Modes The LM3S9B96 development board supports a range of hardware debugging configurations Table 2 3 summarizes these configurations Table 2 3 Hardware Debugging Configurations Mode Debug Function Use Selected by 1 Internal ICDI Debug on board LM3S9B96 Default mode microcontroller over Debug USB interface 2 ICDI out to SWD The development board is Remove jumpers on TCk header used as a USB to SWD TMS TDI TDO and PIN1 JTAG interface to an external target 3 In from JTAG SWD header For users who prefer an Connecting an external external debug interface debugger to the JTAG S
58. e Buffers LCD FPGA The FPGA expansion board features a Xilinx Spartan FPGA which interfaces to the Stellaris microcontroller through its EPI port and acts as a crossbar to the rest of the peripherals Camera The Omnivision OV7690 camera provides color VGA images at up to 30 frames per second to the FPGA over 8 bit wide parallel interface It is configured by the Stellaris microcontroller SRAM The 1 MB 8 bit wide 10 ns SRAM is nominally used as a set of frame buffers 16 bits of the 20 bit address space are latched and multiplexed with its data Access time may be dependent on the previous address Configuration PROM A Xilinx standard configuration PROM holds the default FPGA image and automatically uploads it at power on Configuration Pushbutton To reload the configuration PROM image to the FPGA press the configuration pushbutton This allows you to load a new image via JTAG without resetting the rest of the system 52 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Test Port Eight uncommitted FPGA pins are brought to test pads Five of the FPGA pins can only be used as inputs The remaining three FPGA pins can be used as inputs or outputs Camera Connector The camera is hosted by the FPC Connector P1 located to the left of the FPGA To insert or remove the camera first open the latch by grasping either side of the connector and gently lifting straight
59. e page Loading a New Image to the FPGA The FPGA can be re imaged using any of the JTAG tool chains that support the Xilinx Spartan 3e XC3S100e Two standard JTAG interfaces are provided with the FPGA expansion board 2 x 7 with 2mm pitch and 1 x 6 with 1 pitch Once connected your JTAG scan chain should show an XC3S100e FPGA and an XCF01S PROM NOTE Images loaded into the PROM must be set to use CCLK as the startup clock Images loaded direct to the FPGA may use either CCLK or JTAG CLK Figure F 4 FPGA Boundary Scan ISE iMPACT Boundary Scan enex 28 SlaveSerial 22 Direct SPI Configuration amp SystemACE PROM File Formatter xc3s100e video fpga bt IMPACT Processes Available Operations are umb Program 7 Get Device ID Program Succeeded Get Device Signature Usercode gt Check Idcode gt Read Status Register One Step SYF e Boundary Scan Console Programmed successfully PROGRESS END End Operation Elapsed time 0 sec lt Console Errors Warnings Configuration Platform Cable USB 6 MHz usb hs NOTE The LM3S9B96 FPGA boots in JTAG mode but transitions to serial mode once configured by the PROM If your programmer is JTAG only you may need to clear the PROM and power cycle before you can directly program the FPGA via JTAG This issue is rare since most tools support both modes Check with your tool manufacturer for updates September 5 2010 61
60. elopment Board Microcontroller GPIO Assignments on page 37 lists alternative jumper configurations used in conjunction with some of the StellarisWare example applications for this board Table 2 1 Board Features and Peripherals that are Disconnected in Factory Default Configuration Peripheral Jumpers 25 Receive Audio Input JP44 45 47 49 Controller Area Network CAN JP14 15 Ethernet Yellow Status LED LED2 JP2 Analog 3 0V Reference JP33 See Appendix D Stellaris amp LM3S9B96 Development Board Microcontroller GPIO Assignments on page 37 for a complete list of GPIO assignments The table lists all default and alternate September 5 2010 13 assignments that are supported by the 0 1 jumpers and PCB routing The LM3S9B96 has additional internal multiplexing that enables additional configurations which may require discrete wiring between peripherals and GPIO pins The ICDI section of the board has a GND GND jumper that serves no function other than to provide a convenient place to park a spare jumper This jumper may be reused as required
61. eptember 5 2010 Development Kit Contents 10 The Stellaris LM3S9B96 Development Kit contains everything needed to develop and run a range of applications using Stellaris microcontrollers M3S9B96 development board 8 MB SDRAM expansion board EPI signal breakout board Retractable Ethernet cable USB Mini B cable for debugger use USB Micro B cable for OTG to PC connection USB Micro A to USB A adapter for USB Host USB Flash memory stick microSD Card 20 position ribbon cable CD containing A supported version of one of the following including a toolchain specific Quickstart guide Keil RealView Microcontroller Development Kit MDK ARM AR Embedded Workbench Code Sourcery GCC development tools Code Red Technologies development tools Texas Instruments Code Composer Studio IDE Complete documentation Quickstart application source code Stellaris Firmware Development Package with example source code September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Block Diagram Figure 1 2 DK LM3S9B96 Development Board Block Diagram ait gt 0 9 9 9 9 9 9 CQOOOOQOQOQOQOEG _ 9 0 0 9 9 9 9 9 9 9 9 S I O Signal Break
62. exes SWD and JTAG functions and when working in SWD mode provides direction control for the bidirectional data line Virtual COM Port The Virtual COM Port VCP allows Windows applications such as HyperTerminal to communicate with UARTO on the LM3S9B96 over USB Once the FT2232 VCP driver is installed Windows assigns a COM port number to the VCP channel Table 2 4 shows the debug related signals Table 2 4 Debug Related Signals Microcontroller Pin Board Function Jumper Name Pin 77 TDO SWO JTAG data out or trace data out TDO Pin 78 TDI JTAG data in TDI Pin 79 TMS SWDIO JTAG TMS or SWD data in out TMS Pin 80 TCK SWCLK JTAG Clock or SWD clock TCK Pin 26 PAO UORX Virtual Com port data to LM3S9B96 VCPRX Pin 27 PA1 UOTX Virtual Com port data from LM3S9B96 VCPTX Pin 64 RSTn System Reset RSTn Serial Wire Out SWO The development board supports the Cortex M3 Serial Wire Output SWO trace capabilities Under debugger control on board logic can route the SWO datastream to the VCP transmit channel The debugger software can then decode and interpret the trace information received from the Virtual Com Port The normal VCP connection to UARTO is interrupted when using SWO Not all debuggers support SWO See the Stellaris LM3S9B96 Microcontroller Data Sheet for additional information on the Trace Port Interface Unit TPIU Color QVGA LCD Touch Panel The development board features a TFT Liquid C
63. g SWD and JTAG interfaces Table C 1 Debug Interface Pin Assignments Function Pin Number TDI 5 TDO SWO 13 TMS SWDIO 7 TCK SWCLK 9 System Reset 15 VDD 1 GND 4 6 8 10 12 14 16 18 20 No Connect 2 9 11 17 19 Insert Jumper VDD PIN1 Jumper JP57 only when using the development board with an external debug interface such as a ULINK or JLINK September 5 2010 35 36 September 5 2010 Stellaris amp LM3S9B96 Development Board Microcontroller GPIO Assignments Table D 1 shows the pin assignments for the LM3S9B96 microcontroller Table D 1 Microcontroller GPIO Assignments LM3S9B96 GPIO Pin Development Board Use Number Description Default Function Default Use Alt Function Alternate Use 26 PAO UORx Virtual Com Port 27 PA1 UOTx Virtual Com Port 28 PA2 SSIOCIk SPI 29 PA3 SSIOFss SD Card CSn 30 PA4 SSIORx SPI 31 PA5 SSIOTx SPI 34 PA6 USBOEPEN USB Pwr Enable CANORX 35 PA7 USBOPFLT USB Pwr Fault CANOTX 66 PBO USBOID USB OTG ID 67 PB1 USBOVBUS USB Vbus 72 PB2 I2COSCL Audio I2C 65 I2COSDA Audio 12 92 4 ADC10 Potentiometer EPIOS23 EPI Breakout 91 PB5 PB5 LCD RDn 10522 EPI Breakout 90 PB6 PB6 I2STXSCK AVREF Ext Volt Ref 89 PB7 PB7 LCD RST 80 PCO TCK SWCLK JTAG 79 PC1 TMS SWDIO JTAG 78 PC2 TDI JTAG 77 PC3 TDO SWO JTAG 25 4 052 SDRAM 002 0802 24 PC5 EPIOS3 SDRAM
64. ging Modes on page 16 for a description of how to enter ICDI Out mode Figure 4 1 ICD Interface Out Mode JTAG or SWD connects to the external microcontroller Target Stellaris 5 MCU Board lt gt PC with IDE Stellaris 3 3V Remove jumpers to use ICD Out Feature debugger The debug interface operates in either serial wire debug SWD or JTAG mode depending on the configuration in the debugger IDE The IDE debugger does not distinguish between the on board Stellaris microcontroller and external Stellaris microcontroller The only requirement is that the correct Stellaris device is selected in the project configuration The Stellaris target board should have a 2x10 0 1 pin header with signals as indicated in Table C 1 on page 35 This applies to both an external Stellaris microcontroller target Debug Output mode and to external JTAG SWD debuggers Debug Input mode ICDI does not control RST device reset or TRST test reset signals Both reset functions are implemented as commands over JTAG SWD so these signals are usually not necessary September 5 2010 23 24 September 5 2010 Stellaris LM3S9B96 Development Board Schematics This section contains the schematics for the DK LM3S9B96 development board Micro EPI connector USB and Ethernet on page 26 LCD CAN Serial Memory and User I O on page 27 Power Supplies on page 28 25 Audio Expansion Board on page 29 E
65. h and SRAM Memory Expansion Board 41 ELE eh TT 41 et 41 Hardware DescrlptiOn en sn eda tH ERE e rti d ei REA 43 Functional Description 5 2 eter Ree eek de DE dT Pee dE den de Pe eet n Ue 43 Memory Map qiios nere hei states eger EE E edet y a bene nepote RAPERE RIPE eheu do 45 Component locations 46 SCHEMALICS 46 Appendix Stellaris amp LM3S9B96 FPGA Expansion Board escena 49 Feature cce x M IQ 49 Teile mE 50 Hardware Description tc e rh i nie ee Peek dea aix ac bebe RR e RSEN ERR Cepeda as 52 eerte rete ee bep Pepe ebd 52 netiis Ent eet 52 September 5 2010 3 Gontfig ration PROM eir t no iR er ei Ete 52 Configuration PushbUtton 52 Test Polls does he o Sta diete APR S es Amin esi entere redo 53 Camera Connectors ee ee ein ne i ae 53 tet ath ators ih
66. hics Memory Stride R W 60 MPNC 056 9 0 Memory Port Number of Columns R W 60 MPR 058 8 0 Memory Port Current Row R W 60 MPC 9 0 Memory Port Current Column R W 60 MPML 05C 15 0 Memory Port Address Low R W 60 MPMH 05E 4 0 Memory Port Address High R W 60 MPMS 060 11 0 Memory Port Stride R W 60 MPORT 080 15 0 Memory Port R W 61 MEMWIN 400 15 0 Memory Window R W 61 Register Descriptions This section provides the detailed register information for the FPGA expansion board Version Register The Version register communicates the revision numbers of the PCB the FPGA RTL and the Stellaris silicon A dummy write of 0x0000 to this register determines if the Stellaris silicon is revision C or higher and configures the EPI clocking circuit appropriately This is required during initialization for proper operation Table F 2 Version Register VERSION 0xA000 0000 15 14 13 12 11 10 9 8 PCB Board Version 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 RTL Major Version RTL Minor Version R R R R R R R R Bit Name Description PCB Board Version RevC RTL Version September 5 2010 Revision level of the FPGA expansion board This bit is high if the FPGA believes it is communicating with Revision C of the silicon or higher This bit is only valid after being initialized as described above Revision level of the code running in the FPGA expansion board
67. in power rails A 43 3 V supply powers the microcontroller and most other circuitry 5 V is used by the OTG USB port and In circuit Debug Interface USB controller A low drop out LDO regulator U5 converts the 5 V power rail to 3 3 V Both rails are routed to test loops for easy access USB The LM3S9B96 s full speed USB controller supports On the Go Host and Device configurations See Table 2 2 for USB related signals The 5 pin microAB OTG connector supports all three interfaces in conjunction with the cables included in the kit The USB port has additional ESD protection diode arrays D1 D2 D5 for up to 15 kV of ESD protection Table 2 2 USB Related Signals Microcontroller Pin Board Function Jumper Name Pin 70 USBODM USB Data Pin 71 USBODP USB Data Pin 73 USBORBIAS USB bias resistor Pin 66 USBOID OTG ID signal input to microcontroller OTG ID Pin 67 USBOVBUS Vbus Level monitoring VBUS Pin 34 USBOEPE Host power enable active high EPEN Pin 35 USBOPFLT Host power fault signal active low PFLT U6 a fault protected switch controls and monitors power to the USB host port USBOEPEN the control signal from the microcontroller has a pull down resistor to ensure host port power remains off during reset The power switch will immediately cut power if the attached USB device draws September 5 2010 15 more than 1 Amp or if the switches thermal limits are exceeded by a
68. installed onto the EM2 expansion board See the README First document for the EM module you are installing to determine if there is a specific requirement or recommendation for which header the EM module should be installed in If installing a single module and if there is no specific requirement or recommendation in the module s README First document indicating which slot it should be installed in install the single module into the primary EM header MOD1 To install an EM module into the primary module EM slot of the EM2 expansion board do the following 1 Attach any supplied antennas to the EM module 2 Locate the two 20 pin sockets on the back side of the EM module Note the tab on the side of each of the 20 pin sockets This tab denotes pin 1 and aligns with the 20 pin headers on the EM2 expansion board that contain slots near pin 1 for the tab See Figure G 5 for details Figure G 5 Connecting an EM Module to the EM2 Expansion Board Top side of EM2 expansion board Bottom side of EM module 1 189010 94V 0 23 PRIMARY EM HEADER 7 MOD1 4 20 5 on module Primary EM header MOD1 20 pin headers Secondary EM header MOD2 20 pin headers 3 Align the two 20 pin sockets on the EM module over the 20 pin headers on the EM2 expansion board that are within the primary EM silkscreen 72 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual 4
69. ite increments by rows VCQVGA Video Capture is QVGA VGA If set to 0 the video capture controller assumes that the camera is configured for VGA capture If set to 1 it assumes that the camera is configured for QVGA This only affects video capture the camera s 2 and LCD settings must be reconfigured manually VCTEST Video Capture Test When set to 1 the incoming pixel stream is ignored and replaced with a test pattern PCBrA PCB is Revision A An early internal revision of the PCB had a different pin configuration for the camera data port Setting this bit to 1 provides backwards compatibility September 5 2010 Interrupt Enable Register The Interrupt Enable register masks or enables interrupts from the FPGA to the Stellaris Stellaris amp LM3S9B96 Development Kit User s Manual LM3S9B96 microcontroller Masked interrupts will not assert the IRQ line but they will still appear in the Interrupt Status Register Table F 4 Interrupt Enable Register IRQEN 0xA000 0004 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 LRMIE LTEIE LTSIE VRMIE VCFEIE VCFSIE R R R W R W R W R W R W R W Bit Name Description VCFSIE Video capture frame start interrupt enable VCFEIE Video capture frame end interrupt enable VRMIE Video capture row match interrupt enable LTSIE LCD transfer start interrupt enable LTEIE LCD transfer end interrupt enable LRMIE LCD display
70. n specifically indicated in the EM module s README First document CAT24C01 EEPROM The EM2 board contains a 1 Kbit 2 EEPROM which connects to 2 bus separate from the one connected to the EM headers This EEPROM contains data that is used by the software drivers to auto detect that the EM2 expansion board is installed in the system The EEPROM is normally write protected To make the EEPROM writeable install a jumper between pins 2 and 3 of JPS1 125 Header The primary EM header and the secondary EM header each contain connections to separate 6 pin 25 headers J2 and J4 respectively These headers connect to the EM modules only and are not connected to the EPI header which connects to the DK LM3S9B96 See the EM module s documentation for more information on the functionality of this header Analog Audio Header The primary EM header and the secondary EM header each contain connections to separate 4 pin analog audio headers J3 and J5 respectively These headers connect to the EM modules only and are not connected to the EPI header which connects to the DK LM3S9B96 See the EM module s documentation for more information on the functionality of this header SDIO Header The primary EM header contains a connection to 8 pin SDIO header J1 This header connects to the EM modules only and is not connected to the EPI header which connects to the DK LM3S9B96 See the EM module s documentation for more information on the functionality of
71. ng options Integrated In circuit Debug Interface ICDI JTAG SWD and SWO all supported Standard ARM 20 JTAG debug connector USB Virtual COM Port Jumper shunts to conveniently reallocate resources Develop using tools supporting Keil RealView Microcontroller Development Kit MDK ARM IAR Embedded Workbench Code Sourcery GCC development tools Code Red Technologies development tools or Texas Instruments Code Composer Studio IDE Supported by StellarisWare software including the graphics library the USB library and the peripheral driver library Optional expansion boards that work with the External Peripheral Interface EPI of the DK LM3S9B96 development board extend the capabilities of this development platform each board sold separately Stellaris Flash and SRAM Memory Expansion Board DK LM3S9B96 FS8 sold separately Provides Flash memory SRAM and an improved performance LCD interface For more information on the DK LM3S9B96 FS8 memory expansion board see Appendix E Stellaris amp LM3S9B96 Flash and SRAM Memory Expansion Board on page 41 Stellaris amp FPGA Expansion Board DK LM3S9B96 FPGA sold separately Provides machine to machine M2M high bandwidth parallel interface capability of the Stellaris microcontroller Allows users to control and display the FPGA expansion board s video on the DK LM3S9B96 development board s large 3 5 touchscreen display
72. nterface for the FPGA expansion board Writing Your Own Stellaris Application The Stellaris microcontroller communicates with the default FPGA image through a memory mapped interface To get started you must first configure the EPI port by doing the following 1 Configure the GPIO 2 Configure the EPI port and map it into memory at 0xA000 0000 Code Example F 1 Configuring the EPI Port EP IModeSet EPIO BASE EPI MODE GENERAL General Purpose mode EPIDividerSet EPIO BASE 1 Divide system clock by 2 September 5 2010 53 16 Bit data 12 Bit address Use Word Access Mode Use read and write strobe pins Reads take two cycles EPI outputs clock to peripheral Peripheral emits a ready signal Not using frame signal so ignore Not using clock enable so ignore EPIConfigGPModeSet EPIO BASE EPI GPMODE DSIZE 16 EPI GPMODE ASIZE 12 EPI GPMODE WORD ACCESS EPI GPMODE READWRITE EPI GPMODE READ2CYCLE EPI GPMODE CLKPIN EPI GPMODE RDYEN 74 0 0 EPIAddressMapSet EPIO BASE EPI ADDR PER SIZE 64KB EPI ADDR PER BASE A 2 LM3S9B96 FPGA expansion board memory is shown Table F 1 The default Stellaris code maps this into the OxA000 0XXX memory space Detailed descriptions for each regi
73. of Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice is not responsible or liable for any such statements TI products not authorized for use in safety critical applications such as life support where a failure of the product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulat
74. of the CPLD LCD Interface Connector The LCD Interface Connector J2 is a 2x17 socket that connects to headers JP16 JP31 and JP39 on the DK LM3S9B96 All signals previously driven to the LCD from the Stellaris MCU are replaced by equivalent signals driven from the LCD DECODE CPLD DC Regulator DC regulator U4 receives 5 V from the EPI connector and provides 3 3 V for the board LED D1 provides a power indicator and lights when the regulator is providing power to the board 44 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Memory Map The DK LM3S9B96 EXP FS8 expansion board memory map is shown Table E 1 and Table E 2 shows the LCD Latch register Table E 1 Flash and SRAM Memory Expansion Board Memory Map FLASH OX XXX Flash memory 8 Megabytes R W 0x6000 0000 SRAM 10 XXX SRAM 1 Megabyte R W 0x6800 0000 11 000 LCD latch set R W 0x6C00 0000 11 001 LCD latch clear R W 0x6C00 0001 CD 11 010 LCD command port 0x6C00 0002 11 011 LCD data port 0x6C00 0003 ICD 11 110 LCD command port read start R 0x6C00 0006 11 111 LCD data port read start R 0x6C00 0007 a Forreads to the LCD Command and Data Port registers the corresponding LCD Port Read Start register must be read first followed by a 500 nsec delay before reading this register Table E 2 LCD Latch Register Reserved RST YN XN 0 0 0 0 0 R W RW R W
75. oller LM3S9B96 Microcontroller Overview The Stellaris LM3S9B96 is an ARM Cortex M3 based microcontroller with 256 KB flash memory 80 MHz operation Ethernet USB EPI SAFERTOS in ROM and a wide range of peripherals See the LM3S9B96 Microcontroller Data Sheet order number DS LM3S9B96 for complete microcontroller details The LM3S9B96 microcontroller is factory programmed with a quickstart demo program The quickstart program resides in on chip flash memory and runs each time power is applied unless the quickstart has been replaced with a user program Jumpers and GPIO Assignments Each peripheral circuit on the development board is interfaced to the LM3S9B96 microcontroller through a 0 1 pitch jumper shunt Figure 2 1 on page 14 shows the factory default positions of the jumpers The jumpers must be in these positions for the quickstart demo program to function correctly The development board offers capabilities that the LM3S9B96 cannot support simultaneously due to pin count and GPIO multiplexing limitations For example as configured the board does not support SDRAM and 25 receive microphone or line input functions at the same time The jumpers associated with 25 receive are omitted in the default configuration Table 2 1 lists all features and peripherals that are disconnected in the factory default configuration Using these peripherals requires that other peripherals be disconnected Appendix D Stellaris amp LM3S9B96 Dev
76. oller GPIO line Because the FAN5331 B operates in a constant current mode its output voltage will jump up if the LCD should become disconnected To prevent over voltage failure of the IC or diode D3 a zener D4 clamps the voltage The current will limit to 20 mA but the total board current will be higher than when the LCD panel is connected To avoid over heating the backlighting circuit install the BLON jumper to completely shut down the backlighting circuit Power The LCD module has internal bias voltage generators and requires only a single 3 3 V dc supply Resistive Touch Panel The 4 wire resistive touch panel interfaces directly to the microcontroller using 2 ADC channels and 2 GPIO signals See the StellarisWare source code for additional information on touch panel implementation 18 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual 125 Audio The LM3S9B96 development board has advanced audio capabilities using an I S connected Audio TLV320AIC23 CODEC The factory default configuration has Audio output Line Out and or Headphone output enabled Four additional 25 signals are required for Audio input Line Input and or Microphone four audio interfaces are through 1 8 3 5mm stereo jacks Table 2 6 shows the 25 audio related signals Table 2 6 125 Audio Related Signals Microcontroller Pin Board Function Jumper Name I2COSDA CODEC Configuration Dat
77. ory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Audio Amplifiers Data Converters DLP Products DSP
78. qe Clocking The development board uses a 16 0 MHz Y2 crystal to complete the LM3S9B96 microcontroller s main internal clock circuit An internal PLL configured in software multiples this clock to higher frequencies for core and peripheral timing A 25 0 MHz Y1 crystal provides an accurate timebase for the Ethernet PHY 14 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Reset The RESETn signal into the LM3S9B96 microcontroller connects to the reset switch SW2 and to the ICDI circuit for a debugger controlled reset External reset is asserted active low under any one of the three following conditions Power on reset filtered by an R C network W Reset push switch SW2 held down W By the ICDI circuit U12 FT2232 U13D 74LVC125A when instructed by the debugger this capability is optional and may not be supported by all debuggers The LCD module has special Reset timing requirements requiring a dedicated control line from the microcontroller Power Supplies The development board requires a regulated 5 0 V power source Jumpers JP34 36 select the power source with the default source being the ICDI USB connector Only one 5 V source should be selected at any time to avoid conflict between the power sources When using USB in Host mode the power source should be set to either or to EXT 5 V power supply not included in the kit is available The development board has two ma
79. remove the shunt jumpers on JP16 JP31 and the JP39 headers as shown in Figure F 1 on page 49 Place the expansion board on top of the DK LM3S9B96 board and press firmly downward until the board snaps in Connect the the male EPI expansion connector on the bottom side of the FPGA expansion board to the female EPI expansion connector on the DK LM3S9B96 development board J2 The LCD header pins should fit through the holes on the PCB Use the included jumper wire to provide 5 V power to J5 from any of the three upper pins immediately below and to the right of the EXT 5V connector on the development board When powering up the board verify that the power indicator LED 1 is lit September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Figure F 2 Removing EPI Board from DK LM3S9B96 Development Board 5 V Power Lu Remove board B sait Remove POT PB4 jumper Remove JP16 31 jumpers September 5 2010 51 Hardware Description The FPGA expansion board is designed for use with the Stellaris EPI module Figure F 3 shows a simplified system block diagram Components of the default FPGA board are shown in half tone outline Figure F 3 FPGA Expansion Board Block Diagram Stellaris EPI Bus Configuration MED Configuration me MM DM RAM EEPROM Fram
80. ripheral Interface EPI is a high speed 8 16 32 bit parallel bus for connecting external peripherals or memory without glue logic Supported modes include SDRAM SRAM and Flash memories as well as Host bus and FIFO modes The LM3S9B96 development kit includes an 8 MB SDRAM board in addition to an EPI break out board Other EPI expansion boards may be available SDRAM Expansion Board The SDRAM board provides 8 MB of memory 4M x 16 which once configured becomes part of the LM3S9B96 s memory map at either 0x6000 0000 or 0x8000 0000 The SDRAM interface multiplexes DQOO 14 and AD BAO 14 without requiring external latches or buffers Of the 32 EPI signals only 24 are used in SDRAM mode with the remaining signals used for non EPI functions on the board Flash and SRAM Memory Expansion Board The optional Flash and SRAM Memory Expansion Board DK LM3S9B96 FS8 is a plug in for the DK LM3S9B96 development board This expansion board works with the External Peripheral Interface EPI of the Stellaris microcontroller and provides Flash memory SRAM and an improved performance LCD interface For more information on the Flash and SRAM Memory Expansion Board sold separately see Appendix E Stellaris amp LM3S9B96 Flash and SRAM Memory Expansion Board on page 41 FPGA Expansion Board The FPGA Expansion Board DK LM3S9B96 FPGA is an optional expansion board which connects directly to the External Peripheral Interface EPI port of the
81. row match interrupt enable Interrupt Status Register The Interrupt Status register reports and clears interrupts from the camera and LCD systems An interrupt latches its corresponding bit high until cleared by writing a 1 to it Table F 5 Interrupt Status Register IRQSTAT 0xA000 0006 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 LRMI LTEI LTSI VRMI VCFEI VCFSI R R R W R W R W R W R W R W Bit Name Description VCFSI Video capture frame start interrupt Clear the interrupt by setting the September 5 2010 corresponding bit to 1 Setting the bit to 0 has no effect 57 Video capture frame end interrupt Clear the interrupt by setting the corresponding bit to 1 Setting the bit to 0 has no effect VRMI Video capture row match interrupt Clear the interrupt by setting the corresponding bit to 1 Setting the bit to 0 has no effect LTSI LCD transfer start interrupt Clear the interrupt by setting the corresponding bit to 1 Setting the bit to 0 has no effect LTEI LCD transfer end interrupt Set to 1 to clear the corresponding bit Clear the interrupt by setting the corresponding bit to 1 Setting the bit to 0 has no effect LRMI LCD display row match interrupt Clear the interrupt by setting the corresponding bit to 1 Setting the bit to 0 has no effect Memory Page Register The Memory Page register selects to memory page to access Test Pa
82. rystal graphics display with 320 x 240 pixel resolution The display is protected during shipping by a thin protective plastic film which should be removed before use Features Features of the LCD module include Kitronix K350QVG V1 F display 320 x RGB x 240 dots 3 5 262 colors September 5 2010 17 Wide temperature range White LED backlight Integrated RAM Resistive touch panel Control Interface The Color LCD module has a built in controller IC with a multi mode parallel interface The development board uses an 8 bit 8080 type interface with GPIO Port D providing the data bus Table 2 4 shows the LCD related signals Table 2 5 LCD Related Signals Microcontroller Pin Board Function Jumper Name PE6 ADC1 Touch X X PE3 Touch Y Y PE2 Touch X X PE7 ADCO Touch Y Y PB7 LCD Reset LRSTn PDO 7 LCD Data Bus 0 7 LDO 7 PH7 LCD Data Control Select LDC PB5 LCD Read Strobe LRDn PH6 LCD Write Strobe LWRn Backlight control BLON Backlight The white LED backlight must be powered for the display to be clearly visible U7 FAN5331B implements a 20 mA constant current LED power source to the backlight The backlight is not normally controlled by the microcontroller however the control signal is available on a header A jumper may be installed to disable the backlight by connecting it to GND Alternatively a wire may be used to control this signal from a spare microcontr
83. ster are provide in Register Descriptions on page 55 64kB memory space EPI base address is 0xA0000000 NOTE Ten bits are used for addressing but the EPI controller allocates a 12 bit address space The result is that 0 0 00 0000 is equivalent to 00 0400 0x0A00 0800 and 0x0A00 0C00 Table F 1 FPGA Expansion Board Memory Map VERSION 000 15 0 Board and FPGA Design Version R 55 SYSCTRL 002 15 0 System Control R W 56 IRQEN 004 15 0 Interrupt Enable R W 57 IRQSTAT 006 15 0 Interrupt Status R W 57 MEMPAGE 008 10 0 Memory Page R W 58 TPAD 00A 7 0 Test Pad R W 58 010 3 0 LCD Control Set R W LCTRL 58 012 3 0 LCD Control Clear R W CHRMKEY 022 15 0 Chroma Key R W 59 VCRM 026 8 0 Video Capture Row Match R W 59 VML 030 15 0 Video Memory Address Low R W 59 VMH 032 4 0 Video Memory Address High R W 59 VMS 034 11 0 Video Memory Stride R W 59 LRM 036 7 0 LCD Row Match R W 59 LVML 040 15 0 LCD Video Memory Address Low R W 60 LVMH 042 4 0 LCD Video Memory Address High R W 60 LVMS 044 11 0 LCD Video Memory Stride register in bytes R W 60 54 September 5 2010 Stellaris amp LM3S9B96 Development Kit User s Manual Table F 1 FPGA Expansion Board Memory Map Continued LGML 050 15 0 LCD Graphics Memory Address Low R W 60 LGMH 052 4 0 LCD Graphics Memory Address High R W 60 LGMS 054 11 0 LCD Grap
84. this header EPI Signal Descriptions Figure G 1 provides the EPI module s signal descriptions Table G 1 EPI Signal Descriptions PE1 PE1 SPI CS1 Out SPI Chip Select for Primary EM Module PJ4 PJ4 SPI_CS2 Out SPI Chip Select for Secondary EM Module SSH CLK PH4 SPI_CLK Out SPI Clock SSHRx 4 SPI MISO In SPI Receive September 5 2010 75 Table G 1 EPI Signal Descriptions Continued SSHTX PF5 SPI MOSI Out SPI Transmit U1RX PC6 MOD UART TX In Modulator UART TX LM3S9B96 RX U1TX PC7 MOD UART RX Out Modulator UART RX LM3S9B96 TX U1RTS PJ6 MOD UART CTS Out Modulator UART CTS LM3S9B96 RTS U1CTS PJ3 MOD UART RTS In Modulator UART RTS LM3S9B96 CTS I2C1SCL PJO MOD 12 SCL Out Bus to EM Modules I2C1SDA PJ1 MOD 126 SDA Bus to EM Modules I2COSCL PB2 AD I2C SCLO Out Bus to Auto Discovery EEPROM I2COSDA PB3 AD 12 SDAO Bus to Auto Discovery EEPROM 4 4 MOD1_nSHUTD Out Shutdown Reset Signal for Primary EM Module PH5 PH5 MOD2_nSHUTD Out Shutdown Reset Signal for Secondary EM Module PHO PHO MOD1 GPIOO GPIO for Primary EM Module PH1 PH1 MOD1 GPIO1 GPIO for Primary Module PH2 PH2 MOD1 GPIO2 GPIO for Primary Module MOD1 GPIO3 GPIO for Primary EM Module PGO PGO MOD2 GPIOO GPIO for Secondary EM Module PG1 PG1 MOD2 GPIO1 y o GPIO for Secondary EM Module PG7 PG7 MO
85. ties of the Stellaris External Peripheral Interface EPI using the highly integrated DK LM3S9B96 development platform This combination adds full screen motion video to the powerful easy to use StellarisWare amp GUI tools Figure F 1 shows a photo of the FPGA expansion board Figure F 1 FPGA Expansion Board Features The LM3S9B96 FPGA memory expansion board has the following features Xilinx Spartan 3E FPGA with 100k system gates 1 13 CMOS 640 x 480 Color Camera Module 1 MB of asynchronous 10 nsec SRAM for graphics video buffers Standard 1 x 6 and 2 x 5 JTAG headers for FPGA programming 1 kilobit of memory for storing configuration data 8 FPGA test pads provide 5 inputs and 3 I Os All necessary power regulation The default FPGA image adds the following features EPI operation in D16 A12 mode at 50 MHz up to 100 MB s W Graphical on screen display OSD overlaid on moving QVGA video September 5 2010 49 Widget based touchscreen user interface Screen capture to SDCard or USB stick in Windows bitmap BMP format Brightness saturation tint nue and sharpness picture controls Mirror Flip Normal Picture controls Installation To install the expansion board on the DK LM3S9B96 development board do the following 50 1 2 3 Remove the LM3S9B96 FPGA memory expansion board from the antistatic bag On DK LM3S9B96 board remove any installed board on EPI connector J2 On the DK LM3S9B96 board
86. tinued Stellaris amp LM3S9B96 Development Kit User s Manual LM3S9B96 GPIO Pin Development Board Use Number Description Default Function Default Use Alt Function Alternate Use 63 PH5 EPIOS11 SDRAM D11 62 PH6 EPIOS26 LCD WHRn EPIOS26 EPI Breakout 15 PH7 10527 LCD DC 10527 EPI Breakout 14 PJO 0516 SDRAM DQM 87 PJ1 EPIOS17 SDRAM DOM 39 PJ2 EPIOS18 SDRAM CAS 50 PJ3 EPIOS19 SDRAM RAS 52 PJ4 EPIOS28 SDRAM WEn 53 PJ5 EPIOS29 SDRAM CSn 54 PJ6 EPIOS30 SDRAM SDCKE 55 PJ7 PJ7 User Switch September 5 2010 39 40 September 5 2010 APPENDIX Stellaris LM3S9B96 Flash and SRAM Memory Expansion Board This document describes the Flash and SRAM memory expansion board DK LM3S9B96 EXP FS8 plug in for the DK LM3S9B96 development board This expansion board works with the External Peripheral Interface EPI port of the Stellaris microcontroller and provides Flash memory SRAM and an improved performance LCD interface Figure E 1 Flash and SRAM Memory Expansion Board FLASH SRAM LCD IF Features The DK LM3S9B96 EXP FS8 memory expansion board has the following features 8 Megabytes of Flash memory 1 Megabyte of SRAM Memory mapped LCD I F for improved LCD performance 1 kilobit of IC memory for storing configuration data Power LED indicator Installation To install the expansion board on the DK LM3S9B96 development board do the following
87. ucts and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement there
88. up With the latch open the camera moves easily do not force The camera faces away from the FPGA Close the latch by pushing down on it gently before use Caution Handle the camera carefully when inserting or removing it from the board Never force the camera into a different position doing so could damage the camera 5 V Power Pin J5 is used to provide 5 V power to the FPGA expansion board s regulators This must be connected for successful board operation Connect the the male EPI expansion connector on the bottom side of the FPGA expansion board to the female EPI expansion connector on the DK LM3S9B96 development board J2 The LCD header pins should fit through the holes on the PCB 24 MHz Oscillator The camera and the camera interface portion of the FPGA are clocked by a 24 MHz external oscillator External Peripheral Interface EPI Module The External Peripheral Interface EPI module provides a slave interface for use with the Stellaris microcontroller s EPI controller configured in general purpose mode A12 D16 The direction of the signal allocation is in relation to the FPGA for example a signal labeled n is an input to the FPGA a signal labelled Outis an output from the FPGA See Table F 8 on page 63 for a list of the EPI signals NOTE Only 16 bit or 32 bit transfers are allowed for this interface Using the Widget Interface This section provides information about writing your own graphics using the widget i

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