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TSC693E Memory Controller / User`s Manual

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1. 4 DMAADRhbld p jam e EN ERE E EE C S eee PT TT LIL ee t26 t26 111 174 75 74 M 75 40 Jt40 LOW If block transfer gt 137 137 71 78 gt Coa FDI Fig 32 DMA IO Load Rev D 10 Apr 97 36 2 1 5 5 CLK2 SYSCLK AADRtpd DMAADRhold A 81 0 ER A2 If gt ci Tia I SIZE 1 0 2 X m gt A FA0 ALE transfer N IOSEL IOBEN 5 DDIR 14 IOWR OE 5 126 Block transfer BHOLD t27 DE AOE DOE HIGH If block transfer DMAAS EE 174 Block 40 140 DMAREQ LOW If block transfer DMAGNT LOW If block transfer RD TES eet WRT DRDY E 4 1 D 31 0 DMAD1 JOMAD2block tr LEX t23 t24 L CED Fig33 DMA IO Store E i 6 0 MATRA MHS Rev D 10 Apr 97 37 SS F CLK2 SYSCLK 4 0 AADRtpd ADRhdd 31 0 C D4 C XK
2. sos TSC693E TSC693E Memory Controller User s Manual For Embedded Real time 32 bit Computer ERC32 for SPACE Applications MATRA MHS Rev D 10 Apr 97 1 TSC693E TABLE OF CONTENTS Page 1 INTRODUCTION 3 5 Sas gees ane 4 1 1 Nis eL 4 1 2 aasan aspas 5 1 21 Applicable a ade 5 1 2 2 Reference Documents Medos e ea reae 3 1 3 CI OSSA osse e p t 6 1 4 os oue condos 7 14 1 7 1 4 2 oa oae guiadas a ae aes 7 1 4 3 7 2 GENERAL OVERVIEW OF ERC322 8 2 32 OVEry ie Westen edo tr a 8 3 MEMORY CONTROLLER FUNCTIONS 10 3 1 12 2 2 Memory Interfaces 12 3 24 Memory Control SIBngls u oie 12 3 2 12 3 2 2 1 Extended S sto eb Lu 13 32 3 Boot PROM eed tp i A OR late ad UY 14 3453 1 Extended PROM dac 14 3 2 4 Exchange Memory Sun tu 15 222 MINE OT
3. Config WaitSt EDAC LIExXCCV I N Nee 222 Ne Bn uu A Apar L Buffers Timers Bus DMAREQ AsUSizePar Latches EIC Arbiter DMAGNT DatDpar amp Parity General AOE COE DOE checkers purpose IMCti Mpar V J IN Pi C Bhold TN 77 Test Two program _ mable serial RxA RxB Port full duplex J channels PA Ses 2 5 Rev 10 Apr 97 Figure 2 MEC architecture 11 ty tye TSC693E 3 1 Data Types Data type definitions follow the SPARC standard version 7 A byte is 8 bits wide a halfword is 16 bits wide a word 1s 32 bits wide and a double word is 64 bits wide Organization and addressing of data in memory follow the Big Endian convention wherein lower addresses contain the high order bytes For a stored word address N corresponds to the most significant byte and N 3 corresponds to the least significant byte 3 2 Memory Interface 3 2 Memory Control Signals The MEC asserts a system address latch enable signal ALE when the IU address or the DMA address is valid This signal is asserted once in every memory access cycle Four buffer enable signals are provided RAMBEN ROMBEN MEMBEN and IOBEN RAMBEN is asserted during RAM access is asserted during boot PROM access is asserted both during RAM and boot PR
4. EE E TSC693E Access Protection Segment 1 Base Register 01 8 0020 H Access Protection Segment 2 Base Register 01 8 0028 H LE lom Function SEGBASE Segment start address The base address for the segment is calculated according to the formula BASEADDR 0x02000000 SEGBASE 4 0 access protection disabled in user mode 1 access protection enabled in user mode 24 SE 0 0 access protection disabled in supervisor mode 1 access protection enabled in supervisor mode 31 25 Po 0 ______ Newed 1 1 Note The Access Protection is enable only for data write cycles Access Protection Segment 1 End Register 01 8 0024 H Access Protection Segment 2 End Register 01F8 002C H Bits Name Reset value Funcion 0 ow 22 0 SEGEND Segment end address denoting the first address outside the segment The 0x000000 end address for the segment is calculated according to the formula ENDADDR 0x02000000 SEGEND 4 31 23 Interrupt Shape Register 01 8 0044 H Bits Name _________ __ Funcion gt 0 0 0 0 0 0 8 0808 0 0 0 0 4 0 EDGE 00000 External interrupts edge or level triggered r w external interrupt 0 edge triggered external interrupt 0 level triggered 1 external interrupt 1 edge triggered external interrupt 1 level triggered 1xxxx external interrupt 4 edge triggered Oxxxx external interrupt 4 level triggered 7 5 ACK 0
5. sh D 31 0 DPARIO Ubi Fig 26 Load with Busy MATRA MHS Rev D 10 Apr 97 30 TEMI _ _ y CLK2 waiting Store tore SYSCLK AM EDS CCS SAT C sar FA II IOSEL x 9 fal d u NE MDS T 116 BUSRDY 19 IUDATAtpd 120 STD FDS Fig 27 IO Store at 0 waitstates with Busy MATRA MHS Rev D 10 Apr 97 31 E RM 5 CLK2 Addr Waitt gt Busy N 1 Cycl gt Load SYSCLK A 31 0 FAT Lai C F FA2 ALE xxBEN onim L T t26 126 MDS BUSRDY EDATAtpd F h 78 94810 D eee DIARIO Fig 28 Extended Area Load with Busy MATRA MHS Rev D 10 Apr 97 32 jk CLK2 Addr Wait1 Busy waiting Tgtore 1 tore 2 K ra 3 14 4 14 1 5 gt x 1 1 PERS be 15 16 16 a 126 t26 pii ee MDS 38 39 BUSRDY P gt 2 IUDATAtpd IUDATAhoH oe DPARIO C C T 23 gt 124 MEIST 5681 Fig 29 Extended Area Store with Busy MATRA MHS Rev D 10 Apr 97 33 Se
6. NRI EIS 15 3 2 5 1 lod uno 17 3 2 6 MEC Memory aa n anlatan 18 3 3 Interfaces up a a 19 3 4 Bus At DICE 20 3 5 Exeeutiom 20 3 5 1 Reset Mode s once a a 22 3 9 24 Run Mode 22 3 5 3 System Halt Mod E 22 3 5 4 Power Down Mode 23 3 5 5 Error Halt NIOUG 23 3 6 Wait State and Timeout 23 3 7 Memory Access Protection a 24 3 7 1 Uninplemented Areas Goss eh uu uay 24 3 7 2 Write Access Protection 25 3 7 3 Boot PROM Write Protection 26 3 8 Register Access Protection secs en riga n Pe estote 26 3 9 rom 27 3 9 1 Check 28 3 9 2 Syndrome Generator 29 3 9 3 Syndrome Detector esu eh 30 5 10 97 2 VO VO NTC TSC693E 3 9 4 Paule BIG UD 31 3 9 5 Memory and VO aec tti a ege etus dct du 31 3 10 Memory Redundancy nas Sa e o te 32 3 11 Synchronous Traps C y aun
7. o n lt 00 lt lt CLK2 Prioritized eSampled t Latche Taken SYSCLK A 31 0 1 L D31 0 DPARIO 7 Le ex ee es 757 NULL P a t43 28 eee ii 144 145 EXTINT 0 t29 128 INTACK Fig 45 Edge triggered interrupt Timing MATRA MHS Rev D 10 Apr 97 49 gt CLK2 Prioritized Taken gt SYSCLK FA FAS ZU 1772 A 31 0 FACI 141 1414 1 _ 31 0 DPARIO eC CC FDS cec ja soa o0 207 _ T T rj L T TC TL T IT TL T _ EXTINT 0 143 143 EXTINTACK t29 128 INTACK Fig 46 Level triggered interrupt Timing MATRA MHS Rev D 10 Apr 97 50
8. ESI E e um us ee TI 110 MEMCS C i 1 LJ ima HE 2 nexe t25 125 Let DSD2 23 124 9 9 Figure 13 RAM Store Double at 0 WS with exception in 2 nd word MATRA MHS Rev D 10 Apr 97 17 ACCESS OF BYTE 2 AND 1 ARE NOT SHOWN HERE CLK2 SYSCLK A 31 0 T in ii FAS mie 11 ROMCS ROMBEN ee MEMBEN TT TT L oE 1 0 PE 0110 ___ __ MHOLD 111 MDS 78 171 171 122 D 31 0 C FDI C LDBYTEO 121122 DPARIO aree Figure 14 PROM bytewide Load at 2 waitstates MATRA MHS Rev D 10 Apr 97 18 TSC693E Semiconductors CLK2 io CF A 31 0 C s j C s L lll C 0 Tj C p T1 G s 8 8 ARE lI j d ROMCS P MEMBEN 1 ROMBEN 1 fe o o Fol E E 1 1 17 gt 1779 MHOLD 26 26 120 19 D 7 0 FD1 SD1 FD2 Fig 15 PROM Bytewide Store at 1 WS MATRA MHS 19 Rev D 10 Apr 97 CLK2 A 31 0 FA TAI FA2 mu C F
9. asus 32 3 12 Interrupts Asynchronous Traps 33 3 13 General Purpose and Real Time Clock Timers 36 3 14 WY US cde attendee Ga m ole 38 3 15 yau mamam asqa esa a aan 40 3 16 Parity Checkin S ETE 41 3 17 uquna hu 42 3 18 47 3 19 Test mode and Test Access 47 3 19 1 EDAC lila tes 47 3 19 2 Parity ras 47 3 19 3 I t errupt itu ks casas aieiai 47 3 19 4 48 3 19 5 dest Access Port usupa 48 3 20 HL DR 48 3 21 MEG Registers catenin natas eot M 49 3 21 1 Register Address tes HH ans aei ges rper ee evi aped 49 22202 Register Configuration and Allocation 50 4 MEMORY CONTROLLER SIGNAL DESCRIPTIONS 63 4 1 Memory Controller Signal Summary 63 4 2 MEC Detailed Signal Descriptions 65 4 2 1 IU EPU Interface Signals
10. 9 Storg 1 2 SYSCLK Mn Fem m s mm s FAI SESI SAI ir ARR pem TD ALE ica RED od 14 __ 15 E MEMWR2 16 NE NE MDS agis IUDATAhofd Fr 501 23 gt 124 6 0 FCB1 SCB1 FCB2 Fig 23 Exchange Memory Store with Busy and with EDAC and or Parity Protection MATRA MHS Rev D 10 Apr 97 27 I CLK2 Wait1 wait2 _wait3 oad Wait SYSCLK 4 31 0 FA a FA2 mi BEI FA2 ALE OH IOSEL x 134 IOBEN FA3 om t26 MDS t16 178 Otpd gt 471 31 0 DPARIO FDO FD1 LD1 FD2 Fig 24 IO Load at 3 waitstates MATRA MHS Rev D 10 Apr 97 28 CLK2 AG C 2 FA4 IOSEL x ey l o gt gt 1 1 IOWR MHOLD he 15 MDS 16 gt Pt 16 OE 31 0 DPARIO 31 0 FDO FD1 LD1 FD2 FD3 Fig 25 IO Store at 2 waitstates MATRA MHS Rev D 10 Apr 97 29 Rk CLK2 Waiti gt Busy Waiting 1oad Wait 4 SYSCLK 31 0 zm Cr Cr FR FAS ALE IOSEL x LB IOBEN LL id l MDS t16 gt OE 138 139 BUSRDY 78
11. Semiconductors TSC693E CLK2 SYSCLK 4 kes FAD CAT C C T Jj Z 812 1 0 T aud Cj CT _ LL MEMGS 0 MEMBEN DDIR Son t26 t26 BHOLD COE AOE DOE y gt 174 175 75 DMAAS Pr N gt 140 DMAREQ OW If block transfer Ri DMAGNT OW If block transfer RD WRT DRDY Ep pe t25 t25 MEXC t21 E 178 122 010 aK Como C maoo C CB 6 0 Fig36 DMA RAM Load with Uncorrectable error MATRA MHS Rev D 10 Apr 97 40 0 1 2 3 4 N Cycles N i N 4 CLK2 lt _ SYSCLK ASITO payor Een oe p We ER ER pa T _ 126 down mode until any interrupt delected BHOLD Ede e 0 DMAREQ DMAGNT o 143 RED TL on 119 5 120 y 31 0 DPARIO VERS C82 Fig 37 Power down mode after writing to MEC Power Down Register MATRA MHS Rev D 10 Apr 97 41 TEM Logic RESET IDLE Sel IR Sc Capt IR Shift IR Shift IR Shift IR Exit IR _Update IDLE 55 27 TRST TCLK1 159 159 159 58 58 158 TMS 161 leto zx A t62 TDO Fig 38 TAP Control Timing MATRA MHS Rev D 10 Apr 9
12. 09H OBH 09H E M 114 T LH 16 6 5 t20 IUDATAtpd IUDATAhold Fig 19 Register Store MATRA MHS 23 F k CLK2 Addr Wait gt Y dd A 31 0 FAI T m C e ALE B ef 191 112 t11 EXMCS IOBEN la HF E 16 16 gt OE MHOLD MDS BUSRDY p IA EMEMtpd 784 D 31 0 E DPARIO Fig 20 Exchange Memory Load with no Parity or EDAC Protection MATRA MHS Rev D 10 Apr 97 24 CLK2 Addr Wait Ader Wait2 s nvore 1 2 mii ATO FAT Cs 5 D D 5 EE 110 5 T EXMCS E I MEMWR2 EB _ MDS BUSRDY IUDATAtpd IUDATAhold C 501 FD2 23 124 5259 5081 Fig 21 Exchange Memory Store with EDAC and or Parity Protection MATRA MHS Rev D 10 Apr 97 25 F CLK2 Addr Wait Busy 1 WS A 31 0 LAI a al E T 19 EXMCS IOBEN E LE OE MHOLD MDS BUSRDY EMEMtpd 471 78 D 31 0 LD1 FD2 E reed BEABIS Fig 22 Exchange Memory Load Busy with EDAC and or Parity Protection MATRA MHS Rev D 10 Apr 97 26 CLK2 Addr Wait Wait Busy 1
13. Test scan register data output not affected by MODE 4 2 5 UART Interface WDCLK Watch Dog Clock input WDCLK is the WD clock input but this clock can also be used as a clock input for the UART interface The clock frequency of WDCLK must be less than the clock frequency of SYSCLK i e lt RXA Receive Data channel A input RXA is the serial data input for channel A of the UART RXB Receive Data channel B input is the serial data input for channel of the UART TXA Transmit Data channel A output 15 the serial data output for channel A of the UART TXB Transmit Data channel B output TXB is the serial data output for channel B of the UART MATRA MHS Rev D 10 Apr 97 78 ty 02s TSC693E 4 2 6 Power and Clock Signals CLK2 Double Frequency Clock input CLK2 is the input clock to the ERC32 hardware The frequency of this clock must be twice the clock frequency used to clock the IU and the FPU Note that the external timing of the MEC is affected by the duty cycle of CLK2 as some MEC output signals are latched with respect to the edges of CLK2 SYSCLK 1 0 Clock output SYSCLK is a nominally 50 duty cycle clock generated by the MEC from CLK2 and is used for clocking the IU and the FPU as well as other system logic The SYSCLK is used as input clock during MEC slave mode VCCI VCCO Power inputs These pins provide 5 V powe
14. ere ene taedet iae edis 65 4 2 2 Memory System Interface Signals 71 4 2 3 Interrupt and Control Signals 75 4 2 4 Test Acess ah Tob tbe die Ue EM 77 4 2 5 Interface 78 4 2 6 Power and lock Signals pe eoe dea ee 79 5 ELECTRICAL AND MECHANICAL SPECIFICATION 80 5 1 Maximum Rating and DC Characteristics 80 5 1 1 Maximum Rating Sao ee 80 5 1 2 Operating Range 4 ood ba ee SQ 80 5 1 3 DC Characteristics over Operating Range 80 5 1 4 Capacitance ende secte ae 81 5 2 Package idum er deo eee 8l 32 es saa deis Ra ut don 8l 5 2 2 Packase 82 APPENDIX 1 TIMING DIAGRAMS MATRA MHS Rev D 10 Apr 97 3 ty tye TSC693E 1 INTRODUCTION 1 1 Scope This document constitutes a functional specification of iteration two of the TSC693E Memory Controller MEC which is an element in the ERC32 microprocessor core It is intended to function as a User s guide both for the software and hardware developers The document is divided into the following sections GENER
15. Interrupt Acknowledge input INTACK is asserted by the IU when an external interrupt is taken not when it is sampled and latched The MEC will clear the corresponding pending interrupt when INTACK is asserted EXTINT 4 0 External Interrupt input The five external interrupt inputs are programmable to be level or edge sensitive and active high rising or active low falling EXTINTACK External Interrupt Acknowledge output EXTINTACK is for giving acknowledge to an interrupting unit which requires such a signal It is programmable to which of the five external interrupt input it is associated It is issued as soon as the IU has recognized the interrupt by asserting the INTACK signal SYSRESET System Reset input Assertion of this pin will reset the MEC Following this the MEC will then assert RESET for a minimum of sixteen clock cycles SYSRESET must be asserted for a minimum of four clock cycles RESET Reset output will be asserted when the IU and the FPU is to be synchronously reset This occurs when either SYSRESET is asserted or the MEC initiate a reset due to an error or a programming command MATRA MHS Rev D 10 Apr 97 75 TSC693E IUERR IU Error input This input is connected to the ERROR output of the master IU and is asserted when the master IU enters error mode IUHWERR IU Hardware Error input This input is connected to the HWERR output of the
16. The MEC is capable of handling 9 different fault events which all will result in a synchronous trap of the type instruction access exception or data access exception in the IU by assertion of the MEXC signal MATRA MHS Rev D 10 Apr 97 32 ty 2s TSC693E Parity error on control bus This occurs if the MEC detects a parity error on the external control bus Parity error on the data bus This trap occurs if the MEC detects a parity error on the external data bus Parity error on address bus This trap occurs if the MEC detects a parity error on the external address bus Access to protected area This trap occurs if any addressing device performs an access which does not match the memory protection scheme Access to unimplemented area This trap occurs if any addressing device performs an access with invalid address to an unimplemented area MEC register access violation This trap occurs if an illegal access is attempted to an internal MEC register Uncorrectable error in memory The trap occurs if the EDAC detects a non correctable error Bus time out This trap occurs if the ready generation times out i e if during a BUSRDY controlled access BUSRDY is not asserted within 256 clock cycles System bus error This trap occurs if the Bus error BUSERR input is asserted 3 12 Interrupts Asynchronous Traps The MEC handles 15 different events corresponding to asynchronous traps
17. 0 no error 1 0 IU hardware error error 0 no error 2 IUCMP 0 IU comparison error error 0 no error 3 FPUHE 0 FPU hardware error no MEC action error 0 no error 4 0 FPU comparison error error 0 no error 5 MECHE 0 MEC hardware error Internal parity error 0 no error 12 SYSAV 0 ERC32 System availability System available 0 System not available 13 HLT 0 TU FPU halted active 0 not active 15 14 RSTC Reset cause XX 00 system reset 01 software reset 0 error reset 1 watchdog reset 31 16 Note Bit 5 0 are only writeable when the EWE bit in the Test Control Register is set Test Control Register 01F8 0000 EDAC test enable 0 Testing disabled 1 Memory test enabled Parity test r w 1 test enabled 0 test disabled Interrupt Force Register Write Enable 1 enabled 0 disable Error Write Enable 1 Write to Error and Reset Status Register enabled 0 Write to Error and Reset Status Register disabled 31 21 L 271 MATRA MHS Rev D 10 Apr 97 61 TSC693E UART Channel A RX and TX Register 01F8 00E0 H Reset value Function Reserved UART Channel B RX and TX Register 01F8 00E4 H Reset value UART Status Register 01F8 00E8 H rw Data Ready in channel A Transmitter A Holding register Empty ready to load data Transmitter Holding register Empty ready to load data 0 0 Overrun Error in
18. 1 5806 s EXTINTACK 92 255 vccos 5 MHOLD pse 6 FPUHWERR 45 NOpAR 197 __ 8 T J ps __ pe iNTACK jo i 9 e 6 vccoo fa is 107 vccou fs RESET p 7 ios 5 PRD 72 26 ps 105812 2 os __ __ 2 81 VERON iy thee TSC693E 5 2 2 Package Diagram MATRA MHS Rev D 10 Apr 97 82 TSC693E APPENDIX 1 TIMING DIAGRAMS SYSCLK 10 MHz MATRA MHS Rev D 10 Apr 97 TSC693E Figure __ Diagram 6 Store at 1 waitstate with EDAC and or Parity Protection M Load with Correctable Error M Load with Uncorrectable Error M Load at 1 Waitstate with Access Violation M Store at 1 Waitstate with Access Violation M Store at 0 Waitstate with Access Violation RAM Store Byte Halfword with No Error Correctable Error 11 RAM Store Byte Halfword with Uncorrectable Error 2 SISSIES Nn Register Load MEC Register Store Exchange Memory Load with no parity or EDAC protection Exchange Memory Store with EDAC and or parity protection 12 13 1 14 16 17 18 20 1 21 1 22 23 24 5 6 7 8 9 0 1 2 3 4 5 6 7 38 TAP Control Timing Level
19. EDAC uncorrectable error Bus time out System bus error Wathdog meou 10 Ju Ext interrupt4 0 Real time clock interrupt d General purpose timer interrupt Ext Ext interrupt 0 DMA session timeout JU DMA access error _ _ JU U UART error interrupt JU EDACcomecableerr U U UART B data received or transmitter c cer UART A data received or ee 4 Ex inemupt Ext interrupt0 Masked hardware error interrupt u U register updated parity updated SFSR System Fault Status register ERSR Error and Reset Status Register FAR Failing Address Register SFSR is updated at the time of Watchdog interrupt while ERSR is only updated if the Watchdog elapsed causes a halt or reset MATRA MHS Rev D 10 Apr 97 46 ty tye TSC693E 3 18 System Availability The SYSAV bit in the Error and Reset Status Register see page 61 can be used by software to indicate system availability The SYSAV bit 15 cleared by reset and is programmable by software Note that the SYSAV output of the MEC will be asserted only if the SYSAV is set and SYSERR is deasserted i e no error has been detected 3 19 Test mode and Test Access Port The MEC includes a number of test facilities such as EDAC test Parity test Interrupt test Error test and a simple Test Acces
20. FAB pr ITT TT Wr SIZE 1 0 ai C IX 1L 1L L9 j 1 140 10 HL _ 13 IOBEN OE t26 t26 BHOLD m COE AOE DOE 74 e 75 174 e 75 5 Blockjrbnsfer N 40 40 DMAREQ O LOW If block transfer 142 DMAGNT ae rT WRT ee 137 DRDY MEXC 71 78 D 31 0 FD DMAD with Exception FD1 CB 6 0 Fig 34 DMA IO Load with exception MATRA MHS Rev D 10 Apr 97 38 CLK2 SYSCLK 4 jungs 31 0 7 UN ___ C F EAS itc II SIZE 1 0 7 C 19 ALE HM g L N 4 Md _____ MEMBEN e H o Clas 126 126 BHOLD COE AOE DOE gt 174 75 ee DMAAS Bloch gt DMAREQ OW I block transfer 42 DMAGNT OW If block transfer E E T WRT Rae B eL __ __ __ __ __ j X j j j MEXC 121 178 122 00310 7549 C CB 6 0 Fig35 DMA RAM Load with Correctable error MATRA MHS Rev D 10 Apr 97 39
21. Reset 0 Halt FPU Comparison Error Mask Error masked disabled 0 Error not masked Reset or Halt when FPU comparison error Reset 0 Halt HW Error Mask Error masked disabled 0 Error not masked Reset or Halt when MEC HW Error MECHWERR Reset 0 Halt MA DMA Parity Enabled enabled 0 disabled DMA session timeout enabled 0 disabled UART baud rate 1 No change of UART scaler baudrate 0 Divide UART scaler baudrate by two UART parity enable parity enabled 0 no parity UART parity odd parity 0 even parity UART stop bits two stop bits 0 one stop bit UART clock supply system clock 0 external clock UART scaler 1 255 Divide factor 0 stops the UART clock The scaler shall be set to Scaler Clock 32 Baudrate 2 UBR 1 Where Clock is either the frequency of the system clock SYSCLK or the watchdog clock WDCLK selected by UCS bit 23 in MEC Control Register UBR is the value of the UBR bit Baudrate is the desired baudrate Note that the resulting actual baudrate will probably not be exactly the desired one This is due to the fact that Scaler is an integer number and the above given equation may yield a non integer result depending on the Clock frequency MATRA MHS Rev D 10 Apr 97 TSC693E 51 TSC693E Software Reset Register 01 8 0004 H Write only with any data A write to this register will cause the MEC to issue the
22. Setting a bit in IFR will force the corresponding interrupt if it is not masked in IMR MATRA MHS Rev D 10 Apr 97 47 ty tye TSC693E When the interrupt is acknowledged the MEC will automatically clear the corresponding bit in the IFR if this bit is set otherwise it will clear the corresponding bit in the IPR In this way no external interrupts are lost Interrupt test mode is enabled in the Test Control Register see page 61 3 19 4 Error Test The MEC error detection and handling allows fault injection for test purpose By enabling Error test mode in TCR EWE 1 an error could be simulated by writing to the Error and Reset Status Register bits 5 0 3 19 5 Test Access Port TAP The MEC includes a Test Access Port TAP interface IEEE standard 1149 1 for debugging and test purposes The TAP does however not implement any scan function in the present version of the MEC and only implements the Bypass register The timing of the TAP signals is according to IEEE 1149 1 This means that TDI and TMS are sampled by the ERC32 devices on the rising edge of TCK and that TDO is driven on the falling edge Figure 12 removed 3 20 System Clock The MEC provides a system clock signal SYSCLK with a nominal 50 duty cycle for the IU FPU and the rest of the system The system clock is obtained by dividing an external clock signal CLK2 by two Please note that the MEC itself uses both SYSCLK and CLK2 di
23. asserted for 16 SYSCLK cycles RESET D31 0 DPARIO 1 FDO FDA Fig 41 External Error with Reset Timing MATRA MHS Rev D 10 Apr 97 45 CLK2 SYSCLK A 31 0 _FAn 1 FAn FAn i 1 5 70 09H 09H SIZE 1 0 71 10 10 1 ALE XERR 148 SYSERR 126 BHOLD 8 SYSAV A 132 CPUHALT 031 0 7j Fig 42 External Error with Timing MATRA MHS Rev D 10 Apr 97 46 sous dow ane ons TSC693E cycles 18 19 1 20 CLK2 Not all cyclkes is shown SYSCLK A 31 0 7 C EK Fn I ASI 7 0 7 09H 09H 09H __ __ 09H 09H SIZE 1 0 10 10 10 t8 ALE t48 MECHWERR 148 SYSERR SYSAV t32 t32 RESET asserted for 16 SYSCLK cycles RESET D31 0 DPARIO FDO FD4 Fig 43 Internal MEC Error with Reset Timing MHS Rev D 10 Apr 97 47 CLK2 SYSCLK A 31 0 Fani 1 ASI 7 0 09H Ee SIZE 1 0 10 10 MECHWERR 8 SYSERR 126 BHOLD 8 SYSAV m 132 CPUHALT 031 0 7j Fig 44 Internal Error with Timing MATRA MHS Rev D 10 Apr 97 48
24. master IU and is asserted when the IU detects an internal hardware error IUCMPERR IU Comparison Error input This input is connected to the signal of the slave IU in master slave configuration and is asserted when there is a comparison error FPUHWERR Hardware Error input This input is connected to the HWERROR output of the master FPU and is asserted whenever there is an error in the master FPU FPU Comparison Error input This input is connected to the CMPERR signal of the slave FPU in a master slave configuration and is asserted when there is a comparison error MECHWERR MEC Hardware Error output MECHWERR is an output indicating that a hardware error has been detected in the MEC System Error output This output is asserted whenever an unmasked error is set in the ERSR register It stays asserted until the ERSR is cleared The error can originate from either the IU the FPU or the MEC itself SYSERR is used to signal to the system outside the ERC32 based computer MATRA MHS Rev D 10 Apr 97 76 2s TSC693E SYSAV System Availability output This signal is asserted whenever the system is available i e when the SYSAV bit in the ERSR is set and the CPUHALT and SYSERR signals are The SYSAV bit is cleared by reset and is programmable by software SYSHALT System Halt input SYSHALT is used
25. 1 O Address Output Enable CMOS COE 1 Control Output Enable CMOS 1 O Data Output Enable CMOS BHOLD MO MDS Memory Daa Swobe Mos Memory Exception CMOS MATRA MHS Rev D 10 Apr 97 63 Seer er ty tye TSC693E MHOLD 1 0 Memory BusHod CMOS Memory System Interface Signals Memory System Interface Signals BA 1 0 2 Latched Address used 8 bit 16 0 7 0 Check Bits ALE 1 O Address Latch Enable __ 5 PROM8 1 I jSelect amp bit Wide PROM ___ TIL ROMCS 1 0 __ Chip Select CMOS IMEMCS 9 0 0 0 Chip Select CMOS OE 0 2 O jOupuEnble IMEMWRI1 1 0 2 0 Write Strobe CMOS IMEMWR2 1 0 2 O Check Bit Memory Write Strobe CMOS IRAMBEN 1 O RAM Buffer Enable CMOS 1 __ Buffer Enable CMOS IMEMBEN 1 Buffer Enable CMOS DDIR 1 0 Buffer Data Direction CMOS DDIR 1 O Buffer Data Direction CMOS IOSEL 30 4 IO Chip Select CMOS IOWR 1 IO and Exchange Memory Write CMOS Strobe and Exchange Mem Buf Enable CMOS EXMCS 1 0 Exchange Memory Chip Select CMOS IBUSRDY 1 I BuReady 1 TIL IBUSERR jBuEmr rm IDMAREQ 1 1 DMA Request TIL 1
26. Address Register see page 60 in accordance with the conditions in the table IU data fault valid and asynchronous fault valid are implemented in the System Fault Status Register DMA errors will not overwrite the System Fault Status Register if IU data fault valid bit is set If a data access results in an error the Failing Address Register is always updated even if an error has already been latched before With data access is meant an IU operand fetch or a DMA i e the ASI bits indicate an ongoing data load store cycle The following figure shows all possible latching scenarios for the SFSR and FAR registers MATRA MHS Rev D 10 Apr 97 44 Semiconductors TSC693E NO ERROR Synchronous 5s EDAC jo Corectable error etecte All errors cleared detected for DMA All errors cleared by SW by SW for IU and DMA EDAC CORRECTABLE ERROR EDAC Corectable error detected for IU and DMA IU Synchronous data error only Synchronous data error detected for or DMA Each transition will update the SFSR and FAR registers FAR will keep its old value Figure 12 Error Handler Modes MATRA MHS Rev D 10 Apr 97 45 ty E TSC693E The following tables show when updating of the registers is made Control bus parity error Address bus parity error Data bus parity error Memory access protection Unimplemented address violation MEC register violation error
27. DMA has permanent access to the system i e is asserted immediately on DMA request When SYSHALT is deasserted the previous mode is entered MATRA MHS Rev D 10 Apr 97 22 iy 223 TSC693E 3 5 4 Power Down Mode This mode is entered by writing to the Power Down Register see page 52 in the MEC which will cause the MEC bus arbiter to remove the bus ownership from the IU The entering of power down mode must first permitted by programming the MEC Control Register see page 51 In power down mode the MEC asserts and maintains the BHOLD and deasserts and maintains the AOE COE and DOE output signals If an external interrupt is asserted whilst being in power down mode the MEC deasserts the BHOLD and asserts the AOE COE and DOE output signals And thereafter ensures that all data at all inputs to the IU FPU are the same as it was before BHOLD was asserted The IU gets back the bus ownership and the MEC leaves the power down mode The MEC allows DMA accesses during power down mode in which DMA has permanent access to the system i e DMAGNT is asserted immediately on DMA request 3 5 5 Error Halt Mode Error Halt mode is entered under the following circumstances A hardware parity error EDAC uncorrectable error or a comparison error see paragraph 3 17 has occurred The IU enters error mode by asserting the ERROR output In Error Halt mode the CPUHALT and
28. Data xor 00000000000000 1000000000000000000 when 01011101 gt Corrected Data Data xor 0000000000000 10000000000000000000 when 00100011 gt Corrected Data Data xor 000000000000 100000000000000000000 when 00110001 gt Corrected Data Data xor 00000000000 1000000000000000000000 when 01001100 gt Corrected Data Data xor 0000000000 10000000000000000000000 when 01101000 gt Corrected Data Data xor 000000000 100000000000000000000000 when 00010011 gt Corrected Data Data xor 00000000 1000000000000000000000000 when 00110010 gt Corrected Data Data xor 0000000 10000000000000000000000000 when 00110100 gt Corrected Data Data xor 000000100000000000000000000000000 when 01011000 gt Corrected Data Data xor 00000 1000000000000000000000000000 when 01000011 gt Corrected Data Data xor 0000 10000000000000000000000000000 when 01010001 gt Corrected Data Data xor 000100000000000000000000000000000 when 01011011 gt Corrected Data Data xor 001000000000000000000000000000000 when 01101101 gt Corrected Data Data xor 010000000000000000000000000000000 when 00000000 gt Corrected Data Data xor 100000000000000000000000000000000 when 10000000 gt Corrected Data Data xor 000000000000000000000000000000000 no error MATRA MHS Rev D 10 Apr 97 30 ty 02s TSC693E A correctable error is detected 1f Syndrome 7 0 00111000 01000101
29. Extended areas the BUSRDY signal works as a ready signal to tell the accessing unit that data is ready In the Exchange Memory area the BUSRDY signal works as a busy signal to tell the accessing unit that the access can not yet start MATRA MHS Rev D 10 Apr 97 18 ty aos TSC693E 3 3 DMA Interface The MEC supports Direct Memory Access DMA The DMA unit requests access to the processor bus by asserting the DMA request signal When the DMA unit receives the DMAGNT signal in response the processor bus is granted In case the processor is in the power down mode the IU is permanent three stated and a DMAREQ will directly give a DMAGNT The detailed timing for DMA accesses is defined in Appendix A It is possible to enable disable DMA access to the system bus by programming the MEC Control Register see page 51 The default status after system reset is DMA enabled i e permitted If DMA is enabled the MEC asserts BHOLD and deasserts AOE COE and DOE following an DMA Request and then asserts DMA Grant A memory cycle started by the processor is not interrupted by a DMA access before it is finished The following signals shall be used by the DMA unit during the access DMAREQ to be generated by the DMA unit asking for access DMAGNT generated by the MEC when DMA access is granted SYSCLK from the MEC to be used as synchronizing clock A 31 0 ASI 3 0 address and SIZE 1
30. RAM size is performed by programming the Memory Configuration Register see page 52 The default value after system reset is 256 Kbytes It is possible to divide the selected RAM size into one two four or eight equally sized memory blocks by programming the Memory Configuration Register The default value after system reset is one block A memory block is a block composed of 32 bit data parity bit and 7 bit check code and controlled with one chip select signal The MEC provides eight RAM memory chip selects One two four or eight chip selects are possible to use corresponding to the programmed number of memory blocks The default value after system reset is one chip select The MEC also provides two additional RAM chip selects to handle memory redundancy See paragraph 3 10 In the RAM area a store subword byte or half word is implemented as a read modify write since check bits must be generated over the whole word see Figure 3 below CNN NE ND NEN EEN eder eu eli CLK y Store Address A 31 0 IU drives byte store data loads whole word drives new word 31 0 DPARIO Old checkbits MEC drives new checkword CB 6 0 Figure 3 RAM Store Subword sequence 3 2 2 1 Extended RAM In addition to the nominal RAM area an extended RAM area is reserved in the MEC memory map The MEC does not provide any chip select signals for the extended RAM area i e address decoding mus
31. RESET signal if the software reset function is enabled in the MEC Control register If the software reset function is not enabled a write to this register will have no effect Power Down Register 01F8 0008 H Write only with any data A write to this register will cause the system to enter power down mode see paragraph 3 5 4 if the power down function is enabled in the MEC Control Register If the power down function is not enabled a write to this register will have no effect Memory Configuration Register 01 8 0010 H ed F rw RBCS Number of RAM blocks chip selects used 00 lt 0 gt active 01 MEMCS lt 1 0 gt active 10 MEMCS lt 3 0 gt active 11 MEMCS lt 7 0 gt active Redundant RAM blockO selected 0 not selected 1 selected Redundant RAM block0 can replace of the RAM blocks The MEMCS corresponding to the replaced block will be inactive and MEMCS lt 8 gt will be active instead 000 MEMCS lt 0 gt inactive and replaced 001 lt 1 gt inactive and replaced 010 MEMCS lt 2 gt inactive and replaced 011 MEMCS lt 3 gt inactive and replaced 100 MEMCS 4 inactive and replaced 101 lt 5 gt inactive and replaced 110 MEMCS lt 6 gt inactive and replaced 111 MEMCS lt 7 gt inactive and replaced p 0 Redundant RAM block selected 0 not selected 1 selected p 1 Redundant RAM block can replace any of the RAM blocks The MEMCS correspondin
32. SCALER is a counter to adjust the step size in which COUNTER does the actual time count COUNTER is a counter to actually count time in steps as set by the value in SCALER COUNTER is decrements when SCALER reaches zero The implementation is shown in Figure 6 Timer function Set Preload The Scaler Set Preload The Counter SYSCLK Interrupt Zero indication Control Enable Load Reload Hold Stop at zer o Figure 6 Timer implementation Both timers are clocked by the internal system clock The timers are programmable by writing to the Timer Control Register see page 59 They are possible to program to be either of single shot type or periodical type in both cases generate an interrupt when the delay time has elapsed If the timer is not programmed with a new value when set to periodical type it restarts from the latest programmed value and continue to count down thus generating interrupts periodically The Real Time Clock Timer interrupt has higher priority than the General Purpose Timer interrupt It is possible to halt and restart the timers by writing to the Timer Control Register The only functional difference between the two timers is that the Real Time Clock Timer has an 8 bit scaler while the General Purpose Timer has a 16 bit scaler providing a wider range While the signal CPUHALT is active timers are temporary halted MATRA MHS Rev D 10 Apr 97 36 ty tye TSC
33. The MEC allocates each specific interrupt to an interrupt level The interrupt allocation is in accordance with the scheme in Table 5 page 35 The following interrupts representing asynchronous traps asserts the Interrupt Request Level IRL inputs of the processor Watch Dog time out This interrupt occurs if the watchdog timer times out DMA time out This interrupt occurs if the DMA session exceeds permitted time MATRA MHS Rev D 10 Apr 97 33 ty tye TSC693E DMA access error This interrupt occurs if the DMA performs an access violation or illegal access UART error This interrupt is generated by the UARTS if an error is detected UART A and B Data Ready or Transmitter Ready These interrupts are generated by the UARTS each time a data word has been correctly received and each time a data word has been sent Real Time Clock This interrupt is issued by the real time clock timer tick General purpose timer This interrupt is issued by the general purpose timer Correctable error in memory This interrupt occurs if the EDAC detects and corrects an error Masked Hardware Errors This occurs when there is a hardware error set in the Error and Reset Status Register see page 61 and the error is masked an unmasked hardware error leads to an Error Halt or Warm Reset instead of an interrupt see paragraph 3 5 5 external individually prioritized interrupts The sources of these interrup
34. Triggered Interrupt Timing 2 2 2 2 2 3 3 3 3 3 3 3 3 39 40 42 43 44 45 46 MATRA MHS Rev D 10 Apr 97 TSC693E 56 _ SYSCLK period CLK2 high and low pulse width 5 8 CIR period t4 15 Address Input Setup Time SYSCLK s 4 Address Input Hold Time SYSCLK pe ASI 7 0 SIZE 1 0 RD WRT WE LOCK LDSTO DXFER Input Setup SYSCLK Time died ASI 7 0 SIZE 1 0 RD WRT WE LOCK LDSTO DXFER Input Hold SYSCLK Time T ooo SYSCLK SYSCLK sBs 15 ALE Output Delay 20 Address Valid to MEC Internal Chip Select Delay t10 15 MEMCS 9 0 ROMCS EXMCS Maximum Clock to SYSCLK tll 1 MEMCS 9 0 ROMCS EXMCS Minimum Clock to SYSCLK t12 MEMCS 9 0 ROMCS EXMCS Output Latch t13 35 MEMBEN RAMBEN ROMBEN Output Delay CLK2 lo gt hi ua 35 DDR Output Delay us 35 MEMWRI MEMWR2 IOWR Output Delay t16 35 OE Output Delay CLK2 lo gt hi ES 17 20 _ Boot PROM Address BA Output Delay t18 30 IOSEL 3 0 Clock to Output Delay SYSCLK lo gt hi SYSCLK hi gt lo 19 0 Data Setup Time During Store 020 Hold Time During Store 1 120 Data and DPARIO Maximum Output Delay 22 2 MEC Data and DPARIO Valid to High Z Delay 23 35 _ Output Maximum Delay 4 2 CB Outpu Valid to High Z Delay 25 _ 20 __ MEX
35. WDCLK Clock Period Time 00 166 35 ____ generation Time including Output Delay Data Valid B 2 ExtHold ExtCCV Input Setup CT io j 20 SYSCLK High Output Delay 70 20 SYSCLK to High OutputDelay CLK2 3 Data and checkbits Setup Time duringload Data Valid to MHOLD Delay when MEC checks parity Data Valid and checkbits For the chip select timing the following formula applies If address valid before SYSCLK gt 19 then chip select output delay time 10 else chip select output delay time t9 t12 DOE is deasserted on SYSCLK during store byte halfword Abreviations used in the timing diagrams FAn Fetch address n LAn Load address n SAn Store address n TAn Trapp address n FDn Fetch data n LDn Load data n SDn Store data n TDn Trapp data n MATRA MHS Rev D 10 Apr 97 Semiconductors SYSCLK MATRA MHS Rev D 10 Apr 97 TSC693E Figure 1 CLK2 to SYSCLK Skew Semiconductors TSC693E 0 1 2 3 CLK2 SYSCLK A 31 0 ee 42212 417754 t10 MEMCS 0 t10 dL ud t11 MEMCS 1 3AMBEN MEMBEN DDIR MEMWR1 MEMWR2 t20 t7 7 119 r PO PEABO 8071 CL CB 6 0 t23 t24 Figure 2 RAM Load Store Sequence at 0 Waitstates wit
36. and asserted high for read accesses WE Write Enable input is asserted by the integer unit during the cycle in which the store data is on the data bus For a store single instruction this is during the second store address cycle the second and third store address cycles of store double instructions and the third load store address cycle of atomic load store instructions It is sent out unlatched and is latched in the MEC before it is used To avoid writing to memory during memory exceptions WE is internally qualified MHOLD and MEXC unit must supply this signal during a DMA session asserted low for write and deasserted high for read accesses MATRA MHS Rev D 10 Apr 97 68 ty tye TSC693E WRT Advanced Write input WRT is an early write signal asserted by the processor during the first store address cycle of integer single or double store instructions the first store address cycle of floating point single or double store instructions and the second load store address cycle of atomic load store instructions WRT is sent out unlatched and is latched in the MEC before it is used A DMA unit must supply this signal during a DMA session deasserted low for read and asserted high for write accesses IMPAR IU to MEC Control Parity input This input is used by the MEC to check the odd parity over the LDSTO DXFER LOCK WRT RD and WE signals This signal must be driven by the DMA if
37. and generation The default is no parity is implemented for the I O units Since the I O unit never includes EDAC check bits the store subword half word or byte instruction in the I O area is different from the store subword in the RAM area In the RAM area a store subword is implemented as a read modify write since check bits must be generated over the whole word In the I O area a store subword is implemented as a store word from a timing point of view but the subword byte or halfword is repeated by the IU on the other subwords in the full word see Figure 4 MATRA MHS Rev D 10 Apr 97 16 Semiconductors STORE BYTE STORE HALF WORD 3 2 5 1 Extended I O DATA BIT 16 8 d TSC693E SAME DATA AS ON BITS SAME DATA AS ON BITS SAME DATA AS ON BITS IU DATA SAME DATA AS ON BITS 15 0 IU DATA Figure 4 Store Subword Data Layout In addition to the nominal I O area an extended I O area is reserved in the MEC memory map The MEC does not provide any chip select signals for the extended I O area i e address decoding must be implemented with external logic The extended I O area is BUSRDY controlled with the same number of waitstates as the nominal I O area The number of waitstates is however always at least one even if the I O area waitstate value has been programmed to zero The same no of waitstates and parity option as for I O area 3 apply MATRA MHS
38. as buffer enable for data and check bit buffers in the RAM and boot PROM areas if RAM and boot PROM share the same buffers DDIR Data Direction output DDIR is used for determining the direction of the data buffers connected between the local ERC32 bus and the ERC32 system bus The DDIR is asserted when the data flows from the local bus to the system bus i e during write operations It is valid during all memory accesses DDIR Data Direction output DDIR is used for determining the direction of the data buffers connected between local ERC32 bus and ERC32 system bus The DDIR is asserted when the data flows from the local bus to the system bus i e during write operations It is valid during all memory accesses IOSEL 3 0 IO Chip Select output These four select signals are used to enable one of four possible I O address areas IOWR IO Write output IOWR is asserted during write operations to the I O area extended I O area and the exchange memory area MATRA MHS Rev D 10 Apr 97 73 ty 2s TSC693E IOBEN IO Buffer Enable output IOBEN is asserted during I O access extended I O area extended general area and exchange memory access in order to enable the data buffers for the I O and exchange memory EXMCS Exchange Memory Chip Select output EXMCS 15 asserted when the exchange memory is accessed BUSRDY Bus Ready input is to be generated by a unit
39. bit general purpose timer with 16 bit scaler One 32 bit timer with 8 bit scaler Real Time Clock UART function with two serial channels Built in concurrent error detection including support for master slave checking of IU and FPU System error handler Parity control on system bus Test support including a minimal TAP interface The MEC interfaces directly to the address data and control buses of the IU and FPU requiring no additional components It also interfaces directly to external memory and units only requiring additional buffers for the address and data bus The architecture of the MEC is illustrated in Figure 2 MATRA MHS Rev D 10 Apr 97 10 Semiconductors TSC693E MEC Architecture ExtIntack CLK Reset ExtINT 4 0 Errors EDS x AK N Interrupt amp v Cpuhalt sysreset Support Error handler Startup Ctrl Internal Interrupt SysAv MecErr Reset gen External Iterrupt XR WDCLK _ Clock gen Failing Registers Power Down Error Reset Halt J INTACK 07 P m2 7 N System Bus Interface P DEREN 442 N MemCS 4 Address Access Access ROMCS decoder Protect Control Rc Busrdy IOSel NoPar 7 prc s oe C MDS ExtHOLD aM y 3
40. i t 78 gt PEER C Figure 6 RAM Load with Uncorrectable Error at 0 WS MATRA MHS Rev D 10 Apr 97 10 CLK2 SYSCLK 31 0 FR ai C T ALE E i j u RAMBEN MEMBEN ERU t16 116 t16 OE MHOLD till MDS En 125 125 MEXC D 31 0 DPARIO FDI FD CB 6 0 Figure 7 RAM Load at 1 Waitstate with Access Violation MATRA MHS Rev D 10 Apr 97 11 Semiconductors CLK2 SYSCLK A 31 0 ALE MEMCS 0 MEMBEN DDIR 1 2 MHOLD MDS MEXC 31 0 DPARIO Rev 10 Apr 97 TSC693E O lba t25 t25 Due to the violation no data is stored FD1 SD1 FD2 Figure 8 RAM Store at 1 waitstate with Access Violation Semiconductors CLK2 SYSCLK A 31 0 ALE MEMCS 0 RAMBEN MEMBEN DDIR 1 2 MHOLD MDS MEXC D 81 0 DPARIO MATRA MHS Rev D 10 Apr 97 TSC693E ko SM SAT La t25 t25 Due to the violation no data is stored 501 FD2 TDi Figure 9 RAM Store at 0 waitstate with Access Violation 13 CLK2 SYSCLK 31 0 SH SA C SH C SH K SAL SIZE 1 0 i d j 10 0001 00
41. in the I O area exchange memory area or in extended areas which requires extended time when accessed in addition to the preprogrammed number of wait states Note however that waitstates can not be preprogrammed for units in the extended general area only for extended I O boot PROM and RAM BUSERR Bus Error input is to be generated together with BUSRDY by a unit in the I O area exchange memory area or in the extended areas if an error is detected by the accessed unit during an access DMAREQ DMA Request input DMAREQ is to be issued by a unit requesting the access to the processor bus as a master DMAGNT DMA Grant output DMAGNT is generated by the MEC as a response to DMAREQ DMAGNT is sent after that the MEC has asserted BHOLD and deasserted AOE DOE and COE for holding and three stating the IU MATRA MHS Rev D 10 Apr 97 74 TSC693E 4 2 3 Interrupt and Control Signals IRL 3 0 Interrupt Request Level output The state of these pins defines the Interrupt Request Level IRL IRL 3 0 0000 indicates that no external interrupts are pending and is the normal state of the IRL pins IRL 3 0 1111 signifies a nonmaskable interrupt All other interrupt levels are maskable by the Processor Interrupt Level PIL field of the Processor State Register PSR External interrupts are latched and prioritized by the MEC before they are passed to the IU INTACK
42. outputs of MEC are asserted note that SYSERR is also asserted if a masked error occurs even though Error Halt mode is not entered in this case All timers are halted and the UART operation is stopped in this mode The only way to exit Error Halt Mode is through Cold Reset by asserting SYSRES The MEC allows DMA accesses during error halt mode in which DMA has permanent access to the system i e is asserted immediately DMA request Error Halt Mode can be induced by software by first setting the EWE bit in the Test Control Register see page 61 and then write an error to the Error and Reset Status Register see page 61 Note however that this also requires that the Reset Halt bit for the chosen error is set to halt in the MEC Control Register 3 6 Wait State and Timeout Generator It is possible to control the wait state generation by programming a Waitstate Configuration Register see page 55 in the MEC The maximum programmable number of wait states is applied as default at reset MATRA MHS Rev D 10 Apr 97 23 ty 02s TSC693E It is possible to program the number of wait states for the following combinations RAM read RAM write PROM read PROM write i e EEPROM write EXM read write i e Exchange memory read write Four individual I O peripherals read write The MEC supports wait state generation by asserting the MHOLD output in the second memory access cycle
43. receiver MATRA MHS Rev D 10 Apr 97 62 ty 02s TSC693E 4 MEMORY CONTROLLER SIGNAL DESCRIPTIONS 4 1 Memory Controller Signal Summary Table 6 lists the MEC signals They are listed according to the signal name the number of pins allocated the input 1 output O operating modes a signal description if it is protected by parity P and the classification and grouping related to electrical characteristics An asterisk after the signal name indicates that the signal is active low true at a logic 0 level Table 6 MEC Signal Summary IU FPU Interface Signals 10 32 I AddressBus Tr APAR I Address Bus Parity ASI3 0 4 I Address Space Identifier SIZE 0 2 I j BusTranacionSize PTTL ASPAR 1 1 JASlandSIZEPaiy rr 3 0 322 TIL CMOS 1 10 DataBusPariyInpu Ouput TTL CMOS DMAAS 1 1 DMA Address Strobe DRDY O during DMA access TTL EXTHOLD 1 I Hold FHOLD TTL EXTCCV 1 1 External CCV Input rr NULL I Integer Unit Cycle TTL DXFER 1 I Transfer LDSTO 1 1 Lock 1 1 PTT RD Read Access WE Write Enable TIL WRT JjAdvacedWrte IMPAR I _ IU to MEC Control Parity rr AO
44. see page 54 The default status after system reset is that DMA parity is disabled If DMA parity is enabled it has to be generated during write and possibly checked by the DMA during read If DMA parity is not enabled the MEC generates the parity bit to be stored in the memory in case of write accesses Memory access protection is active also during DMA i e attempted write access to protected memory segments will lead to a memory exception depending on how the ASI bits are driven by the DMA unit user or supervisor mode Normally the same restrictions apply to DMA access of MEC registers as for the IU in User mode see page 49 However during system halt i e CPUHALT signal active the DMA has the same access rights as the IU in supervisor mode for MEC register access With register write access memory protection could be changed to permit DMA to access all areas The MEC includes a DMA session timeout function preventing the DMA unit to lockout the IU FPU by asserting DMAREQ for a long time If the DMA Request input is not deasserted within 1024 system clock cycles after the assertion of DMA Grant the memory exception output is asserted and the DMA Grant is removed The DMA session timeout function is possible to enable or disable by programming the MEC Control Register see page 54 After system reset the timeout function is enabled Note that the session timeout function 15 not the same as a bus timeout rather an session sche
45. 0 WRT WE RD DXFER LDSTO LOCK to be generated by the DMA unit SIZEO and SIZEI to be driven by the DMA during DMA transfers Note that only word transfers are allowed in DMA mode which means that the values of the size bits must always be driven to SIZEO 0 and SIZE1 1 in DMA mode APAR ASPAR and IMPAR parity bits to be generated by the DMA unit in case parity is enabled for the DMA D 31 0 data generated by the DMA unit in case of write cycle or fetched by the DMA unit during read cycle DPARIO data parity to be generated and possibly checked by the DMA unit in case parity is enabled for the DMA DMAAS line used for address strobe to be generated by the DMA unit when the address is valid Assertion of this signal will initiate the memory access DRDY line used for indicating data ready for DMA unit or data written on write It is generated by the MEC generated by the MEC indicating a memory access exception when no valid data can be supplied from the memory system e g access violation or error If no subsequent DMA cycles are to be issued the DMA unit shall remove the DMAREQ signal as soon as it has fetched the data on read after that it has received MATRA MHS Rev D 10 Apr 97 19 ty 22s TSC693E DRDY or when DRDY is removed on write The MEC will then remove the DMAGNT signal It is possible to enable disable DMA parity by programming the MEC Control Register
46. 00 Acknowledge on external interrupt r w 000 No action 001 external interrupt 0 acknowledged 010 external interrupt 1 acknowledged 011 external interrupt 2 acknowledged 100 external interrupt 3 acknowledged 101 external interrupt 4 acknowledged 110 No action 111 No action 12 8 POL 00000 External interrupts polarity xxxxl external interrupt 0 active high external interrupt 0 active low xxx1x external interrupt 1 active high external interrupt active low 1xxxx external interrupt 4 active high Oxxxx external interrupt 4 active low 31 13 Interrupt Pending Register 01 8 0048 H Bits Name Resetvale Funcion 0 00 0 0 0 0 vw Reserve Pending interrupts bit 1 1 interrupt 1 pending bit 1 0 interrupt 1 not pending bit 15 1 interrupt 15 pending bit 15 0 interrupt 15 not pending 31 16 MATRA MHS Rev D 10 Apr 97 56 aos TSC693E Interrupt Mask Register 01F8 004C H Function Reserved Not used Hr 1 IM Masked interrupts r w bit 1 1 interrupt 1 masked bit 1 0 interrupt 1 not masked bit 14 1 interrupt 14 masked bit 14 0 interrupt 14 not masked r 31 15 Interrupt Clear Register 01F8 0050 H Name e tin o Reserved Not used I 1 15 1 Ic Cleared interrupts bit 1 1 interrupt 1 cleared bit 1 2 0 interrupt 1 not cleared bit 15 1 in
47. 001 when 01000101 gt Corrected Data Data xor 000000000000000000000000000000010 when 01010100 gt Corrected Data Data xor 000000000000000000000000000000 100 when 00010110 gt Corrected Data Data xor 000000000000000000000000000001000 when 00011111 gt Corrected Data Data xor 000000000000000000000000000010000 when 00100101 gt Corrected Data Data xor 000000000000000000000000000 100000 when 00100110 gt Corrected Data Data xor 00000000000000000000000000 1000000 when 01001010 gt Corrected Data Data xor 0000000000000000000000000 10000000 when 00101111 gt Corrected Data Data xor 000000000000000000000000 100000000 when 00111011 gt Corrected Data Data xor 00000000000000000000000 1000000000 when 00111101 gt Corrected Data Data xor 0000000000000000000000 10000000000 when 01100001 gt Corrected Data Data xor 000000000000000000000 100000000000 when 00011010 gt Corrected Data Data xor 00000000000000000000 1000000000000 when 00101010 gt Corrected Data Data xor 000000000000000000010000000000000 when 00101100 gt Corrected Data Data xor 000000000000000000100000000000000 when 01001111 gt Corrected Data Data xor 00000000000000000 1000000000000000 when 01000110 gt Corrected Data Data xor 000000000000000010000000000000000 when 01010010 gt Corrected Data Data xor 000000000000000100000000000000000 when 01100100 gt Corrected Data
48. 01 0001 0001 10 2 cJ emere enge ds nt 111 MEMCS 0 Ex e cp E p qusc TC Pi s de hr 120 178 31 0 s ds 21 22 n FDO FDI IU drives subword C Olddata FD2 t78 CB 6 0 23 124 Figure 10 RAM Store Byte Halfword with No Error Correctable Error MATRA MHS Rev D 10 Apr 97 14 CLK2 SYSCLK 31 0 0 LEN SH S SIZE 1 0 E 0001 0001 09 01 D 5 TI LIP MEMCS 0 a ina t20 t78 31 0 DPARIO 13 121 FDO FD1 U drives subword Old data Ney data FD2 178 7 23 124 229 Css FCEZ Figure 11 RAM Store Byte Halfword with Uncorrectable Error MATRA MHS Rev D 10 Apr 97 15 CLK2 pa 1 m1 AM Cose 55 55 55 C Te FAS ae cru uc r ue 09 1 oU 1 K T 1 jJ j 9 111 MEMCS 1 pa 1 MEMWR2 a i EN SN its 126 126 120 19 20 19 por X 23 124 Figure 12 RAM Store Double at 0 WS MATRA MHS Rev D 10 Apr 97 16 0 1 2 3 4 5 CLK2 SYSCLK d EL ey s cp t 9 ski T ee Dsa2 Cim CE j
49. 01010100 00010110 00011111 00100101 700100110 01001010 1 00101111 1 00111011 00111101 01100001 00011010 1 00101010 00101100 01001111 01000110 01010010 1 01100100 01011101 00100011 00110001 01001100 1 01101000 00010011 00110010 00110100 01011000 1 01000011 1 01010001 01011011 01101101 00000000 10000001 10000010 10000100 10001000 10010000 10100000 11000000 The non correctable error is detected if Syndrome 7 0 are not equal to 00111000 01000101 01010100 I 00010110 00100101 00100110 01001010 1 00101111 1 00111011 00111101 01100001 00011010 1 00101010 00101100 01001111 01000110 01010010 01100100 01011101 00100011 00110001 01001100 01101000 00010011 00110010 00110100 01011000 01000011 1 01010001 01011011 01101101 00000000 10000001 10000010 10000100 10001000 10010000 1 10100000 1 11000000 10000000 00011111 3 9 4 Fault Injection Moved to paragraph 3 19 3 9 5 Memory and I O Parity The MEC handles parity towards memory and I O in a special way The MEC can be programmed to use no parity only parity or parity and EDAC protection towards memory Towards I O the MEC can be programmed to use no parity or only parity The signal used for the parity bit is DPARIO This
50. 693E The Real Time Clock Timer see page 58 is implemented as one down counting 8 bit scaler and one down counting 32 bit counter The current value of the scaler and counter of the Real Time Clock can be read The timer scaler load value is programmable in Real Time Clock Program Register lt Scaler gt see page 58 The timer count load value is programmable in Real Time Clock Program Register Counter see page 58 The value of these registers will not be altered unless reprogrammed or reset After system reset the Real Time Clock is not running and must be programmed as required The General Purpose Timer see page 58 is implemented as one down counting 16 bit scaler and one down counting 32 bit counter The current value of the scaler and counter of the General Purpose Timer can be read The timer scaler load value is programmable in General Purpose Timer Program Register lt Scaler gt see page 58 The timer count load value is programmable in General Purpose Timer Program Register Counter see page 58 The value of these registers will not be altered unless reprogrammed or reset After system reset the General Purpose Timer is not running and must be programmed as required MATRA MHS Rev D 10 Apr 97 37 ty 02s TSC693E 3 14 Watch Dog The watch dog function consists of a Watchdog Timer see page 57 The watch dog is supplied from a separate external input WDCLK which must have a frequency whic
51. 7 42 Semiconductors TSC693E 1 2 4 5 15 cycles 17 18 19 CLK2 All clocks are shown SYSCLK oen Esp oH f 09 H SIZE 1 0 E 136 35 INULL 30 gt 31 30 SYSRESET 49 eee eck ee S TE es J J 49 see 8 IU Boot using 40 bit PROM 132 132 _ is asserted for 16 SYSCLI RESET Fig 39 Reset Timing MATRA MHS Rev D 10 Apr 97 43 Semiconductors lEMIC TSC693E CLK2 SYSCLK A 31 0 7 ASI 7 0 cj T oH SIZE 1 0 C elo C10 LII ALE 130 1305 131 t31 SYSHALT t26 BHOLD 148 148 SYSAV 132 132 CPUHALT D31 0 DPARIO 7 Fig 40 Halt Timing MATRA MHS 44 Rev D 10 Apr 97 5222 TSC693E __p _ _1_ gt FU P _ HVHHI cycles 1s hh _ 20 P CLK2 Not all cyclkes is shown SYSCLK A 31 0 1 EAn 4H ASI 7 0 sa 127 SIZE 1 0 10 Jel 122 10 ALE Iet46m 147 9 XERR 148 sysay 132 132 RESET
52. AL OVERVIEW OF ERC32 A short overview of a typical ERC32 based system TSC693E MEMORY CONTROLLER FUNCTIONS Detailed description of the MEC functions including software interface TSC693E MEMORY CONTROLLER SIGNAL DESCRIPTIONS Functional description of MEC signals TSC693E ELECTRICAL AND MECHANICAL SPECIFICATION TIMING DIAGRAMS APPENDIX 1 Timing specifications and diagrams MATRA MHS Rev D 10 Apr 97 4 ty 02s TSC693E 1 2 Documents 1 2 1 Applicable Documents ADI AD2 AD3 AD4 12 2 RD2 RD3 MATRA MHS ESA 32 Bit Microprocessor and Computer Development Programme Statement of Work WDI JG 1317 NL Issue 2 1 28 05 1991 Specification for a 32 bit embedded computing core ERC32 WDI JG 1334 NL Issue 3 29 05 1991 32 bit Microprocessor Software Tools Technical Requirements WDI 1339 FGM NL 05 06 1991 ERC32 Technical Specification MCD SPC 0001 SE issue 7 1 Apr 1994 Reference Documents SPARC Standard Version 7 TSC691E Integer Unit TSC692E Floating Point Unit User s Manual Rev D 10 Apr 97 5 ty 02s TSC693E 1 3 Glossary AD Applicable Document ASI Address Space Identifier ATAC Ada TAsking Coprocessor CS Chip Select DMA Direct Memory Access EDAC Error Detection And Correction EEPROM _ Electrically Erasable Programmable Read Only Memory ERC32 32 bit Embedded Real time Computing Core EXM EXchange Memory FAR Failing Addres
53. ALE ua s ROMCS 113 gt 13 gt MEMBEN 4 ROMBEN Mis _ c ede sir RAMBEN DDIR 16 gt 19 gt DENEN E 106 137 MDS 178 PROMtpd UIL1 31 0 DPARIO FDO LD1 FD2 178 PROMtpd Y CB 6 0 Fig 16 PROM 40 bit wide load at 2 WS MATRA MHS Rev D 10 Apr 97 20 es eae ey wee Cae ee CLK2 gt 31 0 I ll Hw ROMCS 13 MEMBEN 13 ROMBEN mi Pass le qon s nen MEMWR1 15 MEMWR2 Lea t26 id MHOLD IUDATAtpd IUDATAhold D 31 0 DPARIO FDO D 23 j 120 CB 6 0 Fig 17 PROM 40 bit wide store 1 WS MATRA MHS Rev D 10 Apr 97 21 Semiconductors TSC693E E a CLK2 SYSCLK 31 0 C FA ASI 7 0 09H DNE 09H SIZE 1 0 _ 1 io __ br 16 gt 16 21 gt 122 D 31 0 DPARIO FDO FD1 LD1 FD2 CB 6 0 Fig 18 MEC Register Load MATRA MHS Rev D 10 Apr 97 Semiconductors CLK2 SYSCLK A 31 0 ASI 7 0 SIZE 1 0 ALE DXFER WRT RD WE DIR OE 31 0 DPARIO CB 6 0 Rev D 10 Apr 97 TSC693E 5 Ne eee
54. C Output Delay 06 2 MHOLD BHOLD Output Delay 07 20 DOE TOE Output Delay 128 8 INTACK Input Setup Time 029 4 INTACK Input Hold Time 30 8 SYSRESET SYSHALT Input Setup 81 14 SYSRESET SYSHALT Input Hold 32 1 _ RESET CPUHALT Output Delay 035 3 INULL Input Setup 36 4 INULL Input Hold 37 _ 15 ___ MDS DRDY Output Delay 38 15 BUSRDY BUSERR Input Setup 39 4 BUSRDY BUSERR Input Hold uo _ 15 DMAREQ Input Setup Time 2 15 ___ DMAGNT Output Delay 15 IRLG 0 EXTINTACK Output Delay 44 8 EXTINTO Input Setup 45 _ 4 0 Input Hold ers ir IUERR IUHWERR IUCMPERR FPUHWERR FPUCMPERR Input Setup pecie cd IUERR IUHWERR IUCMPERR FPUHWERR FPUCMPERR Input Hold 148 15 5 5 SYSAV MECHWERR Output Delay 149 8 NOPAR ROMWRT PROM8 Input Setup Time tso 4 NOPAR ROMWRT PROM8 Input Hold Time 153 15 APAR ASPAR IMPAR Input Setup Time 184 APAR ASPAR IMPAR Input Hold Time MATRA MHS Rev D 10 Apr 97 TSC693E 57 100 00 6 5 TRST IpuSeup CLK O 857 14 588 5 TMSIpuSeup 59 4 TMS TK 15 TE Input Setup TCLK OE 6 DE InputHold TK 4 15 P TDOOutput Delay CLK 63
55. D09 xor D04 xor D03 xor 202 xor DOO 5 D31 xor D26 D25 xor D23 xor D21 xor D20 018 xor D14 xor D13 xor D11 xor D10 xor D09 xor D08 xor D06 xor DOS xor DOO CB6 D31 xor D30 xor D29 xor D28 xor D27 xor D23 xor D22 xor D19 xor D18 xor D17 xor D16 xor D15 xor D11 xor D07 xor D02 xor DOI DPARIO Odd parity over D31 to DO not D31 xor D30 xor xor D01 xor DOO MATRA MHS Rev D 10 Apr 97 28 TSC693E 3 9 2 Syndrome Generator The Syndrome Generator generates the internally used and externally observable syndrome bits SY 7 0 It uses the read data bits and the eight read check bits The coding of the syndrome is given below SY7 CB6 Read Data xor CB5 Read Data xor not CB4 Read Data xor CB3 Read Data xor not CB2 Read Data xor CB1 Read Data xor CBO Read Data xor Read Parity SY6 Data xor Read Checkbit6 SY5 CB5 Read Data xor Read Checkbit5 SY4 CB4 Read Data xor Read Checkbit4 SY3 CB3 Read Data xor Read Checkbit3 SY2 CB2 Read Data xor Read Checkbit2 SY1 1 Read Data xor Read SY0 CBO Read Data xor Read CheckbitO MATRA MHS Rev D 10 Apr 97 29 TSC693E 3 9 3 Syndrome Detector If there is a correctable error in the read data word the correction is performed according to the following procedure In case of Syndrome 7 0 when 00111000 gt Corrected Data Data xor 000000000000000000000000000000
56. DMA uses parity AOE Address Output Enable output The MEC deasserts this signal when an external master DMA unit uses the address bus Control Output Enable output The MEC deasserts this signal when an external master DMA unit uses the control bus DOF Data Output Enable output The MEC deasserts this signal when an external master DMA unit uses the data bus BHOLD Bus Hold output The MEC asserts this signal during DMA accesses MDS Memory Data Strobe output During nominal execution with the IU as bus master MDS is asserted by the MEC to enable the clock to the instruction register of the IU during an instruction fetch or to the load result register during a data fetch while the pipeline is frozen with an MATRA MHS Rev D 10 Apr 97 69 ty 02s TSC693E Memory Exception output Assertion of this signal by the MEC initiates an instruction access exception or data access exception trap and indicates to the IU that the memory system was unable to supply a valid instruction or data It is asserted when a parity error uncorrectable EDAC error access violation bus time out or system bus error is detected If this signal is asserted during a DMA transfer the DMA must withdraw its DMA request and end the DMA cycle Memory Bus Hold output is used to freeze the clock to both the IU and floating point
57. Kbytes 256 Kbytes and 512 Kbytes Selection of exchange memory size is done by programming the Memory Configuration Register see page 52 The default value of the exchange memory size after system reset 15 the minimum size 4 Kbytes The MEC provides one exchange memory chip select output Only word access is allowed in the exchange memory area Any attempt to access byte or halfword data in the exchange memory will cause a memory exception In case the exchange memory includes EDAC check bits and parity bits these protection bits will be treated in the same manner as for the main memory If the exchange memory does not include any check bits the MEC will generate the parity to the IU The default is that no EDAC or parity is implemented in the exchange memory If the exchange memory implements check bits this must be defined in the Memory Configuration Register in the MEC during start up and initialization The MEC is designed to allow implementation of the exchange memory with a DPRAM The BUSY signal from the DPRAM can then be connected to the BUSRDY signal of the MEC The MEC waits one cycle at the start of the access for the assertion of the BUSRDY signal If the BUSRDY signal is asserted in the beginning of the second cycle the normal data wait state controlled access continues If the BUSRDY signal is deasserted during the wait states the MEC will delay the access until the BUSRDY signal has been asserted and then continue with th
58. O CMOS Interrupt and Control Signals 1811301 4 0 Request CMOS Interrupt Acknowledge O EXTINT 40 5 External Interrupt TIL IEXTINTACK 0 External Interrupt Acknowledge CMOS ISYSRESET I 5 SCH TR __ Rest IUERR i TIL IUHWERR 1 12 HerdwaeEmo TIL IUCMPERR I IU Comparison Error TIL FPUHWERR I FPU Hardware Error TL I FPU Comparison Error rr MECHWERR 0 MEC hardware Error CMOS ISYSERR O jSystemEmr CMOS SYSAV 1 System Availability CMOS ISYSHALT jSysemHat rr NOPAR 1 I No Parity TTL MATRA MHS Rev D 10 Apr 97 64 TSC693E ROM Write Enable Processor IU and FPU Halt CPUHALT S gt S 3 e 9 5 R 5 Test Clock Test Reset Test Mode Select Test Data Input Test Data Output C TRST 4 j DI TDO gt 5 WDCLK Watch Dog Clock Receive Data channel Receive Data channel B Transmit Data channel A Transmit Data channel B x xB vsso U gt gt amp 5 amp TTL CMOS ouble Frequency Clock ystem Clock ai
59. OM access IOBEN is asserted during I O Extended general area and exchange memory access DDIR and DDIR are output by the MEC to indicate buffer direction As RAM chip select signals MEMCS 9 0 are provided The boot PROM chip select signal is ROMCS Four I O device chip select signals are provided IOSEL 3 0 EXMCS is used as chip select signal for exchange memory For RAM and boot PROM write access two strobe pairs are provided MEMWRI 1 0 and MEMWR2 1 0 MEMWRI is used to strobe data D 31 0 into memory 2 is used to strobe check bits CB 6 0 and parity DPARIO into memory For I O and exchange memory write access the IOWR strobe is provided As output enable to memory during read access OE 1 0 is provided BUSRDY is used to control access cycle length when accessing I O exchange memory and extended areas is used to signal erroneous access to the MEC when accessing I O exchange memory and extended areas 3 2 2 RAM The MEC is reprogrammable to interface with a number of different RAM sizes and organisations The table below shows all possible memory sizes and organisations MATRA MHS Rev D 10 Apr 97 12 ty tye TSC693E Table 1 Memory sizes and organizations using 8 bit wide memory chips RAM Size Chip org Chip org Chip org Chip org 8 CS used 4 CS used 2 CS used 1 CS used 32 8 chips 16 4 chips 8 2 chips 4 1 chips Selection of
60. On exchange memory accesses the will sense the bus ready signal BUSRDY after the first two cycles of the access If the bus ready signal is asserted at this time the MEC will continue with the programmed no of wait states However if the bus ready signal is deasserted the start of the access is put on hold Once the bus ready signal is asserted again the access will start with the programmed no of waitstates On I O and extended area accesses the MEC will sense the bus ready signal BUSRDY after the first cycle of the access If the bus ready signal is asserted at this time the MEC will continue with the programmed no of wait states If the bus ready signal is deasserted at this time the MEC will introduce wait states until the bus ready signal is again asserted Note the difference between wait state handling for exchange memory and wait state handling for I O For exchange memory the access will start when BUSRDY is asserted i e after BUSRDY is asserted an access with the programmed no of wait states will be performed BUSRDY is then handled as for the I O and extended area On the other hand during I O and extended area access assertion of BUSRDY signals the end of the access i e the access will finish one cycle after BUSRDY has been asserted at the earliest after the programmed no of wait states A bus timeout function of 256 or 1024 system clock cycles is provided for the bus ready controlled memory areas 256
61. RBRO and are set to the same value settings will have no effect 2 Is at reset automatically written with same value as PROMS input pin to MEC A write operation to this bit has no effect Lr EPA 3 Exchange memory parity protected r w enabled 0 disabled is don t 3 If the NOPAR signal is asserted data parity is not checked even if enabled in this register MATRA MHS Rev D 10 Apr 97 53 Semiconductors Configuration Register 01F8 0014 H Bits Name Reset value Function 3 0 SIZO 0000 unit 0 size 0000 512 bytes 0001 1 Kbytes 0010 2 Kbytes 0011 4 Kbytes 8 Kbytes 16 Kbytes 32 Kbytes 64 Kbytes 128 Kbytes 256 Kbytes 512 Kbytes 1 Mbytes 2 Mbytes 4 Mbytes 8 Mbytes 11 16 Mbytes 4 100 0 unit lt 0 gt enabled1 enable 0 disabled 23 0 0 0 0 Parity supplied by I O unit 0 Yes Note MEC checks parity 0 No Note generated parity lt 1 gt size Coded as for I O unit lt 0 gt unit lt 1 gt enabled 1 enabled 0 disabled Parity supplied by I O unit lt 1 gt 1 Yes Note MEC checks parity 0 No Note MEC generated parity Reserved ____ _____ 5172 0000 unit lt 2 gt size r w Coded as I O unit lt 0 gt unit lt 2 gt enabled 1 enabled 0 disable
62. Rev D 10 Apr 97 tye TSC693E 3 2 6 MEC Memory Map The MEC memory map is shown in Table 3 Table 3 MEC Memory map Address Memory contents Size Bytes Data size and parity hexadecimal options 0x00000000 Boot PROM 128k 16M 8 bit mode 8 to 32 bit conversion No parity Only byte write 40 bit mode Parity EDAC mandatory Only word write 0x01000000 Extended PROM 15M BUSRDY controlled Boot PROM 0 01 00000 Exchange memory 4k 512k Parity EDAC options BUSRDY controlled Only word accesses 0 01 80000 Registers 512 136 Parity only Word write and Word Hword Byte read 8 blocks All data sizes allowed 0x04000000 Extended RAM area 192M The same settings as for 0x 10000000 area 0 0 16 Parity option LM 0 11000000 0 12000000 0 16 0 13000000 1 0 14000000 Extended I O area The same settings as for BUSRDY controlled area 3 0 80000000 Extended general area No parity EDAC BUSRDY controlled All data sizes allowed 1 Neither access protection nor chip select generation is performed by the MEC for the extended areas Note that these areas are only controlled by the BUSRDY signal In the O areas and in the Extended areas one waitstate 15 always inserted since the MEC has to wait for BUSRDY signal In the Exchange Memory area two waitstates are always inserted to wait for the BUSRDY signal In the O areas and in the
63. and ground pins must be connected before power is applied 2 Ambient temperature is defined as the instant case temperature MATRA MHS Rev D 10 Apr 97 80 Semiconductors TSC693E 5 1 4 Capacitance Ratings ERC32 MEC CIN Max pF Input Capacitance 8 CIO Input Output Bus Capacitance 10 5 2 Package Description 5 2 1 Pin Assignments ROMWRT VSSII 4 fiso BHOLD ps 4 2 o 19 vsso 6 5 ue 4 2 846 1 553 6 78 BUSRDY 7 77 SYSCLK_0 5515 8 76 29 74 30 5502 D31 o m lo o 72 73 7 71 68 6 LK2 OE PUHALT Q R oO o gt gt gt gt gt gt gt gt gt 5 ve v 3 o o s o vo o D3 4 174 70 167 ior N nf aftr 53 a lt 02 93 93 L9 92 Un sS els i MATRA MHS Rev D 10 Apr 97 DIR 94 SYSRESET VSSO4 DIR MAAS MAGNT DOE DPARIO o Njo 5 gt 5 0 a s MECHWERR 20 Tck 41 vssos 4 232 MEMBEN fios 53 vssoo 8 253 53 TXA mi vssoio 2 2 UA UA a RTO a 5 EXTINTO 08 75
64. ans that all MEC registers will be initialized to their reset contents The reset signal from the MEC to the IU FPU etc RESET is minimum 16 clock cycles long i e it will remain asserted 16 system clock cycles after SYSRES has been deasserted Reset mode is also entered when the RESET output of the MEC is asserted from any other reason than SYSRES Software reset which is caused by the software writing to a Software Reset Register see page 52 Watchdog reset which is caused by a Watchdog counter timeout see paragraph 3 14 Error reset which is caused by a hardware parity error EDAC uncorrectable error or a comparison error see paragraph 3 17 When the reset cause is one of the above all MEC registers will be initialized to their reset contents except the Error and Reset Status Register see page 61 which contains the source of the last processor reset System reset software reset error reset watch dog reset By reading that register upon reset the IU can determine the cause of the reset 3 5 2 Run Mode In this mode the IU FPU is executing all timers of the MEC are running if software enabled and the UAR T is running 3 5 3 System Halt Mode System mode is entered when the SYSHALT input of the MEC is asserted CPUHALT output is asserted freezing IU FPU execution All timers are halted and the UART operation is stopped The MEC allows DMA accesses during system halt mode in which
65. by the system outside to halt the ERC32 By asserting this signal the MEC will assert CPUHALT halting the IU and the FPU This signal could be used for testing through the DMA or the TAP interface NOPAR No Parity input Assertion of this signal will disable the parity checking of all signals related to the ERC32 local buses The parity generation on the data bus towards memory and IO units is not affected by this signal but note that parity checking is disabled if NOPAR is asserted This is a static signal and shall not change when running ROMWRT ROM Write Enable input Assertion of this signal will validate allow programming write operations of the boot PROM when EEPROM devices are used Processor IU and FPU Halt output This output is intended to be connected to the HALT inputs of the IU and of FPU and is used to halt the IU the FPU and possibly other units in the system 4 2 4 Test Access Port Signals The following Test Access Port interface IEEE standard 1149 1 is used to perform boundary scan for test and debugging purposes TCK Test Clock input Test clock for scan registers MATRA MHS Rev D 10 Apr 97 77 iy aos TSC693E TRST Test Reset input Reset the TAP controller TMS Test Mode Select input Selects test mode of the TAP controller TDI Test Data Input input Test scan register data input TDO Test Data Output output
66. ck is derived either from the system clock or can use the watchdog clock with a UART oscillator input The baudrate of the UARTS can be programmed in the Scaler field and UBR bit of the MEC Control Register The scaler shall be set to Clock Scaler 1 32 Baudrate 2 UBR Where Clock is either the frequency of the system clock SYSCLK or the watchdog clock WDCLK selected by UCS bit 23 in MEC Control Register is the value of the UBR bit Baudrate is the desired baudrate Note that the resulting actual baudrate will probably not be exactly the desired one This is due to the fact that Scaler is an integer number and the above given equation may yield a non integer result depending on the Clock frequency The UART is temporary halted when CPUHALT is active and no transmission is performed by the UART The external UART interfaces consist of one transmit data output for each UART channel TXA and TXB and one receive data input for each UART channel RXA and RXB Note that no hardware handshake signals such as CTS or RTS are implemented Any handshaking must be implemented in software e g using XON XOFFP 3 16 Parity Checking The MEC includes parity checking and generation if required on the external data bus DPARIO It includes parity checking on the external address bus APAR It also includes parity checking on ASI and SIZE ASPAR together with parity generati
67. d Parity supplied by I O unit lt 2 gt 1 Yes Note MEC checks parity 0 No Note generated parity TSC693E 5 27 24 5173 0000 unit lt 3 gt size r w Coded as I O unit lt 0 gt MATRA MHS Rev D 10 Apr 97 unit lt 3 gt enabled 1 enabled 0 disabled Parity supplied by I O unit lt 3 gt 1 Yes Note MEC checks parity 0 No Note generated parity 5 il 54 Semiconductors Waitstate Configuration Register Bits Name Reset value Note 1 MATRA MHS 01F8 0018 H Function RAM read no of waitstates 00 0 WS 0 1 WS 10 2 WS RAM write no of waitstates ROM read no of waitstates 0000 0 WS 0001 0 WS 0010 1 WS 1 14 WS ROM write no of waitstates 0000 0 WS 0001 0 WS 0010 1 WS 1 Exchange memory read write no of waitstates 15 WS 0000 0 WS 0001 0 WS 0010 1 WS 11 ad write no of waitstates 0000 0 WS See Note 1 below 0001 0 WS 0010 1 WS 1111 14 WS IO 2 read write no of waitstates 0000 0 WS See Note 1 below 0001 0 WS 0010 1 WS 1111 14 11 3 read write no of waitstates 0000 0 WS See Note 1 below 0001 0 0010 1 TSC693E In the I O area MEC will always insert one waitstate to wait for the BUSRDY signal even when WS is programmed in the above register Rev D 10 Apr 97 55
68. d The write access possibility is enabled by asserting the Prom Write Control signal ROMWRT The following sizes of the boot PROM are allowed 128 Kbytes 256 Kbytes 512 Kbytes 1 Mbytes 2 Mbytes 4 Mbytes 8 Mbytes and 16 Mbytes Selection of PROM size is to be performed by programming the Memory Configuration Register see page 51 The default size of the boot PROM after system reset is the minimum size 128 Kbytes The MEC provides one PROM chip select output 3 2 3 1 Extended PROM In addition to the boot PROM area an extended PROM area is reserved in the MEC memory map The MEC does not provide any chip select signals for the extended PROM area i e address decoding must be implemented with external logic The extended PROM area is BUSRDY controlled with the same number of waitstates as the boot PROM area In addition one extra clock cycle is always introduced in the beginning of the cycle for the external address decoding The number of cycles is however always at least two even if the PROM area waitstate value has been programmed to zero The same restrictions as for boot PROM apply regarding data width and write access MATRA MHS Rev D 10 Apr 97 14 ty 2s TSC693E 3 2 4 Exchange Memory The MEC supports a dedicated exchange memory area that can be used for system bus interchange of data The following sizes of the exchange memory are allowed 4 Kbytes 8 Kbytes 16 Kbytes 32 Kbytes 64 Kbytes 128
69. e Clock lt Scaler gt 01F8 0084 H its Name RTCS Down counting 8 bit scaler Not used Real Time Clock Program Register lt Scaler gt 01F8 0084 H Function Programmed 8 bit scaler value Noted 44 The timeout for real time clock before interrupt occurs is calculated as Timeout Z RTCC RTCS 1 SYSCLK where SYSCLK is the system clock frequency General Purpose Timer Counter 01F8 0088 H rw 1 0 GPTC FFFFFFFFh Down counting 32 bit counter T General Purpose Timer Program Register Counter 01F8 0088 H rw 1 0 GPTC FFFFFFFFh Programmed 32 bit counter value T General Purpose Timer lt Scaler gt 01F8 008C H Bits Name hRestvaue Funcion GPTS Down counting 16 bit scaler 31 16 Oh Nusa f cs d MATRA MHS Rev D 10 Apr 97 58 TSC693E General Purpose Timer Program Register lt Scaler gt 01F8 008C H Bits Name Reset value Funcion vw GPTS Programmed 16 bit scaler value 31 16 Reserved o The timeout for the general purpose timer before the interrupt occurs is calculated as Timeout GPTC GPTS 1 SYSCLK where SYSCLK is the system clock frequency Timer Control Register 01F8 0098 H General Purpose Timer Counter Reload 1 reload counter at zero and restart 0 stop counter at zero General Purpose Timer counter load T load counter with preset value and start if enab
70. e normal data wait state controlled access If a cycle is prolonged to more than 256 clock cycles the Bus Timeout function will signal a system bus error The minimum length of an exchange memory access is three clock cycles 3 2 5 Four address decoded I O select outputs are provided in the MEC The minimum length of an I O access for each I O select is programmable in the MEC The BUSRDY signal is used to prolong I O access for devices with variable access time The signal is used to signal to MEC that a bus error has occurred Table 2 gives the encoding for the system bus transaction response signals The transactions that signal a system bus error set the corresponding bit in the System Fault Status Register SFSR of the MEC which then responds by asserting Error to the interrupt logic These bits describe system bus error cases in addition the bus timeout is set if the internal bus time out timer causes abortion MATRA MHS Rev D 10 Apr 97 15 TSC693E Table 2 Bus Transaction Response Signals BUSERR BUSRDY Nothing not ready Data Strobe ready Nothing not ready System Bus Error denotes an active low signal An I O cycle which is to be extended beyond that of the number of wait states set in the MEC for the corresponding I O select output requires that the BUSRDY signal is deasserted as input to the MEC The BUSRDY signal must be deasserted no late
71. erized by low circuit complexity and power consumption Extensive concurrent error detection and support for fault tolerance and reconfiguration is emphasized In addition to the main objective the ERC32 core is possible to use for performance demanding research applications in deep space probes In addition to the above characteristics the radiation tolerance and error masking are important By including support for reconfigurable of the error handling the different demands from the applications can be optimized for the best purpose in each case The ERC32 is to be used as a building block only requiring memory and application specific peripherals to be added to form a complete on board computer All other system support functions are provided by the core The ERC32 incorporates the followings functions Processor which consists of one Integer Unit TSC691E called IU in this document and one Floating Point Unit TSC692E called FPU in this document The processor includes concurrent error detection facilities Memory Controller TSC693E called MEC in this document which is a unit consisting of all necessary support functions such as memory control and protection EDAC wait state generator timers interrupt handler watch dog UARTS and test support The unit also includes concurrent error detection facilities One or two oscillator s Buffers necessary to interface with memory and peripherals Figure 1 schematically sho
72. except the UART RX and TX registers are readable in all access modes user supervisor and DMA The UART RX and TX registers are only readable in supervisor mode The MEC allows word halfword and byte accesses when a register is read The total 32 bit data together with the parity bit are thus always issued on the data bus All MEC registers which are writeable are writeable only in supervisor mode or in DMA mode if the is active and only as full 32 bit size data write accesses to the registers If a register access violation is performed by the IU the memory exception output is asserted If a register access violation is performed by the DMA the memory exception output MEXC and the DMA access error interrupt output are asserted MATRA MHS Rev D 10 Apr 97 26 22s TSC693E 3 9 EDAC The MEC includes a 32 bit EDAC Error Detection And Correction Seven bits CB 6 0 are used as check bits over the data bus The Data Bus Parity Input Output signal DPARIO is used to check and generate the odd parity over the 32 bit data bus This means that altogether 40 bits are used when the EDAC is enabled The MEC EDAC uses a seven bit Hamming code which detects any double bit error on the 40 bit bus as a non correctable error In addition the EDAC detects all bits stuck at one and stuck at zero failure for any nibble in the data word as a non correctable error Stuck at one and stuck at zero for all 32 bit
73. g to the replaced block will be inactive and MEMCS lt 9 gt will be active instead 000 MEMCS lt 0 gt inactive and replaced 001 MEMCS lt I gt inactive and replaced 010 MEMCS lt 2 gt inactive and replaced 011 MEMCS lt 3 gt inactive and replaced 100 MEMCS lt 4 gt inactive and replaced MEMCS lt 5 gt inactive and replaced MEMCS lt 6 gt inactive and replaced MEMCS lt 7 gt inactive and replaced 12 10 RSIZ RAM size 000 256 Kbyte 001 512 Kbyte 010 1 Mbyte 011 2 Mbyte 00 4 Mbyte 01 8 Mbyte 0 16 Mbyte 1 32 Mbyte RPA 3 RAM memory parity protected enabled 0 disabled RAM EDAC protected enabled 0 disabled Note When EDAC is enabled parity is enabled independent of RPA 5 Reserved ______ Not used PWR PROM write function r w enabled if external ROMWRT present 0 disabled MATRA MHS Rev D 10 Apr 97 52 asas TSC693E P8 2 PROM 8 bit wide 1 40 bit wide EDAC and Parity 0 8 bit wide Parity generation DN 18 PSIZ PROM size 000 128 Kbyte 001 256 Kbyte 0 512 Kbyte 1 Mbyte 100 2 Mbyte 101 4 Mbyte 0 8 Mbyte 16 Mbyte 26 24 ESIZ Exchange memory size 000 4 Kbyte 001 8 Kbyte 0 16 Kbyte 1 32 Kbyte 00 64 Kbyte 01 128 Kbyte 0 256 Kbyte 1 512 Kbyte Exchange memory EDAC protected enabled 0 disabled Note When EDAC is enabled parity is enabled independent of EPA Exchange memory exists exists 0 exists not 1 If
74. h is at least three times lower than SYSCLK This input could be divided by 16in a prescaler or routed directly to the scaler of the watch dog as set in the MEC Control Register see page 51 The WDCLK input consists of a Schmitt trigger to allow clock supply from an external RC oscillator It is possible to program the timer by setting a specific value in the Watchdog Program and Timeout Acknowledge Register see page 57 The register consists of one scaler field and one counter field corresponding directly to the scaler field and the counter field of the watchdog timer After system reset or processor reset the timer is enabled and starts running The default value is the scaler set to maximum and the counter set to maximum By writing to the Trap Door Set see page 57 after system reset the timer can be disabled After the disabling of the watch dog timer a write operation to the Watchdog Program and Timeout Acknowledge Register see page 57 starts the timer counting with the value of the specified fields Note that the Watchdog cannot be disabled once the Watchdog Program and Timeout Acknowledge Register has been written If the timer is refreshed by writing to Watchdog Program and Timeout Acknowledge Register see page 57 before the counter reaches zero value the timer restarts the counting with the new delay value If the timer is not refreshed reprogrammed before the counter reaches zero value an interrupt is issued to the IU Sim
75. h EDAC and or Parity Protection MATRA MHS Rev D 10 Apr 97 6 CLK2 SYSCLK 31 0 ALE MEMCS 0 DDIR OE MHOLD MDS D 31 0 DPARIO CB 6 0 MATRA MHS Rev D 10 Apr 97 FAS t37 137 137 78 Fi FD 6 1 78 gt Figure 3 RAM Load at 1 waitstate with EDAC and or Parity Protection _ CLK2 SYSCLK ALE I MEMBEN L C t14 DDIR MHOLD t26 t26 D 31 0 DPARIO Cl CB 6 0 123 4 124 Figure 4 RAM Store 1 waitstate with EDAC and or Parity Protection MATRA MHS Rev D 10 Apr 97 8 gt CLK2 SYSCLK 31 0 t T C FA ESTA C FAS ALE t tojt MEMCS 0 113 AMBEN MEMBEN W pou t16 116 16 116 tp t73 t26 MHOLD j n j X G VV 171 78 21 122 D 31 0 DPARIO CB 6 0 Figure 5 RAM Load at 0 waitstate with Correctable Error MATRA MHS Rev D 10 Apr 97 9 E CLK2 SYSCLK ca 10 19 ____ MEMCS 0 dL Tb T J 252 a 116 5 12 MHOLD di t25 t25 C FA2 2 MEXC 7 78 gt _
76. hdog Trap Door Set Unimplemented area Time Clock Timer lt Counter gt Real Time Clock Program Register lt Counter gt Real Time Clock lt Scaler gt Real Time Clock Program Register lt Scaler gt eneral Purpose Timer lt Counter gt eneral Purpose Timer Program Register lt Counter gt eneral Purpose Timer lt Scaler gt eneral Purpose Timer Program Register lt Scaler gt nimplemented area imer Control Register nimplemented area ystem Fault Status Register ailing Address Register nimplemented area rror and Reset Status Register nimplemented area est Control Register nimplemented area ART Channel A RX and TX Register ART Channel B RX and TX Register ART Status Register Unimplemented area MATRA MHS Rev D 10 Apr 97 01 8 FFFF 49 ty 2s TSC693E 3 21 2 Register Configuration and Bit Allocation For each register the following information is given Address of the register Bits is the bit allocation of the register A bit can either have a unique function or a number of bits can be grouped together into a specific field Name is the abbreviation for each bit or field Reset value states the value for each bit or field to be obtained after the assertion of system reset Function explains the function and use of each bit or field r w explains if the bit or field can be read and or written Note that in some cases only part of the 32 bit register is used The
77. he RAM area If both the SE and UE bits of the Segment Base Register are cleared write protection is effectively disabled for that segment MATRA MHS Rev D 10 Apr 97 25 ty 02s TSC693E The segment access protection can also be used as a block protect function by setting the BP bit in the MEC Control Register The BP bit inverts the address criterion for the protection function so that any access within the segment is detected If a write access protection error is detected a memory exception is generated and the SFSR and Failing Address Register is updated as for unimplemented area accesses see also paragraph 3 17 In normal mode 0 a memory exception is generated only if both segments indicated a write protection error In block protect mode 1 a memory exception is generated if any of the segments indicate a write protection error 3 7 3 Boot PROM Write Protection The MEC supports PROM write only when it is qualified by the external enable signal ROMWRT and the enable bit in the Memory Configuration Register see page 52 The MEC only supports byte write operations for an 8 bit wide PROM and only word write operations for a 40 bit wide PROM If a write access to PROM is attempted when any of the above conditions are not fulfilled the SFSR and Failing Address Register is updated as for unimplemented area accesses see also paragraph 3 17 3 8 Register Access Protection All MEC registers
78. input of a flip flop used to latch the address from the IU PROMS Select 8 bit Wide PROM input This input indicates that only 8 bit wide PROM is connected to the MEC The eight data lines from the PROM is to be connected to the D 7 0 signals The MEC will perform a 8 bit to 32 bit conversion when the IU reads from the PROM There is no EDAC or parity checking on accesses to the PROM when PROMS is asserted and EDAC and parity bits must be supplied by the PROM when PROMS is deasserted MATRA MHS Rev D 10 Apr 97 71 ty 223 TSC693E ROMCS PROM Chip Select output This output is asserted whenever there is an access to the PROM It can be connected directly to the PROM chip select pins MEMCS 9 0 Memory Chip Select output MEMCS 9 0 is asserted during an access to the main memory MEMCS 9 8 are redundant signals used to substitute any of the nominal memory banks when memory connected to any of MEMCS 7 0 malfunctions OE 1 0 Output Enable output OE 1 0 are asserted during read accesses to the main memory and is used to control memory devices with output enable features Two signals are provided in order to avoid an external buffer since a single OE signal would be too heavily loaded in typical system MEMWR 1 1 0 Memory Write output is asserted during write access to RAM extended RAM boot PROM extended boot PROM It is intended to be used as write strobe to
79. ive high and to define the external interrupts to be either edge or level sensitive Also by programming the ISR it is possible to make one of the external interrupts generate a pulse on the EXTINTACK output when the IU acknowledges the interrupt The external interrupt inputs are filtered such that both level and edge sensitive interrupts are detected only if the external interrupt is active for at least two system clock cycles Edge sensitive interrupts will be detected only when a transition occurs from high to low if programmed to be active low and vice versa i e the corresponding bit in IPR will be set Level sensitive interrupts will be detected i e the corresponding bit in IPR will be set as long as the interrupt line is asserted When the interrupt line is deasserted the corresponding bit in IPR will be cleared Table 5 Interrupt Trap Type and default priority assignments 1 Transmitter Ready UART A Data Ready or Transmitter Ready Ext Interrupt 1 Ext Interrupt 0 MATRA MHS Rev D 10 Apr 97 35 ones ty tye TSC693E 3 13 General Purpose and Real Time Clock Timers Two timers apart from the special Watchdog timer are available in the MEC These timers provide in addition to a generalized counter mechanisms a mechanism for setting the step size in which actual time counts are performed a two stage counter Each timer counter pulse generator consists of two parts pre SCALER COUNTER
80. le below 31 16 Reserved o _ Noewed f 8 id L __ Note 1 If this register is written the data is irrelevant The register is set to the value 00000078 hex Note 2 DMA errors will not overwrite the System Fault Status Register if IU data fault valid bit is set Note 3 The information about ASFT can be extracted by SW from the IPR as well Access type Access Type 0000 User Data RAM ROM Register ot used 00 0010 00 r w r r w r w fw r w r w r 0100 DMA RAM ROM Register 010 upervisor O Exchange 1010 10 T L Supervisor Data RAM ROM Register L Donotcare _______ 1 0 0 ser VO Exchange OxA 0 8 Loa B 0 0 1100 DMA l O Exchange S ser VO Exchange OxA 0 8 5 User Supervis 2 1000 User Data RAM ROM Register Supervisor Data RAM ROM Register User 51 xB Do not care xA xB D S _____________ Nu G 1110 Supervisor I O Exchange OxB 0x9 DMA l O Exchange Note tore DMA RAM ROM Register not care Accesses in the Extended general area are treated as RAM Accesses from an Access Type point of view Failing Address Register 01F8 00A4 H Bits Name Reset value Funcion 0 00 y ww MATRA MHS Rev D 10 Apr 97 60 E TSC693E Error and Reset Status Register 01F8 00B0 H Bis _____ Name Reset value Function 0 IUEM 0 IU error mode error
81. led 0 no function General Purpose Timer enable 1 enable counting 0 hold scaler and counter General Purpose Timer Scaler load 2 load scaler with preset value and start if enabled no function Real Time Clock Counter Reload 1 reload counter at zero and restart 0 stop counter at zero Real Time Clock counter load Ix load counter with preset value and start if enabled 0 no function Real Time Clock Scaler enable 15 enable counting 0 hold scaler and counter Real Time Clock Scaler load load scaler with preset value and start if enabled no function MATRA MHS Rev D 10 Apr 97 59 TSC693E System Fault Status Register 01F8 00A0 H pi Name Reset value Function Not used 2 SDFV ata fault valid 2 valid not valid 6 3 SRFT 1111 Data fault type or DMA error type 0000 Parity error on control bus 0001 Parity error on data bus 0010 Parity error on address bus 0011 Access to protected area 0100 Access to unimplemented area 0101 MEC register parity error 0110 MEC register access violation 0111 Uncorrectable error in memory 000 Bus time out 001 System bus error 010 to 1110 Not used 111 Reset value ASFV 0 Asynchronous fault valid valid 0 not valid 10 9 ASFT 00 Asynchronous fault type 00 Watch Dog time out 01 DMA time out access error 0 UART error 1 Correctable error in memory 15 12 AT 0000 Access type see tab
82. me timeout In case of a bus timeout during DMA the MEC asserts the Memory Exception output and removes the Bus Grant For further actions taken see paragraph 3 17 3 4 Bus Arbiter The IU and the FPU always have the lowest priority to the system bus and are denied access to memory in case of a request from a DMA unit unless the IU is performing a locked access or after a DMA exception cycle to allow interrupt handling Thus the DMA is granted access to the system bus provided this has been enabled by the IU in the MEC In other words the IU has the capability to prevent DMA accesses by disabling DMA in the MEC 3 5 Execution Modes The execution modes of the ERC32 as controlled by the MEC is shown in Figure 5 MATRA MHS Rev D 10 Apr 97 20 Semiconductors TSC693E Error detected and HALT selected DMA Power down 1 System halt mode is entered upon assertion of SYSHALT and exited when SYSHALT is deasserted Figure 5 ERC32 Execution Modes MATRA MHS Rev D 10 Apr 97 21 ty 223 TSC693E 3 5 1 Reset Mode When the SYSRES input is asserted the MEC issues a reset of itself and asserts the RESET output which is intended be used as reset signal to all other components in the system e g IU and FPU The SYSRES signal shall be applied for at least four clock cycles After the assertion of SYSRES the MEC starts the ERC32 system in the reset mode which me
83. miconductors CLK2 SYSCLK A 31 0 SIZE 1 0 ALE MEMCS 0 MEMBEN DDIR OE BHOLD COE AOE DOE DMAAS DMAREQ DMAGNT RD WRT DRDY D 31 0 CB 6 0 MATRA MHS TSC693E p p 4 ___ ___ hh FA2 all Gs 1 j C 10 rus drop DESDE s _ __ E mM 2104 1 174 F je 05 gt t40 LOW If block transfer 142 LOW If block transfer 121 71 178 122 _ C DMAD J FDI Fig30 DMA RAM Load Rev D 10 Apr 97 34 CLK2 SYSCLK AADRtpd DMAADRhold A 31 0 SIZE 1 0 ALE 5 0 DDIR MEMWR1 MEMWR2 OE 5 126 BHOLD INI t27 JE AOE DOE 174 175 DMAAS e t40 DMAREQ OW Tf block transfer DMAGNT OW Tr block transfer RD WRT 5 g DRDY 37 a D 31 0 CB 6 0 Fig31 DMA RAM Store MATRA MHS Rev D 10 Apr 97 35 Semiconductors CLK2 SYSCLK A 31 0 SIZE 1 0 ALE IOSEL IOBEN DDIR OE BHOLD COE AOE DOE DMAAS DMAREQ DMAGNT RD WRT DRDY D 31 0 CB 6 0 MATRA MHS TSC693E
84. mming the MEC Control Register see page 51 After system reset odd parity and one stop bit are set The baud rate of the UART is set by programming the MEC Control Register see page 51 After system reset the baud rate is set to system clock frequency divided by 32 which is probably not a usable baud rate It follows that the baud rate in the MEC Control Register must be programmed after system reset The UARTS provides double buffering i e each UART consists of a transmitter holding register a receiver holding register a transmitter shift register and a receiver shift register Each of these registers has a width of 8 bits For each UART a RX and TX Register see page 62 is provided There is also common UART Status Register see page 62 Figure 9 removed The receiver converts serial start bit data word parity bit and stop bit s into parallel form The transmitter converts parallel data into serial form automatically adding start bit parity bit and stop bit s To output a byte on the serial output the following procedure should be followed First the UART Status Register should be read in order to check that the transmitter holding register THE bit 2 and bit 18 respectively for channel A and B is empty Otherwise the previous byte to be output may be lost note that the TSE bit is not useful for the purpose of checking if a character may be written to the RX TX register Then the byte to be output RTD bits 0 7 is wri
85. n internal VCC Output driver VCC Main internal VSS Output driver VSS oa Ee p p 4 2 Detailed Signal Descriptions 4 2 1 IU FPU Interface Signals A 31 0 Address Bus input The address bus for the MEC is an input only bus The MEC uses the address bus to perform decoding to generate select signals and to check against the memory access protection scheme It is also used to address the MEC registers In case of Direct Memory Access DMA the address bus is driven by the DMA unit Address Bus Parity input This input is used by the MEC to check the odd parity over the 32 bit address bus In case of Direct Memory Access DMA this signal must be driven by the DMA unit in case DMA parity is enabled MATRA MHS Rev D 10 Apr 97 65 ty 2s TSC693E ASI 3 0 Address Space Identifier input These four bits constitute the Address Space Identifier ASI which identifies the memory address space to which the memory access is being directed The ASI bits are latched by the MEC and are used to detect supervisor mode instruction or data access etc A DMA unit must supply these bits SIZE 1 0 Bus Transaction Size input The coding on these pins specifies for the MEC the size of the data being transferred during a memory access DMA unit must drive these bits to 10 since only word transfers are allowed in DMA mode ASPAR ASI and SIZE Pa
86. non usable bits are marked as reserved and will always have a fix value generally zero when being read and can thus not be altered by a write operation NOTE reserved bits have to be written with zeros in order to avoid parity error resulting in a MEC internal error Certain registers below are not true registers in the sense that they only correspond to a write operation with any data Any data may be used when writing to these registers Nevertheless they are part of the register memory map and therefore included MATRA MHS Rev D 10 Apr 97 50 Control Register 1 Semiconductors Bits Name Reset value p E nc p ii BN 01F8 0000 H Function Power down enabled allowed 0 disable Software reset enabled allowed 0 disable Bus timeout enabled 0 disable Block protection instead of normal access protection enabled 0 disable log clock supply external clock with prescaler divide by 16 0 external clock prescaler IU Error Mode Mask Error masked disabled 0 Error not masked Reset or Halt when IU error mode ERROR Reset 0 Halt 10 Hardware Error Mask Error masked disabled 0 Error not masked Reset or Halt when IU Hardware Error HWERR Reset 0 Halt IU Comparison Error Mask Error masked disabled 0 Error not masked Reset or Halt when IU comparison error
87. on and checking on all internal registers The MEC also includes parity generation and checking on the external control bus to the IU IMPAR If a parity error is detected on the external data bus the external address the external ASI and SIZE the external control bus the memory exception output MEXC is asserted If a memory exception event occurs the System Fault Status Register see page 60 is updated and reflects the type and location of parity errors external parity checking can be disabled using the signal MATRA MHS Rev D 10 Apr 97 41 TSC693E 3 17 Error Handler The MEC has one error output signal SYSERR which indicates that an unmasked error has occurred Any error signaled on the error inputs from the IU and the FPU is latched and reflected in the Error and Reset Status Register see page 61 It is possible to program an error mask in the MEC Control Register for each type of error in order to determine whether the specific error shall lead to the MEC ignoring the error or asserting a processor halt or processor reset It is possible to choose either a processor halt or processor reset by programming the MEC Control Register see page 51 As default an error leads to a processor halt unmasked errors asserts the SYSERR pin and this pin is asserted until all the unmasked error bits in the Error and Reset Status Register see page 61 are cleared In Figure 8 a schematic
88. pin is used by the MEC to check and generate the odd parity over the 32 bit data bus according to Table 4 below MATRA MHS Rev D 10 Apr 97 31 a aao ses TSC693E Table 4 MEC parity handling Accessed memory area Memory Read Write parity enabled parity generated C parity checked N parity not checked nor generated Note When a correctable error occurs in the RAM or exchange memory MEC generates parity G even if parity is enabled 3 10 Memory Redundancy The MEC dedicates chip selects for two redundant memory banks for replacement of faulty banks A memory bank is a block composed of 32 bit data parity and a 7 bit checkcode and controlled with one chip select signal The size of the redundant memory banks are dependent of the memory size register Exclusion of a faulty memory block and selection of a redundant memory block is performed by programming the Memory Configuration Register see page 52 This remapping has no influence on the performance 3 11 Synchronous Traps Memory access error are signaled by the MEC by assertion of the MEXC signal This event will force the IU to vector to either an instruction access exception or a data access exception see RD2 Upon detecting an instruction or data exception the IU enters the corresponding trap The trap handler software can identify the synchronous fault with the aid from the Error Handler functions included in the MEC see paragraph 3 17
89. r than the number of system clock cycles equal to the wait states set in the MEC after start of the access The actual length of an IO cycle will equal the number of programmed waitstates possibly extended a number of clock cycles by deassertion of the BUSRDY signal If a cycle is prolonged to more than 256 clock cycles the Bus Timeout function will signal a system bus error As BUSRDY signal is used to extend the IO cycle one waitstate is minimum for I O access Programming the no of IO waitstates to zero will have no effect i e one waitstate is inserted anyway Each I O unit is enabled by programming the I O Configuration Register see page 54 The default value after system reset is no I O unit enabled Each of the four I O units is programmable to following sizes 512 bytes 1 Kbyte 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes 32 Kbytes 64 Kbytes 128 Kbytes 256 Kbytes 512 Kbytes 1 Mbyte 2 Mbytes 4 Mbytes 8 Mbytes 16 Mbytes Selection of each individual I O unit size is performed by programming the I O Configuration Register see page 54 The default value after system reset is 512 bytes for all units In case the I O unit includes a parity bit the parity will be treated in the same manner as for the main memory If the I O unit does not include parity the MEC will generate parity to the IU The I O Configuration Register see page 54 is used to determine for each individual I O unit if the MEC shall use parity checking
90. r to various sections of the MEC Power is supplied on two different buses to provide clean stable power to each section output drivers and the main internal circuitry VCCO pins supply the output driver bus and the VCCI pins supply main internal circuitry VSSI VSSO Ground inputs These pins provide ground return for the power signals Ground is supplied on different buses to match the power signals to each section VSSO pins for the output driver bus VSSI pins for the main internal circuitry bus MATRA MHS Rev D 10 Apr 97 79 TSC693E 5 ELECTRICAL AND MECHANICAL SPECIFICATION 5 1 Maximum Rating and DC Characteristics 5 1 1 Maximum Ratings Storage Temperature 65 C to 150 C Ambient Temperature with power applied 55 C to 125 C Supply Voltage 0 5 V to 47 0 V Input Voltage 0 5 V to 47 0 V 5 1 2 Operating Range Ambient Temperature Military 55 C to 125 C 5 V 109 5 1 3 DC Characteristics over the Operating Range Conditions VOH Output HIGH Voltage V per Ioh 2 0mA 0 Ve Min 05V HIGH Voltage 2 VIL Input LOW Voltage os HZ Input Leakage Current Vcc Max 10 10 Vss lt VIN lt Vcc 102 Output Leakage Current Vcc Max 15 15 Vss lt Vouts Current Vout 0V Supply Current Vcc 5V 100 mA All outputs loaded to f 20 MHz 50 p Notes 1 All power
91. re DXFER is sent out unlatched and is latched in the MEC before it is used A DMA unit must supply this signal during a DMA session MATRA MHS Rev D 10 Apr 97 67 aos TSC693E LDSTO Atomic Load Store input This signal is used to identify an atomic load store to the system and is asserted by the integer unit during all the data cycles the load cycle and both store cycles of atomic load store instructions LDSTO is sent out unlatched and is latched in the MEC before it is used A DMA unit must supply this signal during a DMA session LOCK Bus Lock input LOCK is asserted by the processor when it needs to retain control of the bus address and data for multiple cycle transactions Load Double Store Single and Double Atomic Load Store The bus will not be granted to another bus master as long as LOCK is asserted Note that BHOLD should not be asserted in the processor clock cycle which follows a cycle in which LOCK is asserted LOCK is sent out unlatched and must be latched externally before it is used A DMA unit must supply this signal during a DMA session RD Read Access input RD is used in conjunction with SIZE 1 0 ASI 3 0 and LDSTO to determine the type of transfer and to check the write access rights of bus transactions It may also be used to turn off the output drivers of data RAMs during a store operation A DMA unit must supply this signal during a DMA session deasserted low for write
92. re 9 Master Slave configuration on IU and FPU A detected comparison error CMPERR from either of the checking devices will cause the MEC to assert the SYSERR signal if the comparison error is unmasked MATRA MHS Rev D 10 Apr 97 43 ty 03 TSC693E The MEC detects illegal register access e g write to internal register in non supervisor mode The memory exception output MEXC is asserted by the MEC if such an access is made or if an access to an internal MEC register with erroneous data size is attempted A list of all events synchronous traps that cause a MEXC is found on page 33 Less critical errors and some other events are called asynchronous traps These events do not cause a MEXC but only an interrupt A list of all asynchronous traps is found on page 33 The MEC always completes the current cycle when an error is detected and the is generated in the beginning of the next cycle Apart from issuing MEXC and or interrupt synchronous and asynchronous events also cause the MEC to latch some internal registers to hold information about the occurred error If a trap event occurs the System Fault Status Register see page 60 is updated and reflects the type of error in accordance with the conditions in the table Also the Error and Reset Status Register see page 61 is updated reflecting the type of error in accordance with the conditions in the table The associated bus address is latched in the Failing
93. rectly Some MEC output signals are clocked by the CLK2 negative edge which means that the CLK2 duty cycle has a direct impact on the system performance When interfacing peripherals I O interface DMA interface etc it is highly recommended that only SYSCLK rising edge is used as reference as far as possible CLK2 should be used as input to the MEC only MATRA MHS Rev D 10 Apr 97 48 Semiconductors 3 21 MEC Registers The writeable registers of the MEC are only writeable in the supervisor mode or in TSC693E DMA mode during CPUHalt All registers except the UART RX and TX are readable in every access mode The UART RX and TX registers are only readable in supervisor mode or in DMA mode during CPUHalt Read write byte halfword are not allowed in any mode and will generate Memory Exception MEXC 3 21 1 Register Address Map IMEC Register IMEC Control Register oftware Reset Register Power Down Register Unimplemented area emory Configuration Register Configuration Register aitstate Configuration Register Unimplemented area Access Protection Segment 1 Base Register Access Protection Segment 1 End Register Access Protection Segment 2 Base Register Access Protection Segment 2 End Register Unimplemented area Interrupt Shape Register nterrupt Pending Register Interrupt Mask Register nterrupt Clear Register nterrupt Force Register Unimplemented area atchdog Program and Timeout Acknowledge Register atc
94. rity input This input is used by the MEC to check the odd parity over the ASI 3 0 and the SIZE 1 0 signals A DMA unit must supply this bit in case DMA parity is enabled Note that although ASI 7 0 exist in the IU only ASI 3 0 are connected to the MEC This means that from the IU only alternate address space accesses with ASI 7 4 containing 0 2 or 4 ones may be used ASI 7 4 0000 0011 0101 0110 1001 1010 1100 or 1111 otherwise an ASI and SIZE parity error will be detected in the MEC as the IU computes ASPAR over the full ASI 7 0 range D 31 0 Data Bus bi directional These pins form a 32 bit bi directional data bus that serves as the interface between the IU and the MEC It is driven by the MEC only during read of its internal registers when reading the boot PROM in 8 bit mode and when a single bit error is detected by the EDAC When implementing a system with an 8 bit PROM the PROM shall be connected to bits D 7 0 In case of Direct Memory Access DMA it is driven or read by the DMA unit DPARIO Data Bus Parity Input Output bi directional This pin is used by the MEC to check and generate the odd parity over the 32 bit data bus during write cycles A DMA unit must supply this bit in case DMA parity is enabled See also Table 4 on page 32 MATRA MHS Rev D 10 Apr 97 66 TSC693E DMAAS DMA Address Strobe input During DMA transfers when the external DMA is bus master this inpu
95. s Port These test functions are controlled using the Test Control Register TCR see page 61 3 19 1 EDAC Test The EDAC function allows fault injection for memory test purposes and also test of the EDAC function itself By enabling EDAC test mode in TCR ET 1 the bits in the CB field of TCR will substitute the normal checkbits during store cycles 3 19 2 Parity Test The MEC register parity function allows fault injection for parity test purposes By enabling parity test mode in TCR PT 1 wrong parity will be generated when any MEC register is read 3 19 3 Interrupt Test It is possible to test and force interrupts by setting the corresponding bit in the Interrupt Force Register page 57 Clearing of interrupts by setting the corresponding bit in the Interrupt Clear Register ICR will always clear the corresponding bit s in the Interrupt Pending Register IPR but will never affect the interrupts set in the Interrupt Force Register IFR However it is possible to remove these interrupts by clearing the corresponding bit in IFR If the MEC is in interrupt test mode the handling of IFR and IPR is different When Interrupt test is not enabled Setting or clearing a bit in IFR will only affect IFR The corresponding interrupt will not be forced When the interrupt is acknowledged the MEC will automatically clear the bit in the IPR corresponding to the trap address as described above When Interrupt test is enabled
96. s Register FPU Floating Point Unit VO Input Output ICR Interrupt Clear Register IFR Interrupt Force Register IMR Interrupt Mask Register IPR Interrupt Pending Register IU Integer Unit MEC MEmory Controller PROM Programmable Read Only Memory RAM Random Access Memory RD Reference Document ROM Read Only Memory RTC Real Time Clock SFSRSystem Fault Status Register SW Software TAP Test Access Port TBC To Be Confirmed TBD To Be Defined UART Universal Asynchronous Receiver Transmitter WD Watch Dog MATRA MHS Rev D 10 Apr 97 6 2s TSC693E 1 4 Definitions 1 4 1 Bit Numbering In this document the following conventions are used The most significant bit in a vector has the highest bit number and the leftmost position in a field The least significant bit in a vector has the lowest bit number and the rightmost position in a field 1 4 2 Signal Names The following conventions are used for signal names Signal names are written in capital letters SIGNALNAME Active low signals are named SIGNALNAME 1 4 3 Registers The following convention is used for registers Register names bolded Register Name MATRA MHS Rev D 10 Apr 97 7 olei TSC693E 2 GENERAL OVERVIEW OF ERC32 2 1 ERC32 Overview The objective of the ERC32 is to provide a high performance 32 bit computing core for on board embedded real time computers The core is charact
97. s of the data word is also detected as a non correctable error The EDAC corrects any single bit data error on the 40 bit bus However in order to correct any error in memory e g Single Event Upset induced the data has to be read and re written by software as the MEC does not automatically write back the corrected data nibble is defined as a bit group of four within the data word D 3 0 D 7 4 etc MATRA MHS Rev D 10 Apr 97 27 ty 02s TSC693E 3 9 1 Check Bit Generator The Check Bit Generator generates the seven check bits plus parity bit that is to be fed to a multiplexer The output from the multiplexer is either the check bits generated by the Check Bit Generator or the contents of the check bits in the Test Control register checkbit DPARIO parity bit D31 xor D30 xor D29 xor D28 xor 024 xor D21 xor D20 xor D19 xor D15 xor D11 xor D10 xor D09 xor D08 xor D05 xor D04 xor DOI 030 xor D28 xor D25 xor D24 xor D20 xor D17 xor 016 xor D15 xor D13 xor D12 xor D09 xor D08 xor D07 xor D06 xor D04 xor D03 CB2 not D31 xor D26 xor D22 xor D19 xor D18 xor D16 xor D15 xor D14 xor D10 xor D08 xor D06 xor D05 xor D04 xor 203 xor D02 xor D01 CB3 D31 xor D30 xor D27 xor D23 D22 xor D19 xor 015 xor D14 xor D13 xor D12 xor D10 xor D09 xor D08 xor D07 xor D04 xor DOO CB4 not D30 xor D29 xor D27 xor D26 xor D25 xor D24 xor D21 xor D19 xor D17 xor D12 xor D10
98. system clocks in the Extended RAM Extended General and Extended I O areas and 1024 system clocks in the Extended PROM area The MEC Control Register see page 51 is used to select this function The default after system reset is that the bus timeout function is enabled The bus timeout counter will start when the access is initiated If the bus ready signal is not asserted before a valid number of system clock cycles a memory exception will occur For further actions taken see paragraph 3 17 MATRA MHS Rev D 10 Apr 97 24 ty 223 TSC693E 3 7 Memory Access Protection 3 7 Unimplemented Areas Accesses to all unimplemented memory areas are handled by the MEC and detected as illegal according to Table 3 page 18 The memory and I O configuration registers define the size of memory and I O areas The unused area of the memory space dependent on the programming of the memory size is decoded as illegal If an access from the IU is attempted to an illegal area the memory exception output is asserted If an access from the DMA is attempted to an illegal area the memory exception output MEXC and the DMA access error interrupt output are asserted For the extended areas no access protection is implemented However since these areas are bus ready BUSRDY controlled the bus timeout function will detect an access to an unimplemented extended area When the IU issues the trap service routine the contents of the MEC S
99. t be implemented with external logic The extended RAM area is BUSRDY controlled with the same number of waitstates as the RAM MATRA MHS Rev D 10 Apr 97 13 TSC693E area In addition one extra clock cycle is always introduced in the beginning of the cycle for the external address decoding Byte halfword and word access is allowed 3 2 3 Boot PROM The MEC allows software to be executed from a single byte wide PROM Alternatively a full wide EDAC protected 40 bits PROM can be used Hereafter this start up PROM is called boot PROM One extra clock cycle is always introduced in the beginning of the cycle for the address decoding The IU supports byte operations on data but for instruction fetches it needs a full 32 bit wide word In the case that byte wide boot PROM is used selected by asserting the PROMS input pin of the MEC the MEC performs an 8 to 32 bit conversion of the boot PROM data during read access This means that a word access to byte wide boot PROM will correspond to four byte fetches The total number of cycles required for each word read will then be equal to 4 1 no of boot PROM waitstates 2 When 32 bit wide PROM is used both EDAC and parity bits must be supplied to the MEC During read operations byte halfword and word access is allowed If the boot PROM is based on EEPROM devices the MEC supports write access but note that only byte write is supported if byte wide EEPROM is use
100. t is used to inform the MEC that the address from the DMA is valid and that the access cycle shall start DMAAS can be asserted multiple times during DMA grant DRDY Data Ready during DMA access output During DMA read transfers when the external DMA is bus master this output is used to inform the DMA unit that the data are valid During DMA write transfers this signal indicates that data have been written into memory INULL Integer Unit Nullify Cycle input INULL is output from the IU to indicate that the current memory access is nullified See further the IU signal description ExtHOLD External unit Hold input This signal input is used to synchronize coprocessor compare instructions with branch instructions The MEC shall use this signal for prolonging of ongoing cycle See further the FPU FHold CHold signal description ExtCCV External unit Condition Codes Valid input This signal input is used to hold the MEC when a coprocessor can not continue execution The MEC shall use this signal for prolonging of ongoing cycle See further the FPU FCCV CCCV signal description DXFER Data Transfer input is used to differentiate between the addresses being sent out for instruction fetches and the addresses of data fetches DXFER is asserted by the processor during the address cycles of all bus data transfer cycles including both cycles of store single and all three cycles of store double and atomic load sto
101. terrupt 15 cleared bit 15 0 interrupt 15 not cleared 31 16 Reserved Interrupt Force Register 01 8 0054 H R ese Hee EE Reserved 1 IF Forced interrupts bit 1 1 interrupt 1 forced bit 1 0 interrupt 1 not forced bit 15 1 interrupt 15 forced bit 15 0 interrupt 15 not forced 31 16 Watchdog Program and Timeout Acknowledge Register 01F8 0060 H Bits Name Reset value Function 0 y vw The timeout for the watchdog before the watchdog interrupt occurs is calculated as Timeout 16WPCS WDS 1 WDC 1 WDCLK The timeout for the watchdog before warm reset occurs is calculated as Reset timeout Timeout 16WPCS WDS 1 WDR 1 WDCLK Where WDCS is the Watchdog Clock Supply bit of the MEC Control Register and WDCLK is the frequency of the WDCLK input signal Watchdog Trap Door Set 01 8 0064 H Write only with any data A write to this register after reset but before the watchdog has elapsed will disable the watchdog The watchdog will stay disabled until it is reprogrammed by writing to the Watchdog Program and Timeout Acknowledge Register MATRA MHS Rev D 10 Apr 97 57 TSC693E Real Time Clock Timer Counter 01F8 0080 H pi Name Resetvalue Function riw 31 0 Down counting 32 bit counter Real Time Clock Program Register Counter 01F8 0080 H Bits Name Resetvalue Function RTCC Real Tim
102. the memory devices If latching buffers are used for the data bus this signal can be used as a strobe to latch the data and the MEMWR2 signal can be used to write the data into the main memory Two signals are provided in order to avoid an external buffer since a single signal would be too heavily loaded in typical system MEMWRQ 2 1 0 Check Bit Write output MEMWARO 2 is asserted during write access to RAM extended RAM boot PROM extended boot PROM and exchange memory It is intended to be used as write strobe to check bit memory devices if implemented If latching buffers are used for the data bus this signal can be used to write both the check bits into the check bit memory and the data bits into the main memory Two signals are provided in order to avoid an external buffer since a single signal would be too heavily loaded in typical system RAMBEN RAM Buffer Enable output RAMBEN is asserted during memory accesses to RAM It is intended to be used as buffer enable for data and check bit buffers in the RAM MATRA MHS Rev D 10 Apr 97 22 ty 02s TSC693E ROMBEN Boot PROM Buffer Enable output ROMBEN is asserted during memory accesses to boot PROM It is intended to be used as buffer enable for data and check bit buffers in the boot PROM areas Memory Buffer Enable output is asserted during memory accesses to both RAM and boot It is intended to be used
103. ts are located outside the ERC32 Consequently these interrupts are inputs to the MEC The interrupt allocation for the asynchronous traps is in accordance with the scheme in Table 5 page 35 It is possible to mask each individual interrupt except interrupt 15 by setting the corresponding bit in the Interrupt Mask Register see page 57 The MEC includes a specific register called Interrupt Pending Register see page 56 which reflects the pending interrupts It is possible to clear pending interrupts by setting the corresponding bit in the Interrupt Clear Register see page 57 Interrupt test description moved to paragraph 3 19 The interrupts in the IPR are cleared automatically when the interrupt is acknowledged The MEC will sample the trap address in order to know which bit to clear Upon receiving an interrupt external or forced the MEC issues a request on its IRL outputs to the IU with the corresponding interrupt level If two or more interrupts occur MATRA MHS Rev D 10 Apr 97 34 ty 2s TSC693E simultaneously the interrupt with the highest priority level is issued to the IU If a higher level interrupt is recognized by the MEC before the lower level interrupt request is acknowledged the higher level interrupt will replace the lower level interrupt request By programming the Interrupt Shape Register see page 56 it is possible to define the external interrupts to be either active low or act
104. tten in the RX and TX register The byte written will then automatically be transferred to the transmitter send register and converted to serial form also adding start bit parity bit and stop bit s The above described sequence can be part of a trap handler for the UART interrupt When a data byte has been received on the serial interface an interrupt is issued to the IU The byte received is converted to parallel form and loaded into the receiver data register Framing error i e the stop bit is not of correct polarity parity error and overrun error i e the preceding byte has not been read before a complete following byte is received are indicated by the bits FE PE and OE respectively in the UART status register A correctly received byte is indicated by the Data Ready bits for channel A and B DRA bit 0 and bit 16 when reading the UA RT status register The UARTS generate an interrupt each time a data word has been received a data word has been sent and if an error is detected There is one interrupt from each UART A and B to indicate that data is correctly received or that the transmitter register is empty MATRA MHS Rev D 10 Apr 97 40 iy tye TSC693E There is another interrupt to indicate errors but this interrupt is common for both UART channels The UART uses an internal clock which is 16 times faster than the baud rate and samples each bit 16 times to ensure error free reception The clo
105. ultaneously the timer starts counting a reset timeout period with the programmed delay time Then if the timer is acknowledged by writing to Watchdog Program and Timeout Acknowledge Register see page 57 with a new programmed value before the reset timeout period elapses again the timer restarts counting with the new delay value but if the timer is not acknowledged before the reset timeout period elapses a processor reset is issued by the MEC The Watchdog is temporary halted when the CPUHALT signal is active Figure 7 explains all the states and transitions of the watchdog timer MATRA MHS Rev D 10 Apr 97 38 TEM TSC693E System processor reset Watchdog Program New valu Watchdog timeout default value Trap Door set WD disabled Watchdog Program new value Watchdog Progra Refresh WD enabled normal mode Watchdog Timeout acknowledge Watchdog Timeout New value WD Reset timer enabled Interrupt Reset Timeout WD Processor reset halted Figure 7 Watchdog timer states and transitions MATRA MHS Rev D 10 Apr 97 39 ty 2s TSC693E 3 15 UART The MEC includes two full duplex asynchronous receiver transmitters UARTS The data format of the UARTS is eight bits It is possible to choose between even or odd parity or no parity and between one and two stop bits by progra
106. unit during cache miss for systems with cache memory or when accessing a slow memory It is generated by the MEC to insert wait states during memory or I O accesses MATRA MHS Rev D 10 Apr 97 70 ty 02s TSC693E 4 2 2 Memory System Interface Signals BA 1 0 Boot PROM Latched Address used for 8 bit Wide PROM output These outputs are used when 8 bit wide PROM is connected to the MEC During a read access to the PROM the BA 1 0 will be asserted four times in order to get the four bytes needed to generate a 32 bit word The MEC will assert the BA 1 0 in the sequence according to Table 7 Table 7 BA 1 0 Sequence BA 1 0 Bits in the 32 bit word CB 6 0 Check Bits bi directional CB 6 0 is the EDAC checkword over the 33 bit data bus consisting of D 31 0 and the parity bit DPARIO When IU performs a write operation to the main memory the MEC will assert the EDAC checkword on the CB 6 0 During read access from the main memory CB 6 0 are input signals and will be used for checking and correction of the data word and the parity bit During read access to areas which do not generate a parity bit the MEC will latch the data from the accessed address and drive the correct parity bit on the DPARIO pin ALE Address Latch Enable output This output is asserted when the address from the IU or a DMA unit is to be latched by an external latch The signal is intended to be used to enable the clock
107. view of the error handler is shown ERSR MCR Errors Reset Halt MCR Error Mask SYSERR Masked Hardware Erro Interrupt Level 1 Figure 8 Error Handler Schematic A MEC hardware error occurs if a parity error is detected on the internal registers A detected MEC hardware error will cause MEC to assert MECHWERR and SYSERR signals The memory exception output MEXC is not asserted in this case MATRA MHS Rev D 10 Apr 97 42 ty 02s TSC693E The MEC provides inputs for handling of the following IU and FPU errors see RD2 and RD3 IU Error Mode IUERR IU Hardware Error IUHWERR IU Comparison Error IUCMPERR FPU Hardware Error FFUHWERR Comparison Error FFUCMPERR A detected error on those inputs will cause the MEC to assert the SYSERR signal IU FPU and MEC errors are latched even if previous errors are latched The MEC also provides inputs for handling of master slave checking for the IU FPU In Figure 9 a system is shown where master checkers are used on both the IU and FPU Master Checker on IU and FPU IU FPU CMPERR HWERR 4 ERROR 4 HWERR MEC IUCMPERR IUHWERR IUERR FPUCMPERR SYSERR 9 FPUHWERR SYSAV MECHWERR 9 CIU CFPU CMPERR HWERR CMPERR ERROR HWERR Figu
108. ws a basic ERC32 computer with external functions added to form a complete system MATRA MHS Rev D 10 Apr 97 8 Seer or TSC693E Check bits External IRQs Figure 1 ERC32 Computer with typical peripherals MATRA MHS Rev D 10 Apr 97 9 TSC693E 3 MEMORY CONTROLLER FUNCTIONS support functions of the ERC32 except for the local clock oscillator and address and data bus drivers buffers and latches are incorporated in one single chip memory controller unit MEC The MEC is designed to interface the IU and the FPU to external memory and I O units thus forming a system with which computers for on board embedded real time applications can be built In order to achieve this the MEC constitutes all necessary support and on chip resources accordingly System start up control and reset Power down mode control System clock Watchdog function Memory interface to RAM ranging from 256 Kbyte to 32 Mbyte Memory interface to PROM ranging from 128 Kbyte to 4 Mbyte I O interface to exchange memory e g DPRAM ranging from 4 Kbyte to 512 Kbyte I O interface to four peripherals DMA interface Bus arbiter Programmable wait state generator Programmable memory access protection Memory redundancy control EDAC with byte and halfword write support Trap handler including 15 level interrupt controller One 32
109. ystem Fault Status Register SFSR give the cause of the exception When a memory data access violation error occurs RAM write protection or illegal area the associated bus address is latched in a separate register MEC Failing Address Register FAR With memory data access is meant IU operand fetch or DMA An IU instruction fetch error will not latch the bus address For further actions taken see paragraph 3 17 3 7 2 RAM Write Access Protection In addition to the access protection defined by the fixed memory map in the MEC which will detect any access to unimplemented and illegal addresses the MEC can be programmed to detect and mask write accesses in any part of the RAM The protection scheme is enabled only for data area not for the instruction area The programmable write access protection is segment based A segment defines an area where write cycles are allowed Any write cycle outside a segment is trapped and does not change the memory contents Two segments are implemented Each segment is implemented with two registers the Segment Base Register and the Segment End Register The segment base register contains the start address of the segment and enabling bits for supervisor user mode SE UE The segment end register contains the first address outside the segment i e last address of segment plus one word Only word aligned addresses are supported The segments are only active during RAM access i e they can only be mapped to t

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