Errata to MPC885 PowerQUICC™ Reference Manual
Contents
1. 885 PowerQUICC Reference Manual Rev 2 Freescale Semiconductor 7 How to Reach Us Home Page www freescale com Web Support http Awww freescale com support USA Europe or Locations Not Listed Freescale Semiconductor Inc Technical Information Center EL516 2100 East Elliot Road Tempe Arizona 85284 1 800 521 6274 or 1 480 768 2130 www freescale com support Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French www freescale com support Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 1 303 675 2140 Fax 1 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number MPC885UMAD Rev 4 2 2008 Information in this document is provided solely to enable system and software implementers to use Freescale Semic2. AM microcode package 0 DREQO cannot interrupt the CP 1 DREQO will interrupt the CP This bit must be set to enable USB host SOF generation 19 1 2 19 3 In Table 19 1 U Bus Arbitration IDs change the term G2 Core to PTEC Core Errata to MPC885 PowerQUICC Reference Manual Rev 2 Freescale Semiconductor Section Page No 27 1 27 2 31 7 1 31 9 31 7 2 31 11 31 7 2 31 11 32 4 3 32 7 33 8 33 19 35 2 1 35 3 42 2 2 42 3 Changes In Figure 27 2 Ethernet Block Diagram Clock Generator block Internal Clock s arrows should be reversed pointing into the block and RCLK and TCLK arrows should be reversed pointing out of the block In Figure 31 5 USB Controller Operating Modes the arrow on the bottom of Preamble should point in the opposite direction In Figure 31 6 SOF Generation the dreqO signal should point in the opposite direction In the last paragraph please change to DREQO should be configured as external interrupt bit EIE should be set to 1 in RCCR When there are no hardware originated requests to the CP it enters stall state Configuring DREQO as an external interrupt request ensures that only a hardware interrupt request can wake up the host controller In Table 32 3 I2BRG Field Descriptions change the description for bits 0 7 to read as follows Division ratio 0 7 Specifies the divide ratio of the BRG divider in the IC
3. Freescale Semiconductor Document Number MPC885UMAD Addendum Rev 4 2 2008 Errata to MPC885 PowerQUICC Reference Manual Rev 2 This document describes corrections to the MPC885 PowerQUICC User s Manual Rev 2 For convenience the chapter number and page number of each erratum are provided Items in bold are new since the last revision of this document To locate any published updates for this document refer to the worldwide web at www freescale com semiconductors Freescale Semiconductor Inc 2008 All rights reserved se 2 freescale semiconductor e a e ae C Section Page No General erratum Changes Replace all instances of the term 60x with external 10 4 1 10 4 In Figure 10 2 Internal Memory Map Register MMR change PARTNUM reset from 000_0000 to O000_1001 or 0x09 10 4 1 10 4 In Figure 10 2 Internal Memory Map Register MMR and Table 10 2 MMR Field Descriptions change bits 0 15 for ISB to 0 13 Bits 14 and 15 are reserved bits and are restricted to containing only a value of 0 to prevent conflicts between the Internal Memory Map and the SEC s memory map 12 1 2 12 22 In Table 12 1 MPC885 MPC880 Signal Descriptions add RMI_MII_MDIO to name column of pin P19 12 1 2 12 23 In Table 12 1 MPC885 MPC880 Signal Descriptions add RMII2 TXEN pin T6 description to MII1 TXEN pin T5 descriptio
4. clock generator The output of the prescaler is divided by 2 x DIV 3 2x FLT and the clock has a 50 duty cycle The FLT bit is in the IZ2MOD register The minimum value for DIV is 3 if the digital filter is disabled FLT 0 and 6 if the digital filter is enabled FLT 1 Add a note to beginning of section as follows PIP in transparent mode is not supported First bullet should reference SPS 0 and second bullet should reference SPS 1 Add the following note below the second paragraph NOTE The actual number of active PHY address signals is selected in UTMODE ADDPIN see Section 43 2 UTOPIA Mode Register UTMODE When a PHY address signal is not activated the pin reverts to its function as defined by PBDIR alone UT becomes a don t care For example assuming that the UTOPIA interface has been initialized properly and if only seven PHYs are used in a UTOPIA master application the SMC1 data signals are still available because RxAddr 3 and TxAddr 3 are not active 45 2 1 45 3 45 2 5 45 7 45 3 1 45 12 In Table 45 2 MII and RMII Signals add input next to the signal descriptions Transmit Clock and Receive Clock In Figure 45 2 Ethernet Address Recognition Flowchart the promiscuous mode check at the bottom should indicate when R_ CNTRL PROM 0 the state machine leads to False Add the following note below Table 45 6 CPTR RMII Related Field Description
5. n 14 2 1 14 4 In Table 14 1 The Input Frequency Requirements change 320 MHz to 400 MH as follows Table 14 1 The Input Frequency Requirements MODCK 1 2 Frequency In PDF MFI MFN MFD for DPGDCK 00 01 OSCM 10 MHz to 10 66 MHz 0 160 MHz lt OSCLK 2 MFI MFN MFD 1 lt 400 MHz 11 EXTCLK 10 MHz to 10 66 MHz 0 160 MHz lt OSCLK 2 MFI MEN MFD 1 lt 400 MHz 10 45 MHz lt EXTCLK lt 66 MHz 10 MHz lt EXTCLK 160 MHz lt OSCLK 2 MFI MFN MFD 1 PDF 1 lt 32 MHz PDF 1 lt 400 MHz 14 3 1 3 14 13 In the first bullet note dealing with internal clock of 2 x EXTCLK add the following assuming EXTCLK is between 50 MHz to 80 MHz 14 4 3 14 17 In the description An inductor value of 8 2 Mhz and bypass capacitor values of 0 1 uF and 10 uF provide a two pole filter with a cutoff frequency of 500 Hz change 8 2 MHz to 8 2 mH 14 6 2 14 21 In Figure 14 13 PLL and Reset Control Register PLPRCR change 0000 under field PDF to because PDF is not affected by HRESET 14 6 2 14 22 In Figure 14 13 PLL and Reset Control Register PLPRCR and Table 14 9 PLPRCR Field Descriptions change bit field FIOPD to RESERVED 18 6 1 18 6 In Table 18 4 RCCR Field Descriptions change bit 12 description to say EIE External interrupt enable Configure as instructed in the download process of a Motorola supplied R
6. onductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Sho
7. s Errata to MPC885 PowerQUICC Reference Manual Rev 2 Freescale Semiconductor Section Page No Changes NOTE If auto negotiation is used then it is recommended to configure RMIIx_RATE_FECx after the PHY has finished the auto negotiation The user can then read the line speed from the PHY status registers using MII management frames and then configure RMIIx_RATE_FECx accordingly 45 3 2 13 45 23 45 3 2 13 45 24 45 3 2 14 45 24 Appendix F F 1 In Figure 45 17 MII_DATA Register remove address offset s for FEC_2 Ox 1E80 and 0x1E82 In the last paragraph add the following In the MPC88x or MPC87x all MII management interface transactions must be done through FEC registers This includes MII_SPEED and MII_DATA registers In Figure 45 18 MII_SPEED Field Descriptions remove address offset s for FEC_2 0x1E84 and Ox1E86 Under the first bullet remove the sentence The time slot assigner is not implemented Errata to MPC885 PowerQUICC Reference Manual Rev 2 Freescale Semiconductor Section Page No Changes THIS PAGE INTENTIONALLY LEFT BLANK Errata to MPC885 PowerQUICC Reference Manual Rev 2 Freescale Semiconductor 5 Section Page No Changes THIS PAGE INTENTIONALLY LEFT BLANK Errata to MPC885 PowerQUICC Reference Manual Rev 2 6 Freescale Semiconductor Section Page No Changes THIS PAGE INTENTIONALLY LEFT BLANK Errata to MPC
8. uld Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by Power org All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2008 Printed in the United States of America All rights reserved 2 freescale Power semiconductor
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