RL78/G10 Datasheet - Renesas Electronics
Contents
1. 220 1 byte data for mode setting A 222222222 L V eT V Llessuseesrej5e V o X lt 1 gt The low level is input to the TOOLO pin lt 2 gt The external reset is released SPOR reset must be released before the external reset is released 3 The TOOLO pin is set to the high level 4 Setting of entry to the flash memory programming mode by UART reception is completed Remark tsuinit Communication for the initial setting must be completed within 100 ms after the external reset is released during this period tsu Time to release the external reset after the pin is set to the low level tup Time to hold the TOOLO pin at the low level after the external reset is released RO1DS0207EJ0300 Rev 3 00 AS Page 30 of 32 Nov 19 2014 SENES lt R gt RL78 G10 3 PACKAGE DRAWINGS 3 PACKAGE DRAWINGS 3 1 10 pin products R5F10Y17ASP R5F10Y16ASP R5F10Y14ASP R5F10Y17DSP 5 R5F10Y16DSP R5F10Y14DSP ete JEITA Package Code RENESAS Code Previous Code MASS TYP g P LSSOP10 4 4x3 6 0 65 PLSP0010JA A P10MA 65 CAC 2 0 05 NOTE Each lead centerline is located within 0 13 mm of its true position T P at maximum material condition Note Under development detail of lead end UNIT mm I2. TxDO RL78 microcontroller User s device RxDO UART mode bit width reference 1 Transfer rate High Low bit width Baud rate error tolerance TxDO RxDO Remark fmck Serial array unit operation clock frequency Operation clock to be set by the serial clock select register 0 SPSO and the CKSOn bit of the serial mode register SMROnH n Channel number n 0 1 RO1DS0207EJ0300 Rev 3 00 a2 AS Page 21 of 32 Nov 19 2014 KENES lt R gt RL78 G10 2 CSI mode master mode SCKp internal clock output Ta 40 to 85 C 2 0 V lt Voo lt 5 5 V Vss 0 V Parameter SCKp cycle time Conditions tkcy1 gt 4 fcik 2 7 V lt Voo lt 5 5 V 2 ELECTRICAL SPECIFICATIONS 200 2 0 V lt Voo lt 5 5 V 800 SCKp high low level width tkH1 tkL1 2 7V lt Vo0 lt 5 5V tkcy1 2 18 2 0 V lt Voo lt 5 5 V tkcy1 2 50 Slp setup time to SCKp 2 7 V lt Voo lt 5 5 V 47 2 0 V lt Voo lt 5 5 V Slp hold time from SCKpf e Delay time from SCKp to SOp output ete C 30 pF Note 3 Notes 1 When DAPOn 0 and CKPOn 0 or DAPOn 1 and CKPOn 1 The Slp setup time becomes to SCKpv and Slp hold time becomes from SCKpv when DAPOn 0 and CKPOn 1 or DAPOn 1 and CKPOn 0 2 When DAPOn 0 and CKPOn 0 or DAPOn 1 and CKPOn 1 The delay time to SOp output b
3. lt lt lt lt lt lt lt lt lt lt t gt P121 P122 X1 X2 EXCLK In input port or Vi external clock input In resonator connection Input leakage POO to 07 40 41 125 137 current low Vi Vss P121 P122 X1 X2 EXCLK In input port or Vi Vss external clock input In resonator connection On chip pull up resistance Notes 1 The value under the condition which satisfies the high level output current loH1 2 The value under the condition which satisfies the low level output current loL1 Caution The maximum value of Viu of P00 P01 P06 and P07 is even in N ch open drain mode POO P01 P06 and P07 do not output high level in N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port RO1DS0207EJ0300 Rev 3 00 AS Page 14 of 32 Nov 19 2014 KENES RL78 G10 2 3 2 Supply current characteristics 1 Flash ROM 1 and 2 KB of 10 pin products Ta 40 to 85 C 2 0 V lt lt 5 5 V Vss 0 V Parameter Supply current Operating Note 1 mode Basic operation Conditions fin 20 MHz 2 ELECTRICAL SPECIFICATIONS Voo 3 0 V 5 0 V Normal operation fiu 20 MHz Voo 3 0 V 5 0 V fiu 2 5 MHz Voo 3 0 V 5 0 V Ipp2 Note HALT mode fiu 20 MHz Voo 3 0 V 5
4. 80 and 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA e Total output current of pins lot x 0 7 n x 0 01 Example Where n 80 and lo 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin 4 Value of current at which the device operation is guaranteed even if the current flows from an output pin to the Vss pin Caution P00 P01 P06 and P07 do not output high level in N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port R01DS0207EJ0300 Rev 3 00 Nov 19 2014 7tENESAS Page 13 of 32 RL78 G10 2 ELECTRICAL SPECIFICATIONS Ta 40 to 85 C 2 0 V lt Von lt 5 5 V Vss 0 V 2 2 Parameter Conditions lt Input voltage high Input voltage low Output voltage high 4 0 V lt Voo lt 5 5 V 10 mA Note 1 3 0 mA 2 7 V lt Voio lt 5 5 V loH 2 0 mA 2 0 V lt Voo lt 5 5 V lou 1 5 mA Output voltage low 4 0 V lt 0 lt 5 5 V lo 20 mA Note 2 lo 8 5 mA 2 7 V lt Voo lt 5 5 V lo 3 0 mA lo 1 5mA 2 0 V lt Voio lt 5 5 V lo 0 6 mA Input leakage POO to P07 P40 P41 P125 P137 current high Vi
5. 2 The maximum value MAX of is during normal transfer and a wait state is inserted in the acknowledge timing Remark The maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Standard mode Cb 400 pF Rb 2 7 Fast mode Cb 200 pF Rb 1 7 KQ IICA serial transfer timing SCLAO tHD STA SDAAO Stop Start Restart Stop condition condition condition condition RO1DS0207EJ0300 Rev 3 00 7tENESAS Page 25 of 32 Nov 19 2014 RL78 G10 2 ELECTRICAL SPECIFICATIONS 2 6 Analog Characteristics 2 6 1 A D converter characteristics Target pin ANIO to ANI6 internal reference voltage Ta 40 to 85 C 2 4 V lt lt 5 5 V Vss 0 V Parameter Conditions Resolution RES 8 10 bit Overall error e 23 AINL 10 bit resolution Vop 5V 17 3 1 LSB Vop 2 3 4 5 LSB Conversion time tconv 10 bit resolution 2 7 V lt lt 5 5 V 3 4 18 4 us Target pin 5 av lt Vop lt 5 5 y 5 4 6 18 4 us to ANIG 10 bit resolution 2 4 lt lt 5 5 V 4 6 18 4 us Target pin internal reference voltage e 5 Zero scale error etes 1234 Ezs 10 bit resolution Vop 5V 0 19 FSR Vop 3V 0 39 FSR Full scale errorNtes 1 2 3 4 Ers 10 bit resolution Vop 5V 0 29 FSR Vop 0 42 FSR Integral linear
6. CENESAS Datasheet RL78 G10 RENESAS MCU R01DS0207EJ0300 Rev 3 00 Nov 19 2014 True Low Power Platform as low as 46 uA MHz 2 0 to 5 5V Operation 1 to 4 Kbyte Flash for General Purpose Applications 1 OUTLINE 1 1 Features Ultra Low Power Technology e 2 0 to 5 5 V operation from a single supply e Stop RAM retained 0 56 pA e Operating 46 uA MHz RL78 S1 Core e Instruction execution 78 of instructions can be executed in 1 to 2 clock cycles CISC architecture Harvard with 3 stage pipeline Multiply 8 x 8 to 16 bit result in 2 clock cycles 16 bit barrel shifter for shift amp rotate in 2 clock cycle 1 wire on chip debug function Main Flash Memory e Density 1 to 4 Kbyte e Flash memory rewritable voltage 4 5 to 5 5 V RAM e 128 to 512 Byte size options e Supports operands or instructions e Back up retention in all modes High speed On chip Oscillator e 20 MHz with 2 accuracy over voltage 2 0 to 5 5 V and temperature 20 to 85 e Pre configured settings 20 MHz 10 MHz 5 MHz 2 5 MHz and 1 25 MHz Reset and Supply Management e Selectable power on reset SPOR generator with 4 setting options Multiple Communication Interfaces e 1 x master e 1x C multi master only for 16 pin product e 1x UART 7 8 bit e Up to 2 x CSI SPI 7 8 bit R01DS0207EJ0300 Rev 3 00 Nov 19 2014 7tENESAS Extended Function Timers e Multi function 16 bit timers Up to 4 channels e
7. Operation clock to be set by the serial clock select register 0 SPSO and the CKSOn bit of the serial mode register SMROnH n Channel number n 0 1 R01DS0207EJ0300 Rev 3 00 Nov 19 2014 7tENESAS Page 22 of 32 RL78 G10 2 ELECTRICAL SPECIFICATIONS CSI mode connection diagram SCKOO SCK RL78 5100 SO Users device microcontroller 5000 51 CSI mode serial transfer timing When DAPOn 0 and 0 or DAPOn 1 CKPOn 1 tkcy1 2 2 tkH1 2 SCK00 5100 tkso1 2 5000 Output data Remark p CSI number p 00 01 n Channel number n 0 1 RO1DS0207EJ0300 Rev 3 00 a2 AS Page 23 of 32 Nov 19 2014 KENES RL78 G10 2 ELECTRICAL SPECIFICATIONS 4 Simplified 2 mode Ta 40 to 85 C 2 0 V lt Von lt 5 5 V Vss 0 V Parameter Conditions SCLr clock frequency fsc Co 100 pF Ro KQ 400 Note Hold time when SCLr L tLow Cb 100 pF Rb KQ 1150 Hold time when SCLr H tHIGH Cb 100 pF Rb KQ 1150 Data setup time reception tsu DAT Cb 100 pF Rb KQ 1 fuck 145 Note 2 Data hold time transmission Co 100 pF Rb 3 KQ 0 Notes 1 The value must also be equal to or less than fwck 4 2 Set the fuck value to keep the hold time of SCLr L and SCLr H Caution Select the N ch open drain output tolerance mode for the SDAr pin by using the
8. R5F10Y46 R5F10Y47 Code flash memory 1KB 2KB 4KB 1KB 2KB 4KB RAM 128B 256B 512B 128B 256B 512B Main High speed system X1 X2 crystal ceramic oscillation external system clock main system clock input EXCLK clock 1 to 20 MHz Voo 2 7 to 5 5 V 1 to 5 MHz Voo 2 0 to 5 5 V ee High speed on chip oscillator clock e 1 25 to 20 MHz VDD 2 7 to 5 5 V e 1 25 to 5 MHz VDD 2 0 to 5 5 V Note 3 Low speed on chip oscillator clock 15 kHz TYP General purpose register 8 bit register x 8 Minimum instruction execution time 0 05 us 20 MHz operation Instruction set e Data transfer 8 bits e Adder and subtractor logical operation 8 bits e Multiplication 8 bits x 8 bits e Rotate barrel shift and bit manipulation set reset test and Boolean operation etc port Total 8 14 CMOS I O 6 N ch open drain output tolerance 2 10 N ch open drain output tolerance 4 CMOS input 2 4 Timer 16 bit timer 2 channels 4 channels Watchdog timer 1 channel 12 bit interval timer 1 channel Timer output 2 channels PWM output 1 4 channels PWM outputs 3 Clock output buzzer output 1 2 44 kHz to 10 MHz Peripheral hardware clock 20 MHz operation Comparator 1 8 10 bit resolution A D converter 4 channels 7 channels Serial interface 10 pin products CSI 1 cha
9. You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics 6 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment
10. 0 V fiu 2 5 MHz Voo 3 0 V 5 0 V 003 3 STOP mode Notes 1 Total current flowing into including the input leakage current flowing when the level of the input pin is fixed to Vop or Vss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter I O port and on chip pull up pull down resistors 2 During HALT instruction execution by flash memory Voo 3 0 V 3 including the current flowing into the watchdog timer Remarks 1 High speed on chip oscillator clock frequency 2 Temperature condition of the typical value is 25 R01DS0207EJ0300 Rev 3 00 Nov 19 2014 134 NE SAS Page 15 of 32 RL78 G10 2 ELECTRICAL SPECIFICATIONS 2 Flash ROM 4 KB of 10 pin products and 16 pin products Ta 40 to 85 C 2 0 V lt lt 5 5 V Vss 0 V Parameter Conditions Supply current Operating Basic fiu 20 MHz Voo 3 0 V 5 0 V mode operation e e Normal finu 20 MHz Voo 3 0 V 5 0 V operation 4 fia 5 MHz Voo 3 0 V 5 0 V Note 4 fmx 20 MHz Square wave input Notes 5 6 Voo 3 0 V 5 0V Resonator connection fux 5 MHz Square wave input Notes 5 6 Resonator Voo 3 0 V connection 5 0V HALT mode 20 MHz Voo 3 0 V 5 0 V Note 4 fin 5 MHz Voo
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12. Industrial applications operating ambient temperature 40 C to 85 C ROM capacity 4 1 KB 6 2 KB 7 4KB Pin count 1 10 pin 4 16 pin RL78 G10 group 10Y Memory type F Flash memory Renesas MCU Renesas semiconductor product Table 1 1 List of Ordering Part Numbers Pin count Package Fields of Application 10 pin plastic LSSOP 4 4 x 3 6 mm 0 65 mm pitch Note 1 R5F10Y17ASP 30 R5F10Y17ASP 50 R5F10Y16ASP VO R5F10Y16ASP X0 R5F10Y14ASP VO R5F10Y14ASP X0 R5F10Y17DSP 30 R5F10Y17DSP 50 R5F10Y16DSP VO R5F10Y16DSP XO R5F10Y14DSPs VO R5F10Y14DSP X0 16 pin plastic SSOP 4 4 x 5 0 mm 0 65 mm pitch Notes and Caution are listed on the next page R01DS0207EJ0300 Rev 3 00 Nov 19 2014 R5F10Y47ASP 30 R5F10Y47ASP 50 R5F10Y46ASP 30 R5F10Y46ASP 50 R5F10Y44ASP 30 R5F10Y44ASP 50 R5F10Y47DSP 30 R5F10Y47DSP 50 R5F10Y46DSP 30 R5F10Y46DSP 50 R5F10Y44DSP 30 R5F10Y44DSP 50 7tENESAS Page 3 of 32 RL78 G10 1 OUTLINE Notes 1 For the fields of application refer to Figure 1 1 Part Number Memory Size and Package of RL78 G10 2 Under development Caution The part number represents the number at the time of publication Be sure to review the latest part number through the target product page in the Renesas Electronics Corp website 1 3 Pin Configuration Top View 1 3 1 10 pin products lt R gt e 10 plastic LSSOP 4 4 x 3 6 mm 0 65 mm pitch P40 KRO TO
13. P41 Total of 10 pin products P40 16 pin products P40 P41 When duty lt 70 4 0V lt Vp0 lt 5 5V 2 7 V lt Voo lt 4 0 V 2 0 V lt Voo lt 2 7 V Total of 10 pin products POO to P04 16 pin products POO to P07 When duty lt 70 3 4 0 V lt Vopx 5 5 V 27 lt Vop 4 0 V 2 0 V lt Voo lt 2 7 V Total of all pins When duty lt 70 3 Output current low Note 4 Per pin for 10 pin products to P04 P40 16 pin products to P07 P40 P41 Total of 10 pin products P40 16 pin products P40 P41 When duty lt 70 4 0 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 0 V 2 0 V lt Voo lt 2 7 V Total of 10 pin products POO to P04 4 0 V lt Vopx 5 5 V 2 7 V lt Voo lt 4 0 V 16 pin products POO to P07 When duty lt 70 2 0 V lt Voo lt 2 7 V Total of all pins When duty lt 70 3 Notes 1 Value of current at which the device operation is guaranteed even if the current flows from the Voo pin to an output pin 2 Do not exceed the total current value 3 This is the output current value under conditions where the duty factor lt 70 The output current value when the duty factor gt 70 can be calculated with the following expression when changing the duty factor to n e Total output current of pins x 0 7 n x 0 01 Example Where
14. bit interval ITMKA timer operating Notes 1 2 3 current Watchdog timer Iwor operating Notes 1 4 current A D converter lanc When conversion Voo 5 0 V operating Notes 1 5 at maximum speed yy 30V current Comparator In high speed Voo 5 0 V operating Notes 1 6 mode current In low speed mode Voo 5 0 V Internal reference voltage operating current Notes 1 Current flowing to 2 When high speed on chip oscillator and high speed system clock are stopped 3 Current flowing only to the 12 bit interval timer excluding the operating current of the low speed on chip oscillator The supply current of the RL78 microcontrollers is the sum of the values of either Ipp1 Ipp2 or Ipps and IFit and when the 12 bit interval timer is in operation 4 Current flowing only to the watchdog timer excluding the operating current of the low speed on chip oscillator The supply current of the RL78 microcontrollers is the sum of Ipp1 Ipp2 or Ipp3 and Iri and when the watchdog timer is in operation 5 Current flowing only to the A D converter The supply current of the RL78 microcontrollers is the sum of Ipp1 or and lanc when the A D converter operates an operation mode or the HALT mode 6 Current flowing only to the comparator The supply current of the RL78 microcontrollers is the sum of Ipp1 Ipp2 or and Icme when the comparator is
15. for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you 8 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations 9 Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the regulations and follow the procedures required by such laws and regulations products 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Note 2 Renesas Electronics product s means any product developed or manufactured by or for
16. port output mode register 0 POMO Simplified mode connection diagram Vb Rb SDA00 RL78 microcontroller User s device SCLOO SCL Simplified mode serial transfer timing 1 fscL tLow tHIGH SCLOO SDAO0 tHD DAT tsu DAT Remarks 1 Rb Communication line SDAr pull up resistance Co F Communication line SCLr SDAr load capacitance 2 r IIC number 00 3 fuck Serial array unit operation clock frequency Operation clock to be set by the serial clock select register 0 SPSO and the CKSOn bit of the serial mode register SMROnH n Channel number n 0 RO1DS0207EJ0300 Rev 3 00 AS Page 24 of 32 Nov 19 2014 SENES RL78 G10 2 ELECTRICAL SPECIFICATIONS 2 5 2 Serial interface Ta 40 to 85 C 2 0 V x Von lt 5 5 V Vss 0 V Parameter Conditions Standard Mode Fast Mode MIN MAX MIN MAX SCLAO clock frequency Fast mode gt 3 5 MHz Standard mode gt 1 MHz Setup time of restart condition tsu sTA Note 1 Hold time Hold time when SCLAO L tLow Hold time when SCLAO H tHIGH THD STA Data setup time reception tsu DAT je 2 Data hold time transmission tHD DAT Setup time of stop condition tsu sto Bus free time teur Notes 1 The first clock pulse is generated after this period when the start restart condition is detected
17. power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Notice 1 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 2 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 3 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intelle
18. selectable power on reset SPOR circuit should also be considered R01DS0207EJ0300 Rev 3 00 Nov 19 2014 434 NE SAS Page 9 of 32 RL78 G10 2 ELECTRICAL SPECIFICATIONS 2 ELECTRICAL SPECIFICATIONS Cautions 1 The RL78 microcontrollers have an on chip debug function which is provided for development and evaluation Do not use the on chip debug function in products designated for mass production because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when the on chip debug function is used 2 The pins mounted depend on the product Refer to 2 1 Port Functions and 2 2 1 Functions for each product in the RL78 G10 User s Manual 3 Use this product within the voltage range from 2 25 to 5 5 V because the detection voltage Vspor of the selectable power on reset SPOR circuit should also be considered RO1DS0207EJ0300 Rev 3 00 AS Page 10 of 32 Nov 19 2014 XENES RL78 G10 2 1 Absolute Maximum Ratings Ta 25 C Parameter Supply Voltage Symbols Conditions 2 ELECTRICAL SPECIFICATIONS Ratings 0 5 to 6 5 Input Voltage 0 3 to 0 3 Output Voltage 0 3 to Voo 0 3 Output current high Per pin 40 Total of all pins P40 P41 70 POO to 07 Output current low Per pin 40 Total o
19. 19 2014 SSENESAS RL78 G10 1 OUTLINE 1 4 Pin Identification ANIO to ANIG Analog Input INTPO to INTP3 Interrupt Request From Peripheral KRO to KR5 Key Return POO to P07 Port 0 P40 P41 Port 4 P121 P122 P125 Port 12 P137 Port 13 PCLBUZO Programmable Clock Output Buzzer Output EXCLK External Clock Input X1 X2 Crystal Oscillator Main System Clock IVCMPO Comparator Input VCOUTO Comparator Output IVREFO Comparator Reference Input RESET Reset RxDO Receive Data SCKOO SCK01 Serial Clock Input Output SCLOO SCLAO Serial Clock Output SDAOO SDAAO Serial Data Input Output 5100 SIO1 Serial Data Input 5000 SO01 Serial Data Output TIOO to TIO3 Timer Input TOO0 to Timer Output TOOLO Data Input Output for Tool TxDO Transmit Data VDD Power Supply Vss Ground R01DS0207EJ0300 Rev 3 00 Page 5 of 32 Nov 19 2014 434 NE SAS RL78 G10 1 OUTLINE 1 5 Block Diagram 1 5 1 10 pin products TIOO TOOO choo On chip won BCD adjustment KC Code flash 4 KB Interrupt control R01DS0207EJ0300 Rev 3 00 Nov 19 2014 Clock generator RESET Reset generator Selectable Low speed E on chip power on oscillator reset oscillator 1 25 to 20 15 kHz MHz Voo Vss 13 NE S AS oo KE P00 to P04 P40 P125 Porm P137 output control amp KRO to KR5 Inte
20. 3 0 V 5 0 V Note 4 fmx 20 MHz Square wave input Notes 5 6 Voo 3 0 V 5 0 V Resonator connection fux 5 MHz Square wave input Notes 5 6 Voo 3 0 V 5 0 V STOP mode Voo 3 0 V Resonator connection Notes 1 Total current flowing into including the input leakage current flowing when the level of the input pin is fixed to Vop or Vss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter comparator 16 pin products only I O port and on chip pull up pull down resistors During HALT instruction execution by flash memory Not including the current flowing into the 12 bit interval timer and watchdog timer When the high speed system clock is stopped When the high speed on chip oscillator is stopped 16 pin products only gt Remarks 1 fiu High speed on chip oscillator clock frequency 2 fwx High speed system clock frequency X1 clock oscillator frequency or external main system clock frequency 3 Temperature condition of the typical value is 25 RO1DS0207EJ0300 Rev 3 00 AS Page 16 of 32 Nov 19 2014 KENES RL78 G10 2 ELECTRICAL SPECIFICATIONS 3 Peripheral Functions Common to all products Ta 40 to 85 C 2 0 V lt lt 5 5 V Vss 0 V Parameter Conditions Low speed on chip oscillator operating current 12
21. ELECTRICAL SPECIFICATIONS 2 8 Flash Memory Programming Characteristics Ta 0 to 40 C 4 5 V lt lt 5 5 V Vss 0 V Code flash memory Cerwr Retained for 20 years Ta 85 C 1000 Times rewritable times 5 2 3 Notes 1 1 erase 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite 2 When using flash memory programmer 3 These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation 2 9 Dedicated Flash Memory Programmer Communication UART Ta 0 to 40 C 4 5 V lt lt 5 5 V Vss 0 V Remark The transfer rate during flash memory programming is fixed to 115 200 bps RO1DS0207EJ0300 Rev 3 00 AS Page 29 of 32 Nov 19 2014 KENES RL78 G10 2 ELECTRICAL SPECIFICATIONS 2 10 Timing of Entry to Flash Memory Programming Modes Parameter Conditions Time to complete the tsuinit SPOR reset must be released before the communication for the initial setting external reset is released after the external reset is released Time to release the external reset SPOR reset must be released before the after the TOOLO pin is set to the external reset is released low level Time to hold the TOOLO pin at the SPOR reset must be released before the low level after the external reset is external reset is released released V RESET
22. ENESAS Page 26 of 32 RL78 G10 2 ELECTRICAL SPECIFICATIONS 2 6 2 Comparator characteristics Ta 40 to 85 C 2 0 V lt lt 5 5 V Vss 0 V Parameter Conditions Input voltage range IVREFO pin input when COVFR bit 0 Internal reference voltage when COVRF bit 1 Note 1 IVCMPO pin input VoD 0 3 Output delay Vpop 3 0 V High speed mode 0 5 input slew rate gt 50 mV us Low speed mode Operation stabilization wait time Notes 1 When the internal reference voltage is selected as the reference voltage of the comparator the internal reference voltage cannot be used as the target for A D conversion 2 Refer to 2 6 3 Internal reference voltage characteristics 2 6 3 Internal reference voltage characteristics 40 to 85 C 2 0 V lt Von lt 5 5 V Vss 0 V Internal reference voltage VREG E 0 74 EET 0 815 DET 0 89 Operation stabilization wait time When A D converter is used ADS register 07H Note The internal reference voltage cannot be simultaneously used by the A D converter and the comparator only one of them must be selected RO1DS0207EJ0300 Rev 3 00 AS Page 27 of 32 Nov 19 2014 KENES RL78 G10 2 ELECTRICAL SPECIFICATIONS 2 6 4 SPOR circuit characteristics Ta 40 to 85 C Vss 0 V Parameter Conditions Detection Power supply Vsporo Power supply rise time voltage voltage level Power supply f
23. Interval timer 12 bit 1 channel only for 16 pin product e 15 kHz watchdog timer 1 channel Rich Analog e ADC Up to 7 channels 10 bit resolution 3 4 us conversion time e Supports 2 4 V e Internal reference voltage 0 815 V typ e Comparator 1 channel only for 16 pin product Safety Features e Detects execution of illegal instruction e Detects watchdog timer program loop General Purpose I O e High current up to 20 mA per pin e Open drain internal pull up support External Interrupt e External interrupt input Up to 4 e Key interrupt input 6 Operating Ambient Temperature e Standard 40 to 85 C Package Type and Pin Count e SSOP 10 and 16 pin Page 1 of 32 RL78 G10 1 OUTLINE O ROM RAM capacities Flash ROM R5F10Y17 R5F10Y47 R5F10Y16 R5F10Y46 R5F10Y14 Note 16 products only Remark The functions mounted depend on the product See 1 6 Outline of Functions R01DS0207EJ0300 Rev 3 00 AS Nov 19 2014 RENES R5F10Y44 Page 2 of 32 lt R gt lt R gt RL78 G10 1 2 List of Part Numbers Figure 1 1 Part Number Memory Size and Package of RL78 G10 Packaging style V0 Tray X0 Embossed Tape 30 Tray 50 Embossed Tape Package type SP 10 pin LSSOP 0 65 mm pitch 16 pin SSOP 0 65 mm pitch Classification 1 OUTLINE A Consumer applications operating ambient temperature 40 C to 85 C D
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25. OLO PCLBUZO TIO1 TOO1 PO4 ANIS TIO1 TOO1 KR5 P125 KR1 RESET O RL78 G10 O POS ANIZ TOOO0 KR4 INTP1 P137 TIOO INTPO Top View O P02 ANI1 SCK00 SCLOO PCLBUZO KRS Vss O O P01 ANIO SIO0 RXDO SDAOO KR2 Voo O P00 SO00 TXDO INTP1 Remarks 1 For pin identification see 1 4 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR See Figure 4 6 Format of Peripheral I O Redirection Register PIOR in the RL78 G10 User s Manual 1 3 2 16 pin products R e 16 plastic SSOP 4 4 x 5 0 mm 0 65 mm pitch PO7 SDAAO TOO3 ANIG SCKO1 O PO6 SCLAO INTP3 ANIS SIO1 O PO5 ANI4 TIO2 TOO2 SOO01 RL78 G10 O PO4 ANI3 TI01 TO01 KR5 IVREFO Top View O PO3 ANI2 TOOO KR4 INTP1 IVCMPO PO2 ANI1 SCK00 SCL00 PCLBUZ0 KR3 VCOUTO O PO1 ANIO S100 RXDO SDA00 KR2 O P00 SOO0 TXDO INTP1 P41 TIO3 INTP2 O P40 KRO TOOLO PCLBUZO TIO1 TOO1 O P125 KR1 RESET O P137 TIOO INTPO O gt P122 X2 EXCLK INTP2 O P121 X1 INTP3 Vss O Vpp O AN gt Remarks 1 For pin identification see 1 4 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR See Figure 4 6 Format of Peripheral I O Redirection Register PIOR in the RL78 G10 User s Manual RO1DS0207EJ0300 Rev 3 00 22 Page 4 of 32 Nov
26. Renesas Electronics development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and 10 Itis the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries 24 NE SAS SALES OFFICES Renesas Electronics Corporation http Awww renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes
27. TEM DIMENSIONS 3 60 0 10 0 50 0 65 T P 0 24 0 08 0 10 0 05 1 45 1 20 0 10 6 40 0 20 4 40 0 10 1 00 0 20 0 08 0 17_ 0 07 0 50 0 13 0 10 gis 0 25 T P 0 60 0 15 0 25 MAX 0 15 MAX 2 icavu izir zx i riommo ouo 2012 Renesas Electronics Corporation All rights reserved R01DS0207EJ0300 Rev 3 00 13 NE SAS Page 31 of 32 Nov 19 2014 RL78 G10 3 PACKAGE DRAWINGS 3 2 16 pin products R5F10Y47ASP R5F10Y46ASP R5F10Y44ASP lt R gt R5F10Y47DSP R5F10Y46DSP R5F10Y44DSP Pet lt R gt JEITA Package code RENESAS code MASS TYP g P SSOP16 4 4x5 0 65 PRSP0016JC B P16MA 65 FAB 1 detail of lead end me 4 _ 0 cC A2 Referance Dimension in Millimeters Symbol Win Nom Max D 4 85 5 00 5 15 D4 5 05 5 20 5 35 Terminal cross section Note Under development RO1DS0207EJ0300 Rev 3 00 a2 Page 32 of 32 Nov 19 2014 SSENESAS Revision History RL78 G10 Datasheet Description Summary 1 00 Apr 15 2013 First Edition issued 2 00 Jan 10 2014 1 2 Modification of descriptions in 1 1 Features 3 Modi
28. all time Vsport Power supply rise time Power supply fall time Vspor2 Power supply rise time Power supply fall time Vspor3 Power supply rise time Power supply fall time Minimum pulse width Note Time required for the reset operation by the SPOR when Voo becomes under Caution Set the detection voltage Vsror the operating voltage range The operating voltage range depends on the setting of the user option byte 000C2H The operating voltage range is as follows When the CPU operating frequency is from 1 MHz to 20 MHz 2 7 to 5 5 V When the CPU operating frequency is from 1 MHz to 5 MHz Vp 2 0 to 5 5 V 2 6 5 Power supply voltage rising slope characteristics Ta 40 to 85 C Vss 0 V R 2 7 RAM Data Retention Characteristics Ta 40 to 85 C Vss 0 V Caution Data in RAM is retained until the power supply voltage becomes under the minimum value of the data retention power supply voltage Vpppr Note that data in the RESF register might not be cleared even if the power supply voltage becomes under the minimum value of the data retention power supply voltage Vpppr STOP mode SPOR reset period Normal operation Retain data in RAM and RESF Vpop STOP instruction Rising of VsPoR execution Hevea VDDDR R01DS0207EJ0300 Rev 3 00 134 NE S AS Page 28 of 32 Nov 19 2014 RL78 G10 2
29. cillation stabilization time counter status register OSTC by the user Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register OSTS after sufficiently evaluating the oscillation stabilization time with the resonator to be used Remark When using the X1 oscillator refer to 5 4 System Clock Oscillator in the RL78 G10 User s Manual 2 2 2 On chip oscillator characteristics Ta 40 to 85 C 2 0 V lt Voo lt 5 5 V Vss 0 V Oscillators Parameters Conditions High speed on chip oscillator oscillation clock frequency etes 2 High speed on chip oscillator oscillation 20 to 85 C clock frequency accuracy TA 40 to 20 C Low speed on chip oscillator oscillation clock frequency Low speed on chip oscillator oscillation clock frequency accuracy Notes 1 High speed on chip oscillator frequency is selected by bits to 2 of option byte 000C2H 2 This only indicates the oscillator characteristics Refer to AC Characteristics for instruction execution time RO1DS0207EJ0300 Rev 3 00 AS Page 12 of 32 Nov 19 2014 KENES RL78 G10 2 ELECTRICAL SPECIFICATIONS 2 3 DC Characteristics 2 3 1 Pin characteristics Ta 40 to 85 C 2 0 V lt lt 5 5 V Vss 0 V Parameter Output current high Note 1 Conditions Per pin for 10 pin products to P04 P40 16 pin products to P07 P40
30. ctual property rights of Renesas Electronics or others 4 You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product 5 Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application
31. ecomes from SCKpf when DAPOn 0 and CKPOn 1 or DAPOn 1 and CKPOn O 3 C is the load capacitance of the SCKp and SOp output lines 3 CSI mode slave mode SCKp external clock input Ta 40 to 85 C 2 0 V lt lt 5 5 V Vss 0 V Parameter SCKp cycle time SCKp high low level width Conditions 2 7 V lt lt 5 5 V fuck gt 16 MHz 8 fuck lt 16 MHz G fuck 2 0 V lt Voo lt 5 5 V 2 0 V lt Voo lt 5 5 V 6 fuck tkcy2 2 18 Slp setup time to SCKpT 2 7 V lt Voo lt 5 5 V 1 fuck 20 2 0 V lt Voo lt 5 5 V 1 fuck Slp hold time from SCKp N 2 0 V lt Voo lt 5 5 V 1 fuck 31 Delay time from SCKp to SOp output Note 2 C 30 pF N 27V lt Vn 55V 2 50 2 0 V lt Vo lt 5 5 V 2ffvick 110 Notes 1 When DAPOn 0 and CKPOn or DAPOn 1 and CKPOn 1 The Slp setup time becomes to SCKpV and the Slp hold time becomes from SCKpv when DAPOn 0 and CKPOn 1 or DAPOn 1 and 0 2 When DAPOn 0 and 0 or DAPOn 1 and CKPOn 1 The delay time to SOp output becomes from SCKpf when DAPOn 0 and CKPOn 1 or DAPOn 1 and CKPOn 0 3 C is the load capacitance of the SOp output lines Remarks 1 p CSI number p 00 01 n Channel number n 0 1 2 fuck Serial array unit operation clock frequency
32. f all pins P40 P41 70 POO to P07 100 Operating ambient 40 to 85 temperature Storage temperature 65 to 150 Note Must be 6 5 V or lower Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remarks 1 Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 2 The reference voltage is Vss R01DS0207EJ0300 Rev 3 00 Page 11 of 32 Nov 19 2014 RENESAS RL78 G10 2 ELECTRICAL SPECIFICATIONS 2 2 Oscillator Characteristics 2 2 1 X1 oscillator characteristics Ta 40 to 85 C 2 0 V lt Von lt 5 5 V Vss 0 V X1 clock Ceramic resonator 2 7 V lt Voo lt 5 5 V oscillation crystal resonator 20V zVop 27 V frequency px ete Note Indicates only permissible oscillator frequency ranges Refer to AC Characteristics for instruction execution time Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics Caution Since the CPU is started by the high speed on chip oscillator clock after a reset release check the X1 clock oscillation stabilization time using the os
33. fication of description in 1 2 List of Part Numbers 4 Modification of remark 2 in 1 3 1 10 pin products and 1 3 2 16 pin products 8 9 Addition of description of R5F10Y17ASP in 1 6 Outline of Functions 11 Modification of description in 2 1 Absolute Maximum Ratings 12 Modification of description in 2 2 Oscillator Characteristics 13 14 Modification of description notes 1 to 4 and caution in 2 3 1 Pin characteristics 16 Addition of description notes 1 to 6 and remarks 1 and 2 in 2 Flash ROM 4 KB of 10 pin products and 16 pin products 17 Addition of description notes 1 to 6 and remarks 1 to 3 in 3 Peripheral Functions Common to all products 18 Modification of description in 2 4 AC Characteristics 19 Addition of figure of Minimum Instruction Execution Time during Main System Clock Operation 19 Addition of figure of External System Clock Timing 20 Modification of TI TO Timing 25 Addition of description in 2 5 2 Serial interface IICA 26 Modification of description and notes 1 to 6 in 2 6 1 A D converter characteristics 27 Addition of description notes 1 and 2 in 2 6 2 Comparator characteristics 27 Addition of description and note in 2 6 3 Internal reference voltage characteristics 28 Addition of caution in 2 6 4 SPOR Circuit characteristics 28 Addition of figure in 2 6 6 Data retention power supply voltage characteristics 31 Addition of R5F10Y17ASP in 3 1 10 pin products 3 00 Nov 19 2014 Modification of pac
34. hands Similar precautions need to be taken for PW boards with mounted semiconductor devices 4 STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up
35. in operation Remarks 1 fi Low speed on chip oscillator clock frequency 2 Temperature condition of the typical value is TA 25 RO1DS0207EJ0300 Rev 3 00 AS Page 17 of 32 Nov 19 2014 KENES RL78 G10 2 ELECTRICAL SPECIFICATIONS 2 4 AC Characteristics Ta 40 to 85 C 2 0 V lt lt 5 5 V Vss 0 V Instruction cycle minimum instruction execution time Conditions When high speed on chip oscillator clock fiu is selected 2 7 V lt Voo lt 5 5 V 2 0 V lt Voo lt 2 7 V When high speed system clock fmx is selected 2 7 V lt Voo lt 5 5 V 2 0 V lt Voo lt 2 7 V 0 2 External system clock frequency 2 7 V lt Voo lt 5 5 V 1 0 2 0 V lt Voo lt 2 7 V 1 0 External system clock input high level width low level width 27 V lt Voo lt 5 5 V 24 2 0 V lt Voo lt 2 7 V 95 TIOO to input high level width low level width trit Noise filter is not used 1 10 TOOO to TOOS3 output frequency fro 4 0 V lt lt 5 5 27 V lt Voo lt 4 0 V 2 0 V lt Voo lt 2 7 V PCLBUZO output frequency 4 0 V lt lt 5 5 V 2 7 V lt Voo lt 4 0 V 2 0 V lt Voo lt 2 7 V RESET low level width tRSL Remark fmck Timer array unit operation clock frequency Operation clock to be set by the timer clock select reg
36. ister 0 TPSO and the CKSOn1 bit of timer mode register OnH TMROnH n Channel number n 0 to 3 R01DS0207EJ0300 Rev 3 00 Nov 19 2014 134 NE SAS Page 18 of 32 RL78 G10 2 ELECTRICAL SPECIFICATIONS Minimum Instruction Execution Time during Main System Clock Operation Tcv vs 1 0 0 8 0 2 Cycle time Tcv us 0 1 0 05 0 01 3 0 27 Supply voltage Vop V 0 1 0 2 0 4 0 AC Timing Test Points Vin Vou Vit Vor External System Clock Timing gt Test points m When the high speed on chip oscillator clock is selected When the high speed system clock is selected Viu Von Viu VoL EXCLK R01DS0207EJ0300 Rev 3 00 Nov 19 2014 13 NE S AS Page 19 of 32 RL78 G10 2 ELECTRICAL SPECIFICATIONS TI TO Timing tri triH TIOO to TIO3 m 1 fto TOOO to RESET Input Timing TRSL RESET R01DS0207EJ0300 Rev 3 00 ESAS Page 20 of 32 Nov 19 2014 RL78 G10 2 ELECTRICAL SPECIFICATIONS 2 5 Serial Interface Characteristics AC Timing Test Points Vin Vou Vin Vou Vi Vot uem Test points ES Vi VoL 2 5 1 Serial array unit 1 UART mode Ta 40 to 85 C 2 0 V lt lt 5 5 V Vss 0 V Transfer rate Theoretical value of the maximum transfer rate fuck 20 MHz UART mode connection diagram
37. ity error 23 ILE 10 bit resolution Vop 5V 1 8 LSB Vop 3V 1 7 LSB Differential linearity error DLE 10 bit resolution Voo 5V 1 4 LSB pele Voo 3 V 1 5 LSB Analog input voltage Vain Target pin ANIO to ANI6 0 Voo V Target pin internal reference voltage Vreg V 3 4 This value is indicated as a ratio FSR to the full scale value 5 Set the LVO bit in the A D converter mode register 0 ADMO to 0 when conversion is done in the operating voltage range of 2 4 V lt Voo lt 2 7 V 6 Set the LVO bit in the A D converter mode register 0 ADMO to O when the internal reference voltage is selected as the target for conversion 7 Refer to 2 6 3 Internal reference voltage characteristics TYP Value is the average value at Ta 25 C MAX value is the average value 30 at normal distribution 2 These values are the results of characteristic evaluation and are not checked for shipment Excludes quantization error 1 2 LSB Cautions 1 Arrange wiring and insert the capacitor so that no noise appears on the power supply ground line 2 Do not allow any pulses that rapidly change such as digital signals to be input output to from the pins adjacent to the conversion pin during A D conversion 3 Note that the internal reference voltage cannot be used as the reference voltage of the comparator when the internal reference voltage is selected as the target for A D conversion R01DS0207EJ0300 Rev 3 00 Nov 19 2014 7t
38. kage drawing in 3 2 16 pin products 3 Addition of industrial applications in Figure 1 1 Part Number Memory Size and Package of RL78 G10 3 Addition of industrial applications in Table 1 1 List of Ordering Part Numbers 4 Addition of description to pin configuration in 1 3 1 10 pin products and 1 3 2 16 pin products 22 Correction of error in 2 5 1 Serial array unit 3 CSI mode slave mode SCKp external clock input 28 Renamed to 2 7 RAM Data Retention Characteristics and modification of figure 31 Addition of industrial application in 3 1 10 pin products 32 Addition of industrial application in 3 2 16 pin products and modification of package drawing trademarks and registered trademarks are the property of their respective owners SuperFlash is a registered trademark of Silicon Storage Technology Inc in several countries including the United States and Japan Caution This product uses SuperFlash technology licensed from Silicon Storage Technology Inc NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between VIL MAX and VIH MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes
39. nnel simplified 16 pin products CSI 2 channels simplified 1 channel UART 1 channel 1 channel UART 1 channel PC bus 1 channel Vectored Internal 8 14 interrupt External 3 5 Sources Key interrupt 6 Reset e Reset by RESET pin e Internal reset by watchdog timer e Internal reset by selectable power on reset e Internal reset by illegal instruction execution Note 2 e Internal reset by data retention lower limit voltage Selectable power on reset circuit R01DS0207EJ0300 Rev 3 00 Nov 19 2014 e Detection voltage Rising edge Vspor 2 25 V 2 68 V 3 02 V 4 45 V max Falling edge Vsppr 2 20 V 2 62 V 2 96 V 4 37 V max 7tENESAS Page 8 of 32 RL78 G10 On chip debug function 1 OUTLINE 10 pin 16 pin R5F10Y14 Provided R5F10Y16 R5F10Y17 R5F10Y44 R5F10Y46 R5F10Y47 Power supply voltage Vpop 2 0 to 5 5 V ee Operating ambient temperature Notes 1 40 to 85 C The number of outputs varies depending on the setting of channels in use and the number of the master see 6 9 4 Operation as multiple PWM output function in the RL78 G10 User s Manual The illegal instruction is generated when instruction code FFH is executed Reset by the illegal instruction execution not issued by emulation with the on chip debug emulator Use this product within the voltage range from 2 25 to 5 5 V because the detection voltage Vspor of the
40. rrupt control 2ch PCLBUZO INTPO INTP1 8 10 bit K gt A D converter 4 ch Low speed Watchdog timer on chip oscillator ANIO to Page 6 of 32 RL78 G10 1 OUTLINE 1 5 2 16 pin products TIO0 TOO0 PORT 0 lt 8 PO00 to P07 TIO1 TOO1 C PORT 4 K 2 PA40 P41 TIO2 TO02 C PORT 12 K 3 P121 P122 P125 TIO3 PORT 13 P137 Code flash 4 KB L Paisu RxDO output control TxDO Key return son merus KO um 5100 control SO00 Interrupt control INTPO to INTP3 SCKO01 pun 5101 5B 5001 SCLOO SDAOO TOOLO On chip debugger KLID Clock generator Reset generator Main OSC 1 to 20 MHz 8 10 bit AD converter 7 ch Watchdog timer 4 12 bit interval timer ANIO to ANIG Low speed on chip oscillator BCD adjustment dup X1 X2 EXCLK High speed SCLAO cao Selectable Low speed gh spe on chip on chip SDAAD reset oscillator oscillator 15 kHz 1 25 to 20 MHz Voo Vss IVREFO IVCMPO VCOUTO K R01DS0207EJ0300 Rev 3 00 13 NE S AS Page 7 of 32 Nov 19 2014 RL78 G10 1 OUTLINE 1 6 Outline of Functions This outline describes the function at the time when Peripheral I O redirection register PIOR is set to OOH 10 pin 16 pin R5F10Y14 R5F10Y16 R5F10Y17 R5F10Y44
41. through the area between VIL MAX and VIH MIN 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device 3 PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare
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