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Microcontroller User`s Manual

1. Clear CLR A A 0 Complement CPLA Ai O Ai Rotate RXX A 1 Shift SXX Rm or Wj 1 SWAP A A3 0 AT 4 Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States A Rn Reg to acc 1 1 2 2 A dir8 Dir byte to acc 2 1 3 2 1 3 A Ri Indir addr to acc 1 2 2 3 A data Immediate data to acc 2 1 2 1 dir8 A Acc to dir byte 2 2 4 2 2 4 dir8 data Immediate data to dir byte 3 3 4 3 3 4 Rmd Rms Byte reg to byte reg 3 2 2 1 ie WRjd WRjs Word reg to word reg 3 3 2 2 XRL Rm data 8 bit data to byte reg 4 3 3 2 WRij data16 16 bit data to word reg 5 4 4 3 Rm dir8 Dir addr to byte reg 4 3 3 3 2 3 WRi dir8 Dir addr to word reg 4 4 3 3 Rm dir16 Dir addr 64K to byte reg 5 3 4 2 WRj dir16 Dir addr 64K to word reg 5 4 4 3 Rm WRj Indir addr 64K to byte reg 4 3 3 2 Rm DRk Indir addr 16M to byte reg 4 4 3 3 CLR A Clear acc 1 1 1 1 CPL A Complement acc 1 1 1 1 RL A Rotate acc left 1 1 1 1 RLC A Rotate acc left through the carry 1 1 1 1 RR A Rotate acc right 1 1 1 1 Rotate acc right through the carry 1 1 1 1 Ert Rm Shift byte reg left 3 1 WRj Shift word reg left 3 1 NOTES 1 See Instruction Descriptions on page A 26 2 shaded cell denotes an instruction in the MCS9 51 architecture 3 If this instruction addresses an I O port Px x 0 3 add 1 to the number of states 4 If this i
2. E7 00000000 D8 CCON CMOD 1 CCAPM2 CCAPM4 DF 00x00000 00xxx000 x0000000 x0000000 x0000000 x0000000 x0000000 PSW PSW1 DO D7 00000000 00000000 C8 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 CF 00000000 xxxxxx00 00000000 00000000 00000000 00000000 7 IPL ADEN PH B8 0 gt B BF x0000000 00000000 00000000 P IPH BO 3 0 B7 11111111 x0000000 IE ADDR A8 9 S AF 00000000 00000000 P2 WDTRST 7 11111111 XXXXXXXX SCON SBUF 98 9F 00000000 90 B 97 11111111 88 TCON TMOD TLO TL1 THO TH1 00000000 00000000 00000000 00000000 00000000 00000000 80 SP DPL DPH DPXL PCON 87 11111111 00000111 00000000 00000000 00000001 00xx0000 0 8 1 9 2 A 3 B 4 C 5 D 6 E 7 F NOTE Shaded areas represent unimplemented SFR locations Locations S 000H S 07FH and S 100H S 1FFH are also unimplemented ADDRESS SPACES The following tables list the mnemonics names and addresses of the SFRs Table 3 6 on page 3 18 Core SFRs Table 3 7 on page 3 18 I O Port SFRs Table 3 8 on page 3 19 Serial I O SFRs Table 3 9 on page 3 19 Timer Counter and Watchdog Timer SFRs Table 3 10 on page 3 19 Programmable Counter Array PCA SFRs Table 3 6 Core SFRs Mnemonic Name Address ACC Accumulator S EOH Bi B Register S FOH PSW Progra
3. nenne rennen nnns 14 7 14 6 2 Configuration Bytes nnne nnne 14 8 14 6 9 LOCK Bit SYSTEM noe a PE e toten eV 14 8 14 6 4 Encryption Array 5 Axi nies A Pa A aie ab d ecu 14 9 14 6 5 Signature Bytes eene rete o o dae dede vested 14 10 14 7 VERIFYING THE 83 2515 SB SP SQ 14 10 14 8 VERIFYING THE 80C251SB ROMLESS A STEPPING 14 10 APPENDIX A INSTRUCTION SET REFERENCE A 1 NOTATION FOR INSTRUCTION OPERANDS seen A 2 2 MAP AND SUPPORTING TABLES eee A 4 INSTRUCTION SET SUMMARY sssssseseeeeeeneneneen nennen nnne tenete nennen nni A 11 A 3 1 Execution Times for Instructions that Access the Port 5 A 11 A 3 2 Instruction Surmmaries cete t B nec ee ete iced epe ae ntn A 14 4 INSTRUCTION DESCRIPTIONS sse A 26 APPENDIX B SIGNAL DESCRIPTIONS APPENDIX C REGISTERS GLOSSARY INDEX CONTENTS intel Figure 2 1 2 2 3 1 3 2 3 4 3 5 3 6 3 7 3 8 4 2 4 8 4 5 4 6 4 7 4 8 4 9 4 10 5 1 5 8 6 1 6 3 6 4 6 6 6 7 7 2 7 8 8 1 8 2 8 4 8 5 8 6 8 7 8 9 FIGURES Page Functional Block Diagram of the 8XC251SA SB SP 9
4. 7 0 EA EC ET2 ES ET1 EX1 ETO EXO ums iens Function 7 EA Global Interrupt Enable Setting this bit enables all interrupts that are individually enabled by bits 0 6 Clearing this bit disables all interrupts except the TRAP interrupt which is always enabled 6 EC PCA Interrupt Enable Setting this bit enables the PCA interrupt 5 ET2 Timer 2 Overflow Interrupt Enable Setting this bit enables the timer 2 overflow interrupt 4 ES Serial I O Port Interrupt Enable Setting this bit enables the serial I O port interrupt 3 ET1 Timer 1 Overflow Interrupt Enable Setting this bit enables the timer 1 overflow interrupt 2 1 External Interrupt 1 Enable Setting this bit enables external interrupt 1 1 ETO Timer 0 Overflow Interrupt Enable Setting this bit enables the timer 0 overflow interrupt 0 EXO External Interrupt 0 Enable Setting this bit enables external interrupt 0 intel i REGISTERS IPHO Address S B7H Reset State X000 0000B Interrupt Priority High Control Register 0 IPHO together with IPLO assigns each interrupt a priority level from 0 lowest to 3 highest IPHO x IPLO x Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPHO 6 IPHO 5 4 IPHO 3 IPHO 2 IPHO 1 0 Md ME E Function 7 Reserved The value read from this bit is indeterminate Do
5. XXXX Bit Instruction 0001 JBC bit 0010 JB bit 0011 JNB bit 0111 ORL CY bit 1000 ANL CY bit 1001 MOV bit CY 1010 MOV CY bit 1011 CPL bit 1100 CLR bit 1101 SETB bit 1110 ORL bit 1111 ANL CY bit A 7 INSTRUCTION SET REFERENCE intel Table A 12 PUSH POP Instructions Instruction Byte 0 x Byte 1 Byte 2 Byte 3 PUSH data 0000 0010 data PUSH data16 0000 0110 data16 high data16 low PUSH Rm C A m 1000 PUSH WRj e A j 2 1001 PUSH DRk k 4 1011 MOV DRk PC 4 0001 POP Rm D A m 1000 POP WRj D A j 1001 POP DRk D A k 4 1011 Table A 13 Control Instructions Instruction Byte 0 Byte 1 Byte 2 Byte 3 EJMP addr24 8 A addr 23 16 addr 15 8 addr 7 0 ECALL addr24 9 A addr 23 16 addr 15 8 addr 7 0 LUMP WRj 8 9 j 2 0100 WRj 9 9 j 2 0100 EJMP DRk 8 9 k 4 1000 ECALL DRk 9 9 k 4 1000 ERET A A JE rel 8 8 rel JNE rel 7 8 rel JLE rel 2 8 rel JG rel 3 8 rel JSL rel 4 8 rel JSGE rel 5 8 rel JSLE rel 0 8 rel JSG rel 1 8 rel TRAP B 9 In tel INSTRUCTION SET REFERENCE Table A 14 Displacement Extended MOVs Instruction Byte 0 Byte 1 Byte 2 Byte 3 MOV Rm WRi dis 0 9 m j 2 dis 15 8 dis 7 0 MOV W
6. 13 21 13 6 5 1 Application Requiring Fast Access to the Stack 13 21 13 6 5 2 An Application Requiring Fast Access to Data 13 21 13 6 6 Example 6 RD1 0 11 16 bit Bus External EPROM and RAM 13 24 13 6 7 Example 7 RD1 0 01 17 bit Bus External 13 25 viii intel 13 7 EXTERNAL BUS AC TIMING 13 25 19 74 Explanation of AC Symbols iei cerit here tees ca 13 26 19 72 AC Timing Definitions oet et gerere 13 31 CHAPTER 14 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 14 1 ZGENERAL AE ham 14 1 14 1 1 Programming Considerations for On chip Code Memory 14 2 14 2 EPROM DeViGES ere DER eI OUO 14 3 14 2 PROGRAMMING AND VERIFYING MODES eene 14 3 14 3 GENERAL SETUP ueneno ea a a teal 14 3 14 4 PROGRAMMING 1 4000000000000 0000010 nennen nennen nnne nennen 14 6 14 5 icit ots eA erate petro eee tern estes 14 7 14 6 PROGRAMMABLE FUNCTIONS sess nnne nnne nennen 14 7 14 6 1 On chip Code Memory
7. 13 15 Memory Space for Example 2 13 16 Bus Diagram for Example 3 87C251SB 83C251SB in Nonpage Mode 13 17 Memory Space for Example 3 eene nen nennen 13 18 Bus Diagram for Example 4 87C251SB 83C251SB in Nonpage Mode 13 19 Memory Space for 4 eee nennen nnne 13 20 xi CONTENTS intel FIGURES Figure Page 13 20 Bus Diagram for Example 5 80C2518SB in Nonpage 13 22 13 21 Memory Space for Examples 5 13 23 13 22 Bus Diagram for Example 6 80C251SB in Page 13 24 13 23 Bus Diagram for Example 7 80C251SB in Page 13 25 13 24 External Bus Cycle Timing Code Fetch Nonpage Mode 13 26 13 25 External Bus Cycle Timing Data Read in Nonpage 13 27 13 26 External Bus Cycle Timing Data Write in Nonpage 13 28 13 27 External Bus Cycle Timing Code Fetch in Page 13 29 13 28 External Bus Cycle Timing Data Read in Page 13 30 13 29 External Bus Cycle Timing Data Write in Page 13 31 14 1 Setup for Programm
8. Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States A Rn Reg to acc 1 1 2 2 xS A dir8 Dir byte to acc 2 1 2 2 1 2 A Ri Indir addr to acc 1 2 2 3 A data Immediate data to acc 2 1 2 1 Rmd Rms Byte reg to from byte reg 3 2 2 1 WRjd WRjs Word reg to from word reg 3 3 2 2 DRkd DRks Dword reg to from dword reg 3 5 2 4 Rm data Immediate 8 bit data to from byte reg 4 3 3 2 WRij data16 Immediate 16 bit data to from word reg 5 4 4 3 ADD DRk 0data16 16 bit unsigned immediate data to from 5 6 4 5 dword reg REB Rm dir8 Dir addr to from byte reg 4 3 2 3 2 2 WRi dir8 Dir addr to from word reg 4 4 3 3 Rm dir16 Dir addr 64K to from byte reg 5 3 4 2 WRj dir16 Dir addr 64K to from word reg 5 4 4 3 Rm WRj Indir addr 64K to from byte reg 4 3 3 2 Rm DRk Indir addr 16M to from byte reg 4 4 3 3 A Rn Reg to from acc with carry 1 1 2 2 ADDC A dir8 Dir byte to from acc with carry 2 1 2 2 1 2 SUBB A Ri Indir RAM to from acc with carry 1 2 2 3 A data Immediate data to from acc with carry 2 1 2 1 NOTES 1 shaded cell denotes an instruction in the MCS 51 architecture 2 If this instruction addresses an I O port x 3 0 add 1 to the number of states intel INSTRUCTION SET REFERENCE Table A 20 Summary of Compare Instructions Compare CMP lt dest gt lt src gt dest opnd src opnd Binary Mode Source Mode
9. Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 1001 1110 uuuu 1000 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB DRk lt data16 SUB Rm 8 Binary Mode Source Mode Bytes 4 3 States 3t 2t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1001 1110 5555 0001 direct Code in A5 Encoding Source Encoding Operation SUB Rm lt Rm dir8 SUB WRj dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 1001 1110 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB WRj lt WRj dir8 SUB Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 INSTRUCTION SET REFERENCE intel Encoding 1001 1110 5555 0011 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rm lt Rm dir16 SUB WRj dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 1001 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB WRj lt WRj dir16 SUB Rm QWRj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 1001 1110 tttt 1001 ssss 000
10. 7 0 B Register Contents Bit Bit Number Mnemonic Function 7 0 B 7 0 B Register REGISTERS intel CCAPxH CCAPxL x 0 4 Address Soya HR SERN SEN CCAP2H L S FCH S ECH CCAP3H L S FDH S EDH CCAP4H L S FEH S EEH Reset State XXXX XXXXB PCA Module Compare Capture Registers These five register pairs store the 16 bit comparison value or captured value for the corresponding compare capture modules In the PWM mode the low byte register controls the duty cycle of the output waveform High Low Byte of Compare Capture Values Bit Bit Number Mnemonic Function 7 0 7 0 High byte of PCA comparison or capture values CCAPxL 7 0 Low byte of PCA comparison or capture values intel REGISTERS CCAPMx x 0 4 Address 2 S DCH S DDH S DEH Reset State X000 0000B PCA Compare Capture Module Mode Registers These five registers select the operating mode of the corresponding compare capture module Each register also contains an enable interrupt bit ECCFx for generating an interrupt request when the module s compare capture flag CCFx in the CCON register is set See Table 9 3 on page 9 15 for mode select bit combinations 7 0 ECOMx CAPPx CAPNx MATx TOGx PWMx ECCFx Bit Bit Number Mnemonic Function 7 Reserved The value read from this bit is
11. The instruction JSGE LABEL1 causes program execution to continue at LABEL1 if the N flag and the OV flag have the same value Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0101 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JSGE PC PC 2 IF N OV THEN PC lt PC rel Jump if less than signed If the N flag and the OV flag have different values branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice CY AC OV N 2 intel Example Bytes States Encoding Hex Code in Operation JSLE rel Function Description Flags Example Bytes States Encoding Hex Code in INSTRUCTION SET REFERENCE The instruction JSL LABEL1 causes program execution to continue at LABEL1 if the N flag and the OV flag have different values Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0100 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JSL PC PC 2 IF OV THEN PC PC rel Jump if less than or equal signed If the Z flag is set OR if the the N flag and the OV flag have different values branch to the address spec
12. pin high and asserts TI 51 to indicate the end of the transmission 10 4 intel SERIAL I O PORT Transmit uu S3P1 S6P1 Write to JL SBUF 56 2 Shift DL Dn S6P2 S6P2 S6P2 S6P2 o No X 9 S6P2 S6P2 TI HN LC Receive Eo rr 0 tabe s ibo S3P1 S6P1 Write to REN CI RI SCON Set Clear S6P2 Shift 55 D 56 2 56 2 56 2 56 2 DO D1 D6 D7 56 2 56 2 55 2 _ S1P1 4124 02 Figure 10 3 Mode 0 Timing 10 2 1 2 Reception Mode 0 To start a reception in mode 0 write to the SCON register Clear bits SMO SM1 and RI and set the REN bit Hardware executes the write to SCON in the last phase S6P2 of a peripheral cycle Figure 10 3 In the second peripheral cycle following the write to SCON goes low at S3P1 for the first clock signal pulse and the LSB DO is sampled on pin at S5P2 The DO bit is then shift ed into the shift register After eight shifts at S6P2 of every peripheral cycle the LSB D7 is shift ed into the shift register and hardware asserts RI SIPI to indicate a completed reception Software can then read the received byte from SBUF 10 5 SERIAL I O PORT intel 10 2 2 Asynchronous Modes Modes 1 2 and 3 The serial port has three asynchronous modes of operation Mode 1 Mode 1 is a full duplex
13. 2 2 The CRU a ittis mmt tete lec m A UND 2 5 Clocking Definitions fis icc ree ie ant eet gencre vedo ee ie e veces 2 6 Address Spaces for MCS 251 Microcontrollers 3 1 Address Spaces for the MCS 51 Architecture 3 Address Space Mappings MCS 51 Architecture to MCS 251 Architecture 3 4 8XC251SA SB SP SQ Memory Space Hardware Implementation of the 8XC251 SA SB SP Memory Space EERE e TA The Register File e m nee Cre peo e Eat a t 3 11 Register File Locations 0 7 812 Dedicated Registers in the Register File and their Corresponding SFR 103 14 B stepping Configuration Array 4 4 B stepping Configuration Array External sese 4 5 User Configuration Byte 0 4 6 User Configuration Byte 4 7 Configuration Byte 0 4 9 Configuration Byte nennen nennen nere 4 10 Internal External Memory Mapping RD1 0 00 and 01 4 13 Internal External Memory NIA a 0 10 ANd 1 4 14 Binary Mode Opcode Map LU Exe Source Mode Opcode 2 4 19 Word and Double word Storage in Big Endien 5 3 Program Status W
14. R7 i e the range of n is 0 7 The instruction ADD Rm data uses Rm to denote R15 i e the range of m is 0 15 Table 5 2 summarizes the notation used for the register indices When an instruction contains two registers of the same type e g MOV Rmd Rms the first index denotes destination and the second index s denotes source 5 2 3 Address Notation In the MCS 251 architecture memory addresses include a region number 00 01 FF Fig ure 3 4 on page 3 6 SFR addresses have a prefix 5 S 000H S 1FFH The distinction be tween memory addresses and SFR addresses is necessary because memory locations 00 0000 00 01FFH and SFR locations S 000H S 1FFH can both be directly addressed in an instruction 5 2 PROGRAMMING Memory 200H 201H 202H 203H 29 0 2 23 MOV WRO A3B6H MOV 00 0201H WRO MOV DR4 0000C4D7H Register File 0 1 2 3 4 5 6 7 en oon o us eee WRO DR4 Contents of register file and memory after execution A4242 01 Figure 5 1 Word and Double word Storage in Big Endien Form Table 5 2 Notation for Byte Registers Word Registers and Dword Registers kcu Register Range Ri RO R1 Byte Rn RO R7 Rm Rmd Rms RO R15 Word WRj WRid WRis WRO WR2 WR4 WR30 Dword DRk DRkd DRks DRO DR4 8 DR28 DR56 DR60 Instructions in the MCS
15. seems 4 2 4 3 DEVICE CONFIGURATION A STEPPING essen 4 2 4 4 THE GONEIGURATION BLITS ii ace citet eeepc etre tete acere 4 3 4 5 DEVICE CONFIGURATION A STEPPING COMPATIBLE 4 5 4 6 CONFIGURING THE EXTERNAL MEMORY 4 11 4 6 1 Page Mode and Nonpage Mode PAGE 2 4 11 4 6 2 Configuration Bits RD 1 0 ci en c trae o cere eee uerb bb cesa tia 4 11 4 6 2 1 RD1 0 00 18 External Address Bits 2 2 2210112 4 12 4 6 2 2 RD1 02 01 17 External Address Bits eee 4 12 4 6 2 3 RD1 0 10 16 External Address Bits 4 15 4 6 24 RD1 0 11 Compatible with MCS 51 Microcontrollers 4 15 4 6 38 Wait State Configuration Bits essen nennen 4 16 4 6 3 1 Configuration Bits WSA1 0 WSB1 08 4 16 4 6 3 2 Configuration Bits WSA and WSB senem 4 16 4 6 3 3 Configuration BIC XAL EH n HERR RR ERE 4 16 4 7 OPCODE CONFIGURATIONS SRO esses 4 17 4 7 1 Selecting Binary Mode or Source Mode sse 4 18 4 8 MAPPING ON CHIP CODE MEMORY TO DATA MEMORY EMAP 4 20 4 9 INTERRUPT STACK MODE 4 20 CHAPTER 5 PROGRAMMING 5 1 SOURCE MOD
16. Rms DIV WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 22 21 Encoding 1000 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation DIV 16 bit operands WRjd lt remainder WRjd WRjd 2 lt quotient WRjd WRjs if dest jd 0 4 8 28 WRjs WRjd 2 lt remainder WRid WRis if dest jd 2 6 10 30 WRjd lt quotient WRjd WRjs For word operands lt dest gt lt src gt WRjd WRjs the 16 bit quotient is in WR jd 2 and the 16 bit remainder is in WRjd For example for a destination register WR4 assume the quotient is 1122H and the remainder is 3344H Then the results are stored in these register file locations Location 4 5 6 7 Contents 33H 44H 11H 22H A 58 intel Function Description Flags Hex Code in Example Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Divide Divides the unsigned 8 bit integer in the accumulator by the unsigned 8 bit integer in register B The accumulator receives the integer part of the quotient register B receives the integer remainder The CY and OV flags are cleared Exception if register B contains 00H the values returned in the accumulator and register B are undefined the CY flag is cleared and the OV flag is set CY AC OV N 2 For division b
17. direct addr Binary Mode Encoding Source Mode A5 Encoding MOV Ri lt dir8 Binary Mode 2 1t tlf this instruction addresses a port Px x 0 3 add 1 state 3 21 Source Mode 1010 1rrr direct addr A 85 INSTRUCTION SET REFERENCE intel Hex Code in Operation MOV AJdir8 Bytes States Encoding Hex Code in Operation MOV A Ri Bytes States Encoding Hex Code in Operation MOV A Rn Bytes States Encoding Hex Code in Operation A 86 Binary Mode Encoding Source Mode A5 Encoding MOV Rn lt dir8 Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state 1110 0101 direct addr Binary Mode Encoding Source Mode Encoding MOV A lt dir8 Binary Mode Source Mode 1 2 2 3 1110 0111 Binary Mode Encoding Source Mode A5 Encoding MOV A lt Ri Binary Mode Source Mode 1 2 1 2 1110 1rrr Binary Mode Encoding Source Mode A5 Encoding MOV lt Rn intel MOV dir8 A Bytes States Encoding Hex Code in Operation MOV Ri A Bytes States Encoding Hex Code in Operation MOV Rn A Bytes States Encoding Hex Code in Operation MOV Rmd Rms Bytes States Encoding
18. 5 1 PROGRAMMING intel 5 2 4 Data Types Table 5 1 lists the data types that are addressed by the instruction set Words or dwords double words can be in stored memory starting at any byte address alignment on two byte or four byte boundaries is not required Words and dwords are stored in memory and the register file in big endien form Table 5 1 Data Types Data Type Number of Bits Bit 1 Byte 8 Word 16 Dword Double Word 32 5 2 1 1 Order of Byte Storage for Words and Double Words MCS 251 microcontrollers store words 2 bytes and double words 4 bytes in memory and in the register file in big endien form In memory storage the most significant byte MSB of the word or double word is stored in the memory byte specified in the instruction the remaining bytes are stored at higher addresses with the least significant byte LSB at the highest address Words and double words can be stored in memory starting at any byte address In the register file the MSB is stored in the lowest byte of the register specified in the instruction For a description of the register file see page 3 10 The code fragment in Figure 5 1 illustrates the storage of words and double words in big endien form 5 2 2 Register Notation In register addressing instructions specific indices denote the registers that can be used in that instruction For example the instruction ADD A Rn uses Rn to denote any one of RO
19. Variations CLR bit51 Binary Mode Source Mode Bytes 4 3 States 2T 2T tlf this instruction addresses a port x 0 3 add 2 states Encoding 1100 0010 Bit addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation CLR bit51 0 CLR CY Binary Mode Source Mode Bytes 1 1 States 1 1 Encoding 1100 0011 Hex Code in Binary Mode Encoding Source Mode Encoding Operation CLR CY 0 CLR bit Binary Mode Source Mode Bytes 4 4 States 4T 3t tlf this instruction addresses a port Px x 0 3 add 2 states Encoding 1010 1001 1100 0 dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CLR bit lt 0 A 46 intel INSTRUCTION SET REFERENCE CMP lt dest gt lt src gt Function Compare Description Subtracts the source operand from the destination operand The result is not stored in the destination operand If a borrow is needed for bit 7 the CY borrow flag is set otherwise it is clear When subtracting signed integers the OV flag indicates a negative result when a negative value is subtracted from a positive value or a positive result when a positive value is subtracted from a negative value Bit 7 in this description refers to the most significant byte of the operand 8 16 or 32 bit The source operand allows four addressing modes register direct
20. 02 0000 TT FFFFH MCS 51 Architecture External Data Memory 01 0000H 0000H MCS 51 Architecture ds Internal Data Memory 00 0000H 00H SFR Space 512 Bytes FFH MCS 51 Architecture SFRs Register File 64 Bytes ERBEN i 0 MCS 51 Architecture R F 7 A4133 01 Figure 3 3 Address Space Mappings MCS 51 Architecture to MCS 251 Architecture Table 3 1 Address Mappings MCS 51 Architecture MCS 251 Architecture Memory Type D _ 3 ata Size Location Addressing Location Indirect using i Code 64 Kbytes 0000H FFFFH MOVC instr FF 0000H FF FFFFH Indirect using External Data 64 Kbytes 0000H FFFFH MOVX instr 01 0000H 01 FFFFH 128 bytes 00H 7FH Direct Indirect 00 0000H 00 007FH Internal Data 128 bytes 80H FFH Indirect 00 0080H 00 00FFH SFRs 128 bytes S 80H S FFH Direct 5 080 5 0 Register File 8 bytes RO R7 Register RO R7 3 4 intel ADDRESS SPACES The 64 Kbyte external data memory for MCS 51 microcontrollers is mapped into the memory region specified by bits 16 23 of the data pointer DPX i e DPXL DPXL is accessible as register file location 57 and also as the SFR at S 084H see Dedicated Registers on page 3 13 The re set value of DPXL is 01H which maps the external memory to region 01 as shown in Figure 3 3 You can change this mapping by writing a different value to DPXL mapping of the MCS 51 microcontroller external data
21. A4146 01 Figure 13 22 Bus Diagram for Example 6 80C251SB in Page Mode 13 24 intel EXTERNAL MEMORY INTERFACE 13 6 7 Example 7 RD1 0 01 17 bit Bus External Flash In this example an 80C251SB operates in page mode with a 17 bit external address bus inter faced to 128 Kbytes of flash memory Figure 13 23 Port 2 carries both the upper address bits A15 0 and the data D7 0 while port O carries only the lower address bits A7 0 The 80C251SB A steppingor B stepping is configured for a single read signal PSEN The 128 Kbytes of external flash are accessed via internal memory regions FE and FF in the internal memory space 80C251SB FLASH 128 Kbytes 4151 01 Figure 13 23 Bus Diagram for Example 7 80C251SB in Page Mode 13 7 EXTERNAL BUS AC TIMING SPECIFICATIONS This section defines the AC timing specifications for the B stepping external bus For A stepping AC timing specifications see the A stepping data sheet Always refer to the latest data sheet to insure that your system meets specifications Figures 13 24 13 25 and 13 26 show the bus wave forms for code fetch data read and data write in nonpage mode Figures 13 27 13 28 and 13 29 show the bus waveforms for code fetch data read and data write in page mode Table 13 4 on page 13 27 defines the symbols used in the timing diagrams Tables 13 5 and 13 6 define the tim ing parameters 13 25 EXTERNAL M
22. lt addr 15 0 WRj Binary Mode Source Mode Bytes 3 2 States 9 8 Encoding 1001 1001 ittt 0100 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation LCALL A 81 INSTRUCTION SET REFERENCE intel LJMP lt dest gt Function Description Flags Example LJMP addr16 Bytes States Encoding Hex Code in Operation LJMP WRj Bytes States Encoding Hex Code in Operation A 82 Long Jump Causes an unconditional branch to the specified address by loading the high and low bytes of the PC respectively with the second and third instruction bytes The destination may therefore be anywhere in the 64 Kbyte memory region where the next instruction is located CY AC OV N 2 The label JMPADR is assigned to the instruction at program memory location 1234H After executing the instruction LJMP JMPADR at location 0123H the program counter contains 1234H Binary Mode Source Mode 3 3 5 5 0000 0010 addr15 addr8 7 Binary Encoding Source Encoding LJMP PC lt addr 15 0 Binary Mode Source Mode 3 2 6 5 1000 1001 tttt 0100 Binary Mode Encoding Source Mode Encoding LJMP lt WRi intel INSTRUCTION SET REFERENCE MOV dest src Function Description Flags Example Variations
23. wes ETE nece quts 13 1 13 22 EXTERNAL BUS CYCLES ied De IC Lee CERT 13 3 19 2 BusCycle Definitions x taeda doen weet 13 3 13 2 2 Nonpage Mode Bus Cycles sesssssseseeeeeeenneee nennen nennen 13 4 13 2 8 Page Mode Bus Cycles nennen nnne neret nennen 13 6 13 3 EXTERNAL BUS CYCLES WITH WAIT 5 6 13 8 13 31 Extending RDZ WR PSEN ssssssssesseeneenee nennen rennen enne neret 13 8 19 9 2 Extending ALE iere e d hein 13 10 13 4 CONFIGURATION BYTE BUS CYOCLES sese 13 10 19 5 PORTOAND PORT 2 STATUS iiit eee ir ste RE 13 11 13 5 1 Port 0 and Port 2 Pin Status Nonpage Mode 13 12 13 5 2 Port 0 and Port 2 Pin Status in Page 13 12 13 6 EXTERNAL MEMORY DESIGN EXAMPLES seen 13 12 13 6 1 Example 1 RD1 0 00 18 bit Bus External Flash and RAM 13 13 13 6 2 Example 2 RD1 0 01 17 bit Bus External Flash and RAM 13 15 13 6 3 Example 3 RD1 0 01 17 bit Bus External RAM 13 17 13 6 4 Example 4 RD1 0 10 16 bit Bus External RAM _ 13 19 13 6 5 Example 5 RD1 0 11 16 bit Bus External EPROM and RAM
24. 7 lt 0 Rotate accumulator right through carry flag Rotates the eight bits in the accumulator and the CY flag one bit to the right Bit moves into the CY flag position the original value of the CY flag moves into the bit 7 position OV N Z V The accumulator contains 0 5 11000101B and the CY flag is clear After executing the instruction RRC A the accumulator contains 62 01100010B and the CY flag is set Binary Mode Source Mode 1 1 1 1 0001 0011 Binary Mode Encoding Source Mode Encoding RRC lt A a41 7 lt lt A 0 123 INSTRUCTION SET REFERENCE SETB bit Function Description Flags Example SETB bit51 Bytes States Encoding Hex Code in Operation SETB CY Bytes States Encoding Hex Code in Operation A 124 intel Set bit Sets the specified bit to one SETB can operate on the CY flag or any directly addressable bit No flags are affected except the CY flag for instruction with CY as the operand OV N Z V The CY flag is clear and output Port 1 contains 34H 00110100B After executing the instruction sequence SETB CY SETB P1 0 the CY flag is set and output Port 1 contains 35H 00110101B Binary Mode Source Mode 2 2 21 2t tlf this instruction addresses a port Px x 0
25. 7 0 T20E DCEN Nuribel Function 7 2 Reserved The values read from these bits are indeterminate Do not write a 1 to these bits 1 2 Timer 2 Output Enable Bit In the timer 2 clock out mode connects the programmable clock output to external pin T2 0 DCEN Down Count Enable Bit Configures timer 2 as an up down counter C 33 REGISTERS intel TCON Address 5 88 Reset State 0000 0000B Timer Counter Control Register Contains the overflow and external interrupt flags and the run control and interrupt transition select bits for timer 0 and timer 1 7 0 TF1 TR1 TFO TRO IE1 IT1 IEO ITO Bit Bit Number Mnemonic Function 7 TF1 Timer 1 Overflow Flag Set by hardware when the timer 1 register overflows Cleared by hardware when the processor vectors to the interrupt routine 6 TR1 Timer 1 Run Control Bit Set cleared by software to turn timer 1 on off 5 TFO Timer 0 Overflow Flag Set by hardware when the timer 0 register overflows Cleared by hardware when the processor vectors to the interrupt routine 4 TRO Timer 0 Run Control Bit Set cleared by software to turn timer 1 on off 3 IE1 Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INT1 pin Edge or level triggered see IT1 Cleared when interrupt is processed if edge triggered 2 IT1 Interrupt 1 Type Control Bit Set
26. 0001 dir8 addr Oper WRj dir8 x E j 2 0101 dir8 addr Oper DRk dir8 k 4 1101 dir8 addr Oper Rm dir16 x m 0011 dir16 addr high dir16 addr low Oper WRij dir16 x E 2 0111 dir16 high dir16 addr low Oper DRk dir16 1 k 4 1111 dir16 addr high dir16 addr low Oper Rm WRij j 2 1001 m 00 Oper Rm DRk x E k 4 1011 m 00 NOTE 1 For this instruction the only valid operation is MOV Table A 9 High Nibble Byte 0 of Data Instructions x Operation Notes 2 ADD reg op2 9 SUB reg op2 B CMP reg op2 1 All addressing modes are 4 ORL reg op2 2 supported 5 ANL reg op2 2 6 XRL reg op2 2 7 MOV reg op2 8 DIV reg op2 Two modes only reg op2 Rmd Rms A MUL reg op2 reg op2 Wjd Wjs NOTES 1 The CMP operation does not support DRk direct16 2 Forthe ORL ANL and operations neither reg nor op2 can be DRk intel INSTRUCTION SET REFERENCE of the bit instructions in the MCS 251 architecture Table 7 have opcode A9 which serves as an escape byte similar to A5 The high nibble of byte 1 specifies the bit instruction as given in Table A 10 Table A 10 Bit Instructions Instruction Byte 0 x Byte 1 Byte 2 Byte 3 k Bit Instr dir8 A 9 XXXX O bit dir8 addr rel addr Table A 11 Byte 1 High Nibble for Bit Instructions
27. INDEX extended 4 16 following reset 11 7 idle mode 12 4 programming and verifying nonvolatile memory 14 3 ANL instruction 5 9 5 11 for bits A 23 ANL instruction 5 11 for bits A 23 Arithmetic instructions 5 8 5 9 table of A 14 A 15 A 16 B B register 3 15 C 5 as SER 3 17 3 18 in register file 3 13 Base address 5 4 Baud rate See Serial I O port Timer 1 Timer 2 Binary and source modes 2 4 4 17 4 19 5 1 opcode maps 4 17 selection guidelines 2 4 4 18 Bit address addressing modes 5 12 definition A 3 examples 5 11 Bit instructions 5 1 5 11 5 12 addressing modes 5 4 5 11 bit51 5 11 A 3 Broadcast address See Serial I O port C Call instructions 5 15 Capacitors bypass 11 2 CCAPIL CCAPAL 3 17 3 20 C 6 CCAPM1 4 3 17 3 19 9 16 C 7 interrupts 6 5 CCON 3 17 3 19 9 14 C 8 Ceramic resonator 11 4 CEX4 0 7 1 CH CL 3 17 3 20 C 9 CJNE instruction A 25 Clock 2 6 Index 1 external 11 4 11 5 external source 11 3 idle and powerdown modes 12 5 idle mode 12 4 powerdown mode 12 5 12 6 sources 11 3 CLR instruction 5 9 5 11 A 17 A 23 CMOD 3 17 3 19 9 13 C 10 interrupts 6 5 CMP instruction 5 8 5 14 A 15 Code constants 4 20 Code fetches external 13 1 13 6 internal 13 6 page hit and page miss 13 6 page mode 13 6 Code memory MCS 51 architecture 3 3 See also On chip code memory External code memory Com
28. SUB R1 RO register 1 contains 75H 01110101B the CY and AC flags are clear and the OV flag is set Binary Mode Source Mode 3 2 2 1 1001 1100 5555 5555 Binary Mode A5 Encoding Source Mode Encoding SUB Rma lt Rmd Rms SUB WRjd WRjs Bytes States Binary Mode Source Mode 3 2 3 2 A 129 INSTRUCTION SET REFERENCE Encoding Hex Code in Operation Bytes States Encoding Hex Code in Operation SUB Rm data 1001 1101 tttt TTET Binary Mode A5 Encoding Source Mode Encoding SUB WRjd WRjd WRjs SUB DRkd DRks Binary Mode 3 5 Source Mode 2 4 1001 1111 uuuu UUUU Binary Mode A5 Encoding Source Mode Encoding SUB DRkd lt DRkd DRks Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 1001 1110 ssss 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rm Rm data SUB WRij data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 1001 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding A 130 Source Mode Encoding intel Operation SUB WRj lt data16 SUB DRk data16 INSTRUCTION SET REFERENCE
29. Timer can generate very low baud rates with the following setup Enable the timer 1 interrupt by setting the bit in the IE register Configure timer 1 to run as a 16 bit timer high nibble of TMOD 0001B Use the timer 1 interrupt to initiate a 16 bit software reload Table 10 4 lists commonly used baud rates and shows how they are generated by timer 1 10 11 SERIAL I O PORT intel Table 10 4 Timer 1 Generated Baud Rates for Serial I O Modes 1 and 3 Baud E SMOD1 uod Foso C T Mode Reload 62 5 Kbaud Max 12 0 MHz 1 2 FFH 19 2 Kbaud 11 059 MHz 1 2 FDH 9 6 Kbaud 11 059 MHz 0 2 FDH 4 8 Kbaud 11 059 MHz 0 2 FAH 2 4 Kbaud 11 059 MHz 0 0 2 F4H 1 2 Kbaud 11 059 MHz 0 2 137 5 Baud 11 986 MHz 0 2 1DH 110 0 Baud 6 0 MHz 0 2 72H 110 0 Baud 12 0 MHz 0 1 FEEBH 10 6 3 3 Timer 2 Generated Baud Rates Modes 1 and 3 Timer 2 may be selected as the baud rate generator for the transmitter and or receiver Figure 10 5 on page 10 13 The timer 2 baud rate generator mode is similar to the auto reload mode A roll over in the TH2 register reloads registers TH2 and TL2 with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software The timer 2 baud rate is expressed by the following formula Timer 2 Overflow Rate Serial I O Modes 1 and Baud Rate 16 10 6 3 4 Selecting Timer 2 as th
30. intel PROGRAMMING Table 5 10 The Effects of Instructions on the PSW and PSW1 Flags Flags Affected 1 5 Instruction Type Instruction CY OV AC 2 N Z ADD ADDC SUB X X X X X SUBB CMP Arithmetic INC DEC X X MUL DIV 3 0 X X X DA X X X ANL ORL XRL CLR A X X CPL A RL RR SWAP Logical RLC RRC SRL SLL X X X SRA 4 CJNE X X X Program Control DJNE X X NOTES 1 X the flag can be affected by the instruction 0 the flag is cleared by the instruction The AC flag is affected only by operations on 8 bit operands If the divisor is zero the OV flag is set and the other bits are meaningless For SRL SLL and SRA instructions the last bit shifted out is stored in the CY bit The parity bit PSW 0 is set or cleared by instructions that change the contents of the accumulator ACC Register R11 PROGRAMMING intel PSW Address S DOH Reset State 0000 0000B 0 FO RS1 RSO OV UD Bit Bit m Number Mnemonic unction 7 Carry Flag The carry flag is set by an addition instruction ADD ADDO if there is a carry out of the MSB It is set by a subtraction SUB SUBB or compare CMP if a borrow is needed for the MSB The carry flag is also affected by some rotate and shift instructions logical bit instructions and bit move instructions and the multiply MUL and decimal adjust DA
31. 0 4 8 28 WRid lt high word of the WRjd X WRjs WRijd 2 lt low word of the WRjd X WRjs if dest jd 2 6 10 30 WRjd 2 lt high word of the WRjd X WRjs WRid low word of the WRjd X WRjs Multiply Multiplies the unsigned 8 bit integers in the accumulator and register B The low byte of the 16 bit product is left in the accumulator and the high byte is left in register B If the product is greater than 255 OFFH the OV flag is set otherwise it is clear The CY flag is always clear CY AC OV N 2 0 The accumulator contains 80 50H and register B contains 160 OAOH After executing the instruction MUL AB which gives the product 12 800 3200H register B contains 32H 00110010B the accumulator contains 00H the OV flag is set and the CY flag is clear Binary Mode Source Mode 1 1 5 5 1010 0100 Binary Mode Encoding Source Mode Encoding MUL lt low byte of A X B B lt high byte of A X B A 107 INSTRUCTION SET REFERENCE intel NOP Function No operation Description Execution continues at the following instruction Affects the PC register only Flags CY AC OV N Z Example You want to produce a low going output pulse on bit 7 of Port 2 that lasts exactly 11 states A simple CLR SETB sequence generates an eight state pulse Each instruction requires four states to write to a port SFR
32. 0 INTx is triggered by a detected low at the pin If ITx 1 INTx is neg ative edge triggered External interrupts are enabled with bits and EX1 EXx in the reg ister see Figure 6 2 on page 6 6 Events on the external interrupt pins set the interrupt request flags IEx in TCON These request bits are cleared by hardware vectors to service routines only if the interrupt is negative edge triggered If the interrupt is level triggered the interrupt service routine must clear the request bit External hardware must deassert INTx before the service rou tine completes or an additional interrupt is requested External interrupt pins must be deasserted for at least four state times prior to a request External interrupt pins are sampled once every four state times a frame length of 666 4 ns at 12 MHz A level triggered interrupt pin held low or high for any five state time period guarantees detection Edge triggered external interrupts must hold the request pin low for at least five state times This ensures edge recognition and sets interrupt request bit EXx The CPU clears EXx au tomatically during service routine fetch cycles for edge triggered interrupts 6 3 INTERRUPT SYSTEM Table 6 3 Interrupt Control Matrix Global Timer Serial Timer Timer Interrupt Name Enable PCA 2 Port 1 INT1 0 INTO Bit Name in IEO Register EA EC ET2 ES ET1 1 Interrupt Priority Within Level 7 L
33. 4 1 4 1 4 DPTR A Acc to external mem 16 bit addr 4 1 5 1 5 NOTES 1 A shaded cell denotes an instruction in the MCS 51 architecture 2 Instructions that move bits are in Table A 26 on page A 23 3 If this instruction addresses an I O port x 0 3 add 1 to the number of states 4 External memory addressed by instructions in the MCS 51 architecture is in the region specified by DPXL reset value 01H See Compatibility with the MCS 51 Architecture on page 3 2 A 21 INSTRUCTION SET REFERENCE intel Table A 25 Summary of Exchange Push and Pop Instructions Exchange Contents lt dest gt lt src gt A o src Exchange Digit XCHD dest src A3 0 lt gt on chip RAM bits 3 0 Push PUSH src SP lt SP 1 SP lt src Pop POP lt dest gt dest SP SP SP 1 Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States A Rn Acc and reg 1 3 2 4 XCH A dir8 Acc and dir addr 2 3 2 2 3 2 A Ri Acc and on chip RAM 8 bit addr 1 4 2 5 A Ri Acc and low nibble in on chip RAM 1 4 2 5 8 bit addr dir8 Push dir byte onto stack 2 2 data Push immediate data onto stack data16 Push 16 bit immediate data onto 4 PUSH stack Rm Push byte reg onto stack 3 4 2 WRj Push word reg onto stack 3 6 2 DRk Push double word reg onto stack 3 10 2 Dir Pop dir byte from stack
34. 6 7 2 Variable Interrupt Parameters Both response time and latency calculations contain fixed and variable components By defini tion it is often difficult to predict exact timing calculations for real time requests One large vari able is the completion time of an instruction cycle coincident with the occurrence of an interrupt request Worst case predictions typically use the longest executing instruction in an architecture s code set In the case of the 8XC251Sx the longest executing instruction is a 16 bit divide DIV However even this 21 state instruction may have only 1 or 2 remaining states to complete before the interrupt system injects a context switch This uncertainty affects both response time and la tency 6 7 2 1 Response Time Variables Response time is defined as the start of a dynamic time period when a source requests an interrupt and lasts until a break in the current instruction execution stream occurs see Figure 6 5 on page 6 9 Response time and therefore latency is affected by two primary factors the incidence of the request relative to the four state time sample window and the completion time of instructions in the response period 1 shorter instructions complete earlier than longer instructions NOTE External interrupt signals require one additional state time in comparison to internal interrupts This is necessary to sample and latch the pin value prior to a poll of interrupts The sample occurs in th
35. 64 Kbytes WR RD PSEN A4145 01 13 22 Figure 13 20 Bus Diagram for Example 5 80C251SB in Nonpage Mode intel EXTERNAL MEMORY INTERFACE FF FE Memory Address Space 512 Kbytes FFFFH 64 Kbytes External EPROM 0000H FD FC 03 02 01 00 External RAM FFFFH 64 Kbytes 1056 Bytes 0420H 1056 Bytes On chip RAM FF FE FD FC 03 02 01 00 00 0000H Memory Address Space 512 Kbytes 0000H FFFFH 64 Kbytes External EPROM FFFFH 64 Kbytes External RAM 1056 Bytes On chip RAM 4175 02 Figure 13 21 Memory Space for Examples 5 and 6 13 23 EXTERNAL MEMORY INTERFACE intel 13 6 6 Example 6 RD1 0 11 16 bit Bus External EPROM and RAM In this example an 80C251SB operates in page mode with a 16 bit external address bus inter faced to 64 Kbytes of EPROM and 64 Kbytes of RAM Figure 13 22 The 80C251SB A step ping or B stepping is configured so that RD is asserted for addresses 7F FFFFH and PSEN is asserted for addresses gt 80 0000 This system is the same as Example 5 Figure 13 20 except that it operates in page mode Ac cordingly the two systems have the same memory map Figure 13 21 and the comments on ad dressing external RAM apply here also EPROM RAM 80C251SB 64 Kbytes 64 Kbytes D7 0 A15 8 D7 0 CE OE WE
36. 8XC251SA 8XC251SB 8XC251SP 8XC251SQ Embedded Microcontroller User s Manual November 1995 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including in fringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcontroller products may have minor variations to this specification known as errata Other brands and names are the property of their respective owners Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 or call 1 800 548 4725 COPYRIGHT INTEL CORPORATION 1995 intel CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1 1 MANUAL CONTENT Siti iiti nde texere taut winless 1 1 1 2 NOTATIONAL CONVENTIONS AND TERMINOLOGY eem 1 3 1 3 RELATED DOCUMENTS 2 2 eL ei ite eene edo Fere tb eed da dent ten Lee 1 5 1 3 1 ENSIS 1 6 1 3 2 Application Notes ene EP Germ Pepe alae dna eee 1 6 1 4 CUSTOMER SERVICE eii ete er ae ertet En es 1 7
37. Bytes States Encoding Hex Code in Operation Logical AND Performs the bitwise logical AND A operation between the specified variables and stores the results in the destination variable The two operands allow 10 addressing mode combinations When the destination is the register or accumulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins CY AC OV N Z Register 1 contains 11000011B and register 0 contains 55H 01010101B After executing the instruction ANL R1 RO register 1 contains 41H 01000001 When the destination is a directly addressed byte this instruction clears combinations of bits in any RAM location or hardware register The mask byte determining the pattern of bits to be cleared would either be an immediate constant contained in the instruction or a value computed in the register or accumulator at run time The instruction ANL P1 01110011B clears bits 7 3 and 2 of output port 1 Binary Mode Source Mode 2 2 21 2t tlf this instruction addresses a port Px x 0 3 add 2 states 0101 0010 direct addr Binary Mode Encoding Source Mode En
38. The B stepping version can be configured to have a 16 bit 17 bit or 18 bit external address bus to address up to 256 Kbytes of memory The A stepping version can be configured to have a 16 bit or 17 bit external address bus to address up to 128 Kbytes of memory The B stepping version can be configured to have 0 1 2 or 3 external wait states for RD WR PSEN The A stepping version can be configured to have 0 or 1 external wait states for RD WR PSEN See Chapter 4 Device Configuration 2 4 8 Configuration Bytes The B stepping version has two configuration bytes UCONFIGO and UCONFIGI located in user code memory See Figures 4 3 and 4 4 for bit definitions 2 9 ARCHITECTURAL OVERVIEW intel The A stepping version has two configuration bytes CONFIGO and CONFIGI located in nonvol atile memory outside the memory address space See Figures 4 5 and 4 6 for bit definitions The B stepping and A stepping configuration bytes differ only in their complements of wait state bits UCONFIGO has two wait state bits WSAI and WSAO WSAO corresponds WSA in CONFIGO UCONFIGI has two wait state bits WSB1 and WSBO plus WSB which is retained for compat ibility 2 10 intel Address Spaces intel CHAPTER 3 ADDRESS SPACES MCS 251 microcontrollers have three address spaces a memory space a special function reg ister SFR space and a register file This chapter describes these address spaces as they apply to all
39. The chip is in powerdown mode 13 2 1 Bus Cycle Definitions Table 13 2 lists the types of external bus cycles It also shows the activity on the bus for nonpage mode and page mode bus cycles with no wait states There are three types of nonpage mode bus cycles code read data read and data write There are four types of page mode bus cycles code read page miss code read page hit data read and data write The data read and data write cy cles are the same for page mode and nonpage mode except the multiplexing of D7 0 on ports 0 and 2 Table 13 2 Bus Cycle Definitions No Wait States Bus Activity Mode Bus Cycle State 1 State 2 State 3 Code Read ALE RD PSEN code in iced Data Read 2 ALE RD PSEN data in Data Write 2 ALE WR WR high data out Code Read Page Miss ALE RD PSEN code in Page Code Read Page Hit 3 PSEN code in Mode Data Read 2 ALE RD PSEN data in Data Write 2 ALE WR WR high data out NOTES 1 Signal timing implied by this table is approximate idealized 2 Data read page mode data read nonpage mode and write page mode write nonpage mode except that in page mode data appears on P2 multiplexed with A15 0 whereas in nonpage mode data appears on PO multiplexed with A7 0 3 The initial code read page hit bus cycle can execute only following a code read page miss cycle 13 3 EXTERNAL MEMORY INTERFACE 13 2 2 Nonpage
40. intel Mnemonic Description Address SBUF Serial Buffer Two separate registers comprise the SBUF register Writing 99H to SBUF loads the transmit buffer reading SBUF accesses the receive buffer SCON Serial Port Control Selects the serial port operating mode SCON enables 98H and disables the receiver framing bit error detection multiprocessor communication automatic address recognition and the serial port interrupt bits SADDR Serial Address Defines the individual address for a slave device A8H SADEN Serial Address Enable Specifies the mask byte that is used to define the B8H given address for a slave device IB Bus Mode 0 Transmit Receive Shift Register Interrupt Request RI TI Serial A4123 01 10 2 Figure 10 1 Serial Port Block Diagram intel SERIAL I O PORT The serial port control SCON register Figure 10 2 configures and controls the serial port SCON Address 98H Reset State 0000 0000B 7 0 FE SMO SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic Function 7 FE Framing Error Bit To select this function set the SMODO bit in the PCON register Set by hardware to indicate an invalid stop bit Cleared by software not by valid frames SMO Serial Port Mode Bit 0 To select this function clear the SMODO bit in the PCON register Software writes to bits SMO and SM1 to select the serial po
41. lt Rm V WRj ORL Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0100 1110 uuuu 1011 ssss 0000 A 113 INSTRUCTION SET REFERENCE Hex Code in Operation Binary Mode A5 Encoding Source Mode Encoding ORL Rm lt Rm V DRk ORL CY lt src bit gt Function Description Flags Example Variations ORL CY bit51 Bytes States Encoding Hex Code in Operation ORL CY bit51 Bytes States Encoding A 114 Logical OR for bit variables Sets the CY flag if the Boolean value is a logical 1 leaves the CY flag in its current state otherwise A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected CY AC OV N V Set the CY flag if and only if P1 0 1 ACC 7 1 or OV 0 MOV CY P1 0 LOAD CARRY WITH INPUT PIN P10 ORL CY ACC 7 OR CARRY WITH THE ACC BIT 7 ORL CY OV OR CARRY WITH THE INVERSE OF OV Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses a port x 0 3 add 1 state 0111 0010 bit addr Binary Mode Encoding Source Mode Encoding ORL CY lt CY V bit51 Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state 1
42. random byte values other than FFH to prevent the encryption key sequence from being revealed To program the encryption array perform the procedure described in Programming Algorithm on page 14 6 using the program encryption array mode Table 14 1 To preserve the secrecy of the encryption key byte sequence the encryption array can not be ver ified 14 9 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY intel 14 6 5 Signature Bytes The 87C251Sx and 83C251Sx contain factory programmed signature bytes These bytes are lo cated in nonvolatile memory outside the memory address space at 30H 31H and 60H A step ping and 30H 31H 60H and 61H B stepping To read the signature bytes perform the procedure described in Verify Algorithm on page 14 7 using the verify signature mode Table 14 1 Signature byte values are listed in Table 14 3 Table 14 3 Contents of the Signature Bytes ADDRESS CONTENTS DEVICE TYPE 30H 89H Indicates Intel Devices 31H 40H Indicates MCS251 core product 60H 7AH Indicates 83 2515 device 60H 7BH Indicates 83C251SB device 60H 4AH Indicates 83 2515 device 60H 4BH Indicates 833C251SQ device 60H FAH Indicates 87C251SA device 60H FBH Indicates 87C251SB device 60H CAH Indicates 87C251SP device 60H CBH Indicates 87C251SQ device 61H 55H Indicates 8XC251SA SB SP SQ B step products 14 7 VERIFYING THE 83 2515 SB SP SQ ROM Nonvolatile
43. signed A dir8 rel Compare dir byte to acc and jump 3 2 5 3 2 5 if not equal A data rel Compare immediate to acc and 3 2 5 3 2 5 jump if not equal CJNE Rn data rel Compare immediate to reg and 3 2 5 4 3 6 jump if not equal Ri data rel Compare immediate to indir and 3 3 6 4 4 7 jump if not equal Rn rel Decrement reg and jump if not 2 2 5 3 3 6 zero DJNZ 7 dir8 rel Decrement dir byte and jump if not 3 3 6 3 3 6 zero TRAP Jump to the trap interrupt vector 2 10 1 9 NOP No operation 1 1 1 1 NOTES 1 Ashaded cell denotes an instruction in the MCS 51 architecture 2 For conditional jumps times are given as not taken taken A 25 INSTRUCTION SET REFERENCE intel INSTRUCTION DESCRIPTIONS This section describes each instruction in the MCS 251 architecture See the note on page A 11 regarding execution times Table A 28 defines the symbols v 1 0 used to indicate the effect of the instruction on the flags in the PSW and PSW1 registers For a conditional jump instruction indicates that a flag influences the decision to jump Table A 28 Flag Symbols Symbol Description The instruction does not modify the flag The instruction sets or clears the flag as appropriate 1 The instruction sets the flag 0 The instruction clears the flag The instruction leaves the flag in an indeterminate state For a conditional jump instruction The state of
44. 0101 1100 ssss 5555 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rmd A Rms ANL WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0101 1101 tttt TTTT A 37 INSTRUCTION SET REFERENCE Hex Code in Operation ANL Rm data Binary Mode A5 Encoding Source Mode Encoding ANL WRjd WRjd A WRjs Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0101 1110 ssss 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm Rm data ANL WRi data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0101 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL WRj lt WRj A data16 ANL Rm dir8 Binary Mode Source Mode Bytes 4 3 States 3t 2t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0101 1110 5555 0001 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm Rm A dir8 A 38 intel INSTRUCTION SET REFERENCE ANL WRi dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0101 1110 tttt 0101 direct addr Hex Code in
45. 0datal6 1datal6 data datal6 short accumulator addr11 addr16 addr24 ALU assert A 32 bit constant that is immediately addressed in an instruction The upper word is filled with zeros A 32 bit constant that is immediately addressed in an instruction The upper word is filled with ones An 8 bit constant that is immediately addressed in an instruction A 16 bit constant that is immediately addressed in an instruction A constant equal to 1 2 or 4 that is immediately addressed in an instruction A register or storage location that forms the result of an arithmetic or logical operation An 11 bit destination address The destination can be anywhere in the same 2 Kbyte block of memory as the first byte of the next instruction A 16 bit destination address The destination can be anywhere within the same 64 Kbyte region as the first byte of the next instruction A 24 bit destination address The destination can be anywhere within the 16 Mbyte address space Arithmetic logic unit The part of the CPU that processes arithmetic and logical operations The term assert refers to the act of making a signal active enabled The polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert ALE is to drive it high Glossary 1 GLOSSARY binary code compatibility
46. 12 1 12 2 18 1 13 2 13 3 13 4 13 5 13 6 13 7 13 8 13 9 13 10 13 11 13 12 13 13 13 14 13 15 13 16 13 17 13 18 13 19 FIGURES Page Timer 2 Clock Out Mode 2 gs S a T2MOD Timer 2 Mode Control Register a Been Re ri 8 16 T2CON Timer 2 Control s Programmable Counter Array M ae PCA 16 bit Capture Mode 5 i tinte te reise titer ai O PCA Software Timer and High speed Output Modes 9 8 Watchdog Timer Mode essen enne 9 10 PCA 8 bit PWM 9 11 PWM Variable Duty 9 12 PCA Timer Counter Mode 9 13 CCON PCA Timer Counter Control Register eee 9 14 CCAPMx PCA Compare Capture Module Mode 9 16 Serial Port Block 10 2 SCON Serial Port Control SR Rice i ide uda qr teg Mode 0 Timing MEM TOFD Data Frame Modes 1 2 and 3 Bustier bee tene eene pneu 10 6 Timer 2 in Baud Rate Generator Mode ve dn mieu onte 10 13 Minimum Setups fave tel dene CHMOS On chip Oscillator Vende vient Pede 11 3 External Clock 11 4 External
47. 5 3 1 5 Displacement Several move instructions use displacement addressing to move bytes or words from a source to a destination Sixteen bit displacement addressing 9 WRj dis16 accesses indirectly the lowest 64 Kbytes in memory The base address can be in any word register WRj The instruction contains a 16 bit signed offset which is added to the base address Only the lowest 16 bits of the sum are used to compute the operand address If the sum of the base address and a positive offset exceeds FFFFH the computed address wraps around within region 00 e g F000H 2005H becomes 1005H Similarly if the sum of the base address and a negative offset is less than zero the com puted address wraps around the top of region 00 e g 2005H F000H becomes 1005H Twenty four bit displacement addressing DRk dis24 accesses indirectly the entire 16 Mbyte address space The base address must be in DRO DR4 DR24 DR28 DR56 or DR60 The upper byte in the dword register must be zero The instruction contains a 16 bit signed offset which is added to the base address 5 3 2 Arithmetic Instructions The set of arithmetic instructions is greatly expanded in the MCS 251 architecture The ADD and SUB instructions Table A 19 on page A 14 operate on byte and word data that is accessed in several ways as the contents of the accumulator a byte register Rn or a word register WRj inthe instruction itself immediate data in memory via
48. 7 Mode Register 0 A4166 01 Figure 9 5 PCA 8 bit PWM Mode 9 11 PROGRAMMABLE COUNTER ARRAY intel The value in CCAPxL determines the duty cycle of the current period The value in CCAPxH de termines the duty cycle of the following period Changing the value in CCAPxL over time mod ulates the pulse width As depicted in Figure 9 6 the 8 bit value in CCAPxL can vary from 0 10096 duty cycle to 255 0 496 duty cycle NOTE To change the value in CCAPxL without glitches write the new value to the high byte register CCAPxH This value is shifted by hardware into CCAPxL when CL rolls over from FFH to 00H The frequency of the PWM output equals the frequency of the PCA timer counter input signal divided by 256 The highest frequency occurs when the Fosc 4 input is selected for PCA tim er counter For Fosc 16 MHz this is 15 6 KHz To program a compare capture module for the PWM mode set the and bits in the module s CCAPM lt x register Table 9 3 on page 9 15 lists the bit combinations for selecting module modes Also select the desired input for the PCA timer counter by programming the CPSO and 51 bits in register see Figure 9 7 on page 9 13 Enter an 8 bit value in CCAPXL to specify the duty cycle of the first period of the PWM output waveform Enter an 8 bit value in CCAPxH to specify the duty cycle of the second period Set the timer counter run con trol bi
49. Binary Mode Encoding Source Mode Encoding EJMP lt DRk Extended return Pops byte 2 byte 1 and byte 0 of the 3 byte PC successively from the stack and decrements the stack pointer by 3 Program execution continues at the resulting address which normally is the instruction immediately following ECALL No flags are affected The stack pointer contains OBH On chip RAM locations 08H 09H and OAH contain 01H 23H and 49H respectively After executing the instruction ERET the stack pointer contains 08H and program execution continues at location 012349H A 63 INSTRUCTION SET REFERENCE Binary Mode Source Mode Bytes 3 2 States 10 9 Encoding 1010 1010 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ERET PC 15 8 SP SP lt SP 1 PC 7 0 SP SP SP 1 PC 23 16 SP SP lt SP 1 INC lt Byte gt Function Increment Description Increments the specified byte variable by 1 An original value of FFH overflows to OOH Three addressing modes are allowed for 8 bit operands register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins Flags CY AC OV Example Register 0 contains 7EH 011111110B and on chip RAM locations 7EH and 7FH contain OFFH and 40
50. Encoding Hex Code in Operation XCH A Rn Bytes States Encoding Hex Code in Operation Variations XCHD A Ri Function Description Flags Example Binary Mode Source Mode 1 2 4 5 1100 011i Binary Mode Encoding Source Mode A5 Encoding XCH gt lt Ri Binary Mode Source Mode 1 2 3 4 1100 irrr Binary Mode Encoding Source Mode A5 Encoding XCH A gt lt Rn Exchange digit INSTRUCTION SET REFERENCE Exchanges the low nibble of the accumulator bits 3 0 generally representing a hexadecimal or BCD digit with that of the on chip RAM location indirectly addressed by the specified register Does not affect the high nibble bits 7 4 of either register OV RO contains the address 20H the accumulator contains 36H 00110110B and on chip RAM location 20H contains 75H 01110101B After executing the instruction XCHD A GRO on chip RAM location 20H contains 76H 01110110B and 35H 00110101B in the accumu lator A 137 INSTRUCTION SET REFERENCE Bytes States Encoding Hex Code in Operation Binary Mode Source Mode 1 2 4 5 1101 011i Binary Mode Encoding Source Mode Encoding XCHD A 3 0 gt lt Ri 3 0 XRL lt dest gt lt src gt Function Description Flags Example A 138 Logical Exclusive OR for byte var
51. Figure 3 4 8 2515 SB SP SQ Memory Space intel ADDRESS SPACES Memory Address Space 16 Mbytes Region FF Detail Configuration Arrayt FF FFF8H FF FFFFH FF 0000H Sheet External Memory FE FFFFH External Memory FF 2000H FF 4000H FE 0000H On chip OTPROM ROM or Externalt Tm SB SQ 16 Kbytes FF 0000H FF 3FFFH SA SP 8 Kbytes FF 0000H FF 1FFFH FD 0000H FD FFFFH 1 Implementation of configuration bytes 87C25184A SB SP SQ on chip nonvolatile memory External Memory 83C251SA SB SP SQ on chip nonvolatile memory FC 0000H 80C251SB SQ external memory Regions 04 are Reserved 03 FFFFH External Memory 03 0000H Region 00 Detail 00 FFFFH 02 FFFFH External Memory 02 0000H External Memory 01 FFFFH 00 0220H 00 0420H On chip RAM SA SB 1 Kbyte 00 0020H 00 041 FH SP SQ 512 bytes 00 0020 00 021 External Memory 01 0000H 00 FFFFH 32 byte Register File 00 0000H 00 001FH A4226 02 Figure 3 5 Hardware Implementation of the 8XC251SA SB SP SQ Memory Space Locations FF FFF8H FF FFFFH are reserved for the configuration array see Chapter 4 Device Configuration The two configuration bytes for the 8XC251Sx are accessed at locations FF FFF8H and FF FFF9H locations FF FFFAH FF FFFFH are reserved for configuration bytes in future products Do not attempt to execute code from locations FF FFF8H
52. JE JNE Signed JSG JSL JSGE JSLE 5 14 intel PROGRAMMING 5 5 3 Unconditional Jumps There are five unconditional jumps NOP and SJMP jump to addresses relative to the program counter AJMP LJMP and EJMP jump to direct or indirect addresses NOP No Operation is an unconditional jump to the next instruction SJMP Short Jump jumps to any instruction within 128 to 127 of the next instruction AJMP Absolute Jump changes the lowest 11 bits of the PC to jump anywhere within the current 2 Kbyte block of memory The address can be direct or indirect LJMP Long Jump changes the lowest 16 bits of the PC to jump anywhere within the current 64 Kbyte region EJMP Extended Jump changes all 24 bits of the PC to jump anywhere in the 16 Mbyte address space The address can be direct or indirect 5 5 4 Calls and Returns The MCS 251 architecture provides relative direct and indirect calls and returns ACALL Absolute Call pushes the lower 16 bits of the next instruction address onto the stack and then changes the lower 11 bits of the PC to the 11 bit address specified by the instruction The call is to an address that is in the same 2 Kbyte block of memory as the address of the next instruction LCALL Long Call pushes the lower 16 bits of the next instruction address onto the stack and then changes the lower 16 bits of the PC to the 16 bit address specified by the instruction The call is to an address in the same 64 Kby
53. Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States Rmd Rms Reg with reg 3 2 2 1 WRjd WRjs Word reg with word reg 3 3 2 2 DRkd DRks Dword reg with dword reg 3 5 2 4 Rm data Reg with immediate data 4 3 3 2 WR j data16 Word reg with immediate 16 bit data 5 4 4 3 DRk 0data16 Dword reg with zero extended 16 bit 5 6 4 5 immediate data CMP DRk 1data16 Dword reg with one extended 16 bit 5 6 4 5 immediate data Rm dir8 Dir addr from byte reg 4 3 2t WRj dir8 Dir addr from word reg 4 4 3 3 Rm dir16 Dir addr 64K from byte reg 5 3 4 2 WRi dir16 Dir addr 64K from word reg 5 4 4 3 Rm WRj Indir addr 64K from byte reg 4 3 3 2 Rm DRk Indir addr 16M from byte reg 4 4 3 3 If this instruction addresses an I O port Px x 3 0 add 1 to the number of states INSTRUCTION SET REFERENCE intel Table A 21 Summary of Increment and Decrement Instructions Increment INC DPTR DPTR DPTR 1 Increment INC byte byte byte 1 Increment INC lt dest gt lt src gt dest opnd dest opnd src opnd Decrement DEC byte byte byte 1 Decrement DEC lt dest gt lt src gt dest opnd lt dest opnd src opnd Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States A acc 1 1 1 1 Rn Reg 1 1 2 2 dir8 Dir byte 2 2 2 2 2 2 INC DEC Ri Indir RAM 1 3 2 4 Rm short Byte reg by 1 2 or 4 3 2 2 1
54. Move Code instruction moves a byte from code memory region FF to the accu mulator MOVS Move with Sign Extension and MOVZ Move with Zero Extension move the contents of an 8 bit register to the lower byte of a 16 bit register The upper byte is filled with the sign bit MOVS or zeros MOVZ The MOVH Move to High Word instruction places 16 bit immedi ate data into the high word of a dword register The XCH Exchange instruction interchanges the contents of the accumulator with a register or memory location The XCHD Exchange Digit instruction interchanges the lower nibble of the accumulator with the lower nibble of a byte in on chip RAM XCHD is useful for BCD binary coded decimal operations The PUSH and POP instructions facilitate storing information PUSH and then retrieving it POP in reverse order Push can push a byte a word or a dword onto the stack using the imme diate direct or register addressing modes POP can pop a byte or a word from the stack to a reg ister or to memory intel PROGRAMMING 5 4 BITINSTRUCTIONS A bit instruction addresses a specific bit in a memory location or SFR There are four categories of bit instructions SETB Set Bit CLR Clear Bit CPL Complement Bit These instructions can set clear or complement any addressable bit ANL And Logical ANL And Logical Complement ORL OR Logical ORL Or Logical Complement These instructions allow ANDing and ORing of any ad
55. Operation INSTRUCTION SET REFERENCE MOV WRj lt DRk dis MOV WRj dis16 Rm Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 0001 1001 tttt ssss dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj dis lt Rm MOV QWhj dis16 WRj Binary Mode Source Mode Bytes 5 4 States 7 6 Encoding 0101 1001 tttt TTTT dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj dis lt WRj MOV DRk dis24 Rm Binary Mode Source Mode Bytes 5 4 States 7 6 Encoding 001 1 1001 uuuu 5555 dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk dis lt Rm A 97 INSTRUCTION SET REFERENCE MOV DRk dis24 WRj Binary Mode Source Mode Bytes 5 4 States 8 7 Encoding 0111 1001 uuuu tttt dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRK dis WRj MOV lt dest bit gt lt src bit gt Function Description Flags Example Variations MOV bit51 CY Bytes States Encoding Hex Code in Operation A 98 Move bit data Copies the Boolean variable specified by the second operand into the location specified
56. PC 15 8 SP SP lt SP 1 PC 7 0 lt SP SP lt SP 1 Return from interrupt This instruction pops two or four bytes from the stack depending on the INTR bit in the CONFIG1 register If INTR 0 RETI pops the high and low bytes of the PC successively from the stack and uses them as the 16 bit return address in region FF The stack pointer is decremented by two No other registers are affected and neither PSW nor PSW1 is automatically restored to its pre interrupt status If INTR 1 RETI pops four bytes from the stack PSW1 and the three bytes of the PC The three bytes of the PC are the return address which can be anywhere in the 16 Mbyte memory space The stack pointer is decremented by four PSW1 is restored to its pre interrupt status but PSW is not restored to its pre interrupt status No other registers are affected For either value of INTR hardware restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed Program execution continues at the return address which normally is the instruction immediately after the point at which the interrupt request was detected If an interrupt of the same or lower priority is pending when the RETI instruction is executed that one instruction is executed before the pending interrupt is processed CY AC OV N 2 INTR 0 The stack pointer contains OBH An interrupt was detected during
57. PROG CEX4 0 Programmable Counter Array Input Output Pins These are input signals for the PCA capture mode and output signals for the PCA compare mode and PCA PWM mode P1 6 3 P1 7 A17 EA External Access Directs program memory accesses to on chip or off chip code memory For EA 0 all program memory accesses are off chip For 1 an access is to on chip ROM OTPROM EPROM if the address is within the range of the on chip ROM OTPROM EPROM otherwise the access is off chip The value of EA is latched at reset For devices without on chip ROM OTPROM EPROM must be strapped to ground Vpp The descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the nonpage mode chip configuration compatible with 44 lead PLCC and 40 lead DIP MCS 51 microcontrollers If the chip is configured for page mode operation port 0 carries the lower address bits A7 0 and port 2 carries the upper address bits A15 8 and the data D7 0 intel SIGNAL DESCRIPTIONS Table B 3 Signal Descriptions Continued ignal Multipl Mane Type Description Dn ECI External Clock Input External clock input to the 16 bit PCA P1 2 timer INT 1 0 External Interrupts 0 and 1 These inputs set bits IE1 0 in the TCON P3 3 2 register If bits IT1 0 in the TCON register are set bits IE1 0 are set by a falling edge on INT1 INTO If bits INT1
58. This configuration leaves P3 7 RD A16 available for general I O RD1 0 10 A maximum of 64 Kbytes of ex ternal memory can be used and all regions of internal memory map into the single 64 Kbyte re gion in external memory see Figure 4 8 on page 4 14 User code is stored in on chip ROM OTPROM EPROM RAM 64 Kbytes 83C251SB 87C251SB OE WE A4221 01 Figure 13 18 Bus Diagram for Example 4 87C251SB 83C251SB in Nonpage Mode 13 19 EXTERNAL MEMORY INTERFACE FF FE FD FC 03 02 01 00 00 0000H Memory Address Space 512 Kbytes FFFFH 0000H 3FFFH FFFFH 0420H 16 Kbytes On chip ROM OTPROM EPROM External RAM 64 Kbytes 1056 Bytes 1056 Bytes On chip RAM 4224 01 13 20 Figure 13 19 Memory Space for Example 4 intel EXTERNAL MEMORY INTERFACE 13 6 5 Example 5 RD1 0 11 16 bit Bus External EPROM and RAM In this example an 80C251SB operates in nonpage mode with a 16 bit external address bus in terfaced to 64 Kbytes of EPROM and 64 Kbytes of RAM Figure 13 20 The 80C251SB A stepping or B stepping is configured so that RD is asserted for addresses lt 7F FFFFH and PSEN is asserted for addresses gt 80 0000H Figure 13 21 shows two ways to address the exter nal memory in the internal memory space Addressing external RAM locations in either region 00 or region 01 produces the same address at t
59. This setup can be used to make pulse width measurements See Pulse Width Measurements on page 8 10 Timer overflow count rolls over from all 1s to all Os sets the TF1 flag generating an interrupt request Interrupt Overflow Request Interrupt Request Overflow A4112 02 Figure 8 4 Timer 0 in Mode 3 Two 8 bit Timers 8 6 intel TIMER COUNTERS AND WATCHDOG TIM ER TMOD Address S 89H Reset State 0000 0000B 7 0 GATE1 C T1 M11 M01 GATEO C TO M10 Bit Number Mnemonic Function 7 GATE1 Timer 1 Gate When GATE1 0 run control bit TR1 gates the input signal to the timer register When GATE1 1 and TR1 1 external signal INT1 gates the timer input 6 C T1 Timer 1 Counter Timer Select C T1 0 selects timer operation timer 1 counts the divided down system clock C T1 1 selects counter operation timer 1 counts negative transitions on external pin T1 5 4 M11 MO1 Timer 1 Mode Select M11 M01 0 0 Mode 0 8 bit timer counter TH1 with 5 bit prescalar TL1 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TL1 Reloaded from TH1 at overflow 1 1 Mode 3 Timer 1 halted Retains count 3 GATEO Timer 0 Gate When GATEO 0 run control bit TRO gates the input signal to the timer register When GATEO 1 and TRO 1 external signal INTO gates the timer input 2 Timer 0 Counter T
60. You can insert three additional states if no interrupts are enabled with the following instruction sequence CLR P2 7 NOP NOP NOP SETB P2 7 Binary Mode Source Mode Bytes 1 1 States 1 1 Encoding 0000 0000 Hex Code in Binary Mode Encoding Source Mode Encoding Operation NOP PC PC 1 ORL lt dest gt lt src gt Function Logical OR for byte variables Description Performs the bitwise logical OR operation V between the specified variables storing the results in the destination operand The destination operand can be a register an accumulator or direct address The two operands allow twelve addressing mode combinations When the destination is the accumulator the source can be register direct register indirect or immediate addressing when the destination is a direct address the source can be the accumulator or immediate data When the destination is register the source can be register immediate direct and indirect addressing Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins A 108 INSTRUCTION SET REFERENCE Flags CY AC OV N Z Example The accumulator contains 11000011B and RO contains 55H 01010101B After executing the instruction ORL A RO the accumulator contains OD7H 11010111B When the destination is a directly addressed byt
61. accumulator register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins CY AC OV N 2 Register 0 contains 7FH 01111111 On chip RAM locations 7EH and 7FH contain 00H and 40H respectively After executing the instruction sequence DEC QRO DEC RO DEC RO register 0 contains 7EH and on chip RAM locations 7EH and 7FH are set to OFFH and 3FH respectively intel Variations DEC A Bytes States Encoding Hex Code in Operation DEC dir8 Bytes States Encoding Hex Code in Operation DEC Ghi Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Source Mode 1 1 1 1 0001 0100 Binary Mode Encoding Source Mode Encoding DEC lt A 1 Binary Mode Source Mode 2 2 2t 2t tlf this instruction addresses a port Px x 0 3 add 2 states 0001 0101 dir addr Binary Mode Encoding Source Mode Encoding DEC dir8 lt dirB 1 Binary Mode Source Mode 1 2 3 4 0001 0111 Binary Mode Encoding Source Mode A5 Encoding DEC Ri lt Ri 1 A 55 INSTRUCTION SET REFERENCE DEC Rn Bytes States Encoding Hex Code in Operation Binary Mode Source
62. and CY 1 Binary Mode Source Mode 3 2 2 1 0001 1110 ssss 0000 Binary Mode A5 Encoding Source Mode Encoding SRL Rm 7 0 lt Rm a 1 CY lt Rm 0 Binary Mode Source Mode 3 2 2 1 0001 1110 tttt 0100 Binary Mode A5 Encoding Source Mode Encoding intel Operation INSTRUCTION SET REFERENCE SRL WRj 15 0 WRj b lt WRj b 1 CY lt WRj 0 SUB lt dest gt lt src gt Function Description Flags Example Variations SUB Rmd Rms Bytes States Encoding Hex Code in Operation Subtract Subtracts the specified variable from the destination operand leaving the result in the destination operand SUB sets the CY borrow flag if a borrow is needed for bit 7 Otherwise CY is clear When subtracting signed integers the OV flag indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number Bit 7 in this description refers to the most significant byte of the operand 8 16 or 32 bit The source operand allows four addressing modes immediate indirect register and direct CY OV TFor dword subtractions AC is not affected Register 1 contains OC9H 11001001B and register 0 contains 54H 01010100B After executing the instruction
63. asynchronous mode The data frame Figure 10 4 consists of 10 bits one start bit eight data bits and one stop bit Serial data is transmitted on the TXD pin and received on the RXD pin When a message is received the stop bit is read in the RB8 bit in the SCON register The baud rate is generated by overflow of timer 1 or timer 2 see Baud Rates on page 10 10 Modes 2 and 3 Modes 2 and 3 are full duplex asynchronous modes The data frame Figure 10 4 consists of 11 bits one start bit eight data bits transmitted and received LSB first one programmable ninth data bit and one stop bit Serial data is transmitted on the TXD pin and received on the RXD pin On receive the ninth bit is read from the RB8 bit in the SCON register On transmit the ninth data bit is written to the TB8 bit in the SCON register Alternatively you can use the ninth bit as a command data flag mode 2 the baud rate is programmable to 1 32 or 1 64 of the oscillator frequency mode 3 the baud rate is generated by overflow of timer or timer 2 Data Byte b Start Bit Ninth Data Bit Modes 2 and 3 only Stop Bit A2261 01 Figure 10 4 Data Frame Modes 1 2 and 3 10 2 2 1 Transmission Modes 1 2 3 Follow these steps to initiate a transmission 1 Write to the SCON register Select the mode with the SMO and SM1 bits and clear the REN bit For modes 2 and 3 also write the ninth bit to the TB8 bit 2
64. compare capture module programmed for the capture mode detects the specified transition it captures the PCA timer counter value This records the time at which an external event is detect ed with a resolution equal to the timer counter clock period 9 5 PROGRAMMABLE COUNTER ARRAY intel To program a compare capture module for the 16 bit capture mode program the CAPPx and CAPN x bits in the module s CCAPM lt x register as follows To trigger the capture on a positive transition set CAPPx and clear CAPNx To trigger the capture on a negative transition set CAPNx and clear CAPPx To trigger the capture on a positive or negative transition set both CAPPx and CAPNx Table 9 3 on page 9 15 lists the bit combinations for selecting module modes For modules in the capture mode detection of a valid signal transition at the I O pin CEXx causes hardware to load the current PCA timer counter value into the compare capture registers CCAPxH CCAPxL and to set the module s compare capture flag CCFx in the CCON register If the corresponding in terrupt enable bit ECCEx in the CCAPMXx register is set Figure 9 9 on page 9 16 PCA sends an interrupt request to the interrupt handler Since hardware does not clear the event flag when the interrupt is processed the user must clear the flag in software A subsequent capture by the same module overwrites the existing captured value To preserve a captured value save it in RAM with th
65. connecting a capacitor between this pin and Vcc Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation RXD lO Receive Serial Data RXD sends and receives data in serial I O mode P3 0 0 and receives data in serial I O modes 1 2 and 3 T1 0 Timer 1 0 External Clock Inputs When timer 1 0 operates as a P3 5 4 counter a falling edge on the T1 0 pin increments the count T2 lO Timer 2 Clock Input Output For the timer 2 capture mode this signal P1 0 is the external clock input For the clock out mode it is the timer 2 clock output t The descriptions of A15 8 P2 7 0 and AD7 0 PO0 7 0 are for the nonpage mode chip configuration compatible with 44 lead PLCC and 40 lead DIP MCS 51 microcontrollers If the chip is configured for page mode operation port 0 carries the lower address bits A7 0 and port 2 carries the upper address bits A15 8 and the data D7 0 SIGNAL DESCRIPTIONS Table B 3 Signal Descriptions Continued intel Signal Name Type Description Multiplexed With T2EX Timer 2 External Input In timer 2 capture mode a falling edge ini tiates a capture of the timer 2 registers In auto reload mode a falling edge causes the timer 2 registers to be reloaded In the up down counter mode this signal determines the count direction 1 up 0 own P1 1 TXD Transmit Serial Data TXD outputs the shift clock in serial I O mode 0 an
66. l ntel INTERRUPT SYSTEM 6 3 PROGRAMMABLE COUNTER ARRAY PCA INTERRUPT The programmable counter array PCA interrupt is generated by logical OR of five event flags and the PCA timer overflow flag CF in the CCON register see Figure 9 8 on page 9 14 All PCA interrupts share a common interrupt vector Bits are not cleared by hardware vec tors to service routines Normally interrupt service routines resolve interrupt requests and clear flag bits This allows the user to define the relative priorities of the five PCA interrupts The PCA interrupt is enabled by bit EC in the register see Figure 6 1 on page 6 2 In addi tion the CF flag and each of the flags must also be individually enabled by bits ECF and ECCFx in registers and CCAPM lt x respectively for the flag to generate an interrupt see Figure 9 8 on page 9 14 and Figure 9 9 on page 9 16 NOTE CCFx refers to 5 separate bits one for each PCA module CCFO CCF1 CCF2 CCF3 CCF4 refers to 5 separate registers one for each PCA module CCAPMO CCAPMI CCAPM2 CCAPM3 CCAPMA 6 4 SERIAL PORT INTERRUPT Serial port interrupts are generated by the logical OR of bits RI and TI in the SCON register see Figure 10 2 on page 10 3 Neither flag is cleared by a hardware vector to the service routine The service routine resolves RI or TI interrupt generation and clears the serial port request flag The serial port interrupt is ena
67. microcontroller runs on the 8XC251Sx without recompiling If a system was originally developed using an MCS 51 microcontroller and if the new 8XC251Sx based system will run code written for the MCS 51 microcontroller performance will be better with the 8XC251Sx running in binary mode Object code written for the MCS 51 mi crocontroller runs faster on the 8 2515 However if most of the code is rewritten using the new instruction set performance will be better with the 8XC251 Sx running in source mode In this case the 8 2515 can run significantly fast er than the MCS 51 microcontroller See Chapter 4 Device Configuration for a discussion of binary mode and source mode MCS 251 microcontrollers store both code and data in a single linear 16 Mbyte memory space 8 2515 can address up to 256 Kbytes of external memory The special function registers SFRs and the register file have separate address spaces See Chapter 3 Address Spaces for description of the address spaces 22 MCS 251 MICROCONTROLLER CORE The MCS 251 microcontroller core contains the CPU the clock and reset unit the interrupt han dler the bus interface and the peripheral interface The CPU contains the instruction sequencer ALU register file and data memory interface 2 4 intel ARCHITECTURAL OVERVIEW 2 2 1 CPU Figure 2 2 is a functional block diagram of the CPU central processor unit The 8XC251Sx fetches instructions
68. slave intel ARCHITECTURAL OVERVIEW 2 4 SUMMARY OF A STEPPING DIFFERENCES This manual covers both the B stepping and A stepping versions of the 8XC251Sx Where the versions differ separate descriptions are provided or the differences in the A stepping version are noted The B stepping is available as the 8 2515 SB SP SQ the A stepping is available as the 8XC251SB This section summarizes the differences between the A stepping and B stepping versions 2 4 4 Package Options The 8XC251Sx B stepping is available in 44 lead PLCC and 40 lead DIP packages The 8XC251SB A stepping is available in the 44 lead PLCC package See latest data sheet for de tails of package options 2 4 2 Memory Address Space The usable memory space of the 8XC251Sx consists of eight 64 Kbyte regions for the B stepping and four 64 Kbyte regions for the A stepping See 8 2515 SB SP SQ Memory Space on page 3 5 and Memory Space for the A stepping of the 8XC251SB on page 3 10 For an expla nation of how internal memory space maps into external memory space for the B stepping and A stepping see Configuration Bits RD1 0 on page 4 11 2 4 2 1 On chip Memory The B stepping provides on chip memory options of 0 8 and 16 Kbytes of ROM OTPROM or EPROM and 512 or 1024 bytes of RAM The A stepping provides on chip memory options of 0 or 16 Kbytes of ROM or OTPROM and 1024 bytes of RAM See Table 2 1 on page 2 3 2 4 2 2 External Memory
69. the 3 bytes of the PC and PSWh1 If this bit is clear interrupts push the 2 lower bytes of the PC onto the stack See Interrupt Stack Mode INTR on page 4 20 3 WSB External Wait State B Region 01 3 For A stepping compatible applications only Clear this bit to generate one external wait state for memory region 01 Set this bit for no wait states for region 01 2 1 WSB1 0 External Wait State B Region 01 4 WSB1 WSBO 0 0 Inserts 3 wait states for region 01 0 1 Inserts 2 wait states for region 01 1 0 Inserts 1 wait state for region 01 1 1 Zero wait states for region 01 0 EMAP EPROM Map For devices with 16 Kbytes of on chip code memory clear this bit to map the upper half of on chip code memory to region 00 data memory Maps FF 2000H FF SFFFH to 00 E000H 00 FFFFH If this bit is set mapping does not occur and addresses in the range 00 000 00 access external RAM See Mapping On chip Code Memory to Data Memory EMAP on page 4 20 NOTES 1 User configuration bytes UCONFIGO and UCONFIG1 define the configuration of the B stepping ver 2 0100 sion of the 8 2515 Address UCONFIG1 is the 2nd lowest byte of a configuration array When EA 1 the 8 2515 obtains configuration information from configuration bytes implemented on chip ROM OTPROM EPROM at the top of memory region FF is at address FF FFF9H When 0 the 8XC251Sx obtains configuration i
70. 0 3 add 1 state Encoding 1010 1001 1111 0 dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL CY lt CY bit CJNE lt dest gt lt src gt rel Function Description Flags Example A 42 Compare and jump if not equal Compares the magnitudes of the first two operands and branches if their values are not equal The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC after incrementing the PC to the start of the next instruction If the unsigned integer value of lt dest byte gt is less than the unsigned integer value of lt src byte the CY flag is set Neither operand is affected The first two operands allow four addressing mode combinations the accumulator may be compared with any directly addressed byte or immediate data and any indirect RAM location or working register can be compared with an immediate constant V The accumulator contains and R7 contains 56H After executing the first instruction in the sequence CJNE R7 460H NOT EQ T Tus R7 60H NOT EQ JC REQ LOW IF R7 60H R7 gt 60H the CY flag is set and program execution continues at label NOT EQ By testing the CY flag this instruction determines whether R7 is greater or less than 60H If the data being presented to Port 1 is also 34H then executing th
71. 0 are clear bits IE1 0 are set by a low level on INT1 0 P0 7 0 Port 0 This is an 8 bit open drain bidirectional I O port AD7 0 P1 0 Port 1 This is an 8 bit bidirectional I O port with internal pullups T2 P1 1 T2EX P1 2 ECI P1 7 3 CEX3 0 CEX4 A17 P2 7 0 Port 2 This is an 8 bit bidirectional I O port with internal pullups A15 8 P3 0 Port 3 This is an 8 bit bidirectional I O port with internal pullups RXD P3 1 TXD P3 3 2 INT 1 0 P3 5 4 T1 0 P3 6 WR P3 7 RD A16 PROG Programming Pulse The programming pulse is applied to this pin for ALE programming the on chip nonvolatile memory PSEN Program Store Enable Read signal output Asserted for the memory address range specified by configuration bits RD1 0 B stepping UCONFIGO 3 2 Table B 4 A stepping CONFIGO 3 2 Table B 4 Also see RD RD Read or 17th Address Bit A16 Read signal output to external data P3 7 A16 memory or 17th external address bit A16 depending on configuration bits RD1 0 B stepping UCONFIGO 3 2 Table B 4 A stepping CONFIGO 3 2 Table B 4 Also see PSEN RST Reset Reset input to the chip Holding this pin high for 64 oscillator periods while the oscillator is running resets the device The port pins are driven to their reset conditions when a voltage greater than Viu is applied whether or not the oscillator is running This pin has an internal pulldown resistor which allows the device to be reset by
72. 1 9 2 POGACHMER CQUNTER ntt ere ees ese rette 9 2 9 3 PCA COMPARE CAPTURE MODULES seen 9 5 9 3 1 16 01 Capture Mode ee RR eR iie cd 9 5 9 3 2 Gompare MOQGS BEER ng nO e eie beet 9 7 vi intel ONENE 9 3 3 16 bit Software Timer nnne 9 7 9 3 4 High speed Output 22220 44424044 00 nennen nennen ener nnne nennen reis 9 8 9 3 5 PCA Watchdog Timer Mode essere nennen nennen nnns 9 9 9 3 6 Pulse Width Modulation Mode 222 22420 9 11 CHAPTER 10 SERIAL I O PORT 10 1 OVERVIEW rie en nter rer Sem PU d c Ads 10 1 10 2 MODES OF OPERATION reta eco epe e 10 4 10 2 1 Synchronous Mode Mode 0 200 10 4 10 2 1 1 Transmission Mode 0 10 4 10 2 1 2 Reception Mode 0 coenae e 10 5 10 2 2 Asynchronous Modes Modes 1 2 10 6 10 2 2 1 Transmission Modes 1 2 3 10 6 10 2 2 2 Reception Modes 1 2 3 10 6 10 3 FRAMING BIT ERROR DETECTION MODES 1 2 AND 3 10 7 10 4 MULTIPROCESSOR COMMUNICATION MODES 2 AND 3 10 7 10 5 AUTOMATIC ADDRESS RECOGNITION sess
73. 1 State 2 State 3 State 4 State 5 State 6 State 7 State 8 xac p vr MA ALE PSEN Po 7 0 F8H A7 0 F8H 7 0 F8H po 15 8 070 Jj 15 8 P2 A15 8 Mode 4228 01 Figure 13 11 Configuration Byte Bus Cycles 13 5 PORT 0 AND PORT 2 STATUS This section summarizes the status of the port 0 and port 2 pins when these ports are used as the external bus A more comprehensive description of the ports and their use is given in Chapter 7 Input Output Ports When port 0 and port 2 are used as the external memory bus the signals on the port pins can orig inate from three sources the 8XC251Sx CPU address bits data bits the port SFRs PO and P2 logic levels anexternal device data bits The port 0 pins but not the port 2 pins can also be held in a high impedance state Table 13 3 lists the status of the port 0 and port 2 pins when the chip in is the normal operating mode and the external bus is idle or executing a bus cycle 13 11 EXTERNAL MEMORY INTERFACE intel Table 13 3 Port 0 and Port 2 Pin Status In Normal Operating Mode 8 bi 16 bit Nonpage Mode Page Mode Bus Cycle Bus Idle Bus Cycle Bus Idle Port 0 8or 16 AD7 0 1 High Impedance A7 0 1 High Impedance Bana 8 P2 2 P2 P2 D7 0 2 High Impedance 16 A15 8 P2 A15 8 D7 0 High
74. 11 Minimum Hardware Setup The basic unit of time in MCS 251 microcontrollers is the state time or state which is two oscillator periods see Figure 2 3 The state time is divided into phase 1 and phase 2 The 8XC251Sx peripherals operate on a peripheral cycle which is six state times This periph eral cycle is particular to the 8 2515 and not a characteristic of MCS 251 architecture one clock interval in a peripheral cycle is denoted by its state and phase For example the PCA timer is incremented once each peripheral cycle in phase 2 of state 5 denoted as S5P2 The reset unit places the 8XC251Sx into a known state A chip reset is initiated by asserting the RST pin or allowing the watchdog timer to time out see Chapter 11 Minimum Hardware Set up Phase 1 Phase 2 P1 P2 XTAL1 KHEN Tosc 2 Tosc State Time State 1 State 2 State 3 State 4 State 5 State 6 P1 P2 P1 1 P2 P2 P2 P1 P2 P1 P2 Peripheral Cycle Figure 2 3 Clocking Definitions A2604 02 2 6 intel ARCHITECTURAL OVERVIEW 2 2 8 Interrupt Handler The interrupt handler can receive interrupt requests from eleven sources seven maskable sources and the TRAP instruction When the interrupt handler grants an interrupt request the CPU dis continues the normal flow of instructions and branches to a routine that services the source that requested the interru
75. 16 bit capture mode with triggering on the positive edge negative edge or either edge Compare modes 16 bit software timer 16 bit high speed output 16 bit WDT module 4 only or 8 bit pulse width modulation No operation Bit combinations programmed into a compare capture module s mode register deter mine the operating mode Figure 9 9 on page 9 16 provides bit definitions and Table 9 3 on page 9 15 lists the bit combinations of the available modes Other bit combinations are invalid and pro duce undefined results The compare capture modules perform their programmed functions when their common time base the PCA timer counter runs The timer counter is turned on and off with the CR bit in the CCON register To disable any given module program it for the no operation mode The occur rence of a capture software timer or high speed output event in a compare capture module sets the module s compare capture flag in the CCON register and generates a PCA interrupt request if the corresponding enable bit in the CCAPMXx register is set The CPU can read or write the CCAPxH and CCAPxL registers at any time 9 3 1 16 bit Capture Mode The capture mode Figure 9 2 provides the PCA with the ability to measure periods pulse widths duty cycles and phase differences at up to five separate inputs External I O pins CEXO through CEX4 are sampled for signal transitions positive and or negative as specified When a
76. 2 MOV ADD ADD ADD ADD rel Rm DRk dis Rm Rm WRj WRj reg op2 2 DRk DRk JG MOV SLL rel DRk dis Rm reg 4 JSL MOV ORL ORL ORL rel WRj WRij dis Rm Rm WRj WRj reg op2 2 5 JSGE MOV ANL ANL ANL rel WRi dis WRj Rm Rm WRj WRj reg op2 2 6 JE MOV XRL XRL XRL rel WRj DRk dis Rm Rm WRj WRj reg op2 2 7 JNE MOV MOV MOV MOV MOV MOV rel DRk dis WRj opt reg 2 Rm Rm WRj WRj reg op2 2 DRk DRk 8 LJMP WRj EJMP DIV DIV EJMP DRk addr24 Rm Rm WRj WR 9 LCALLOWRj ECALL SUB SUB SUB SUB ECALL QDRKk addr24 Rm Rm WRj WR reg op2 2 DRk DRk A Bit ERET MUL MUL Instructions 3 Rm Rm WRj WR B TRAP CMP CMP CMP CMP Rm Rm WRj WR reg op2 2 DRk DRk PUSH 1 4 MOV DRk PC D POP 4 E F NOTES 1 R Rm WRj DRk 2 op2 are defined Table 8 on page A 6 3 See Tables A 10 and A 11 on page A 7 4 See Table A 12 on page A 8 A 5 INSTRUCTION SET REFERENCE intel Table A 8 Data Instructions Instruction Byte 0 Byte 1 Byte 2 Byte 3 Oper Rmd Rms x C md ms Oper WRjd WRjs x D jd 2 js 2 Oper DRkd DRks F kd 4 ks 4 Oper Rm data XE m 0000 data Oper WRj data16 2 0100 data high data low Oper DRk data16 k 4 1000 data high data low MOV DRk h data16 7 A k4 1100 data high data low MOV DRk 1data16 7 E CMP DRk 1data16 Oper Rm dir8
77. 2 3 3 2 3 3 Rm Pop byte reg from stack 3 2 WRj Pop word reg from stack 3 2 4 DRk Pop double word reg from stack 3 2 NOTES 1 Ashaded ell denotes an instruction in the MCS 51 architecture 2 If this instruction addresses an I O port x 0 3 add 2 to the number of states A 22 intel INSTRUCTION SET REFERENCE Table A 26 Summary of Bit Instructions Clear Bit CLR bit bit lt 0 Set Bit SETB bit bit 1 Complement Bit CPL bit bit Obit AND Carry with Bit ANL CY bit CY CY A bit AND Carry with Complement of Bit ANL CY bit CY CYA Obit OR Carry with Bit ORL CY bit CY lt CY V bit ORL Carry with Complement of Bit ORL CY bit lt CY V Obit Move Bit to Carry MOV CY bit CY lt bit Move Bit from Carry MOV bit CY bit CY Binary Mode Source Mode Mnemonic lt src gt lt dest gt Notes Bytes States Bytes States CY Clear carry 1 1 1 1 CLR bit51 Clear dir bit 2 2 2 2 2 2 bit Clear dir bit 4 4 3 3 CY Set carry 1 1 1 1 SETB bit51 Set dir bit 2 2 2 2 2 2 bit Set dir bit 4 4 2 3 3 2 CY Complement carry 1 1 1 1 CPL bit51 Complement dir bit 2 2 2 2 2 2 bit Complement dir bit 4 4 2 3 3 2 ANE CY bit51 AND dir bit to carry 2 1 3 2 1 3 AND dir bit to carry 4 3 3 3 2 3 ANI CY bit51 AND complemented dir bit to carry 2 1 3 2 1 3 CY bit AND complemented dir bit to carry 4
78. 3 add 2 states 1101 0010 bit addr Binary Mode Encoding Source Mode Encoding SETB bitb1 lt 1 Binary Mode Source Mode 1 1 1 1 1101 0011 Binary Mode Encoding Source Mode Encoding SETB CY 1 intel INSTRUCTION SET REFERENCE SETB bit Binary Mode Source Mode Bytes 4 3 States 41 3t tlf this instruction addresses a port Px x 0 3 add 2 states Encoding 1010 1001 1101 0 yyy direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SETB bit lt 1 SJMP rel Function Short jump Description Program control branches unconditionally to the specified address The branch destination is computed by adding the signed displacement in the second instruction byte to the PC after incrementing the PC twice Therefore the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it Flags CY AC OV N 2 The label RELADR is assigned to an instruction at program memory location 0123H The instruction SJMP RELADR assembles into location 0100H After executing the instruction the PC contains 0123H Note In the above example the instruction following SJMP is located at 102H Therefore the displacement byte of the instruction is the relative offset 0123 0102 21H Put another way an SJMP with a d
79. 3 3 3 2 3 CY bit51 OR dir bit to carry 2 1 3 2 1 3 CY bit OR dir bit to carry 4 3 3 3 2 3 oni CY bit51 OR complemented dir bit to carry 2 1 3 2 1 3 CY bit OR complemented dir bit to carry 4 3 3 3 2 3 CY bit51 Move dir bit to carry 2 1 3 2 1 3 ay CY bit Move dir bit to carry 4 3 3 3 2 3 bit51 CY Move carry to dir bit 2 2 2 2 2 2 bit CY Move carry to dir bit 4 4 2 3 3 2 NOTES 1 shaded cell denotes an instruction in the MCS 51 architecture 2 If this instruction addresses an I O port x 0 3 add 2 to the number of states 3 If this instruction addresses an I O port x 0 3 add 1 to the number of states A 23 INSTRUCTION SET REFERENCE Table A 27 Summary of Control Instructions intel Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States 2 Bytes States 2 ACALL addr11 Absolute subroutine call 2 9 2 9 DRk Extended subroutine call indirect 3 12 2 11 ECALL addr24 Extended subroutine call 5 14 4 13 WRj Long subroutine call indirect 3 9 2 8 LCALL addr16 Long subroutine call 3 9 3 9 RET Return from subroutine 1 6 1 6 ERET Extended subroutine return 3 10 2 9 RETI Return from interrupt 1 6 1 6 AJMP addr11 Absolute jump 2 3 2 3 addr24 Extended jump 5 6 4 5 EJMP DRk Extended jump indirect 3 7 2 6 WRj Long jump
80. 5 7 4 PORTO AND PORT 2 Ports 0 and 2 are used for general purpose I O or as the external address data bus Port 0 shown in Figure 7 2 differs from the other ports in not having internal pullups Figure 7 3 on page 7 4 shows the structure of port 2 An external source can pull a port 2 pin low To use a pin for general purpose output set or clear the corresponding bit in the Px register x 0 2 To use a pin for general purpose input set the bit in the Px register to turn off the output driver FET 7 2 intel INPUT OUTPUT PORTS Alternate Read Output pog Latch Function Internal Bus Write to Latch Read Pin Alternate Input Function A2239 01 Figure 7 1 Port 1 and Port 3 Structure Address Read Data Control Vcc Latch Internal Bus Write to Latch Read Pin A2238 01 Figure 7 2 Port 0 Structure 7 3 INPUT OUTPUT PORTS intel Address Voc Control Read Internal Latch Pullup Internal Bus Write to Latch Read Pin 2240 01 Figure 7 3 Port 2 Structure When port 0 and port 2 are used for an external memory cycle an internal control signal switches the output driver input from the latch output to the internal address data line External Memory Access on page 7 7 discusses the operation of port 0 and port 2 as the external address data bus NOTE Port 0 and port 2 are precluded from use as general purpose
81. 5 Pulses 69H data FFF8H FFFFH 1 4 5 Configuration Bytes 12 75 V UCONFIGO UCONFIG1 87 2515 Verify Mode B stepping High Low 5V High 29H data FFF8H FFFFH 4 5 Configuration Bytes UCONFIGO UCONFIG1 8XC251Sx Program Mode A stepping High Low 5 5 Pulses 69H data 0080H 0083H 1 4 Configuration Bytes 12 75 V CONFIGO CONFIG1 87C251SB Verify Mode A stepping High Low 5V High 29H data 0080H 0083H 4 Configuration Bytes CONFIGO CONFIG1 8XC251SB Program Mode Lock Bits High Low 5V 25 Pulses 6BH data 0001H 0003H 1 2 87 2515 12 75 V Verify Mode Lock bits High Low 5V High 2BH data 0000H 3 87 2515 83 2515 Program Mode Encryption High Low 5V 25 Pulses 6CH data 0000H 007FH 1 Array 12 75 V 87 2515 NOTES 1 To program raise Vpp to 12 75 V and pulse the PROG pin See Figure 14 2 for waveforms 2 No data input Identify the lock bits with the address lines as follows LB3 0003H LB2 0002H LB1 0001H 3 three lock bits are verified in a single operation The states of the lock bits appear simultaneously at port 2 as follows LB3 P2 3 LB2 P2 2 LB1 P2 1 High programmed 4 For the case of B stepping devices used as A stepping compatible specify the configuration in UCONFIGO and UCOMFIG1 5 Forthese modes the internal address is FF xxxxH 14 4 intel PROGRAMMING AND VERIFYING NONVOLATILE MEMORY Table 14 1 Programming and Verifying Mo
82. 51 architecture use 80H FFH as addresses for both memory locations and SFRs because memory locations are addressed only indirectly and SFR locations are ad dressed only directly For compatibility software tools for MCS 251 controllers recognize this notation for instructions in the MCS 51 architecture No change is necessary in any code written for MCS 51 controllers For new instructions in the MCS 251 architecture the memory region prefixes 00 01 FF and the SFR prefix S are required Also software tools for the MCS 251 architecture permit 00 to be used for memory addresses and permit the prefix S to be used for SFR ad dresses in instructions in the MCS 51 architecture 5 3 PROGRAMMING intel 5 2 4 Addressing Modes The MCS 251 architecture supports the following addressing modes register addressing The instruction specifies the register that contains the operand immediate addressing The instruction contains the operand direct addressing The instruction contains the operand address indirect addressing The instruction specifies the register that contains the operand address displacement addressing The instruction specifies a register and an offset The operand address is the sum of the register contents the base address and the offset relative addressing The instruction contains the signed offset from the next instruction to the target address the address for transfer of cont
83. 5i ote oet ec ehe don 6 14 6752 5 Jnterr pt Vector Cycle 5mm tome e Died 6 14 6 9 JSBs itePrOCOeSS RE PUDE ME 6 15 CHAPTER 7 INPUT OUTPUT PORTS 7 1 INPU T OUTPUT PORT OVERVIEW ning pennae tentem 7 1 7 2 l O CONFIGURATIONS 5 2 e cet enne ie ecce Eee eee 7 2 7 3 ta cp ate uter entere da t cr ae 7 2 intel 7 4 PORT 0 AND PORT 2 i e eret dd ide 7 2 7 5 READ MODIFY WRITE 2 44 4 7 5 7 6 QUASI BIDIRECTIONAL PORT 0 0 7 5 7 7 residet te e dex Ra 7 7 7 8 EXTERNAL MEMORY 58 020022 41 2 2 20 ei 7 7 8 TIMER COUNTERS AND WATCHDOG 8 1 TIMER COUNTER 2 44 2 0 02 2 0 nennen neret 8 1 8 2 TIMER COUNTER 8 1 8 3 TIMER Oi ERE it 8 4 8 3 1 Mode 0 13 bit Timer e ede ee e UI decet 8 4 8 3 2 Mode T i16 bit Tlmet gna eletti e 8 5 8 3 8 Mode 2 8 bit Timer With Auto reload 8 5 8 34 Mode 3 Two 8 bit Timers nee tnnt AD e E 8 5 8 4 tet e ge YER Ui bete i ob e
84. A 26 PSW PSWI 3 17 3 18 5 16 5 17 C 22 C 23 conditional jumps 5 14 effects of instructions on flags 5 17 PSWI A 26 Pullups 7 7 ports 1 2 3 7 5 Pulse width measurements 8 10 Index 6 intel PUSH instruction 3 15 5 10 A 22 Q Quick pulse algorithm 14 1 R RCAP2H RCAP2L 3 17 3 19 8 2 10 12 C 24 RD 7 1 described 13 2 regions for asserting 4 11 RD1 0 configuration bits 4 11 Read modify write instructions 7 2 7 5 Register addressing 5 4 5 5 Register banks 3 2 3 12 accessing in memory address space 5 4 implementation 3 12 3 13 MCS 51 architecture 3 3 selection bits RS1 0 5 18 5 19 Register file 2 5 3 1 3 5 3 10 3 15 address space 3 2 addressing locations in 3 13 and reset 11 6 MCS 51 architecture 3 4 naming registers 3 13 register types 3 13 Registers See Register addressing Register banks Register file rel A 3 Relative addressing 5 4 5 13 Reset 11 5 11 8 cold start 11 6 12 1 entering ONCE mode 12 7 exiting idle mode 12 5 exiting powerdown mode 12 6 externally initiated 11 6 need for 11 7 operation 11 6 power on 11 7 power on setup 11 1 timing sequence 11 6 11 8 warm start 11 6 12 1 RET instruction 5 15 A 24 RETI instruction 6 1 6 14 6 15 A 24 Return instructions 5 15 RL instruction A 17 RLC instruction A 17 ROM on chip 14 1 intel verifying 14 1 14 11 See also On chip code memory Configuration bytes Lock bits Encryption ar
85. A stepping and B stepping configured as A stepping compatible Selects O or 1 wait states for memory region 01 e WSA1 0 B stepping only Selects 0 1 2 or 3 wait states for all memory regions except 01 WSB1 0 B stepping only Selects 0 1 2 or 3 wait states for memory region 01 EMAP Affects the external memory interface in that when asserted addresses in the range 00 E000H 00 FFFH access on chip memory 4 3 DEVICE CONFIGURATION intel 83 2515 SP 83C251SB SQ 87C2518A SPI 87C251SB SQ FF it FF FFFFH FF FFFEH FF FFFDH Reserved FF FFFCH FF FFFBH FF FFFAH Y FF FFF9H UCONFIG1 FF FFF8H UCONFIGO 8 Kbytes Mbytes For EA 1 the 8 2515 obtains configuration information from on chip nonvolatile memory at addresses FF FFF8H and FF FFF9H Detail On chip configuration array A4237 01 Figure 4 1 B stepping Configuration Array On chip Table 4 1 External Addresses for Configuration Array Size of External Address of Address of Address Bus Configuration Array on Configuration Bytes Bits External Bus 2 on External Bus 1 16 FFF8H FFFFH UCONFIG1 FFF9H UCONFIGO FFF8H 17 1FFF8H 1FFFFH UCONFIG1 1FFF9H UCONFIGO 1FFF8H 18 UCONFIG1 3FFF9H UCONFIGO 3FFF8H NOTES 1 When EA 0 the reset routine retrieves UCONFIGO and UCONFIG1 from external memory using the internal addresses FF FFF
86. ANL ANL ANL rel addr11 dir8 A dir8 data A data A dir8 A Ri A Rn 6 JZ AJMP XRL XRL XRL XRL XRL XRL rel addr11 dir8 A dir8 data A data A dir8 A Ri A Rn 7 JNZ ACALL ORL JMP MOV MOV MOV MOV rel 11 CY bit A DPTR A data dir8 data Ri data Rn data 8 SUMP AJMP ANL MOVC DIV MOV MOV MOV rel addr11 CY bit A A PC AB dir8 dir8 dir8 Ri dir8 Rn 9 MOV ACALL MOV MOVC SUBB SUBB SUBB SUBB DPTR data16 addr11 bit CY A A DPTR A data A dir8 A Ri A Rn A ORL AJMP MOV INC MUL ESC MOV MOV CY bit addr11 CY bit DPTR AB Ri dir8 Rn dir8 ANL ACALL CPL CPL CJNE CJNE CJNE CJNE CY bit addr11 bit CY A data rel A dir8 rel Ri data rel Rn data rel C PUSH AJMP CLR CLR SWAP XCH XCH XCH dir8 11 bit CY A A dir8 A Ri A Rn D POP ACALL SETB SETB DA DJNZ XCHD DJNZ dir8 addr11 bit CY A dir8 rel A Ri Rn rel E MOVX AJMP MOVX CLR MOV MOV MOV A DPTR addr11 A Ri A A dir8 A Ri A Rn F MOV ACALL MOVX CPL MOV MOV MOV DPTR A addr11 Ri A A dir8 A Ri A Rn A 4 INSTRUCTION SET REFERENCE Table 7 New Instructions for the MCS 251 Architecture Bin A5x8 5 9 5 5 5 A5xD A5xE A5xF Src x8 x9 xA xB xC xD xE xF 0 JSLE MOV MOVZ INC R short 1 SRA rel Rm WRij dis WRj Rm MOV reg 1 JSG MOV MOVS DEC R short 1 SRL rel WhRj dis Rm WRj Rm MOV ind reg reg
87. Architecture on page 3 2 A 20 intel INSTRUCTION SET REFERENCE Table A 24 Summary of Move Instructions Continued Move 2 Move with Sign Extension Move with Zero Extension Move Code Byte Move to External Mem Move from External Mem MOV lt dest gt lt src gt MOVS dest src MOVZ lt dest gt lt src gt MOVC lt dest gt lt src gt MOVX lt dest gt lt src gt MOVX dest src destination lt src destination lt src with sign extend destination src with zero extend A lt code byte external mem lt A lt source in external mem Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States WRi dis16 WRj Word reg to Indir addr with disp 64K 5 7 4 6 MOV DRk dis24 Rm_ Byte reg to Indir addr with disp 16M 5 7 4 6 DRk dis24 WRj_ Word reg to Indir addr with disp 5 8 4 7 16M MOVH DRk hi data16 16 bit immediate data into upper 5 3 4 2 word of dword reg MOVS WRj Rm Byte reg to word reg with sign 3 2 2 1 extension WRj Rm Byte reg to word reg with zeros 3 2 2 1 MONE extension MOVE A A DPTR Code byte relative to DPTR to acc 1 6 1 6 Code byte relative to PC to 1 6 1 6 A Ri External mem 8 bit addr to acc 4 1 4 2 5 A DPTR External mem 16 bit addr to acc 4 1 5 1 5 Ri A Acc to external mem 8 bit addr
88. Binary Mode 2 2T 2 2T Source Mode INSTRUCTION SET REFERENCE tlf this instruction addresses a port Px x 0 3 add 1 state 1111 0101 direct addr Binary Mode Encoding Source Mode Encoding MOV dir8 lt A Binary Mode 1 3 2 4 1111 011i Binary Mode Encoding Source Mode A5 Encoding MOV Ri lt Binary Mode 1 1 2 2 1111 111r Binary Mode Encoding Source Mode A5 Encoding MOV Rn lt A Binary Mode 3 2 2 1 Source Mode Source Mode Source Mode 0111 1100 5555 5555 87 INSTRUCTION SET REFERENCE Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rms MOV WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0111 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRjd WRjs MOV DRkd DRks Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0111 1111 uuuu UUUU Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRkd lt DRks MOV Rm Zdata Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0111 1110 ssss 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Oper
89. Binary Mode A5 Encoding Source Mode Encoding Operation ANL WRj lt WRj A dir8 ANL Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0101 1110 ssss 0011 direct direct Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm Rm A dir16 ANL WRi dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0101 1110 tttt 0111 direct direct Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL WRj WRj A dir16 ANL Rm GWRj Binary Mode Source Mode Bytes 4 3 States 3 2 A 39 INSTRUCTION SET REFERENCE Encoding 0101 1110 tttt 1001 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm lt Rm A WRj ANL Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0101 1110 uuuu 1011 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm lt Rm A DRk ANL CY lt src bit gt Function Description Flags Example A 40 Logical AND for bit variables If the Boolean value of the source bit is a logical 0 clear the CY flag otherwise leave the CY flag in its current state A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit
90. Bit Number Mnemonic Function 7 CF PCA Timer Counter Overflow Flag Set by hardware when the PCA timer counter rolls over This generates an interrupt request if the ECF interrupt enable bit in CMOD is set CF can be set by hardware or software but can be cleared only by software 6 CR PCA Timer Counter Run Control Bit Set and cleared by software to turn the PCA timer counter on and off 5 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 4 0 CCF4 0 PCA Module Compare Capture Flags Set by hardware when a match or capture occurs This generates a PCA interrupt request if the ECCFx interrupt enable bit in the corresponding CCAPMx register is set Must be cleared by software Figure 9 8 CCON PCA Timer Counter Control Register PROGRAMMABLE COUNTER ARRAY Table 9 3 PCA Module Modes ECOMx CAPPx CAPNx MATx TOGx PWMx ECCFx Module Mode 0 0 0 0 0 0 No operation X 1 0 0 0 X 16 bit capture on positive edge trigger at CEXx X 0 1 0 0 0 X 16 bit capture on negative edge trigger at CEXx X 1 1 0 0 0 X 16 bit capture on positive or negative edge trigger at CEXx 1 0 0 1 0 X Compare software timer 1 0 0 1 1 X Compare high speed output 1 0 0 0 0 1 0 Compare 8 bit PWM 1 0 0 1 X 0 X Compare PCA WDT CCAPMA only Note 3 NOTES 1 This table shows the CCAPMx register bit combinations for selecti compare capture modules
91. Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Source Mode 2 2 2t 2t tlf this instruction addresses a port Px x 0 3 add 2 states 0110 0010 direct addr Binary Mode Encoding Source Mode Encoding XRL dir8 lt dir8 v A Binary Mode Source Mode 3 3 3t 3t tlf this instruction addresses a port Px x 0 3 add 1 state 0110 0011 direct addr immed data Binary Mode Encoding Source Mode Encoding XRL dir8 lt dir8 v data Binary Mode Source Mode 2 2 1 1 0110 0100 immed data Binary Mode Encoding Source Mode Encoding XRL lt A v data A 139 INSTRUCTION SET REFERENCE XRL A dir8 Bytes States Encoding Hex Code in Operation XRL A Ri Bytes States Encoding Hex Code in Operation XRL A Rn Bytes States Encoding Hex Code in Operation XRL Rmd Rms Bytes States Encoding A 140 Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state 0110 0101 direct addr Binary Mode Encoding Source Mode Encoding XRL A lt A Y dir8 Binary Mode Source Mode 1 2 2 3 0110 011i Binary Mode Encoding Source Mode A5 Encoding XRL A lt A Ri Binar
92. Clock Drive eee emere 11 5 Reset Timing 11 8 Power Control PCON Register EUER D ROUTE Perte ese Idle and Powerdown Clock Control uis rb 1039 Bus Structure in Nonpage Mode and Page 13 1 External Bus Cycle Code Fetch Nonpage 13 4 External Bus Cycle Data Read Nonpage Mode 13 5 External Bus Cycle Data Write Nonpage 13 5 External Bus Cycle Code Fetch Page Mode sse 13 7 External Bus Cycle Data Read Page 13 7 External Bus Cycle Data Write Page Mode eee 13 8 External Bus Cycle Code Fetch with One RD PSEN Wait State Nonpage Mode a nere Rare tie a aee eni 13 9 External Bus Cycle Data Write with One WR Wait State Nonpage Mode 13 9 External Bus Cycle Code Fetch with One ALE Wait State Nonpage Mode 13 10 Configuration Byte Bus nennen 13 11 Bus Diagram for Example 1 80C2518B in Page 13 13 Memory Space for 1 13 14 Bus Diagram for Example 2 80C2518B in Page
93. Counter Mode Register S D9H 00XX X000 Data Pointer High S 83H 0000 0000 DPLt Data Pointer Low S 82H 0000 0000 DPXLt Data Pointer Extended Low 5 84 0000 0001 IEO Interrupt Enable Control Register 0 S A8H 0000 0000 IPHO Interrupt Priority High Control S B7H X000 0000 Register 0 IPLO Interrupt Priority Low Control S B8H X000 0000 Register 0 Port 0 S 80H 1111 1111 P1 Port 1 S 90H 1111 1111 P2 Port 2 S AO0H 1111 1111 P3 Port 3 S BOH 1111 1111 PCON Power Control Register 5 87 00XX 0000 PSW Program Status Word S DOH 0000 0000 PSW1 Program Status Word 1 S D1H 0000 0000 RCAP2H Timer 2 Reload Capture Register S CBH 0000 0000 High Byte RCAP2L Timer 2 Reload Capture Register S CAH 0000 0000 Low Byte SADDR Slave Individual Address Register S A9H 0000 0000 SADEN Mask Byte Register S B9H 0000 0000 SBUF Serial Data Buffer 5 99 XXXX XXXX SCON Serial Port Control Register S 98H 0000 0000 spt Stack Pointer LS byte of SPX S 81H 0000 0111 SPH Stack Pointer High MSB of SPX S BEH 0000 0000 T2CON Timer 2 Control Register S C8H 0000 0000 T2MOD Timer 2 Mode Control Register S C9H XXXX XX00 TCON Timer 0 1 Control Register S 88H 0000 0000 TMOD Timer 0 1 Mode Control Register 5 89 0000 0000 THO Timer 0 Timer Register High Byte S 8CH 0000 0000 TLO Timer 0 Timer Register Low Byte S 8AH 0000 0000 This register resides in the register file It can also be accessed as an SFR C 2 intel REGISTERS Table C 1 8XC251SA SB SP S
94. EXEN2 TR2 C T2 CP RL2 Bit Bit Function Number Mnemonic uneto 7 TF2 Timer 2 Overflow Flag Set by timer 2 overflow Must be cleared by software TF2 is not set if RCLK 1 or TCLK 1 6 EXF2 Timer 2 External Flag If EXEN2 1 capture or reload caused by a negative transition on T2EX sets EFX2 EXF2 does not cause an interrupt in up down counter mode DCEN 1 5 RCLK Receive Clock Bit Selects timer 2 overflow pulses RCLK 1 or timer 1 overflow pulses RCLK 0 as the baud rate generator for serial port modes 1 and 3 4 TCLK Transmit Clock Bit Selects timer 2 overflow pulses TCLK 1 or timer 1 overflow pulses TCLK 0 as the baud rate generator for serial port modes 1 and 3 3 EXEN2 Timer 2 External Enable Bit Setting EXEN2 causes a capture or reload to occur as a result of a negative transition on T2EX unless timer 2 is being used as the baud rate generator for the serial port Clearing EXEN2 causes timer 2 to ignore events at T2EX 2 TR2 Timer 2 Run Control Bit Setting this bit starts the timer 1 C T2 Timer 2 Counter Timer Select C T2 0 selects timer operation timer 2 counts the divided down system clock C T2 1 selects counter operation timer 2 counts negative transitions on external pin T2 0 CP RL2 Capture Reload Bit When set captures occur on negative transitions at T2EX if EXEN2 1 When cleared auto reloads occur on timer 2 overflows or negative transition
95. EXTERNAL MEMORY DESIGN EXAMPLES This section presents several external memory designs for 8XC251Sx systems These examples illustrate the design flexibility provided by the configuration options especially for the PSEN and RD signals Many designs are possible The examples employ the 8XC251SB but also apply to SA SP and SQ devices if the differences in on chip memory are allowed for Except for the first example which employs an 18 bit external address bus the examples are valid for A step ping as well B stepping devices 13 12 intel EXTERNAL MEMORY INTERFACE For a general discussion on external memory see Chapter 4 Configuring the External Memory Interface Figures 4 7 and 4 8 depict the mapping of internal memory space into external mem ory 13 6 1 Example 1 RD1 0 00 18 bit Bus External Flash and RAM In this example an 80C251SB operates in page mode with an 18 bit external address bus inter faced to 128 Kbytes of external flash memory and 128 Kbytes of external RAM Figure 13 12 This example does not apply to A stepping devices Figure 13 13 shows how the external flash and RAM are addressed in the internal memory space On chip data RAM 1056 bytes occupies the lowest addresses in region 00 CE CE RAM Flash 128 Kbytes 128 Kbytes 80 2515 17 WR A4219 01 Figure 13 12 Bus Diagram for Example 1 80C251SB in Page Mode 13 13 EXTERNAL MEMORY INTERFACE Mem
96. Encoding Source Mode Encoding JNZ PC PC 2 IF A 0 THEN PC lt PC rel Jump if greater than signed If the Z flag is clear AND the N flag and the OV flag have the same value branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice CY AC OV N 2 The instruction JSG LABEL1 causes program execution to continue at LABEL1 if the Z flag is clear AND the N flag and the OV flag have the same value Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0001 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JSG PC PC 2 IF N 0 AND OV THEN PC lt PC rel A 77 INSTRUCTION SET REFERENCE JSGE rel Function Description Flags Example Bytes States Encoding Hex Code in Operation JSL rel Function Description Flags A 78 intel Jump if greater than or equal signed If the N flag and the OV flag have the same value branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice CY AC OV N 2
97. I O power PWR or ground GND Note that all inputs except RESET are sampled inputs RESET is a level sensitive input During powerdown mode the powerdown circuitry uses EXTINTx as a level sensitive input Description Signal Name column Briefly describes the function of the pin for the specific signal listed in the Multiplexed With provides if applicable Lists the multiplexed signal name for the alternate function that the pin Table B 3 Signal Descriptions Signal Name Type Description Multiplexed With A17 Address Line A17 Eighteenth external address bit A17 in extended bus applications Selected by configuration bits RD1 0 B stepping UCONFIGO 3 2 Table B 4 Also see RD and PSEN P1 7 CEX4 A16 Address Line A16 Seventeenth external address bit A16 in extended bus applications Selected by configuration bits RD1 0 B stepping UCONFIGO0 3 2 Table B 4 A stepping CONFIGO 3 2 Table B 4 Also see RD RD 15 8 Address Lines Upper address lines for the external bus P2 7 0 AD7 0 VO Address Data Lines Multiplexed lower address lines and data lines for external memory P0 7 0 ALE Address Latch Enable ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15 8 and AD7 0 An external latch can use ALE to demultiplex the address from the address data bus
98. I O ports when used as address data bus drivers Port 0 internal pullups assist the logic one output for memory bus cycles only Except for these bus cycles the pullup FET is off All other port 0 outputs are open drain 7 4 intel INPUT OUTPUT PORTS 7 5 READ MODIFY WRITE INSTRUCTIONS Some instructions read the latch data rather than the pin data The latch based instructions read the data modify the data and then rewrite the latch These are called read modify write in structions Below is a complete list of these special instructions When the destination operand is a port or a port bit these instructions read the latch rather than the pin ANL logical AND e g ANL Pl A ORL logical OR e g ORL P2 A XRL logical EX OR e g XRL P3 A JBC jump if bit 1 and clear bit e g JBC P1 1 LABEL CPL complement bit e g CPL P3 0 INC increment e g INC P2 DEC decrement e g DEC P2 DJNZ decrement and jump if not zero e g DJNZ P3 LABEL MOV PX Y C move carry bit to bit Y of port X CLR PX Y clear bit Y of port X SETB PX Y set bit Y of port x It is not obvious the last three instructions in this list are read modify write instructions These instructions read the port all 8 bits modify the specifically addressed bit and write the new byte back to the latch These read modify write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretati
99. INPUT OUTPUT PORTS intel 7 2 CONFIGURATIONS Each port SFR operates via type D latches as illustrated in Figure 7 1 for ports 1 and 3 A CPU write to latch signal initiates transfer of internal bus data into the type D latch A CPU read latch signal transfers the latched Q output onto the internal bus Similarly a read pin signal transfers the logical level of the port pin Some port data instructions activate the read latch sig nal while others activate the read pin signal Latch instructions are referred to as read modify write instructions see Read Modify Write Instructions on page 7 5 Each I O line may be in dependently programmed as input or output 7 3 PORT 1 AND PORT Figure 7 1 shows the structure of ports 1 and 3 which have internal pullups external source can pull the pin low Each port pin can be configured either for general purpose I O or for its al ternate input or output function Table 7 1 To use a pin for general purpose output set or clear the corresponding bit in the Px register x 1 3 To use a pin for general purpose input set the bit in the Px register This turns off the output driver FET To configure a pin for its alternate function set the bit in the Px register When the latch is set the alternate output function signal controls the output level Figure 7 1 The operation of ports 1 and 3 is discussed further in Quasi bidirectional Port Operation on page 7
100. Internal Memory and External 16 external address bits Read Write Signals Memory PO P2 Notes 1 Single read signal 2 P3 7 RD A16 functions PSEN only as P3 7 WR 64 Kbytes 00 01 02 03 FC FD FE FF PSEN WR RD1 0 11 Internal Memory and External 16 external address bits Read Write Signals Memory Po P2 Notes 1 Compatible with MCS 51 PSEN microcontrollers 128 Kbytes 2 Cannot write to regions FC FF FC FD FE FF 00 01 02 03 RD WR A4217 01 Figure 4 8 Internal External Memory Mapping RD1 0 10 and 11 intel DEVICE CONFIGURATION This selection provides a 128 Kbyte external address space The advantage of this selection in comparison with the 256 Kbyte external memory space with RD1 0 00 is the availability of pin P1 7 CEXA for general I O or PCA I O I O P3 7 is unavailable All four 64 Kbyte regions are strobed by PSEN and WR Sections 13 6 2 and 13 6 3 show examples of memory designs with this option For the A stepping of the 8XC251SB this selection provides a 128 Kbyte external memory space The only difference from the B stepping is the absence of internal regions 02 03 FC and FD Regions 00 and FE map into one region in external memory while regions 01 and FF map into the other region of external memory 4 6 2 3 RD1 0 10 16 External Address Bits For RD1 0 10 the 16 external address bits A15 0 on ports PO and P2 provide a single 64 Kb
101. Mbyte address space RETI also clears the interrupt request line See the note in Table 5 8 regarding compatibility with code written for MCS 51 microcontrollers The TRAP instruction is useful for the development of emulations of an MCS 251 microcontrol ler 5 6 PROGRAM STATUS WORDS The Program Status Word PSW register and the Program Status Word 1 PSW 1 register contain four types of bits Figure 5 2 on page 5 18 and Figure 5 3 on page 5 19 CY AC OV N and Z are flags set by hardware to indicate the result of an operation The P bit indicates the parity of the accumulator e Bits RSO and RSI are programmed by software to select the active register bank for registers RO R7 e 0 UD are available to the user as general purpose flags The PSW PSWI registers are read write registers however the parity bit in the PSW is not affected by a write Individual bits can be addressed with the bit instructions Bit Instructions on page 5 11 The PSW and PSW1 bits are used implicitly in the conditional jump instructions Conditional Jumps on page 5 14 The PSW register is identical to the PSW register in MCS 51 microcontrollers The PSW regis ter exists only in MCS 251 microcontrollers Bits CY AC RSO RS1 and OV in PSWI are iden tical to the corresponding bits in PSW i e the same bit can be accessed in either register Table 5 10 lists the instructions that affect the CY AC OV N and Z bits
102. Mode 1 2 1 2 0001 irrr Binary Mode Encoding Source Mode A5 Encoding DEC Rn lt Rn 1 DEC lt dest gt lt src gt Function Description Flags Example Variations Decrement Decrements the specified variable at the destination operand by 1 2 or 4 An original value of 00H underflows to OFFH CY AC OV N 2 Register 0 contains 7FH 01111111B After executing the instruction sequence DEC RO 1 register 0 contains 7EH DEC Rm short Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0001 1011 5555 01 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation DEC Rm lt Rm short DEC WRij short Bytes States A 56 Binary Mode Source Mode 3 2 2 1 intel Encoding Hex Code in Operation INSTRUCTION SET REFERENCE 0001 1011 tttt 0 1 vv Binary Mode A5 Encoding Source Mode Encoding DEC lt WR short DEC DRk short Binary Mode Source Mode Bytes 3 2 States 5 4 Encoding 0001 1011 uuuu 11 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation DEC lt short DIV lt dest gt lt src gt Divides the unsigned integer in the register by the unsigned integer operand in register For byte operands lt dest gt lt src
103. Mode Source Mode Bytes 4 3 States 4 3 Encoding 0111 1110 uuuu 1011 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm lt DRk MOV WRjd OWRjs Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0000 1011 TTTT 1000 tttt 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRjd lt WRis MOV WRj DRk Binary Mode Source Mode Bytes 4 3 States 5 4 Encoding 0000 1011 uuuu 1010 tttt 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV A 92 WRj lt DRk intel INSTRUCTION SET REFERENCE MOV dir8 Rm Binary Mode Source Mode Bytes 4 3 States 41 31 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0111 1010 ssss 0011 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV dir8 lt Rm MOV dir8 WRj Binary Mode Source Mode Bytes 4 3 States 5 4 Encoding 0111 1010 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV dir8 lt WRj MOV dir8 DRk Binary Mode Source Mode Bytes 4 3 States 7 6 Encoding 0111 1010 uuuu 1101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV dir8 lt MOV dir16 Rm Binary Mode Sour
104. Other bit combinations are invalid See Figure 9 9 for bit definitions 2 0 4 X Don t care ing the operating modes of the PCA 3 For PCA WDT mode also set the WDTE bit the register to enable the reset output signal PROGRAMMABLE COUNTER ARRAY intel CCAPMx x 0 4 Address CCAPMO S DAH CCAPM1 S DBH CCAPM2 S DCH CCAPM3 S DDH CCAPM4 S DEH Reset State X000 0000B 7 0 ECOMx CAPPx CAPNx MATx TOGx PWMx ECCFx Bit Bit Number Mnemonic Function 7 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 6 ECOMx Compare Modes 1 enables the module comparator function The comparator is used to implement the software timer high speed output pulse width modulation and watchdog timer modes 5 CAPPx Capture Mode Positive CAPPx 1 enables the capture function with capture triggered by a positive edge on pin CEXx 4 CAPNx Capture Mode Negative CAPNx 1 enables the capture function with capture triggered by a negative edge on pin CEXx 3 MATx Match Set ECOMx and MAT x to implement the software timer mode When MATx 1 a match of the PCA timer counter with the compare capture register sets the CCFx bit in the CCON register flagging an interrupt 2 TOGx Toggle Set ECOMx MATx and TOGx to implement the high speed output mode When TOGx 1 a match of the PCA timer counter with the
105. PCA module that has the WDT mode When not programmed as a WDT it can be used in the other modes To program module 4 for the PCA WDT mode Figure 9 4 set the ECOM4 and MAT4 bits in the CCAPM4 register and WDTE bit in register Table 9 3 on page 9 15 lists the bit combinations for selecting module modes Also select the desired input for the PCA tim er counter by programming the CPSO CPS1 bits in register see Figure 9 7 on page 9 13 Enter a 16 bit comparison value in the compare capture registers CCAP4H CCAP4L Enter a 16 bit initial value in the PCA timer counter CH CL or use the reset value 0000H The difference between these values multiplied by the PCA input pulse rate determines the running time to expiration Set the timer counter run control bit CR in the CCON register to start the PCA WDT 9 9 PROGRAMMABLE COUNTER ARRAY intel The PCA WDT generates a reset signal each time a match occurs To hold off a PCA WDT reset the user has three options e periodically change the comparison value in CCAPAH CCAPAL so a match never occurs periodically change the PCA timer counter value so a match never occurs disable the module 4 reset output signal by clearing the WDTE bit before a match occurs then later re enable it The first two options are more reliable because the WDT is not disabled as in the third option The second option is not recommended if other PCA modules are in use
106. RCAP2H Timer 2 Reload Capture High Byte S CBH WDTRST WatchDog Timer Reset S A6H Table 3 10 Programmable Counter Array PCA SFRs Mnemonic Name Address CCON PCA Timer Counter Control S D8H CMOD PCA Timer Counter Mode S D9H CCAPMO PCA Timer Counter Mode 0 S DAH CCAPM1 PCA Timer Counter Mode 1 S DBH CCAPM2 PCA Timer Counter Mode 2 S DCH CCAPMS3 PCA Timer Counter Mode 3 S DDH CCAPM4 PCA Timer Counter Mode 4 S DEH ADDRESS SPACES 3 20 In Table 3 10 Programmable Counter Array PCA SFRs Continued Mnemonic Name Address CL PCA Timer Counter Low Byte S E9H CH PCA Timer Counter High Byte S F9H CCAPOL PCA Compare Capture Module 0 Low Byte S EAH CCAP1L PCA Compare Capture Module 1 Low Byte S EBH CCAP2L PCA Compare Capture Module 2 Low Byte S ECH CCAP3L PCA Compare Capture Module 3 Low Byte S EDH CCAP4L PCA Compare Capture Module 4 Low Byte S EEH CCAPOH PCA Compare Capture Module 0 High Byte S FAH CCAP1H PCA Compare Capture Module 1 High Byte S FBH CCAP2H PCA Compare Capture Module 2 High Byte S FCH CCAP3H PCA Compare Capture Module 3 High Byte S FDH CCAP4H PCA Compare Capture Module 4 High Byte S FEH tel intel Device Configuration intel CHAPTER 4 DEVICE CONFIGURATION The 8 2515 provides user design flexibility by configuring certain operating features at de vice reset These features fall into the following cat
107. Source Mode Encoding Operation ADD DRkd DRks A 29 INSTRUCTION SET REFERENCE ADD Rm data Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0010 1110 ssss 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD Rm Rm data ADD WRij data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0010 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD WRj WRj data16 ADD DRk 0data16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 0010 1110 uuuu 1000 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD DRk lt data16 ADD Rm dir8 Binary Mode Source Mode Bytes 4 3 States 3t 2t tlf this instruction addresses a port Px x 0 3 add 1 state A 30 intel INSTRUCTION SET REFERENCE Encoding 0010 1110 5555 0001 direct Hex Code in Binary A5 Encoding Source Mode Encoding Operation ADD Rm Rm dir8 ADD WRi dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0010 1110 tttt 0101 direct addr Hex Co
108. THEN PC PC rel Jump if less than or equal If the Z flag or the CY flag is set branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice CY AC OV N 2 The instruction JLE LABEL1 causes program execution to continue at LABEL1 if the Z flag or the CY flag is set Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0010 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding intel INSTRUCTION SET REFERENCE Operation JLE PC PC 2 IF 2 1 OR CY 1 THEN PC lt PC rel JMP A DPTR Function Jump indirect Description Add the 8 bit unsigned contents of the accumulator with the 16 bit data pointer and load the resulting sum into the lower 16 bits of the program counter This is the address for subsequent instruction fetches The contents of the accumulator and the data pointer are not affected Flags CY AC OV N Z Example The accumulator contains an even number from 0 to 6 The following sequence of instruc tions branch to one of four AJMP instructions in a jump table starting at JMP_TBL MOV DPTR ZJMP JMP A DPTR AJMP LABELO JME TBE LABEL1 AJMP LABEL2 AJMP LABEL3 If the accumulator contains 04H at th
109. This means that reads writes to different internal memory addresses can access the same location in external memory For example if the 8XC251Sx is configured for 18 external address lines a write to location 03 6000H and a write to location FF 6000H accesses the same 18 bit external address 1 6000H because A16 1 and A17 1 for both internal addresses In other words regions 00 and FC map into the same 64 Kbyte region in external memory In some situations however a multiple mapping from internal memory to external memory does not preclude using more than one region For example for a device with on chip ROM OTPROM EPROM configured for 17 address bits and with 1 an access to FF 0000H FF 3FFFH 16 Kbytes accesses the on chip ROM OTPROM EPROM while an access to 03 0000H 03 3FFFH is to external memory In this case you could execute code from these lo cations in region FF and store data in the corresponding locations in region 03 without conflict See Figure 4 7 and Example 3 RD1 0 01 17 bit Bus External RAM on page 13 17 4 6 2 1 RD1 0 00 18 External Address Bits NOTE The combination RD1 0 00 is invalid for the A stepping 8XC251SB The selection RD1 0 00 provides 18 external address bits A15 0 ports PO and P2 A16 from P3 7 RD A16 and A17 from P1 7 CEX4 A17 Bits A16 and A17 can select four 64 Kbyte regions of external memory for a total of 256 Kbytes top half of Figure 4 7 on page 4 13 Thi
110. WRij short Word reg by 1 2 or 4 3 2 2 1 DRk short Double word reg by 1 2 or 4 3 4 2 3 INC DPTR Data pointer 1 1 1 1 NOTES 1 A shaded cell denotes an instruction in the MCS 51 architecture 2 fthis instruction addresses an I O port Px x 0 3 add 2 to the number of states Table A 22 Summary of Multiply Divide and Decimal adjust Instructions Multiply MUL lt reg1 reg2 gt 2 MUL AB B A AxB Divide DIV lt reg1 gt lt reg2 gt 2 DIV AB A Quotient B Remainder Decimal adjust ACC DAA 2 for Addition BCD Binary Mode Source Mode Mnemonic dest src Notes Bytes States Bytes States AB Multiply A and B 1 5 1 5 MUL Rmd Rms Multiply byte reg and byte reg 3 6 2 5 WRjd WRjs Multiply word reg and word reg 3 12 2 11 AB Divide A by B 1 10 1 10 DIV Rmd Rms Divide byte reg by byte reg 3 11 2 10 WRjd WRjs Divide word reg by word reg 3 21 2 20 DA A Decimal adjust acc 1 1 1 1 NOTES 1 Ashaded cell denotes an instruction in the MCS 51 architecture 2 Instruction Descriptions on page 26 intel INSTRUCTION SET REFERENCE Table A 23 Summary of Logical Instructions Logical AND Logical OR Logical Exclusive OR ANL dest src ORL lt dest gt lt src gt XRL dest src dest dest A src dest opnd lt dest opnd V src opnd dest opnd lt dest opnd v src opnd
111. Write the byte to be transmitted to the SBUF register This write starts the transmission 10 2 2 2 Reception Modes 1 2 3 To prepare for a reception set the REN bit in the SCON register The actual reception is then ini tiated by a detected high to low transition on the RXD pin intel SERIAL I O PORT 10 3 FRAMING BIT ERROR DETECTION MODES 1 2 AND 3 Framing bit error detection is provided for the three asynchronous modes To enable the framing bit error detection feature set the SMODO bit in the PCON register see Figure 12 1 on page 12 2 When this feature is enabled the receiver checks each incoming data frame for a valid stop bit An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs If a valid stop bit is not found the software sets the FE bit in the SCON register see Figure 10 2 on page 10 3 Software may examine the FE bit after each reception to check for data errors Once set only soft ware or reset can clear the FE bit Subsequently received frames with valid stop bits cannot clear the FE bit 10 4 MULTIPROCESSOR COMMUNICATION MODES 2 AND 3 Modes 2 and 3 provide a ninth bit mode to facilitate multiprocessor communication To enable this feature set the SM2 bit in the SCON register see Figure 10 2 on page 10 3 When the mul tiprocessor communication feature is enabled the serial port can differentiate between data frames ninth bit clear and address
112. a signal name the symbol means that the signal is active low When used in an instruction the symbol prefixes an immediate value in immediate addressing mode Italics identify variables and introduce new terminology The context in which italics are used distinguishes between the two possible meanings Variables in registers and signal names are commonly represented by x and y where x represents the first variable and y represents the second variable For example in register Px y x represents the variable 1 4 that identifies the specific port and y represents the register bit variable 7 0 Variables must be replaced with the correct values when configuring or programming registers or identifying signals Uppercase X no italics represents an unknown value or a don t care state or condition The value may be either binary or hexadecimal depending on the context For example 2XAFH hex indicates that bits 11 8 are unknown 10 in binary context indicates that the two LSBs are unknown The terms assert and deassert refer to the act of making a signal active enabled and inactive disabled respectively The active polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert ALE is to drive it high to deassert RD is to drive it high to deassert ALE is to drive it low Instruction m
113. binary mode bit bit operand bit51 byte clear code memory configuration bytes dir8 dir16 DPTR DPX deassert Glossary 2 intel The ability of an MCS 251 microcontroller to execute without modification binary code written for an MCS 51 microcontroller An operating mode selected by a configuration bit that enables an MCS 251 microcontroller to execute without modification binary code written for an MCS 51 microcontroller A binary digit An addressable bit in the MCS 251 architecture An addressable bit in the MCS 51 architecture Any 8 bit unit of data The term clear refers to the value of a bit or the act of giving it a value If a bit is clear its value is 0 clearing a bit gives it a 0 value See program memor y Bytes residing in on chip OTPROM ROM that determine a set of operating parameters for the 8XC251SB An 8 bit direct address This can be a memory address or an SFR address A 16 bit memory address 00 0000 00 used in direct addressing The 16 bit data pointer In MCS 251 microcontrollers DPTR is the lower 16 bits of the 24 bit extended data pointer DPX The 24 bit extended data pointer in MCS 251 micro controllers See also DPTR The term deassert refers to the act of making a signal inactive disabled The polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high s
114. by the first operand One of the operands must be the CY flag the other may be any directly addressable bit Does not affect any other register CY AC OV N 2 The CY flag is set input Port 3 contains 11000101B and output Port 1 contains 35H 00110101B After executing the instruction sequence MOV P1 3 CY MOV MOV P1 2 CY the CY flag is clear and Port 1 contains 39H 00111001B Binary Mode Source Mode 2 2 2t 2t tlf this instruction addresses a port x 0 3 add 2 states 1001 0010 bit addr Binary Mode Encoding Source Mode Encoding MOV bit51 lt CY intel INSTRUCTION SET REFERENCE MOV CY bit51 Binary Mode Source Mode Bytes 2 2 States 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1010 0010 bit addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOV CY lt bit51 MOV bit CY Binary Mode Source Mode Bytes 4 3 States 4t 3t tlf this instruction addresses a port x 0 3 add 2 states Encoding 1010 1001 1001 0 yyy direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV bit lt CY MOV CY bit Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state
115. clear the compare capture flag when the interrupt is processed the user must clear the flag in soft ware If the user does not change the compare capture registers in the interrupt routine the next toggle occurs after the PCA timer counter rolls over and the count again matches the comparison value During the interrupt routine a new 16 bit compare value can be written to the compare capture registers CCAPxH CCAPAXL NOTE To prevent an invalid match while updating these registers user software should write to CCAPxL first then CCAPxH A write to CCAPXL clears the bit disabling the compare function while a write to CCAPxH sets the bit re enabling the compare function 9 3 5 PCA Watchdog Timer Mode A watchdog timer WDT provides the means to recover from routines that do not complete suc cessfully A WDT automatically invokes a device reset if it does not regularly receive hold off signals WDTs are used in applications that are subject to electrical noise power glitches elec trostatic discharges etc or where high reliability is required In addition to the 8XC251Sx s 14 bit hardware WDT the PCA provides a programmable fre quency 16 bit WDT as a mode option on compare capture module 4 This mode generates a de vice reset when the count in the PCA timer counter matches the value stored in the module 4 compare capture registers A PCA WDT reset has the same effect as an external reset Module 4 is the only
116. crystal case To Internal Timing Circuit 8XC251Sx Quartz Crystal or Ceramic Resonator D1 gt um A4143 02 Figure 11 2 CHMOS On chip Oscillator 11 3 MINIMUM HARDWARE SETUP intel For a more in depth discussion of crystal specifications ceramic resonators and the selection of C1 and C2 see Applications Note AP 155 Oscillators for Microcontrollers in the Embedded Applications handbook 11 3 2 On chip Oscillator Ceramic Resonator In cost sensitive applications you may choose a ceramic resonator instead of a crystal Ceramic resonator applications may require slightly different capacitor values and circuit configuration Consult the manufacturer s data sheet for specific information 11 3 3 External Clock To operate the CHMOS 8XC251Sx from an external clock connect the clock source to the XTALI pin as shown in Figure 11 3 Leave the XTAL2 pin floating The external clock driver can be a CMOS gate If the clock driver is a TTL device its output must be connected to Vec through a 4 7 KQ pullup resister 8XC251Sx Note Voce is secondary power pin that reduces power supply noise and are secondary ground pins that reduce ground bounce and improve power supply by passing Connections to these pins are not required for proper device operation A4141 02 Figure 11 3 External Clock Connection intel MINIMUM HARDWARE SETUP For external clock drive re
117. cycle from two states to three For read and write external bus cycles the extended ALE extends the bus cycle from three states to four State 1 State 2 State 3 ALE i i RD PSEN 17 16 2 15 8 2813 04 Figure 13 10 External Bus Cycle Code Fetch with ALE Wait State Nonpage Mode 13 4 CONFIGURATION BYTE BUS CYCLES If EAst 0 B stepping devices obtain configuration information from a configuration array in external memory This section describes the bus cycles executed by the reset routine to fetch user configuration bytes from external memory Configuration bytes are discussed in Chapter 4 De vice Configuration To determine whether the external memory is set up for page mode or nonpage mode operation the 8XC251Sx accesses external memory using internal address FF FFF8H UCONFIGO See states 1 4 in Figure 13 11 If the external memory is set up for page mode it places UCONFIGO on P2 as D7 0 overwriting A15 8 FFH If external memory is set up for nonpage mode A15 8 is not overwritten The 8XC251Sx examines P2 bit 1 Subsequent configuration byte fetches are in page mode if P2 1 0 and nonpage mode if P2 1 1 The 8XC251 Sx fetches UCONFIGO again states 5 8 in Figure 13 11 and then UCONFIGI via internal address FF FFF9H The configuration byte bus cycles always execute with ALE extended and one PSEN wait state 13 10 intel e EXTERNAL MEMORY INTERFACE State
118. dir8 MOV DRk dir8 Binary Mode Source Mode Bytes 4 3 States 6 5 Encoding 0111 1110 uuuu 1101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk dir8 MOV Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 A 90 intel INSTRUCTION SET REFERENCE Encoding 0111 1110 5555 0011 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm lt dir16 MOV WRi dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0111 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj dir16 MOV DRk dir16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 0111 1110 uuuu 1111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk lt dir16 MOV Rm WRj Binary Mode Source Mode Bytes 4 3 States 2 2 Encoding 0111 1110 tttt 1001 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding A 91 INSTRUCTION SET REFERENCE Operation MOV Rm MOV Rm DRk Binary
119. direct or indirect addressing The ADDC and SUBB instructions Table A 19 on page A 14 are the same as those for MCS 51 microcontrollers The CMP compare instruction Table A 20 on page A 15 calculates the difference of two bytes or words and then writes to flags CY OV AC N and Z in the PSW and PSWI registers The difference is not stored The operands can be addressed in a variety of modes The most frequent use of CMP is to compare data or addresses preceding a conditional jump instruction Table A 21 on page A 16 lists the INC increment and DEC decrement instructions The in structions for MCS 51 microcontrollers are supplemented by instructions that can address byte word and dword registers and increment or decrement them by 1 2 or 4 denoted by short These instructions are supplied primarily for register based address pointers and loop counters 5 8 intel PROGRAMMING The MCS 251 architecture provides the MUL multiply and DIV divide instructions for un signed 8 bit and 16 bit data Table A 22 on page A 16 Signed multiply and divide are left for the user to manage through a conversion process The following operations are implemented eight bit multiplication 8 bits x 8 bits 16 bits sixteen bit multiplication 16 bits x 16 bits 32 bits eight bit division 8 bits 8 bits 16 bits 8 bit quotient 8 bit remainder sixteen bit division 16 bits 16 bits 32 bits 16 bit quotient 1
120. dword reg DRk 1data16 one extended 16 bit immediate data 5 5 4 4 to dword reg NOTES 1 A shaded cell denotes an instruction in the MCS 51 architecture 2 Instructions that move bits are in Table A 26 on page A 23 3 If this instruction addresses an I O port x 0 3 add 1 to the number of states 4 External memory addressed by instructions in the MCS 51 architecture is in the region specified by DPXL reset value 01H See Compatibility with the MCS 51 Architecture on page 3 2 INSTRUCTION SET REFERENCE intel Table A 24 Summary of Move Instructions Continued MOV lt dest gt lt src gt MOVS dest src MOVZ lt dest gt lt src gt MOVC lt dest gt lt src gt MOVX lt dest gt lt src gt MOVX dest src Move 2 Move with Sign Extension Move with Zero Extension Move Code Byte Move to External Mem Move from External Mem destination lt src destination lt src with sign extend destination src with zero extend A lt code byte external mem lt A lt source in external mem Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States DRk dir8 Dir addr to dword reg 4 6 3 5 DRk dir16 Dir addr 64K to dword reg 5 6 4 5 Rm dir8 Dir addr to byte reg 4 3 3 3 2 3 WRj dir8 Dir
121. enabling the PCA WDT reset output module 4 only and enabling the PCA timer counter overflow interrupt 4 0 CIDL WDTE CPS1 50 Bit Bit Number Mnemonic Function 7 CIDL PCA Timer Counter Idle Control CIDL 1 disables the PCA timer counter during idle mode CIDL 0 allows the PCA timer counter to run during idle mode 6 WDTE Watchdog Timer Enable WDTE 1 enables the watchdog timer output on PCA module 4 WDTE 0 disables the PCA watchdog timer output 5 3 Reserved The values read from these bits are indeterminate Do not write a 1 to these bits 2 1 CPS1 0 PCA Timer Counter Input Select CPS1 CPSO 0 0 Fosc 12 0 1 Fosc 4 1 0 Timer 0 overflow 1 1 External clock at pin maximum rate Fog 8 0 ECF PCA Timer Counter Interrupt Enable 1 enables the CF bit in the CCON register to generate an interrupt request intel i REGISTERS DPH Address 5 83 Reset State 0000 0000B Data Pointer High DPH provides SFR access to register file location 58 also named DPH DPH is the upper byte of the 16 bit data pointer DPTR Instructions in the MC for data moves code moves and for a jump instruction JMP A DPTR See also DPL and DPXL 51 architecture use DPTR 7 0 DPH Contents Bit Bit Number Mnemonic Function 7 0 DPH 7 0 Data Pointer High Bits 8 15 of the extended data po
122. gt Rmd Rms the result is 16 bits The 8 bit quotient is stored in the higher byte of the word where Rmd resides the 8 bit remainder is stored in the lower byte of the word where Rmd resides For example Register 1 contains 251 OFBH or 11111011B and register 5 contains 18 12H or 00010010B After executing the instruction register 1 contains 13 ODH or 00001101B register 0 contains 17 11H or 00010001B Function Divide Description addressing mode and clears the CY and OV flags DIV R1 R5 since 251 13 X 18 17 and the CY and OV bits are clear see Flags Flags The CY flag is cleared The N flag is set if the MSB of the quotient is set The Z flag is set if the quotient is zero CY AC OV N 2 0 Exception if src contains 00H the values returned in both operands are undefined the CY flag is cleared OV flag is set and the rest of the flags are undefined CY AC OV N Z 0 um 1 A 57 INSTRUCTION SET REFERENCE intel Variations DIV Rmd Rms Binary Mode Source Mode Bytes 3 2 States 11 10 Encoding 1000 1100 ssss 5555 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation DIV 8 bit operands lt remainder Rms if dest md 0 2 4 14 Rmd 1 lt quotient Rmd Rms Rmd 1 remainder Rmd Rms if dest md 1 3 5 15 lt quotient
123. increases switch speed The extra pullup briefly sources 100 times normal internal circuit current The internal pullups are field effect transistors rather than linear resistors Pullups consist of three p channel FET pFET devices A pFET is on when the gate senses logical zero and off when the gate senses logical one pFET 1 is turned on for two oscillator periods immediately after a zero to one transition in the port latch A logic one at the port pin turns on pFET 3 a weak pullup through the inverter This inverter and pFET pair form a latch to drive logic one pFET 2 is a very weak pullup switched on whenever the associated nFET is switched off This is traditional CMOS switch convention Current strengths are 1 10 that of pFET 3 2 Osc Periods Vcc Voc Voc Port Q From Port Latch Input Data Read Port Pin A2242 01 Figure 7 4 Internal Pullup Configurations 7 6 intel INPUT OUTPUT PORTS 7 7 PORT LOADING Output buffers of port 1 port 2 and port 3 can each sink 1 6 mA at logic zero see Vo specifica tions in the 8XC251Sx data sheet These port pins can be driven by open collector and open drain devices Logic zero to one transitions occur slowly as limited current pulls the pin to a log ic one condition Figure 7 4 on page 7 6 A logic zero input turns off pFET 3 This leaves only pFET 2 weakly in support of the transition In external bus mode port 0 output buffers each sink 3 2 mA at logic ze
124. intel INSTRUCTION SET REFERENCE Table A 2 Notation for Direct Addresses Direct 251 MCS 51 Address Description Arch Arch dir8 An 8 bit direct address This can be a memory address v v 00 0000 00 007 or an SFR address S 00H S FFH dir16 A 16 bit memory address 00 0000H 00 FFFFH used in direct v addressing Table A 3 Notation for Immediate Addressing Immediate oe MCS 251 MCS 51 Data Description Arch Arch data An 8 bit constant that is immediately addressed in an instruction v v data16 A 16 bit constant that is immediately addressed in an instruction v 0data16 A 32 bit constant that is immediately addressed in an instruction The v 1data16 upper word is filled with zeros 0data16 or ones 1data16 short A constant equal to 1 2 or 4 that is immediately addressed an instruction v Binary representation of short Table A 4 Notation for Bit Addressing Bit 222 99 251 MCS 51 Address Description Arch Arch bit A directly addressed bit in memory locations 00 0020 00 007 or in any defined SFR v yyy A binary representation of the bit number 0 7 within a byte bit51 A directly addressed bit bit number 00 in memory or an SFR Bits 00H 7FH are the 128 bits in byte locations 20H 2FH in the on chip v RAM Bits 80H FFH are the 128 bits in the 16 SFR s with addresses that end in OH or 8
125. intel SERIAL I O PORT The SADEN byte is selected so that each slave may be addressed separately For Slave A bit 0 the LSB is a don t care bit for Slaves and C bit 0 is a 1 To communicate with Slave A only the master must send an address where bit 0 is clear e g 1111 0000 For Slave A bit 1 is a 0 for Slaves B and C bit 1 is a don t care bit To communicate with Slaves and but not Slave A the master must send an address with bits and 1 both set e g 1111 0011 For Slaves A and B bit 2 is a don t care bit for Slave C bit 2 is a0 To communicate with Slaves A and B but not Slave C the master must send an address with bit O set bit 1 clear and bit 2 set e g 1111 0101 To communicate with Slaves A B and C the master must send an address with bit set bit 1 clear and bit 2 clear e g 1111 0001 10 5 2 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don t care bits e g SADDR 01010110 SADEN 11111100 SADDR OR SADEN 1111 111X The use of don t care bits provides flexibility in defining the broadcast address however in most applications a broadcast address is OFFH The following is an example of using broadcast addresses Slave A SADDR 1111 0001 Slave C SADDR 11110010 SADEN 11111010 SADEN 1111 1101 Broadcast 1111 1X11 Broadcast 1111 1111 Slave B SADDR 11110011 SADEN 1111 10
126. memory on the 83C251Sx controller is factory programmed The verification proce dure for the 83C251Sx is exactly the same as for the 87C251Sx The setup shown in Figure 14 1 applies as do the waveform and timing diagrams Like the 87C25 1Sx the 83C251Sx has 8 Kbytes or 16 Kbytes of on chip code memory and a 128 byte encryption array For information on verifying the contents of nonvolatile memory on the 83C251Sx see Pro grammable Functions on page 14 7 for each function desired Or more directly perform the ver ification procedure described in Verify Algorithm on page 14 7 using the appropriate verify mode Table 14 1 14 8 VERIFYING THE 80C251SB ROMLESS A STEPPING The configuration bytes stored in nonvolatile memory on an A stepping 80C251SB can be read using the verify procedure presented in this chapter For information regarding the A stepping configuration bytes see Device Configuration A stepping on page 4 2 14 10 intel PROGRAMMING AND VERIFYING NONVOLATILE MEMORY Programming Cycle Verification Cycle Address 16 Bits va P2 Data In 8 Bits TDVGL TGHDX lt gt TAVGL TGHAX ee TGHGL gt PROG lt 112 4 5 gt E TGHSL TSHGL ERN 12 75V PP TELQV TEHQZ gt TEHSH gt gt x Mode 8 Bits 4128 01 Figure 14 3 Program Verify Timing Diagram Table 14 4 Program Verify Timing Definitions Symbol Definition Symbol
127. mode of operation program verify and memory area specified on port 0 the address with respect to the starting address of the memory area ap plied to ports 1 and 3 and the data on port 2 Apply a logic high to the RST and V to ALE PSEN normally an output pin must be held low externally To perform the write operation raise Vy to 12 75 V and pulse the PROG pin per Table 14 1 Then return V to 5 V Verification is performed in a similar manner but without increasing and without pulsing PROG Figure 14 2 on page 14 6 shows the program and verify bus cycle waveforms For waveform timing information refer to Figure 14 3 and Table 14 4 at the end of this section CAUTION The source must be well regulated and free of glitches The voltage on the Vpp pin must not exceed the specified maximum even under transient conditions See latest data sheet 14 3 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY Table 14 1 Programming and Verifying Modes Mode RST PSEN PROG Port Port Address Notes 0 2 Port 1 high Port 3 low Program Mode On chip High Low 5 V 5 Pulses 68H data 1 5 Code Memory 12 75 V 8K 87C251SA SP 0000H 1FFFH 16K 87C251SB SQ 0000 Verify Mode On chip High Low 5V High 28H data 5 Code Memory 8K 87 83C251SA SP 0000H 1FFFH 16K 87 83C251SB SQ 0000 Program Mode B stepping High Low 5V
128. not clear the THx and TLx timer registers The timer registers can be accessed to obtain the current count or to enter preset values Timer 0 and timer can also be controlled by external pin INTx to facilitate pulse width measurements 8 1 TIMER COUNTERS AND WATCHDOG TIMER intel Table 8 1 Timer Counter and Watchdog Timer SFRs Mnemonic Description Address TLO Timer 0 Timer Registers Used separately as 8 bit counters or in cascade S 8AH THO as a 16 bit counter Counts an internal clock signal with frequency Fosc 12 S 8CH timer operation or an external input event counter operation TL1 Timer 1 Timer Registers Used separately as 8 bit counters or in cascade S 8BH TH1 as 16 bit counter Counts an internal clock signal with frequency 12 S 8DH timer operation or an external input event counter operation TL2 Timer 2 Timer Registers TL2 and TH2 connect in cascade to provide a S CCH TH2 16 bit counter Counts an internal clock signal with frequency Fog 12 S CDH timer operation or an external input event counter operation TCON Timer 0 1 Control Register Contains the run control bits overflow flags S 88H interrupt flags and interrupt type control bits for timer 0 and timer 1 TMOD Timer 0 1 Mode Control Register Contains the mode select bits S 89H counter timer select bits and external control gate bits for timer 0 and timer 1 T2CON Timer 2 Control Register Contains the r
129. of the configuration array are reserved for future use When EA 1 the MCS 251 micro controller obtains configuration information at reset from on chip non volatile memory at ad dresses FF FFF8H and FF FFF9H When 0 the MCS 251 microcontroller obtains configuration information at reset from external user memory using internal addresses FF FFF8H and FF FFF9H CAUTION The eight highest addresses in the memory address space FF FFF8H FF FFFFH are reserved for the configuration array Do not read or write user code at these locations These address are also used to access the configuration array in external memory so the same restrictions apply to the eight highest addresses implemented in external memory Instructions that might inadvert ently cause these addresses to be accessed due to call returns or prefetches should not be located at addresses immediately below the configuration array Use an EJMP instruction five or more addresses below the user configuration array to continue execution in other areas of memory 4 3 DEVICE CONFIGURATION A STEPPING The A stepping version of the MCS 251 microcontroller obtains configuration information from configuration bytes implemented in OTPROM ROM outside the memory address space These configuration bytes are not accessible by user code Space is provided for four configuration bytes at addresses 80H through 83H Two configuration bytes CONFIGO at 80H and CONFIGI at 81H have been i
130. on page 8 16 8 1 TIMER COUNTER OVERVIEW The 8 2515 contains three general purpose 16 bit timer counters Although they are identi fied as timer 0 timer 1 and timer 2 you can independently configure each to operate in a variety of modes as a timer or as an event counter Each timer employs two 8 bit timer registers used separately or in cascade to maintain the count The timer registers and associated control and cap ture registers are implemented as addressable special function registers SFRs Table 8 1 briefly describes the SFRs referred to in this chapter Four of the SFRs provide programmable control of the timers as follows Timer counter mode control register TMOD and timer counter control register TCON control timer 0 and timer 1 Timer counter 2 mode control register T2MOD and timer counter 2 control register T2CON control timer 2 For a map of the SFR address space see Table 3 5 on page 3 17 Table 8 2 describes the external signals referred to in this chapter 8 2 TIMER COUNTER OPERATION The block diagram in Figure 8 1 depicts the basic logic of the timers Here timer registers THx and TLx x 0 1 and 2 connect in cascade to form a 16 bit timer Setting the run control bit TRx turns the timer on by allowing the selected input to increment TLx When TLx overflows it increments THx when THx overflows it sets the timer overflow flag TFx in the TCON or T2CON register Setting the run control bit does
131. or separately as 8 bit timer counters 7 0 High Low Byte of Timer 1 Register Bit Bit Number Mnemonic Function 7 0 TH1 7 0 High byte of the timer 1 timer register TL1 7 0 Low byte of the timer 1 timer register C 37 REGISTERS intel TH2 TL2 Address 2 S CDH TL2 S CCH Reset State 0000 0000B TH2 TL2 Timer Registers These registers operate in cascade to form the 16 bit timer register in timer 2 7 0 High Low Byte of Timer 2 Register Bit Bit Number Mnemonic Function 7 0 TH2 7 0 High byte of the timer 2 timer register TL2 7 0 Low byte of the timer 2 timer register C 38 intel REGISTERS WDTRST Address S A6H Reset State XXXX XXXXB Watchdog Timer Reset Register Writing the two byte sequence 1EH E1H to the WDTRST register clears and enables the hardware WDT The WDTRST register is a write only register Attempts to read it return FFH The WDT itself is not read or write accessible See Watchdog Timer on page 8 16 7 0 WDTRST Contents Write only Bit Bit Number Mnemonic Function 7 0 WDTRST 7 0 Provides user control of the hardware WDT C 39 intel Glossary intel GLOSSARY This glossary defines acronyms abbreviations and terms that have special meaning in this man ual Chapter 1 Guide to this Manual discusses notational conventions and general terminol ogy
132. the currently selected register bank n Byte register index n 0 7 v rrr Binary representation of n Rm Byte register RO R15 of the currently selected register file Rmd Destination register Rms Source register 2 m md ms Byte register index m md ms 0 15 5555 Binary representation of m or md SSSS Binary representation of ms WRj Word register WRO WR2 WR30 of the currently selected register file WRjd Destination register WRjs Source register WRj A memory location 00 0000 00 addressed indirectly through word register WRO WR30 2 WRj Data RAM location 00 0000 00 addressed indirectly dis16 through a word register WR0 WR30 displacement value where the displacement value is from 0 to 64 Kbytes j jd js Word register index j jd js 0 30 tttt Binary representation of j or jd TTTT Binary representation of js DRk Dword register DRO DR4 DR28 DR56 DR60 of the currently selected register file DRkd Destination Register DRks Source Register DRk A memory location 00 0000H FF FFFFH addressed Indirectly through dword register DRO DR28 DR56 DR60 DRk Data RAM location 00 0000H FF FFFFH addressed indirectly dis24 through a dword register DRO DR28 DR56 DR60 displacement value where the displacement value is from 0 to 64 Kbytes k kd ks Dword register index kd ks 0 4 8 28 56 60 uuuu Binary representation of k or kd UUUU Binary representation of ks
133. the instruction ending at location 0122H On chip RAM locations 0AH and OBH contain 01H and 23H respectively After executing the instruction RETI the stack pointer contains 09H and program execution continues at location 0123H intel Bytes States INTR 0 States INTR 1 Encoding Binary Mode Source Mode 1 1 9 9 12 12 0011 0010 Hex Code in Binary Mode Encoding Source Mode Encoding Operation for INTR 0 RETI PC 15 8 SP S P S an 1 lt C 7 0 SP P CS 1 Operation for INTR 1 RETI PC 15 8 SP SP lt SP 1 PC 7 0 SP S P lt SP 1 23 16 lt SP SP lt SP 1 PSW1 lt SP SP lt SP 1 RLA Function Rotate accumulator left INSTRUCTION SET REFERENCE Description Rotates the eight bits in the accumulator one bit to the left Bit 7 is rotated into the bit 0 position Flags CY AC OV Example The accumulator contains OC5H 11000101B After executing the instruction RLA the accumulator contains 8BH 10001011B the CY flag is unaffected Binary Mode Source Mode Bytes 1 1 States 1 1 Encoding 0010 0011 A 121 INSTRUCTION SET REFERENCE Hex Code in Operation RLCA Function Description Flags Example Bytes States Encoding Hex Code in Operation RRA Function Description Fl
134. the operand 8 16 or 32 bit The source operand allows four addressing modes register direct register indirect or immediate CY AC OV N Z The accumulator contains OC9H 11001001B register 2 contains 54H 01010100 and the CY flag is set After executing the instruction SUBB A R2 the accumulator contains 74H 01110100B the CY and AC flags are clear and the OV flag is set Notice that OC9H minus 54H is 75H The difference between this and the above result is due to the CY borrow flag being set before the operation If the state of the carry is not known before starting a single or multiple precision subtraction it should be explicitly cleared by a CLR CY instruction Binary Mode Source Mode 2 2 1 1 1001 0100 immed data A 133 INSTRUCTION SET REFERENCE Hex Code in Operation SUBB A dir8 Bytes States Encoding Hex Code in Operation SUBB A Ri Bytes States Encoding Hex Code in Operation SUBB A Rn Bytes States Encoding Hex Code in Operation A 134 Binary Mode Encoding Source Mode Encoding SUBB lt A CY data Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state 100 1 0101 direct addr Binary Mode Encoding Source Mode Encoding SUBB lt A CY dir8 Bina
135. this bit to select edge triggered high to low for external interrupt 1 Clear this bit to select level triggered active low 1 IEO Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INTO pin Edge or level triggered see ITO Cleared when interrupt is processed if edge triggered 0 ITO Interrupt O Type Control Bit Set this bit to select edge triggered high to low for external interrupt 0 Clear this bit to select level triggered active low C 34 intel REGISTERS TMOD Address 5 89 Reset State 0000 0000B Timer Counter Mode Control Register Contains mode select run control select and counter timer select bits for controlling timer 0 and timer 1 7 0 GATE1 C T1 M11 M01 GATEO C TO M10 Moo Bit Bit Number Mnemonic Function 7 GATE1 Timer 1 Gate When GATE1 0 run control bit TR1 gates the input signal to the timer register When GATE1 1 and TR1 1 external signal INT1 gates the timer input 6 C T1 Timer 1 Counter Timer Select C T1 0 selects timer operation timer 1 counts the divided down system clock C T1 1 selects counter operation timer 1 counts negative transitions on external pin T1 5 4 M11 MO1 Timer 1 Mode Select M11 M01 0 0 Mode 0 8 bit timer counter TH1 with 5 bit prescalar TL1 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TL1 Reload
136. value toggling an output pin when the timer matches a stored value generating a programmable PWM pulse width mod ulator signal on an output pin and serving as a software watchdog timer Chapter 9 mable Counter Array describes this peripheral in detail 2 3 8 Serial I O Port The serial I O port provides one synchronous and three asynchronous communication modes The synchronous mode mode 0 is half duplex the serial port outputs a clock signal on one pin and transmits or receives data on another pin The asynchronous modes modes 1 3 are full duplex 1 the port can send and receive simul taneously Mode 1 uses a serial frame of 10 bits a start bit 8 data bits and a stop bit The baud rate is generated by overflow of timer 1 or timer 2 Modes 2 and 3 use a serial frame of 11 bits a start bit eight data bits a programmable ninth data bit and a stop bit The ninth bit can be used for parity checking or to specify that the frame contains an address and data In mode 2 you can use a baud rate of 1 32 or 1 64 of the oscillator frequency In mode 3 you can use the overflow from timer 1 or timer 2 to determine the baud rate In its synchronous modes modes 1 3 the serial port can operate as a slave in an environment where multiple slaves share a single serial line It can accept a message intended for itself or a message that is being broadcast to all of the slaves and it can ignore a message sent to another
137. value used as the original data is read from the output data latch not the input pin A 51 INSTRUCTION SET REFERENCE Flags Only for instructions with CY as the operand CY AC OV N Z Example Port 1 contains 5BH 01011101B After executing the instruction sequence CPL P1 1 CPL P1 2 port 1 contains 5BH 01011011B Variations CPL bit51 Binary Mode Source Mode Bytes 2 2 States 2t 21 tlf this instruction addresses a port Px x 0 3 add 2 states Encoding 1011 0010 bit addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation CPL bit51 O bit51 CPL CY Binary Mode Source Mode Bytes 1 1 States 1 1 Encoding 1011 0011 Hex Code in Binary Mode Encoding Source Mode Encoding Operation CPL CY CPL bit Binary Mode Source Mode Bytes 4 3 States 4t 3t tlf this instruction addresses a port Px x 0 3 add 2 states A 52 intel Encoding INSTRUCTION SET REFERENCE 1010 1001 1011 0 yyy dir addr Hex Code in Operation DAA Function Description Flags Example Binary Mode A5 Encoding Source Mode Encoding CPL bit lt O bit Decimal adjust accumulator for addition Adjusts the 8 bit value in the accumulator that resulted from the earlier addition of two variables each in packed BCD format producing two 4 b
138. 0 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rm lt Rm WRj SUB Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 1001 1110 uuuu 1011 ssss 0000 A 132 intel Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode A5 Encoding Source Mode Encoding SUB Rm lt Rm DRk SUBB A src byte Function Description Flags Example Variations SUBB A data Bytes States Encoding Subtract with borrow SUBB subtracts the specified variable and the CY flag together from the accumulator leaving the result in the accumulator SUBB sets the CY borrow flag if a borrow is needed for bit 7 and clears CY otherwise If CY was set before executing a SUBB instruction this indicates that a borrow was needed for the previous step in a multiple precision subtraction so the CY flag is subtracted from the accumulator along with the source operand AC is set if a borrow is needed for bit 3 and cleared otherwise OV is set if a borrow is needed into bit 6 but not into bit 7 or into bit 7 but not bit 6 When subtracting signed integers the OV flag indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number Bit 6 and bit 7 in this description refer to the most significant byte of
139. 0 FFFFH If this bit is set mapping does not occur and addresses in the range 00 000 00 access external RAM See Mapping On chip Code Memory to Data Memory EMAP on page 4 20 NOTES 1 Configuration bytes CONFIGO and CONFIG1 define the configuration of the A stepping version of the MCS 251 microcontroller 2 make the 8XC251SB pin compatible with 44 pin PLCC MCS 51 microcontrollers use the following bit values in CONFIG1 1110 0111B 3 Instructions for programming and verifying on chip configuration bytes are given in Chapter 14 Figure 4 6 Configuration Byte CONFIG1 intel DEVICE CONFIGURATION 4 6 CONFIGURING THE EXTERNAL MEMORY INTERFACE This section describes the configuration options that affect the external memory interface The configuration bits described here determine the following interface features page mode nonpage mode PAGE the number of external address pins 16 17 or 18 RD1 0 the memory regions assigned to the read signals RD and PSEN RD 1 0 the external wait states WSA1 0 WSB1 0 WSA WSB XALE mapping a portion of on chip code memory to data memory NOTE This section applies to both the A stepping of the 8XC251SB and the B stepping of the 8 2515 Differences between the steppings are noted in the text 4 6 4 Page Mode and Nonpage Mode PAGEZ The PAGE bit UCONFIGO 1 and CONFIGO 1 selects page mode or nonpage mode code f
140. 00 2 SRA WRj E j 2 0100 3 SRL Rm 1 E m 0000 4 SRL WRj 1 E j 2 0100 5 SLL Rm E m 0000 6 SLL WRj E 2 0100 intel INSTRUCTION SET REFERENCE A 3 INSTRUCTION SET SUMMARY This section contains tables that summarize the instruction set For each instruction there is a short description its length in bytes and its execution time in states NOTE The instruction execution times given in the tables are for code executing from on chip code memory and for data that is read from and written to on chip RAM Execution times are increased by executing code from external memory accessing peripheral SFRs accessing data in external memory using a wait state or extending the ALE pulse For some instructions accessing the port SFRs Px x 0 3 increases the execution time These cases are noted individually in the tables A 3 1 Execution Times for Instructions that Access the Port SFRs The execution times for some instructions increase when the instruction accesses a port SFR Px x 0 3 as opposed to any other SFR Table A 18 lists these instructions and the execution times for Case 0 Case 0 Code executes from on chip ROM OTPROM EPROM and accesses locations in on chip data RAM The port SFRs are not accessed In Cases 1 4 the instructions access a port SFR Case l Code executes from on chip ROM OTPROM EPROM and accesses a port SFR Case 2 Code executes from external memory with no w
141. 00 0000H 00 007FH as both bytes and words and addresses the SFRs dir8 5 080 5 1 as bytes only See the note on page 5 5 regarding SFRs in the MCS 251 architecture The 16 bit direct mode addresses both bytes and words in memory dir16 00 0000H 00 FFFFH MCS 51 architecture The 8 bit direct mode addresses 256 bytes of on chip RAM dir8 00H 7FH as bytes only and the SFRs dir8 S0H FFH as bytes only 5 5 PROGRAMMING intel Table 5 3 Addressing Modes for Data Instructions in the MCS 51 Architecture Address Range of Assembly Language Mode Operand Reference RO R7 Register Dude Bank selected by PSW Immediate Operand in Instruction data 400H 4FFH 00H 7FH dir8 00H 7FH On chip RAM Direct dir8 80H FFH BERS or SFR mnemonic ain aadtess Accesses on chip RAM or the 00H FFH ORO R1 lowest 256 bytes of external data memory MOVX Indirect Accesses external data 0000H FFFFH DPTR A DPTR memory MOVX E Accesses region FF of code 0000H FFFFH A DPTR A PC memory MOVC 5 3 1 4 Indirect In arithmetic and logical instructions that use indirect addressing the source operand is always a byte and the destination is either the accumulator or a byte register RO R15 The source address is a byte word or dword The two architectures do indirect addressing via different registers MCS 251 architecture Memory is indirectly addressed via word
142. 0000 nennen 5 12 5 5 1 Addressing Modes for Control Instructions 5 13 5 5 2 gt Gonditional Jumps er eel eal on a a 5 14 5 5 3 Unconditional JUMPS 22 5 15 5 5 4 Calls and Retutris ue ae desde D 5 15 5 6 PROGRAM STATUS WORDS nennen 5 16 CHAPTER 6 INTERRUPT SYSTEM 6 1 OMERVIEW OCS 52i aiti tuno bind hbnettdbt b tes 6 1 6 2 8XC251SA SB SP SQ INTERRUPT SOURCES eee 6 3 6 2 1 External Interrupts 2 6 3 6 2 22 Timer nterr pts eie ee eed emp Prset 6 4 6 3 PROGRAMMABLE COUNTER ARRAY 6 5 6 4 SERIAL PORT INTERRUPT etre rue reete ena aiid de dog iu 6 5 6 5 INTERRUPT ENABLE cnet eene ceto io 6 5 6 6 INTERRUPT PRIORITIES 2 erre idet p mre Cre eee 6 6 6 7 INTERRUPT PROGESSING eii cit me tU Ett e A eo tg Sites 6 9 6 7 1 Minimum Fixed Interrupt Time meer 6 10 6 7 2 Variable Interrupt Parameters eese nennen emen nnne 6 10 6 7 2 1 Response Time Variables emen 6 10 6 7 2 2 Computation of Worst case Latency With Variables 6 12 6 7 22 Latency Calculations ii enge reed ete encre eoa 6 13 67 24 Blockinig Conditions
143. 0011 011i A 33 INSTRUCTION SET REFERENCE Hex Code in Operation ADDC A Rn Bytes States Encoding Hex Code in Operation AJMP addr11 Function Description Flags Example Bytes States Encoding Hex Code in Operation A 34 Binary Mode Encoding Source Mode A5 Encoding ADDC lt A CY Ri Binary Mode Source Mode 1 2 1 2 0011 irrr Binary Mode Encoding Source Mode A5 Encoding ADDC A A CY Rn Absolute jump Transfers program execution to the specified address which is formed at run time by concatenating the upper five bits of the PC after incrementing the PC twice opcode bits 7 5 and the second byte of the instruction The destination must therefore be within the same 2 Kbyte page of program memory as the first byte of the instruction following AJMP OV The label JMPADR is at program memory locat AJMP JMPADR at location 0345H the PC contains 0123H Binary Mode Source Mode 2 2 3 3 a10 a9 a8 0 0001 a7 a6 a5 a4 a3 a2 a1 a0 Binary Mode Encoding Source Mode Encoding AJMP PC PC 2 PC 10 0 page address ion 0123H After executing the instruction intel INSTRUCTION SET REFERENCE ANL lt dest gt lt src gt Function Description Flags Example Variations ANL dir8 A
144. 01 Figure 8 9 Timer 2 Auto Reload Mode DCEN 1 8 13 TIMER COUNTERS AND WATCHDOG TIMER intel 8 6 3 Baud Rate Generator Mode This mode configures timer 2 as a baud rate generator for use with the serial port Select this mode by setting the RCLK and or TCLK bits in T2CON See Table 8 3 on page 8 15 For details re garding this mode of operation refer to Baud Rates on page 10 10 8 6 4 Mode In the clock out mode timer 2 functions as a 50 duty cycle variable frequency clock Figure 8 10 The input clock increments TLO at frequency Fosc 2 The timer repeatedly counts to over flow from a preloaded value At overflow the contents of the RCAP2H and RCAP2L registers are loaded into TH2 TL2 In this mode timer 2 overflows do not generate interrupts The formula gives the clock out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers Clock out Frequency NEN 4 x 65535 RCAP2H RCAP2L For a 16 MHz system clock timer 2 has a programmable frequency range of 61 Hz to 4 MHz The generated clock signal is brought out to the T2 pin Timer 2 is programmed for the clock out mode as follows 1 Set the T2OE bit in T2MOD This gates the timer register overflow to the 2 counter 2 Clear the C T2 bit in T2CON to select Fo 2 as the timer input signal This also gates the output of the 2 counter to pin T2 3 Determine the 16 bit reloa
145. 01 Broadcast 1111 1X11 For Slaves and B bit 2 is a don t care bit for Slave C bit 2 is set To communicate with all of the slaves the master must send an address FFH To communicate with Slaves A and B but not Slave C the master can send an address FBH 10 9 SERIAL I O PORT intel 10 5 3 Reset Addresses On reset the SADDR and SADEN registers are initialized to OOH i e the given and broadcast addresses are XXXX XXXX all don t care bits This ensures that the serial port is backwards compatible with MCS9 51 microcontrollers that do not support automatic address recognition 10 6 BAUD RATES You must select the baud rate for the serial port transmitter and receiver when operating in modes 1 2 and 3 The baud rate is preset for mode 0 In its asynchronous modes the serial port can transmit and receive simultaneously Depending on the mode the transmission and reception rates can be the same or different Table 10 3 summarizes the baud rates that can be used for the four serial I O modes Table 10 3 Summary of Baud Rates Mode No of Send and Receive Send and Receive Baud Rates at the Same Rate at Different Rates 0 1 N A N A 1 Many Yes Yes 2 2 Yes 3 Many Yes Yes Baud rates are determined by overflow of timer 1 and or timer 2 10 6 1 Baud Rate for Mode 0 The baud rate for mode 0 is fixed at Fosc 12 10 6 2 Baud Rates for Mode 2 Mode 2 has two baud rates w
146. 010 0000 bit addr intel INSTRUCTION SET REFERENCE Hex Code in Binary Mode Encoding Source Mode Encoding Operation ORL CY lt CY bit51 ORL CY bit Binary Mode Source Mode Bytes 4 3 States 3t 2t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1010 1001 0111 0 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL CY lt CY V bit ORL CY bit Binary Mode Source Mode Bytes 4 3 States 3t 2t tlf this instruction addresses a port Px x 0 3 1 state Encoding 1010 1001 1110 0 yyy direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL CY lt CY V bit POP src Function Pop from stack Description Reads the contents of the on chip RAM location addressed by the stack pointer then decrements the stack pointer by one The value read at the original RAM location is transferred to the newly addressed location which can be 8 bit or 16 bit Flags CY AC OV N 2 115 INSTRUCTION SET REFERENCE intel Example The stack pointer contains 32H and on chip RAM locations 30H through 32H contain 01H 23H and 20H respectively After executing the instruction sequence POP DPH POP DPL the stack pointer contains 30H and the data pointer contains 0123H After ex
147. 1 5 RCLK Receive Clock Bit Selects timer 2 overflow pulses RCLK 1 or timer 1 overflow pulses RCLK 0 as the baud rate generator for serial port modes 1 and 3 4 TCLK Transmit Clock Bit Selects timer 2 overflow pulses TCLK 1 or timer 1 overflow pulses TCLK 0 as the baud rate generator for serial port modes 1 and 3 3 EXEN2 Timer 2 External Enable Bit Setting EXEN2 causes a capture or reload to occur as a result of a negative transition on T2EX unless timer 2 is being used as the baud rate generator for the serial port Clearing EXEN2 causes timer 2 to ignore events at T2EX 2 TR2 Timer 2 Run Control Bit Setting this bit starts the timer 1 C T2 Timer 2 Counter Timer Select C T2 0 selects timer operation timer 2 counts the divided down system clock C T2 1 selects counter operation timer 2 counts negative transitions on external pin T2 0 CP RL2 Capture Reload Bit When set captures occur on negative transitions at T2EX if EXEN2 1 When cleared auto reloads occur on timer 2 overflows or negative transitions at T2EX if EXEN2 1 The CP RL2 bit is ignored and timer 2 forced to auto reload on timer 2 overflow if RCLK 1 or TCLK 1 C 32 intel REGISTERS T2MOD Address S C9H Reset State XXXX XX00B Timer 2 Mode Control Register Contains the timer 2 down count enable and clock out enable bits for timer 2
148. 1 to a reserved bit The term set refers to the value of a bit or the act of giving it a value If a bit is set its value is 1 setting a bit gives it a 1 value Special function register A method for converting data to a larger format by filling the extra bit positions with the value of the sign This conversion preserves the positive or negative value of signed integers Current flowing into a device to ground Always a positive value The ability of an MCS 251 microcontroller to execute recompiled source code written for an MCS 51 micro controller Current flowing out of a device from Always a negative value An operating mode that is selected by a configuration bit In source mode an MCS 251 microcontroller can execute recompiled source code written for an MCS 51 microcontroller In source mode the MCS 251 microcontroller cannot execute unmodified binary code written for an MCS 51 microcontroller See binary mode Stack pointer Extended stack pointer Glossary 5 GLOSSARY state time or state UART WDT word wraparound Glossary 6 intel The basic time unit of the device the combined period of the two internal timing signals PH1 and 2 The internal clock generator produces PH1 and PH2 by halving the frequency of the signal on XTALI1 With a 16 MHz crystal one state time equals 125 ns Because the device can operate at many frequencies this manual defines time
149. 1 0 1 selects edge triggered high to low IT1 0 0 selects level triggered active low INT 1 02 also serves as external run control for timer 1 0 when selected by TCON bits GATE1 0 T1 0 Timer 1 0 External Clock Inputs When timer 1 0 operates as P3 5 4 counter a falling edge on the T1 0 pin increments the count TIMER COUNTERS AND WATCHDOG TIMER intel 8 3 0 Timer 0 functions as either a timer or event counter in four modes of operation Figures 8 2 8 3 and 8 4 show the logical configuration of each mode Timer 0 is controlled by the four low order bits of the TMOD register Figure 8 5 and bits 5 4 1 and 0 of the TCON register Figure 8 6 The TMOD register selects the method of timer gating GATEO timer or counter operation T CO and mode of operation M10 and The TCON register provides timer 0 control functions overflow flag run control TRO inter rupt flag and interrupt type control ITO For normal timer operation GATEO 0 setting TRO allows TLO to be incremented by the se lected input Setting GATEO and TRO allows external pin INTO to control timer operation This setup can be used to make pulse width measurements See Pulse Width Measurements on page 8 10 Timer 0 overflow count rolls over from all 1s to all Os sets the flag generating an interrupt request 8 3 1 Mode 0 13 bit Timer Mode 0 configures timer 0 as an 13
150. 1 4 1 How to Use Intel s FaxBack Service sssssssseeeeeeeeeen enne 1 7 1 4 2 How to Use Intel s Application BBS 2 1 8 1 4 3 How to Find the Latest ADBUILDER Files and Hypertext Manuals and Data Sheets on the BBS 1 9 CHAPTER 2 ARCHITECTURAL OVERVIEW 2 1 8XC251SA SB SP SQ 4 0000400 4 rennen nen 2 3 2 2 MCS 251 MICROCONTROLLER CORE sese 2 4 2 2 1 CPUS Z 2 5 2 222 Clock and Reset Unit e Datei dete cedere 2 6 2 2 3 Interrupt Hardlet ttt oret bri NE EO ES DI Eee 2 7 2 24 On chip Code Memory 40 4 00111 enne nnne enses entente nente en 2 7 2 23 5 On chip ciere cet eet te i das erii t dea donee dsr 2 7 2 3 ON GHIP PERIPHERALS 1 2 tt tete Ee odere eg de 2 7 2 3 1 Timer Counters and Watchdog Timer 2 7 2 3 2 Programmable Counter Array 2 8 2 9 9 Seriall O BOtt i eat ee ae Edd reb eb e bd e D HERO TE 2 8 2 4 SUMMARY OF A STEPPING DIFFERENCES essen 2 9 2 4 1 Package Options ee t teer ht eit e Pp UTERE E nal 2 9 2 4 2 Memory Address Space 44422022244 0 nnne ernst nnns 2 9 2 52 44 On chip Memory c i aie 2 9 24 2 2 Exte
151. 10 The serial port signals are defined in Table 10 1 and the serial port special function registers are described in Table 10 2 Figure 10 1 is a block diagram of the serial port For the three asynchronous modes the UART transmits on the TXD pin and receives on the RXD pin For the synchronous mode mode 0 the UART outputs a clock signal on the TXD pin and sends and receives messages on the RXD pin Figure 10 1 The SBUF register which holds re ceived bytes and bytes to be transmitted actually consists of two physically different registers To send software writes a byte to SBUF to receive software reads SBUF The receive shift reg ister allows reception of a second byte before the first byte has been read from SBUF However if software has not read the first byte by the time the second byte is received the second byte will overwrite the first The UART sets interrupt bits TI and RI on transmission and reception respec tively These two bits share a single interrupt request and interrupt vector Table 10 1 Serial Port Signals Function Multiplexed Description With TXD Transmit Data In mode 0 TXD transmits the clock signal In P3 1 modes 1 2 and 3 TXD transmits serial data RXD Receive Data In mode 0 RXD transmits and receives serial P3 0 data In modes 1 2 and 3 RXD receives serial data 10 1 SERIAL I O PORT Table 10 2 Serial Port Special Function Registers
152. 10 7 10 54 Given Address casse Rede eet eel Needs 10 8 10 5 2 Broadcast Address ciere oe em ch d ba teer dette 10 9 10 5 3 Reset Addresses eee eee n tust i 10 10 10 6 BAUD RATES ic cete trt e eet desereret ere aerae dt e uer vae de 10 10 10 6 1 Rate for Mode Q neon eC eee e dede iets 10 10 10 6 2 Baud Rates for Mode 2 10 10 10 6 3 Baud Rates for Modes 1 and 3 10 10 10 6 3 1 Timer 1 Generated Baud Rates Modes 1 3 10 11 10 6 3 2 Selecting Timer 1 as the Baud Rate Generator 10 11 10 6 3 3 Timer 2 Generated Baud Rates Modes 1 3 10 12 10 6 3 4 Selecting Timer 2 as the Baud Rate Generator 10 12 CHAPTER 11 MINIMUM HARDWARE SETUP 11 1 MINIMUM HARDWARE SETOUP ccccccccsceeeseeceeeeeeeeeeeeeeaeeessaeeesecaeessceeessneeeseeees 11 1 11 2 ELECTRICAL ENVIRONMENT 440004002 22 066000 00000008000000000000000000000 nnne 11 2 11 2 1 Power and Ground Pitseum t NR ed oh gre 11 2 11 2 2 nused Pins SIBI enu 11 2 11 2 8 Noise Consideraltioris n niea aisi a mute 11 2 11 3 GEOGK SOURGES s iiec uiui nu 11 3 11 8 1 On chip Oscillator 11 3 11 3 2 On chip Oscill
153. 11 C 22 intel REGISTERS PSW1 Address S D1H Reset State 0000 0000B Program Status Word 1 PSW1 contains bits that reflect the results of operations and bits that select the register bank for registers RO R7 d 0 RS1 RSO OV 7 Z Bit Bit f Number Mnemonic Function 7 Carry Flag Identical to the CY bit in the PSW register on page C 22 6 AC Auxiliary Carry Flag Identical to the AC bit in the PSW register on page C 22 5 N Negative Flag This bit is set if the result of the last logical or arithmetic operation was negative Otherwise it is cleared 4 3 RS1 0 Register Bank Select Bits 0 and 1 Identical to the RS1 0 bits in the PSW register on page C 22 2 OV Overflow Flag Identical to the OV bit in the PSW register page C 22 1 2 Zero Flag This flag is set if the result of the last logical or arithmetic operation is zero Otherwise it is cleared 0 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit C 23 REGISTERS intel RCAP2H RCAP2L Address RCAP2H S CBH RCAP2L S CAH Reset State 0000 0000B Timer 2 Reload Capture Registers This register pair stores 16 bit values to be loaded into or captured from the timer register TH2 TL2 in timer 2 7 0 High Low Byte of Timer 2 Reload Capture Value Bit Bit Number Mnemonic Function 7 0
154. 2 Tun ALE Low to RD or PSEN Low Time after ALE goes high until RD or PSEN goes 1 low TninH RD or PSEN Pulse Width Length of time RD or PSEN is asserted 3 RD PSEN High to ALE Asserted Data Time after RD goes high until the next ALE 1 pulse goes high RD PSEN Low to Address Float Time after RD goes low until the 8 2515 stops driving the address on the bus TavLL Address Valid to ALE Low Length of time the lower byte of the address is valid on port 2 0 before ALE goes low ALE High to Address Hold Length of time the 8XC251Sx holds the lower byte of the 2 address on the bus port 0 after ALE goes high Tuax Address Hold after ALE Low Length of time the 8 2515 holds the lower byte of the address on the bus port 0 after ALE goes low TavRL Address Valid to RD or PSEN Low Length of time the lower byte of the address is 12 valid on the bus port 0 before RD or PSEN goes low WR Pulse Width Length of time is asserted 3 WR High to ALE High Time after WR goes high until the next ALE pulse goes high TavwL1 Address port 0 Valid to WR Low Length of time that the 83XC251Sx drives the 2 address onto the bus port 0 before WR goes low TavwL2 Address port 2 Valid to WR Low Length of time that the 83XC251Sx drives the 2 address onto the bus port 2 before WR goes low Address Hold after WR High Time the 8X
155. 3 wait states for RD WR PSEN For A step ping devices configuration bites WSA and WSB specify 0 or wait states for RD WR PSEN The XALE configuration bit specifies or 1 wait state for ALE See Wait State Configuration Bits on page 4 16 You can also configure the chip to use both types of wait states Accesses to on chip code and data memory always use zero wait states 13 3 1 Extending RD WR PSEN Figure 13 8 shows the nonpage mode code fetch bus cycle with one RD PSEN wait state The wait state extends the bus cycle to three states Figure 13 9 shows the nonpage mode data write bus cycle with one WR wait state The wait state extends the bus cycle to four states The wave forms in Figure 13 9 also apply to the nonpage mode data read external bus cycle if RD PSEN is substituted for WR EXTERNAL MEMORY INTERFACE RD PSEN A17 A16 A15 8 A17 A16 P2 State 1 ALE i State 2 State 3 A2812 04 Figure 13 8 External Bus Cycle Code Fetch with One RD PSEN Wait State Nonpage Mode XTAL ALE WR PO A17 A16 P2 State 1 State 2 State 3 A17 A16 A15 8 State 4 A4174 02 Figure 13 9 External Bus Cycle Data Write with One WR Wait State Nonpage Mode 13 9 EXTERNAL MEMORY INTERFACE intel 13 3 2 Extending ALE Figure 13 10 shows the nonpage mode code fetch external bus cycle with ALE extended The wait state extends the bus
156. 4 5 intel INSTRUCTION SET REFERENCE Encoding 1011 1110 uuuu 1000 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP DRk 0data16 CMP DRk 1data16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 1011 1110 uuuu 1100 data hi hi Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP 1data16 8 Binary Mode Source Mode Bytes 4 3 States 3t 2t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1011 1110 ssss 0001 dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP Rm dir8 CMP WRi dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 1011 1110 tttt 0101 dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding A 49 INSTRUCTION SET REFERENCE Operation CMP WRj dir8 CMP 16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 1011 1110 ssss 0011 dir addr dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP Rm dir16 CMP WRij dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encodin
157. 4 4 4 7 3 6 A 69 INSTRUCTION SET REFERENCE intel Encoding 1010 1001 0001 0 yyy direct addr rel addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation JBC PC PC 3 IF bit51 1 THEN bit51 0 PC PC rel JC rel Function Jump if carry is set Description If the CY flag is set branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice Flags CY AC OV N E me Example The CY flag is clear After the instruction sequence JC LABEL1 CPL CY JC LABEL 2 the CY flag is set and program execution continues at label LABEL2 Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 2 2 2 2 States 1 4 1 4 Encoding 0100 0000 rel addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation JC PC PC 2 IF CY 1 A 70 THEN PC lt PC rel intel JE rel Function Description Flags Example Bytes States Encoding Hex Code in Operation JG rel Function Description Flags INSTRUCTION SET REFERENCE Jump if equal If the Z flag is set branch to the address specified otherwise proceed with the next instruction The bra
158. 5 0 A 12 A 19 Summary of Add and Subtract A 14 A 20 Summary of Compare A 15 A 21 Summary of Increment and Decrement Instructions A 16 A 22 Summary of Multiply Divide and i AG eH 16 23 Summary of Logical Instructions LER EA A 24 Summary of Move Instructions 222 25 Summary of Exchange Push and Pop Instructions 22 26 Summary of Bit A 23 A 27 Summary of Control A 24 A 28 Flag Symbols NS CMS B 1 Signals Arranged by Functional Categories X 1 B 2 Description of Columns of Table B 3 Midis va intel CONTENTS TABLES Table Page B 3 Signal Descriptions etii vienne B 4 Memory Signal Selections RD1 20 B stepping B 5 Memory Signal Selections RD1 0 A stepping Bed C 1 8XC251SA SB SP SQ Special Function Registers intel Guide to This Manual intel CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 8XC251SA SB SP SQt embedded microcontroller which is the first member of the Intel MCS 251 microcont
159. 5 Encoding DJNZ PC PC 2 Rn lt Rn 1 IF Rn gt 0 or Rn 0 THEN PC PC rel Extended call Calls a subroutine located at the specified address The instruction adds four to the program counter to generate the address of the next instruction and then pushes the 24 bit result onto the stack high byte first incrementing the stack pointer by three The 8 bits of the high word and the 16 bits of the low word of the PC are then loaded respectively with the second third and fourth bytes of the ECALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 16 Mbyte memory space CY AC OV N 2 The stack pointer contains 07H and the label SUBRTN is assigned to program memory location 123456H After executing the instruction ECALL SUBRTN at location 012345H SP contains OAH on chip RAM locations 08H 09H and OAH contain 01H 23H and 45H respectively and the PC contains 123456H A 61 INSTRUCTION SET REFERENCE Variations ECALL addr24 Binary Mode Source Mode Bytes 5 4 States 14 13 Encoding 1001 1010 addr23 addr15 addr8 addr7 addr0 addr16 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ECALL PC PC 4 SP lt SP 1 SP lt 23 16 SP lt SP 1 SP 15 8 S
160. 6 bit remainder These instructions operate on pairs of byte registers Rmd Rms word registers WRjd WRjs or the accumulator and B register A B For 8 bit register multiplies the result is stored in the word register that contains the first operand register For example the product from an instruction MUL R3 R8 is stored in WR2 Similarly for 16 bit multiplies the result is stored in the dword register that contains the first operand register For example the product from the instruction MUL WR6 WR18 is stored in For 8 bit divides the operands are byte registers The result is stored in the word register that con tains the first operand register The quotient is stored in the lower byte and the remainder 15 stored in the higher byte A 16 bit divide is similar The first operand is a word register and the result is stored in the double word register that contains that word register If the second operand the di visor is zero the overflow flag OV is set and the other bits in PSW and PSW1 are meaningless 5 3 3 Logical Instructions The MCS 251 architecture provides a set of instructions that perform logical operations The ANL ORL and XRL logical AND logical OR and logical exclusive OR instructions operate on bytes and words that are accessed via several addressing modes Table A 23 on page A 17 A byte register word register or the accumulator can be logically combined with a register im mediate data or data tha
161. 7 0 for the external bus ALE O Address Latch Enable ALE signals the start of an external bus cycle PROG and indicates that valid address information is available on lines A15 8 and AD7 0 An external latch can use ALE to demultiplex the address from the address data bus EA External Access Directs program memory accesses to on chip or off Vpp chip code memory For EA strapped to ground all program memory accesses are off chip For EA strapped to Vec an access is to on chip OTPROM ROM if the address is within the range of the on chip OTPROM ROM otherwise the access is off chip The value of EA is latched at reset For a ROMless part must be strapped to ground PSEN O Program Store Enable Read signal output This output is asserted for a memory address range that depends on bits RDO and RD1 in configuration byte CONFIG1 see also RD RD1 RDO Address Range for Assertion 0 0 All addresses 0 1 Alladdresses 1 0 All addresses 1 1 Alladdresses gt 80 0000H RD Read or 17th Address Bit A16 Read signal output to external data P3 7 A16 memory or 17th external address bit 16 depending on the values of bits RDO and RD1 in configuration byte CONFIG1 See also PSEN RD1 RDO Function 0 0 The pin functions as A16 only 0 1 The pin functions as A16 only 1 0 The pin functions as P3 7 only 1 1 RD asserted for reads at all addresses lt 7F FFFFH WR O Write Write signal output to external memory For configurati
162. 8 3 17 3 18 7 2 C 17 P1 3 17 3 18 7 2 C 18 P2 3 17 3 18 7 2 C 19 P3 3 17 3 18 7 2 C 20 Page mode 2 5 address access time 13 6 bus cycles See External bus cycles page mode configuration 4 11 design example 13 15 13 24 port pin status 13 12 PAGE bit 4 11 Parity See P bit PCA compare capture modules 9 1 idle mode 12 4 pulse width modulation 9 11 SFRs 3 19 timer counter 9 1 watchdog timer 9 1 9 9 PCON 3 17 3 18 10 7 12 1 12 2 12 5 C21 idle mode 12 4 powerdown mode 12 6 reset 11 6 Peripheral cycle 2 6 Phase 1 and phase 2 2 6 Index 5 Pin conditions 12 3 Pins unused inputs 11 2 Pipeline 2 5 POP instruction 3 15 5 10 A 22 Port 0 7 2 and top of on chip code memory 14 2 pullups 7 7 structure 7 3 See also External bus Port 1 7 2 structure 7 3 Port 2 7 2 and top of on chip code memory 14 2 structure 7 4 See also External bus Port 3 7 2 structure 7 3 Ports at power on 11 7 exiting idle mode 12 5 exiting powerdown mode 12 5 extended execution times 5 1 A 1 A 11 programming and verifying nonvolatile memory 14 3 14 6 14 7 Power supply 11 2 Powerdown mode 2 4 12 1 12 5 12 6 accidental entry 12 4 entering 12 6 exiting 11 6 12 6 external bus 13 3 PROG 14 1 Program status word See PSW PSWI PSEN caution 11 7 description 13 2 idle mode 12 4 programming and verifying nonvolatile memory 14 3 regions for asserting 4 11 PSW
163. 8 Bits Count Interrupt Request CCAPMx Mode Register Reset Write to CCAPxL X Don t Care x 0 1 2 3 4 For software timer mode set ECOMx and MATx For high speed output mode set ECOMx MATx and TOGx A4164 01 Write to CCAPxH Figure 9 3 PCA Software Timer and High speed Output Modes 9 3 4 High speed Output Mode The high speed output mode Figure 9 3 generates an output signal by toggling the module s I O pin CEXx when a match occurs This provides greater accuracy than toggling pins in software because the toggle occurs before the interrupt request is serviced Thus interrupt response time does not affect the accuracy of the output To program a compare capture module for the high speed output mode set the ECOMx MATx TOGx bits in the module s CCAPMXx register Table 9 3 on page 9 15 lists the bit combinations for selecting module modes match between the PCA timer counter and the compare capture registers CCAPxH CCAPxL toggles the CEXx pin and sets the module s compare capture flag CCFx in the CCON register By setting or clearing the CEXx pin in software the user selects whether the match toggles the pin from low to high or vice versa 9 8 intel PROGRAMMABLE COUNTER ARRAY The user also has the option of generating an interrupt request when the match occurs by setting the corresponding interrupt enable bit ECCFx in the CCAPMx register Since hardware does not
164. 8H and FF FFF9H which appear on the microcontroller external address bus A17 A16 A15 0 as shown in this table See Figure 4 2 2 upper six bytes of the configuration array are reserved for future use 8 Kbytes 1FF8H 7 DEVICE CONFIGURATION 16 Kbytes 32 Kbytes 2 64 Kbytes FFF8H E 7FF9H x 3FF8H F 128K 1 FFF9H Kbytes Y 1 FFF8H E This figure shows the addresses of configuration bytes UCONFIG1 and UCONFIGO in external memory for several memory implementations For EA 0 the 8XC251Sx obtains configuration information from configuration bytes in external memory using internal addresses FF FFF8H and FF FFF9H In external memory the eight byte configuration array is located at the highest addresses implemented 256K 296 Kbytes 3 XxFFFH XxFFEH XxFFDH XxFFCH XxFFBH XxFF9H UCONFIG1 x Detail Configuration array in external memory A4236 01 Figure 4 2 B stepping Configuration Array External 4 5 DEVICE CONFIGURATION A STEPPING COMPATIBLE To configure the B stepping 8XC251SB microcontroller to function as an A stepping 8XC251SB specify the configuration using UCONFIGI 0 with the following restrictions e WSAILtt 1 Use WSAO to replace WSA to select 0 or 1 wait states for RD WR3 PSEN for accesses to external memory via memory regions 00 FE FF WSB1 1 Program WSBO WSB to select 0 or wa
165. AC OV N 2 The instruction TRAP causes an interrupt call to location OFF007BH during normal operation A 135 INSTRUCTION SET REFERENCE Binary Mode Source Mode Bytes 2 1 States 2 bytes 11 10 States 4 bytes 16 15 Encoding 1011 1001 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation TRAP SP SP 2 SP PC XCH A lt byte gt Function Description Flags Example Variations 8 Bytes States Encoding Hex Code in Operation A 136 PC lt OFF007BH Exchange accumulator with byte variable Loads the accumulator with the contents of the specified variable at the same time writing the original accumulator contents to the specified variable The source destination operand can use register direct or register indirect addressing CY AC OV N 2 RO contains the address 20H the accumulator contains 00111111B and on chip RAM location 20H contains 75H 01110101B After executing the instruction A GRO RAM location 20H contains SFH 00111111B and the accumulator contains 75H 01110101B Binary Mode Source Mode 2 2 3t 3t tlf this instruction addresses a port Px x 0 3 add 2 states 1100 0101 direct addr Binary Mode Encoding Source Mode Encoding XCH gt dir8 intel A Ri Bytes States
166. ACC Register R11 Figure 5 2 Program Status Word Register intel PROGRAMMING PSW1 Address S D1H Reset State 0000 0000B 0 RS1 RSO OV 7 Nomea Function 7 Carry Flag Identical to the CY bit in the PSW register Figure 5 2 on page 5 18 6 AC Auxiliary Carry Flag Identical to the AC bit in the PSW register Figure 5 2 on page 5 18 5 N Negative Flag This bit is set if the result of the last logical or arithmetic operation was negative i e bit 15 1 Otherwise it is cleared 4 3 RS1 0 Register Bank Select Bits 0 and 1 Identical to the RS1 0 bits in the PSW register Figure 5 2 on page 5 18 2 OV Overflow Flag Identical to the OV bit in the PSW register Figure 5 2 on page 5 18 1 2 Zero Flag This flag is set if the result of the last logical or arithmetic operation is zero Otherwise it is cleared 0 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit Figure 5 3 Program Status Word 1 Register intel Interrupt System intel CHAPTER 6 INTERRUPT SYSTEM 6 1 OVERVIEW The 8XC251Sx like other control oriented computer architectures employs a program interrupt method This operation branches to a subroutine and performs some service in response to the interrupt When the subroutine completes execution resumes at the point where th
167. AM SFRs MCS 251 Architecture 20 7 defined SFRs SFRs with addresses ending in OH or 8H MCS 51 Architecture 20 2 80H 88H 90H 98H 5 11 PROGRAMMING intel Table 5 7 lists the addressing modes for bit insructions and Table A 26 on page A 23 summarizes the bit instructions Bit denotes a bit that is addressed by a new instruction in the MCS 251 ar chitecture and bit51 denotes a bit that is addressed by an instruction in MCS 51 architec ture Table 5 6 Addressing Two Sample Bits Addressing MCS 51 MCS 251 Location Mode Architecture Architecture Register Name RAMREG 5 RAMREG 5 Register Address 23H 5 23H 5 On chip RAM Bit Name RAMBIT RAMBIT Bit Address 1DH NA Register Name TCON 2 TCON 2 Register Address 88 2H 88 2H SFR Bit Name IT1 IT1 Bit Address 8A NA Table 5 7 Addressing Modes for Bit Instructions Architecture Variants Bit Address Memory SFR Address Comments MCS 251 Memory NA 20H 0 7FH 7 Architecture bit SFR NA All defined SFRs Memory 00H 7FH 20H 0 7FH 7 AR S SFR t defined Architecture ce 5 are not define bit51 SFR 80H F8H 55 280 at all bit addressable Tuus locations 5 5 CONTROL INSTRUCTIONS Control instructions instructions that change program flow include calls returns and condi tional and unconditional jumps see Table A 27 on page A 24 I
168. B 2 Signature bytes setup for verifying 14 5 values 14 10 verifying 14 1 14 10 SJMP instruction 5 15 A 24 SLL instruction 5 9 A 17 Software application notes 1 6 Source register 5 3 SP 3 15 3 17 3 18 C 30 Special function registers See SFRs SPH 3 15 3 17 3 18 C 31 SPX 3 13 3 15 SRA instruction 5 9 A 18 SRL instruction 5 9 A 18 State time 2 6 SUB instruction 5 8 A 14 SUBB instruction 5 8 A 14 SWAP instruction 5 9 A 18 T T1 0 7 1 8 3 T2 7 1 8 3 T2CON 3 17 3 19 8 1 8 2 8 10 8 17 10 13 C 32 baud rate generator 10 12 T2EX 7 1 8 3 8 11 10 12 T2MOD 3 17 3 19 8 1 8 2 8 10 8 16 C 33 Target address 5 4 TCON 3 17 3 19 8 1 8 2 8 4 8 6 8 8 C 34 interrupts 6 1 Index 7 TH2 TL2 baud rate generator 10 14 baud rate generator 10 12 THx TLx x 0 1 2 3 17 3 19 8 2 C 36 C 37 C 38 Timer 0 8 4 8 8 applications 8 9 auto reload 8 5 interrupt 8 4 mode 0 8 4 mode 1 8 5 mode 2 8 5 mode 3 8 5 pulse width measurements 8 10 Timer 1 applications 8 9 auto reload 8 9 baud rate generator 8 6 interrupt 8 6 mode 0 8 6 mode 1 8 9 mode 2 8 9 mode 3 8 9 pulse width measurements 8 10 Timer 2 8 10 8 17 auto reload mode 8 12 baud rate generator 8 14 capture mode 8 11 clock out mode 8 14 interrupt 8 11 mode select 8 15 Timer counters 8 1 8 17 external input sampling 8 3 internal clock 8 3 inter
169. Binary Mode A5 Encoding Source Mode Encoding Operation ORL WRj lt WRj V data16 ORL 8 Binary Mode Source Mode Bytes 4 3 States 3t 2t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0100 1110 5555 0001 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rm lt Rm V dir8 ORL WRj dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0100 1111 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL WRj lt WRj V dir8 ORL Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 A 112 intel INSTRUCTION SET REFERENCE Encoding 0100 1110 ssss 0011 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rm lt Rm V dir16 ORL WRi dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0100 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL WRj lt WRJ V dir16 ORL Rm QWRj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0100 1110 tttt 1001 5555 0000 Code in Binary A5 Encoding Source Mode Encoding Operation ORL Rm
170. Bit When set activates idle mode Cleared by hardware when an interrupt or reset occurs If IDL and PD are both set PD takes precedence Figure 12 1 Power Control PCON Register 12 2 intel Table 12 1 Pin Conditions in Various Modes SPECIAL OPERATING MODES Mode Program ALE PSEN Port 0 Port 1 Port 2 Port 3 Memory Pin Pin Pins Pins Pins Pins Reset Don t Care Weak High Weak High Floating Weak High Weak High Weak High Idle Internal 1 1 Data Data Data Data Idle External 1 1 Floating Data Data Data Powerdown Internal 0 0 Data Data Data Data Powerdown External 0 0 Floating Data Data Data ONCE Don t Care Floating Floating Floating Weak High Weak High Weak High XTAL1 PD IDL Interrupt Serial Port Timer Block CPU A4160 01 Figure 12 2 Idle and Powerdown Clock Control 12 3 SPECIAL OPERATING MODES intel 12 3 IDLE MODE Idle mode is a power reduction mode that reduces power consumption to about 40 of normal In this mode program execution halts Idle mode freezes the clocks to the CPU at known states while the peripherals continue to be clocked Figure 12 2 The CPU status before entering idle mode is preserved i e the program counter program status word register and register file retain their data for the duration of idle mode The contents of the SFRs and RAM are also retained The stat
171. C251Sx holds the upper byte of the address on the bus port 2 after WR goes high NOTES 1 Specifications for PSEN are identical to those for RD 2 Ifa wait state is added by extending ALE this time increases by 2Tosc 3 If await state is added by extending RD PSEN WR this time increases by 2Tosc 4 If wait states are added as described in both Note 2 and Note 3 this time increases by a total of 4Tosc 13 32 intel Table 13 6 AC Timing Definitions for Specifications on the Memory System EXTERNAL MEMORY INTERFACE THE EXTERNAL MEMORY SYSTEM MUST MEET THESE SPECIFICATIONS Symbol Definition Notes Tnupzi Instruction Float After RD or PSEN High Time after RD or PSEN goes high until 1 memory system must float the bus If this timing is not met bus contention occurs Tnupz2 Data Float After RD PSEN High Time after RD or PSEN goes high until memory 1 system must float the bus If this timing is not met bus contention occurs Tnupx Data Instruction Hold After RD PSEN High Length of time the memory system must 1 hold data on the bus after RD or PSEN goes high RD Low to Input Data Valid Time after RD goes low until the memory system must 1 3 output valid data instruction Data Valid to WR High Length of time the memory system must output valid data before WR goes high Twuox Data Hold after WR High Length of time the m
172. CC MCS 51 microcontrollers 0 SRC Source Mode Binary Mode Select Clear this bit for binary mode opcodes compatible with MCS 51 microcon trollers Set this bit for source mode NOTES 1 Configuration bytes CONFIGO and CONFIG1 define the configuration of the A stepping version of the MCS 251 microcontroller 2 make the 8XC251SB pin compatible with 44 pin PLCC MCS 51 microcontrollers use the following bit values in CONFIGO 1101 1110B 3 Instructions for programming and verifying on chip configuration bytes are given in Chapter 14 Figure 4 5 Configuration Byte CONFIGO DEVICE CONFIGURATION intel CONFIG1 1 2 3 7 0 INTR WSB EMAP Bit Bit Number F ncHon 7 5 Reserved Set these bits when writing to CONFIG1 4 INTR Interrupt Mode If this bit is set interrupts push 4 bytes onto the stack the 3 bytes of the PC register and the PSW1 register If this bit is clear interrupts push 2 bytes onto the stack the 2 lower bytes of the PC register See Interrupt Stack Mode INTR on page 4 20 3 WSB Wait State B Clear this bit to generate one external wait state for memory region 01 Set this bit for no wait states for region 01 2 1 Reserved Set these bits when writing to CONFIG1 0 EMAP EPROM MAP Clearing this bit maps the upper 8 Kbytes of on chip code memory FF 2000H FF SFFFH to 00 E000H 0
173. CY bit MINI PM NINI PP P MO Pw PO MO N HR HR PO HR RB HR HR mM HR PMO BR BR PM Pw PP N MY N om wl wl wl wl MD DMD 9 MD DM WI MD WwW A HR RB RB AJAI AJAI BR BR OO OO BR ojojoj BR CO MO HR CoO om 25 HR HR BR HR RIK intel INSTRUCTION SET REFERENCE Table A 18 State Times to Access the Port SFRs Continued n Ed Additional State Times Binary Source Case 1 Case 2 Case 3 Case 4 ORL CY bit51 1 1 1 2 3 4 ORL dir8 data 3 3 1 2 3 4 ORL dir8 A 2 2 2 4 6 8 ORL Rm dir8 3 2 1 2 3 4 SETB bit 4 3 2 4 6 8 SETB bit51 2 2 2 4 6 8 SUB Rm dir8 3 2 1 2 3 4 SUBB A dir8 1 1 1 2 3 4 XCH A dir8 3 3 2 4 6 8 XRL A dir8 1 1 1 2 3 4 XRL dir8 data 3 3 2 4 6 8 XRL dir8 A 2 2 2 4 6 8 XRL Rm dir8 3 2 1 2 3 4 INSTRUCTION SET REFERENCE intel A 3 2 Instruction Summaries Table A 19 Summary of Add and Subtract Instructions Add ADD lt dest gt lt sre gt dest opnd lt dest opnd src opnd Subtract SUB lt dest gt lt src gt dest opnd dest opnd src opnd Add with Carry Subtract with Borrow ADDC lt dest gt lt src gt SUBB lt dest gt lt src gt lt src carry bit A A src opnd carry bit
174. Definition Oscillator Frequency Tauax Address Hold after PROG Address Setup to PROG Low Toupx Data Hold after PROG Tavav Address to Data Valid Vpp Hold after PROG Tove Data Setup to PROG Low PROG High to PROG Low Teusu ENABLE High to Vpp Teton PROG Width Data Float after ENABLE Vpp Setup to PROG Low Tetov ENABLE Low to Data Valid NOTE Address D Data E Enable G PROG H High L Low Q Data out S Supply Vpp V Valid X No longer valid Z Floating 14 11 intel Instruction Set Reference APPENDIX A INSTRUCTION SET REFERENCE This appendix contains reference material for the instructions in the MCS 251 architecture It includes an opcode map a summary of the instructions with instruction lengths and execution times and a detailed description of each instruction It contains the following tables Tables A 1 through 4 describe the notation used for the instruction operands Table 5 describes the notation used for control instruction destinations Table A 6 on page A 4 and Table A 7 on page A 5 comprise the opcode map for the instruction set Table 8 on page A 6 through Table A 17 on page A 10 contain supporting material for the opcode map Table A 18 on page A 12 lists execution times for a group of instructions that access the port SFRs The following tables list the instructions giv
175. E OR BINARY MODE 5 1 5 2 PROGRAMMING FEATURES OF THE MCS 251 ARCHITECTURE 5 1 5 2 1 Data ly POS Rr UR at e Det dee rato 5 2 5 2 1 1 Order of Byte Storage for Words and Double Words 5 2 5 2 2 Register Notation 2 5 e nadie Rene nigro n ete 5 2 5 2 3 Address Notaltlon ciet einge alm ie ODE Lect e SE 5 2 5 24 Addressing Modes oho 5 4 intel eee 5 3 DATA INSTRU GTIONS 1 IRE tite ER ity okie 5 4 5 3 1 Data Addressing MOd6S ects eiii te exemit e ated re ne eat 5 4 5 3 1 1 Register Addressing srncie i eter 5 5 5 9 1 2 inscio bubo uidi ui 5 5 5 94 39 JDirect serta cand eee rete e ire ce Ee cene e d 5 5 1 nee t ee trat ad ee ce i pe 5 6 5 9 4 5 Displacement 2 noie reet aa idtm eie cee 5 8 5 3 2 Arithmetic Instructions ete eet eet reine nrbs ANAE 5 8 5 3 3 Logical Instructions z isian oe eter ertet 5 9 5 3 4 Data Transfer nStr ctlons eh ERR OE DR ORARE 5 10 5 4 BIT INSTR GTIONS i Red rr EG e ie era 5 11 5 4 1 Bit Addressing eit ed ePi eg A RE EUR ER 5 11 5 5 CONTROL 2224
176. EFERENCE SLL WR b 1 WRj b WRj 0 lt 0 lt WRj 15 Shift arithmetic right by 1 bit Shifts the specified variable to the arithmetic right by 1 bit The MSB is unchanged The bit shifted out LSB is stored in the CY bit OV N Z V Register 1 contains OC5H 11000101B After executing the instruction SRA register 1 Register 1 contains OE2H 11100010B and CY 1 Binary Mode Source Mode 3 2 2 1 0000 1110 ssss 0000 Binary Mode A5 Encoding Source Mode Encoding SRA Rm 7 lt Rm 7 Rm a Rm a 1 CY lt Rm 0 Binary Mode Source Mode 3 2 2 1 0000 1110 tttt 0100 Binary Mode A5 Encoding Source Mode Encoding A 127 INSTRUCTION SET REFERENCE intel Operation SRL src Function Description Flags Example Variations SRL Rm Bytes States Encoding Hex Code in Operation SRL WRj Bytes States Encoding Hex Code in A 128 SRA WRj 15 lt WRj 15 WRj b lt WRj b 1 CYc WR 0 Shift logical right by 1 bit SRL shifts the specified variable to the right by 1 bit replacing the MSB with a zero The bit shifted out LSB is stored in the CY bit OV N 2 V Register 1 contains OC5H 11000101B After executing the instruction SRL register 1 Register 1 contains 62H 01100010B
177. EH 011111110B After executing the instruction INC RO 1 register 0 contains 7FH Variations INC Rm short Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0000 1011 5555 00 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation INC Rm lt Rm short WRj short Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0000 1011 tttt 01 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation INC WRj WRj short INC DRk short Binary Mode Source Mode Bytes 3 2 States 4 3 Encoding 0000 1011 uuuu 11 66 intel Hex Code in Operation INC DPTR Function Description Flags Example Bytes States Encoding Hex Code in Operation JB bit51 rel JB bit rel Function Description Flags INSTRUCTION SET REFERENCE Binary Mode A5 Encoding Source Mode Encoding INC DRk DRk shortdata pointer Increment data pointer Increments the 16 bit data pointer by one A 16 bit increment modulo 219 is performed an overflow of the low byte of the data pointer DPL from OFFH to 00H increments the high byte of the data pointer DPH by one An overflow of the high byte DPH does not increment the high word of the extended data pointer DPX DR56 CY AC OV N 2 Registers DPH DPL
178. EMORY INTERFACE intel 13 7 4 Explanation of AC Symbols Each symbol consists of two pairs of letters prefixed by for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two sig nal condition points For example T 4 is the time between signal L ALE condition H high and R RD condition L Low Table 13 4 defines the signal and condition codes Tosc 1 ALE i TLHLL 1 SENE TRLRH RD PSEN Instruction In gt lt lt Tavpv2 gt P2 A16 A17 A15 8 A16 A17 The value of this parameter depends on wait states See the table of AC characteristics A4211 02 Figure 13 24 External Bus Cycle Timing Code Fetch in Nonpage Mode 13 26 EXTERNAL MEMORY INTERFACE XTAL1 ALE RD PSEN PO P2 A16 A17 The value of this parameter depends on wait states See the table of AC characteristics 4 2 3 9 e T Hax H TAVLL AT 0 TLLAX Tosc A15 8 A16 A17 Data In lt lt TRHDZ2 I gt D C e 3 TAVRL A4210 02 Figure 13 25 External Bus Cycle Timing Data Read in Nonpage Mode Table 13 4 AC Timing Symbol Definitions Signals Conditions A Address H High D DATA L Low L ALE V
179. Encoding 1010 1001 1010 0 yyy direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV CY bit A 99 INSTRUCTION SET REFERENCE intel MOV DPTR data16 Function Description Flags Example Bytes States Encoding Hex Code in Operation Load data pointer with a 16 bit constant Loads the 16 bit data pointer DPTR with the specified 16 bit constant The high byte of the constant is loaded into the high byte of the data pointer DPH The low byte of the constant is loaded into the low byte of the data pointer DPL CY AC OV N 2 After executing the instruction MOV DPTR 1234H DPTR contains 1234H DPH contains 12H and DPL contains 34H Binary Mode Source Mode 3 3 2 2 1001 0000 data hi data low Binary Mode Encoding Source Mode Encoding MOV DPTR lt data16 MOVC A A lt base reg gt Function Description Flags A 100 Move code byte Loads the accumulator with a code byte or constant from program memory The address of the byte fetched is the sum of the original unsigned 8 bit accumulator contents and the contents of a 16 bit base register which may be the 16 LSBs of the data pointer or PC In the latter case the PC is incremented to the address of the following instruction before being added with the accumulator otherwise the base register is not altered Sixteen bit a
180. External bus cycles Nonpage mode bus structure 13 1 configuration 4 11 design example 13 17 13 21 port pin status 13 12 Nonvolatile memory programming and verifying 14 1 14 11 NOP instruction 5 15 A 25 On chip code memory 3 2 13 8 accessing in data memory 4 20 accessing in region 00 3 9 idle mode 12 4 powerdown mode 12 5 programming and verifying 14 1 14 7 setup for programming and verifying 14 3 14 5 starting address 3 8 14 2 top eight bytes 3 9 14 2 See also OTPROM EPROM ROM On chip oscillator hardware setup 11 1 On chip RAM 3 2 3 8 bit addressable 3 8 5 11 bit addressable in MCS 51 architecture 5 11 idle mode 12 4 MCS 51 architecture 3 3 3 4 reset 11 6 ONCE mode 12 1 12 7 entering 12 7 exiting 12 7 Opcodes for binary and source modes 4 17 5 1 map A 4 binary mode 4 19 source mode 4 19 See also Binary and source modes ORL instruction 5 9 5 11 for bits A 23 ORL instruction 5 11 for bits A 23 INDEX Oscillator 2 6 at startup 11 7 during reset 11 5 on chip 11 3 ONCE mode 12 7 powerdown mode 12 5 12 6 programming and verifying nonvolatile memory 14 3 OTPROM EPROM on chip programming algorithm 14 6 programming and verifying 14 3 timing for programming and verifying 14 11 verify algorithm 14 7 See also On chip code memory Configuration bytes Lock bits Encryption array Signature bytes OV bit 5 18 5 19 Overflow See OV bit P P bit 5 1
181. FF FFFFH Also see the caution on page 4 2 regarding execution of code from locations immediately below the configuration array 3 7 ADDRESS SPACES intel Figure 3 4 also indicates the addressing modes that can be used to access different areas of mem ory The first 64 Kbytes can be directly addressed The first 96 bytes of general purpose RAM 00 0020 00 007 are bit addressable Chapter 5 Programming discusses addressing modes Figure 3 5 on page 3 7 shows how areas of the memory space are implemented by on chip RAM on chip ROM OTPROM EPROM and external memory The first 32 bytes of on chip RAM store banks 0 3 of the register file see 8 2515 SB SP SQ Register File on page 3 10 3 2 1 On chip General purpose Data RAM On chip RAM 512 bytes or 1 Kbyte is provided for general data storage Figure 3 5 Instruc tions cannot execute from on chip data RAM The data is accessible by direct indirect and dis placement addressing Locations 00 0020H 00 007FH are also bit addressable 3 2 2 On chip Code Memory 83 2515 SB SP SQ 87C251SA SB SP SQ The 8XC251Sx is available with 8 Kbytes or 16 Kbytes of on chip ROM 83C251Sx or OTPROM EPROM 87 2515 as well as without on chip code memory Figure 3 5 Table 2 1 on page 2 3 lists the amount of on chip code memory for each device The on chip ROM OTPROM EPROM is intended primarily for code storage although its contents can also be read as data w
182. H S 80H S 88H S 90H S FOH S F8H Table A 5 Notation for Destinations in Control Instructions Destination 251 MCS 51 Address Description Arch Arch rel A signed two s complement 8 bit relative address The destination is v v 128 to 127 bytes relative to first byte of the next instruction addr11 An 11 bit destination address The destination is in the same 2 Kbyte v v block of memory as the first byte of the next instruction addr16 A 16 bit destination address A destination can be anywhere within v v the same 64 Kbyte region as the first byte of the next instruction addr24 A 24 bit destination address A destination can be anywhere within v the 16 Mbyte address space INSTRUCTION SET REFERENCE A 2 MAP AND SUPPORTING TABLES Table 6 Instructions for MCS 51 Microcontrollers Bin 0 1 2 3 4 5 6 7 8 F Src 0 1 2 3 4 5 5 6 5 7 5 8 5 0 AJMP LJMP RR INC INC INC INC addr11 addri6 A dir8 Ri Rn 1 JBC ACALL LCALL RRC DEC DEC DEC DEC bit rel addr11 addri6 A A dir8 Ri Rn 2 JB AJMP RET RLA ADD ADD ADD ADD bit rel addr11 A data A dir8 A Ri A Rn JNB ACALL RETI RLCA ADDC ADDC ADDC ADDC bit rel addr11 A dir8 A Ri A Rn 4 JC AJMP ORL ORL ORL ORL ORL ORL rel addr11 dir8 A dir8 data A data A dir8 A Ri A Rn 5 JNC ACALL ANL ANL ANL
183. H respectively After executing the instruction sequence INC RO INC RO INC RO register 0 contains 7FH and on chip RAM locations 7EH and 7FH contain 00H and 41H respectively Variations INC A Binary Mode Source Mode Bytes 1 1 States 1 1 Encoding 0000 0100 A 64 intel Hex Code in Operation INC dir8 Bytes States Encoding Hex Code in Operation INC Ri Bytes States Encoding Hex Code in Operation INC Rn Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Encoding Source Mode Encoding INC lt A 1 Binary Mode Source Mode 2 2 2t 2t tlf this instruction addresses a port Px x 0 3 add 2 states 0000 0101 direct addr Binary Mode Encoding Source Mode Encoding INC dir8 lt dir8 1 Binary Mode Source Mode 1 2 3 4 0000 011i Binary Mode Encoding Source Mode A5 Encoding INC Ri lt Ri 1 Binary Mode Source Mode 1 2 1 2 0000 1rrr Binary Mode Encoding Source Mode A5 Encoding INC Rn lt Rn 1 A 65 INSTRUCTION SET REFERENCE INC dest src intel Function Increment Description Increments the specified variable by 1 2 or 4 An original value of OFFH overflows to Flags CY AC OV N 2 Register 0 contains 7
184. IG1 located in user code memory space The A stepping version of the MCS 251 microcontroller stores configuration information in two configuration bytes CONFIGO and CONFIGI located in OTPROM outside the memory address space 4 1 DEVICE CONFIGURATION intel 4 2 DEVICE CONFIGURATION B STEPPING The B stepping version of the 8XC251Sx microcontroller reserves the top eight bytes of the memory address space FF FFF8H FF FFFFH for an eight byte configuration array Figure 4 1 The two lowest bytes of the configuration array are assigned to user configuration bytes UCONFIGO FF FFF8H and UCONFIGI FF FFF9H For ROM OTPROM EPROM devices configuration information is stored in non volatile memory at these addresses For devices with out ROM OTPROM EPROM configuration information is accessed from external memory using these addresses For ROM OTPROM EPROM devices user configuration bytes UCONFIGO and UCONFIGI can be programmed at the factory or by the user using the procedures provided in Chapter 14 Programming and Verifying Nonvolatile Memory For devices without ROM OTPROM EPROM the user should store configuration information in user configuration bytes UCONFIGO UCONFIGI in an eight byte configuration array located at the highest addresses implement ed in external user code memory space See Table 4 1 and Figures 4 1 and 4 2 Bit definitions of UCONFIGO and UCONFIGI are provided in Figures 4 3 and 4 4 The upper 6 bytes
185. Impedance NOTES 1 During external memory accesses the CPU writes FFH to the PO register and the register con tents are lost 2 The P2 register can be used to select 256 byte pages in external memory 13 5 1 Port 0 and Port 2 Pin Status in Nonpage Mode In nonpage mode the port pins have the same signals as those on the 8XC51FX For an external memory instruction using a 16 bit address the port pins carry address and data bits during the bus cycle However if the instruction uses an 8 bit address e g MOVX Ri the contents of P2 are driven onto the pins These pin signals can be used to select 256 bit pages in external memory During a bus cycle the CPU always writes FFH to PO and the former contents of PO are lost A bus cycle does not change the contents of P2 When the bus is idle the port O pins are held at high impedance and the contents of P2 are driven onto the port 2 pins 13 5 2 Port 0 and Port 2 Pin Status in Page Mode In a page mode bus cycle the data is multiplexed with the upper address byte on port 2 However if the instruction uses an 8 bit address e g MOVX the contents of P2 are driven onto the pins when data is not on the pins These logic levels can be used to select 256 bit pages in external memory During bus idle the port 0 and port 2 pins are held at high impedance For port pin status when the chip in is idle mode powerdown mode or reset see Chapter 12 Special Operating Modes 13 6
186. Kbyte code memory has a separate memory space Data in the code memory can be accessed only with the MOVC instruction Similarly the 64 Kbyte external data memory can be accessed only with the MOVX instruction t 51 Microcontroller Family User s Manual Order Number 272383 3 2 intel ADDRESS SPACES The register file registers RO R7 comprises four switchable register banks each having 8 reg isters The 32 bytes required for the four banks occupy locations 00H 1FH in the on chip data memory Figure 3 3 shows how the address spaces in the MCS 51 architecture map into the address spaces in the MCS 251 architecture details are listed in Table 3 1 The 64 Kbyte code memory for MCS 51 microcontrollers maps into region FF of the memory space for MCS 251 microcontrollers Assemblers for MCS 251 microcontrollers assemble code for MCS 51 microcontrollers into region FF and data accesses to code memory are directed to this region The assembler also maps the interrupt vectors to region FF This mapping is trans parent to the user code executes just as before without modification RO Register File R7 External Data MOVX Internal Data SFRs indirect direct Internal Data direct indirect A4139 01 Figure 3 2 Address Spaces for the MCS 51 Architecture 3 3 ADDRESS SPACES Memory Address Space 16 Mbytes FFFFH MCS 51 Architecture Code Memory FF 0000H 0000H 5 100
187. MCS 251 microcontrollers and to the 8XC251Sx in particular It also discusses the compati bility of the MCS 251 architecture and the 51 architecture in terms of their address spaces 3 1 ADDRESS SPACES FOR MCS 251 MICROCONTROLLERS Figure 3 1 shows the memory space the SFR space and the register file for MCS 251 microcon trollers The address spaces are depicted as being eight bytes wide with addresses increasing from left to right and from bottom to top Memory Address Space 16 Mbytes SFR Space 512 Bytes Register File 64 Bytes 63 A4100 01 Figure 3 1 Address Spaces for MCS 251 Microcontrollers 3 1 ADDRESS SPACES intel Itis convenient to view the unsegmented 16 Mbyte memory space as consisting of 256 64 Kbyte regions numbered 00 to FF NOTE The memory space in the MCS 251 architecture is unsegmented The 64 Kbyte regions 00 O1 FF are introduced only as a convenience for discussions Addressing in the MCS 251 architecture is linear there are no segment registers MCS 251 microcontrollers can have up to 64 Kbytes of on chip code memory in region FF On chip data RAM begins at location 00 0000H The first 32 bytes 00 0000H 00 001FH provide storage for a part of the register file On chip general purpose data RAM begins at 00 0020H The sizes of the on chip code memory and on chip RAM depend on the particular device The register file has its own address space Fi
188. MORY Table 14 2 Lock Bit Function Lock Bits Programmed Protection Type LB3 LB2 LB1 Level 1 U U U No program lock features are enabled On chip user code is encrypted when verified if encryption array is programmed Level 2 U U P External code is prevented from fetching code bytes from on chip code memory Further programming of the on chip OTPROM is disabled Level 3 U P P Same as level 2 plus on chip code memory verify is disabled Level 4 P P P Same as level 3 plus external memory execution is disabled NOTE Other combinations of the lock bits are not defined 14 6 4 Encryption Array The 87 2515 and 83C2515x controllers include a 128 byte encryption array located in nonvol atile memory outside the memory address space During verification of the on chip code memory the seven low order address bits also address the encryption array As the byte of the code mem ory is read it is exclusive NOR ed XNOR with the key byte from the encryption array If the encryption array is not programmed still all 1s the user program code is placed on the data bus in its original unencrypted form If the encryption array is programmed with key bytes the user program code is encrypted and can t be used without knowledge of the key byte sequence CAUTION If the encryption feature is implemented the portion of the on chip code memory that does not contain program code should be filled with
189. MOV A data Bytes States Encoding Hex Code in Operation MOV dir8 data Bytes States Encoding Move byte variable Copies the byte variable specified by the second operand into the location specified by the first operand The source byte is not affected This is by far the most flexible operation Twenty four combinations of source and destination addressing modes are allowed CY AC OV N 2 On chip RAM location 30H contains 40H on chip RAM location 40H contains 10H input port 1 contains 11001010B 0CAH After executing the instruction sequence MOV R0 230H RO 30H MOV A RO lt 40H MOV R1 A R1 lt 40H MOV B R1 B lt 10H MOV R1 P1 RAM 40H lt MOV P2 P1 P2 0CAH register 0 contains 30H the accumulator and register 1 contain 40H register B contains 10H and on chip RAM location 40H and output port 2 contain OCAH 11001010B Binary Mode Source Mode 2 2 1 1 0111 0100 immed data Binary Mode Encoding Source Mode Encoding MOV lt data Binary Mode Source Mode 3 3 3t 3t tlf this instruction addresses a port Px x 0 3 add 1 state 0111 0101 direct addr immed data A 83 INSTRUCTION SET REFERENCE Hex Code in Operation MOV Ri data Bytes States Encoding Hex Code in Operation MOV Rn data Bytes States Encoding Hex Co
190. MOVS lt dest gt lt src gt MOVZ lt dest gt lt src gt MOVC lt dest gt lt src gt MOVX lt dest gt lt src gt MOVX lt dest gt lt src gt destination lt src destination lt src with sign extend destination src opnd with zero extend A lt code byte external mem lt A lt source in external mem Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States A Rn Reg to acc 1 1 2 2 A dir8 Dir byte to acc 2 1 3 2 1 3 A Ri Indir RAM to acc 1 2 2 3 A data Immediate data to acc 2 1 2 1 Rn A Acc to reg 1 1 2 2 Rn dir8 Dir byte to reg 2 1 3 3 2 3 Rn data Immediate data to reg 2 1 3 2 dir8 A Acc to dir byte 2 2 3 2 2 3 dir8 Rn Reg to dir byte 2 2 3 3 3 3 dir8 dir8 Dir byte to dir byte 3 3 3 3 dir8 Ri Indir RAM to dir byte 2 3 3 4 dir8 data Immediate data to dir byte 3 3 3 3 3 3 MEN Ri A Acc to indir RAM 1 3 2 4 Ri dir8 Dir byte to indir RAM 2 3 3 4 Ri data Immediate data to indir RAM 2 3 3 4 DPTR data16 Load Data Pointer with a 16 bit const 3 2 3 2 Rmd Rms Byte reg to byte reg 3 2 2 1 WRjd WRjs Word reg to word reg 3 2 2 1 DRkd DRks Dword reg to dword reg 3 3 2 2 Rm data 8 bit immediate data to byte reg 4 3 3 2 WR j data16 16 bit immediate data to word reg 5 3 4 2 DRk 0data16 zero extended 16 bit immediate data 5 5 4 4 to
191. Mode 2 2 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state 0100 0101 direct addr Binary Mode Encoding Source Mode Encoding ORL lt A V dir8 Binary Mode Source Mode 1 2 2 3 0100 011i Binary Mode Encoding Source Mode A5 Encoding ORL lt A V Ri Binary Mode Source Mode 1 2 1 2 0100 1rrr INSTRUCTION SET REFERENCE intel Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation ORL lt A V Rn ORL Rmd Rms Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0100 1100 ssss 5555 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rmd Rmd V Rms ORL WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0100 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL WRjd WRjd V WRjs ORL Rm Zdata Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0100 1110 ssss 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rm lt Rm V data A 111 INSTRUCTION SET REFERENCE ORL WRj data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0100 1110 tttt 0100 data hi data low Hex Code in
192. Mode Bus Cycles intel In nonpage mode the external bus structure is the same as for MCS 51 microcontrollers The up per address bits A15 8 are on port 2 and the lower address bits A7 0 are multiplexed with the data D7 0 on port 0 External code read bus cycles execute in approximately two state times See Table 13 2 and Figure 13 2 External data read bus cycles Figure 13 3 and external write bus cycles Figure 13 4 execute in approximately three state times For the write cycle Figure 13 4 a third state is appended to provide recovery time for the bus Note that the write signal WR is asserted for all memory regions except for the case of RD1 0 11 where WR is assert ed for regions 00 03 but not for regions FC FF 13 4 RD PSEN PO A17 A16 P2 Figure 13 2 External Bus Cycle Code Fetch Nonpage Mode State 1 State 2 A7 0 D7 0 A17 A16 A15 8 A2807 04 EXTERNAL MEMORY INTERFACE XTAL RD PSEN PO A17 A16 P2 State 1 gt N State 2 A17 A16 A15 8 State 3 A4230 01 Figure 13 3 External Bus Cycle Data Read Nonpage Mode XTAL ALE WR PO A17 A16 P2 State 1 State 2 17 16 15 8 State 3 A2808 03 Figure 13 4 External Bus Cycle Data Write Nonpage Mode 13 5 EXTERNAL MEMORY INTERFACE intel The first code fetch to a 256 byte page of memory always us
193. Number Mnemonic unco 7 FE Framing Error Bit To select this function set the SMODO bit in the PCON register Set by hardware to indicate an invalid stop bit Cleared by software not by valid frames SMO Serial Port Mode Bit 0 To select this function clear the SMODO bit in the PCON register Software writes to bits SMO and SM1 to select the serial port operating mode Refer to the SM1 bit for the mode selections 6 SM1 Serial Port Mode Bit 1 Software writes to bits SM1 and SMO above to select the serial port operating mode SMO SM1 Mode Description Baud Rate 0 0 0 Shift register Fosc 12 0 1 1 8 bit UART Variable 1 0 2 9 bit UART 32 or 64 1 1 3 9 bit UART Variable Select by programming the SMOD bit in the PCON register see Baud Rates on page 10 10 5 SM2 Serial Port Mode Bit 2 Software writes to bit SM2 to enable and disable the multiprocessor communication and automatic address recognition features This allows the serial port to differentiate between data and command frames and to recognize slave and broadcast addresses 4 REN Receiver Enable Bit To enable reception set this bit To enable transmission clear this bit 3 TB8 Transmit Bit 8 In modes 2 and 3 software writes the ninth data bit to be transmitted to TB8 Not used in modes 0 and 1 2 RB8 Receiver Bit 8 Mode 0 Not used Mode 1 SM2 clear Set or cleared by hardware to reflect the stop bit received Mo
194. OG pins are used for their alternative programming functions For a complete list of signal descriptions see Appendix B 14 1 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY intel In some microcontroller applications it is desirable that user program code be secure from unau thorized access The 8 2515 offers two types of protection for program code stored in the on chip array Program code in the on chip code memory is encrypted when read out for verification if the encryption array is programmed Athree level lock bit system restricts external access to the on chip code memory 14 1 1 Programming Considerations for On chip Code Memory Itis recommended that user program code be located starting at address FF 0100H Since the first instruction following device reset is fetched from FF 0000H use a jump instruction to FF 0100H to begin execution of the user program For information on address spaces see Chapter 3 For B stepping devices the top eight bytes of the memory address space FF FFF8H FF FFFFH are reserved for device configuration Do not read or write user code at these locations For 1 the reset routine obtains configuration information from a configuration array located these addresses For EA 0 the reset routine obtains configuration information from a config uration array in external memory using these internal addresses A stepping devices store con figuration information in a four byte a
195. P lt SP 1 SP 7 0 PC addr 23 0 ECALL DRk Binary Mode Source Mode Bytes 3 2 States 12 11 Encoding 1001 1001 uuuu Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ECALL PC PC 4 SP lt SP 1 SP lt 23 16 SP lt SP 1 SP 15 8 SP lt SP 1 SP 7 0 lt DRk lt dest gt Function Extended jump Description Causes an unconditional branch to the specified address by loading the 8 bits of the high order and 16 bits of the low order words of the PC with the second third and fourth instruction bytes The destination may be therefore be anywhere in the full 16 Mbyte memory space A 62 Variations EJMP addr24 Bytes States Encoding Hex Code in Operation EJMP DRk Bytes States Encoding Hex Code in Operation ERET Function Description Flags Example INSTRUCTION SET REFERENCE CY AC OV The label JMPADR is assigned to the instruction at program memory location 123456H The instruction is EJMP JMPADR Binary Mode Source Mode 5 4 6 5 1000 1010 addr23 addr15 addr8 addr7 addrO addr16 Binary Mode A5 Encoding Source Mode Encoding EJMP PC lt addr 23 0 Binary Mode Source Mode 3 2 7 6 1000 1001 uuuu
196. PU is not interrupted by command frames addressed to other devices If desired you may enable the automatic address recognition feature in mode 1 In this configu ration the stop bit takes the place of the ninth data bit The RI bit is set only when the received command frame address matches the device s address and is terminated by a valid stop bit NOTE The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 i e setting the SM2 bit in the SCON register in mode 0 has no effect To support automatic address recognition a device is identified by a given address and a broad cast address 10 5 1 Given Address Each device has an individual address that is specified in the SADDR register the SADEN reg ister is a mask byte that contains don t care bits defined by zeros to form the device s given ad dress These don t care bits provide the flexibility to address one or more slaves at a time The following example illustrates how a given address is formed To address a device by its individ ual address the SADEN mask byte must be 1111 1111 SADDR 0101 0110 SADEN 1111 1100 Given 0101 01XX The following is an example of how to use given addresses to address different slaves Slave A SADDR 1111 0001 Slave C SADDR 11110010 SADEN 1111 1010 SADEN 1111 1101 Given 1111 0 0 Given 1111 00X1 Slave B SADDR 1111 0011 SADEN 1111 1001 Given 1111 OXX1 10 8
197. Q Special Function Registers SFRs SFR Binary Reset Value Mnemonic SFR Name Hex Address High Low TH1 Timer 1 Timer Register High Byte S 8DH 0000 0000 TL1 Timer 1 Timer Register Low Byte S 8BH 0000 0000 TH2 Timer 2 Timer Register High Byte S CDH 0000 0000 TL2 Timer 2 Timer Register Low Byte S CCH 0000 0000 WDTRST Watchdog Timer Reset Register S A6H XXXX XXXX This register resides in the register file It can also be accessed as an SFR REGISTERS intel ACC Address EOH Reset State 0000 0000B Accumulator ACC provides SFR access to the accumulator which resides in the register file as byte register R11 also named ACC Instructions in the MCS 51 architecture use the accumulator as both Source and destination for calculations and moves Instructions in the MCS 251 architecture assign no special significance to R11 These instructions can use byte registers Rm m 0 15 interchangeably 7 0 Accumulator Contents Bit Bit Number Mnemonic Function 7 0 7 0 intel i REGISTERS B Address FOH Reset State 0000 0000B B Register The B register provides SFR access to byte register R10 also named B in the register file The B register is used as both a source and destination in multiply and divide operations For all other operations the B register is available for use as one of the byte registers Rm m 0 15
198. RCAP2H 7 0 High byte of the timer 2 reload recapture register RCAP2L 7 0 Low byte of the timer 2 reload recapture register C 24 intel REGISTERS SADDR Address S A9H Reset State 0000 0000B Slave Individual Address Register SADDR contains the device s individual address for multiprocessor communication 7 0 Slave Individual Address Bit Bit Number Mnemonic Function 7 0 SADDR 7 0 C 25 REGISTERS intel SADEN Address S B9H Reset State 0000 0000B Mask Byte Register This register masks bits in the SADDR register to form the device s given address for multiprocessor communication 7 0 Mask for SADDR Bit Bit Number Mnemonic Function 7 0 SADEN 7 0 C 26 intel REGISTERS SBUF Address S 99H Reset State XXXX XXXXB Serial Data Buffer Writing to SBUF loads the transmit buffer of the serial I O port Reading SBUF reads the receive buffer of the serial I O port d 0 Data Sent Received by Serial I O Port Bit Bit Number Mnemonic Function 7 0 SBUF 7 0 C 27 REGISTERS intel SCON Address 98H Reset State 0000 0000B Serial Port Control Register SCON contains serial I O control and status bits including the mode select bits and the interrupt flag bits 7 0 FE SMO SM1 SM2 REN TB8 RB8 TI RI Bit Bit Function
199. ROM OTPROM EPROM and external memory your code can be placed in the upper eight bytes of the on chip ROM OTPROM EPROM As the 8 2515 fetches bytes above the top address in the on chip ROM OTPROM EPROM the code fetches automati cally become external bus cycles In other words the rollover from on chip ROM OTPROM EPROM to external code memory is transparent to the user 3 2 2 1 Accessing On chip Code Memory in Region 00 The 87C251SB SQ and the 83C251SB SQ can be configured so that the upper half of the 16 Kbyte on chip code memory can also be read as data at locations in the top of region 00 see Configuration Bytes on page 14 8 That is locations 2000 can also be access ed at locations 00 E000H 00 FFFFH This is useful for accessing code constants stored in ROM OTPROM EPROM Note however that all of the following three conditions must hold for this mapping to be effective The device is configured with EMAP 0 in the UCONFIGI register Chapter 4 Device Configuration 1 access to this area of region 00 is a data read not a code fetch 3 9 ADDRESS SPACES intel If one or more of these conditions do not hold accesses to the locations in region 00 are referred to external memory NOTE Remapping does not apply to the 87C251SA SP and the 83C251SA SP 3 2 3 External Memory Regions 01 02 03 FC FD and FE and portions of regions 00 and FF of
200. Rk WRi dis 49 2 k2 dis 15 8 dis 7 0 MOV Rm DRk dis 2 9 m k 4 dis 15 8 dis 7 0 MOV WRj DRk dis 6 9 j2 k 4 dis 15 8 dis 7 0 MOV QWRj dis Rm 1 9 m j 2 dis 15 8 dis 7 0 MOV WRij dis WRk 5 9 j 2 k2 dis 15 8 dis 7 0 MOV DRk dis Rm 3 9 m k 4 dis 15 8 dis 7 0 MOV DRk dis WRj 7 9 j2 k 4 dis 15 8 dis 7 0 MOVS WRj Rm T A j 2 m MOVZ WRj Rm OJA j 2 m MOV WRj WRj 0 B j 2 1000 j 2 0000 MOV WRj DRk 0 8B k 4 1010 2 0000 MOV QWRj WRj 1 B 2 1000 j 2 0000 MOV DRk WRj 1 B k 4 1010 j 2 0000 MOV dir8 Rm 7 m 0001 dir8 addr MOV dir8 WRj 7 j2 0101 dir8 addr MOV dir8 DRk 7 k 4 1101 dir8 addr MOV dir16 Rm 7 A m 0011 dir16 addr high dir16 addr low MOV dir16 WRj 7 2 0111 dir16 addr high dir16 addr low MOV dir16 DRk 7 k 4 1111 dir16 addr high dir16 addr low MOV WRj Rm 7 2 1001 0000 MOV QDRk Rm 7 k 4 1011 m 0000 INSTRUCTION SET REFERENCE Table A 15 INC DEC Instruction Byte 0 Byte 1 1 INC Rm short 0B m 00 55 2 INC WRj short 2 01 ss 3 INC DRk short 0 B k 4 11 ss 4 DEC Rm short 1B m 00 5 5 DEC WRj short 1 2 01 ss 6 DEC DRk short 1 B k 4 11 ss Table A 16 Encoding for INC DEC ss short 00 1 01 10 Table A 17 Shifts Instruction Byte 0 Byte 1 1 SRA Rm O E m 00
201. Rs x 3 0 increases the execution time These cases are noted individually in the tables in Appendix A 5 1 SOURCE MODE OR BINARY MODE OPCODES Source mode and Binary mode refer to the two ways of assigning opcodes to the instruction set of the MCS 251 architecture Depending on the application one mode or the other may produce more efficient code The mode is established during device reset based on the value of the SRC bit in configuration byte UCONFIGO or CONFIGO For information regarding the selection of the opcode mode see Opcode Configurations SRC on page 4 17 5 2 PROGRAMMING FEATURES OF THE MCS 251 ARCHITECTURE The instruction set for MCS 251 microcontrollers provides the user with new instructions that ex ploit the features of the architecture while maintaining compatibility with the instruction set for MCS 51 microcontrollers Many of the new instructions can operate on either 8 bit 16 bit or 32 bit operands In comparison with 8 bit and 16 bit operands 32 bit operands are accessed with fewer addressing modes This capability increases the ease and efficiency of programming MCS 251 microcontrollers in a high level language such as C The instruction set is divided into Data Instructions page 5 4 Bit Instructions page 5 11 and Control Instructions page 5 12 Data instructions process 8 bit 16 bit and 32 bit data bit instructions manipulate bits and control instructions manage program flow
202. SH WRj Bytes States Encoding Hex Code in Operation PUSH DRk Bytes States Encoding Hex Code in Operation RET Function Description Flags Example INSTRUCTION SET REFERENCE Binary Mode Source Mode 3 2 5 4 1100 1010 tttt 1001 Binary Mode A5 Encoding Source Mode Encoding PUSH SP lt SP 1 SP lt WRj SP lt SP 1 Binary Mode Source Mode 3 2 9 8 1100 1010 uuuu 1011 Binary Mode A5 Encoding Source Mode Encoding PUSH SP SP 1 SP lt DRk SP SP 3 Return from subroutine Pops the high and low bytes of the PC successively from the stack decrementing the stack pointer by two Program execution continues at the resulting address which normally is the instruction immediately following ACALL or LCALL CY AC OV The stack pointer contains and on chip RAM locations 0AH and OBH contain 01H and 23H respectively After executing the instruction RET the stack pointer contains 09H and program execution continues at location 0123H A 119 INSTRUCTION SET REFERENCE Bytes States Encoding Hex Code in Operation RETI Function Description Flags Example A 120 Binary Mode 1 7 Source Mode 1 7 0010 0010 Binary Mode Encoding Source Mode Encoding RET
203. SP 63 SP 81H Data Data Pointer Extended Low DPXL 57 DPXL 5 84 Pointer DR56 DPX DPTR Data Pointer High DPH 58 DPH S 83H Data Pointer Low DPL 59 DPL S 82H Accumulator A Register A R11 11 ACC S EOH B Register B R10 10 B S FOH 3 15 ADDRESS SPACES intel 3 4 SPECIAL FUNCTION REGISTERS SFRS The special function registers SFRs reside in their associated on chip peripherals or in the core Table 3 5 shows the SFR address space with the SFR mnemonics and reset values SFR addresses are preceded by S to differentiate them from addresses in the memory space Unoccupied lo cations in the SFR space the shaded locations in Table 3 5 are unimplemented i e no register exists If an instruction attempts to write to an unimplemented SFR location the instruction exe cutes but nothing is actually written If an unimplemented SFR location is read it returns an un specified value NOTE SFRs may be accessed only as bytes they may not be accessed as words or dwords ADDRESS SPACES Table 3 5 8XC251SA SB SP SQ SFR Map and Reset Values 0 8 1 9 2 A 3 B 4 C 5 D 6 E 7IF F8 CH CCAPOH CCAP1H CCAP2H CCAP3H CCAP4H FF 00000000 B FO 52 00000000 CL CCAPOL CCAP1L CCAP2L CCAP3L CCAP4L EF 00000000
204. Set this bit for source mode NOTES 1 User configuration bytes UCONFIGO and UCONFIG1 define the configuration of the B stepping ver sion of the 8XC251Sx 2 Address UCONFIGO is the lowest byte of the 8 byte configuration array When EA 1 the 8XC251Sx obtains configuration information from a configuration array located in on chip ROM OTPROM EPROM at the top of memory region FF UCONFIGO is at address FF FFF8H When 0 the 8XC251Sx obtains configuration information from a configuration array located at the highest addresses implemented in external user memory using internal addresses FF FFF8H FF FFF9H The address of the configuration array in external memory depends on the size of the external memory see Table 4 1 and Figure 4 2 3 WSAO0O WSA1 For A stepping compatible applications program WSA1 1 and use WSAO to replace WSA See the WSA bit in CONFIGO Figure 4 5 4 Instructions for programming and verifying on chip configuration bytes are given in Chapter 14 Figure 4 3 User Configuration Byte UCONFIGO intel DEVICE CONFIGURATION UCONFIG1 Address FF FFF9H 2 1 4 7 0 INTR WSB WSB1 WSBO EMAP Bit Bit Number Mnemonic 7 5 Reserved Reserved for internal or future use Set these bits when writing to UCONFIG1 4 INTR Interrupt Stack Mode If this bit is set interrupts push 4 bytes onto the stack
205. Setting the run control bit CR in the CCON register turns the PCA timer counter on if the out put of the NAND gate Figure 9 1 equals logic 1 The PCA timer counter continues to operate during idle mode unless the CIDL bit of the CMOD register is set The CPU can read the contents of the CH and CL registers at any time However writing to them is inhibited while they are counting i e when the CR bit is set 9 2 intel PROGRAMMABLE COUNTER ARRAY Compare Capture Modules Module 0 r J P1 3 CEXO Module 1 5 P1 4 CEX1 5 2 Module 2 r P1 5 CEX2 Module 3 P1 6 CEX3 Module 4 P1 7 CEX4 16 Bits A17 Fosc 12 UG OSC m Interrupt Fosc 4 CH cL Request Timer 0 Overflow 10 8 Bits 8 Bits gt P12 ECI 1 1 PCA CCON 7 Timer Counter Overflow 712 CPS1 50 CIDL ECF CMOD 2 CMOD41 CMOD 7 CMOD 0 Enable PCON 0 CCON 6 Idle Mode Run Control A4162 03 Figure 9 1 Programmable Counter Array 9 3 PROGRAMMABLE COUNTER ARRAY Table 9 1 PCA Special Function Registers SFRs intel Mnemonic Description Address CL PCA Timer Counter These registers serve as a common 16 bit timer or S E9H CH event counter for the five compare capture modules Counts Fos 12 S F9H Fosc 4 timer 0 overflow or the external signal on P1 2 ECI as selected by CMOD In PWM mode CL operates as an 8 bit timer CCON PCA Timer Counte
206. Use the following modem settings 14400 N 8 1 If your modem does not support 14 4K baud the system provides auto configuration support for 1200 baud through 14 4K baud modems To access the BBS just dial the telephone number see page 1 7 and respond to the system prompts During your first session the system asks you to register with the system operator by entering your name and location The system operator will then set up your access account within 24 hours At that time you can access the files on the BBS For a listing of files call the FaxBack service and order catalog 6 the BBS catalog If you encounter any difficulty accessing our high speed modem try our dedicated 2400 baud modem see page 1 7 Use the following modem settings e 2400 baud N 8 1 intel GUIDE TO THIS MANUAL 1 4 3 Howto Find the Latest ApDBUILDER Files and Hypertext Manuals and Data Sheets on the BBS The latest ApBUILDER files and hypertext manuals and data sheets are available first from the BBS To access the files 1 Select F from the BBS Main menu Select L from the Intel Apps Files menu The BBS displays the list of all area levels and prompts for the area number Select 25 to choose the ApBUILDER Hypertext area Area level 25 has four sublevels 1 General 2 196 Files 3 186 Files and 4 8051 Files des pues be 6 Select 1 to find the latest ApBUILDER files or the number of the appropriate product family
207. V WRj MOV WRi dis MOV dir16 17 MOV DRk MOV DRk dis 18 MOV DRk MOV DRk dis NOTE Avoid MOV instructions for external memory accesses These instructions can corrupt input code bytes at port 0 External signal ALE address latch enable facilitates external address latch capture The address byte is valid after the ALE pin drives Vo For write cycles valid data is written to port 0 just prior to the write WR pin asserting Vor Data remains valid until WR is undriven For read cycles data returned from external memory must appear at port 0 before the read RD pin is undriven refer to the 8 2515 datasheet for exact specifications Wait states by definition affect bus timing 7 8 intel 9 Timer Counters Watchdog Timer intel CHAPTER 8 TIMER COUNTERS AND WATCHDOG TIMER This chapter describes the timer counters and the watchdog timer WDT included as peripherals on the 8 2515 When operating as a timer a timer counter runs for a programmed length of time then issues an interrupt request When operating as a counter a timer counter counts nega tive transitions on an external pin After a preset number of counts the counter issues an interrupt request Timer counters are covered in sections 8 1 through 8 6 The watchdog timer provides a way to monitor system operation It causes a system reset if a soft ware malfunction allows it to expire The watchdog timer is covered in Watchdog Timer
208. Valid Q Data Out X No Longer Valid R RD PSEN Z Floating W WR 13 27 13 28 EXTERNAL MEMORY INTERFACE ALE WR TLHAX TLLAX id lt lt TWHOX Po lt lt Data Out m TAVWL2 pz TWHAX P2 A16 A17 A15 8 A16 A17 The value of this parameter depends on wait states See the table of AC characteristics A4179 01 Figure 13 26 External Bus Cycle Timing Data Write in Nonpage Mode EXTERNAL MEMORY INTERFACE Tosc Ss UFU TLHLL gt TEAL RD PSEN t TRLDV TRLAZ c TLHAX H TRHDZ1 TAVLL Til AX TRHDX lt gt Pe C me 0 TAVRL Instruction In TAVDv1 TAVDV3 lt TAvbv2 Cors Instruction In PO A16 A17 A7 0 A16 A17 A7 0 A16 A17 Page Miss Hi The value of this parameter depends on wait states See the table of AC characteristics A page hit i e a code fetch to the same 256 byte page as the previous code fetch requires one state 2 a page miss requires two states 4Tosc ttt During a sequence of page hits PSEN remains low until the end of the last page hit cycle A4213 02 Figure 13 27 External Bus Cycle Timing Code Fetch in Page Mode 13 29 EXTERNAL MEMORY INTERFACE RD PSEN P2 PO A16 A17 The value of this paramete
209. WDT initiated reset signals are combined internally For an ex ternal reset the voltage on the RST pin must be held high for 64T For WDT initiated resets 5 bit counter in the reset logic maintains the signal for the required 64 The CPU checks for the presence of the combined reset signal every 2Tosc When a reset is de tected the CPU responds by triggering the internal reset routine The reset routine loads the SFR s with their reset values see Table 3 5 on page 3 17 Reset does not affect on chip data RAM or the register file However following a cold start reset these are indeterminate because has fallen too low or has been off Following a synchronizing operation and the configuration fetch the CPU vectors to address FF 0000 Figure 11 5 shows the reset timing sequence 11 6 intel MINIMUM HARDWARE SETUP While the RST pin is high ALE PSEN and the port pins are weakly pulled high The first ALE occurs 32Tosc after the reset signal goes low For this reason other devices can not be synchro nized to the internal timings of the 8XC251Sx NOTE Externally driving the ALE and or PSEN pins to 0 during the reset routine may cause the device to go into an indeterminate state Powering up the 8 2515 without a reset may improperly initialize the program counter and SFRs and cause the CPU to execute instructions from an undetermined memory location 11 4 4 Power on Reset To automatically generate a reset
210. addr to word reg 4 4 3 3 Rm dir16 Dir addr 64K to byte reg 5 3 4 2 WRj dir16 Dir addr 64K to word reg 5 4 4 3 Rm WRj Indir addr 64K to byte reg 4 2 3 2 Rm DRk Indir addr 16M to byte reg 4 4 3 3 WRjd WRijs Indir addr 64K to word reg 4 4 3 3 WRj DRk Indir addr 16M to word reg 4 5 3 4 dir8 Rm Byte reg to dir addr 4 4 3 3 3 3 dir8 WRj Word reg to dir addr 4 5 3 4 MOV dir16 Rm Byte reg to dir addr 64K 5 4 4 3 dir16 WRj Word reg to dir addr 64K 5 5 4 4 WRj Rm Byte reg to indir addr 64K 4 4 3 3 DRk Rm Byte reg to indir addr 16M 4 5 3 4 WRid WRijs Word reg to indir addr 64K 4 5 3 4 DRk WRj Word reg to indir addr 16M 4 6 3 5 dir8 DRk Dword reg to dir addr 4 7 3 6 dir16 DRk Dword reg to dir addr 64K 5 7 4 6 Rm WRi dis16 Indir addr with disp 64K to byte reg 5 6 4 5 WRj WRij dis16 Indir addr with disp 64K to word reg 5 7 4 6 Rm GDRk dis24 Indir addr with disp 16M to byte reg 5 7 4 6 WRj DRk dis24 Indir addr with disp 16M to word reg 5 8 4 7 WRi dis16 Rm_ Byte reg to Indir addr with disp 64K 5 6 4 5 NOTES 1 Ashaded cell denotes an instruction in the MCS 51 architecture 2 Instructions that move bits in Table A 26 on page A 23 3 fthis instruction addresses an I O port x 0 3 add 1 to the number of states 4 External memory addressed by instructions in the MCS 51 architecture is in the region specified by DPXL reset value 01H See Compatibility with the MCS 51
211. ags A 122 Binary Mode Encoding Source Mode Encoding RL 1 lt A a A 0 lt A 7 Rotate accumulator left through the carry flag Rotates the eight bits in the accumulator and the CY flag one bit to the left Bit 7 moves into the CY flag position and the original state of the CY flag moves into bit O position OV N 2 V The accumulator contains OC5H 11000101B and the CY flag is clear After executing the instruction RLC A the accumulator contains 8AH 10001010B and the CY flag is set Binary Mode Source Mode 1 1 1 1 0011 0011 Binary Mode Encoding Source Mode Encoding RLC 1 lt A a A 0 lt CY A 7 Rotate accumulator right Rotates the 8 or 16 bits in the accumulator one bit to the right Bit 0 is moved into the bit 7 or 15 position CY AC OV N 2 intel Example Bytes States Encoding Hex Code in Operation RRCA Function Description Flags Example Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE The accumulator contains 0C5H 11000101B After executing the instruction RRA the accumulator contains OE2H 11100010B and the CY flag is unaffected Binary Mode Source Mode 1 1 1 1 0000 0011 Binary Mode Encoding Source Mode Encoding RR lt A a41
212. ait state and a short ALE not extended and accesses a port SFR Case 3 Code executes from external memory with one wait state and a short ALE not extended and accesses a port SFR e Case 4 Code executes from external memory with one wait state and an extended ALE and accesses a port SFR The times for Cases 1 through 4 are expressed as the number of state times to add to the state times for given for Case 0 INSTRUCTION SET REFERENCE Table A 18 State Times to Access the Port SFRs Instruction Case 0 Execution Times Additional State Times Binary Source Case 1 Case 2 Case 3 Case 4 ADD A dir8 1 1 Co A ADD Rm dir8 3 2 ADDC A dir8 ANL A dir8 ANL CY bit ANL CY bit51 ANL CY bit ANL CY bit51 ANL dir8 data ANL dir8 A ANL Rm dir8 CLR bit CLR bit51 mnm CMP an CPL bit CPL bit51 DEC dir8 INC dir8 MINI Mm AJOIN HR O N PO MI WO MI WO MP MY PO PM MY PP MOV A dir8 MOV bit CY MOV bit51 CY CY bit w N A m m c MOV CY bit51 k E MOV dir8 data MOV dir8 A MOV dir8 Rm MOV dir8 Rn MOV Rm dir8 w N n MOV Rn dir8 MINIUNI o ORL A dir8 ORL CY bit ORL CY bit51 ORL
213. al interrupts if the in struction in progress is a RETI or any write to IEO IPHO or IPLO The complete polling cycle is repeated each four state times 6 7 2 5 Interrupt Vector Cycle When an interrupt vector cycle is initiated the CPU breaks the instruction stream sequence re solves all instruction pipeline decisions and pushes multiple program counter PC bytes onto the stack The CPU then reloads the PC with a start address for the appropriate ISR The number of bytes pushed to the stack depends upon the INTR bit in the UCONFIGI Figure 4 4 or CONFIGI Figure 4 6 configuration bytes The complete sample poll request and context switch vector sequence is illustrated in the interrupt latency timing diagram see Figure 6 5 on page 6 9 NOTE If the interrupt flag for a level triggered external interrupt is set but denied for one of the above conditions and is clear when the blocking condition is removed then the denied interrupt is ignored In other words blocked interrupt requests are not buffered for retention 6 14 l ntel INTERRUPT SYSTEM 6 7 3 ISRsin Process ISR execution proceeds until the RETI instruction is encountered The RETI instruction informs the processor the interrupt routine is completed The RETI instruction in the ISR pops PC address bytes off the stack as well as PSW1 for INTR 1 and execution resumes at the suspended in struction stream NOTE Some programs written for MCS 51 microcontrollers us
214. ample Move external Transfers data between the accumulator and a byte in external data RAM There are two types of instructions One provides an 8 bit indirect address to external data RAM the second provides a 16 bit indirect address to external data RAM In the first type of MOVX instruction the contents of RO or R1 in the current register bank provides an 8 bit address on port 0 Eight bits are sufficient for external I O expansion decoding or for a relatively small RAM array For larger arrays any port pins can be used to output higher address bits These pins would be controlled by an output instruction preceding the MOVX In the second type of MOVX instruction the data pointer generates a 16 bit address Port 2 outputs the upper eight address bits from DPH while port 0 outputs the lower eight address bits from DPL For both types of moves in nonpage mode the data is multiplexed with the lower address bits on port 0 In page mode the data is multiplexed with the contents of P2 on port 2 8 bit address or with the upper address bits on port 2 16 bit address It is possible in some situations to mix the two MOVX types A large RAM array with its upper address lines driven by P2 can be addressed via the data pointer or with code to output upper address bits to P2 followed by a MOVX instruction using RO or R1 CY AC OV The MCS 251 controller is operating in nonpage mode An external 256 byte RAM us
215. and dword registers Word register OG WRj 0 2 4 30 The 16 bit address in WRj can access locations 00 0000H 00 FFFFH Dword register k 0 4 8 28 56 and 60 The 24 least significant bits can access the entire 16 Mbyte address space The upper eight bits of must be 0 If you use DR60 as a general data pointer be aware that DR60O is the extended stack pointer register SPX MCS 51 architecture Instructions use indirect addressing to access on chip RAM code memory and external data RAM See the note on page 5 5 regarding the region of external data RAM that is addressed by instructions in the MCS 51 architecture Byte register Ri i 1 2 Registers RO and indirectly address on chip memory locations and the lowest 256 bytes of external data RAM 16 bit data pointer 9 DPTR or A DPTR The MOVC and MOV lt X instructions use these indirect modes to access code memory and external data RAM 16 bit program counter A PC The MOVC instruction uses this indirect mode to access code memory 5 6 intel PROGRAMMING Table 5 4 Addressing Modes for Data Instructions in the MCS 251 Architecture Address Range of Assembly Language Mode Operand Notation Comments RO R7 WRO WR6 DRO and 00 0000H 00 001FH Register RO R15 WRO WR30 DR2 are in the register bank egiste RO R7 WRO WR3 DRO DR28 DR56 DR60 curre
216. are capture modules See Figure 9 9 on page 9 16 For a list of SFRs associated with the PCA see Table 9 1 For an SFR address map see Table 3 5 on page 3 17 Port 1 provides external I O for the PCA on a shared basis with other functions Table 9 2 identifies the port pins associated with the timer counter and compare capture modules When not used for PCA I O these pins can be used for standard I O functions The operating modes of the five compare capture modules determine the functions performed by the PCA Each module can be independently programmed to provide input capture output com pare or pulse width modulation Module 4 only also has a watchdog timer mode The PCA timer counter and the five compare capture modules share a single interrupt vector The EC bit in the IE special function register is a global interrupt enable for the PCA Capture events compare events in some modes and PCA timer counter overflow set flags in the CCON register Setting the overflow flag CF generates a PCA interrupt request if the PCA timer counter inter rupt enable bit ECF in the CMOD register is set Figure 9 1 Setting a compare capture flag generates a PCA interrupt request if the ECCFx interrupt enable bit in the corresponding CCAPMXx register is set Figures 9 2 and 9 3 For a description of the 8XC251Sx interrupt sys tem see Chapter 6 Interrupt System 9 1 PROGRAMMABLE COUNTER ARRAY intel 9 2 TIMER COUNTER Figu
217. at contains data to be driven out from the port 3 pins Read modify write instructions that read port 3 read this register Other instructions that read port 3 read the port 3 pins 0 P3 Contents Bit Bit Number Mnemonic Function 7 0 P3 7 0 Port 3 Register Write data to be driven onto the port 3 pins to these bits C 20 intel REGISTERS PCON Address 5 87 Reset State 00 0000 Power Control Register Contains the power off flag POF and bits for enabling the idle and powerdown modes Also contains two general purpose flags and two bits that control serial I O functions the double baud rate bit and a bit that selects whether accesses to SCON 7 to the FE bit or the SMO bit 7 0 SMOD1 SMODO POF GF1 GFO PD IDL Bit Bit Number Mnemonic Function 7 SMOD1 Double Baud Rate Bit When set doubles the baud rate when timer 1 is used and mode 1 2 or 3 is selected in the SCON register See Baud Rates on page 10 10 6 SMODO SCON 7 Select When set read write accesses to SCON 7 are to the FE bit When clear read write accesses to SCON 7 are to the SMO bit See Figure 10 2 on page 10 3 5 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 4 POF Power Off Flag Set by hardware as Vcc rises above 3 V to indicate that power has been off or Vcc had fallen below 3 V and that on chi
218. at includes the first byte of the next instruction addr24 The target address can be anywhere in the 16 Mbyte address space Indirect addressing There are two types of indirect addressing for control instructions For the instructions LCALL WRj and LJMP WR the target address is in the current 64 Kbyte region The 16 bit address in WRj is placed in the lower 16 bits of the PC The upper eight bits of the PC remain unchanged from the address of the next instruction For the instruction JMP A DPTR the sum of the accumulator and DPTR is placed in the lower 16 bits of the PC and the upper eight bits of the PC are FF which restricts the target address to the code memory space of the MCS 51 architecture Table 5 8 Addressing Modes for Control Instructions Description Address Range Relative 8 bit relative address rel 8 128 to 127 from first byte of next instruction Direct 11 bit target address addr11 11 Current 2 Kbytes Direct 16 bit target address addr16 16 Current 64 Kbytes Direct 24 bit target address addr24 t 24 00 0000H FF FFFFH Indirect WRi t 16 Current 64 Kbytes Indirect A DPTR 16 e 1 specified by DPXL reset These modes are not used by instructions in the MCS 51 architecture 5 13 PROGRAMMING intel 5 5 2 Conditional Jumps The MCS 251 architecture supports bit conditional jumps compare conditional jumps and jumps based on the value of the accum
219. ate external memory operations Port 0 drives the lower address byte onto the parallel address bus and port 2 drives the upper ad dress byte onto the bus In nonpage mode the data is multiplexed with the lower address byte on port 0 In page mode the data is multiplexed with the upper address byte on port 2 All port 1 and port 3 pins serve for both general purpose I O and alternate functions see Table 7 1 Table 7 1 Input Output Port Pin Descriptions us Type Alternate Description TEES 0 7 0 AD7 O Address Data Lines Nonpage Mode Address Lines Page Mode VO P1 0 VO T2 Timer 2 Clock Input Output yo P1 1 VO 2 Timer 2 External Input 1 2 VO ECI PCA External Clock Input P1 3 CEXO PCA Module 0 I O 1 4 VO CEX1 PCA Module 1 I O yo P1 5 2 PCA Module 2 I O yo P1 6 PCA Module 3 I O P1 7 CEX4 A17 PCA Module 4 I O or 18th Address Bit 2 7 0 VO A15 8 Address Lines Nonpage Mode Address Data Lines Page Mode VO P3 0 VO RXD Serial Port Receive Data Input I I O P3 1 VO TXD Serial Port Transmit Data Output O O P3 2 VO INTO External Interrupt 0 VO External Interrupt 1 l P3 4 VO Timer 0 Input l P3 5 VO T1 Timer 1 Input 1 P3 6 VO WR Write Signal to External Memory P3 7 RD A16 Read Signal to External Memory or 17th Address Bit
220. ation MOV A 88 Rm data intel INSTRUCTION SET REFERENCE MOV WRi data16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0111 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV lt data16 MOV DRk 0data16 Binary Mode Source Mode Bytes 5 4 States 5 4 Encoding 0111 1110 uuuu 1000 hi low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk 0data16 MOV DRk 1data16 Binary Mode Source Mode Bytes 5 4 States 5 4 Encoding 0111 1110 uuuu 1100 hi low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk 1data16 A 89 INSTRUCTION SET REFERENCE intel MOV Rm dir8 Binary Mode Source Mode Bytes 4 3 States 3t 2t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0111 1110 5555 0001 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm lt dir8 MOV WRj dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0111 1110 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj
221. ator Ceramic Resonator 11 4 1215338 External GloGk i mul DERI qu IR 11 4 11 4 CARES Eee cs ec MC MeL eb i 11 5 11 4 1 Externally Initiated Resets 80 nainen 11 6 11 4 2 WDT Initiated Resets eni a a a e r aa a 11 6 vii intel 11 4 3 Reset Operation esnin nein eee eie Lee te e eene decies 11 6 11 4 4 Power onifeset cepi tra enter der e esa er cen rte da 11 7 CHAPTER 12 SPECIAL OPERATING MODES 1231 GENERAL ien ener eeiam e 12 1 12 2 POWER CONTROL REGISTER 12 1 12 2 1 Serial l O Control Bits eene enne 12 1 12 2 2 Power Off Flag nete n ded e ted n iege a bugs 12 1 12 3 IDLE MODE ioni ihe be ater eh aie c mendo eta 12 4 12 31 Entering Idle Mode eset deest ede cerent denote 12 4 12 3 2 Exiting Idle Mode torte et a aad 12 5 12 4 POWERDOWN 4 2220004044 nnn 12 5 12 41 Entering Powerdown Mode 12 6 12 4 2 Exiting Powerdown Mode 12 6 12 5 ON CIRCUIT EMULATION ONCE MODE eene 12 7 12 51 Entering ONCE Mode edd eed de db er aie eet 12 7 12 5 2 Exiting ONCE MOJE eiie ERR BU edente tete ru qoibus 12 7 CHAPTER 13 EXTERNAL MEMORY INTERFACE 13A OVERVIEW iiie ctii inm nn ene ete
222. bit timer which is set up as an 8 bit timer THO register with a modulo 32 prescaler implemented with the lower five bits of the TLO register Figure 8 2 The upper three bits of the TLO register are indeterminate and should be ignored Prescaler overflow increments the THO register Interrupt THx TLx Request 8 Bits 8 Bits Mode 0 13 bit Timer Counter Mode 1 16 bit Timer Counter GATEx 00 1 4110 02 Figure 8 2 Timer 0 1 in Mode 0 and Mode 1 8 4 intel TIMER COUNTERS AND WATCHDOG TIMER 8 3 2 Mode 1 16 bit Timer Mode 1 configures timer 0 as a 16 bit timer with THO and TLO connected in cascade Figure 8 2 The selected input increments TLO 8 3 3 Mode 2 8 bit Timer With Auto reload Mode 2 configures timer 0 as an 8 bit timer TLO register that automatically reloads from the THO register Figure 8 3 TLO overflow sets the timer overflow flag in the TCON register and reloads TLO with the contents of THO which is preset by software When the interrupt re quest is serviced hardware clears The reload leaves THO unchanged See Auto load Setup Example on page 8 9 Interrupt Overflow Request A4111 02 Figure 8 3 Timer 0 1 in Mode 2 Auto Reload 8 3 4 Mode 3 Two 8 bit Timers Mode 3 configures timer O such that registers TLO and THO operate as separate 8 bit timers Fig ure 8 4 This mode is provided for applications requiring an additi
223. bled by bit ES in the IEO register see Figure 6 2 on page 6 6 6 5 INTERRUPT ENABLE Each interrupt source with the exception of TRAP may be individually enabled or disabled by the appropriate interrupt enable bit in the IEO register at S A8H see Figure 6 2 on page 6 6 Note also contains a global disable bit EA If EA is set interrupts are individually enabled or dis abled by bits in If EA is clear all interrupts are disabled 6 5 intel INTERRUPT SYSTEM IEO Address S A8H Reset State 0000 0000B 7 0 EA EC ET2 ES ET1 EX1 ETO EXO NU Function 7 EA Global Interrupt Enable Setting this bit enables all interrupts that are individually enabled by bits 0 6 Clearing this bit disables all interrupts except the TRAP interrupt which is always enabled 6 EC PCA Interrupt Enable Setting this bit enables the PCA interrupt 5 ET2 Timer 2 Overflow Interrupt Enable Setting this bit enables the timer 2 overflow interrupt 4 ES Serial Port Interrupt Enable Setting this bit enables the serial I O port interrupt 3 ET1 Timer 1 Overflow Interrupt Enable Setting this bit enables the timer 1 overflow interrupt 2 1 External Interrupt 1 Enable Setting this bit enables external interrupt 1 1 ETO Timer 0 Overflow Interrupt Enable Setting this bit enables the timer 0 overflow interrupt 0 EXO External Interrupt 0 Enable Setting this bit enables exter
224. ce A 75 INSTRUCTION SET REFERENCE Flags Example Bytes States Encoding Hex Code in Operation JNZ rel Function Description Flags Example A 76 CY AC OV N The instruction JNE LABEL1 causes program execution to continue at LABEL1 if the Z flag is clear Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0111 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JNE PC PC 2 IF Z 0 THEN PC lt PC rel Jump if accumulator not zero If any bit of the accumulator is set branch to the specified address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified CY AC The accumulator contains OOH After executing the instruction sequence JNZ LABEL1 INCA JNZ LABEL2 the accumulator contains 01H and program execution continues at label LABEL2 intel Bytes States Encoding Hex Code in Operation JSG rel Function Description Flags Example Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Source Mode Not Taken Taken Not Taken Taken 2 2 2 2 2 5 2 5 0111 0000 rel addr Binary Mode
225. ce Mode Bytes 5 4 States 4 3 Encoding 0111 1010 5555 0011 direct addr direct addr A 93 INSTRUCTION SET REFERENCE Hex Code in Operation MOV dir16 WRj Binary Mode A5 Encoding Source Mode Encoding MOV dir16 lt Binary Mode Source Mode Bytes 5 4 States 5 4 Encoding 0111 1010 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV dir16 lt WRj MOV dir16 DRk Binary Mode Source Mode Bytes 5 4 States 7 6 Encoding 0111 1010 uuuu 1111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV dir16 lt MOV WRj Rm Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0111 1010 tttt 1001 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV A 94 WRj lt Rm intel INSTRUCTION SET REFERENCE MOV DRk Rm Binary Mode Source Mode Bytes 4 3 States 5 4 Encoding 0111 1010 uuuu 1011 SSSS 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRK Rm MOV WRijd WRjs Binary Mode Source Mode Bytes 4 3 States 5 4 Encoding 0001 1011 tttt 1000 TT TT 0000 H
226. cern User instructions activate these modes by setting bits in the PCON reg ister Program execution halts but resumes when the mode is exited by an interrupt While in idle or power down the Vec pin is the input for backup power ONCE is a test mode that electrically isolates the 8XC251Sx from the system in which it operates 12 2 POWER CONTROL REGISTER The PCON special function register Figure 12 1 provides two control bits for the serial I O function bits for selecting the idle and powerdown modes the power off flag and two general purpose flags 12 2 1 Serial I O Control Bits The SMODI bit in the PCON register is a factor in determining the serial I O baud rate See Fig ure 12 1 and Baud Rates on page 10 10 The SMOD O bit in the PCON register determines whether bit 7 of the SCON register provides read write access to the framing error FE bit SMODO 1 or to SMO a serial I O mode select bit SMODO 0 See Figure 12 1 and Figure 10 2 SCON Serial Port Control Register on page 10 3 12 2 2 Power Off Flag Hardware sets the Power Off Flag POF in PCON when Vcc rises from 3 V to 3 V to indicate that on chip volatile memory is indeterminate e g at power on The POF can be set or cleared by software In general after a reset check the status of this bit to determine whether a cold start reset or a warm start reset occurred see Reset on page 11 5 After a cold start user software should clear the POF I
227. ch pointer length NOTE In the following discussion external interrupt request pins are assumed to be inactive for at least four state times prior to assertion In this chapter all external hardware signals maintain some setup period 1 less than one state time Signals must meet Vm and Vu specifications prior to any state time under discussion This setup state time is not included in examples or calcula tions for either response or latency 6 9 INTERRUPT SYSTEM intel 6 7 4 Minimum Fixed Interrupt Time interrupts are sampled or polled every four state times see Figure 6 5 on page 6 9 Two of eight interrupts are latched and polled per state time within any given four state time window One additional state time is required for a context switch request For code branches to jump lo cations in the current 64 Kbyte memory region compatible with MCS 51 microcontrollers the context switch time is 11 states Therefore the minimum fixed poll and request time is 16 states 4 poll states 1 request state 11 states for the context switch 16 state times Therefore this minimum fixed period rests upon four assumptions The source request is an internal interrupt with high enough priority to take precedence over other potential interrupts The request is coincident with internal execution and needs no instruction completion time The program uses an internal stack location and The ISR is in on chip OTPROM ROM
228. coding ANL dir8 lt dir8 A A A 35 INSTRUCTION SET REFERENCE ANL dir8 data Binary Mode Source Mode Bytes 3 3 States 3t 3t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0101 0011 direct addr immed data Hex Code in Binary Mode Encoding Source Mode Encoding Operation ANL dir8 lt dir8 A data ANL A data Binary Mode Source Mode Bytes 2 2 States 1 1 Encoding 0101 0100 immed data Hex Code in Binary Mode Encoding Source Mode Encoding Operation ANL A data ANL A dir8 Binary Mode Source Mode Bytes 2 2 States 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0101 0101 direct addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation ANL A A dir8 A 36 intel ANL A Ri Binary Mode Source Mode Bytes 1 2 States 2 3 Encoding 0101 011i Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation ANL lt A A Ri INSTRUCTION SET REFERENCE ANL A Rn Binary Mode Source Mode Bytes 1 2 States 1 2 Encoding 0101 irrr Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation ANL lt Rn ANL Rmd Rms Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding
229. compare capture register toggles the CEXx pin 1 PWMx Pulse Width Modulation Mode PWMx 1 configures the module for operation as an 8 bit pulse width modulator with output waveform on the pin 0 ECCFx Enable CCFx Interrupt Enables compare capture flag CCFx in the CCON register to generate an interrupt request Figure 9 9 CCAPMx PCA Compare Capture Module Mode Registers intel 10 Serial I O Port intel CHAPTER 10 SERIAL I O PORT The serial input output port supports communication with modems and other external peripheral devices This chapter provides instructions on programming the serial port and generating the se rial I O baud rates with timer and timer 2 10 1 OVERVIEW The serial I O port provides both synchronous and asynchronous communication modes It oper ates as a universal asynchronous receiver and transmitter UART in three full duplex modes modes 1 2 and 3 Asynchronous transmission and reception can occur simultaneously and at different baud rates The UART supports framing bit error detection multiprocessor communi cation and automatic address recognition The serial port also operates in a single synchronous mode mode 0 The synchronous mode mode 0 operates at a single baud rate Mode 2 operates at two baud rates Modes 1 and 3 operate over a wide range of baud rates which are generated by timer 1 and timer 2 Baud rates are detailed in Baud Rates on page 10
230. contain 12H and OFEH respectively After the instruction sequence INC DPTR INC DPTR INC DPTR DPH and DPL contain 13H and 01H respectively Binary Mode Source Mode 1 1 1 1 1010 0011 Binary Mode Encoding Source Mode Encoding INC DPTR DPTR 1 Jump if bit set If the specified bit is a one jump to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified CY AC OV N 2 67 INSTRUCTION SET REFERENCE intel Example Input port 1 contains 11001010B and the accumulator contains 56 01010110B After the instruction sequence JB P1 2 LABEL1 JB ACC 2 LABEL2 program execution continues at label LABEL2 Variations JB bit51 rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 2 5 2 5 Encoding 0010 0000 bit addr rel addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation JB PC PC 3 IF bit51 1 THEN PC PC rel JB bit rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 5 5 4 4 States 4 7 3 6 Encoding 1010 1001 0010 0 yy direct addr rel addr Hex Code in Binary Mod
231. current instruction to complete The actual latency is 26 states Worst case latency calculations predict 43 states for this example due to inclusion of total DIV instruction time less one state Table 6 7 Actual vs Predicted Latency Calculations Latency Factors Actual Predicted Base Case Minimum Fixed Time 16 16 INTO External Request 1 1 External Execution 2 64K Byte Stack Location 4 Execution Time for Current DIV Instruction 3 20 TOTAL 26 43 INTERRUPT SYSTEM intel 6 7 2 4 Blocking Conditions If all enable and priority requirements have been met a single prioritized interrupt request at a time generates a vector cycle to an interrupt service routine see CALL instructions Appendix A Instruction Set Reference There are three causes of blocking conditions with hardware gen erated vectors 1 An interrupt of equal or higher priority level is already in progress defined as any point after the flag has been set and the RETI of the ISR has not executed 2 Thecurrent polling cycle is not the final cycle of the instruction in progress 3 The instruction in progress is RETI or any write to the IEO IPHO or IPLO registers Any of these conditions blocks calls to interrupt service routines Condition two ensures the in struction in progress completes before the system vectors to the ISR Condition three ensures at least one more instruction executes before the system vectors to addition
232. d UCONFIGI FF FFF9H are implemented the remaining bytes are reserved for future use See Figures 4 1 4 3 and 4 4 The A stepping 83C251SB and 87C251SB store configuration information in nonvolatile mem ory outside the memory address space CONFIGO 80H and CONFIGI 81H are implemented two additional bytes at 82H and 83H are reserved for future use See Figures 4 2 4 5 and 4 6 To program the 87C251Sx configuration bytes perform the procedure described in Program ming Algorithm on page 14 6 using the B stepping or A stepping program configuration byte mode Table 14 1 To verify the 87C251Sx 83C251Sx or 80C251SB SQ configuration bytes perform the proce dure described in Verify Algorithm on page 14 7 using the B stepping or A stepping verify configuration byte mode Table 14 1 14 6 3 Lock Bit System The 87 2515 provides a three level lock system for protecting user program code stored in the on chip code memory from unauthorized access On the 83 2515 only protection is avail able Table 14 2 describes the levels of protection To program the lock bits perform the procedure described in Programming Algorithm on page 14 6 using the program lock bits mode Table 14 1 To verify that the lock bits are correctly programmed perform the procedure described in Verify Algorithm on page 14 7 using the verify lock bits mode Table 14 1 14 8 intel PROGRAMMING AND VERIFYING NONVOLATILE ME
233. d the highest priority In addition the duration of the interrupt must be of sufficient length to allow the oscillator to stabilize Generate a reset See Reset on page 11 5 A logic high on the RST pin clears the PD bit in the PCON register directly and asynchronously This starts the oscillator and restores the clocks to the CPU and peripherals Program execution momentarily resumes with the instruction immediately following the instruction that activated powerdown and may continue for a number of clock cycles before the internal reset algorithm takes control Reset initializes the 8 2515 and vectors the CPU to address FF 0000H NOTE During the time that execution resumes the internal RAM cannot be accessed however it is possible for the port pins to be accessed To avoid unexpected outputs at the port pins the instruction immediately following the instruction that activated the powerdown mode should not write to a port pin or to the external RAM 12 6 intel SPECIAL OPERATING MODES 12 5 ON CIRCUIT EMULATION ONCE MODE The on circuit emulation ONCE mode permits external testers to test and debug 8 2515 based systems without removing the chip from the circuit board A clamp on emulator or test CPU is used in place of the 8XC251Sx which is electrically isolated from the system 12 5 4 Entering ONCE Mode To enter the ONCE mode 1 Assert RST to initiate a device reset See Externally Initiated Resets on pag
234. d transmits serial data in serial modes 1 2 and 3 P3 1 Voc PWR Supply Voltage Connect this pin to the 5V supply voltage Voca PWR Secondary Supply Voltage 2 This supply voltage connection is pro vided to reduce power supply noise Connection of this pin to the 5V supply voltage is recommended However when using the 8XC251SB as a pin for pin replacement for the 8XC51FX Vas can be uncon nected without loss of compatibility Not available on DIP Programming Supply Voltage The programming supply voltage is applied to this pin for programming on chip nonvolatile memory EA GND Circuit Ground Connect this pin to ground GND Secondary Ground This ground is provided to reduce ground bounce and improve power supply bypassing Connection of this pin to ground is recommended However when using the 8XC251SA SB SP SQ as a pin for pin replacement for the 8XC51BH 4 can be unconnected without loss of compatibility Not available on Vss2 WR GND Secondary Ground 2 This ground is provided to reduce ground bounce and improve power supply bypassing Connection of this pin to ground is recommended However when using the 8XC251SB as a pin for pin replacement for the 8XC51FX Vaso can be unconnected without loss of compatibility Not available on DIP Write Write signal output to external memory Asserted for the mem ory address range specified by configuration bi
235. d value from the formula and enter in the RCAP2H RCAP2L registers 4 Enter a 16 bit initial value in timer register TH2 TL2 This can be the same as the reload value or different depending on the application 5 start the timer set the TR2 run control bit in T2CON Operation is similar to timer 2 operation as a baud rate generator It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously For this configuration the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers 8 14 intel TIMER COUNTERS AND WATCHDOG TIMER TH2 8 Bits Interrupt Request T2EX 7 g EXEN2 4116 02 Figure 8 10 Timer 2 Clock Out Mode Table 8 3 Timer 2 Modes of Operation Mode RCLK OR TCLK CP RL2 T20E in 2 in T2CON in T2MOD Auto reload Mode 0 0 0 Capture Mode 0 1 0 Baud Rate Generator Mode 1 X X Programmable Clock Out X 0 1 8 15 TIMER COUNTERS AND WATCHDOG TIMER intel T2MOD Address S C9H Reset State XXXX XX00B 7 0 2 Bit Bit Number Mnemonic Function 7 2 Reserved The values read from these bits are indeterminate Do not write a 1 to these bits 1 2 Timer 2 Output Enable Bit In the timer 2 clock out mode connects the programmable clock output to external
236. ddition is performed CY AC OV N 2 intel INSTRUCTION SET REFERENCE Example The accumulator contains a number between 0 and 3 The following instruction sequence translates the value in the accumulator to one of four values defined by the DB define byte directive RELPC INC A MOVC 66 DB 77H DB 88H DB 99H If the subroutine is called with the accumulator equal to 01H it returns with 77H in the accumulator The INC A before the MOVC instruction is needed to get around the RET instruction above the table If several bytes of code separated the MOVC from the table the corresponding number would be added to the accumulator instead Variations MOVC A A PC Binary Mode Source Mode Bytes 1 1 States 6 6 Encoding 1000 0011 Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOVC PC PC 1 lt A MOVC A A DPTR Binary Mode Source Mode Bytes 1 1 States 6 6 Encoding 1001 0011 Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOVC lt A DPTR A 101 INSTRUCTION SET REFERENCE intel MOVH DRk data16 Function Description Flags Example Variations Move immediate 16 bit data to the high word of a dword double word register Moves 16 bit immediate data to the high word of a dword 32 bit register The low word of the dw
237. de scribes a minimum hardware setup Topics covered include power ground clock source and de vice reset For parameter values refer to the device data sheet 11 1 MINIMUM HARDWARE SETUP Figure 11 1 shows a minimum hardware setup that employs the on chip oscillator for the system clock and provides power on reset Control signals and Ports 0 1 2 and 3 are not shown See Clock Sources on page 11 3 and Power on Reset on page 11 7 8XC251Sx Note Voca is a secondary power pin that reduces power supply noise Vas and secondary ground pins that reduce ground bounce and improve power supply by passing Connections to these pins are not required for proper device operation A4141 02 Figure 11 1 Minimum Setup MINIMUM HARDWARE SETUP intel 11 2 ELECTRICAL ENVIRONMENT The 8XC251Sx is a high speed CHMOS device To achieve satisfactory performance its operat ing environment should accommodate the device signal waveforms without introducing distor tion or noise Design considerations relating to device performance are discussed in this section See the device data sheet for voltage and current requirements operating frequency and wave form timing 11 2 1 Power and Ground Pins Power the 8XC251Sx from a well regulated power supply designed for high speed digital loads Use short low impedance connections to the power Vcc and Vcc and ground and 2 pins is a secondary po
238. de gt 64K External External External Variable INT1 Executio Jump to Wait y Stack Stack Stack T2bX n ISR 1 State 64K 1 gt 64K 1 Wait State Number of 1 per 1 per States 1 2 1 bus cycle 8 bus cycle Added NOTES 1 lt 64 gt 64 means inside outside the 64 Kbyte memory region where code is executing 2 Base case fixed time is 16 states and assumes A 2 byte instruction is the first ISR byte 64K jump to ISR Internal peripheral interrupt Internal execution Internal stack 6 7 2 3 Latency Calculations Assume the use of a zero wait state external memory where current instructions the ISR and the stack are located within the same 64 Kbyte memory region compatible with memory maps for MCS 51 microcontrollers Further assume there are 3 states yet to complete in the current 21 state DIV instruction when INTO requests service Also assume INTO has made the request one state prior to the sample state as in Figure 6 7 on page 6 12 Unlike in Figure 6 7 the response time for this assumption is three state times as the current instruction completes in time for the branch to occur Latency calculations begin with the minimum fixed latency of 16 states From Table 6 6 one state is added for an INTO request from external hardware two states are added for external execution and four states for an external stack in the current 64 Kbyte region Final ly three states are added for the
239. de in Operation MOV dir8 dir8 Bytes States Encoding Hex Code in Operation A 84 Binary Mode Encoding Source Mode Encoding MOV dir8 lt data Binary Mode Source Mode 2 3 3 4 0111 011i immed data Binary Mode Encoding Source Mode A5 Encoding MOV Ri lt data Binary Mode Source Mode 2 3 1 2 0111 dirrrr immed data Binary Mode Encoding Source Mode A5 Encoding MOV Rn data Binary Mode Source Mode 3 3 3 3 1000 0101 direct addr direct addr Binary Mode Encoding Source Mode Encoding MOV dir8 lt dir8 intel MOV dir8 Ri Bytes States Encoding Hex Code in Operation MOV dir8 Rn Bytes States Encoding Hex Code in Operation MOV Ri dir8 Bytes States Encoding Hex Code in Operation MOV 8 Bytes States Encoding INSTRUCTION SET REFERENCE Binary Mode Source Mode 2 3 3 4 1000 0111 direct addr Binary Mode Encoding Source Mode A5 Encoding MOV dir8 lt Ri Binary Mode Source Mode 2 3 2t 3t tlf this instruction addresses a port Px x 0 3 add 1 state 1000 irrr direct addr Binary Mode Encoding Source Mode A5 Encoding MOV dir8 Rn Binary Mode Source Mode 2 3 3 4 1010 011i
240. de in Binary Mode A5 Encoding Source Mode Encoding Operation ADD WRj lt WRj dir8 ADD Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0010 1110 5555 0011 direct addr direct add Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD Rm dir16 ADD WRi dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0010 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding A 31 INSTRUCTION SET REFERENCE Operation ADD WRj WRj dir16 ADD Rm GWRj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0010 1110 tttt 1001 5556 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD Rm lt Rm WR ADD Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0010 1110 uuuu 1011 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD Rm lt Rm DRk ADDC lt gt Function Add with carry Description Simultaneously adds the specified byte variable the CY flag and the accumulator contents leaving the result in the accumulator If there is a carry out of bit 7 CY the CY flag is set if there is a carry out of bit 3 AC the AC flag is set When adding unsigned integers the CY flag indicates that a
241. dered a part of the general purpose 1 Kbyte on chip RAM locations 00 0020 00 041 3 12 intel ADDRESS SPACES 3 3 4 Byte Word and Dword Registers Depending on its location in the register file a register is addressable as a byte a word and or a dword as shown on the right side of Figure 3 6 A register is named for its lowest numbered byte location For example R4 is the byte register consisting of location 4 WRA is the word register consisting of registers 4 and 5 is the dword register consisting of registers 4 7 Locations RO R15 are addressable as bytes words or dwords Locations 16 31 are addressable only as words or dwords Locations 56 63 are addressable only as dwords Registers are ad dressed only by the names shown in Figure 3 6 except for the 32 registers that comprise the four banks of registers RO R7 which can also be accessed as locations 00 0000H 00 001FH in the memory space 3 3 2 Dedicated Registers The register file has four dedicated registers e R10 is the B register e R11 is the accumulator ACC DR56is the extended data pointer DPX DR60 is the extended stack pointer SPX These registers are located in the register file however R10 R11 and some bytes of DR56 and DR60 are also accessible as SFRs The bytes of DPX and SPX can be accessed in the register file only by addressing the dword registers The dedicated registers in the register file and their cor resp
242. des Continued Mode RST PSEN Vpp PROG Port Port Address Notes 0 2 Port 1 high Port 3 low Verify Mode A stepping High Low 5V High 29H data 0030H 0031H Signature Bytes 0060H 87C251SB 83 2515 Verify Mode B stepping High Low 5V High 29H data 0030H 0031H Signature Bytes 0060H 87 62515 83 2515 0061 NOTES 1 To program raise to 12 75 V and pulse the PROG pin See Figure 14 2 for waveforms 2 No data input Identify the lock bits with the address lines as follows LB3 0003H LB2 0002H LB1 0001H 3 three lock bits are verified a single operation The states of the lock bits appear simultaneously at port 2 as follows LB3 P2 3 LB2 P2 2 LB1 P2 1 High programmed 4 For the case of B stepping devices used as A stepping compatible specify the configuration in UCONFIGO and UCOMFIG1 5 Forthese modes the internal address is FF xxxxH 8 2515 Vg RST Address 16 Bits Data 8 Bits EA V pp XTAL1 ALE PROG Coe 4 MHz io a PSEN 6 MHz Program Verify Mode 8 Bits A4122 02 Figure 14 1 Setup for Programming and Verifying Nonvolatile Memory 14 5 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY intel 14 4 PROGRAMMING ALGORITHM The procedure for programming 87C251Sx is as follows 1 Set up the controller for operation in the appropriate mode according to Table 14 1 Input t
243. des 2 and 3 SM2 set Set or cleared by hardware to reflect the ninth data bit received C 28 intel REGISTERS SCON Address 98H Reset State 0000 0000B Serial Port Control Register SCON contains serial I O control and status bits including the mode select bits and the interrupt flag bits 7 FE SMO SM1 SM2 REN TB8 RB8 TI RI Bit Number Bit Mnemonic Function 1 TI Transmit Interrupt Flag Bit Set by the transmitter after the last data bit is transmitted Cleared by software RI Receive Interrupt Flag Bit Set by the receiver after the last data bit of a frame has been received Cleared by software C 29 REGISTERS intel SP Address Reset State 0000 0111B Stack Pointer SP provides SFR access to location 63 in the register file also named SP SP is the lowest byte of the extended stack pointer SPX DR60 The extended stack pointer points to the current top of stack When a byte is saved PUSHed on the stack SPX is incremented and then the byte is written to the top of stack When a byte is retrieved POPped from the stack it is copied from the top of stack and then SPX is decremented 7 0 SP Contents Bit Bit Number Mnemonic Function 7 0 SP 7 0 Stack Pointer Bits 0 7 of the extended stack pointer SPX DR60 C 30 inte
244. description also applies to the A stepping of the 8XC251SB Memory Space for the A stepping of the 8XC251SB on page 3 10 describes the differences between the memory spaces for the A stepping and the B stepping of the 8XC251SB Figure 3 4 shows the logical memory space for the 8XC251Sx microcontroller The usable mem ory space of the 8XC251Sx consists of eight 64 Kbyte regions 00 01 02 03 FD FE and FF Code can execute from all eight regions code execution begins at FF 0000H Regions 04 are reserved Reading a location in the reserved area returns an unspecified value Soft ware can execute a write to the reserved area but nothing is actually written Although the memory space comprises eight regions not all of these regions are available at the same time The maximum number of external address lines is 18 which limits external memory to a maximum of four regions 256 Kbytes See Configuring the External Memory Interface on page 4 11 and External Memory Design Examples on page 13 12 3 5 ADDRESS SPACES Memory Address Space 16 Mbytes FF FFF8H A 8 Byte Configuration Array FF FFF7H FF 0000H FE 0000H FD 0000H Regions 04 are Reserved 03 FFFFH Indirect and Displacement 03 0000H Addressing 16 Mbytes 02 0000H 01 0000H Direct Addressing 64 Kbytes 00 0080H Y Bit Add Register 1655109 Addressing 96 Bytes 32 Bytes F A4101 02 3 6
245. dressable bit or its complement with the CY flag MOV Move instructions transfer any addressable bit to the carry CY bit or vice versa Bit conditional jump instructions execute a jump if the bit has a specified state The bit conditional jump instructions are classified with the control instructions and are described in Conditional Jumps on page 5 14 5 4 1 Bit Addressing The bits that can be individually addressed are in the on chip RAM and the SFRs Table 5 5 The bit instructions that are unique to the MCS 251 architecture can address a wider range of bits than the instructions from the MCS 51 architecture There are some differences in the way the instructions from the two architectures address bits In the MCS 51 architecture a bit denoted by bit51 can be specified in terms of its location within a certain register or it can be specified by a bit address in the range 00H 7FH The MCS 251 architecture does not have bit addresses as such A bit can be addressed by name or by its location within a certain register but not by a bit address Table 5 6 illustrates bit addressing in the two architectures by using two sample bits e RAMBIT is bit 5 in RAMREG which is location 23H WRAMBIT and are assumed to be defined in user code e TI is bit 2 in TCON which is an SFR at location 88H Table 5 5 Bit addressable Locations Bit addressable Locations Architecture On chip R
246. e A5 Encoding Source Mode Encoding Operation JB PC lt PC IF bit 1 A 68 PC lt PC rel intel JBC bit51 rel JBC bit rel Function Description Flags Example Variations JBC bit51 rel Bytes States Encoding Hex Code in Operation JBC bit rel Bytes States INSTRUCTION SET REFERENCE Jump if bit is set and clear bit If the specified bit is one branch to the specified address otherwise proceed with the next instruction The bit is not cleared if it is already a zero The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incre menting the PC to the first byte of the next instruction Note When this instruction is used to test an output pin the value used as the original data is read from the output data latch not the input pin CY AC OV N 2 The accumulator contains 56H 01010110B After the instruction sequence JBC ACC 3 LABEL1 JBC ACC 2 LABEL2 the accumulator contains 52H 01010010B and program execution continues at label LABEL2 Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 3 3 4 7 4 7 0001 0000 bit addr rel addr Binary Mode Encoding Source Mode Encoding JBC PC PC 3 IF bit51 1 THEN bitb1 0 PC rel Binary Mode Source Mode Not Taken Taken Not Taken Taken 5 5
247. e the instruction can set combinations of bits in any RAM location or hardware register The pattern of bits to be set is determined by a mask byte which may be a constant data value in the instruction or a variable computed in the accumulator at run time After executing the instruction ORL P1 00110010B sets bits 5 4 and 1 of output Port 1 Variations ORL dir8 A Binary Mode Source Mode Bytes 2 2 States 21 21 tlf this instruction addresses a port Px x 0 3 add 2 states Encoding 0100 0010 direct addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation ORL dir8 lt dir8 V A ORL dir8 data Binary Mode Source Mode Bytes 3 3 States 3t 3t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0100 0011 direct addr immed data Hex Code in Binary Mode Encoding Source Mode Encoding Operation ORL dir8 lt dir8 V data A 109 INSTRUCTION SET REFERENCE intel ORL A data Bytes States Encoding Hex Code in Operation ORL A dir8 Bytes States Encoding Hex Code in Operation ORL A Ri Bytes States Encoding Hex Code in Operation ORL A Rn Bytes States Encoding A 110 Binary Mode Source Mode 2 2 1 1 0100 0100 immed data Binary Mode Encoding Source Mode Encoding ORL lt A V stdata Binary Mode Source
248. e 11 6 and the reset waveforms in Figure 11 5 on page 11 8 2 While holding RST asserted apply and hold logic levels to I O pins as follows PSEN low P0 7 5 low P0 4 high P0 3 0 low 1 port 0 10H 3 Deassert RST then remove the logic levels from PSEN and port 0 These actions cause the 8XC251Sx to enter the ONCE mode Port 1 2 and 3 pins are weakly pulled high and port 0 ALE and PSEN pins are floating Table 12 1 Thus the device is elec trically isolated from the remainder of the system which can then be tested by an emulator or test CPU Note that in the ONCE mode the device oscillator remains active 12 5 2 Exiting ONCE Mode To exit ONCE mode reset the device 12 7 intel 13 External Memory Interface intel CHAPTER 13 EXTERNAL MEMORY INTERFACE This chapter describes the external memory interface and the external bus cycles Examples illus trate several types of external memory designs 13 1 OVERVIEW The external memory interface comprises the external bus ports 0 and 2 and the bus control sig nals Chip configuration bytes Chapter 4 Device Configuration determine several interface options page mode or nonpage mode for external code fetches the number of external address bits 16 17 or 18 the address ranges for RD WR and PSEN and the number of external wait states You can use these options to tailor the interface to your application See Configuring the External M
249. e 3 13 5 3 1 1 Register Addressing Both architectures address registers directly MCS 251 architecture In the register addressing mode the operand s in a data instruction in byte registers 15 word registers WR2 WR30 dword registers DRO DR4 DR28 DR56 DR60 MCS 51 architecture Instructions address registers RO R7 only 5 3 1 2 Immediate Both architectures use immediate addressing MCS 251 architecture In the immediate addressing mode the instruction contains the data operand itself Byte operations use 8 bit immediate data data word operations use 16 bit immediate data 16 Dword operations use 16 bit immediate data in the lower word and either zeros in the upper word denoted by 0datal6 or ones in the upper word denoted by 1 16 MOV instructions that place 16 bit immediate data into a dword register place the data either into the upper word while leaving the lower word unchanged or into the lower word with a sign extension or a zero extension The increment and decrement instructions contain immediate data short 1 2 or 4 which specifies the amount of the increment decrement MCS 51 architecture Instructions use only 8 bit immediate data data 5 3 1 3 Direct MCS 251 architecture In the direct addressing mode the instruction contains the address of the data operand The 8 bit direct mode addresses on chip RAM dir8
250. e 5 10 on page 5 17 6 AC Auxiliary Carry Flag The auxiliary carry flag is affected only by instructions that address 8 bit operands The AC flag is set if an arithmetic instruction with an 8 bit operand produces a carry out of bit 3 from addition or a borrow into bit 3 from subtraction Otherwise it is cleared This flag is useful for BCD arithmetic see Table 5 10 on page 5 17 5 FO Flag 0 This general purpose flag is available to the user 4 3 RS1 0 Register Bank Select Bits 1 and 0 These bits select the memory locations that comprise the active bank of the register file registers RO R7 RS1 RSO Bank Address 0 0 0 00 07 0 1 1 08 1 0 2 10H 17H 1 1 3 18H 1FH 2 OV Overflow Flag This bit is set if an addition or subtraction of signed variables results in an overflow error i e if the magnitude of the sum or difference is too great for the seven LSBs in 2 s complement representation The overflow flag is also set if a multiplication product overflows one byte or if a division by zero is attempted 1 UD User definable Flag This general purpose flag is available to the user 0 P Parity Bit This bit indicates the parity of the accumulator It is set if an odd number of bits in the accumulator are set Otherwise it is cleared Not all instruc tions update the parity bit The parity bit is set or cleared by instructions that change the contents of the accumulator ACC Register R
251. e Baud Rate Generator NOTE Turn the timer off clear the TR2 bit in the T2CON register before accessing registers TH2 TL2 RCAP2H and RCAP2L To select timer 2 as the baud rate generator for the transmitter and or receiver program the RCLCK and TCLCK bits in the T2CON register as shown in Table 10 5 You may select differ ent baud rates for the transmitter and receiver Setting RCLK and or TCLK puts timer 2 into its baud rate generator mode Figure 10 5 In this mode a rollover in the TH2 register does not set the TF2 bit in the T2CON register Also a high to low transition at the T2EX pin sets the EXF2 bit in the T2CON register but does not cause a reload from RCAP2H RCAP2L to TH2 TL2 You can use the T2EX pin as an additional external interrupt by setting the EXEN2 bit in T2CON 10 12 intel SERIAL I O PORT You may configure timer 2 as a timer or a counter In most applications it is configured for timer operation 1 the C T2 bit is clear in the T2CON register Table 10 5 Selecting the Baud Rate Generator s RCLCK TCLCK Receiver Transmitter Bit Bit Baud Rate Generator Baud Rate Generator 0 Timer 1 Timer 1 1 Timer 1 Timer 2 1 0 Timer 2 Timer 1 1 1 Timer 2 Timer 2 Note Oscillator frequency is divided by 2 not 12 Timer 1 Overflow RX Clock TX Clock RCAP2H RCAP2L TCLCK Interrupt 2 o 5 1 gt EXF2 ius EXEN2 Note availabilit
252. e RETI instead of RET to return from a subroutine that is called by ACALL or LCALL 1 not an interrupt service routine ISR In the 8XC251Sx this causes a compatibility problem if INTR 1 in configuration byte CONFIGI In this case the CPU pushes four bytes the three byte PC and PSW1 onto the stack when the routine is called and pops the same four bytes when the RETI is executed In contrast RET pushes and pops only the lower two bytes of the PC To maintain compatibility configure the 8XC251Sx with INTR 0 With the exception of TRAP the start addresses of consecutive interrupt service routines are eight bytes apart If consecutive interrupts are used and for example or TFO and IE1 the first interrupt routine if more than seven bytes long must execute a jump to some other memory location This prevents overlap of the start address of the following interrupt routine 6 15 intel Input Output Ports intel CHAPTER 7 INPUT OUTPUT PORTS 7 1 INPUT OUTPUT PORT OVERVIEW The 8 2515 uses input output I O ports to exchange data with external devices In addition to performing general purpose I O some ports are capable of external memory operations see Chapter 13 External Memory Interface others allow for alternate functions All four 8XC251Sx I O ports are bidirectional Each port contains a latch an output driver and an input buffer Port 0 and port 2 output drivers and input buffers facilit
253. e emen 14 4 14 2 Eock BIt EUDCHOn sso ot ae elm onde P Een E Pres 14 9 14 3 Contents of the Signature enne 14 10 14 4 Program Verify Timing Definitions 14 11 A 1 Notation for Register memi 2 A 2 Notation for Direct Addresses sss eem ACG A 3 Notation for Immediate 0 ACG A 4 Notation for Bit eene nne A 3 A 5 Notation for Destinations in Control Instructions A 6 Instructions for MCS 51 A 4 A 7 New Instructions for the MCS 251 Architecture A 5 A 8 Data Instructions iniit ener A 6 A 9 High Nibble Byte 0 of Data A 6 A 10 Bit Instructions iere eerie nere serere tinere alee A 11 Byte 1 High Nibble for Bit 7 A 12 PUSH POP Instructions oriri medetur sedge ced Ree dne a A 8 A 13 Control Instructions beaver ian verterem 14 Displacement Extended MOVs c ER A 9 A 15 10 16 Encoding for INC DEC et pte 10 17 Rcs A 10 A 18 State Times to Access the Port
254. e first half of the state time and the poll request occurs in the second half of the next state time Therefore this sample and poll request portion of the minimum fixed response and latency 6 10 intel INTERRUPT SYSTEM time is five states for internal interrupts and six states for external interrupts External interrupts must remain active for at least five state times to guarantee interrupt recognition when the request occurs immediately after a sample has been taken i e requested in the second half of a sample state time If the external interrupt goes active one state after the sample state the pin is not resampled for another three states After the second sample is taken and the interrupt request is recognized the interrupt controller requests the context switch The programmer must also consider the time to complete the instruction at the moment the context switch request is sent to the execution unit If 9 states of a 10 state instruction have completed when the context switch is requested the total response time is 6 states with a context switch immediately after the final state of the 10 state instruction see Figure 6 6 Response Time 6 OSC State Time INTO Sample INTO Request Ten State macron Pehee 4155 02 Figure 6 6 Response Time Example 1 Conversely if the external interrupt requests service in the state just prior to the next sample re sponse is much quicker One state a
255. e five PCA compare capture modules 7 0 CR CCF2 CCF1 CCFO Bit Bit Number Mnemonic Function 7 CF PCA Timer Counter Overflow Flag Set by hardware when the PCA timer counter rolls over This generates an interrupt request if the ECF interrupt enable bit in CMOD is set CF can be set by hardware or software but can be cleared only by software 6 CR PCA Timer Counter Run Control Bit Set and cleared by software to turn the PCA timer counter on and off 5 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 4 0 CCF4 0 PCA Module Compare Capture Flags Set by hardware when a match or capture occurs This generates a PCA interrupt request if the ECCFx interrupt enable bit in the corresponding CCAPMXx register is set Must be cleared by software intel REGISTERS CH CL Address S F9H S E9H Reset State 0000 0000B CH CL Registers These registers operate in cascade to form the 16 bit PCA timer counter 7 0 High Low Byte PCA Timer Counter Bit Bit Number Mnemonic 7 0 CH 7 0 High byte of the PCA timer counter CL 7 0 Low byte of the PCA timer counter REGISTERS intel CMOD Address S D9H Reset State 00 X000B PCA Timer Counter Mode Register Contains bits for selecting the PCA timer counter input disabling the PCA timer counter during idle mode
256. e in Operation ADD A Rn Bytes States A 28 Binary Mode 2 1 Source Mode 2 1 0010 0100 immed data Binary Mode Encoding Source Mode Encoding ADD A lt A data Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state 0010 0101 direct addr Binary Mode Encoding Source Mode Encoding ADD A lt A dir8 Binary Mode Source Mode 1 2 2 3 0010 011i Binary Mode Encoding Source Mode A5 Encoding ADD lt A Ri Binary Mode Source Mode 1 1 2 2 intel Encoding 0010 irrr Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation ADD lt A Rn INSTRUCTION SET REFERENCE ADD Rmd Rms Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0010 1100 ssss 5555 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD Rms ADD WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0010 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD WRjd lt WRijd WRjs ADD DRkd DRks Binary Mode Source Mode Bytes 3 2 States 5 4 Encoding 0010 1111 uuuu UUUU Hex Code in Binary Mode A5 Encoding
257. e instruction WAIT CJNE A P1 WAIT clears the CY flag and continues with the next instruction in the sequence since the accumulator does equal the data read from P1 If some other value was being input on P1 the program loops at this point until the P1 data changes to 34H intel INSTRUCTION SET REFERENCE Variations CJNE A data rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 2 5 2 5 Encoding 1011 0100 immed data rel addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation PC IF A data THEN PC lt PC relative offset IF A lt data THEN CY 1 ELSE CY 0 CJNE A dir8 rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 3 6 3 6 Encoding 1011 0101 direct addr rel addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation PC IF dir8 THEN PC lt PC relative offset IF A lt dir8 THEN CY 1 ELSE CY 0 A 43 INSTRUCTION SET REFERENCE CJNE Ri data rel Bytes States Encoding Hex Code in Operation Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 4 4 3 6 4 7 1011 011i immed data rel addr Binary Mode Encoding Source Mode A5 Encoding PC PC 3 IF Ri data THEN PC PC relat
258. e interrupt oc curred Interrupts may occur as a result of internal 8X C2515x activity e g timer overflow or at the initiation of electrical signals external to the microcontroller e g serial port communication In all cases interrupt operation is programmed by the system designer who determines priority of interrupt service relative to normal code execution and other interrupt service routines Seven of the eight interrupts are enabled or disabled by the system designer and may be manipulated dynamically A typical interrupt event chain occurs as follows internal or external device initiates an inter rupt request signal This signal connected to an input pin see Table 6 1 and periodically sam pled by the 8XC251Sx latches the event into a flag buffer The priority of the flag see Table 6 2 Interrupt System Special Function Registers is compared to the priority of other interrupts by the interrupt handler A high priority causes the handler to set an interrupt flag This signals the in struction execution unit to execute a context switch This context switch breaks the current flow of instruction sequences The execution unit completes the current instruction prior to a save of the program counter PC and reloads the PC with the start address of a software service routine The software service routine executes assigned tasks and as a final activity performs a RETI re turn from interrupt instruction This instruction signals comp
259. e interrupt service routine before the next capture event occurs PCA Timer Counter CL 8 Bits Count CH Input 8 Bits Capture cEXx J External I O X 0 1 2 3 or 4 X Don t Care nterrupt Request 7 CCAPMx Mode Register 0 A4163 02 Figure 9 2 PCA 16 bit Capture Mode 9 6 intel PROGRAMMABLE COUNTER ARRAY 9 3 2 Compare Modes The compare function provides the capability for operating the five modules as timers event counters or pulse width modulators Four modes employ the compare function 16 bit software timer mode high speed output mode WDT mode and PWM mode In the first three of these the compare capture module continuously compares the 16 bit PCA timer counter value with the 16 bit value pre loaded into the module s CCAPxH CCAPXL register pair In the PWM mode the module continuously compares the value in the low byte PCA timer counter register CL with an 8 bit value in the CCAPxL module register Comparisons are made three times per peripheral cycle to match the fastest PCA timer counter clocking rate Fosc 4 For a description of periph eral cycle timing see Clock and Reset Unit on page 2 6 Setting the bit in a module s mode register CCAPMX selects the compare function for that module Figure 9 9 on page 9 16 To use the modules in the compare modes observe the following general procedure 1 Select the module s mode of operation Select the input s
260. e start this sequence execution jumps to LABEL2 Remember that AJMP is a two byte instruction so the jump instructions start at every other address Binary Mode Source Mode Bytes 1 1 States 5 5 Encoding 0111 0011 Hex Code in Binary Mode Encoding Source Mode Encoding Operation JMP PC 15 0 A DPTR A 73 INSTRUCTION SET REFERENCE intel JNB bit51 rel JNB bit rel Function Jump if bit not set Description If the specified bit is clear branch to the specified address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified Flags CY AC OV N Z Example Input port 1 contains 11001010B and the accumulator contains 56H 01010110B After executing the instruction sequence JNB P1 3 LABEL1 JNB ACC 3 LABEL2 program execution continues at label LABEL2 Variations JNB bit51 rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 2 5 2 5 Encoding 0011 0000 bit addr rel addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation JNB PC PC 3 IF bit51 0 THEN lt PC rel JNB bit rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 5 5 4 4 States 4 7 3 6 Encoding 1010 1001 0011 0 yy direc
261. eceive clock transmit clock and S C8H capture reload bits used to configure timer 2 Also contains the run control bit counter timer select bit overflow flag external flag and external enable for timer 2 T2MOD Timer 2 Mode Control Register Contains the timer 2 output enable and S C9H down count enable bits RCAP2L Timer 2 Reload Capture Registers RCAP2L RCAP2H Provide values S CAH RCAP2H to and receive values from the timer registers TL2 TH2 S CBH WDTRST Watchdog Timer Reset Register WDTRST Used to reset and enable S A6H the WDT Interrupt THx Tlx Request 1 8 Bits 8 Bits Tx x 0 1 0r2 TRx A4121 02 Figure 8 1 Basic Logic of the Timer Counters intel TIMER COUNTERS AND WATCHDOG TIMER The control bit selects timer operation or counter operation by selecting the divided down system clock or external pin Tx as the source for the counted signal For timer operation 0 the timer register counts the divided down system clock The timer register is incremented once every peripheral cycle i e once every six states see Clock and Reset Unit on page 2 6 Since six states equals 12 clock cycles the timer clock rate is Fosc 12 Exceptions are the timer 2 baud rate and clock out modes where the timer register is incremented by the system clock divided by two For counter operation 1 the timer register counts the negati
262. ecuting the instruction POP SP the stack pointer contains 20H Note that in this special case the stack pointer was decremented to 2FH before it was loaded with the value popped 20H Variations POP dir8 Binary Mode Source Mode Bytes 2 2 States 3 3 Encoding 1101 0000 direct addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation POP dir8 lt SP SP lt SP 1 POP Rm Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 1101 1010 ssss 1000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation POP Rm lt SP SP SP 1 POP WRj Binary Mode Source Mode Bytes 3 2 States 5 4 Encoding 1101 1010 tttt 1001 A 116 intel Hex Code in Operation POP DRk Bytes States Encoding Hex Code in Operation PUSH dest Function Description Flags Example Variations PUSH dir8 Bytes States Encoding INSTRUCTION SET REFERENCE Binary Mode A5 Encoding Source Mode Encoding POP SP SP 1 WHj lt SP SP lt SP 1 Binary Mode Source Mode 3 2 10 9 1101 1010 uuuu 1011 Binary Mode A5 Encoding Source Mode Encoding POP SP SP 3 lt SP SP SP 1 Push onto stack Increments the stack pointer by one The contents of the specifi
263. ed from TH1 at overflow 1 1 Mode 3 Timer 1 halted Retains count 3 GATEO Timer 0 Gate When GATEO 0 run control bit TRO gates the input signal to the timer register When GATEO 1 and TRO 1 external signal INTO gates the timer input 2 C TO Timer 0 Counter Timer Select C TO 0 selects timer operation timer 0 counts the divided down system clock C TO 1 selects counter operation timer 0 counts negative transitions on external pin TO 1 0 M10 Timer 0 Mode Select M10 M00 0 0 Mode 0 8 bit timer counter TO with 5 bit prescaler TLO 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TLO Reloaded from THO at overflow 1 1 Mode 3 TLO is an 8 bit timer counter THO is an 8 bit timer using timer 1 s TR1 and TF1 bits C 35 REGISTERS intel THO TLO Address THO S 8CH TLO S 8AH Reset State 0000 0000B THO TLO Timer Registers These registers operate in cascade to form the 16 bit timer register in timer 0 or separately as 8 bit timer counters 7 0 High Low Byte of Timer 0 Register Bit Bit Number Mnemonic Function 7 0 THO0 7 0 High byte of the timer 0 timer register TLO 7 0 Low byte of the timer 0 timer register C 36 intel REGISTERS TH1 TL1 Address 1 S 8DH TL1 S 8BH Reset State 0000 0000B TH1 TL1 Timer Registers These registers operate in cascade to form the 16 bit timer register in timer 1
264. ed variable are then copied into the on chip RAM location addressed by the stack pointer CY AC OV N On entering an interrupt routine the stack pointer contains 09H and the data pointer contains 0123H After executing the instruction sequence PUSH DPL PUSH DPH the stack pointer contains OBH and on chip RAM locations 0AH and OBH contain 01H and 23H respectively Binary Mode Source Mode 2 2 4 4 1100 0000 direct addr A 117 INSTRUCTION SET REFERENCE Hex Code in Binary Mode Encoding Source Mode Encoding Operation PUSH lt SP SP lt dir 5 PUSH data Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 1100 1010 0000 0010 Hex Code in Binary Mode Encoding Source Mode Encoding Operation PUSH SP lt SP 1 SP lt data PUSH data16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 1100 1010 0000 0110 data hi lo Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation PUSH SP lt SP 2 SP lt MSB of data16 SP lt LSB of data16 PUSH Rm Binary Mode Source Mode Bytes 3 2 States 4 3 Encoding 1100 1010 ssss 1000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation PUSH SP lt SP 1 A 118 SP lt Rm intel PU
265. egories external memory interface page mode address bits wait states range for RD WR and PSEN source mode binary mode opcodes selection of bytes stored on the stack by an interrupt mapping of the upper portion of on chip code memory to region 00 The B stepping version of the 8XC251Sx extends the range of configurable features with respect to the A stepping version You can now specify a 16 bit 17 bit or 18 bit external addresses bus 256 Kbyte external address space versus a 16 bit or 17 bit bus in the A stepping version Wait state selection has been expanded to provide 0 1 2 or 3 wait states This chapter provides a detailed discussion of device configuration It describes the configuration bytes and provides information to aid you in selecting a suitable configuration for your applica tion It discusses the choices involved in configuring the external memory interface and shows how the internal memory space maps into external memory See Configuring the External Mem ory Interface on page 4 11 Opcode Configurations SRC on page 4 17 discusses the choice of source mode or binary mode opcode arrangements 41 CONFIGURATION OVERVIEW The configuration of the MCS 251 microcontroller is established by the reset routine based on information stored in configuration bytes The B stepping version of the MCS 251 microcontrol ler stores configuration information in two user configuration bytes UCONFIGO and UCONF
266. emory Interface on page 4 11 The external memory interface operates in either page mode and nonpage mode Page mode pro vides increased performance by reducing the time for external code fetches Page mode does not apply to code fetches from on chip memory The reset routine configures the 8XC251Sx for op eration in page mode or nonpage mode according to bit 1 of configuration bytes UCONFIGO B stepping or CONFIGO A stepping Figure 13 1 shows the structure of the external address bus for page and nonpage mode operation PO carries address A7 0 while P2 carries address A15 8 Data D7 0 is multiplexed with A7 0 on PO in nonpage mode and with A15 8 on P2 in page mode Table 13 1 describes the external memory interface signals The address and data signals AD7 0 on port 0 and 15 8 on port 2 are defined for nonpage mode 8XC251SA 8XC251SA 8XC251SB 8XC251SB 8XC251SP 8XC251SP 8XC251SQ 8XC251SQ P gt AD7 0 A7 0 epee Nonpage Mode Page Mode A4159 02 Figure 13 1 Bus Structure in Nonpage Mode and Page Mode 13 1 EXTERNAL MEMORY INTERFACE Table 13 1 External Memory Interface Signals intel Signal Multiplexed Name Type Description With A17 O Address Line 17 P1 7 CEX4 A16 O Address Line 16 See RD P3 7 RD A15 8t Address Lines Upper address lines for the external bus P2 7 0 AD7 0t lO Address Data Lines Multiplexed lower address lines and data lines P0
267. emory system must hold data on the bus after WR goes high Address port 0 valid to Valid Data Instruction In Time after the 8XC251Sx places 2 3 4 valid address on the bus port 0 until the memory system must place valid data on the bus port 0 2 Address port 2 Valid to Valid Data Instruction In Time after the 8 2515 places a 2 3 4 valid address on the bus port 2 until the memory system must place valid data instruction on the bus port 0 If the bus cycle is an instruction fetch this applies to a page miss Address port 2 Valid to Valid Instruction In Time after the 8 2515 places a valid address on the bus port 2 until the memory system must place a valid instruction on the bus port 0 This applies to a page hit NOTES 1 Specifications for PSEN are identical to those for RD 2 Ifa wait state is added by extending ALE this time increases by 2Tosc 3 If await state is added by extending RD PSEN WRi this time increases by 2Togc 4 If wait states are added as described in both Note 2 and Note 3 this time increases by a total of 4Tosc 13 33 intel 14 Programming and Verifying Nonvolatile Memory 14 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY This chapter provides instructions for programming and verifying on chip nonvolatile memory on the 8XC251Sx The programming instructions cover the entry of program code into on chip code memory c
268. ers and Watchdog Timer The timer counter unit has three timer counters which can be clocked by the oscillator for timer operation or by an external input for counter operation You can set up an 8 bit 13 bit or 16 bit timer counter and you can program them for special applications such as capturing the time of an event on an external pin outputting a programmable clock signal on an external pin or gen erating a baud rate for the serial I O port Timer counter events can generate interrupt requests 2 7 ARCHITECTURAL OVERVIEW intel The watchdog timer is a circuit that automatically resets the 8XC251Sx in the event of a hardware or software upset When enabled by software the watchdog timer begins running and unless software intervenes the timer reaches a maximum count and initiates a chip reset In normal op eration software periodically clears the timer register to prevent the reset If an upset occurs and software fails to clear the timer the resulting chip reset disables the timer and returns the system to a known state The watchdog and the timer counters are described in Chapter 8 Tim er Counters and WatchDog Timer 2 32 Programmable Counter Array PCA The programmable counter array PCA has its own timer and five capture compare modules that perform several functions capturing storing the timer value in response to a transition on an in put pin generating an interrupt request when the timer matches a stored
269. es a two state bus cycle Subse quent successive code fetches to the same page page hits require only a one state bus cycle When subsequent fetch is to a different page a page miss it again requires a two state bus cy cle The following external code fetches are always page miss cycles the first external code fetch after a page rollover the first external code fetch after an external data bus cycle the first external code fetch after powerdown or idle mode the first external code fetch after a branch return interrupt etc In page mode the 8 2515 bus structure differs from the bus structure in MCS 51 controllers Figure 13 1 The upper address bits A15 8 are multiplexed with the data D7 0 on port 2 and the lower address bits A7 0 are on port 0 Figure 13 5 shows the two types of external bus cycles for code fetches in page mode The page miss cycle is the same as a code fetch cycle in nonpage mode except D7 0 is multiplexed with A15 8 on P2 For the page hit cycle the upper eight address bits are the same as for the preced ing cycle Therefore ALE is not asserted and the values of A15 8 are retained in the address latches In a single state the new values of A7 0 are placed on port 0 and memory places the in struction byte on port 2 Notice that a page hit reduces the available address access time by one state Therefore faster memories may be required to support page mode Figure 13 6 and Figure 13 7 sho
270. est src Function Description Flags Example Add Adds the source operand to the destination operand which can be a register or the accumu lator leaving the result in the register or accumulator If there is a carry out of bit 7 CY the CY flag is set If byte variables are added and if there is a carry out of bit 3 AC the AC flag is set For addition of unsigned integers the CY flag indicates that an overflow occurred If there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not bit 6 the OV flag is set When adding signed integers the OV flag indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Bit 6 and bit 7 in this description refer to the most significant byte of the operand 8 16 or 32 bit Four source operand addressing modes are allowed register direct register indirect and immediate CY AC OV N 2 Register 1 contains 11000011B and register 0 contains OAAH 10101010B After executing the instruction ADD R1 RO register 1 contains 6DH 01101101B the AC flag is clear and the CY and OV flags are set A 27 INSTRUCTION SET REFERENCE Variations ADD A data Bytes States Encoding Hex Code in Operation ADD 8 Bytes States Encoding Hex Code in Operation ADD A Ri Bytes States Encoding Hex Cod
271. etches and determines whether data is transmitted on P2 or PO See Figure 13 1 on page 13 1 and Page Mode Bus Cycles on page 13 5 for a description of the bus structure and page mode op eration Nonpage mode 1 The bus structure is the same as for the MCS 51 architecture with data D7 0 multiplexed with A7 0 on PO External code fetches require two state times 4T osc Page mode PAGE 0 The bus structure differs from the bus structure in MCS 51 controllers Data D7 0 is multiplexed with A15 8 on P2 Under certain conditions external code fetches require only one state time 2Toso 4 6 2 Configuration Bits RD1 0 The RD1 0 configuration bits UCONFIGO 3 2 and CONFIGO 3 2 determine the number of ex ternal address lines and the address ranges for asserting the read signals PSEN RD and the write signal WR These selections offer different ways of addressing external memory Figures 4 7 and 4 8 show how internal memory space maps into external memory space for the four val ues of RD1 0 External Memory Design Examples on page 13 12 provides examples of exter nal memory designs for each choice of RD1 0 4 11 DEVICE CONFIGURATION intel A key to the memory interface is the relationship between internal memory addresses and exter nal memory addresses While the 8XC251Sx has 24 internal address bits the number of external address lines is less than 24 1 16 17 or 18 depending on the values of RD1 0
272. ex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRjd lt WRjs MOV DRk WRj Binary Mode Source Mode Bytes 4 3 States 6 5 Encoding 0001 1011 uuuu 1010 tttt 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk lt MOV Rm WRj 41516 Binary Mode Source Mode Bytes 5 4 States 6 5 A 95 INSTRUCTION SET REFERENCE intel Encoding 0000 1001 ssss tttt dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm lt WRj dis MOV WRj WRj dis16 Binary Mode Source Mode Bytes 5 4 States 7 6 Encoding 0100 1001 tttt TTTT dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV lt WRij dis MOV Rm DRk dis24 Binary Mode Source Mode Bytes 5 4 States 7 6 Encoding 0010 1001 ssss dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm lt DRk dis MOV WRj DRk dis24 Binary Mode Source Mode Bytes 5 4 States 8 7 Encoding 0110 1001 tttt uuuu dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding A 96 intel
273. f nnne nnne eene nnns 8 15 9 1 PCA Special Function Registers 6 9 4 9 2 External Signals iiie eec MEER UR MEER E AERE REPRE 9 4 9 3 PGA Module Modes nri ERE Ud e RR Ede ripae este dE drea 9 15 10 1 Serial Port Signals erroe er eth e E RET e Per ree HE be 10 1 10 2 Serial Port Special Function 10 2 10 3 Summary of Baud Rates ecce c ene rid ied eene 10 10 xiii CONTENTS intel TABLES Table Page 10 4 Timer 1 Generated Baud Rates for Serial I O Modes 1 and 3 10 12 10 5 Selecting the Baud Rate Generator s see 10 13 10 6 Timer 2 Generated Baud meme 10 14 12 1 Pin Conditions in Various Modes esee emere 12 3 13 1 External Memory Interface Signals sese LOPE 13 2 Bus Cycle Definitions No Wait 13 3 13 3 Port 0 and Port 2 Pin Status In Normal MR eerte 13 12 13 4 AC Timing Symbol Definitions 3 temo tat Otek 13 5 AC Timing Definitions for Specifications on 1 the 8 251 Sx Tp O G2 13 6 AC Timing Definitions for Specifications on the Memory 13 33 14 1 Programming and Verifying Modes ses
274. f POF 1 is detected at other times do a reset to reinitialize the chip since for Vcc 3 V data may have been lost or some logic may have malfunctioned 12 1 SPECIAL OPERATING MODES intel PCON Address 5 87 Reset State 00 0000B 7 0 SMOD1 SMODO POF GF1 GFO PD IDL earn Function 7 SMOD1 Double Baud Rate Bit When set doubles the baud rate when timer 1 is used and mode 1 2 or 3 is selected in the SCON register See Baud Rates on page 10 10 6 SMODO SCON 7 Select When set read write accesses to SCON 7 are to the FE bit When clear read write accesses to SCON 7 are to the SMO bit See Figure 10 2 on page 10 3 5 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 4 POF Power Off Flag Set by hardware as Vcc rises above 3 V to indicate that power has been off or had fallen below V and that on chip volatile memory is indeterminate Set or cleared by software 3 GF1 General Purpose Flag Set or cleared by software One use is to indicate whether an interrupt occurred during normal operation or during idle mode 2 GFO General Purpose Flag Set or cleared by software One use is to indicate whether an interrupt occurred during normal operation or during idle mode 1 PD Powerdown Mode Bit When set activates powerdown mode Cleared by hardware when an interrupt or reset occurs 0 IDL Idle Mode
275. figuration byte bus cycles It also provides bus cycle diagrams with AC timing symbols and definitions of the symbols Chapter 14 Programming and Verifying Nonvolatile Memory provides instructions for programming and verifying on chip code memory configuration bytes signature bytes lock bits and the encryption array Appendix Instruction Set Reference provides reference information for the instruction set It describes each instruction defines the bits in the program status word registers PSW PSW1 shows the relationships between instructions and PSW flags and lists hexadecimal op codes instruction lengths and execution times Chapter 5 Programming includes a general discussion of the instruction set intel GUIDE TO THIS MANUAL Appendix B Signal Descriptions describes the function s of each device pin Descrip tions are listed alphabetically by signal name This appendix also provides a list of the signals grouped by functional category Appendix C Registers accumulates for convenient reference copies of the register defi nition figures that appear throughout the manual 1 2 NOTATIONAL CONVENTIONS AND TERMINOLOGY The following notations and terminology are used in this manual The Glossary defines other terms with special meanings italics XXXX Assert and Deassert Instructions The pound symbol has either of two meanings depending on the context When used with
276. frames ninth bit set This allows the microcontroller to func tion as a slave processor in an environment where multiple slave processors share a single serial line When the multiprocessor communication feature is enabled the receiver ignores frames with the ninth bit clear The receiver examines frames with the ninth bit set for an address match If the received address matches the slave s address the receiver hardware sets the RB8 bit and the RI bit in the SCON register generating an interrupt NOTE The ES bit must be set in the register to allow the RI bit to generate an interrupt The IE register is described in Chapter 8 Interrupts The addressed slave s software then clears the SM2 bit in the SCON register and prepares to re ceive the data bytes The other slaves are unaffected by these data bytes because they are waiting to respond to their own addresses 10 5 AUTOMATIC ADDRESS RECOGNITION The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled the SM2 bit is set in the SCON register 10 7 SERIAL I O PORT intel Implemented in hardware automatic address recognition enhances the multiprocessor communi cation feature by allowing the serial port to examine the address of each incoming command frame Only when the serial port recognizes its own address does the receiver set the RI bit in the SCON register to generate an interrupt This ensures that the C
277. from MCS 51 microcontrollers Other MCS 251 microcontrollers may have unique interrupt priority within level tables 6 7 INTERRUPT SYSTEM intel IPHO Address S B7H Reset State X000 0000B 7 0 IPHO 6 0 5 4 IPHO 3 IPHO 2 IPHO 1 0 0 NR F ncton 7 x Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 6 IPHO 6 PCA Interrupt Priority Bit High 5 IPHO 5 Timer 2 Overflow Interrupt Priority Bit High 4 4 Serial I O Port Interrupt Priority Bit High 3 IPHO 3 Timer 1 Overflow Interrupt Priority Bit High 2 IPHO 2 External Interrupt 1 Priority Bit High 1 IPHO 1 Timer 0 Overflow Interrupt Priority Bit High 0 0 0 External Interrupt 0 Priority Bit High Figure 6 3 Interrupt Priority High Register IPLO Address S B8H Reset State X000 0000B 7 0 IPLO 6 IPLO 5 IPLO 4 IPLO 3 IPLO 2 IPLO 1 IPLO O Nus Function 7 um Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 6 IPLO 6 PCA Interrupt Priority Bit Low 5 IPLO 5 Timer 2 Overflow Interrupt Priority Bit Low 4 IPLO 4 Serial I O Port Interrupt Priority Bit Low 3 IPLO 3 Timer 1 Overflow Interrupt Priority Bit Low 2 IPLO 2 External Interrupt 1 Priority Bit Low 1 IPLO 1 Timer 0 Overflow Interrupt Priority Bit Low 0 IPLO O Externa
278. from on chip code memory two bytes at a time or from external memory in single bytes The instructions are sent over the 16 bit code bus to the execution unit You can con figure the 8XC251Sx to operate in page mode for accelerated instruction fetches from external memory In page mode if an instruction fetch is to the same 256 byte page as the previous fetch the fetch requires one state two clocks rather than two states four clocks The 8XC251Sx register file has forty registers which be accessed as bytes words and double words As in the MCS 51 architecture registers 0 7 consist of four banks of eight registers each where the active bank is selected by the program status word PSW for fast context switches The 8XC251Sx is a single pipeline machine When the pipeline is full and code is executing from on chip code memory an instruction is completed every state time When the pipeline is full and code is executing from external memory with no wait states and no extension of the ALE signal an instruction is completed every two state times Code Bus Code Address Instruction Sequencer Interrupt Handler Data Bus Register File Memory Interface Data Address Figure 2 2 The CPU 2 5 ARCHITECTURAL OVERVIEW intel 2 2 2 Clock and Reset Unit The timing source for the 8XC251Sx can be an external oscillator or an internal oscillator with an external crystal resonator see Chapter
279. g 1011 1110 tttt 0111 dir addr dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP WRj dir16 CMP Rm WRj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 1011 1110 tttt 1001 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP A 50 Rm WRj intel INSTRUCTION SET REFERENCE CMP Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 1011 1110 uuuu 1011 SSSS 0000 Hex Code in Binary Mode A5 Encoding Operation CPLA Function Description Flags Example Bytes States Source Mode Encoding CMP Rm DRk Complement accumulator Logically complements each bit of the accumulator one s complement Clear bits are set and set bits are cleared CY AC OV The accumulator contains 5CH 01011100B After executing the instruction CPLA the accumulator contains 10100011B Source Mode 1 1 Binary Mode 1 1 Encoding Hex Code in Operation CPL bit Function Description 1111 0100 Binary Mode Encoding Source Mode Encoding CPL lt Complement bit Complements 0 the specified bit variable A clear bit is set and a set bit is cleared CPL can operate on the CY or any directly addressable bit Note When this instruction is used to modify an output pin the
280. gister Used to enable and disable programmable S A8H interrupts The reset value of this register is zero interrupts disabled IPLO Interrupt Priority Low Register Establishes relative four level priority for S B8H programmable interrupts Used in conjunction with IPHO IPHO Interrupt Priority High Register Establishes relative four level priority for S B7H programmable interrupts Used in conjunction with IPLO NOTE Other special function registers are described in their respective chapters 6 2 8XC2518SA SB SP SQ INTERRUPT SOURCES Figure 6 1 on page 6 2 illustrates the interrupt control system The 8 2515 has eight interrupt sources seven maskable sources and the TRAP instruction always enabled The maskable sources include two external interrupts INTO and INT1 three timer interrupts timers 0 1 and 2 one programmable counter array PCA interrupt and one serial port interrupt Each in terrupt except TRAP has an interrupt request flag which can be set by software as well as by hardware see Table 6 3 on page 6 4 For some interrupts hardware clears the request flag when it grants an interrupt Software can clear any request flag to cancel an impending interrupt 6 2 1 External Interrupts External interrupts INTO and INT1 INTx pins may each be programmed to be level trig gered or edge triggered dependent upon bits ITO and IT1 in the TCON register see Figure 8 6 on page 8 8 If ITx
281. gister controls the duty cycle of the output waveform CCAPMO PCA Compare Capture Module Mode Registers Contain bits for S DAH CCAPM1 selecting the operating mode of the compare capture modules and S DBH CCAPM2 enabling the compare capture flag See Table 9 3 on page 9 15 for mode S DCH CCAPM3 select bit combinations S DDH CCAPM4 S DEH Table 9 2 External Signals Signal Multipl Nome Type Description u tiplexed ECI Timer counter External Input This signal is the external clock P1 2 input for the PCA timer counter CEXO Compare Capture Module External I O Each compare capture P1 3 CEX1 module connects to a Port 1 pin for external I O When not used by P1 4 CEX2 the PCA these pins can handle standard I O P1 5 CEX3 P1 6 4 1 7 17 intel PROGRAMMABLE COUNTER ARRAY 9 3 COMPARE CAPTURE MODULES Each compare capture module is made up of compare capture register pair CCAPxH CCAPXL a 16 bit comparator and various logic gates and signal transition selectors The registers store the time or count at which an external event occurred capture or at which an action should occur comparison In the PWM mode the low byte register controls the duty cy cle of the output waveform The logical configuration of a compare capture module depends on its mode of operation Figures 9 2 through 9 5 Each module can be independently programmed for operation in any of the following modes
282. gure 3 1 The 64 locations in the register file are numbered decimally from 0 to 63 Locations 0 7 represent one of four switchable register banks each having 8 registers The 32 bytes required for these banks occupy locations 00 0000H 00 001FH in the memory space Register file locations 8 63 do not appear in the memory space See 8XC251SA SB SP SQ Register File on page 3 10 for a further description of the register file The SFR space can accommodate up to 512 8 bit special function registers with addresses 5 000 5 1 Some of these locations may be unimplemented in a particular device In the MCS 251 architecture the prefix S is used with SFR addresses to distinguish them from the memory space addresses 00 0000H 00 01FFH See Special Function Registers SFRs on page 3 16 for details on the SFR space 3 4 1 Compatibility with the MCS 51 Architecture The address spaces in the MCS 51 architecture are mapped into the address spaces in MCS 251 architecture This mapping allows code written for MCS 51 microcontrollers to run on MCS 251 microcontrollers Chapter 5 Programming discusses the compatibility of the two instruc tion sets Figure 3 2 shows the address spaces for the MCS 51 architecture Internal data memory locations 00H 7FH can be addressed directly and indirectly Internal data locations 830H FFH can only be addressed indirectly Directly addressing these locations accesses the SFRs The 64
283. he 16 bit address on ports 1 and 3 Input the data byte on port 2 Raise the voltage on the V pin from 5 V to 12 75 V Chr qp S 2 Pulse the PROG pin 5 times for the on chip code memory and the configuration bytes and 25 times for the encryption array and the lock bits e Reduce the voltage on the V pin to 5 V 7 Ifthe procedure is program immediate verify go to Verify Algorithm on page 14 7 and perform steps 1 through 4 to verify the currently addressed byte Make sure the voltage on the EA V pp pin has been lowered to 5 V before performing the verifying procedure 8 Repeat steps 1 through 7 until all memory locations are programmed Programming Cycle Verification Cycle i Address 16 Bit P2 Data In 8 Bit Data Out PROG 1 2 3 4 5 EARN 12 75V PP 5V Po 4129 01 Figure 14 2 Program Verify Bus Cycles 14 6 intel PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 14 5 VERIFY ALGORITHM Use this procedure to verify user program code signature bytes configuration bytes and lock bits stored in nonvolatile memory on the 8 2515 To preserve the secrecy of the encryption key byte sequence the encryption array can not be verified Verification can be performed on bytes as they are programmed or on a block of bytes that have been previously programmed The pro cedure for verifying the 8XC251Sx is as follows 1 Setup the controller for operation in the appropria
284. he external bus pins However if the external EPROM and the external RAM require different numbers of wait states the external RAM must be addressed entirely in region 01 Recall that the number of wait states for region 01 is independent of the remaining regions which always have the same number of wait states See Table 4 4 on page 4 17 The examples that follow illustrate two possibilities for addressing the external RAM 13 6 5 1 An Application Requiring Fast Access to the Stack If an application requires fast access to the stack the stack can reside in the fast on chip data RAM 00 0020H 00 041FH and when necessary roll out into the slower external RAM See the left side of Figure 13 21 In this case the external RAM can have wait states only if the EPROM has wait states Otherwise if the stack rolls out above location 00 041FH the external RAM would be accessed with no wait state 13 6 5 2 Application Requiring Fast Access to Data If fast access to a block of data is more important than fast access to the stack the data can be stored in the on chip data RAM and the stack can be located entirely in external memory If the external RAM requires a different number of wait states than the EPROM address the external RAM entirely in region 01 See the right side of Figure 13 21 Addresses above 00 041FH roll out to external memory beginning at 0420H gt 13 21 EXTERNAL MEMORY INTERFACE EPROM RAM 80C251SB 64 Kbytes
285. hich are selected by the SMODI bit in the PCON register Figure 12 1 on page 12 2 The following expression defines the baud rate F Serial I O Mode 2 Baud Rate 25 001 Uu 10 6 3 Baud Rates for Modes 1 and 3 In modes 1 and 3 the baud rate is generated by overflow of timer 1 default and or timer 2 You may select either or both timer s to generate the baud rate s for the transmitter and or the receiv er 10 10 intel SERIAL I O PORT 10 6 3 1 Timer 1 Generated Baud Rates Modes 1 and 3 Timer 1 is the default baud rate generator for the transmitter and the receiver in modes 1 and 3 The baud rate is determined by the timer 1 overflow rate and the value of SMOD as shown in the following formula SMOD Timer 1 Overflow Rate Serial I O Modes 1 and 3 Baud Rate 2 32 10 6 3 2 Selecting Timer 1 as the Baud Rate Generator To select timer 1 as the baud rate generator Disable the timer interrupt by clearing the ETI bit in the IEO register Figure 6 2 on page 6 6 Configure timer 1 as a timer or an event counter set or clear the C T bit in the TMOD register Figure 8 5 on page 8 7 Select timer mode 0 3 by programming the M1 MO bits in the TMOD register In most applications timer 1 is configured as a timer in auto reload mode high nibble of TMOD 0010B The resulting baud rate is defined by the following expression SMOD Fosc Serial I O Modes 1 and 3 Baud Rate 2 x 82 x12 x 256 TH1
286. hile regions FE and FF map into the other external 64 Kbyte region 4 15 DEVICE CONFIGURATION intel 4 6 3 Wait State Configuration Bits You can add wait states to external bus cycles by extending the RD WR PSEN pulse and or extending ALE pulse Each additional wait state extends the pulse by 2Tosc A separate wait state specification for external accesses via region 01 permits a slow external device to be ad dressed in region 01 without slowing accesses to other external devices Table 4 4 summarizes the wait state selections for RD WR PSEN For waveform diagrams showing wait states see External Bus Cycles with Wait States on page 13 8 4 6 3 1 Configuration Bits WSA1 0 WSB1 0 For B stepping devices the WSA1 0 wait state bits UCONFIGO 6 5 permit RD WR and PSEN to be extended by 1 2 or 3 wait states for accesses to external memory via all regions except region 01 For B stepping devices the WSB1 0s wait state bits UCONFIG1 2 1 permit RD WR and PSEN to be extended by 1 2 or 3 wait states for accesses to external memory via region 01 4 6 3 2 Configuration Bits WSA and WSB For A stepping devices the WSA wait state bit CONFIGO 5 permits RD WR and PSEN to be extended by one wait state for accesses to external memory via all regions except region 01 For A stepping devices the WSB wait state bit UCONFIG1 3 permits RD WR and PSEN to be extended by one wait state for accesses to exte
287. iables Performs the bitwise logical Exclusive OR operation V between the specified variables storing the results in the destination The destination operand can be the accumulator a register or a direct address The two operands allow 12 addressing mode combinations When the destination is the accumulator or a register the source addressing can be register direct register indirect or immediate when the destination is a direct address the source can be the accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins CY AC OV N 2 The accumulator contains 11000011B and RO contains 10101010B After executing the instruction XRL A RO the accumulator contains 69H 01101001B When the destination is a directly addressed byte this instruction can complement combina tions of bits in any RAM location or hardware register The pattern of bits to be comple mented is then determined by a mask byte either a constant contained in the instruction or a variable computed in the accumulator at run time The instruction XRL P1 00110001B complements bits 5 4 and 0 of output Port 1 intel Variations XRL dir8 A Bytes States Encoding Hex Code in Operation XRL dir8 data Bytes States Encoding Hex Code in Operation XRL A data
288. ified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice CY AC OV N 2 The instruction JSLE LABEL1 causes program execution to continue at LABEL1 if the Z flag is set OR if the the N flag and the OV flag have different values Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0000 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding A 79 INSTRUCTION SET REFERENCE Operation JZ rel Function Description Flags Example Bytes States Encoding Hex Code in Operation LCALL lt dest gt Function Description A 80 JSLE PC PC 2 IF 2 1 OR N OV THEN PC PC rel Jump if accumulator zero If all bits of the accumulator are clear zero branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified CY AC OV N 2 The accumulator contains 01H After executing the instruction sequence JZ LABEL1 DECA JZ LABEL2 the accumulator contains 00H and program execution continues at label LABEL2 Binary Mode So
289. iggered 2 IT1 Interrupt 1 Type Control Bit Set this bit to select edge triggered high to low for external interrupt 1 Clear this bit to select level triggered active low 1 IEO Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INTO pin Edge or level triggered see ITO Cleared when interrupt is processed if edge triggered 0 ITO Interrupt O Type Control Bit Set this bit to select edge triggered high to low for external interrupt 0 Clear this bit to select level triggered active low Figure 8 6 TCON Timer Counter Control Register intel TIMER COUNTERS AND WATCHDOG TIMER When timer 0 is in mode 3 it uses timer 1 s overflow flag TF1 and run control bit TR1 For this situation use timer 1 only for applications that do not require an interrupt such as a baud rate generator for the serial interface port and switch timer 1 in and out of mode 3 to turn it off and on 8 4 4 Mode 0 13 bit Timer Mode 0 configures timer 0 as a 13 bit timer which is set up as an 8 bit timer TH1 register with a modulo 32 prescaler implemented with the lower 5 bits of the TL1 register Figure 8 2 The upper 3 bits of the TL1 register are ignored Prescaler overflow increments the register 8 4 2 Mode 1 16 bit Timer Mode configures timer 1 as a 16 bit timer with TH1 and TL1 connected in cascade Figure 8 2 The selected input increments TL1 8 4 3 Mode 2 8 bit Timer with Au
290. ignal for the PCA timer counter Load the comparison value into the module s compare capture register pair Set the PCA timer counter run control bit Oi cae 59 59 After a match causes an interrupt clear the module s compare capture flag 9 3 3 16 bit Software Timer Mode To program a compare capture module for the 16 bit software timer mode Figure 9 3 set the and bits in the module s CCAPMXx register Table 9 3 on page 9 15 lists the bit combinations for selecting module modes A match between the PCA timer counter and the compare capture registers CCAPxH CCAPxL sets the module s compare capture flag CCFx in the CCON register This generates an interrupt request if the corresponding interrupt enable bit ECCFx in the CCAPMXx register is set Since hardware does not clear the compare capture flag when the interrupt is processed the user must clear the flag in software During the interrupt routine a new 16 bit compare value can be written to the compare capture registers CCAPxH CCAPxL NOTE To prevent an invalid match while updating these registers user software should write to CCAPxL first then CCAPxH A write to CCAPXL clears the ECOMkx bit disabling the compare function while a write to CCAPxH sets the bit re enabling the compare function 9 7 PROGRAMMABLE COUNTER ARRAY intel Compare Capture PCA Timer Counter Module CH CL CCAPxH CCAPxL 8 Bits 8 Bits 8 ES 1
291. ignals have no suffix To deassert RD is to drive it high to deassert ALE is to drive it low double word dword edge triggered encryption array EPROM external address FET idle mode input leakage integer internal address interrupt handler interrupt latency GLOSSARY The process of introducing a periodic table Group III or Group V element into a Group IV element e g silicon A Group III impurity e g indium or gallium results in a p type material A Group V impurity e g arsenic or antimony results in an n type material A 32 bit unit of data memory a double word comprises four contiguous bytes See double word The mode in which a device or component recognizes a falling edge high to low transition a rising edge low to high transition or a rising or falling edge of an input signal as the assertion of that signal See also level triggered An array of key bytes used to encrypt user code in the on chip code memory as that code is read protects against unauthorized access to user s code Eraseable programmable read only memory A 16 bit or 17 bit address presented on the device pins The address decoded by an external device depends on how many of these address bits the external system uses See also internal address Field effect transistor The power conservation mode that freezes the core clocks but leaves the peripheral clocks running Current leakage from an inpu
292. imal number 67 The CY flag is set After executing the instruction sequence ADDC A R3 DAA the accumulator contains OBEH 10111110 and the CY and AC flags are clear The Decimal Adjust instruction then alters the accumulator to the value 24H 00100100B indicating the packed BCD digits of the decimal number 24 the lower two digits of the decimal sum of 56 67 and the carry in The CY flag is set by the Decimal Adjust instruction indicating that a decimal overflow occurred The true sum of 56 67 and 1 is 124 A 53 INSTRUCTION SET REFERENCE intel Bytes States Encoding Hex Code in Operation DEC byte Function Description Flags Example A 54 BCD variables can be incremented or decremented by adding 01H or 99H If the accumulator contains 30H representing the digits of 30 decimal then the instruction sequence ADD A 99H DAA leaves the CY flag set and 29H in the accumulator since 30 99 129 The low byte of the sum can be interpreted to mean 30 1 29 Binary Mode Source Mode 1 1 1 1 1101 0100 Binary Mode Encoding Source Mode Encoding DA Contents of accumulator are BCD IF A 3 0 gt 9 V AC 1 THEN A 3 0 lt A 3 0 6 AND IF A 7 4 gt 9 V CY 1 THEN 7 4 lt A 7 4 6 Decrement Decrements the specified byte variable by 1 An original value of 00H underflows to OFFH Four operands addressing modes are allowed
293. imer Select C TO 0 selects timer operation timer 0 counts the divided down System clock 1 selects counter operation timer 0 counts negative transitions on external pin TO 1 0 M10 MOO Timer 0 Mode Select M10 M00 0 0 Mode 0 8 bit timer counter TO with 5 bit prescaler TLO 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TLO Reloaded from THO at overflow 1 1 Mode 3 TLO is an 8 bit timer counter THO is an 8 bit timer using timer 1 s TR1 and TF1 bits Figure 8 5 TMOD Timer Counter Mode Control Register TIMER COUNTERS AND WATCHDOG TIMER intel TCON Address 5 88 Reset State 0000 0000B 7 0 TF1 TR1 TFO TRO IE1 IT1 IEO ITO Bit Bit Number Mnemonic Function 7 TF1 Timer 1 Overflow Flag Set by hardware when the timer 1 register overflows Cleared by hardware when the processor vectors to the interrupt routine 6 TR1 Timer 1 Run Control Bit Set cleared by software to turn timer 1 on off 5 Timer 0 Overflow Flag Set by hardware when the timer 0 register overflows Cleared by hardware when the processor vectors to the interrupt routine 4 TRO Timer 0 Run Control Bit Set cleared by software to turn timer 1 on off 3 IE1 Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INT1 pin Edge or level triggered see IT1 Cleared when interrupt is processed if edge tr
294. imer register THO TLO to obtain the new value Calculate pulse width 12 x new value initial value Example Fog 16 MHz and 12Tosc 750 ns If the new value 10 000 and the initial value 0 the pulse width 750 ns x 10 000 7 5 ms 8 6 TIMER2 Timer 2 is a 16 bit timer counter The count is maintained by two eight bit timer registers TH2 and TL2 connected in cascade The timer counter 2 mode control register T2MOD Figure 8 11 on page 8 16 and the timer counter 2 control register T2CON Figure 8 12 on page 8 17 control the operation of timer 2 intel TIMER COUNTERS AND WATCHDOG TIMER Timer 2 provides the following operating modes capture mode auto reload mode baud rate gen erator mode and programmable clock out mode Select the operating mode with T2MOD and TCON register bits as shown in Table 8 3 on page 8 15 Auto reload is the default mode Setting RCLK and or TCLK selects the baud rate generator mode Timer 2 operation is similar to timer 0 and timer 1 C T2 selects Fosc 12 timer operation or external pin T2 counter operation as the timer register input Setting TF2 allows TL2 to be in cremented by the selected input The operating modes are described in the following paragraphs Block diagrams in Figures 8 7 through 8 10 show the timer 2 configuration for each mode 8 6 1 Capture Mode In the capture mode timer 2 functions as a 16 bit timer or counter Figure 8 7 An overflow con dition se
295. immediate and indirect Flags CY AC OV N 7 r4 Register 1 contains OC9H 11001001 and register 0 contains 01010100B The instruction CMP R1 RO clears the CY and AC flags and sets the OV flag Variations CMP Rmd Rms Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 1011 1100 ssss 5555 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP Rmd Rms CMP WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 1011 1110 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding A 47 INSTRUCTION SET REFERENCE Operation CMP WRjd WRjs CMP DRkd DRks Binary Mode Source Mode Bytes 3 2 States 5 4 Encoding 1011 1111 uuuu UUUU Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP DRkd DRks CMP Rm Zdata Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 1011 1110 ssss 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP Rm data WRj data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 1011 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP WRj data16 CMP DRk 0data16 Bytes States A 48 Binary Mode 5 6 Source Mode
296. indeterminate Do not write a 1 to this bit 6 ECOMx Compare Modes ECOMx 1 enables the module comparator function The comparator is used to implement the software timer high speed output pulse width modulation and watchdog timer modes 5 CAPPx Capture Mode Positive CAPPx 1 enables the capture function with capture triggered by a positive edge on pin CEXx 4 CAPNx Capture Mode Negative CAPNx 1 enables the capture function with capture triggered by a negative edge on pin CEXx 3 MATX Match Set ECOMx and MATx to implement the software timer mode When MATx 1 a match of the PCA timer counter with the compare capture register sets the CCFx bit in the CCON register flagging an interrupt 2 TOGx Toggle Set ECOMx MATx and TOGx to implement the high speed output mode When TOG x 1 a match of the PCA timer counter with the compare capture register toggles the pin 1 PWMx Pulse Width Modulation Mode PWMx 1 configures the module for operation as an 8 bit pulse width modulator with output waveform on the pin 0 ECCFx Enable CCFx Interrupt Enables compare capture flag CCFx in the CCON register to generate an interrupt request REGISTERS intel CCON Address Reset State S D8H 00X0 0000B PCA Timer Counter Control Register Contains the run control bit and overflow flag for the PCA timer counter and the compare capture flags for th
297. indicates whether a reset is a warm start or a cold start A cold start reset POF 1 is a reset that occurs after power has been off or has fallen below 3 V so the contents of volatile memory are indeterminate POF is set by hardware when Vcc rises from less than to its normal operating level See Power Off Flag on page 12 1 A warm start reset POF 0 is a reset that occurs while the chip is at operating voltage for exam ple a reset initiated by a WDT overflow or an external reset used to terminate the idle or power down modes 11 4 1 Externally Initiated Resets To reset the 8XC251Sx hold the RST pin at a logic high for at least 64 clock cycles 64Toso while the oscillator is running Reset can be accomplished automatically at the time power is ap plied by capacitively coupling RST to Vcc see Figure 11 1 and Power on Reset on page 11 7 The RST pin has a Schmitt trigger input and a pulldown resistor 11 4 2 WDT Initiated Resets Expiration of the hardware WDT overflow or the PCA WDT comparison match generates a reset signal WDT initiated resets have the same effect as an external reset See Watchdog Tim er on page 8 16 and PCA Watchdog Timer Mode on page 9 9 11 4 3 Reset Operation When a reset is initiated whether externally or by a WDT the port pins are immediately forced to their reset condition as a fail safe precaution whether the clock is running or not The external reset signal and the
298. indirect 3 6 2 5 LUMP addr16 Long jump 3 4 3 4 SJMP rel Short jump relative addr 2 3 2 3 JMP A DPTR Jump indir relative to the DPTR 1 5 1 5 JC rel Jump if carry is set 2 1 4 2 1 4 JNC rel Jump if carry not set 2 1 4 2 1 4 bit51 rel Jump if dir bit is set 3 2 5 3 2 5 JB bit rel Jump if dir bit of 8 bit addr location 5 4 7 4 3 6 is set bit51 rel Jump if dir bit is not set 3 2 5 3 2 5 JNB bit rel Jump if dir bit of 8 bit addr location 4 7 3 6 is not set bit51 rel Jump if dir bit is set amp clear bit 4 7 4 7 JBC Jump if dir bit of 8 bit addr location 7 10 4 6 9 is set and clear bit JZ rel Jump if acc is zero 2 2 5 2 2 5 JNZ rel Jump if acc is not zero 2 2 5 2 2 5 JE rel Jump if equal 3 2 5 2 1 4 JNE rel Jump if not equal 3 2 5 2 1 4 JG rel Jump if greater than 3 2 5 2 1 4 JLE rel Jump if less than or equal 3 2 5 2 1 4 NOTES 1 Ashaded cell denotes an instruction in the MCS 51 architecture 2 For conditional jumps times are given as not taken taken A 24 intel Table A 27 Summary of Control Instructions Continued INSTRUCTION SET REFERENCE Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States 2 Bytes States 2 JSL rel Jump if less than signed 3 2 5 2 1 4 JSLE rel Jump if less than or equal signed 3 2 5 2 1 4 JSG rel Jump if greater than signed 3 2 5 2 1 4 JSGE rel Jump if greater than or equal 3 2 5 2 1 4
299. ing multiplexed address data lines e g an Intel 8155 RAM I O Timer is connected to port 0 Port provides control lines for the external RAM ports 1 and 2 are used for normal I O RO and R1 contain 12H and 34H Location 34H of the external RAM contains 56H After executing the instruction sequence A 103 INSTRUCTION SET REFERENCE MOVX A QR1 MOVX the accumulator and external RAM location 12H contain 56H Variations MOVX A DPTR Binary Mode Source Mode Bytes 1 1 States 5 5 Encoding 1110 0000 Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOVX lt DPTR MOVX A Ri Binary Mode Source Mode Bytes 1 1 States 3 3 Encoding 1110 001i Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation MOVX lt Ri MOVX DPTR A Binary Mode Source Mode Bytes 1 1 States 5 5 Encoding 1111 0000 Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOVX A 104 DPTR lt intel MOVX QRi A Bytes States Encoding Hex Code in Operation MOVZ WRj Rm Function Description Flags Example Variations MOVZ WRj Rm Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Source Mode 1 1 4 4 1111 001i Binary Mode Encoding Source Mode A5 Encoding MOVX Ri lt Move 8 bi
300. ing and Verifying Nonvolatile 14 5 14 2 Program Verify Bus Cycles ssseeeeem meme 14 6 14 3 Program Verify Timing Diagram seem mm 14 11 xii intel CONTENTS TABLES Table Page 2 1 8 2515 SB SP SQ Feat reS vitinn e 2 3 3 1 Address Mappings EU MEDI 9 4 3 2 Minimum Times to Fetch Two Bytes of Code IRE 3 9 3 3 Register Bank 3 12 3 4 Dedicated Registers in the Register File and their Corresponding SFRs 3 15 3 5 8XC251SA SB SP SQ SFR and Reset 3 17 3 6 Core SERS 5 i ote ue rae br d 3 18 3 7 VO Pont SFRS aaae pet mn et entend 3 18 3 8 Serial SFRs EE 3 9 Timer Counter and Watchdog Timer SFRs JEN IR RA Use Ee ed Ph en De rh te o 3 19 3 10 Programmable Counter Array PCA 6 3 19 4 1 External Addresses for Configuration 4 4 4 2 Memory Signal Selections RD1 0 4 3 Memory Signal Selections RD1 0 A stepping 48 4 4 RD WR PSEN External Wait States rc UNA 4 5 Examples of Opcodes in Binary and Source Modes POMPIERS 4 18 5 1 DEYCNDU DTE 5 2 5 2 Notation for Byte Registers Word Registers and Dword Reg
301. ing length in bytes and execution time Add and Subtract Instructions Table A 19 on page A 14 Compare Instructions Table A 20 on page A 15 Increment and Decrement Instructions Table A 21 on page A 16 Multiply Divide and Decimal adjust Instructions Table A 22 on page A 16 Logical Instructions Table A 23 on page A 17 Move Instructions Table A 24 on page A 19 Exchange Push and Pop Instructions Table A 24 on page A 19 Bit Instructions Table A 26 on page A 23 Control Instructions Table A 27 on page A 24 Instruction Descriptions on page 26 contains a detailed description of each instruction NOTE The instruction execution times given in this appendix are for code executing from on chip code memory and for data that is read from and written to on chip RAM Execution times are increased by executing code from external memory accessing peripheral SFRs accessing data in external memory using a wait state or extending the ALE pulse For some instructions accessing the port SFRs Px x 0 3 increases the execution time These cases are listed in Table A 18 on page A 12 and are noted in the instruction summary tables and the instruction descriptions 1 INSTRUCTION SET REFERENCE A 1 NOTATION FOR INSTRUCTION OPERANDS Table A 1 Notation for Register Operands Register Notation M d Ri A memory location 00 addressed indirectly via byte register v RO or R1 Rn Byte register RO R7 of
302. initions 6 7 ISR See Interrupts service routine J JB instruction 5 14 A 24 JBC instruction 5 14 A 24 JC instruction A 24 JE instruction A 24 JG instruction A 24 JLE instruction A 24 JMP instruction A 24 JNB instruction 5 14 A 24 JNC instruction A 24 JNE instruction A 24 JNZ instruction A 24 Index 4 JSG instruction A 25 JSGE instruction A 25 JSL instruction A 25 JSLE instruction A 25 Jump instructions bit conditional 5 14 compare conditional 5 14 unconditional 5 15 JZ instruction A 24 K Key bytes See Encryption array L LCALL instruction 5 15 A 24 Level sensitive input B 2 LJMP instruction 5 15 A 24 Lock bits programming and verifying 14 1 14 8 protection types 14 9 setup for programming and verifying 14 4 14 5 Logical instructions 5 9 table of A 17 M MCS 251 microcontroller 2 1 core 2 4 features 2 1 MCS 51 microcontroller 2 1 Memory space 2 4 3 1 3 5 3 10 compatibility See Compatibility MCS 251 and MCS 51 architectures regions 3 2 3 5 reserved locations 3 5 Miller effect 11 5 MOV instruction A 19 A 20 A 21 for bits 5 11 A 23 MOVC instruction 3 2 5 10 A 21 Move instructions table of A 19 MOVH instruction 5 10 A 21 MOVS instruction 5 10 A 21 MOVX instruction 3 2 5 10 A 21 MOVZ instruction 5 10 A 21 MUL instruction 5 9 Multiplication 5 9 N flag 5 9 5 19 Noise reduction 11 2 11 3 11 5 Nonpage mode bus cycles See
303. instructions see Table 5 10 on page 5 17 6 AC Auxiliary Carry Flag The auxiliary carry flag is affected only by instructions that address 8 bit operands The AC flag is set if an arithmetic instruction with an 8 bit operand produces a carry out of bit 3 from addition or a borrow into bit 3 from subtraction Otherwise it is cleared This flag is useful for BCD arithmetic see Table 5 10 on page 5 17 5 FO Flag 0 This general purpose flag is available to the user 4 3 RS1 0 Register Bank Select Bits 1 and 0 These bits select the memory locations that comprise the active bank of the register file registers RO R7 RS1 RSO Bank Address 0 0 0 00 07 0 1 1 08 1 0 2 10H 17H 1 1 3 18H 1FH 2 OV Overflow Flag This bit is set if an addition or subtraction of signed variables results in an overflow error i e if the magnitude of the sum or difference is too great for the seven LSBs in 2 s complement representation The overflow flag is also set if a multiplication product overflows one byte or if a division by zero is attempted 1 UD User definable Flag This general purpose flag is available to the user 0 P Parity Bit This bit indicates the parity of the accumulator It is set if an odd number of bits in the accumulator are set Otherwise it is cleared Not all instruc tions update the parity bit The parity bit is set or cleared by instructions that change the contents of the accumulator
304. inter DPX DR56 REGISTERS intel DPL Address 5 82 Reset State 0000 0000B Data Pointer Low DPL provides SFR access to register file location 59 also named DPL DPL is the low byte of the 16 bit data pointer DPTR Instructions in the MCS 51 architecture use the 16 bit data pointer for data moves code moves and for a jump instruction JMP A DPTR See also DPH and DPXL 7 0 DPL Contents Bit Bit Number Mnemonic Function 7 0 DPL 7 0 Data Pointer Low Bits 0 7 of the extended data pointer DPX DR56 intel i REGISTERS DPXL Address 5 84 Reset State 0000 0001B Data Pointer Extended Low DPXL provides SFR access to register file location 57 also named DPXL Location 57 is the lower byte of the upper word of the extended data pointer DPX DR56 whose lower word is the 16 bit data pointer DPTR See also DPH and DPL 7 0 DPXL Contents Bit Bit Number Mnemonic Function 7 0 DPL 7 0 Data Pointer Extended Low Bits 16 23 of the extended data pointer DPX DR56 REGISTERS intel IEO Address Reset State S A8H 0000 0000B Interrupt Enable Register 0 IEO contains two types of interrupt enable bits The global enable bit EA enables disables all of the interrupts except the TRAP interrupt which is always enabled The remaining bits enable disable the other individual interrupts
305. isplacement of OFEH would be a one instruction infinite loop Binary Mode Source Mode Bytes 2 2 States 4 4 Encoding 1000 0000 rel addr Hex Code in Binary Mode Encoding Source Mode Encoding A 125 INSTRUCTION SET REFERENCE intel Operation SLL src Function Description Flags Example Variations SLL Rm Bytes States Encoding Hex Code in Operation SLL WRj Bytes States Encoding Hex Code in A 126 SJMP PC lt PC 2 lt PC rel Shift logical left by 1 bit Shifts the specified variable to the left by 1 bit replacing the LSB with zero The bit shifted out MSB is stored in the CY bit CY AC OV N 2 V Register 1 contains OC5H 11000101B After executing the instruction SLL register 1 Register 1 contains 8AH 10001010B and CY 1 Binary Mode Source Mode 3 2 2 1 0011 1110 ssss 0000 Binary Mode A5 Encoding Source Mode Encoding SLL 1 lt Rm a Rm 0 lt 0 CY lt Rm 7 Binary Mode Source Mode 3 2 2 1 0011 1110 tttt 0100 Binary Mode A5 Encoding Source Mode Encoding intel Operation SRA src Function Description Flags Example Variations SRA Rm Bytes States Encoding Hex Code in Operation SRA WRj Bytes States Encoding Hex Code in INSTRUCTION SET R
306. ister TLO so that the timer overflows after the desired number of peripheral cycles Enter an eight bit reload value ng in register THO This can be the same as ng or different depending on the application Set the TRO bit in the TCON register Figure 8 6 to start the timer Timer overflow occurs after 1 ng peripheral cycles setting the flag and loading n into TLO from THO When the interrupt is serviced hardware clears TFO The timer continues to overflow and generate interrupt requests every FFH 1 ng peripheral cycles To halt the timer clear the TRO bit Pulse Width Measurements For timer 0 and timer 1 setting GATEx and TRx allows an external waveform at pin INTx to turn the timer on and off This setup can be used to measure the width of a positive going pulse present at pin INTx Pulse width measurements using timer 0 in mode 1 can be made as follows 1 99s 254 TOUS Oe reb 20 Program the four low order bits of the TMOD register Figure 8 5 to specify mode 1 for timer 0 0 to select Fosc 12 as the timer input and GATEO 1 to select INTO as timer run control Enter an initial value of all zeros in the 16 bit timer register THO TLO or read and store the current contents of the register Set the TRO bit in the TCON register Figure 8 6 to enable INTO Apply the pulse to be measured to pin INTO The timer runs when the waveform is high Clear the TRO bit to disable INTO Read t
307. isters 5 8 5 3 Addressing Modes for Data Instructions in the MCS 51 Architecture 5 6 5 4 Addressing Modes for Data Instructions in the MCS 251 Architecture 5 7 5 5 Bit addressable 2511 5 6 Addressing Two Sample 5 12 5 7 Addressing Modes for Bit 5 12 5 8 Addressing Modes for Control Instructions sse 5 13 5 9 Compare conditional Jump Instructions 5 10 The Effects of Instructions on PSW and PSW1 Flags a aa aie noes 5 17 6 1 Interrupt System Pin Signals essen emen nene 6 1 6 2 Interrupt System Special Function Registers 2 6 3 6 3 Interrupt Control Matrix Ert 0A 6 4 Level of Priority EP 6 5 Interrupt Priority Within Level X 6 7 6 6 Interrupt Latency Variables 6 13 6 7 Actual vs Predicted Latency Calculations seruare ipee nde ene orla 7 1 Input Output Port Pin 7 1 7 2 Instructions for External Data 7 8 8 1 Timer Counter and Watchdog Timer SFRS esee een 8 2 8 2 External Signals ettet ibt aes red eed re eni nre e 8 3 8 3 Timer 2 Modes o
308. it digits Any ADD or ADDC instruction may have been used to perform the addition If accumulator bits 3 0 are greater than nine XXXX1010 XXXX1111 or if the AC flag is set six is added to the accumulator producing the proper BCD digit in the low nibble This internal addition sets the CY flag if a carry out of the lowest 4 bits propagated through all higher bits but it does not clear the CY flag otherwise If the CY flag is now set or if the upper four bits now exceed nine 1010XXXX 1111XXXX these four bits are incremented by six producing the proper BCD digit in the high nibble Again this sets the CY flag if there was a carry out of the upper four bits but does not clear the carry The CY flag thus indicates if the sum of the original two BCD variables is greater than 100 allowing multiple precision decimal addition The OV flag is not affected All of this occurs during one instruction cycle Essentially this instruction performs the decimal conversion by adding 00H 06H 60H or 66H to the accumulator depending on initial accumulator and PSW conditions Note DA A cannot simply convert a hexadecimal number in the accumulator to BCD notation nor does DA A apply to decimal subtraction OV N Z V 2 The accumulator contains 56H 01010110B which represents the packed BCD digits of the decimal number 56 Register 3 contains 67H 01100111B which represents the packed BCD digits of the dec
309. it of a frame has been received Cleared by software Figure 10 2 SCON Serial Port Control Register Continued 10 2 MODES OF OPERATION The serial I O port can operate in one synchronous and three asynchronous modes 10 2 1 Synchronous Mode Mode 0 Mode 0 is a half duplex synchronous mode which is commonly used to expand the I O capabil ities of a device with shift registers The transmit data TXD pin outputs a set of eight clock puls es while the receive data RXD pin transmits or receives a byte of data The eight data bits are transmitted and received least significant bit LSB first Shifts occur in the last phase S6P2 of every peripheral cycle which corresponds to a baud rate of Fosc 12 Figure 10 3 shows the timing for transmission and reception in mode 0 10 2 1 1 Transmission Mode 0 Follow these steps to begin a transmission 1 Write to the SCON register clearing bits SMO SM1 and REN 2 Write the byte to be transmitted to the SBUF register This write starts the transmission Hardware executes the write to SBUF in the last phase S6P2 of a peripheral cycle At S6P2 of the following cycle hardware shifts the LSB DO onto pin At S3PI of the next cycle the TXD pin goes low for the first clock signal pulse Shifts continue every peripheral cycle In the ninth cycle after the write to SBUF the MSB D7 is on the RXD pin At the beginning of the tenth cycle hardware drives
310. it states for RD WR PSEN for external accesses via region 01 RD1 0 00 is not valid for A stepping Refer to Table 4 2 Table 4 2 and Figures 4 3 through Figure 4 6 4 5 DEVICE CONFIGURATION intel UCONFIGO Address FF FFF8H 2 1 4 7 0 WSA1 WSA0 XALE RD1 RDO PAGE SRC Bit Bit Number Mnemonic F ncHon 7 Reserved Set this bit when writing to UCONFIGO 6 5 WSA1 0 Wait State A all regions except 01 3 For external memory accesses selects the number of wait states for RD WR and PSEN WSA1 WSAO 0 0 Inserts 3 wait states for all regions except 01 0 1 Inserts 2 wait states for all regions except 01 1 0 Inserts 1 wait state for all regions except 01 1 1 Zero wait states for all regions except 01 4 XALE Extend ALE Set this bit for ALE Togo Clear this bit for ALE 3Tos adds one external wait state 3 2 RD1 0 Memory Signal Selection RD1 0 bit codes specify an 18 bit 17 bit or 16 bit external address bus and address ranges for RD WR and PSEN See Table 4 2 1 PAGE Page Mode Select Clear this bit for page mode enabled with A15 8 D7 0 on P2 and A7 0 on PO Set this bit for page mode disabled with A15 8 on P2 and A7 0 D7 0 on PO compatible with 44 lead PLCC and 40 pin DIP MCS 51 microcontrollers 0 SRC Source Mode Binary Mode Select Clear this bit for binary mode opcodes compatible with MCS 51 microcon trollers
311. ith the indirect and displacement addressing modes Following a chip reset pro gram execution begins at FF 0000H Chapter 14 Programming and Verifying Nonvolatile Memory describes programming and verification of the ROM OTPROM EPROM A code fetch within the address range of the on chip ROM OTPROM EPROM accesses the on chip ROM OTPROM EPROM only if EA 1 For EA 0 a code fetch in this address range accesses external memory The value of EA is latched when the chip leaves the reset state Code is fetched faster from on chip code memory than from external memory Table 3 2 lists the min imum times to fetch two bytes of code from on chip memory and external memory 3 8 intel ADDRESS SPACES Table 3 2 Minimum Times to Fetch Two Bytes of Code Type of Code Memory State Times On chip Code Memory 1 External Memory page mode 2 External Memory nonpage mode 4 NOTE If your program executes exclusively from on chip ROM OTPROM EPROM not from external memory beware of executing code from the upper eight bytes of the on chip ROM OTPROM EPROM FF 1FF8H FF 1FFFH for 8 Kbytes FF 3FF8H FF 3FFFH for 16 Kbytes Because of its pipeline capability the 3X C251Sx may attempt to prefetch code from external memory at an address above FF 1FFFH FF 3FFFH and thereby disrupt I O ports 0 and 2 Fetching code constants from these eight bytes does not affect ports 0 and 2 If your program executes from both on chip
312. itself is not affected Only direct addressing is allowed for the source operand OV N 2 V 2 E Set the CY flag if and only if P1 0 1 ACC 7 1 and OV 0 MOV 1 0 carry with input pin state ANL CY ACC 7 AND carry with accumulator bit 7 ANL CY OV AND with inverse of overflow flag intel INSTRUCTION SET REFERENCE ANL CY bit51 Binary Mode Source Mode Bytes 2 2 States 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1000 0010 bit addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation ANL CY CY A bit51 ANL CY bit51 Binary Mode Source Mode Bytes 2 2 States 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1011 0000 bit addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation ANL CY CY bit51 ANL CY bit Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1010 1001 1000 0 yyy dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL CY CY A bit A 41 INSTRUCTION SET REFERENCE ANL CY bit Binary Mode Source Mode Bytes 4 3 States 3t 2t tlf this instruction addresses a port Px x
313. ive offset IF Ri lt data CJNE Rn data rel Bytes States Encoding Hex Code in Operation A 44 THEN CY 1 ELSE CY 0 Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 4 4 2 5 3 6 1 01 1 irrr immed data rel addr Binary Mode Encoding Source Mode A5 Encoding PC PC 3 IF Rn data THEN PC lt PC relative offset IF Rn data THEN CY 1 ELSE CY 0 intel CLRA Function Description Flags Example Bytes States Encoding Hex Code in Operation CLR bit Function Description Flags Example INSTRUCTION SET REFERENCE Clear accumulator Clears the accumulator i e resets all bits to zero CY AC OV N 2 The accumulator contains 5CH 01011100B The instruction CLRA clears the accumulator to 00H 00000000B Binary Mode Source Mode 1 1 1 1 1110 0100 Binary Mode Encoding Source Mode Encoding CLR 0 Clear bit Clears the specified bit CLR can operate on the CY flag or any directly addressable bit Only for instructions with CY as the operand OV N 2 V gt Port 1 contains 5DH 01011101B After executing the instruction CLR P1 2 port 1 contains 59H 01011001B A 45 INSTRUCTION SET REFERENCE
314. l REGISTERS SPH Address S BEH Reset State 0000 0000B Stack Pointer High SPH provides SFR access to location 62 in the register file also named SPH SPH is the upper byte of the lower word of DR60 the extended stack pointer SPX The extended stack pointer points to the current top of stack When a byte is saved PUSHed on the stack SPX is incremented and then the byte is written to the top of stack When a byte is retrieved POPped from the stack it is copied from the top of stack and then SPX is decremented 7 0 SPH Contents Bit Bit Number Mnemonic Function 7 0 SPH 7 0 Stack Pointer High Bits 8 15 of the extended stack pointer SPX DR 60 31 REGISTERS intel T2CON Address S C8H Reset State 0000 0000B Timer 2 Control Register Contains the receive clock transmit clock and capture reload bits used to configure timer 2 Also contains the run control bit counter timer select bit overflow flag external flag and external enable for timer 2 7 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 Bit Bit Number Mnemonic Function 7 TF2 Timer 2 Overflow Flag Set by timer 2 overflow Must be cleared by software TF2 is not set if RCLK 1 or TCLK 1 6 EXF2 Timer 2 External Flag If EXEN2 1 capture or reload caused by a negative transition on T2EX Sets EFX2 EXF2 does not cause an interrupt in up down counter mode DCEN
315. l Interrupt 0 Priority Bit Low Figure 6 4 Interrupt Priority Low Register intel INTERRUPT SYSTEM 6 7 INTERRUPT PROCESSING Interrupt processing is a dynamic operation that begins when a source requests an interrupt and lasts until the execution of the first instruction in the interrupt service routine see Figure 6 5 Response time is the amount of time between the interrupt request and the resulting break in the current instruction stream Latency is the amount of time between the interrupt request and the execution of the first instruction in the interrupt service routine These periods are dynamic due to the presence of both fixed time sequences and several variable conditions These conditions contribute to total elapsed time Response Time OSC State Time FLTLTLTLELTLTLTLTLTITLTLTLTLTLTLTLTLTLTLTUTLTLTLTLTLTLTLTLTLTLTLTLTLTTTLTI External N M Interrupt Request Ending Instructions Push PC call SR MESES zi Latency A4153 01 Figure 6 5 The Interrupt Process Both response time and latency begin with the request The subsequent minimum fixed sequence comprises the interrupt sample poll and request operations The variables consist of but are not limited to specific instructions in use at request time internal versus external interrupt source requests internal versus external program operation stack location presence of wait states page mode operation and bran
316. letion of the interrupt resets the in terrupt in progress priority and reloads the program counter Program operation then continues from the original point of interruption Table 6 1 Interrupt System Pin Signals Signal rs Multiplexed Description With INT1 0 External Interrupts 0 and 1 These inputs set bits IE1 0 in the P3 3 2 TCON register If bits IT1 0 in the TCON register are set bits IE1 0 are controlled by a negative edge trigger on INT1 INTO If bits INT1 0 are clear bits IE1 0 are controlled by a low level trigger on INT 1 0 NOTE Other pin signals are defined in their respective chapters and in Appendix B Signal Descrip tions INTERRUPT SYSTEM intel Interrupt Enable Priority Enable Highest Priority 0 gt o Interrupt INTO ITO IEO y z 0 0 1 1 Timer 0 TFO EE Pt INT1 IT1 IE1 EN H g Elias 1 DN o Timer 1 TF1 D uli D E 0 o PCA as Counter ECF i amp Overflow 1 B gt 5 0 l Match ECCFx Capture 1 5 1 1 Receive R eS Transmit ES J 1 1 Timer 2 TF2 i M T2EX EXF2 ET2 Lowest Priority Interrupt 4149 01 Figure 6 1 Interrupt Control System l ntel INTERRUPT SYSTEM Table 6 2 Interrupt System Special Function Registers Mnemonic Description Address IEO Interrupt Enable Re
317. m Status Word S DOH PSW1 Program Status Word 1 S D1H SP Stack Pointer LSB of SPX S 81H SPH Stack Pointer High MSB of SPX S BEH DPTR Data Pointer 2 bytes DPLi Low Byte of DPTR S 82H DPH High Byte of DPTR S 83H DPXL Data Pointer Extended Low 5 84 Power Control 5 87 IEO Interrupt Enable Control 0 S A8H IPHO Interrupt Priority Control High 0 S B7H IPLO Interrupt Priority Control Low 0 S B8H These SFRs can also be accessed by their corresponding registers in the register file see Table 3 4 on page 3 15 Table 3 7 I O Port SFRs Mnemonic Name Address PO Port 0 5 80 P1 Port 1 5 90 2 Port 2 S A0H P3 Port 3 S BOH intel ADDRESS SPACES Table 3 8 Serial I O SFRs Mnemonic Name Address SCON Serial Control 5 98 SBUF Serial Data Buffer 5 99 SADEN Slave Address Mask S B9H SADDR Slave Address S A9H Table 3 9 Timer Counter and Watchdog Timer SFRs Mnemonic Name Address TLO Timer Counter 0 Low Byte S 8AH THO Timer Counter 0 High Byte S 8CH TL1 Timer Counter 1 Low Byte S 8BH TH1 Timer Counter 1 High Byte S 8DH TL2 Timer Counter 2 Low Byte S CCH TH2 Timer Counter 2 High Byte S CDH TCON Timer Counter 0 and 1 Control 5 88 TMOD Timer Counter 0 and 1 Mode Control 5 89 T2CON Timer Counter 2 Control S C8H T2MOD Timer Counter 2 Mode Control S C9H RCAP2L Timer 2 Reload Capture Low Byte S CAH
318. mation that is useful in designing systems that incorporate the 8XC251Sx microcontroller To order documents please call Intel Literature Ful fillment 1 800 548 4725 in the U S and Canada 44 0 793 431155 in Europe Embedded Microcontrollers Order Number 270646 Embedded Processors Order Number 272396 Embedded Applications Order Number 270648 Packaging Order Number 240800 GUIDE TO THIS MANUAL intel 1 3 1 Data Sheet The data sheet is included in Embedded Microcontrollers and is also available individually 6XC2518A SB SP SQ High Performance CHMOS Microcontroller Order Number 272783 Commercial Express 1 3 2 Application Notes The following application notes apply to the MCS 251 microcontroller AP 125 Designing Microcontroller Systems Order Number 210313 for Electrically Noisy Environments AP 155 Oscillators for Microcontrollers Order Number 230659 AP 706 Introducing the MCS 251 Microcontroller Order Number 272670 the 8XC251SB AP 709 Maximizing Performance Using MCS9 251 Microcontroller Order Number 272671 Programming the 8XC251SB AP 710 Migrating from the MCS 51 Microcontroller to the MCS 251 Order Number 272672 Microcontroller 8XC251SB Software and Hardware Considerations The following MCS 51 microcontroller application notes also apply to the MCS 251 microcon troller AP70 Using the Intel MCS 51 Boolean Processing Capabilities Order Number 203830 AP 223 8051 Based CRT Terminal Controller O
319. memory into any 64 Kbyte memory region in the MCS 251 archi tecture provides complete run time compatibility because the lower 16 address bits are identical in the two address spaces The 256 bytes of on chip data memory for MCS 51 microcontrollers 00H FFH are mapped to addresses 00 0000H 00 00FFH to ensure complete run time compatibility In the MCS 51 archi tecture the lower 128 bytes OOH 7FH are directly and indirectly addressable however the up per 128 bytes are accessible by indirect addressing only In the MCS 251 architecture all locations in region 00 are accessible by direct indirect and displacement addressing see 8XC251SA SB SP SQ Memory Space on page 3 5 The 128 byte SFR space for MCS 51 microcontrollers is mapped into the 512 byte SFR space of the MCS 251 architecture starting at address S 080H as shown in Figure 3 3 This provides com plete compatibility with direct addressing of MCS 51 microcontroller SFRs including bit ad dressing The SFR addresses are unchanged in the new architecture In the MCS 251 architecture SFRs A B DPL DPH and SP as well as the new SFRs DPXL and SPH reside in the register file for high performance However to maintain compatibility they are also mapped into the SFR space at the same addresses as in the MCS 51 architecture 3 2 8XC251SA SB SP SQ MEMORY SPACE NOTE This section describes the memory space for the B stepping of the 8 2515 With some exceptions this
320. ments for three sample instructions Table 4 5 Examples of Opcodes in Binary and Source Modes Opcode Instruction Binary Mode Source Mode DECA 14H 14H SUBB A R4 9CH A59CH SUB R4 R4 A59CH 9CH 4 7 1 Selecting Binary Mode or Source Mode If you have code that was written for an MCS 51 microcontroller and you want to run it unmod ified on an MCS 251 microcontroller choose binary mode You can use the object code without reassembling the source code You can also assemble the source code with an assembler for the MCS 251 architecture and have it produce object code that is binary compatible with MCS 51 microcontrollers The remainder of this section discusses the selection of binary mode or source mode for code that may contain instructions from both architectures An instruction with a prefixed opcode requires one more byte for code storage and if an addition al fetch is required for the extra byte the execution time is increased by one state This means that using fewer prefixed opcodes produces more efficient code If a program uses only instructions from the MCS 51 architecture the binary mode code is more efficient because it uses no prefixes On the other hand if a program uses many more new instruc tions than instructions from the MCS 51 architecture source mode is likely to produce more ef ficient code For a program where the choice is not clear the better mode can be found by experimenting with a si
321. microcontroller type in the family has its own on chip peripherals I O ports external system bus size of on chip RAM and type and size of on chip program memory Table 2 1 lists the distinguishing features of the 8XC251SA SB SP SQ Thee 8XC2515x peripherals include a dedicated watchdog timer a timer counter unit a program mable counter array PCA and a serial I O unit The 8XC251Sx has four 8 bit I O ports PO P3 Each port pin can be individually programmed as a general I O signal or as a special function sig nal that supports the external bus or one of the on chip peripherals Ports PO and P2 comprise a 16 line external bus which transmits a 16 bit address multiplexed with 8 data bits You can also configure the 8 2515 to have a 17 bit or an 18 bit external address bus See Configuring the External Memory Interface on page 4 11 Ports P1 and P3 carry bus control and peripheral sig nals Table 2 1 8XC251SA SB SP SQ Features On chip Memory Part OTPROM Version ROM RAM x Number EPROM Stepping Kbytes Kbytes Bytes 80C251SB 0 0 1024 A B 80C251SQ 0 0 512 B 83 2515 0 8 1024 B 83C251SB 0 16 1024 A B 83C251SP 0 8 512 B 83C251SQ 0 16 512 B 87 2515 8 0 1024 87 2515 16 0 1024 87 2515 8 0 512 87 25150 16 0 512 Common features Address space 512 Kbytes 1 External Address bus 16 bit 17 bit or 18 bit 2 Register file 40 bytes lines 32 Interru
322. modify write instructions that read port 0 read this register The other instructions that read port 0 read the port 0 pins When port 0 is used for an external bus cycle the CPU always writes to PO and the former contents of PO are lost 7 0 Contents Bit Bit Number Mnemonic Function 7 0 P0 7 0 Port 0 Register Write data to be driven onto the port 0 pins to these bits REGISTERS intel P1 Address Reset State 5 90 1111 1111B Port 1 P1 is the SFR that contains data to be driven out from the port 1 pins Read write modify instructions that read port 1 read this register Other instructions that read port 1 read the port 1 pins 7 0 P1 Contents Bit Bit F rictior Number Mnemonic uneuo 7 0 P1 7 0 Port 1 Register Write data to be driven onto the port 1 pins to these bits intel REGISTERS P2 Address Reset State Port 2 P2 is the SFR that contains data to be driven out from the port 2 pins Read modify write instructions that read port 2 read this register Other instructions that read port 2 read the port 2 pins S A0H 1111 1111B 7 0 P2 Contents Bit Bit Number Mnemonic Function 7 0 2 7 0 Port 2 Register Write data to be driven onto the port 2 pins to these bits REGISTERS intel P3 7 Address Reset State S BOH 1111 1111B Port 3 P3 is the SFR th
323. mory locations memory One additional port pin 1 1 P1 7 CEX4 RD asserted Asserted for Asserted only for 64 Kbyte external for addresses gt 80 0000H writes to MCS 51 memory Compatible lt 7F FFFFH microcontroller data with MCS 51 micro memory locations controllers NOTE RD1 0 are bits 3 2 of configuration byte UCONFIGO Figure 4 3 on page 4 6 Table B 5 Memory Signal Selections RD1 0 A stepping all addresses all memory locations RD1 0 P3 7 RD A16 PSEN WR Features 0 0 Reserved Reserved Reserved Reserved 0 1 A16 Asserted for Asserted for writes to 128 Kbyte external all addresses all memory locations memory 10 P3 7 only Asserted for Asserted for writes to One additional port pin RD asserted for lt 7F FFFFH Asserted for gt 80 0000H Asserted only for writes to locations 00 0000 01 Compatible with MCS 51 microcon trollers NOTE RD1 0 are bits 3 2 of configuration byte CONFIGO Figure 4 5 page 4 9 intel Registers REGISTERS APPENDIX C REGISTERS Table C 1 8XC251SA SB SP SQ Special Function Registers SFRs SFR Binary Reset Value Mnemonic SFR Name Hex Address High Low Acct Accumulator S EOH 0000 0000 Bt B Register S FOH 0000 0000 CCAPOH PCA Module 0 Compare Capture S FAH XXXX XXXX Register High Byte CCAPOL PCA Module 0 Co
324. mpare Capture S EAH XXXX XXXX Register Low Byte CCAP1H PCA Module 1 Compare Capture S FBH XXXX XXXX Register High Byte CCAP1L PCA Module 1 Compare Capture S EBH XXXX XXXX Register Low Byte CCAP2H PCA Module 2 Compare Capture S FCH XXXX XXXX Register High Byte CCAP2L PCA Module 2 Compare Capture S ECH XXXX XXXX Register Low Byte CCAP3H PCA Module 3 Compare Capture S FDH XXXX XXXX Register High Byte CCAP3L PCA Module 3 Compare Capture S EDH XXXX XXXX Register Low Byte CCAP4H PCA Module 4 Compare Capture S FEH XXXX XXXX Register High Byte CCAP4L PCA Module 4 Compare Capture S EEH XXXX XXXX Register Low Byte CCAPMO PCA Compare Capture Module 0 S DAH X000 0000 Mode Register CCAPM1 PCA Compare Capture Module 1 S DBH X000 0000 Mode Register CCAPM2 PCA Compare Capture Module 2 S DCH X000 0000 Mode Register CCAPM3 PCA Compare Capture Module 3 S DDH X000 0000 Mode Register CCAPM4 PCA Compare Capture Module 4 S DEH X000 0000 Mode Register CCON PCA Timer Counter Control S D8H 00X0 0000 Register This register resides in the register file It can also be accessed as an SFR REGISTERS intel Table C 1 8XC251SA SB SP SQ Special Function Registers SFRs SFR Binary Reset Value Mnemonic SFR Name Hex Address High Low CH PCA Timer Counter High Byte S F9H 0000 0000 CL PCA Timer Counter Low Byte S E9H 0000 0000 CMOD PCA Timer
325. mplemented See Figures 4 5 and 4 6 for bit assignments Addresses 82H and 83H are reserved for future use 4 2 intel DEVICE CONFIGURATION The CONFIGO and CONFIGI configuration bytes can programmed by the user or programmed at the factory See Configuration Bytes on page 14 8 The B stepping 8XC251SB can be configured as A stepping compatible See Device Configu ration A stepping Compatible on page 4 5 4 4 THE CONFIGURATION BITS This section provides a brief description of the configuration bits contained in the configuration bytes Figures 4 3 through 4 6 The B stepping and A stepping configuration bytes have the same configuration bits except for wait state bits UCONFIGI 0 have five wait state bits WSA1 0 WSB1 0 and WSB retained for compatibility CONFIG1 0 have two wait state bits WSA and WSB SRC Selects source mode or binary mode opcode configuration INTR Selects the bytes pushed onto the stack by interrupts Maps on chip code memory 16 Kbyte devices only to memory region 00 The following bits configure the external memory interface PAGE Selects page nonpage mode and specifies the data port e RDI O Selects the number of external address bus pins and the address range for RD WR and PSEN For B stepping see Table 4 2 For A stepping see Table 4 2 XALE Extends the ALE pulse WSA A stepping only Selects 0 or 1 wait states for all memory regions except 01 WSB
326. mulator intel DEVICE CONFIGURATION 5 Prefix OH 5H 6H FH 6H FH OH MCS 51 MCS 51 MCS 251 Architecture Architecture Architecture A4131 01 Figure 4 9 Binary Mode Opcode Map 5 Prefix OH 5H 6H FH 6H FH OH II FH MCS 51 MCS 251 MCS 51 Architecture Architecture Architecture A4130 01 Figure 4 10 Source Mode Opcode Map 4 19 DEVICE CONFIGURATION intel 4 8 MAPPING ON CHIP CODE MEMORY TO DATA MEMORY EMAP For devices with 16 Kbytes of on chip code memory 87C251SB SQ and 83C251SB SQ the bit UCONFIG1 0 and CONFIGI 0 provides the option of accessing the upper half of on chip code memory as data memory This allows code constants to be accessed as data in region 00 using direct addressing See Accessing On chip Code Memory in Region 00 on page 3 9 for the exact conditions required for this mapping to be effective EMAP 0 For 87C251SB 83C251SB A stepping and B stepping and 87C251SQ 83C25 1SQ B stepping only the upper 8 Kbytes of on chip code memory FF 2000 FF 3FFFH are mapped to locations 00 E000H 00 FFFFH 1 Mapping of on chip code memory to region 00 does not occur Addresses in the range 00 E000H 00 FFFFH access external RAM 4 9 INTERRUPT STACK MODE INTR The INTR bit UCONFIGI 4 or CONFIG1 4 determines what bytes are stored on the stack when an interrupt occurs and how the RETI Return from Interrupt instruction restores operati
327. n chip RAM locations 40H 50H and 60H contain 01H 70H and 15H respectively After executing the following instruction sequence DJNZ 40H LABEL1 DJNZ 50H LABEL2 DJNZ 60H LABEL on chip RAM locations 40H 50H and 60H contain 00H 6FH and 14H respectively and program execution continues at label LABEL2 The first jump was not taken because the result was zero This instruction provides a simple way of executing a program loop a given number of times or for adding a moderate time delay from 2 to 512 machine cycles with a single instruction The instruction sequence MOV R2 8 TOGGLE CPL P1 7 DJNZ R2 TOGGLE toggles P1 7 eight times causing four output pulses to appear at bit 7 of output Port 1 Each pulse lasts three states two for DJNZ and one to alter the pin Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 3 3 3 6 3 6 1101 0101 direct addr rel addr intel Hex Code in Operation DJNZ Rn rel Bytes States Encoding Hex Code in Operation ECALL lt dest gt Function Description Flags Example INSTRUCTION SET REFERENCE Binary Mode Encoding Source Mode Encoding DJNZ PC PC 2 dir8 lt dir8 1 IF dir8 gt 0 or dir8 lt 0 THEN PC lt PC rel Binary Mode Source Mode Not Taken Taken Not Taken Taken 2 2 3 3 2 5 3 6 1101 1rrr rel addr Binary Mode Encoding Source Mode A
328. n overflow occurred If there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not bit 6 the OV flag is set When adding signed integers the OV flag indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Bit 6 and bit 7 in this description refer to the most significant byte of the operand 8 16 or 32 bit Four source operand addressing modes are allowed register direct register indirect and immediate A 32 INSTRUCTION SET REFERENCE Flags CY AC OV N 2 accumulator contains 11000011B register 0 contains OAAH 10101010 and the CY flag is set After executing the instruction ADDC A RO the accumulator contains 6EH 01101110B the AC flag is clear and the CY and OV flags are set Variations ADDC A data Binary Mode Source Mode Bytes 2 2 States 1 1 Encoding 0011 0100 immed data Hex Code in Binary Mode Encoding Source Mode Encoding Operation ADDC A lt A CY data ADDC 8 Binary Mode Source Mode Bytes 2 2 States 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0011 0101 direct addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation ADDC A lt A CY dir8 ADDC A Ri Binary Mode Source Mode Bytes 1 2 States 2 3 Encoding
329. nal interrupt 0 Figure 6 2 Interrupt Enable Register 6 6 INTERRUPT PRIORITIES Each of the seven 8XC251Sx interrupt sources may be individually programmed to one of four priority levels This is accomplished with the IPHO x IPLO x bit pairs in the interrupt priority high IPHO and interrupt priority low IPLO registers Figures 6 3 and 6 4 on page 6 8 Specify the priority level as shown in Table 6 4 using IPHO x as the MSB and IPLO x as the LSB intel INTERRUPT SYSTEM Table 6 4 Level of Priority IPHO X MSB IPLO X LSB Priority Level 0 0 Lowest Priority 1 1 1 0 2 1 1 3 Highest Priority A low priority interrupt is always interrupted by a higher priority interrupt but not by another in terrupt of equal or lower priority The highest priority interrupt is not interrupted by any other in terrupt source Higher priority interrupts are serviced before lower priority interrupts The response to simultaneous occurrence of equal priority interrupts 1 sampled within the same four state interrupt cycle is determined by a hardware priority within level resolver see Table 6 5 Table 6 5 Interrupt Priority Within Level Priority Number Interrupt Name 1 Highest Priority INTO 2 Timer 0 3 INT1 4 Timer 1 5 Serial Port 6 Timer 2 7 Lowest Priority PCA NOTE The 8XC251Sx interrupt priority within level table Table 6 5 differs
330. nary source opcodes interrupt stack mode and mapping a portion of on chip code memory to data memory It describes the configuration bytes and how to program them for the desired configu ration It also describes how internal memory space maps into external memory Chapter 5 Programming provides an overview of the instruction set It describes each in struction type control arithmetic logical etc and lists the instructions in tabular form This chapter also discusses the addressing modes bit instructions and the program status words Appendix A provides a detailed description of each instruction Chapter 6 Interrupts describes the 8XC251Sx interrupt circuitry which provides a TRAP instruction interrupt and seven maskable interrupts two external interrupts three timer interrupts a PCA interrupt and a serial port interrupt This chapter also discusses the interrupt priority scheme interrupt enable interrupt processing and interrupt response time 8XC251SA SB SP SQ is also referred to herein as 8XC251Sx GUIDE TO THIS MANUAL intel Chapter 7 Input Output Ports describes the four 8 bit I O ports ports 0 3 and discusses their configuration for general purpose I O external memory accesses ports 0 2 and alternative special functions Chapter 8 Timer Counters and WDT describes the three on chip timer counters and discusses their application This chapter also provides instructions for usi
331. nch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice CY AC OV N 2 The Z flag is set After executing the instruction JE LABEL1 program execution continues at label LABEL 1 Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0110 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JE PC PC 2 IF 2 1 THEN PC lt PC rel Jump if greater than If the Z flag and the CY flag are both clear branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice CY AC OV N 2 71 INSTRUCTION SET REFERENCE Example Bytes States Encoding Hex Code in Operation JLE rel Function Description Flags Example Bytes States Encoding Hex Code in A 72 intel The instruction JG LABEL1 causes program execution to continue at label LABEL 1 if the Z flag and the CY flag are both clear Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0011 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JG PC PC 2 IF Z 0 AND CY 0
332. nemonics are shown in upper case to avoid confusion When writing code either upper case or lower case may be used GUIDE TO THIS MANUAL intel Logic 0 Low Logic 1 High Numbers Register Bits Register Names Reserved Bits Set and Clear Signal Names An input voltage level equal to or less than the maximum value of Vi or an output voltage level equal to or less than the maximum value of Vor See data sheet for values An input voltage level equal to or greater than the minimum value of or an output voltage level equal to or greater than the minimum value of Voy See data sheet for values Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H Decimal and binary numbers are represented by their customary notations That is 255 is a decimal number and 1111 1111 is a binary number In some cases the letter B is added for clarity Bit locations are indexed by 7 0 for byte registers 15 0 for word registers ands 31 0 for double word dword registers where bit O is the least significant bit and 7 15 or 31 is the most significant bit An individual bit is represented by the register name followed by a period and the bit number For example PCON 4 is bit 4 of the power control register In some discussions bit names are used For example the name of PCON 4 is POF the power off flag Register names are shown in upper case For example PCON is the power control
333. nformation from a configuration array located at the highest addresses implemented in external user memory using internal addresses FF FFF8H FF FFF9H The address of the configuration array in external memory depends on the size of the external memory see Table 4 1 WSB For B stepping applications treat WSB as a reserved bit i e write a 1 to this bit WSB1 WSBO For A stepping compatible applications program WSB1 1 and WSBO WSB Instructions for programming and verifying on chip configuration bytes are given in Chapter 14 Figure 4 4 User Configuration Byte UCONFIG1 DEVICE CONFIGURATION intel Table 4 2 Memory Signal Selections RD1 0 B stepping RD1 0 P1 7 CEX A17 P3 7 RD A16 PSEN WR Features 00 17 A16 Asserted for Asserted for writes to 256 Kbyte external all addresses all memory locations memory 0 1 P1 7 CEX4 A16 Asserted for Asserted for writes to 128 Kbyte external all addresses all memory locations memory 10 P1 7 CEX4 P3 7 only Asserted for Asserted for writes to 64 Kbyte external all addresses all memory locations memory One additional port pin 1 1 P1 7 CEX4 RD asserted Asserted for Asserted only for 64 Kbyte external for addresses gt 80 0000H writes to MCS 51 memory Compatible lt 7F FFFFH microcontroller data with MCS 51 micro memory locations controllers Table 4 3 Memory Signal Selections RD1 0 A steppi
334. ng RD1 0 P3 7 RD A16 PSEN WR Features 0 0 Reserved Reserved Reserved Reserved 0 1 A16 Asserted for Asserted for writes to 128 Kbyte external all addresses all memory locations memory 10 P3 7 only Asserted for Asserted for writes to One additional port pin all addresses all memory locations 1 1 RD asserted for Asserted for Asserted only for Compatible with MCS lt 7F FFFFH gt 80 0000H writes to locations 51 microcontrollers 00 0000H 01 FFFFH intel DEVICE CONFIGURATION CONFIGO 1 2 3 7 0 WSA XALE RD1 RDO PAGE SRC Bit Bit Function Number Mnemonic 7 6 Reserved Set these bits when writing to CONFIGO 5 WSA Wait State A Regions 00 FE and FF Clear this bit to generate one external wait state for memory regions 00 FE and FF Set this bit for no wait states for these regions 4 XALE Extend ALE If this bit is set the time of the ALE pulse is Clearing this bit extends the time of the ALE pulse from to 3Tosc which adds one external wait state 3 2 RD1 0 Memory Signal Selection RD1 0 bit codes specify a 17 bit or 16 bit external address bus and address ranges for RD WR and PSEN See Table 4 2 1 PAGE Page Mode Select Clear this bit for page mode A15 8 D7 0 on P2 and A7 0 on PO Set this bit for nonpage mode A15 8 on P2 and A7 0 D7 0 on PO compatible with 44 pin PL
335. ng the hardware watch dog timer WDT and describes the operation of the WDT during the idle and powerdown modes Chapter 9 Programmable Counter Array PCA describes the PCA on chip peripheral and explains how to configure it for general purpose applications timers and counters and spe cial applications programmable WDT and pulse width modulator Chapter 10 Serial I O Port describes the full duplex serial I O port and explains how to program it to communicate with external peripherals This chapter also discusses baud rate gen eration framing error detection multiprocessor communications and automatic address recog nition Chapter 11 Minimum Hardware Considerations describes the basic requirements for operating the 8 2515 1 system It also discusses on chip and external clock sources and de scribes device resets including power on reset Chapter 12 Special Operating Modes provides an overview of the idle powerdown and on circuit emulation ONCE modes and describes how to enter and exit each mode This chapter also describes the power control PCON special function register and lists the status of the device pins during the special modes and reset Table 12 1 Chapter 13 External Memory Interface describes the external memory signals and bus cycles and provides examples of external memory design It provides waveform diagrams for the bus cycles bus cycles with wait states and the con
336. not write a 1 to this bit 6 IPHO 6 PCA Interrupt Priority Bit High 5 IPHO 5 Timer 2 Overflow Interrupt Priority Bit High 4 IPHO 4 Serial I O Port Interrupt Priority Bit High 3 IPHO 3 Timer 1 Overflow Interrupt Priority Bit High 2 IPHO 2 External Interrupt 1 Priority Bit High 1 IPHO 1 Timer 0 Overflow Interrupt Priority Bit High 0 0 0 External Interrupt 0 Priority Bit High REGISTERS intel IPLO Address Reset State S B8H X000 0000B Interrupt Priority Low Control Register 0 IPLO together with IPHO assigns each interrupt a priority level from 0 lowest to 3 highest IPHO x IPLO x Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPLO 6 IPLO 5 IPLO 4 IPLO 3 IPLO 2 IPLO 1 IPLO O Function 7 Reserved The value read from this bit is indeterminate Do not write a 1 to this bit 6 IPLO 6 PCA Interrupt Priority Bit Low 5 IPLO 5 Timer 2 Overflow Interrupt Priority Bit Low 4 IPLO 4 Serial I O Port Interrupt Priority Bit Low 3 IPLO 3 Timer 1 Overflow Interrupt Priority Bit Low 2 IPLO 2 External Interrupt 1 Priority Bit Low 1 IPLO 1 Timer 0 Overflow Interrupt Priority Bit Low 0 IPLO O External Interrupt 0 Priority Bit Low intel REGISTERS PO Address S 80H Reset State 1111 1111B Port 0 PO is the SFR that contains data to be driven out from the port 0 pins Read
337. nstead of executing the next in struction in the queue the processor executes a target instruction The control instruction provides the address of a target instruction either implicitly as in a return from a subroutine or explicitly in the form of a relative direct or indirect address MCS 251 microcontrollers have a 24 bit program counter PC which allows a target instruction to be anywhere in the 16 Mbyte address space However as discussed in this section some con trol instructions restrict the target address to the current 2 Kbyte or 64 Kbyte address range by allowing only the lowest 11 or lowest 16 bits of the program counter to change intel PROGRAMMING 5 5 1 Addressing Modes for Control Instructions Table 5 8 lists the addressing modes for the control instructions Relative addressing The control instruction provides the target address as an 8 bit signed offset rel from the address of the next instruction Direct addressing The control instruction provides a target address which can have 11 bits addr11 16 bits addr16 or 24 bits addr24 The target address is written to the PC addr11 Only the lower 11 bits of the PC are changed i e the target address must be in the current 2 Kbyte block the 2 Kbyte block that includes the first byte of the next instruction addr16 Only the lower 16 bits of the PC are changed i e the target address must be in the current 64 Kbyte region the 64 Kbyte region th
338. nstruction addresses an port x 0 3 add 2 to the number of states INSTRUCTION SET REFERENCE Table A 23 Summary of Logical Instructions Continued intel Logical AND ANL lt dest gt lt sre gt dest dest A src Logical OR ORL lt dest gt lt srce gt dest opnd lt dest opnd V src opnd Logical Exclusive OR XRL lt dest gt lt srce gt dest opnd lt dest opnd V src opnd Clear CLRA 0 Complement CPLA Ai O Ai Rotate RXX A 1 Shift SXX Rm or Wj 1 SWAP A A3 0 lt gt 7 4 Binary Mode Source Mode Mnemonic dest src Notes Bytes States Bytes States SRA Rm Shift byte reg right through the MSB 3 2 2 1 WRj Shift word reg right through the MSB 3 2 2 1 Rm Shift byte reg right 3 2 2 1 SRL Xa WRj Shift word reg right 3 2 2 1 SWAP A Swap nibbles within the acc 1 2 1 2 NOTES 1 Instruction Descriptions on page A 26 2 shaded cell denotes an instruction in the MCS 51 architecture 3 fthis instruction addresses an I O port x 0 3 add 1 to the number of states 4 fthis instruction addresses an I O port Px x 0 3 add 2 to the number of states intel INSTRUCTION SET REFERENCE Table A 24 Summary of Move Instructions Move 2 Move with Sign Extension Move with Zero Extension Move Code Byte Move to External Mem Move from External Mem MOV lt dest gt lt src gt
339. ntly selected by the DRO DR2 1 PSW and PSW1 Immediate N A Operand is in the _ Used only in increment and 2 bits instruction ey ond decrement instructions Immediate N A Operand is in the _ 8 bits instruction data8 00 Immediate N A Operand is in the _ 16 bits instruction data16 0000H FFFFH Bici 00 0000H 00 007FH dir8 00 0000H 00 007FH On chip RAM irect 8 address bits dir8 S 080H S 1FFH 2 SFRs or SER mnemonic SFR address Direct 00 0000H 00 FFFFH dirt6 00 0000H 00 FFFFH 16 address bits i Indirect Lon 16 address bits 00 0000H 00 FFFFH WRO WR30 Indirect DRO DR30 DR56 Upper 8 bits of DRk must be 24 address bits 00 0000H FF FFFFH DR60 OOH Displacement 16 address bits 00 0000H 00 FFFFH WRj dis16 WRO through WR30 FFFFH Offset is signed address wraps around in region 00 Displacement 24 address bits 00 0000H FF FFFFH DRk dis24 DRO OH through DR28 FFFFH DR56 OH FFFFH DR60 OH FFFFH Offset is signed upper 8 bits of DRk must be 00H NOTES 1 These registers are accessible in the memory space as well as in the register file see 8 2515 SB SP SQ Register File on page 3 10 2 MCS 251 architecture supports SFRs in locations S 000H S 1FFH however in the 8 2515 all SFRs are in the range S 080H S 0FFH PROGRAMMING intel
340. oding Operation XRL Rm lt Rm v dir8 XRL WRij dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0110 1110 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL WRj lt v dir8 XRL Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0110 1110 ssss 0011 direct addr dir8 addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL A 142 Rm lt Rm v dir16 intel XRL WRj dir16 INSTRUCTION SET REFERENCE Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0110 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL WRj lt WRj v dir16 XRL Rm wrj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0110 1110 tttt 1001 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rm lt Rm v WRj XRL Rm Drk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0110 1110 uuuu 1011 ssss 0000 Hex Code In Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rm lt Rm v DRk 143 intel B signal Descriptions APPENDIX B SIGNAL DESCRIPTIONS This appendix provides reference information for the pin functions of the 8XC251S
341. omprise the 16 bit data pointer DPTR While instructions in the MCS 51 architecture always use DPTR as the data point er instructions in the MCS 251 architecture can use any word or dword register as a data pointer DPXL the byte in location 57 specifies the region of memory 00 FF that maps into the 64 Kbyte external data memory space in the MCS 51 architecture In other words the MOVX in struction addresses the region specified by DPXL when it moves data to and from external mem ory The reset value of DPXL is 01H 3 3 2 3 Extended Stack Pointer SPX Dword register DR60 is the stack pointer SPX Figure 3 8 The byte at location 63 is the 8 bit stack pointer SP in the MCS 51 architecture The byte at location 62 is the stack pointer high SPH The two bytes allow the stack to extend to the top of memory region 00 SP and SPH can be accessed as SFRs Two instructions PUSH and POP directly address the stack pointer Subroutine calls ACALL ECALL LCALL and returns ERET RET RETI also use the stack pointer To preserve the stack do not use DR60 as a general purpose register Table 3 4 Dedicated Registers in the Register File and their Corresponding SFRs Register File SFRs Name Mnemonic Reg Location Mnemonic Address 60 Stack 61 Pointer DR60 SPX Stack Pointer High SPH 62 SPH S BEH Stack Pointer Low
342. on For INTR 0 an interrupt pushes the two lower bytes of the PC onto the stack in the following order PC 7 0 PC 15 8 The RETI instruction pops these two bytes in the reverse order and uses them as the 16 bit return address in region FF For INTR 1 an interrupt pushes the three PC bytes and the PSWI register onto the stack in the following order PSW1 PC 23 16 PC 7 0 PC 15 8 The RETI instruction pops these four bytes and then returns to the specified 24 bit address which can be anywhere in the 16 Mbyte address space 4 20 intel Programming intel CHAPTER 5 PROGRAMMING The instruction set for the 251 architecture is a superset of the instruction set for the MCS 51 architecture This chapter describes the addressing modes and summarizes the instruc tion set which is divided into data instructions bit instructions and control instructions Appen dix A Instruction Set Reference contains an opcode map and a detailed description of each instruction The program status words PSW and PSW1 are also described page 5 16 NOTE The instruction execution times given in Appendix A are for code executing from on chip code memory and for data that is read from and written to on chip RAM Execution times are increased by executing code from external memory accessing peripheral SFRs accessing data in external memory using a wait state or extending the ALE pulse For some instructions accessing the port SF
343. on This is not so much to protect the EPROM array from inadvertent erasure as to protect the RAM and other on chip logic Allowing light to impinge on the silicon die during device operaton may cause a logical malfunction 14 2 PROGRAMMING AND VERIFYING MODES Table 14 1 lists the programming and verifying modes and provides details about the setup The value applied to port 0 determines the mode The upper digit specifies program or verify and the lower digit selects what memory function is programmed i e on chip code memory encryption array configuration bytes etc The addresses applied to port 1 and port 3 address locations in the selected memory function The encryption array lock bits signature bytes and A stepping con figuration bytes CONFIGO and reside in nonvolatile memory outside the memory address space B stepping user configuration bytes UCONFIGO and UCONFIGI reside in non volatile memory at top of the memory address space for ROM OTPROM EPROM devices Fig ure 4 1 and in external memory for devices without ROM OTPROM EPROM Figure 4 2 14 3 GENERAL SETUP Figure 14 1 shows the general setup for programming and verifying nonvolatile memory on the 87C25 1Sx The figure also applies to verifying the 83 2515 and reading the configuration bytes on the 80C251SB SQ The controller must be running with an oscillator frequency of 4 MHz to 6 MHz To program set up the controller as shown in Table 14 1 with the
344. on bits P3 6 RD1 0 11 WR is asserted for writes to all compatible MCS 51 microcontroller memory locations For other values of RD1 0 WR is asserted for writes to all memory locations t The descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the nonpage mode chip configuration compatible with 44 pin PLCC MCS 51 microcontrollers If the chip is configured for page mode operation port 0 carries the low er address bits A7 0 and port 2 carries the upper address bits A15 8 and the data D7 0 13 2 intel e EXTERNAL MEMORY INTERFACE 13 2 EXTERNAL BUS CYCLES The section describes the bus cycles the 8XC251Sx executes to fetch code read data and write data in external memory Both page mode and nonpage mode are described and illustrated For simplicity the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing information This section does not cover wait states see External Bus Cycles with Wait States on page 13 8 or configuration byte bus cycles see Configuration Byte Bus Cycles on page 13 10 For bus cycle timing parameters see External Bus AC Timing Specifications on page 13 25 An inactive external bus exists when the 8XC251Sx is not executing external bus cycles This occurs under any of the three following conditions Bus Idle The chip is in normal operating mode but no external bus cycles are executing The chip is in idle mode
345. on of voltage and therefore logic levels at the pin For example a port bit used to drive the base of an external bipolar transistor cannot rise above the transistor s base emitter junction voltage a value lower thanV With a logic one written to the bit attempts by the CPU to read the port at the pin are misinterpreted as logic zero A read of the latch rather than the pin returns the correct logic one value 7 6 QUASI BIDIRECTIONAL PORT OPERATION Port 1 port 2 and port 3 have fixed internal pullups and are referred to as quasi bidirectional ports When configured as an input the pin impedance appears as logic one and sources current see 8 2515 datasheet in response to an external logic zero condition Port 0 is a true bidi rectional pin The pin floats when configured as input Resets write logical one to all port latches If logical zero is subsequently written to a port latch it can be returned to input conditions by a logical one written to the latch For additional electrical information refer to the current 8 2515 datasheet 7 5 INPUT OUTPUT PORTS intel NOTE Port latch values change near the end of read modify write instruction cycles Output buffers and therefore the pin state update early in the instruction after the read modify write instruction cycle Logical zero to one transitions in port 1 port 2 and port 3 utilize an additional pullup to aid this logic transition see Figure 7 4 This
346. on power up connect the RST pin to the Voc pin through a 1 uF capacitor as shown in Figure 11 1 When Vecis applied the RST pin rises to Vcc then decays exponentially as the capacitor charg es The time constant must be such that RST remains high above the turn off threshold of the Schmitt trigger long enough for the oscillator to start and stabilize plus 64 Tos At power up Vcc should rise within approximately 10 ms Oscillator start up time is a function the crystal fre quency typical start up times are 1 ms for a 10 MHz crystal and 10 ms for a 1 Mhz crystal During power up the port pins are in a random state until forced to their reset state by the asyn chronous logic Reducing V quickly to 0 causes the RST pin voltage to momentarily fall below 0 V This volt age is internally limited and does not harm the device 11 7 MINIMUM HARDWARE SETUP RST XTAL Internal Reset Routine PSEN ALE lt gt 64 7 ze pH 1 2 3 32 mS Figure 11 5 Reset Timing Sequence A4103 01 intel 12 Special Operating Modes intel CHAPTER 12 SPECIAL OPERATING MODES This chapter describes the power control PCON register and three special operating modes idle powerdown and on circuit emulation ONCE 12 1 GENERAL The idle and powerdown modes are power reduction modes for use in applications where power consumption is a con
347. onal 8 bit timer or counter TLO uses the timer 0 control bits C TO and GATEO in TMOD and TRO and TFO in TCON in the normal manner THO is locked into a timer function counting Fosc 12 and takes over use of the timer interrupt TF1 and run control TR1 bits Thus operation of timer 1 is restricted when timer 0 is in mode 3 See Timer 1 on page 8 6 and 3 Halt on page 8 9 8 5 TIMER COUNTERS AND WATCHDOG TIMER intel 8 4 TIMER 1 Timer 1 functions as either a timer or event counter in three modes of operation Figures 8 2 and 8 3 show the logical configuration for modes 0 1 and 2 Timer 1 s mode 3 is a hold count mode Timer 1 is controlled by the four high order bits of the TMOD register Figure 8 5 and bits 7 6 3 and 2 of the TCON register Figure 8 6 The TMOD register selects the method of timer gating GATE1 timer or counter operation T C1 and mode of operation M11 and MOI The TCON register provides timer 1 control functions overflow flag TF1 run control TR 1 inter rupt flag IE1 and interrupt type control Timer 1 operation in modes 1 and 2 is identical to timer 0 Timer 1 can serve as the baud rate generator for the serial port Mode 2 is best suited for this purpose For normal timer operation 0 setting TR1 allows timer register TL1 to be increment ed by the selected input Setting GATE1 and TR1 allows external pin INT1 to control timer op eration
348. onding SFRs are illustrated in Figure 3 8 and listed in Table 3 4 3 3 2 1 Accumulator and B Register The 8 bit accumulator ACC is byte register R11 which is also accessible in the SFR space as ACC at S 0EOH Figure 3 8 The B register used in multiplies and divides is register R10 which is also accessible in the SFR space as B at S 0F0H Accessing ACC or B as a register is one state faster than accessing them as SFRs 3 13 ADDRESS SPACES intel Instructions in the MCS 51 architecture use the accumulator as the primary register for data moves and calculations However in the MCS 251 architecture any of registers 15 can serve for these tasksT As a result the accumulator does not play the central role that it has in MCS 51 microcontrollers Register File SFRs Stack Pointer High Stack Pointer 60 61 62 63 DR60 Extended Stack Pointer SPX Data Pointer Extended Low Data Pointer High S 83H S 82H R10 B Register R11 Accumulator ACC A4152 02 Figure 3 8 Dedicated Registers in the Register File and their Corresponding SFRs t Bits in the PSW and PSWI registers reflect the status of the accumulator There are no equivalent status indicators for the other registers 3 14 intel ADDRESS SPACES 3 3 2 2 Extended Data Pointer DPX Dword register DR56 is the extended data pointer DPX Figure 3 8 The lower three bytes of DPX DPL DPH and DPXL are accessible as SFRs DPL and DPH c
349. onfiguration information into the on chip configuration bytes and other catego ries of information into on chip memory outside the memory address space The verify instruc tions permit reading these memory locations to verify their contents The operations covered in this chapter are programming and verifying the on chip code memory 8 Kbytes 16 Kbytes programming and verifying the on chip configuration bytes 4 bytes A stepping 8 bytes B stepping programming and verifying the lock bits 3 bits programming the encryption array 128 bytes verifying the signature bytes 3 bytes Programming instructions apply to the 87C251Sx one time programmable ROM OTPROM and erasable programmable ROM EPROM Verify instructions apply to the 87 2515 the 83C251Sx mask ROM and the configuration bytes on the 80C251SB SQ no ROM OTPROM EPROM In the unprogrammed state EPROM and OTPROM contains all 1s 14 4 GENERAL The 87C251Sx is programmed and verified in the same manner as the 87C51FX using the same quick pulse programming algorithm which programs at Vy 12 75 V using a series of five 100 us PROG pulses per byte This results in a programming time of approximately 16 seconds for the 16 Kbyte on chip code memory Programming and verifying operations differ from normal microcontroller operation Memory accesses are made one byte at a time input output ports are used in a different manner and the EA V pp and ALE PR
350. ord Register 2 19 Program Status Word 1 eene emen 5 19 Interrupt Control System ocior n nennt einen enden ern 6 2 Interrupt Enable Register 4 6 6 Interrupt Priority High Register essen emen 6 8 Interrupt Priority Low Register eene enne 6 8 tLhe Interrupt Process d eee dne ede rer e ene tee re Rt 6 9 Response Time Example 1 6 11 Response Time Example 2 6 12 Port 1 and Port 3 Structure eere eene O Port 0 Structure O Port 2 Structure 535 MD LC EN Internal Pullup Configurations oni ath a even estie 7 6 Basic Logic of the Timer Counters 2 Timer 0 1 in Mode 0 and 1 8 4 Timer 0 1 in Mode 2 8 55 Timer 0 in Mode 3 Two 8 bit 8 6 Timer Counter Mode Control Register B7 TCON Timer Counter Control 8 8 Timer 2 Gaptu re Mode nn eec Ee 8 11 Timer 2 Auto Reload Mode 0 emm emen 8 12 Timer 2 Auto Reload Mode 1 8 13 intel CONTENTS Figure 8 10 8 11 8 12 9 1 9 2 9 4 9 5 9 7 9 8 10 1 10 2 10 3 10 4 10 5 11 1 11 2 11 8 11 4 11 5
351. ord register is unchanged CY AC OV The dword register DRk contains 5566 7788H After the instruction MOVH DRk 1122H executes DRk contains 1122 7788H MOVH DRk data16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0111 1010 uuuu 1100 hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOVH DRk 31 16 data16 MOVS WRj Rm Function Move 8 bit register to 16 bit register with sign extension Description Moves the contents of an 8 bit register to the low byte of a 16 bit register The high byte of the 16 bit register is filled with the sign extension which is obtained from the MSB of the 8 bit source register Flags CY AC OV N Z Example Eight bit register Rm contains 055H 01010101B and the 16 bit register WRj contains A 102 OFFFFH 11111111 11111111B The instruction MOVSE WRj Rm moves the contents of register Rm 01010101B to register WRj i e WRj contains 00000000 01010101B intel Variations MOVS WRj Rm Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Source Mode 3 2 2 1 0001 1010 tttt ssss Binary Mode A5 Encoding Source Mode Encoding MOVS WRj 7 0 lt 7 0 WRj 15 8 MSB MOVX lt dest gt lt src gt Function Description Flags Ex
352. ory Address Space 512 Kbytes FFFFH FF 0000H 128 Kbytes External Flash FE FD FC 03 02 01 128 Kbytes 1056 Bytes FFFFH External RAM 00 00 0000H 0420H 1056 Bytes On chip RAM A4220 01 13 14 Figure 13 13 Memory Space for Example 1 intel EXTERNAL MEMORY INTERFACE 13 6 2 Example 2 RD1 0 01 17 bit Bus External Flash and RAM In this example an 80C251SB operates in page mode with a 17 bit external address bus inter faced to 64 Kbytes of flash memory for code storage and 32 Kbytes of external RAM Figure 13 14 The 80C251SB A stepping or B stepping is configured so that PSEN is asserted for all reads and RD functions as A16 RD1 0 01 Figure 13 15 shows how the external flash and RAM are addressed in the internal memory space For an A stepping device regions 02 03 FC and FD are absent Addresses 0420H 7FFFH in external RAM are addressed in region 00 On chip data RAM 1056 bytes occupies the lowest addresses in region 00 80C251SB CER RAM FLASH 32 Kbytes 64 Kbytes A16 D7 0 D7 0 A15 8 D7 0 OE WE A4148 01 Figure 13 14 Bus Diagram for Example 2 80C251SB in Page Mode 13 15 EXTERNAL MEMORY INTERFACE FF FE FD FC 03 02 01 00 00 0000H Memory Address Space 512 Kbytes FFFFH 0000H 0420H ZFFFH 64 Kbytes External Flash 32 Kby
353. ow Priority Me 1 5 4 2 1 High Priority Bit Names in IPHO Reserved IPHO 6 IPHO 5 IPHO 4 IPHO 3 IPHO 2 IPHO 1 0 0 0 Reserved IPLO 6 IPLO 5 IPLO 4 0 3 0 2 0 1 0 0 Programmable for Negative edge Triggered or Level NA Edge No No No Yes No Yes triggered Detect Interrupt Request Flag in CCON CF TF2 T2CON SCON or NA exF2 RN E TER IED TCON Register Interrupt Request Edge Edge Flag Cleared by No No No No Yes Yes Yes Yes Hardware Level No Level No ISR Vector Address NA FF FF FF FF FF FF FF 0033H 002BH 0023H 001BH 0013H 000BH 0003H 6 2 2 Timer Interrupts Two timer interrupt request bits and TF1 see TCON register Figure 8 6 on page 8 8 are set by timer overflow the exception is Timer 0 in Mode 3 see Figure 8 4 on page 8 6 When a timer interrupt is generated the bit is cleared by an on chip hardware vector to an interrupt service rou tine Timer interrupts are enabled by bits ETO and ET2 in the IEO register see Figure 6 2 on page 6 6 Timer 2 interrupts are generated by a logical OR of bits TF2 and EXF2 in register T2CON see Figure 8 12 on page 8 17 Neither flag is cleared by a hardware vector to a service routine In fact the interrupt service routine must determine if TF2 or EXF2 generated the interrupt and then clear the bit Timer 2 interrupt is enabled by ET2 in register
354. p volatile memory is indeterminate Set or cleared by software 3 GF1 General Purpose Flag Set or cleared by software One use is to indicate whether an interrupt occurred during normal operation or during idle mode 2 GFO General Purpose Flag Set or cleared by software One use is to indicate whether an interrupt occurred during normal operation or during idle mode 1 PD Powerdown Mode Bit When set activates powerdown mode Cleared by hardware when an interrupt or reset occurs 0 IDL Idle Mode Bit When set activates idle mode Cleared by hardware when an interrupt or reset occurs If IDL and PD are both set PD takes precedence C 21 REGISTERS intel PSW Address S DOH Reset State 0000 0000B Program Status Word PSW contains bits that reflect the results of operations bits that select the register bank for registers RO R7 and two general purpose flags that are available to the user d 0 FO RS1 RSO OV UD Bit Bit f Number Mnemonic Function 7 Carry Flag The carry flag is set by an addition instruction ADD ADDC if there is a carry out of the MSB It is set by a subtraction SUB SUBB or compare CMP if a borrow is needed for the MSB The carry flag is also affected by some rotate and shift instructions logical bit instructions bit move instructions and the multiply MUL and decimal adjust DA instructions see Tabl
355. patibility MCS 251 and MCS 51 architectures 2 1 3 2 3 5 address spaces 3 2 3 4 external memory 3 5 instruction set 5 1 SFR space 3 5 See also Binary and source modes CONFIGO 4 2 CONFIGI 4 2 Configuration array 4 2 external 4 5 on chip 4 4 bits 4 3 external memory 4 11 overview 4 1 Configuration bytes A stepping 4 2 A stepping compatible 4 5 B stepping 4 2 bus cycles 13 10 CONFIGO table 4 9 CONFIGI table 4 10 programming and verifying 14 1 UCONFIGO table 4 6 UCONFIGI table 4 7 Control instructions 5 1 5 12 5 16 addressing modes 5 12 5 13 Index 2 intel table of A 24 Core 2 4 SFRs 3 18 CPL instruction 5 9 5 11 A 17 A 23 CPU 2 5 block diagram 2 5 Crystal for on chip oscillator 11 3 CY flag 5 18 5 19 D DA instruction A 16 Data instructions 5 1 5 4 5 10 addressing modes 5 4 Data pointer See DPH DPL DPTR DPX DPXL Data transfer instructions 5 10 table of A 22 See also Move instructions Data types 5 2 DEC instruction 5 8 A 16 Destination register 5 3 Device signal descriptions B 2 dir16 A 3 dir8 A 3 Direct addressing 5 4 in control instructions 5 13 Displacement addressing 5 4 5 8 DIV instruction 5 9 A 16 Division 5 9 DJNZ instruction A 25 Documents related 1 5 DPH DPL 3 15 C 11 C 12 as SFRs 3 17 3 18 DPTR 3 15 in jump instruction 5 13 DPX 3 5 3 13 3 15 5 5 DPXL 3 15 C 13 as SFR 3 17 3 18 external data memory map
356. pin T2 0 DCEN Down Count Enable Bit Configures timer 2 as an up down counter Figure 8 11 T2MOD Timer 2 Mode Control Register 8 7 WATCHDOG TIMER The peripheral section of the 8 2515 contains a dedicated hardware watchdog timer WDT that automatically resets the chip if it is allowed to time out The WDT provides a means of re covering from routines that do not complete successfully due to software malfunctions The WDT described in this section is not associated with the PCA watchdog timer which is implemented in software 8 7 1 Description The WDT is a 14 bit counter that counts peripheral cycles i e the system clock divided by twelve 12 WDTRST special function register at address S A6H provides control access to the WDT Two operations control the WDT Device reset clears and disables the WDT see Reset on page 11 5 Writing a specific two byte sequence to the WDTRST register clears and enables the WDT If it is not cleared the WDT overflows on count 3FFFH 1 With Fosc 16 MHz a peripheral cycle is 750 ns and the WDT overflows in 750 x 16384 12 288 ms The WDTRST is a write only register Attempts to read it return FFH The WDT itself is not read or write accessible The WDT does not drive the external RESET pin intel TIMER COUNTERS AND WATCHDOG TIMER T2CON Address S C8H Reset State 0000 0000B 7 0 TF2 EXF2 RCLK TCLK
357. ping 3 5 5 5 5 10 reset value 3 5 E 3 8 description 13 2 ECALL instruction 5 15 A 24 ECI 7 1 intel EJMP instruction 5 15 A 24 EMAP bit 3 9 4 20 Encryption 14 2 Encryption array key bytes 14 9 programming 14 1 14 9 setup for programming 14 4 14 5 ERET instruction 5 15 A 24 Escape prefix A5H 4 18 extended ALE A 1 A 11 Extended stack pointer See SPX External address lines number of 4 11 See also External bus External bus AC timing definitions 13 31 AC timing specifications 13 25 13 31 inactive 13 3 pin status 13 11 13 12 structure in page mode nonpage mode 13 6 External bus cycles 13 3 definitions 13 3 extended ALE wait state 13 10 extended PSEN RD WR wait state 13 8 extended RD WR PSEN wait state 13 8 nonpage mode 13 4 13 5 page mode 13 6 13 8 page hit vs page miss 13 6 External code memory example 13 15 13 25 idle mode 12 4 powerdown mode 12 5 External memory 3 10 design examples 13 12 13 25 MCS 51 architecture 3 2 3 4 3 5 External memory interface 13 1 configuring 4 11 4 20 signals 13 1 External RAM example 13 21 exiting idle mode 12 5 F FO flag 5 18 Flash memory example 13 13 13 15 13 25 INDEX G Given address See Serial I O port Ground bounce 11 2 H Hardware application notes 1 6 T O ports 7 1 7 8 external memory access 7 7 latches 7 2 loading 7 7 pullups 7 6 quasi bidirectional 7 5 SFRs 3 18 See al
358. pins are reading data Table 12 1 External program memory the ALE and PSEN pins are pulled low the port 0 pins are floating and the pins of ports 1 2 and 3 are reading data Table 12 1 NOTE Vcc may be reduced to as low as 2 V during powerdown to further reduce power dissipation Take care however that Vcc is not reduced until power down is invoked 12 5 SPECIAL OPERATING MODES intel 12 4 1 Entering Powerdown Mode To enter powerdown mode set the PCON register PD bit The 8 2515 enters the power down mode upon execution of the instruction that sets the PD bit The instruction that sets the PD bit is the last instruction executed 12 4 2 Exiting Powerdown Mode CAUTION If Vcc was reduced during the powerdown mode do not exit powerdown until Vec 15 restored to the normal operating level There are two ways to exit the powerdown mode Generate an enabled external interrupt Hardware clears the PD bit in the PCON register which starts the oscillator and restores the clocks to the CPU and peripherals Execution resumes with the interrupt service routine Upon completion of the interrupt service routine program execution resumes with the instruction immediately following the instruction that activated powerdown mode NOTE To enable an external interrupt set the IE register and or EX1 bit s The external interrupt used to exit powerdown mode must be configured as level sensitive and must be assigne
359. pt You can enable or disable the interrupts individually except for TRAP and you can assign one of four priority levels to each interrupt See Chapter 6 Interrupt System for a detailed description 2 2 4 On chip Code Memory For 83C2518A ROM and 87C251SA OTPROM EPROM devices memory locations FF 0000H FF 1FFFH are implemented with 8 Kbytes of on chip code memory For 83C251SB and 87C251SB devices memory locations FF 0000H FF 3FFFH are implemented with 16 Kbytes of on chip code memory Following a reset the first instruction is fetched from location FF 0000H For 80C251SB SQ no ROM OTPROM EPROM devices location FF 0000H is always in external memory 2 2 5 On chip RAM The 8XC251SA and 8XC251SB have 1 Kbyte of on chip data RAM at locations 20H 41FH 8XC251SP and 8XC251SQ have 512 bytes of on chip data RAM at locations 20H 21FH These RAM locations can be accessed with direct indirect and displacement addressing Ninety six of these locations 20H 7FH are bit addressable An additional 32 bytes of on chip RAM 00H 1FH provide storage for the four banks of registers RO R7 2 3 ON CHIP PERIPHERALS The on chip peripherals which lie outside the core perform specialized functions Software ac cesses the peripherals via their special function registers SFRs The 8XC251Sx has four periph erals the watchdog timer the timer counters the programmable counter array PCA and the serial I O port 2 3 1 Timer Count
360. pt sources 11 NOTES 1 256 Kbytes for A stepping 2 16 bit or 17 bit for A stepping 2 3 ARCHITECTURAL OVERVIEW intel The 8XC251Sx has two power saving modes In idle mode the CPU clock is stopped while clocks to the peripherals continue to run In powerdown mode the on chip oscillator is stopped and the chip enters a static state An enabled interrupt or a hardware reset can bring the chip back to its normal operating mode from idle or powerdown See Chapter 12 Special Operating Modes for details on the power saving modes MCS 251 microcontrollers use an instruction set that has been expanded to include new opera tions addressing modes and operands Many instructions can operate on 8 16 or 32 bit oper ands providing easier and more efficient programming in high level languages such as C Additional new features include the TRAP instruction a new displacement addressing mode and several conditional jump instructions Chapter 5 Programming describes the instruction set and compares it with the instruction set for MCS 51 microcontrollers You can configure the 8XC251Sx to run in binary mode or source mode Either mode executes all of the MCS 51 architecture instructions and all of the MCS 251 architecture instructions How ever source mode is more efficient for MCS 251 architecture instructions and binary mode is more efficient for MCS 51 architecture instructions In binary mode object code for an MCS 51
361. quirements see the device data sheet Figure 11 4 shows the clock drive waveform The external clock source must meet the minimum high and low times Toycx and and the maximum rise and fall times Torcy and to minimize the effect of ex ternal noise on the clock generator circuit Long rise and fall times increase the chance that ex ternal noise will affect the clock circuitry and cause unreliable operation The external clock driver may encounter increased capacitance loading at XTAL due to the Miller effect of the internal inverter as the clock waveform builds up in amplitude following power on Once the input waveform requirements are met the input capacitance remains under 20 pF A4119 01 Figure 11 4 External Clock Drive Waveforms 11 4 RESET A device reset initializes the 8X C251Sx and vectors the CPU to address FF 0000H A reset is re quired after applying power at turn on A reset is a means of exiting the idle and powerdown modes or recovering from software malfunctions To achieve a valid reset V must be within its normal operating range see device data sheet and the reset signal must be maintained for 64 clock cycles 64 lt after the oscillator has sta bilized Device reset is initiated in two ways externally by asserting the RST pin internally if the hardware WDT or the PCA WDT expires MINIMUM HARDWARE SETUP intel The power off flag POF in the PCON register
362. r Control Register Contains the run control bit and S D8H the overflow flag for the PCA timer counter and interrupt flags for the five compare capture modules CMOD PCA Timer Counter Mode Register Contains bits for disabling the PCA S D9H timer counter during idle mode enabling the PCA watchdog timer module 4 selecting the timer counter input and enabling the PCA timer counter overflow interrupt CCAPOH PCA Module 0 Compare Capture Registers This register pair stores the S FAH CCAPOL comparison value or the captured value In the PWM mode the low byte S EAH register controls the duty cycle of the output waveform CCAP1H PCA Module 1 Compare Capture Registers This register pair stores the S FBH CCAP1L comparison value or the captured value In the PWM mode the low byte S EBH register controls the duty cycle of the output waveform CCAP2H PCA Module 2 Compare Capture Registers This register pair stores the S FCH CCAP2L comparison value or the captured value In the PWM mode the low byte S ECH register controls the duty cycle of the output waveform CCAP3H PCA Module 3 Compare Capture Registers This register pair stores the S FDH CCAP3L comparison value or the captured value In the PWM mode the low byte S EDH register controls the duty cycle of the output waveform CCAP4H PCA Module 4 Compare Capture Registers This register pair stores the S FEH CCAP4L comparison value or the captured value In the PWM mode the low byte S EEH re
363. r depends on wait states See the table of AC characteristics TLLAX C TRHLH TRHDZ2 TRHDX C ne JH o Tava Tavpv1 9 T Avpv2 gt A7 0 A16 A17 Data In A4212 02 13 30 Figure 13 28 External Bus Cycle Timing Data Read in Page Mode EXTERNAL MEMORY INTERFACE WR lt lt 9 TAVWL2 gt PO A16 A17 A7 0 A16 A17 The value of this parameter depends on wait states See the table of AC characteristics lt lt TwHQX Data Out TWHAX gt A4182 01 Figure 13 29 External Bus Cycle Timing Data Write in Page Mode 13 7 2 AC Timing Definitions This section defines the timing parameters shown in Figures 13 24 through 13 29 Tables 13 5 and 13 6 list the definitions of timing specifications for 8XC251Sx and the memory system 13 31 EXTERNAL MEMORY INTERFACE Table 13 5 AC Timing Definitions for Specifications on the 8XC251Sx In tel THE 8XC251Sx MEETS THESE SPECIFICATIONS Symbol Definition Notes Fosc Frequency on XTAL Frequency of the signal input on the XTAL1 input Tosc 1 Fosc Period of the signal on XTAL1 XTAL2 AC Timings are referenced to Togc ALE Pulse Width Length of time ALE is asserted
364. ray Signature bytes Rotate instructions 5 9 RR instruction A 17 RRC instruction A 17 RST 11 6 11 7 exiting idle mode 12 5 exiting powerdown mode 12 6 ONCE mode 12 7 power on reset 11 7 programming and verifying nonvolatile memory 14 3 RXD 7 1 10 1 mode 0 10 4 modes 1 2 3 10 6 S SADDR 3 17 3 19 10 2 10 8 10 9 10 10 C 25 SADEN 3 17 3 19 10 2 10 8 10 9 10 10 C 26 Sampled input B 2 SBUF 3 17 3 19 10 2 10 4 10 5 C 27 SCON 3 17 3 19 10 2 10 3 10 4 10 5 10 6 10 7 C 28 C 29 bit definitions 10 3 interrupts 6 5 Security 14 2 Serial I O port 10 1 10 14 asynchronous modes 10 6 automatic address recognition 10 7 10 10 baud rate generator 8 9 baud rate mode 0 10 4 10 10 baud rate modes 1 2 3 10 6 10 10 10 14 broadcast address 10 9 data frame modes 1 2 3 10 6 framing bit error detection 10 7 full duplex 10 6 given address 10 8 half duplex 10 4 interrupts 10 1 10 8 mode 0 10 4 10 5 modes 1 2 3 10 6 multiprocessor communication 10 7 SFRs 3 19 10 1 10 2 synchronous mode 10 4 timer 1 baud rate 10 11 10 12 INDEX timer 2 baud rate 10 12 10 14 timing mode 0 10 5 SETB instruction 5 11 A 23 SFRs accessing 3 16 address space 3 1 3 2 idle mode 12 4 map 3 17 MCS 51 architecture 3 4 powerdown mode 12 5 reset initialization 11 6 reset values 3 16 tables of 3 18 unimplemented 3 2 3 16 Shift instruction 5 9 Signal descriptions
365. rce Figure 11 3 or it can generate the clock signal using the on chip oscillator amplifier and external capacitors and resonator Figure 11 2 11 3 1 On chip Oscillator Crystal This clock source uses an external quartz crystal connected from XTALI to XTAL2 as the fre quency determining element Figure 11 2 The crystal operates in its fundamental mode as an inductive reactance in parallel resonance with capacitance external to the crystal Oscillator de sign considerations include crystal specifications operating temperature range and parasitic board capacitance Consult the crystal manufacturer s data sheet for parameter values With high quality components C1 C2 30 pF is adequate for this application Pins XTAL1 and XTAL2 are protected by on chip electrostatic discharge ESD devices D1 and D2 which are diodes parasitic to the FETs They serve as clamps to Voc and Feedback resistor R in the inverter circuit formed from paralleled n and p channel FETs permits the PD bit in the PCON register Figure 12 1 on page 12 2 to disable the clock during powerdown Noise spikes at XTAL1 and XTAL2 can disrupt microcontroller timing To minimize coupling between other digital circuits and the oscillator locate the crystal and the capacitors near the chip and connect to XTAL1 XTAL2 and with short direct traces To further reduce the effects of noise place guard rings around the oscillator circuitry and ground the metal
366. rd Registers Register File DR24 DR28 DR16 DR20 DR12 ROT A4099 01 Figure 3 6 The Register File ADDRESS SPACES intel Register file locations 0 7 actually consist of four switchable banks of eight registers each as il lustrated in Figure 3 7 on page 3 12 The four banks are implemented as the first 32 bytes of on chip RAM and are always accessible as locations 00 0000H 00 001FH in the memory address space T Only one of the four banks is accessible via the register file at a given time The accessi ble or active bank is selected by bits RS1 and RSO in the PSW register as shown in Table 3 3 The PSW is described in Program Status Words on page 5 16 This bank selection can be used for fast context switches Register file locations 8 31 and 56 63 are always accessible These locations are implemented as registers in the CPU Register file locations 32 55 are reserved and cannot be accessed Register File Memory Address Space 8 1 2 3 4 5 6 7 PSW bits RS1 0 select one bank to be accessed via the register file A4215 01 Figure 3 7 Register File Locations 0 7 Table 3 3 Register Bank Selection PSW Selection Bits Bank Address Range RS1 RSO Bank 0 00H 07H 0 0 Bank 1 08H 0FH 0 1 Bank 2 10H 17H 1 0 Bank 3 18H 1FH 1 1 t Because these locations are dedicated to the register file they are not consi
367. rder Number 270032 252 Designing With the 80C51BH Order Number 270068 AP 425 Small DC Motor Control Order Number 270622 AP 410 Enhanced Serial Port on the S3C51FA Order Number 270490 AP 415 83C51FA FB PCA Cookbook Order Number 270609 AP 476 How to Implement PC Serial Communication Order Number 272319 Using Intel MCS 51 Microcontrollers intel GUIDE TO THIS MANUAL 1 44 CUSTOMER SERVICE This section provides telephone numbers and describes various customer services Technical Support U S and Canada 800 628 8686 916 356 7599 and 916 356 6100 fax Customer Training U S and Canada 800 234 8806 Product Literature 800 548 4725 U S and Canada 708 296 9333 U S from overseas 44 0 1793 431155 Europe U K 44 0 1793 421333 Germany 44 0 1793 421777 France 81 0 120 47 88 32 Japan fax only FaxBack Service 800 525 3019 U S and Canada 44 0 1793 496646 Europe 503 264 6835 U S Canada Japan Asia Pacific Application Bulletin Board System 800 897 2536 U S and Canada 916 356 3600 U S Canada Japan Asia Pacific up to 19 2 Kbaud line 916 356 7209 U S Canada Japan Asia Pacific dedicated 2400 baud line 44 0 1793 496340 Europe Intel provides 24 hour automated technical support through our FaxBack service and our central ized Intel Application Bulletin Board System BBS The FaxBack service is a simple to use in formation system tha
368. re 9 1 depicts the basic logic of timer counter portion of The CH CL special function register pair operates as a 16 bit timer counter The selected input increments the CL low byte register When CL overflows the CH high byte register increments after two oscil lator periods when CH overflows it sets the PCA overflow flag CF in the CCON register gen erating a PCA interrupt request if the ECF bit in the CMOD register is set The 51 and 50 bits in the CMOD register select one of four signals as the input to the timer counter Figure 9 7 on page 9 13 Fos 12 Provides an clock pulse at S5P2 of every peripheral cycle With Fog 16 MHz the time counter increments every 750 nanoseconds e Fosc 4 Provides clock pulses at S1P2 S3P2 and S5P2 of every peripheral cycle With 16 MHz the time counter increments every 250 nanoseconds Timer 0 overflow The CL register is incremented at S5P2 of the peripheral cycle when timer 0 overflows This selection provides the PCA with a programmable frequency input External signal on P1 2 ECI The CPU samples the pin at 51 2 S3P2 and S5P2 of every peripheral cycle The first clock pulse S1P2 S3P2 or S5P2 that occurs following a high to low transition at the ECI pin increments the CL register The maximum input frequency for this input selection is Fosc 8 For a description of peripheral cycle timing see Clock and Reset Unit on page 2 6
369. rea outside the memory address space For a detailed discussion of device configuration see Chapter 4 ROM OTPROM EPROM devices have on chip user code memory at FF 0000 FF 1FFFH 8 Kbytes or FF 0000H FF 3FFFH 16 Kbytes Addresses outside these ranges access external memory With 1 and both on chip and external code memory you can place code at the highest addresses of the on chip ROM OTPROM EPROM When the highest on chip address is exceeded during execution code fetches automatically rollover from on chip memory to external memory See the dual note on page 3 9 With EA 1 and only on chip code memory multibyte instructions and instructions that result in call returns or prefetches should be located a few bytes below the maximum address to avoid inadvertently exceeding the top address Use an EJMP instruction five or more addresses below the top of memory to continue execution in other areas of memory See the dual note on page 3 9 CAUTION Execution of user code located in the top few bytes of the on chip user memory may cause prefetches from the next higher addresses i e external memory External memory fetches make use of port 0 and port 3 and may disrupt program execution if the program uses port 0 or port 3 for a different purpose 14 2 intel PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 14 1 2 EPROM Devices On EPROM devices the quartz window must be covered with an opaque label when the device is in operati
370. register If register name contains lowercase character it represents more than one register For example CCAPMXx represents the five registers CCAPMO through CCAPM4 Some registers contain reserved bits These bits are not used in this device but they may be used in future implementations Do not write a 1 to a reserved bit The value read from a reserved bit is indeter minate The terms set and clear refer to the value of a bit or the act of giving it a value If a bit is set its value is 1 setting a bit gives it a 1 value If a bit is clear its value is 0 clearing a bit gives it a 0 value Signal names are shown in upper case When several signals share a common name an individual signal is represented by the signal name followed by a number Port pins are represented by the port abbrevi ation a period and the pin number e g P0 0 PO 1 pound symbol appended to a signal name identifies an active low signal intel GUIDE TO THIS MANUAL Units of Measure The following abbreviations are used to represent units of measure A amps amperes DCV direct current volts Kbyte kilobytes kilo ohms mA milliamps milliamperes Mbyte megabytes MHz megahertz ms milliseconds mW milliwatts ns nanoseconds pF picofarads W watts V volts uA microamps microamperes uF microfarads us microseconds uW microwatts 1 3 RELATED DOCUMENTS The following documents contain additional infor
371. require ments in terms of state times rather than in specific units of time Universal asynchronous receiver and transmitter A part of the serial I O port Watchdog timer an internal timer that resets the device if the software fails to operate properly A 16 bit unit of data In memory a word comprises two contiguous bytes The result of interpreting an address whose hexadecimal expression uses more bits than the number of available address lines Wraparound ignores the upper address bits and directs access to the value expressed by the lower bits intel Index intel 0datal6 3 1 16 3 definition 3 datal6 3 short 3 8XC251SA SB SP SQ 1 1 B stepping 2 1 block diagram 2 2 on chip peripherals 2 3 8XC251SB 2 1 A stepping 2 1 8XC251Sx 1 1 8XCS5IFX 2 1 A 15 8 7 1 description 13 2 16 description 13 2 AC flag 5 18 5 19 ACALL instruction 5 15 A 24 A 26 ACC 3 13 3 17 3 18 C 4 Accumulator 3 15 in register file 3 13 See also ACC AD7 0 7 1 description 13 2 ADD instruction 5 8 A 14 ADDC instruction 5 8 A 14 addrll 5 13 A 3 addr16 5 13 A 3 addr24 5 13 A 3 Address spaces See Memory space SFRs Register file External memory Compatibility Addresses internal vs external 4 12 Addressing modes 3 8 5 4 See also Data instructions Bit instructions Control instructions AJMP instruction 5 15 A 24 ALE caution 11 7 description 13 2
372. rnal Memory vedi eee dede ree 2 9 2 4 9 Configuration Bytes oen en ehe PE eme edema etta 2 9 CHAPTER 3 ADDRESS SPACES 3 1 ADDRESS SPACES FOR MCS 251 3 1 3 1 1 Compatibility with the MCSQG 51 Architecture 3 2 3 2 8XC251SA SB SP SQ MEMORY SPACQGE essere 3 5 3 2 1 On chip General purpose Data RAM 20 42244 0 00 00 3 8 3 2 2 On chip Code Memory 83 2515 SB SP SQ 87C251SA SB SP SQ 3 8 3 2 2 1 Accessing On chip Code Memory in Region 00 3 9 intel 3 2 3 External Memory eet eee epe eet Ld egeo Tene e duree 3 10 3 2 4 Memory Space for the A stepping of the 8XC251SB 3 10 3 3 8XC251SA SB SP SQ REGISTER 3 10 3 3 1 Byte Word and Dword Registers sssssssssssssseseneneneerenenneen 3 13 3 3 2 Dedicated Registers 3 13 3 3 2 1 Accumulator and B Register 3 13 3 3 2 2 Extended Data Pointer 3 15 3 3 23 Extended Stack Pointer SPX 0 3 15 3 4 SPECIAL FUNCTION REGISTERS 5 5 3 16 CHAPTER 4 DEVICE CONFIGURATION 4 1 CONFIGURATION OVERVIEW TE 4 1 4 2 DEVICE CONFIGURATION B STEPPING
373. rnal memory via region 01 4 6 3 3 Configuration Bit XALEZ Clearing XALE UCONFIGO 4 and CONFIGO 4 extends the time ALE is asserted from To to osc This accommodates an address latch that is too slow for the normal ALE signal tending ALE on page 13 10 shows an external bus cycle with ALE extended 4 16 intel DEVICE CONFIGURATION Table 4 4 RD WR PSEN External Wait States B Stepping A Stepping Regions WSA1 WSAO Regions WSA 00 02 03 0 0 3 Wait States 00 FE FF FD FE FF 0 1 2 Wait States 1 0 1 Wait State 0 1 Wait State 1 1 0 Wait States 1 0 Wait States Region 01 WSB1 WSBO Region 01 WSB 0 0 3 Wait States 0 1 2 Wait States 1 0 1 Wait State 0 1 Wait State 1 1 0 Wait States 1 0 Wait States 47 OPCODE CONFIGURATIONS SRC The SRC configuration bit UCONFIGO 0 and CONFIGO 0 selects the source mode or binary mode opcode arrangement Opcodes for the MCS 251 architecture are listed in Table A 6 and Ta ble A 7 in Appendix A Note that in Table A 6 every opcode 00H FFH is used for an instruc tion except ASH ESC which provides an alternative set of opcodes for columns 6H through FH The SRC bit selects which set of opcodes is assigned to columns 6H through FH and which set is the alternative Binary mode and source mode refer to two ways of assigning opcodes to the instruction set for the MCS 251 architecture One of these modes must be selec
374. ro see Vo in the 8XC251Sx data sheet However the port 0 pins require ex ternal pullups to drive external gate inputs See the latest revision of the 8 2515 datasheet for complete electrical design information External circuits must be designed to limit current re quirements to these conditions 7 8 EXTERNAL MEMORY ACCESS The external bus structure is different for page mode and nonpage mode In nonpage mode used by MCS 51 microcontrollers port 2 outputs the upper address byte the lower address byte and the data are multiplexed on port 0 In page mode the upper address byte and the data are multi plexed on port 2 while port 0 outputs the lower address byte The 8XC251Sx CPU writes FFH to the PO register for all external memory bus cycles This over writes previous information in PO In contrast the P2 register is unmodified for external bus cy cles When address bits or data bits are not on the port 2 pins the bit values in P2 appear on the port 2 pins In nonpage mode port 0 uses a strong internal pullup FET to output ones or a strong internal pull down FET to output zeros for the lower address byte and the data Port 0 is in a high impedance state for data input In page mode port O uses a strong internal pullup FET to output ones or a strong internal pulldown FET to output zeros for the lower address byte or a strong internal pull down FET to output zeros for the upper address byte In nonpage mode port 2 uses a st
375. rol e g the jump address bitaddressing The instruction contains the bit address More detailed descriptions of the addressing modes are given in Data Addressing Modes on page 5 4 Bit Addressing on page 5 11 and Addressing Modes for Control Instructions on page 5 13 5 3 DATA INSTRUCTIONS Data instructions consist of arithmetic logical and data transfer instructions for 8 bit 16 bit and 32 bit data This section describes the data addressing modes and the set of data instructions 5 3 1 Data Addressing Modes This section describes the data addressing modes which are summarized in two tables Table 5 4 for the instructions that are native to the MCS 51 architecture and Table 5 4 for the new data in structions in the MCS 251 architecture NOTE References to registers RO R7 WRO WR6 DRO and DR2 always refer to the register bank that is currently selected by the PSW and PSWI registers see Program Status Words on page 5 16 Registers in all banks active and inactive can be accessed as memory locations in the range 00H 1FH 5 4 intel PROGRAMMING NOTE Instructions from the MCS 51 architecture access external memory through the region of memory specified by byte DPXL in the extended data pointer register DPX DR56 Following reset DPXL contains 01H which maps the external memory to region 01 You can specify a different region by writing to DR56 or the DPXL SFR See Dedicated Registers on pag
376. roller family This manual is intended for use by both software and hardware designers familiar with the principles of microcontrollers 11 MANUAL CONTENTS This manual contains 14 chapters and 3 appendixes This chapter Chapter 1 provides an over view of the manual This section summarizes the contents of the remaining chapters and appen dixes The remainder of this chapter describes notational conventions and terminology used throughout the manual and provides references to related documentation Chapter 2 Architectural Overview provides an overview of device hardware It covers core functions pipelined CPU clock and reset unit and on chip memory and on chip peripher als timer counters watchdog timer programmable counter array and serial I O port Chapter 3 Address Spaces describes the three address spaces of the MCS 251 microcon troller memory address space special function register SFR space and the register file It also provides a map of the SFR space showing the location of the SFRs and their reset values and ex plains the mapping of the address spaces of the MCS 51 architecture into the address spaces of the MCS 251 architecture Chapter 4 Device Configuration describes microcontroller features that are configured at device reset including the external memory interface the number of external address bits the number of wait states memory regions for asserting RD WR and PSEN page mode bi
377. rong internal pullup FET to output ones or a strong internal pull down FET to output zeros for the upper address byte In page mode port 2 uses a strong internal pullup FET to output ones or a strong internal pulldown FET to output zeros for the upper address byte and data Port 2 is in a high impedance state for data input NOTE In external bus mode port 0 outputs do not require external pullups There are two types of external memory accesses external program memory and external data memory see Chapter 13 External Memory Interface External program memories utilize sig nal PSEN as a read strobe MCS 51 microcontrollers use RD read or WR write to strobe memory for data accesses Depending on its RD1 0 configuration bits the 8XC251Sx uses PSEN or RD for data reads Configuration Bits RD1 0 on page 4 11 7 7 INPUT OUTPUT PORTS intel During instruction fetches external program memory can transfer instructions with 16 bit ad dresses for binary compatible code or with the external bus configured for extended memory ad dressing 17 bit or 18 bit External data memory transfers use an 8 16 17 or 18 bit address bus depending on the in struction and the configuration of the external bus Table 7 2 lists the instructions that can be used for the these bus widths Table 7 2 Instructions for External Data Moves Bus Width Instructions 8 MOVX Ri MOV Rm MOV dir8 16 MOVX DPTR MO
378. rt operating mode Refer to the SM1 bit for the mode selections 6 SM1 Serial Port Mode Bit 1 Software writes to bits SM1 and SMO above to select the serial port operating mode SMO SM1 Mode Description Baud Rate 0 0 0 Shift register Fosc 12 0 1 1 8 bit UART Variable 1 0 2 9 bit UART 321 or Fog 64 1 1 3 9 bit UART Variable Select by programming the SMOD bit in the PCON register see Baud Rates on page 10 10 5 SM2 Serial Port Mode Bit 2 Software writes to bit SM2 to enable and disable the multiprocessor communication and automatic address recognition features This allows the serial port to differentiate between data and command frames and to recognize slave and broadcast addresses 4 REN Receiver Enable Bit To enable reception set this bit To enable transmission clear this bit 3 TB8 Transmit Bit 8 In modes 2 and 3 software writes the ninth data bit to be transmitted to TB8 Not used in modes 0 and 1 2 RB8 Receiver Bit 8 Mode 0 Not used Mode 1 SM2 clear Set or cleared by hardware to reflect the stop bit received Modes 2 and 3 SM2 set Set or cleared by hardware to reflect the ninth data bit received Figure 10 2 SCON Serial Port Control Register 10 3 SERIAL I O PORT intel 1 Tl Transmit Interrupt Flag Bit Set by the transmitter after the last data bit is transmitted Cleared by software 0 RI Receive Interrupt Flag Bit Set by the receiver after the last data b
379. rupts 8 1 overview 8 1 8 3 registers 8 2 SFRs 3 19 signal descriptions 8 3 See also Timer 0 Timer 1 Timer 2 TMOD 3 17 3 19 8 1 8 2 8 4 8 6 8 7 10 11 C 35 Tosc 2 6 See also Oscillator TRAP instruction 5 16 6 3 6 5 6 15 A 25 TXD 7 1 10 1 mode 0 10 4 modes 1 2 3 10 6 Index 8 U UART 10 1 UCONFIGO 4 2 UCONFIGI 4 2 UD flag 5 18 V Vcc 11 2 during reset 11 5 power off flag 12 1 power on reset 11 7 powerdown mode 12 5 12 6 See also Power supply Vcc2 11 2 Vpp 14 1 requirements 14 3 Vssl 11 2 Vss2 11 2 W Wait state 4 16 5 1 A 1 A 11 configuration bits 4 3 4 16 extended ALE 4 16 RD WR PSEN 4 16 4 17 Watchdog timer hardware 8 16 8 18 enabling disabling 8 16 in idle mode 8 18 in powerdown mode 8 18 initiating reset 11 6 overflow 8 16 SFR WDTRST 3 19 WDTRST 3 17 3 19 8 2 8 16 C 39 WR 7 1 described 13 2 X bit 4 16 XCH instruction 5 10 A 22 XCHD instruction 5 10 A 22 XRL instruction 5 9 XTALI XTAL2 11 3 capacitance loading 11 5 Z Zflag 5 9 5 19
380. ry Mode Source Mode 1 2 2 3 1001 011i Binary Mode Encoding Source Mode A5 Encoding SUBB A lt A CY Ri Binary Mode Source Mode 1 2 1 2 1001 irrr Binary Mode Encoding Source Mode A5 Encoding SUBB lt A CY Rn intel SWAP Function Description Flags Example Bytes States Encoding Hex Code in Operation TRAP Function Description Flags Example INSTRUCTION SET REFERENCE Swap nibbles within the accumulator Interchanges the low and high nibbles 4 bit fields of the accumulator bits 3 0 and bits 7 4 This operation can also be thought of as a 4 bit rotate instruction CY AC OV N 2 The accumulator contains 0C5H 11000101B After executing the instruction SWAPA the accumulator contains 5CH 01011100B Binary Mode Source Mode 1 1 2 2 1100 0100 Binary Mode Encoding Source Mode Encoding SWAP A 3 0 2 lt A 7 4 Causes interrupt call Causes an interrupt call that is vectored through location OFF007BH The operation of this instruction is not affected by the state of the interrupt enable flag in PSWO and PSW1 Interrupt calls can not occur immediately following this instruction This instruction is intended for use by Intel provided development tools These tools do not support user application of this instruction CY
381. s is the largest possible external memory space Regions 00 and FC each having A17 16 00 map into the same 64 Kbyte region in external memory This duplication also occurs for regions 01 and FD 02 and and 03 and FF See Example 1 RD1 0 00 18 bit Bus External Flash and RAM on page 13 13 4 6 2 2 RD1 0 01 17 External Address Bits The selection RD1 0 01 provides 17 external address bits A15 0 ports PO and P2 and A16 from P3 7 RD A16 Bit A16 can select two 64 Kbyte regions of external memory for a total of 128 Kbytes bottom half of Figure 4 7 on page 4 13 Regions 00 02 FC and FE each hav ing A16 0 map into the same 64 Kbyte region in external memory This duplication also occurs for regions 01 03 FD and FF 4 12 intel DEVICE CONFIGURATION RD1 0 00 18 external address bits Internal Memory with External P2 A16 A17 Read Write Signals Memory Notes 1 Maximum external 256 Kbytes memory PSEN 1746 2 Single read signal WR 11 03 FF 10 02 FE 0 1 01 FD PSEN 00 00 FC WR RD1 0 01 17 external address bits PO P2 A16 Internal Memory with External ore Read Write Signals Memory Note Single read signal PSEN 128 Kbytes WR 16 1 01 03 FD FF 0 00 02 FC FE PSEN WR A4218 01 Figure 4 7 Internal External Memory Mapping RD1 0 00 and 01 DEVICE CONFIGURATION intel RD1 0 10 AIO
382. s at T2EX if EXEN2 1 The CP RL2 bit is ignored and timer 2 forced to auto reload on timer 2 overflow if RCLK 1 or TCLK 1 Figure 8 12 T2CON Timer 2 Control Register TIMER COUNTERS AND WATCHDOG TIMER intel 8 7 2 Using the WDT To use the WDT to recover from software malfunctions the user program should control the WDT as follows 1 Following device reset write the two byte sequence to the WDTRST register to enable the WDT The WDT begins counting from 0 2 Repeatedly for the duration of program execution write the two byte sequence 1EH E1H to the WDTRST register to clear and enable the WDT before it overflows The WDT starts over at If the WDT overflows it initiates a device reset see Reset on page 11 5 Device reset clears the WDT and disables it 8 7 3 WDT During Idle Mode Operation of the WDT during the power reduction modes deserves special attention The WDT continues to count while the microcontroller is in idle mode This means the user must service the WDT during idle One approach is to use a peripheral timer to generate an interrupt request when the timer overflows The interrupt service routine then clears the WDT reloads the peripheral timer for the next service period and puts the microcontroller back into idle 8 7 4 WDT During PowerDown The powerdown mode stops all phase clocks This causes the WDT to stop counting and to hold its count The WDT resume
383. s counting from where it left off if the powerdown mode is terminated by INTO INTI To ensure that the WDT does not overflow shortly after exiting the powerdown mode clear the WDT just before entering powerdown The WDT is cleared and disabled if the powerdown mode is terminated by a reset intel Programmable Counter Array intel CHAPTER 9 PROGRAMMABLE COUNTER ARRAY This chapter describes the programmable counter array PCA an on chip peripheral of the 8XC251Sx that performs a variety of timing and counting operations including pulse width mod ulation PWM The PCA provides the capability for a software watchdog timer WDT 9 1 PCA DESCRIPTION The programmable counter array PCA consists of a 16 bit timer counter Pand five 16 bit com pare capture modules The timer counter serves as a common time base and event counter for the compare capture modules distributing the current count to the modules by means of a 16 bit bus A special function register SFR pair CH CL maintains the count in the timer counter while five SFR pairs CCAPxH CCAPXxL store values for the modules see Figure 9 1 Additional SFRs provide control and mode select functions as follows The PCA timer counter mode register CMOD and the PCA timer counter control register CCON control the operation of the timer counter See Figures 9 7 and 9 8 beginning on page 9 13 e Five PCA module mode registers CCAPMx specify the operating modes of the comp
384. since the five modules share a common time base Thus in most applications the first option is the best one Compare Capture PCA Timer Counter Module CH CL CCAP4H CCAP4L 8 Bits 8 Bits 8 Bits 8 Bits Count PCA WDT Reset CCAPM4 Mode Register Reset Write to rd X Don t Care Write to CCAP4H A4165 01 Figure 9 4 PCA Watchdog Timer Mode 9 10 intel PROGRAMMABLE COUNTER ARRAY 9 3 6 Pulse Width Modulation Mode The five PCA comparator capture modules can be independently programmed to function as pulse width modulators Figure 9 5 The modulated output which has a pulse width resolution of eight bits is available at the CEXx pin The PWM output can be used to convert digital data to an analog signal with simple external circuitry In this mode the value in the low byte of the PCA timer counter CL is continuously compared with the value in the low byte of compare capture register CCAPxL When CL lt CCAPAL the output waveform Figure 9 6 is low When a match occurs CL CCAPxL the output wave form goes high and remains high until CL rolls over from FFH to 00H ending the period At roll over the output returns to a low the value in CCAPxH is loaded into CCAPXL and a new period begins CCAPxH CL rollover from FFH to 00H loads CCAPXH contents into CCAPxL X Don t Care x 0 1 2 3 4 8 Bit Comparator 1
385. so Ports 0 3 Idle mode 2 4 12 1 12 4 12 5 entering 12 4 exiting 11 6 12 5 external bus 13 3 IE 6 3 6 5 IEO 3 17 3 18 6 6 6 14 10 11 C 14 Immediate addressing 5 4 INC instruction 5 8 A 16 Indirect addressing 5 4 in control instructions 5 13 in data instructions 5 6 Input pins level sensitive B 2 sampled B 2 Instruction set MCS 251 architecture 5 1 MCS 51 architecture 5 1 Instructions arithmetic 5 8 bit 5 11 data 5 4 data transfer 5 10 logical 5 9 instructions INT1 0 6 1 7 1 8 1 8 3 pulse width measurements 8 10 Interrupt request 6 1 cleared by hardware 6 4 Interrupt service routine exiting idle mode 12 5 Index 3 exiting powerdown mode 12 6 Interrupts 6 1 6 15 blocking conditions 6 14 detection 6 3 edge triggered 6 4 enable disable 6 5 exiting idle mode 12 5 exiting powerdown mode 12 6 external 6 3 6 11 global enable 6 5 instruction completion time 6 10 latency 6 9 6 13 level triggered 6 4 PCA 6 5 polling 6 9 6 10 priority 6 1 6 3 6 4 6 6 priority within level 6 7 processing 6 9 6 15 request See Interrupt request response time 6 9 6 10 sampling 6 3 6 10 serial port 6 5 service routine ISR 6 4 6 9 6 14 6 15 sources 6 3 timer counters 6 4 vector cycle 6 14 vectors 3 3 6 4 INTR bit and RETI instruction 4 20 5 16 IPHO 3 17 3 18 6 3 6 8 6 14 C 15 bit definitions 6 7 IPLO 3 17 3 18 6 3 6 8 6 14 C 16 bit def
386. sserts the request one state samples and one state requests the context switch If at that point the same instruction conditions exist one additional state time is needed to complete the 10 state instruction prior to the context switch see Figure 6 7 on page 6 12 The total response time in this case is four state times The programmer must evaluate all pertinent conditions for accurate predictability INTERRUPT SYSTEM intel Response Time 4 OSC State Time INTO WH Sample INTO Request Ten State parucion Peo A4154 02 Figure 6 7 Response Time Example 2 6 7 2 2 Computation of Worst case Latency With Variables Worst case latency calculations assume that the longest 8 2515 instruction used in the pro gram must fully execute prior to a context switch The instruction execution time is reduced by one state with the assumption the instruction state overlaps the request state therefore 16 bit DIV is 21 state times 1 20 states for latency calculations The calculations add fixed and vari able interrupt times see Table 6 6 on page 6 13 to this instruction time to predict latency The worst case latency both fixed and variable times included is expressed by a pseudo formula FIXED TIME VARIABLES LONGEST INSTRUCTION MAXIMUM LATENCY PREDICTION 6 12 intel INTERRUPT SYSTEM Table 6 6 Interrupt Latency Variables INTOZ External Pa
387. sublevel to find the hypertext manuals and data sheets 7 Enterthe file number to tag the files you wish to download The BBS displays the approx imate download time for tagged files intel Architectural Overview intel CHAPTER 2 ARCHITECTURAL OVERVIEW The 8XC251Sx is the first member of the MCS 251 microcontroller family This family of 8 bit microcontrollers is a high performance upgrade of the widely used MCS 519 microcontrollers It extends features and performance while maintaining binary code compatibility and pin com patibility with the 8XC51FX so the impact on existing hardware and software is minimal Typi cal control applications for the 8XC251Sx include copiers scanners CD ROMs and tape drives Itis also well suited for communications applications such as phone terminals business feature phones and phone switching and transmission systems This manual covers both the B stepping version which is available as memory options 8XC251SA SB SP SQ and the A stepping version which is available as option 8XC251SB Memory options are listed in Table 2 1 on page 2 3 All MCS 251 microcontrollers share a set of common features e 24 bit linear addressing and up to 16 Mbytes of memory aregister based CPU with registers accessible as bytes words and double words apage mode for accelerating external instruction fetches aninstruction pipeline anenriched instruction set including 16 bit arithmetic and logic instr
388. t CR in the CCON register to start the PCA timer counter Duty CCAPXL Cycle Output Waveform 255 0 4 0 230 10 0 1 128 50 0 1 25 90 ll 0 0 100 0 4161 01 Figure 9 6 PWM Variable Duty Cycle 9 12 intel PROGRAMMABLE COUNTER ARRAY CMOD Address S D9H Reset State 00XX X000B 7 0 CIDL WDTE CPS1 CPSO ECF Bit Bit Number Mnemonic Function 7 CIDL PCA Timer Counter Idle Control CIDL 1 disables the PCA timer counter during idle mode CIDL 0 allows the PCA timer counter to run during idle mode 6 WDTE Watchdog Timer Enable WDTE 1 enables the watchdog timer output on PCA module 4 WDTE 0 disables the PCA watchdog timer output 5 3 Reserved The values read from these bits are indeterminate Do not write a 1 to these bits 2 1 CPS1 0 PCA Timer Counter Input Select CPS1 CPSO 0 Fosc 12 1 4 0 Timer 0 overflow 1 External clock at ECI pin maximum rate Fog 8 0 ECF PCA Timer Counter Interrupt Enable 1 enables the CF bit in the CCON register to generate an interrupt request Figure 9 7 CMOD PCA Timer Counter Mode Register PROGRAMMABLE COUNTER ARRAY intel CCON Address S D8H Reset State 00X0 0000B 7 0 CF CR CCF4 CCF3 CCF2 CCF1 CCFO Bit
389. t addr rel addr A 74 intel Hex Code in Operation JNC rel Function Description Flags Example Bytes States Encoding Hex Code in Operation JNE rel Function Description INSTRUCTION SET REFERENCE Binary Mode A5 Encoding Source Mode Encoding JNB lt PC 3 IF bit 0 THEN PC lt PC rel Jump if carry not set If the CY flag is clear branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice to point to the next instruction The CY flag is not modified CY AC OV N 2 The CY flag is set The instruction sequence JNC LABEL1 CPL CY JNC LABEL2 clears the CY flag and causes program execution to continue at label LABEL2 Binary Mode Source Mode Not Taken Taken Not Taken Taken 2 2 2 2 1 4 1 4 0101 0000 rel addr Binary Mode Encoding Source Mode Encoding JNC lt PC 2 IF CY 0 THEN PO rel Jump if not equal If the Z flag is clear branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twi
390. t is addressed directly or indirectly These instructions affect the Z and N flags In addition to the CLR clear CPL complement SWAP swap and four rotate instructions that operate on the accumulator MCS 251 microcontrollers have three shift commands for byte and Word registers SLL Shift Left Logical shifts the register one bit left and replaces the LSB with 0 SRL Shift Right Logical shifts the register one bit right and replaces the MSB with 0 SRA Shift Right Arithmetic shifts the register one bit right the MSB is unchanged 5 9 PROGRAMMING intel 5 3 4 Data Transfer Instructions Data transfer instructions copy data from one register or memory location to another These in structions include the move instructions Table A 24 on page A 19 and the exchange push and pop instructions Table A 24 on page A 19 Instructions that move only a single bit are listed with the other bit instructions in Table A 26 on page A 23 MOV Move is the most versatile instruction and its addressing modes are expanded in the MCS 251 architecture MOV can transfer a byte word or dword between any two registers or between a register and any location in the address space The MOVX Move External instruction moves a byte from external memory to the accumulator or from the accumulator to memory The external memory is in the region specified by DPXL whose reset value is 01H See Dedicated Registers on page 3 13 The MOVC
391. t lets you order technical documents by phone for immediate delivery to your fax machine The BBS is a centralized computer bulletin board system that provides updated application specific information about Intel products Intel offers a variety of information through the World Wide Web URL http www intel com Select Embedded Design Products from the Intel home page 1 4 4 Howto Use Intel s FaxBack Service Think of the FaxBack service as a library of technical documents that you can access with your phone Just dial the telephone number see page 1 7 and respond to the system prompts After you select a document the system sends a copy to your fax machine GUIDE TO THIS MANUAL intel Each document is assigned an order number and is listed in a subject catalog First time users should order the appropriate subject catalogs to get a complete listing of document order num bers The following catalogs and information packets are available 1 Microcontroller Flash and iPLD catalog Development Tools Handbook System catalog DVI and multimedia catalog BBS catalog Microprocessor and peripheral catalog Quality and reliability catalog 9o ddp cQ uA deo 59 qp Technical questionnaire 1 4 2 How to Use Intel s Application BBS The Application Bulletin Board System BBS provides centralized access to information soft ware drivers firmware upgrades and revised software Any user with a modem and computer can access the BBS
392. t pin to power or ground Any member of the set consisting of the positive and negative whole numbers and zero The 24 bit address that the device generates See also external address The module responsible for handling interrupts that are to be serviced by user written interrupt service routines The delay between an interrupt request and the time when the first instruction in the interrupt service routine begins execution Glossary 3 GLOSSARY interrupt response time interrupt service routine ISR level triggered LSB maskable interrupt MSB multiplexed bus n channel FET n type material nonmaskable interrupt npn transistor OTPROM p channel FET p type material PC Glossary 4 intel The time delay between an interrupt request and the resulting break in the current instruction stream The software routine that services an interrupt The mode in which a device or component recognizes a high level logic one or a low level logic zero of an input signal as the assertion of that signal See also edge triggered Least significant bit of a byte or least significant byte of a word An interrupt that can be disabled masked by its individual mask bit in an interrupt enable register 8XC251SB interrupts except the software trap TRAP are maskable Most significant bit of a byte or most significant byte of a word A bus on which the data is time multiplexed with some of
393. t register to 16 bit register with zero extension Moves the contents of an 8 bit register to the low byte of a 16 bit register The upper byte of the 16 bit register is filled with zeros CY AC OV N 2 Eight bit register Rm contains 055H 01010101B 16 bit register WRj contains OFFFFH 11111111 11111111B The instruction MOVZ WRj Rm moves the contents of register Rm 01010101B to register WRj At the end of the operation WRj contains 00000000 01010101B Binary Mode Source Mode 3 2 2 1 0000 1010 tttt ssss Binary Mode A5 Encoding Source Mode Encoding MOVZ WRj 7 0 Rm 7 0 WRj 15 8 lt 0 A 105 INSTRUCTION SET REFERENCE intel MUL dest src Function Description Flags Example MUL Rmd Rms Bytes States Encoding Hex Code in Operation A 106 Multiply Multiplies the unsigned integer in the source register with the unsigned integer in the destination register Only register addressing is allowed For 8 bit operands the result is 16 bits The most significant byte of the result is stored in the low byte of the word where the destination register resides The least significant byte is stored in the following byte register The OV flag is set if the product is greater than 255 OFFH otherwise it is cleared For 16 bit operands the result is 32 bits The most significant word is stored in the low word of the
394. te block of memory as the address of the next instruction ECALL Extended Call pushes the 24 bits of the next instruction address onto the stack and then changes the 24 bits of the PC to the 24 bit address specified by the instruction The call is to an address anywhere in the 16 Mbyte memory space RET Return pops the top two bytes from the stack to return to the instruction following a sub routine call The return address must be in the same 64 Kbyte region ERET Extended Return pops the top three bytes from the stack to return to the address follow ing a subroutine call The return address can be anywhere in the 16 Mbyte address space 5 15 PROGRAMMING intel RETI Return from Interrupt provides a return from an interrupt service routine The operation of RETI depends on the INTR bit in the UCONFIGI or CONFIGI configuration byte For INTR an interrupt pushes the two lower bytes of the PC onto the stack in the following order PC 7 0 PC 15 8 The RETI instruction pops these two bytes and uses them as the 16 bit return address in region FF RETI also restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed For INTR 1 an interrupt pushes the three PC bytes and PSWI onto the stack in the following order PSW1 PC 23 16 PC 7 0 PC 15 8 The RETI instruction pops these four bytes and then returns to the specified 24 bit address which can be anywhere in the 16
395. te mode according to Table 14 1 2 Inputthe 16 bit address on ports P1 and P3 3 Wait for the data on port P2 to become valid Tayoy 48 clock cycles Figure 14 4 then compare the data with the expected value 4 If the procedure is program immediate verify return to step 8 of Programming Algorithm on page 14 6 to program the next byte 5 Repeat steps 1 through 5 until all memory locations are verified 14 6 PROGRAMMABLE FUNCTIONS This section discusses factors related to programming and verifying the various nonvolatile mem ory functions 14 6 1 On chip Code Memory On chip code memory is located in the top region of the memory space starting at address 0000 At reset the 87C251Sx and 83C251Sx devices vector to this address See Chapter 3 for detailed information on the 8XC251Sx memory space To enter user program code and data in the on chip code memory perform the procedure de scribed in Programming Algorithm on page 14 6 using the program on chip code memory mode Table 14 1 To verify that the on chip code memory is correctly programmed perform the procedure de scribed in Verify Algorithm on page 14 7 using the verify on chip code memory mode Table 14 1 14 7 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY intel 14 6 2 Configuration Bytes The B stepping 87C251Sx and 83C251Sx store configuration information in an eight byte con figuration array at FR FFF8H FF FFFFH UCONFIGO FF FFF8H an
396. ted by an interrupt the interrupt service routine may examine GF1 GFO Reset the chip See Reset on page 11 5 A logic high on the RST pin clears the IDL bit in the PCON register directly and asynchronously This restores the clocks to the CPU Program execution momentarily resumes with the instruction immediately following the instruction that activated the idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control Reset initializes the 8XC251Sx and vectors the CPU to address FF 0000H NOTE During the time that execution resumes the internal RAM cannot be accessed however it is possible for the port pins to be accessed To avoid unexpected outputs at the port pins the instruction immediately following the instruction that activated idle mode should not write to a port pin or to the external RAM 12 4 POWERDOWN MODE The powerdown mode places the 8XC251Sx in a very low power state Powerdown mode stops the oscillator and freezes all clocks at known states Figure 12 2 The CPU status prior to enter ing powerdown mode is preserved i e the program counter program status word register and register file retain their data for the duration of powerdown mode In addition the SFRs and RAM contents are preserved The status of the port pins depends on the location of the program mem e Internal program memory the ALE and PSEN pins are pulled low and the ports 0 1 2 and 3
397. ted when the chip is configured De pending on the application binary mode or source mode may produce more efficient code This section describes the binary and source modes and provides some guidelines for selecting the mode for your application The MCS 251 architecture has two types of instructions instructions that originate in the MCS 51 architecture instructions that are unique to the MCS 251 architecture Figure 4 9 shows the opcode map for binary mode Area I columns 1 through 5 in Table A 6 and area II columns 6 through F make up the opcode map for the instructions that originate in the MCS 51 architecture Area III in Figure 4 9 represents the opcode map for the instructions that are unique to the MCS 251 architecture Table A 7 Some of these opcodes are reserved for future instructions Note that the opcode values for areas II and III are identical 06H FFH distinguish between the two areas in binary mode the opcodes in area III are given the prefix ASH The area III opcodes are thus AS06H ASFFH 4 17 DEVICE CONFIGURATION intel Figure 4 10 shows the opcode map for source mode Areas II and III have switched places com pare with Figure 4 9 In source mode opcodes for instructions in area II require the A5F escape prefix while opcodes for instructions in area III MCS 251 architecture do not To illustrate the difference between the binary mode and source mode opcodes Table 4 5 shows the opcode assign
398. tes 1056 Bytes External RAM 1056 Bytes On chip RAM A4168 02 13 16 Figure 13 15 Memory Space for Example 2 intel EXTERNAL MEMORY INTERFACE 13 6 3 Example 3 RD1 0 01 17 bit Bus External RAM In this example an 87C251SB 83C251SB operates in nonpage mode with a 17 bit external ad dress bus interfaced to 128 Kbytes of external RAM Figure 13 16 The 87C251SB 83C251SB A stepping or B stepping is configured so that RD functions as A16 and PSEN is asserted for all reads Figure 13 17 shows how the external RAM is addressed in the internal memory space For an A stepping device regions 02 03 FC and FD are absent RAM 83025158 128 Kbytes EA CE D7 0 OE WE A4147 02 Figure 13 16 Bus Diagram for Example 3 87C251SB 83C251SB in Nonpage Mode 13 17 EXTERNAL MEMORY INTERFACE FF FE FD FC 03 02 01 00 00 0000H Memory Address Space 512 Kbytes FFFFH 0000H 3FFFH FFFFH 0420H 16 Kbytes On chip ROM OTPROM EPROM 128 Kbytes 1056 Bytes External RAM 1056 Bytes On chip RAM A4169 02 13 18 Figure 13 17 Memory Space for Example 3 intel EXTERNAL MEMORY INTERFACE 13 6 4 Example 4 RD1 0 10 16 bit Bus External RAM In this example an 87C251SB 83C251SB A stepping or B stepping operates in nonpage with a 16 bit external address bus interfaced to 64 Kbytes of RAM Figure 13 18
399. the address bits A field effect transistor with an n type conducting path channel Semiconductor material with introduced impurities doping causing it to have an excess of negatively charged carriers An interrupt that cannot be disabled masked The software trap TRAP is the 8XC25ISB s only nonmaskable interrupt A transistor consisting of one part p type material and two parts n type material One time programmable read only memory a version of EPROM A field effect transistor with a p type conducting path Semiconductor material with introduced impurities doping causing it to have an excess of positively charged carriers Program counter intel program memory powerdown mode PWM rel reserved bits set SFR sign extension sink current source code compatibility source current source mode SP SPX GLOSSARY A part of memory where instructions can be stored for fetching and execution The power conservation mode that freezes both the core clocks and the peripheral clocks Pulse width modulated outputs A signed two s complement 8 bit relative destination address The destination is 128 to 127 bytes relative to the first byte of the next instruction Register bits that are not used in this device but may be used in future implementations Avoid any software dependence on these bits In the 8XC251SB the value read from a reserved bit is indeterminate do not write a
400. the dword where the destination register resides The least significant word is stored in the following word register In this operation the OV flag is set if the product is greater than OFFFFH otherwise it is cleared The CY flag is always cleared The N flag is set when the MSB of the result is set The Z flag is set when the result is zero CY AC OV 0 4 Register R1 contains 80 or 10010000B and register RO contains 160 0AO0H or 10010000B After executing the instruction MUL R1 RO which gives the product 12 800 3200H register RO contains 32H 00110010B register R1 contains the OV flag is set and the CY flag is clear Binary Mode Source Mode 3 2 6 5 1010 1100 5555 5555 Binary Mode A5 Encoding Source Mode Encoding MUL 8 bit operands if dest md 0 2 4 14 lt high byte of the Rmd X Rms Rmd 1 lt low byte of the Rmd X Rms if dest md 1 3 5 15 Rmd 1 lt high byte of the Rmd X Rms Rmd lt low byte of the Rmd X Rms intel INSTRUCTION SET REFERENCE MUL WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 12 11 Encoding 1010 1101 tttt tttt Hex Code in Binary Mode A5 Encoding Operation MUL AB Function Description Flags Example Bytes States Encoding Hex Code in Operation Source Mode Encoding MUL 16 bit operands if dest jd
401. the flag before the instruction executes influences the decision to jump or not jump lt addr11 gt Function Absolute call Description Unconditionally calls a subroutine at the specified address The instruction increments the 3 byte PC twice to obtain the address of the following instruction then pushes bytes 0 and 1 of the result onto the stack byte 0 first and increments the stack pointer twice The destination address is obtained by successively concatenating bits 15 11 of the incremented PC opcode bits 7 5 and the second byte of the instruction The subroutine called must therefore start within the same 2 Kbyte page of the program memory as the first byte of the instruction following ACALL Flags CY AC OV N 2 The stack pointer SP contains 07H and the label SUBRTN is at program memory location 0345H After executing the instruction ACALL SUBRTN at location 0123H SP contains 09H on chip RAM locations 08H and 09H contain 01H and 25H respectively and the PC contains 0345H A 26 intel Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Source Mode 2 2 9 9 a10 a9 a8 1 0001 a7 a6 a5 a4 a3 a2 a1 a0 Binary Mode Encoding Source Mode Encoding ACALL PC 2 SP 1 SP lt 7 0 SP 1 15 8 10 0 lt ADD d
402. the memory space are implemented as external memory Figure 3 5 on page 3 7 For discussions of external mem ory see Configuring the External Memory Interface on page 4 11 and Chapter 13 External Memory Interface 3 2 4 Memory Space for the A stepping of the 8XC251SB The memory space for the A stepping of the 8XC251SB is the same as the memory space for the B stepping of the 8XC251SB with the following exceptions The useable memory space for the A stepping comprises regions 00 01 FE and FF Regions 02 FD are reserved In the A stepping the configuration bytes are not in the memory space i e they are not in the user s code data space Instead the configuration bytes are in a separate address space see Device Configuration A stepping Compatible on page 4 5 Accordingly addresses FF FFFSH FF FFFFH are not restricted to storing the configura tion array 3 8 8XC251SA SB SP SQ REGISTER FILE The 8XC251Sx register file consists of 40 locations 0 31 and 56 63 as shown in Figure 3 6 These locations are accessible as bytes words and dwords as described in Byte Word and Dword Registers on page 3 13 Several locations are dedicated to special registers see Dedi cated Registers on page 3 13 the others are general purpose registers intel ADDRESS SPACES Byte Registers Note R10 B R11 Re R10 R11 R12 R13 R14 R15 Ro R1 R2 R4 R5 Re R7 Wo
403. to reload Mode 2 configures timer 1 as an 8 bit timer TL1 register with automatic reload from the register on overflow Figure 8 3 Overflow from TL1 sets overflow flag TF1 in the TCON reg ister and reloads TL1 with the contents of TH1 which is preset by software The reload leaves 1 unchanged See Auto load Setup Example on page 8 9 8 4 4 Mode 3 Halt Placing timer in mode 3 causes it to halt and hold its count This can be used to halt timer 1 when the run control bit is not available i e when timer 0 is in mode 3 See the final para graph of Timer 1 on page 8 6 8 5 0 1 APPLICATIONS Timer 0 and timer 1 are general purpose timers that can be used in a variety of ways The timer applications presented in this section are intended to demonstrate timer setup and do not repre sent the only arrangement nor necessarily the best arrangement for a given task These examples employ timer 0 but timer 1 can be set up in the same manner using the appropriate registers 8 5 1 Auto load Setup Example Timer 0 can be configured as an eight bit timer TLO with automatic reload as follows 1 Program the four low order bits of the TMOD register Figure 8 5 to specify mode 2 for timer 0 C TO 0 to select Fosc 12 as the timer input and GATEO 0 to select TRO as the timer run control 8 9 TIMER COUNTERS AND WATCHDOG TIMER intel 8 5 2 Enter an eight bit initial value ng in timer reg
404. ts 8 6 8 4 1 M de 0 13 bIt ner RE eR UR OA ERES 8 9 8 4 2 Mode 1 16 bit Timer uet ten e d eee ce ei 8 9 8 4 8 Mode 2 8 bit Timer with 8 9 8 4 4 Mode Hall aetna bine de aed 8 9 8 5 hne Ere mali edes 8 9 8 5 1 Auto load Setup Example nee tdi cmt idet ve n ee 8 9 8 5 2 Pulse Width Measurements eese 8 10 8 6 Bc MH 8 10 8 6 1 8 11 8 62 Auto reload Mode ice ee beu 8 12 8 6 2 1 Up Counter Operation 8 12 8 6 2 2 Up Down Counter Operation 22 2 10000 8 13 8 6 3 Baud Rate Generator Mode 8 14 8 6 4 gt Clock Out ModS eaten eed de ae 8 14 8 7 WATGHBOG TIMER eem ret RERUM RERUMS 8 16 8 7 1 D SCriPtlON 8 16 8 52 USING tNE WDT 4 eim e eR 8 18 8 7 83 During Idle 8 18 8 7 4 During 8 18 CHAPTER 9 PROGRAMMABLE COUNTER ARRAY 9 1 POAJDESGRIBTIGON z eH GIU ER DR Ah Ep es 9
405. ts RD1 0 B stepping UCONFIGO 3 2 Table B 4 A stepping CONFIGO 3 2 Table B 4 Also see RD P3 6 XTAL1 Input to the On chip Inverting Oscillator Amplifier To use the internal oscillator a crystal resonator circuit is connected to this pin If an external oscillator is used its output is connected to this pin XTAL1 is the clock source for internal timing XTAL2 Output of the On chip Inverting Oscillator Amplifier To use the internal oscillator a crystal resonator circuit is connected to this pin If an external oscillator is used leave XTAL2 unconnected The descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the nonpage mode chip configuration compatible with 44 lead PLCC and 40 lead DIP MCS 51 microcontrollers If the chip is configured for page mode operation port 0 carries the lower address bits A7 0 and port 2 carries the upper address bits A15 8 and the data D7 0 intel SIGNAL DESCRIPTIONS Table B 4 Memory Signal Selections RD1 0 B stepping RD1 0 P1 7 CEX A17 P3 7 RD A16 PSEN WR Features 00 17 A16 Asserted for Asserted for writes to 256 Kbyte external all addresses all memory locations memory 0 1 P1 7 CEX4 A16 Asserted for Asserted for writes to 128 Kbyte external all addresses all memory locations memory 10 P1 7 CEX4 P3 7 only Asserted for Asserted for writes to 64 Kbyte external all addresses all me
406. ts bit TF2 which you can use to request an interrupt Setting the external enable bit EXEN allows the RCAP2H and RCAP2L registers to capture the current value in timer registers TH2 and TL2 in response to 1 0 0 transition at external input T2EX The transition at 2 also sets bit EXF2 in T2CON The EXF2 bit like TF2 can generate an interrupt TH2 8 Bits TL2 8 Bits Interrupt Request RCAP2H RCAP2L EXEN2 A4113 02 Figure 8 7 Timer 2 Capture Mode 8 11 TIMER COUNTERS AND WATCHDOG TIMER intel 8 6 2 Auto reload Mode The auto reload mode configures timer 2 as a 16 bit timer or event counter with automatic reload The timer operates an as an up counter or as an up down counter as determined by the down counter enable bit DCEN At device reset DCEN is cleared so in the auto reload mode timer 2 defaults to operation as an up counter 8 6 2 1 Up Counter Operation When DCEN 0 timer 2 operates as an up counter Figure 8 8 The external enable bit EXEN2 in the T2CON register provides two options Figure 8 12 If EXEN2 0 timer 2 counts up to FFFFH and sets the TF2 overflow flag The overflow condition loads the 16 bit value in the re load capture registers RCAP2H RCAP2L into the timer registers TH2 TL2 The values in RCAP2H and RCAP2L are preset by software If EXEN2 1 the timer registers are reloaded by either a timer overflow or a high to low tran sition at e
407. uctions a 64 Kbyte extended stack space aminimum instruction execution time of two clocks vs 12 clocks for MCS 51 microcon trollers binary code compatibility with MCS 51 microcontrollers Several benefits are derived from these features preservation of code written for MCS 51 microcontrollers asignificant increase in core execution speed in comparison with MCS 51 microcontrollers at the same clock rate support for larger programs and more data increased efficiency for code written in C 2 1 ARCHITECTURAL OVERVIEW System Bus and I O Ports P0 7 0 P2 7 0 1 1 OTPROM ROM 8 Kbytes Drivers ot Memory Data 16 ume Memory Address 16 Port 0 Drivers 16 Kbytes Interface 1 Data Bus 8 Data Address 24 Ports and Peripheral Signals P1 7 0 P3 7 0 1024 Bytes Watchdog Timer Peripheral Interface Timer ga Counters Interrupt Handler Serial Peripherals MCS 251 Microcontroller Core Clock amp Reset 8XC251SA SB SP SQ Microcontroller A4214 01 Figure 2 1 Functional Block Diagram of the 8XC251SA SB SP SQ 2 2 ARCHITECTURAL OVERVIEW intel 2 1 8XC251SA SB SP SQ ARCHITECTURE Figure 2 1 is a functional block diagram of the 8XC251SA SB SP SQ The core which is com mon to all MCS 251 microcontrollers is described in MCS 251 Microcontroller Core on page 2 4 Each
408. ulator A bit conditional jump is based on the state of a bit In a compare conditional jump the jump is based on a comparison of two operands All condi tional jumps are relative and the target address rel must be in the current 256 byte block of code The instruction set includes three kinds of bit conditional jumps JB Jump on Bit Jump if the bit is set JNB Jump on Not Bit Jump if the bit is clear JBC Jump on Bit then Clear it Jump if the bit is set then clear it Bit Addressing on page 5 11 describes the bit addressing used in these instructions Compare conditional jumps test a condition resulting from a compare CMP instruction that is assumed to precede the jump instruction The jump instruction examines the PSW and PSW1 reg isters and interprets their flags as though they were set or cleared by a compare CMP instruction Actually the state of each flag is determined by the last instruction that could have affected that flag The condition flags are used to test one of the following six relations between the operands equal not equal greater than gt less than greater than or equal 2 less than or equal X For each relation there are two instructions one for signed operands and one for unsigned oper ands Table 5 9 Table 5 9 Compare conditional Jump Instructions Operand Relation Typs gt lt gt lt Unsigned JG JL JGE JLE
409. urce Mode Not Taken Taken Not Taken Taken 2 2 2 2 2 5 2 5 0110 0000 rel addr Binary Mode Encoding Source Mode Encoding JZ PC PC 2 IF A 0 THEN PC lt PC rel Long call Calls a subroutine located at the specified address The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16 bit result onto the stack low byte first The stack pointer is incremented by two The high and low bytes of the PC are then loaded respectively with the second and third bytes of the LCALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the 64 Kbyte region of memory where the next instruction is located intel INSTRUCTION SET REFERENCE Flags CY AC OV N Z Example The stack pointer contains 07H and the label SUBRTN is assigned to program memory location 1234H After executing the instruction LCALL SUBRTN at location 0123H the stack pointer contains 09H on chip RAM locations 08H and 09H contain 01H and 26H and the PC contains 1234H LCALL addr16 Binary Mode Source Mode Bytes 3 3 States 9 9 Encoding 0001 0010 addr15 addr8 addr7 addrO Hex Code in Binary Mode Encoding Source Mode Encoding Operation LCALL PC PC 3 SP lt SP 1 SP 7 0 SP lt SP 1 SP lt 15 8
410. us of the port pins depends upon the location of the program memory Internal program memory the ALE and PSEN pins are pulled high and the ports 0 1 2 and 3 pins are reading data Table 12 1 External program memory the ALE and PSEN pins are pulled high the port 0 pins are floating and the pins of ports 1 2 and 3 are reading data Table 12 1 NOTE If desired the PCA may be instructed to pause during idle mode by setting the CIDL bit in the CMOD register Figure 9 7 on page 9 13 12 31 Entering Idle Mode To enter idle mode set the PCON register IDL bit The 8XC251Sx enters idle mode upon execu tion of the instruction that sets the IDL bit The instruction that sets the IDL bit is the last instruc tion executed CAUTION If the IDL bit and the PD bit are set simultaneously the 8XC251Sx enters powerdown mode 12 4 intel SPECIAL OPERATING MODES 12 3 2 Exiting Idle Mode There are two ways to exit idle mode Generate an enabled interrupt Hardware clears the PCON register IDL bit which restores the clocks to the CPU Execution resumes with the interrupt service routine Upon completion of the interrupt service routine program execution resumes with the instruction immediately following the instruction that activated idle mode The general purpose flags GF1 and GFO in the PCON register may be used to indicate whether an interrupt occurred during normal operation or during idle mode When idle mode is exi
411. ve transitions on the Tx ex ternal input pin The external input is sampled during every S5P2 state Clock and Reset Unit on page 2 6 describes the notation for the states in a peripheral cycle When the sample is high in one cycle and low in the next the counter is incremented The new count value appears in the register during the next S3PI state after the transition was detected Since it takes 12 states 24 oscillator periods to recognize a negative transition the maximum count rate is 1 24 of the os cillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full peripheral cycle Table 8 2 External Signals Signal Name Type Description Multiplexed T2 Timer 2 Clock Input Output This signal is the external clock input P1 0 for the timer 2 capture mode and it is the timer 2 clock output for the clock out mode T2EX Timer 2 External Input In timer 2 capture mode a falling edge P1 1 initiates a capture of the timer 2 registers In auto reload mode a falling edge causes the timer 2 registers to be reloaded In the up down counter mode this signal determines the count direction high up low down INT 1 0 External Interrupts 1 0 These inputs set the IE1 0 interrupt flags P3 3 2 the TCON register TCON bits IT1 0 select the triggering method IT
412. w the bus cycles for data reads and data writes in page mode These cycles are identical to those for nonpage mode except for the different signals on ports 0 and 2 t Apagerollover occurs when the address increments from the top of one 256 byte page to the bottom of the next e g from FF FAFFH to FF FBOOH 13 6 EXTERNAL MEMORY INTERFACE XTAL ALE PSEN A17 A16 PO P2 Cycle 1 Page Miss Cycle 2 Page Hit gt State 1 A15 8 State 2 gt lt A17 A16 A7 0 A17 A16 A7 0 D7 0 State 1 t During a sequence of page hits PSEN remains low until the end of the last page hit cycle A2809 04 Figure 13 5 External Bus Cycle Code Fetch Page Mode XTAL ALE RD PSEN A17 A16 PO P2 State 1 A15 8 State 2 State 3 17 16 7 0 D7 0 A2811 04 Figure 13 6 External Bus Cycle Data Read Page Mode 13 7 EXTERNAL MEMORY INTERFACE XTAL ALE WR A17 A16 PO P2 State 1 A15 8 State 2 State 3 l t 17 16 7 0 7 0 2810 03 Figure 13 7 External Bus Cycle Data Write Page Mode 13 3 EXTERNAL BUS CYCLES WITH WAIT STATES 8 2515 can be configured to add wait states to the external bus cycles by extending the RD WR PSEN pulses or by extending the ALE pulse For B stepping devices configuration bites WSA1 0 and WSB1 0 specify 0 1 2 or
413. wer pin that reduces power supply noise and are secondary ground pins that reduce ground bounce and improve power supply bypassing The secondary power and ground pins are not substitutes for Vcc and V They are not required for proper de vice operation thus the 8XC251Sx is compatible with designs that do not provide connections to these pins 11 2 2 Unused Pins To provide stable predictable performance connect unused input pins to Vs or Vec Untermi nated input pins can float to a mid voltage level and draw excessive current Unterminated inter rupt inputs may generate spurious interrupts 11 2 3 Noise Considerations The fast rise and fall times of high speed CHMOS logic may produce noise spikes on the power supply lines and signal outputs To minimize noise and waveform distortion follow good board layout techniques Use sufficient decoupling capacitors and transient absorbers to keep noise within acceptable limits Connect 0 01 uF bypass capacitors between V c and each V pin Place the capacitors close to the device to minimize path lengths Multilayer printed circuit boards with separate and ground planes help minimize noise For additional information on noise reduction see Application Note AP 125 Designing Microcon troller Systems for Noisy Environments 11 2 intel MINIMUM HARDWARE SETUP 11 3 CLOCK SOURCES The 8 2515 can obtain the system clock signal from an external clock sou
414. x Table B 1 lists the signals grouped by function Table B 2 defines the columns used in Table B 3 which describes the signals Table B 4 and Table B 4 list the memory signal selections for configuration bits RD1 0 referred to in Table B 3 Table B 1 Signals Arranged by Functional Categories Address amp Data Input Output Processor Control ADO PO 0 P1 0 T2 P3 2 INTO AD1 P0 1 P1 1 T2EX P3 3 INT1 AD2 P0 2 P1 2 ECI EA Vpp AD3 P0 3 P1 3 CEXO RST AD4 P0 4 P1 4 CEX1 XTAL1 AD5 P0 5 P1 5 CEX2 XTAL2 AD6 P0 6 P1 6 CEX3 AD7 P0 7 P1 7 CEX4 A17 Power amp Ground A8 P2 0 P3 0 RXD Voc A9 P2 1 P3 1 TXD Vcco A10 P2 2 P3 4 TO Vss A11 P2 3 P3 5 T1 Vss1 A12 P2 4 Vaso A13 P2 5 Bus Control amp Status EA V pp A14 P2 6 P3 6 WR A15 P2 7 P3 7 RD A16 P3 7 RD A16 ALE PROG P1 7 CEX4 A17 PSEN SIGNAL DESCRIPTIONS intel Table B 2 Description of Columns of Table B 3 Column Heading Description Signal Name Lists the signals arranged alphabetically Many pins have two functions so there are more entries in this column than there are pins Every signal is listed in this column for each signal the alternate function that shares the pin is listed in the Multiplexed With column Type Identifies the pin function listed in the Signal Name column as an input 1 output O bidirectional
415. xternal input T2EX This transition also sets the EXF2 bit in the T2CON register Either TF2 or EXF2 bit can generate a timer 2 interrupt request XTAL1 Overflow Interrupt Request EXEN2 A4115 02 Figure 8 8 Timer 2 Auto Reload Mode DCEN 0 8 12 intel TIMER COUNTERS AND WATCHDOG TIMER 8 6 2 2 Up Down Counter Operation When DCEN 1 timer 2 operates as an up down counter Figure 8 9 External pin T2EX con trols the direction of the count Table 8 2 on page 8 3 When T2EX is high timer 2 counts up The timer overflow occurs at FFFFH which sets the timer 2 overflow flag TF2 and generates an interrupt request The overflow also causes the 16 bit value in RCAP2H and RCAP2L to be load ed into the timer registers TH2 and TL2 When T2EX is low timer 2 counts down Timer underflow occurs when the count in the timer registers TH2 TL2 equals the value stored in RCAP2H and RCAP2L The underflow sets the TF2 bit and reloads FFFFH into the timer registers The EXF2 bit toggles when timer 2 overflows or underflows changing the direction of the count When timer 2 operates as an up down counter EXF2 does not generate an interrupt This bit can be used to provide 17 bit resolution Down Counting Reload Value Interrupt Request TH2 TL2 8 Bits 1 8 Bits T2 Count Direction 1 Up 0 Down RCAP2H RCAP2L 2 Up Counting Reload Value A4114
416. y Mode Source Mode 1 2 1 2 0110 irrr Binary Mode Encoding Source Mode A5 Encoding XRL A lt A Y Rn Binary Mode Source Mode 3 2 2 1 0110 1100 5555 5555 intel Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rmd Rmd v Rms INSTRUCTION SET REFERENCE XRL WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0110 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL WRds lt WRjd v WRjs XRL Rm data Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0110 1110 ssss 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rm Rm v data XRL WRj data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0110 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL WRj lt v data16 A 141 INSTRUCTION SET REFERENCE XRL Rm dir8 Binary Mode Source Mode Bytes 4 3 States 3t 2t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0110 1110 5556 0001 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Enc
417. y of additional external interrupt A4120 01 Figure 10 5 Timer 2 in Baud Rate Generator Mode 10 13 SERIAL I O PORT Note that timer 2 increments every state time 2 when it is in the baud rate generator mode In the baud rate formula that follows RCAP2H RCAP2L denotes the contents of RCAP2H and RCAP2L taken as a 16 bit unsigned integer Serial I O Modes 1 and Baud Rates When timer 2 is configured as a timer and is in baud rate generator mode do not read or write the TH2 or TL2 registers The timer is being incremented every state time and the results of a read or write may not be accurate In addition you may read but not write to the RCAP2 registers a write may NOTE Fosc overlap a reload and cause write and or reload errors Table 10 6 lists commonly used baud rates and shows how they are generated by timer 2 32 x 65536 RCAP2H RCAP2L Table 10 6 Timer 2 Generated Baud Rates 10 14 Oscillator Baud Rate Frequency RCAP2H RCAP2L Fosc 375 0 Kbaud 12 MHz FFH FFH 9 6 Kbaud 12 MHz FFH D9H 4 8 Kbaud 12 MHz FFH B2H 2 4 Kbaud 12 MHz FFH 64H 1 2 Kbaud 12 MHz FEH C8H 300 0 baud 12 MHz FBH 1EH 110 0 baud 12 MHz F2H AFH 300 0 baud 6 MHz FDH 8FH 110 0 baud 6 MHz F9H 57H intel 1 Minimum Hardware Setup intel CHAPTER 11 MINIMUM HARDWARE SETUP This chapter discusses the basic operating requirements of the MCS9 251 microcontroller and
418. y zero CY AC OV N 2 0 1 Binary Mode Encoding Source Mode Encoding The accumulator contains 251 OFBH or 11111011B and register B contains 18 12H or 00010010B After executing the instruction DIV AB the accumulator contains 13 ODH or 00001101B register B contains 17 11H or 00010001B since 251 13 X 18 17 and the CY and OV flags are clear Binary Mode Source Mode 1 1 10 10 1000 0100 Binary Mode Encoding Source Mode Encoding DIV A lt quotient A B B remainder A B A 59 INSTRUCTION SET REFERENCE intel DJNZ lt byte gt lt rel addr gt Function Description Flags Example Variations DJNZ dir8 rel Bytes States Encoding A 60 Decrement and jump if not zero Decrements the specified location by 1 and branches to the address specified by the second operand if the resulting value is not zero An original value of 00H underflows to OFFH The branch destination is computed by adding the signed relative displacement value in the last instruction byte to the PC after incrementing the PC to the first byte of the following instruction The location decremented may be a register or directly addressed byte Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins CY AC OV N Z The o
419. yte region in external memory top of Figure 4 8 on page 4 14 This selection provides the smallest external memory space however pin P3 7 RD A 16 is available for general I O and pin P1 7 CEX4 A17 is available for general I O or PCA I O This selection is useful when the avail ability of these pins is required and or a small amount of external memory is sufficient For the A stepping of the 8XC251SB this selection provides a 64 Kbyte external memory space The only difference from the B stepping is the absence of internal regions 02 03 FC and FD Regions 00 01 FE and FF map into a single region in external memory 4 6 2 4 RD1 0 11 Compatible with MCS 51 Microcontrollers The selection RD1 0 11 provides only 16 external address bits A15 0 on ports PO and P2 However PSEN is the read signal for regions FC FF while RD is the read signal for regions 00 03 bottom of Figure 4 8 on page 4 14 The two read signals effectively expand the external memory space to two 64 Kbyte regions WR is asserted only for writes to regions 00 03 This selection provides compatibility with MCS 51 microcontrollers which have separate external memory spaces for code and data For the A stepping of the 8X C251SB this selection provides compatibility with MCS 51 micro controllers The only difference from the B stepping is the absence of internal regions 02 03 FC and FD Regions 00 and 01 map into one external 64 Kbyte region w

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