IP-UD-D
Contents
1. 10 9 Bit map of bytes at base A DataBit 7 6 5 4 3 2 1 90 Output En Bit map of byte at base C Data Biba FA DEE i 2 J J 1 J 0 k Write Master Select Mode Enable Clock Polarity Dbl Buffer En Read 0 Master Select Mode Enable Clock Polarity Dbl Buffer En 10 UO Pin Wiring This section gives the pin assignments and wiring recommendations for IP UD D The pin numbers given in Figure 7 below correspond to numbers on the 50 pin IndustryPack I O connector to the wires on a 50 pin flat cable plugged into a standard IP carrier board and to the screw terminal numbers on the IP Terminal block VO 1 1 I O 1 2 I O 2 3 I O 2 4 VO 3 5 I O 3 6 I O 4 7 I O 4 8 VO 5 9 I O 5 10 I O 6 11 I O 6 12 VO 7 13 I O 7 14 I O 8 15 I O 8 16 I O 9 17 I O 9 18 I O 10 19 I O 10 20 I O 11 21 I O 11 22 I O 12 23 I O 12 24 I O 13 25 I O 13 26 I O 14 27 I O 14 28 I O 15 29 I O 15 30 UO 16 31 I O 16 32 I O 17 33 I O 17 34 UO 18 35 I O 18 36 UO 19 37 I O 19 38 I O 20 39 I O 20 40 I O 21 41 I O 21 42 I O 22 43 I O 22 44 1 0 23 Master Clk Out 45 I O 23 Master Clk Out 46 1 0 24 Slave Clk In 47 I O 24 Slave Clk In 48 Double Buffer Clk 49 GND 50 Figure 7 W O Pin Assignment 11 IndustryPack Logic Interface Pin Assignment Figure 8 below gives the pin assignments for the IndustryPack Logic Interface on the IP UD D Pins mar2. SBS Technologies IP UD D 24 Line Differential Input Output IndustryPack User Manual 1999 2005 SBS Technologies Inc Subject to change without notice Part 89002074 Rev 1 0 20050125 IP UD D 24 Line Differential Input Output IndustryPack SBS Technologies Inc 1284 Corporate Center Drive St Paul MN 55121 1245 Tel 651 905 4700 FAX 651 905 4701 Email support commercial sbs com http www sbs com 1999 2005 SBS Technologies Inc IndustryPack and PCeMIP are a registered trademarks of SBS Technologies Inc QuickPack SDpacK and Unilin are trademarks SBS Technologies Inc SBS Technologies Inc acknowledges the trademarks of other organizations for their respective products mentioned in this document All rights are reserved No one is permitted to reproduce or duplicate in any form the whole or part of this document without the express consent of SBS Technologies This document is meant solely for the purpose in which it was delivered SBS Technologies reserves the right to make any changes in the devices or device specifications contained herein at any time and without notice Customers are advised to verify all information contained in this document The electronic equipment described herein generates uses and may radiate radio frequency energy which can cause radio interference SBS Technologies assumes no liability for any damages caused by such interference SBS Technologie
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4. 8 7 6 5 4 3 2 1 DataBit amp 15 14 33 12 11 10 9 8 7 6 5 4 83 2 1 one 24 23 22 24 20 19 18 17 Note data in bits 15 through 8 are ignored in writes read as O s Bit map of long words at base 8 Output En 16 15 14 13 12 11 100 9 8 7 6 5 4 3 2 1 Data Bit 15 14 13 122 11 10 9 8 7 6 5 4 3 2 1 90 OuputtE 24 23 22 21 20 19 18 17 Note data in bits 15 through 8 are ignored in writes read as O s Bit map of long word at base C Data Bit 31 20 15 0 Write _ Master Select Mode Enable Clock Polarity Dbl BufferEn Read 0 Master Select Mode Enable Clock Polarity Dbl Buffer En 0 Note data in bits 31 through 20 and 15 through 0 are ignored in writes read as O s NuBus Addressing NuBus addressing requires computing the address from the byte addresses given above under VMEbus Addressing The formula is NuBus byte address VMEbus byte address 2 1 All byte data is still transferred on data lines D7 DO Word addresses on the NuBus are the same as for VME Word data is transferred on data lines D15 DO ISA IBM PC AT Addressing IP UD D normally is accessed one word at a time in the host s I O space Alternatively byte accesses may be used The actual application will depend on the carrier board See
5. base B read write Output Enable Lines 17 24 base D read write Control register Figure 3 Byte Access VME Address Map Bit map of bytes at base 0 and base 4 DataBit 7 6 5 4 3 2 1 0 VO Line 16 15 14 13 12 11 10 9 Bit map of bytes at base 1 and base 5 DataBit 7 6 5 4 3 2 1 0 VO Line 8 71615 4131211 Bit map of bytes at base 3 and base 7 DataBit 7 6 5 4 3 2 1 0 VO Line Bit map of bytes at base 8 DataBit 7 6 5 4 3 2 11 0 Output En 16 15 14 13 12 11 10 9 Bit map of bytes at base 9 DataBit 7 6 5 4 3 2 11 0 OutputEn 8 7 16 5 4 3 2 1 Bit map of bytes at base A DataBit 7 6 5 4 3 2 11 0 Output En Bit map of byte at base D DataBt FA 3 2 J 1 J 0 k Write Master Select Mode Enable Clock Polarity Dbl Buffer En Bea 0 Master Select Mode Enable Clock Polarity Dbl Buffer En Alternate Long Word Access I O Space base 0 long write Output Lines 1 24 base 0 long read Read Back Lines 1 24 base 4 long read Direct Read Lines 1 24 base 8 long read write Output Enable Lines 1 24 base C long read write Control register Figure 4 Long Word Access VME Address Map Bit map of long words at base 0 and base 4 VO Line 16115 14 13 12 11 10 9
6. n nee Pe PE Mu ERR 11 Logic Interface Pin Aesignment eme 12 Control Register Bit Definitions 14 ID PROM Data bes 15 WO Line Block Diagram seem emm mmm 17 Master and Slave Block Diagram sseseee een 19 Master and Slave Configuration 20 Product Description The IP UD D is part of the IndustryPack family of modular UO components It provides 24 lines of digital I O each with EIA 422 and EIA 485 formerly RS422 and RS485 compatible differential drivers and receivers Each line may be dynamically and individually configured for either input or output Outputs may be double buffered making it possible to synchronize multiple IPs Both internal read back and direct read registers are provided for ease of software development 16 bit word and 8 bit byte operations are supported The IP UD D conforms to the IndustryPack Interface Specification This guarantees compatibility with multiple Support Modules Because the IPs may be mounted on different form factors while maintaining plug and software compatibility system prototyping may be done on one Support Module with final system implementation on a different one The differential receiver for each line is always enabled allowing the state of each I O line to be determined at any time The output enable for each differential transmitter is controlled by a bit in the Output Enable Register Writing a zero to any bit in this register enables the cor
7. rate faster than 60 ns must be used for the Double Buffer Clock Writing a 0 disables double buffering This is the default Bit 1 D1 Double Buffer Clock Polarity Select This bit controls the Double Buffer Clock polarity Writing a 1 will cause output data to be latched out of the IP and input data to be latched into the IP on the falling edge of the Double Buffer Clock Writing a 0 will cause data to be latched on the rising edge of the Double Buffer Clock This is the default Bit 2 D2 Master Slave Mode Enable This bit determines which pin on the UO connector is the source for the Double Buffer Clock Writing a 1 puts the IP in Master Slave mode and makes pins 47 and 48 I O 24 the source for the Double Buffer Clock In this mode O24 En in the Output Control Register must be set to 1 to make I O line 24 an input This I O line must be set up prior to putting the IP in Master Mode Writing a 0 to the Master Slave Mode Enable bit puts the IP in normal mode and makes pin 49 Double Buffer Clock the source for the Double Buffer Clock In this mode all 24 I O lines are available for use This is the default mode Bit 3 D3 Master Select This bit determines whether the IP is a master or slave Writing a 1 makes the IP a master When it is a master the IP re drives the Double Buffer Clock pin 49 out I O line 23 pins 45 and 46 This clock should then be wired externally to I O line 24 pins 47 and 48 on this IP and a
8. 13 12 11 10 9 8 7 615 4 3 2 1 0 VO Line 16115 14 13 12 11 10 9 8 7 615 4 3 2 1 Bit map of words at base 2 and base 6 DataBit amp 15 14 33 12 11 10 9 8 7 6 5 4 3 2 11 0 ONE ECH EC oe eee ee Note data in bits 15 through 8 are ignored in writes read as O s Bit map of words at base 8 Data Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 90 Output En 16 15 14 13 122 11 10 9 8 7 6 5 4 3 2 1 Bit map of words at base A Data Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 90 OuputE 24 23 22 21 20 19 18 17 Note data in bits 15 through 8 are ignored in writes read as O s Bit map of word at base C Data Bit 154 3 L2 1 Wa e 0 Write Master Select Mode Enable Clock Polarity Dbl Buffer En Read 0 Master Select Mode Enable Clock Polarity Dbl Buffer En Alternate Byte Access I O Space base 0 write Output lines 9 16 base 1 write Output lines 1 8 base 3 write Output lines 17 24 base 0 read Read back lines 9 16 base 1 read Read back lines 1 8 base 3 read Read back lines 17 24 base 4 read Direct read lines 9 16 base 5 read Direct read lines 1 8 base 7 read Direct read lines 17 24 base 8 read write Output Enable Lines 9 16 base 9 read write Output Enable Lines 1 8
9. Slave Block Diagram 19 Master IP VYO1 Control Register OB h IO 1 Output Control Register OEn24 OEn 23 0 I O 22 I O 22 Master Clk Out Master Clk Out Slave Clk In Slave Clk In External Clk Slave IP VYO1 Control Register 05 h I O1 Output Control Register OEn24 I O 23 T O 23 Slave Clk In Slave Clk In External CIk Figure 13 20 Pin 1 Pin 2 Pin 43 Pin 44 Pin 45 SL Pin Bin48 Pin 1 P2 f i Pin Pind6 ER Pin Pind8 To other Slave IPs Master and Slave Configuration Construction and Reliability IndustryPacks were conceived and engineered for rugged industrial environments The IP UD D is constructed out of 0 062 inch thick FR4 VO material The six copper layers consist of two signal layers on the top and bottom and four internal layers Two internal layers are dedicated to power and ground planes and two are used for signal wiring Through hole and surface mounting of components are used IC sockets use gold plated screw machine pins High insertion and removal forces are required which assists in keeping components in place If the application requires unusually high reliability or is in an environment subject to high vibration the user may solder the four corner pins of each socketed IC into the socket using a grounded soldering iron The IndustryPack connectors are keyed shrouded and have gold p
10. a block diagram Output Enable Register Internal Double Buffer T O Line Latch I O Line Read Back Data Bus Double Buffer Clk Clk Pol Sel Double Buffer Enable Figure 11 I O Line Block Diagram 17 Master Slave Mode Master Slave Mode is provided for multiple IP systems using a single external clock to synchronize inputs and outputs If this clock does not have sufficient drive capability for driving all the IPs in the system it may be wired to the Master IP to be re driven to all the Slave IPs Figure 12 shows a block diagram of two IPs in Master Slave Mode while Figure 13 shows a diagram of how to wire a Master and Slave IP An IP is configured to be a Master by setting both the Master Slave Mode Bit and the Master Select Bit bit 2 and bit 3 to a 1 in the Control Register The desired clock polarity is set by the Clock Polarity Select Bit bit 1 Writing a O to this bit will latch data on the rising edge writing a 1 will latch data on the falling edge I O Line 24 is set to be an output by writing a 0 to OEn 24 in the Output Control Register while I O Line 23 is set to be an input by writing a 1 to OEn 23 The Output Enables for the I O lines must be set up before the Master Slave Mode is enabled The external clock is wired to the Double Buffer CIk pin 49 The Master CIk Out pins 45 and 46 are then wired to the Slave Clk In pins 47 and 48 on all the IPs including the Master IP Slave IPs
11. amages due to improper packaging of returned items For service of SBS Technologies products not purchased directly from SBS Technologies contact your reseller Products returned to SBS Technologies for repair by other than the original customer will be treated as out of warranty For service contact SBS Technologies Inc 1284 Corporate Center Drive St Paul MN 55121 1245 Tel 651 905 4700 FAX 651 905 4701 Email support commercial sbs com 22 Specifications Size Digital Interface Interface Level Software Interface Initialization Access Mode Wait States Transfer Rate Onboard Options Dimensions Construction Temperature Coefficient Power Requirements Single High Industry Pack 24 digital signal lines with double buffered inputs and outputs Each line is either an input or an output EIA 485 EIA 422 Differential Interface Common Mode Voltage Range 12V 7V The 24 I O lines are read or written with either word or byte accesses There is an 8 bit Control Register 300 Millisecond delay from reset Forces all lines to be inputs Disables double buffering Byte or word in I O Space Zero 8 Mbytes second maximum continuous All options are software programmable Standard Single High IndustryPack width and length 1 8 x 3 9 inches Conformal Coated FR4 4 layer Printed Circuit Surface mounted components 0 89 W C for uniform heat across IP 5 0 VDC 60 mA typical
12. are configured by setting the Master Slave Mode Bit bit 2 to a 1 and the Master Select Bit bit 3 to a 0 in the Control Register The desired clock polarity is set by the Clock Polarity Select Bit bit 1 I O Line 24 is set to be an input by writing a 1 to OEn24 in the Output Control Register The Master CIk Out signal from the Master IP is wired to the Slave CIk In pins 47 and 48 The termination resistors should be removed for the Master CIk Out signal and all Slave CIk In signals except for the receiver farthest from the Master This is shown in Figure 12 A termination resistor is removed by cutting one of the leads on the resistor network Before removing a resistor network note which direction pin 1 is facing pin 1 has a small dot marked on the resistor network body above the pin To remove a termination resistor remove the resistor network and cut off the lead on the pin corresponding to the I O line then replace the resistor network The Master IP should have pins 2 and 4 of RN3 cut while all Slave IPs except the one farthest from the Master should have pin 1 of RN3 cut 18 Master IP VO 1 T O 1 e Double Buffer 9355 LL 22 Master CIk Out bom Master CIk Out T Slave Clk In pun External Clk In ul q To other Slave IPs Slave IP VO 1 T O 1 Double 7 Buffer M T O 23 PE LO 23 Termination Resistors removed EL Slave Clk In Only on last Slave IP Figure 12 Master and
13. ead back register at the same address used for writing to the signal line I O bits This permits set bit and clear bit instructions to be used in programming which are implemented by the host hardware as read modify write cycles Thus single bits at well as bit fields may be accessed The IP may also be accessed using byte or long word accesses If long word accesses are used from a 68020 68030 or 68040 host the I O space must be mapped into D16 68000 and 68010 hosts internally map all long word accesses into 16 bits so no special precaution is necessary The IP uses a Control Register to enable double buffering and control the polarity of the Double Buffer Clock It also is used to enable Master Slave Mode and define the Master IP in a multiple IP system using an external clock source to synchronize inputs and outputs 13 0 Double Buffer Enable Read Write 1 Double Buffer Clock Polarity Read Write Select Mode Enable Read Write 3 Master Select Read Write 3 4 7 Reserved Read as 0 4 Figure 9 Control Register Bit Definitions Control Register Bit Definitions Bit 0 DO LSB Double Buffer Enable This bit enables double buffering If this bit is set to a 1 the user must provide either a single ended TTL level clock on the Double Buffer Clock pin 49 or a differential clock on the Slave Clock pins 45 and 46 depending on how bit 3 is set This clock may be up to 1 MHz Aclock source with an edge
14. he Xilinx FPGA device The location of the ID PROM in the host s address space is dependent on the carrier board used For most VMEbus carriers the ID PROM space is directly above the IP s I O space or at IP base 80 Macintosh drivers use the ID PROM automatically RM1260 address may be derived from Figure 10 below by multiplying the addresses given by two then subtracting one RM1270 addresses may be derived by multiplying the addresses given by two then adding one available for user CRC for bytes used Model No IP UD D Manufacturer ID SBS GreenSpring Figure 10 ID PROM Data hex 15 Theory of Operation IndustryPack Standards The IP UD D is part of the IndustryPack family of modular I O products It meets the IndustryPack Logic Specification Contact SBS Technologies for a copy of this Specification It is assumed the reader is at least casually familiar with both this document and 68000 processor architecture Control Logic All control logic is contained within a single Xilinx FPGA It is clocked by the 8 MHz IP Logic clock from the Support Module The IP responds to I O and ID selects It does not respond to memory selects however the MEMSel line is routed to the FPGA enabling easy modification for special needs The IP does not require wait states for either read or write cycles Thus the FPGA generates Ack on the clock cycle following either I O or ID Select Hold cycles from the Support Module a
15. is latch is clocked on the falling edge of the IP Clock Figure 11 shows a block diagram Outputs from the Double Buffer Latch drive the differential transmitters Data is latched into the internal latch on the rising edge of the IP Clock after the IOSel line is driven low Double buffering is enabled by setting the Double Buffer Enable Bit bit 0 in the Control Register to a 1 A single ended TTL compatible signal must be provided on the External Clock pin 49 This signal must have an edge rate faster than 60 ns If double buffering is enabled the Double Buffer Clock Polarity Bit bit 1 in the Control Register is used to set the Double Buffer Clock polarity Setting the Double Buffer Clock Polarity Bit to a 0 will latch data on the rising edge and setting it to a 1 will latch data on the falling edge The power up default is 0 for both these bits 16 Data Input The data may be read from two sets of address locations The first set of locations base 0 and base 2 for word operations function as the Internal Read Back Register The data latched in the Internal Latch is read from these addresses They support processor bit operations implemented as read modify write cycles and are also useful for debugging purposes The second set of locations base 4 and base 6 for word operations is the Direct Read Register Data is latched into Input Register with the same clock which latches the Double Buffer Latch Figure 11 shows
16. ked n c below are defined by the specification but are not used on IP UD D Also see the User Manual for your IP Carrier board for more information GND CLK Reset DOIDSel Din c D2n c D3n c D4INTSel D5n c D61OSel 10 11 12 13 A2 39 n c 40 A3 41 n c 42 A4 43 n c 44 A5 20 45 n c 21 46 A6 22 47 Ack 23 48 n c GND 25 50 Note 1 The no connect n c signals above are defined by the IndustryPack Logic Interface Specification but not used by this IP See the Specification for more information Note 2 The layout of the pin numbers in this table corresponds to the physical placement of pins on the IP connector Thus this table may be used to easily locate the physical pin corresponding to a desired signal Pin 1 is marked with a square pad on the IndustryPack Figure8 Logic Interface Pin Assignment 12 Programming Programming the IP requires only the ability to read and write data in the host s I O space The base address is determined by the IP Support Module This document refers to this address as base After power on reset or VME system reset the IP requires a minimum delay of 300 milliseconds before any accesses are made by the host system This is to allow the Xilinx FPGA to configured itself Any accesses during this time will result in a bus error Reset sets all lines to be inputs and clears all bits in the Control Register Each of the 24 I O lines has a differential transceiver on it This ma
17. kes it possible to individually set each bit as input or output The receiver circuit in the transceiver is always enabled allowing the user to read the state of the I O line at any time The transmitter circuit in the transceiver must be enabled to make a bit an output The enable for each transmitter is controlled by a corresponding bit in the Output Control Register Writing a 0 to a bit in the Output Control Register will turn on that bit s output transmitter making it an output The value written to the Output Register will then appear on the I O line Writing a 1 to a bit in the Output Control Register will turn off the transmitter making the bit an input The Output Control Register defaults to all 1 s on reset disabling all the output transmitters Data may be read from two sets of address locations The first set of locations base 0x0 and base 0x2 for word operations function as the Internal Read Back Register The data latched in the Output Latch is read from these addresses They support processor bit operations implemented as read modify write cycles and are also useful for debugging purposes The second set of locations base 0x4 and base 0x6 for word operations is the Direct Read Register Data is latched into the Input Register on the rising edge of the 8 MHz IP Clock Figure 10 in the Theory of Operations section shows a block diagram Using word access up to 16 bits may be programmed at once The IP implements a r
18. lated pins on both plugs and receptacles They are rated at 1 Amp per pin 200 insertion cycles minimum These connectors make consistent correct insertion easy and reliable The IP is secured to the carrier with four M2 metric stainless steel screws The heads of the screws are countersunk into the IP The four screws provide significant protection against shock vibration and incomplete insertion For most applications they are not required The IndustryPack provides a low temperature coefficient of 0 89 W C for uniform heat This is based on the temperature coefficient of the base FR4 material of 0 31 W m C taking into account the thickness and area of the IP This coefficient means that if 0 89 Watts is applied uniformly on the component side then the temperature difference between the component and the solder side is one degree Celsius 21 Repair Service Policy Before returning a product for repair verify as soon as possible that the suspected unit is at fault then call the Customer Service Department for a RETURN MATERIAL AUTHORIZATION RMA number Carefully package the unit in the original shipping carton if it is available and ship prepaid and insured with the RMA number clearly written on the outside of the package Include the return address and telephone number of a technical contact For out of warranty repairs a purchase order for repair charges must accompany the return SBS Technologies will not be responsible for d
19. lave IPs Wiring in this way prevents excessive loading of the external clock source while ensuring all I O latches are clocked with minimal skew Figure 1 shows a block diagram of the IP UD D Output Control Latch Transceiver Output Enable Register 1 Output Enable Register 24 ID PROM Output Differential Register 1 Driver Input Differential Register 1 Receiver e UP Bus Interface e Output Differential Register 24 Driver Input Differential Control Register 24 Receiver Register Double Buffer Clock Clock Control ircui Esd Circuit Single Ended Figure 1 IP UD D Block Diagram VMEbus Addressing IP UD D normally is accessed one word at a time in the host s I O space Alternatively byte or long word accesses may be used If long words are used the host or support module must map 32 bit long words into two 16 bit cycles This is common for 68020 and 68030 implementation of the I O space Standard Word Access I O Space base 0 write Output Lines 1 16 base 2 write Output Lines 17 24 base 0 read Read Back Lines 1 16 base 2 read Read Back Lines 17 24 base 4 read Direct Read Lines 1 16 base 6 read Direct Read Lines 17 24 base 8 read write Output Enable Lines 1 16 base A read write Output Enable Lines 17 24 base C read write Control Register Figure 2 Word Access VME Address Map Bit map of words at base 0 and base 4 DataBit amp 15 14
20. ll slave IPs This minimizes the clock skew between the master and all slaves When this bit is set O23 En in the Output Control Register must be set to 0 to make I O line 23 an output and O24 En must be set to a 1 to make I O line 24 an input These I O lines must be set up prior to putting the IP in Master Mode Writing a 0 to the Master Select bit makes the IP a slave with its clock source I O line 24 if Bit 2 is set to a 1 or normal operation with its Double Buffer Clock source from pin 49 Double Buffer Clock This is the default See Figure 12 in the Theory of Operation section later in this manual for a diagram of how to wire a master and slave IP Bit 7 4 D7 D4 Reserved These bits are reserved for future use and will be read as O 14 ID PROM Every IP contains an IP PROM whose size is at least 32 x 8 bits The ID PROM aids in software auto configuration and configuration management The user s software or a supplied driver may verify that the device it expects is actually installed at the location it expects and is nominally functional The ID PROM contains the manufacturing revision level of the IP If a driver requires a particular revision IP it may check for it directly Standard data in the ID PROM on the IP UD D is shown in Figure 10 below For more information on IP ID PROMs refer to the IndustryPack Logic Interface Specification available from SBS Technologies The ID PROM on the IP UD D is implemented in t
21. re supported for both read and write cycles by extending Ack as required If no hold cycles are requested by the Support Module the IP is capable of supporting the full 8 MByte per second data transfer rate of the IP Logic Interface Specification I O Data Lines All input and output latches are contained within the Xilinx FPGA Each I O line has a EIA 485 EIA 422 differential transceiver with an extended common mode range of 12V to 7V A socketed 8 pin SIP resistor network provides parallel termination to groups of four transceivers A 1000 value is the factory default value though the user may substitute other values to match the characteristic impedance of the I O cables The resistor network may be removed if no termination is desired or individual leads may be cut off if terminations are required only for specific I O lines Data Output Each differential transceiver s transmitter has an output enable that is controlled by a corresponding bit in the Output Enable Register When the bit in the Output Enable Register is set to a 0 the transmitter is enabled and the data written to the Output Register will appear on the I O line When the bit in the Output Enable Register is set to a 1 the transmitter outputs maintain a high impedance over the entire common mode range Each output has two latches associated with it If double buffering is enabled the Double Buffer Latch is clocked by the Double Buffer Clock Without double buffering th
22. responding output driver Writing a one to any bit disables the output driver allowing the I O line to be used as an input The power up default disables all the output drivers Input and output lines may be double buffered by setting a bit in the Control Register When this bit is set the user must provide an external clock of up to 1 MHz Unlike the other inputs this is a single ended TTL level input Another bit in the Control Register selects the polarity of this clock allowing inputs and outputs to be latched on either the rising or falling clock edge Any TTL compatible clock source may be used Two separate locations in UO space are provided for each signal line The first location is used to set the output state and also to read back the written value at the internal latch This read back function is valuable to support bit operations which are implemented by processors as read modify write cycles It is also useful in debugging making it possible to observe directly the last value written to the port The second location is the direct read port which is always used for reading input values This register may also be used to verify the correct logic signal is actually on the interface cable The IP can function in a Master Slave Mode for synchronizing multiple IPs In this mode the Master IP re drives the external clock source out I O line 23 This line becomes the Master Clock that should be wired to I O line 24 on the Master and all S
23. s products are not authorized for use as critical components in medical applications such as life support equipment without the express consent of the general manager of SBS Technologies Commercial Group This product has been designed to operate with IndustryPack PCeMIP or CompactPCI modules or carriers and compatible user provided equipment Connection of incompatible hardware is likely to cause serious damage SBS Technologies assumes no liability for any damages caused by such incompatibility Table of Contents eeler le Ire E 1 VMEb s AddreSsing D ete Eet eeh dti mental NEE eege 3 INUBUS Addressing ret em deett eet adn EE 7 ISA IBM PC AT Addressing ELE rr rl pee aetates 8 IO Pip WARMING sas Ie ORI IPRC Ute RI eebe E tests 11 IndustryPack Logic Interface Pin Assignment eene 12 Programming me PX 13 ID PROMESA 15 Theory of Operation didici teca eta dee oat dede eee e vedendo 16 Construction and Reliability sienne 21 RED aU oc ox RS PE ipee dicte ttes EEE NE 22 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 List of Figures IP UD D Block Diaoram nennen 2 Word Access VME Address Map sssssssssnnenssessrrrnrrnnsresrtrrrnnnseesrtnnnrnnseeertnnn 3 Byte Access VME Address Map 4 Long Word Access VME Address Map 5 Word Access ISA Address Map 8 Byte Access ISA Address Map 9 HCH Pin Assignmient
24. t base C DataBit 54 3 2 T 0 _ Write Master Select Mode Enable Clock Polarity Dbl Buffer En Read 0 Master Select Mode Enable Clock Polarity Dbl Buffer En Alternative Byte Access UO Space base 0 write Output Lines 1 through 8 base 1 write Output Lines 9 through 16 base 2 write Output Lines 17 through 24 base 0 read Read back Lines 1 through 8 base 1 read Read back Lines 9 through 16 base 2 read Read back Lines 17 through 24 base 4 read Direct Read Lines 1 through 8 base 5 read Direct Read Lines 9 through 16 base 6 read Direct Read Lines 17 through 24 base 8 read write Output Enable Lines 1 8 base 9 read write Output Enable Lines 9 16 base A read write Output Enable Lines 17 24 base C read Control Register Figure 6 Byte Access ISA Address Map Bit map of bytes at base 0 and base 4 DataBit 7 6 5 4 3 2 1 0 lOLne 817 615 4 3 2 1 Bit map of bytes at base 1 and base 5 Data Bit 7 6 5 4 3 2 j1 fo VO Line 16 15 14 13 12 11 10 9 Bit map of bytes at base 2 and base 6 DataBt 7 6 5 4 3 2 1 0 VO Line Bit map of bytes at base 8 DataBit 7 6 5 4 3 2 11 0 OutputEn 8 7 6 5 4 3 2 1 Bit map of bytes at base 9 DataBit 7 6 5 4 3 2 11 0 Output En 16 15 14 13 12 11
25. the carrier board manual for details Standard Word Access I O Space base 0 write Output Lines 1 16 base 2 write Output Lines 17 24 base 0 read Read Back Lines 1 16 base 2 read Read Back Lines 17 24 base 4 read Direct Read Lines 1 16 base 6 read Direct Read Lines 17 24 base 8 read write Output Enable Lines 1 16 base A read write Output Enable Lines 17 24 base C read write Control register Figure 5 Word Access ISA Address Map Bit map of words at base 0 and base 4 Data Bit 15 14 33 12 11 10 9 8 7 615 4 3 2 1 0 VO Line 16115 14 13 12 11 109 8 7 6 5 4 3 2 1 Bit map of words at base 2 and base 6 DataBit amp 15 14 13 12 11 100 9 8 7 6 5 4 3 2 11 0 VO Line 24 23 22 24 20 19 18 17 Note data in bits 15 through 8 are ignored in writes read as O s Bit map of word at base C Data Bt 54 3 2 1 J 0 Write Master Select Mode Enable Clock Polarity Dbl Buffer En Read 0 Master Select Mode Enable Clock Polarity Dbl Buffer En Bit map of words at base 8 10 Bit map of words at base A DataBit 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 O Output En p e ECH 124 123 122 21 20 49 18 17 Note data in bits 15 through 8 are ignored in writes read as O s Bit map of word a
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